Initial commit of top_sencha [autogen only]
Change-Id: I3918f97746002191055ef4d662d325c950bc00e1
diff --git a/hw/top_sencha/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_sencha/dv/autogen/rstmgr_tgl_excl.cfg
new file mode 100644
index 0000000..79e0d58
--- /dev/null
+++ b/hw/top_sencha/dv/autogen/rstmgr_tgl_excl.cfg
@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// rstmgr_tgl_excl.cfg generated by `topgen.py` tool
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+//=========================================================
+// This file contains resets that are not used at top level
+//=========================================================
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_usb_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_smc_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_ml_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_video_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_audio_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_smc_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_ml_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_video_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_audio_n[1]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_device_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host0_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host1_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host2_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_usb_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_usb_aon_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c0_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c1_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c2_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_smc_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_ml_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_cam_i2c_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_video_n[0]
+-node tb.dut*.u_rstmgr_aon.resets_o.rst_audio_n[0]
diff --git a/hw/top_sencha/dv/autogen/tb__alert_handler_connect.sv b/hw/top_sencha/dv/autogen/tb__alert_handler_connect.sv
new file mode 100644
index 0000000..12abce3
--- /dev/null
+++ b/hw/top_sencha/dv/autogen/tb__alert_handler_connect.sv
@@ -0,0 +1,81 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool
+
+assign alert_if[0].alert_tx = `CHIP_HIER.u_uart0.alert_tx_o[0];
+assign alert_if[1].alert_tx = `CHIP_HIER.u_uart1.alert_tx_o[0];
+assign alert_if[2].alert_tx = `CHIP_HIER.u_uart2.alert_tx_o[0];
+assign alert_if[3].alert_tx = `CHIP_HIER.u_uart3.alert_tx_o[0];
+assign alert_if[4].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0];
+assign alert_if[5].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_i2c1.alert_tx_o[0];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_i2c2.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_rv_timer.alert_tx_o[0];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[3];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[4];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_usbdev.alert_tx_o[0];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[1];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[1];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_sysrst_ctrl_aon.alert_tx_o[0];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_adc_ctrl_aon.alert_tx_o[0];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_pwm_aon.alert_tx_o[0];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[0];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[1];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[4];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[51].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[52].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
+assign alert_if[53].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[55].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
+assign alert_if[57].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[58].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
+assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[60].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[61].alert_tx = `CHIP_HIER.u_rv_core_ibex_sec.alert_tx_o[0];
+assign alert_if[62].alert_tx = `CHIP_HIER.u_rv_core_ibex_sec.alert_tx_o[1];
+assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex_sec.alert_tx_o[2];
+assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex_sec.alert_tx_o[3];
+assign alert_if[65].alert_tx = `CHIP_HIER.u_smc_uart.alert_tx_o[0];
+assign alert_if[66].alert_tx = `CHIP_HIER.u_rv_timer_smc.alert_tx_o[0];
+assign alert_if[67].alert_tx = `CHIP_HIER.u_cam_i2c.alert_tx_o[0];
+assign alert_if[68].alert_tx = `CHIP_HIER.u_rv_plic_smc.alert_tx_o[0];
+assign alert_if[69].alert_tx = `CHIP_HIER.u_spi_host2.alert_tx_o[0];
+assign alert_if[70].alert_tx = `CHIP_HIER.u_rv_timer_smc2.alert_tx_o[0];
+assign alert_if[71].alert_tx = `CHIP_HIER.u_rv_core_ibex_smc.alert_tx_o[0];
+assign alert_if[72].alert_tx = `CHIP_HIER.u_rv_core_ibex_smc.alert_tx_o[1];
+assign alert_if[73].alert_tx = `CHIP_HIER.u_rv_core_ibex_smc.alert_tx_o[2];
+assign alert_if[74].alert_tx = `CHIP_HIER.u_rv_core_ibex_smc.alert_tx_o[3];
diff --git a/hw/top_sencha/dv/autogen/tb__xbar_connect.sv b/hw/top_sencha/dv/autogen/tb__xbar_connect.sv
new file mode 100644
index 0000000..9cc5dbc
--- /dev/null
+++ b/hw/top_sencha/dv/autogen/tb__xbar_connect.sv
@@ -0,0 +1,279 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// tb__xbar_connect generated by `topgen.py` tool
+
+// This file must be `included in `hw/top_<toplevel>/dv/tb/tb.sv.
+
+`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \
+ force ``tl_name``_tl_if.d2h = dut.top_sencha.u_``inst_name``.``sig_name``_i; \
+ force dut.top_sencha.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \
+ force dut.top_sencha.u_``inst_name``.clk_i = 0; \
+ uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
+ ``tl_name``_tl_if);
+
+`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \
+ force ``tl_name``_tl_if.h2d = dut.top_sencha.u_``inst_name``.``sig_name``_i; \
+ force dut.top_sencha.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \
+ force dut.top_sencha.u_``inst_name``.clk_i = 0; \
+ uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
+ ``tl_name``_tl_if);
+
+`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, inst_name, port_name) \
+ force ``tl_name``_tl_if.h2d = dut.u_``inst_name``.``port_name``_i; \
+ force dut.u_``inst_name``.``port_name``_o = ``tl_name``_tl_if.d2h; \
+ uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \
+ ``tl_name``_tl_if);
+
+wire clk_main;
+clk_rst_if clk_rst_if_main(.clk(clk_main), .rst_n(rst_n));
+wire clk_io;
+clk_rst_if clk_rst_if_io(.clk(clk_io), .rst_n(rst_n));
+wire clk_usb;
+clk_rst_if clk_rst_if_usb(.clk(clk_usb), .rst_n(rst_n));
+wire clk_smc;
+clk_rst_if clk_rst_if_smc(.clk(clk_smc), .rst_n(rst_n));
+wire clk_ml;
+clk_rst_if clk_rst_if_ml(.clk(clk_ml), .rst_n(rst_n));
+wire clk_video;
+clk_rst_if clk_rst_if_video(.clk(clk_video), .rst_n(rst_n));
+wire clk_audio;
+clk_rst_if clk_rst_if_audio(.clk(clk_audio), .rst_n(rst_n));
+wire clk_io_div4;
+clk_rst_if clk_rst_if_io_div4(.clk(clk_io_div4), .rst_n(rst_n));
+
+tl_if rv_core_ibex_sec__corei_tl_if(clk_main, rst_n);
+tl_if rv_core_ibex_sec__cored_tl_if(clk_main, rst_n);
+tl_if rv_dm__sba_tl_if(clk_main, rst_n);
+tl_if dma0__reader_tl_if(clk_main, rst_n);
+tl_if dma0__writer_tl_if(clk_main, rst_n);
+tl_if rv_core_ibex_smc__corei_tl_if(clk_smc, rst_n);
+tl_if rv_core_ibex_smc__cored_tl_if(clk_smc, rst_n);
+tl_if dma_smc__reader_tl_if(clk_smc, rst_n);
+tl_if dma_smc__writer_tl_if(clk_smc, rst_n);
+
+tl_if dma0_tl_if(clk_main, rst_n);
+tl_if rom_ctrl__rom_tl_if(clk_main, rst_n);
+tl_if rom_ctrl__regs_tl_if(clk_main, rst_n);
+tl_if spi_host0_tl_if(clk_io, rst_n);
+tl_if spi_host1_tl_if(clk_io, rst_n);
+tl_if usbdev_tl_if(clk_usb, rst_n);
+tl_if flash_ctrl__core_tl_if(clk_main, rst_n);
+tl_if flash_ctrl__prim_tl_if(clk_main, rst_n);
+tl_if flash_ctrl__mem_tl_if(clk_main, rst_n);
+tl_if hmac_tl_if(clk_main, rst_n);
+tl_if kmac_tl_if(clk_main, rst_n);
+tl_if aes_tl_if(clk_main, rst_n);
+tl_if entropy_src_tl_if(clk_main, rst_n);
+tl_if csrng_tl_if(clk_main, rst_n);
+tl_if edn0_tl_if(clk_main, rst_n);
+tl_if edn1_tl_if(clk_main, rst_n);
+tl_if rv_plic_tl_if(clk_main, rst_n);
+tl_if otbn_tl_if(clk_main, rst_n);
+tl_if keymgr_tl_if(clk_main, rst_n);
+tl_if rv_core_ibex_sec__cfg_tl_if(clk_main, rst_n);
+tl_if sram_ctrl_main__regs_tl_if(clk_main, rst_n);
+tl_if sram_ctrl_main__ram_tl_if(clk_main, rst_n);
+tl_if tlul_mailbox_sec_tl_if(clk_main, rst_n);
+tl_if uart0_tl_if(clk_io_div4, rst_n);
+tl_if uart1_tl_if(clk_io_div4, rst_n);
+tl_if uart2_tl_if(clk_io_div4, rst_n);
+tl_if uart3_tl_if(clk_io_div4, rst_n);
+tl_if i2c0_tl_if(clk_io_div4, rst_n);
+tl_if i2c1_tl_if(clk_io_div4, rst_n);
+tl_if i2c2_tl_if(clk_io_div4, rst_n);
+tl_if pattgen_tl_if(clk_io_div4, rst_n);
+tl_if pwm_aon_tl_if(clk_io_div4, rst_n);
+tl_if gpio_tl_if(clk_io_div4, rst_n);
+tl_if spi_device_tl_if(clk_io_div4, rst_n);
+tl_if rv_timer_tl_if(clk_io_div4, rst_n);
+tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if pinmux_aon_tl_if(clk_io_div4, rst_n);
+tl_if otp_ctrl__core_tl_if(clk_io_div4, rst_n);
+tl_if otp_ctrl__prim_tl_if(clk_io_div4, rst_n);
+tl_if lc_ctrl_tl_if(clk_io_div4, rst_n);
+tl_if sensor_ctrl_tl_if(clk_io_div4, rst_n);
+tl_if alert_handler_tl_if(clk_io_div4, rst_n);
+tl_if sram_ctrl_ret_aon__regs_tl_if(clk_io_div4, rst_n);
+tl_if sram_ctrl_ret_aon__ram_tl_if(clk_io_div4, rst_n);
+tl_if aon_timer_aon_tl_if(clk_io_div4, rst_n);
+tl_if sysrst_ctrl_aon_tl_if(clk_io_div4, rst_n);
+tl_if adc_ctrl_aon_tl_if(clk_io_div4, rst_n);
+tl_if ast_tl_if(clk_io_div4, rst_n);
+tl_if rv_plic_smc_tl_if(clk_smc, rst_n);
+tl_if rv_core_ibex_smc__cfg_tl_if(clk_smc, rst_n);
+tl_if ram_smc_tl_if(clk_smc, rst_n);
+tl_if smc_uart_tl_if(clk_io_div4, rst_n);
+tl_if rv_timer_smc_tl_if(clk_io_div4, rst_n);
+tl_if tlul_mailbox_smc_tl_if(clk_main, rst_n);
+tl_if smc_ctrl_tl_if(clk_smc, rst_n);
+tl_if cam_i2c_tl_if(clk_io_div4, rst_n);
+tl_if cam_ctrl_tl_if(clk_io_div4, rst_n);
+tl_if ml_top__dmem_tl_if(clk_ml, rst_n);
+tl_if ml_top__core_tl_if(clk_ml, rst_n);
+tl_if isp_wrapper_tl_if(clk_smc, rst_n);
+tl_if dma_smc_tl_if(clk_smc, rst_n);
+tl_if spi_host2_tl_if(clk_io, rst_n);
+tl_if rv_timer_smc2_tl_if(clk_io_div4, rst_n);
+tl_if i2s0_tl_if(clk_io_div4, rst_n);
+tl_if rv_dm__regs_tl_if(clk_main, rst_n);
+tl_if rv_dm__mem_tl_if(clk_main, rst_n);
+
+initial begin
+ wait (xbar_mode !== 1'bx);
+ if (xbar_mode) begin
+ // only enable assertions in xbar as many pins are unconnected
+ $assertoff(0, tb);
+ $asserton(0, tb.dut.top_sencha.u_xbar_main);
+ $asserton(0, tb.dut.top_sencha.u_xbar_peri);
+ $asserton(0, tb.dut.top_sencha.u_xbar_smc);
+ $asserton(0, tb.dut.top_sencha.u_xbar_dbg);
+
+ clk_rst_if_main.set_active(.drive_rst_n_val(0));
+ clk_rst_if_main.set_freq_khz(96000000 / 1000);
+ clk_rst_if_io.set_active(.drive_rst_n_val(0));
+ clk_rst_if_io.set_freq_khz(96000000 / 1000);
+ clk_rst_if_usb.set_active(.drive_rst_n_val(0));
+ clk_rst_if_usb.set_freq_khz(48000000 / 1000);
+ clk_rst_if_smc.set_active(.drive_rst_n_val(0));
+ clk_rst_if_smc.set_freq_khz(96000000 / 1000);
+ clk_rst_if_ml.set_active(.drive_rst_n_val(0));
+ clk_rst_if_ml.set_freq_khz(96000000 / 1000);
+ clk_rst_if_video.set_active(.drive_rst_n_val(0));
+ clk_rst_if_video.set_freq_khz(96000000 / 1000);
+ clk_rst_if_audio.set_active(.drive_rst_n_val(0));
+ clk_rst_if_audio.set_freq_khz(48000000 / 1000);
+ clk_rst_if_io_div4.set_active(.drive_rst_n_val(0));
+ clk_rst_if_io_div4.set_freq_khz(24000000 / 1000);
+
+ // bypass clkmgr, force clocks directly
+ force tb.dut.top_sencha.u_xbar_main.clk_main_i = clk_main;
+ force tb.dut.top_sencha.u_xbar_main.clk_fixed_i = clk_io_div4;
+ force tb.dut.top_sencha.u_xbar_main.clk_usb_i = clk_usb;
+ force tb.dut.top_sencha.u_xbar_main.clk_spi_host0_i = clk_io;
+ force tb.dut.top_sencha.u_xbar_main.clk_spi_host1_i = clk_io;
+ force tb.dut.top_sencha.u_xbar_main.clk_smc_i = clk_smc;
+ force tb.dut.top_sencha.u_xbar_peri.clk_peri_i = clk_io_div4;
+ force tb.dut.top_sencha.u_xbar_smc.clk_smc_i = clk_smc;
+ force tb.dut.top_sencha.u_xbar_smc.clk_peri_i = clk_io_div4;
+ force tb.dut.top_sencha.u_xbar_smc.clk_spi_host2_i = clk_io;
+ force tb.dut.top_sencha.u_xbar_smc.clk_ml_i = clk_ml;
+ force tb.dut.top_sencha.u_xbar_smc.clk_video_i = clk_video;
+ force tb.dut.top_sencha.u_xbar_smc.clk_audio_i = clk_audio;
+ force tb.dut.top_sencha.u_xbar_smc.clk_main_i = clk_main;
+ force tb.dut.top_sencha.u_xbar_dbg.clk_main_i = clk_main;
+
+ // bypass rstmgr, force resets directly
+ force tb.dut.top_sencha.u_xbar_main.rst_main_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_main.rst_fixed_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_main.rst_usb_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_main.rst_spi_host0_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_main.rst_spi_host1_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_main.rst_smc_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_peri.rst_peri_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_smc_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_peri_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_spi_host2_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_ml_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_video_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_audio_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_smc.rst_main_ni = rst_n;
+ force tb.dut.top_sencha.u_xbar_dbg.rst_main_ni = rst_n;
+
+ `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex_sec__corei, rv_core_ibex_sec, corei_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex_sec__cored, rv_core_ibex_sec, cored_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(rv_dm__sba, rv_dm, sba_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(dma0__reader, dma0, reader_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(dma0__writer, dma0, writer_tl_h)
+ `DRIVE_CHIP_TL_DEVICE_IF(dma0, dma0, reader_tl_h)
+ `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__rom, rom_ctrl, rom_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__regs, rom_ctrl, regs_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(hmac, hmac, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(kmac, kmac, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(aes, aes, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(entropy_src, entropy_src, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(csrng, csrng, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(edn0, edn0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(edn1, edn1, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(keymgr, keymgr, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex_sec__cfg, rv_core_ibex_sec, cfg_tl_d)
+ `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__regs, sram_ctrl_main, regs_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__ram, sram_ctrl_main, ram_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(tlul_mailbox_sec, tlul_mailbox_sec, core0_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart1, uart1, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart2, uart2, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(uart3, uart3, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(i2c0, i2c0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(i2c1, i2c1, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(i2c2, i2c2, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pattgen, pattgen, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pwm_aon, pwm_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rstmgr_aon, rstmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(clkmgr_aon, clkmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pinmux_aon, pinmux_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl__core, otp_ctrl, core_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl__prim, otp_ctrl, prim_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl, lc_ctrl, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sensor_ctrl, sensor_ctrl, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(alert_handler, alert_handler, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, sram_ctrl_ret_aon, regs_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, sram_ctrl_ret_aon, ram_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(aon_timer_aon, aon_timer_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sysrst_ctrl_aon, sysrst_ctrl_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(adc_ctrl_aon, adc_ctrl_aon, tl)
+ `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast, ast, tl)
+ `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex_smc__corei, rv_core_ibex_smc, corei_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(rv_core_ibex_smc__cored, rv_core_ibex_smc, cored_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(dma_smc__reader, dma_smc, reader_tl_h)
+ `DRIVE_CHIP_TL_HOST_IF(dma_smc__writer, dma_smc, writer_tl_h)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_plic_smc, rv_plic_smc, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_core_ibex_smc__cfg, rv_core_ibex_smc, cfg_tl_d)
+ `DRIVE_CHIP_TL_DEVICE_IF(ram_smc, tl_adapter_ram_smc, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(smc_uart, smc_uart, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_timer_smc, rv_timer_smc, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(tlul_mailbox_smc, tlul_mailbox_sec, core1_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(smc_ctrl, smc_ctrl, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(cam_i2c, cam_i2c, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(cam_ctrl, cam_ctrl, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(ml_top__dmem, ml_top, dmem_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(ml_top__core, ml_top, core_tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(isp_wrapper, isp_wrapper, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(dma_smc, dma_smc, reader_tl_h)
+ `DRIVE_CHIP_TL_DEVICE_IF(spi_host2, spi_host2, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_timer_smc2, rv_timer_smc2, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(i2s0, i2s0, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__regs, rv_dm, regs_tl_d)
+ `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__mem, rv_dm, mem_tl_d)
+ end
+end
+
+`undef DRIVE_CHIP_TL_HOST_IF
+`undef DRIVE_CHIP_TL_DEVICE_IF
+`undef DRIVE_CHIP_TL_EXT_DEVICE_IF
diff --git a/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
new file mode 100644
index 0000000..6f89304
--- /dev/null
+++ b/hw/top_sencha/dv/autogen/xbar_env_pkg__params.sv
@@ -0,0 +1,510 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `topgen.py` tool
+
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+ '{"dma0", '{
+ '{32'h40200000, 32'h4020003f}
+ }},
+ '{"rom_ctrl__rom", '{
+ '{32'h00008000, 32'h0000ffff}
+ }},
+ '{"rom_ctrl__regs", '{
+ '{32'h411e0000, 32'h411e007f}
+ }},
+ '{"spi_host0", '{
+ '{32'h40300000, 32'h4030003f}
+ }},
+ '{"spi_host1", '{
+ '{32'h40310000, 32'h4031003f}
+ }},
+ '{"usbdev", '{
+ '{32'h40320000, 32'h40320fff}
+ }},
+ '{"flash_ctrl__core", '{
+ '{32'h41000000, 32'h410001ff}
+ }},
+ '{"flash_ctrl__prim", '{
+ '{32'h41008000, 32'h4100807f}
+ }},
+ '{"flash_ctrl__mem", '{
+ '{32'h20000000, 32'h200fffff}
+ }},
+ '{"hmac", '{
+ '{32'h41110000, 32'h41110fff}
+ }},
+ '{"kmac", '{
+ '{32'h41120000, 32'h41120fff}
+ }},
+ '{"aes", '{
+ '{32'h41100000, 32'h411000ff}
+ }},
+ '{"entropy_src", '{
+ '{32'h41160000, 32'h411600ff}
+ }},
+ '{"csrng", '{
+ '{32'h41150000, 32'h4115007f}
+ }},
+ '{"edn0", '{
+ '{32'h41170000, 32'h4117007f}
+ }},
+ '{"edn1", '{
+ '{32'h41180000, 32'h4118007f}
+ }},
+ '{"rv_plic", '{
+ '{32'h48000000, 32'h4fffffff}
+ }},
+ '{"otbn", '{
+ '{32'h41130000, 32'h4113ffff}
+ }},
+ '{"keymgr", '{
+ '{32'h41140000, 32'h411400ff}
+ }},
+ '{"rv_core_ibex_sec__cfg", '{
+ '{32'h411f0000, 32'h411f00ff}
+ }},
+ '{"sram_ctrl_main__regs", '{
+ '{32'h411c0000, 32'h411c001f}
+ }},
+ '{"sram_ctrl_main__ram", '{
+ '{32'h10000000, 32'h1001ffff}
+ }},
+ '{"tlul_mailbox_sec", '{
+ '{32'h40800000, 32'h4080003f}
+ }},
+ '{"uart0", '{
+ '{32'h40000000, 32'h4000003f}
+ }},
+ '{"uart1", '{
+ '{32'h40010000, 32'h4001003f}
+ }},
+ '{"uart2", '{
+ '{32'h40020000, 32'h4002003f}
+ }},
+ '{"uart3", '{
+ '{32'h40030000, 32'h4003003f}
+ }},
+ '{"i2c0", '{
+ '{32'h40080000, 32'h4008007f}
+ }},
+ '{"i2c1", '{
+ '{32'h40090000, 32'h4009007f}
+ }},
+ '{"i2c2", '{
+ '{32'h400a0000, 32'h400a007f}
+ }},
+ '{"pattgen", '{
+ '{32'h400e0000, 32'h400e003f}
+ }},
+ '{"pwm_aon", '{
+ '{32'h40450000, 32'h4045007f}
+ }},
+ '{"gpio", '{
+ '{32'h40040000, 32'h4004003f}
+ }},
+ '{"spi_device", '{
+ '{32'h40050000, 32'h40051fff}
+ }},
+ '{"rv_timer", '{
+ '{32'h40100000, 32'h401001ff}
+ }},
+ '{"pwrmgr_aon", '{
+ '{32'h40400000, 32'h4040007f}
+ }},
+ '{"rstmgr_aon", '{
+ '{32'h40410000, 32'h404100ff}
+ }},
+ '{"clkmgr_aon", '{
+ '{32'h40420000, 32'h4042007f}
+ }},
+ '{"pinmux_aon", '{
+ '{32'h40460000, 32'h40460fff}
+ }},
+ '{"otp_ctrl__core", '{
+ '{32'h40130000, 32'h40131fff}
+ }},
+ '{"otp_ctrl__prim", '{
+ '{32'h40132000, 32'h4013201f}
+ }},
+ '{"lc_ctrl", '{
+ '{32'h40140000, 32'h401400ff}
+ }},
+ '{"sensor_ctrl", '{
+ '{32'h40490000, 32'h4049003f}
+ }},
+ '{"alert_handler", '{
+ '{32'h40150000, 32'h401507ff}
+ }},
+ '{"sram_ctrl_ret_aon__regs", '{
+ '{32'h40500000, 32'h4050001f}
+ }},
+ '{"sram_ctrl_ret_aon__ram", '{
+ '{32'h40600000, 32'h40600fff}
+ }},
+ '{"aon_timer_aon", '{
+ '{32'h40470000, 32'h4047003f}
+ }},
+ '{"sysrst_ctrl_aon", '{
+ '{32'h40430000, 32'h404300ff}
+ }},
+ '{"adc_ctrl_aon", '{
+ '{32'h40440000, 32'h4044007f}
+ }},
+ '{"ast", '{
+ '{32'h40480000, 32'h404803ff}
+ }},
+ '{"rv_plic_smc", '{
+ '{32'h60000000, 32'h67ffffff}
+ }},
+ '{"rv_core_ibex_smc__cfg", '{
+ '{32'h54030000, 32'h540300ff}
+ }},
+ '{"ram_smc", '{
+ '{32'h50000000, 32'h503fffff}
+ }},
+ '{"smc_uart", '{
+ '{32'h54000000, 32'h5400003f}
+ }},
+ '{"rv_timer_smc", '{
+ '{32'h54010000, 32'h540101ff}
+ }},
+ '{"tlul_mailbox_smc", '{
+ '{32'h540f1000, 32'h540f103f}
+ }},
+ '{"smc_ctrl", '{
+ '{32'h54020000, 32'h54020007}
+ }},
+ '{"cam_i2c", '{
+ '{32'h54040000, 32'h5404007f}
+ }},
+ '{"cam_ctrl", '{
+ '{32'h54050000, 32'h5405000f}
+ }},
+ '{"ml_top__dmem", '{
+ '{32'h5a000000, 32'h5a3fffff}
+ }},
+ '{"ml_top__core", '{
+ '{32'h5c000000, 32'h5c00003f}
+ }},
+ '{"isp_wrapper", '{
+ '{32'h54060000, 32'h54061fff}
+ }},
+ '{"dma_smc", '{
+ '{32'h54070000, 32'h5407003f}
+ }},
+ '{"spi_host2", '{
+ '{32'h54090000, 32'h5409003f}
+ }},
+ '{"rv_timer_smc2", '{
+ '{32'h54011000, 32'h540111ff}
+ }},
+ '{"i2s0", '{
+ '{32'h54100000, 32'h5410003f}
+ }},
+ '{"rv_dm__regs", '{
+ '{32'h00006000, 32'h00006003}
+ }},
+ '{"rv_dm__mem", '{
+ '{32'h00004000, 32'h00004fff}
+ }}};
+
+ // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+ '{"rv_core_ibex_sec__corei", 0, '{
+ "rom_ctrl__rom",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem"}}
+ ,
+ '{"rv_core_ibex_sec__cored", 1, '{
+ "rom_ctrl__rom",
+ "rom_ctrl__regs",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "sram_ctrl_main__ram",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "pattgen",
+ "gpio",
+ "spi_device",
+ "rv_timer",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "otp_ctrl__core",
+ "otp_ctrl__prim",
+ "lc_ctrl",
+ "sensor_ctrl",
+ "alert_handler",
+ "ast",
+ "sram_ctrl_ret_aon__ram",
+ "sram_ctrl_ret_aon__regs",
+ "aon_timer_aon",
+ "adc_ctrl_aon",
+ "sysrst_ctrl_aon",
+ "pwm_aon",
+ "spi_host0",
+ "spi_host1",
+ "usbdev",
+ "flash_ctrl__core",
+ "flash_ctrl__prim",
+ "flash_ctrl__mem",
+ "aes",
+ "entropy_src",
+ "csrng",
+ "edn0",
+ "edn1",
+ "hmac",
+ "rv_plic",
+ "otbn",
+ "keymgr",
+ "kmac",
+ "sram_ctrl_main__regs",
+ "rv_core_ibex_sec__cfg",
+ "ram_smc",
+ "smc_ctrl",
+ "smc_uart",
+ "rv_timer_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "ram_smc",
+ "rv_core_ibex_smc__cfg",
+ "smc_uart",
+ "rv_timer_smc",
+ "rv_plic_smc",
+ "tlul_mailbox_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "ml_top__dmem",
+ "ram_smc",
+ "ml_top__dmem",
+ "tlul_mailbox_sec",
+ "dma0"}}
+ ,
+ '{"rv_dm__sba", 2, '{
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rom_ctrl__rom",
+ "rom_ctrl__regs",
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "pattgen",
+ "gpio",
+ "spi_device",
+ "rv_timer",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "otp_ctrl__core",
+ "otp_ctrl__prim",
+ "lc_ctrl",
+ "sensor_ctrl",
+ "alert_handler",
+ "ast",
+ "sram_ctrl_ret_aon__ram",
+ "sram_ctrl_ret_aon__regs",
+ "aon_timer_aon",
+ "adc_ctrl_aon",
+ "sysrst_ctrl_aon",
+ "pwm_aon",
+ "spi_host0",
+ "spi_host1",
+ "usbdev",
+ "flash_ctrl__core",
+ "flash_ctrl__prim",
+ "flash_ctrl__mem",
+ "hmac",
+ "kmac",
+ "aes",
+ "entropy_src",
+ "csrng",
+ "edn0",
+ "edn1",
+ "rv_plic",
+ "otbn",
+ "keymgr",
+ "rv_core_ibex_sec__cfg",
+ "sram_ctrl_main__regs",
+ "sram_ctrl_main__ram",
+ "ram_smc",
+ "smc_ctrl",
+ "smc_uart",
+ "rv_timer_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "ram_smc",
+ "rv_core_ibex_smc__cfg",
+ "smc_uart",
+ "rv_timer_smc",
+ "rv_plic_smc",
+ "tlul_mailbox_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "ml_top__dmem",
+ "ram_smc",
+ "ml_top__dmem",
+ "tlul_mailbox_sec"}}
+ ,
+ '{"dma0__reader", 3, '{
+ "rom_ctrl__rom",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem",
+ "ram_smc",
+ "smc_ctrl",
+ "smc_uart",
+ "rv_timer_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "ram_smc",
+ "rv_core_ibex_smc__cfg",
+ "smc_uart",
+ "rv_timer_smc",
+ "rv_plic_smc",
+ "tlul_mailbox_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "ml_top__dmem",
+ "ram_smc",
+ "ml_top__dmem"}}
+ ,
+ '{"dma0__writer", 4, '{
+ "rom_ctrl__rom",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem",
+ "ram_smc",
+ "smc_ctrl",
+ "smc_uart",
+ "rv_timer_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "ram_smc",
+ "rv_core_ibex_smc__cfg",
+ "smc_uart",
+ "rv_timer_smc",
+ "rv_plic_smc",
+ "tlul_mailbox_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_dm__regs",
+ "rv_dm__mem",
+ "rv_timer_smc2",
+ "i2s0",
+ "ram_smc",
+ "ml_top__dmem",
+ "ram_smc",
+ "ml_top__dmem"}}
+};
diff --git a/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
new file mode 100644
index 0000000..c358482
--- /dev/null
+++ b/hw/top_sencha/dv/autogen/xbar_tgl_excl.cfg
@@ -0,0 +1,293 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_tgl_excl.cfg generated by `topgen.py` tool
+
+// [UNSUPPORTED] Exclude unused TL port signals at all hierarchies, wherever port toggle coverage is
+// enabled. Exercising these reserved signals will result in assertion errors thrown by the design.
+-node tb.dut*.u_* *tl_*.a_param
+-node tb.dut*.u_* *tl_*.a_user.rsvd
+-node tb.dut*.u_* *tl_*.d_param
+-node tb.dut*.u_* *tl_*.d_opcode[2:1]
+-node tb.dut*.u_* *tl_*.a_source[7:6]
+-node tb.dut*.u_* *tl_*.d_source[7:6]
+-node tb.dut.top_sencha *tl_*.a_param
+-node tb.dut.top_sencha *tl_*.a_user.rsvd
+-node tb.dut.top_sencha *tl_*.d_param
+-node tb.dut.top_sencha *tl_*.d_opcode[2:1]
+-node tb.dut.top_sencha *tl_*.a_source[7:6]
+-node tb.dut.top_sencha *tl_*.d_source[7:6]
+
+// [LOW_RISK] Exclude the full TL a_address signal on all pass-through hierarchies. We instead look
+// at the full coverage of this signal directly at the host or at the device.
+-node tb.dut.top_sencha *tl_*.a_address
+-node tb.dut.top_sencha.u_xbar_* tl_*.a_address
+
+// [UNR] Exclude unused address bits based on IP address range. It is not possible to cover this.
+-node tb.dut*.u_dma0 tl_*i.a_address[20:6]
+-node tb.dut*.u_dma0 tl_*i.a_address[29:22]
+-node tb.dut*.u_dma0 tl_*i.a_address[31:31]
+-node tb.dut*.u_rom_ctrl rom_tl_*i.a_address[31:16]
+-node tb.dut*.u_rom_ctrl regs_tl_*i.a_address[16:7]
+-node tb.dut*.u_rom_ctrl regs_tl_*i.a_address[23:21]
+-node tb.dut*.u_rom_ctrl regs_tl_*i.a_address[29:25]
+-node tb.dut*.u_rom_ctrl regs_tl_*i.a_address[31:31]
+-node tb.dut*.u_spi_host0 tl_*i.a_address[19:6]
+-node tb.dut*.u_spi_host0 tl_*i.a_address[29:22]
+-node tb.dut*.u_spi_host0 tl_*i.a_address[31:31]
+-node tb.dut*.u_spi_host1 tl_*i.a_address[15:6]
+-node tb.dut*.u_spi_host1 tl_*i.a_address[19:17]
+-node tb.dut*.u_spi_host1 tl_*i.a_address[29:22]
+-node tb.dut*.u_spi_host1 tl_*i.a_address[31:31]
+-node tb.dut*.u_usbdev tl_*i.a_address[16:12]
+-node tb.dut*.u_usbdev tl_*i.a_address[19:18]
+-node tb.dut*.u_usbdev tl_*i.a_address[29:22]
+-node tb.dut*.u_usbdev tl_*i.a_address[31:31]
+-node tb.dut*.u_flash_ctrl core_tl_*i.a_address[23:9]
+-node tb.dut*.u_flash_ctrl core_tl_*i.a_address[29:25]
+-node tb.dut*.u_flash_ctrl core_tl_*i.a_address[31:31]
+-node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[14:7]
+-node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[23:16]
+-node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[29:25]
+-node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[31:31]
+-node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[28:20]
+-node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[31:30]
+-node tb.dut*.u_hmac tl_*i.a_address[15:12]
+-node tb.dut*.u_hmac tl_*i.a_address[19:17]
+-node tb.dut*.u_hmac tl_*i.a_address[23:21]
+-node tb.dut*.u_hmac tl_*i.a_address[29:25]
+-node tb.dut*.u_hmac tl_*i.a_address[31:31]
+-node tb.dut*.u_kmac tl_*i.a_address[16:12]
+-node tb.dut*.u_kmac tl_*i.a_address[19:18]
+-node tb.dut*.u_kmac tl_*i.a_address[23:21]
+-node tb.dut*.u_kmac tl_*i.a_address[29:25]
+-node tb.dut*.u_kmac tl_*i.a_address[31:31]
+-node tb.dut*.u_aes tl_*i.a_address[19:8]
+-node tb.dut*.u_aes tl_*i.a_address[23:21]
+-node tb.dut*.u_aes tl_*i.a_address[29:25]
+-node tb.dut*.u_aes tl_*i.a_address[31:31]
+-node tb.dut*.u_entropy_src tl_*i.a_address[16:8]
+-node tb.dut*.u_entropy_src tl_*i.a_address[19:19]
+-node tb.dut*.u_entropy_src tl_*i.a_address[23:21]
+-node tb.dut*.u_entropy_src tl_*i.a_address[29:25]
+-node tb.dut*.u_entropy_src tl_*i.a_address[31:31]
+-node tb.dut*.u_csrng tl_*i.a_address[15:7]
+-node tb.dut*.u_csrng tl_*i.a_address[17:17]
+-node tb.dut*.u_csrng tl_*i.a_address[19:19]
+-node tb.dut*.u_csrng tl_*i.a_address[23:21]
+-node tb.dut*.u_csrng tl_*i.a_address[29:25]
+-node tb.dut*.u_csrng tl_*i.a_address[31:31]
+-node tb.dut*.u_edn0 tl_*i.a_address[15:7]
+-node tb.dut*.u_edn0 tl_*i.a_address[19:19]
+-node tb.dut*.u_edn0 tl_*i.a_address[23:21]
+-node tb.dut*.u_edn0 tl_*i.a_address[29:25]
+-node tb.dut*.u_edn0 tl_*i.a_address[31:31]
+-node tb.dut*.u_edn1 tl_*i.a_address[18:7]
+-node tb.dut*.u_edn1 tl_*i.a_address[23:21]
+-node tb.dut*.u_edn1 tl_*i.a_address[29:25]
+-node tb.dut*.u_edn1 tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_plic tl_*i.a_address[29:28]
+-node tb.dut*.u_rv_plic tl_*i.a_address[31:31]
+-node tb.dut*.u_otbn tl_*i.a_address[19:18]
+-node tb.dut*.u_otbn tl_*i.a_address[23:21]
+-node tb.dut*.u_otbn tl_*i.a_address[29:25]
+-node tb.dut*.u_otbn tl_*i.a_address[31:31]
+-node tb.dut*.u_keymgr tl_*i.a_address[17:8]
+-node tb.dut*.u_keymgr tl_*i.a_address[19:19]
+-node tb.dut*.u_keymgr tl_*i.a_address[23:21]
+-node tb.dut*.u_keymgr tl_*i.a_address[29:25]
+-node tb.dut*.u_keymgr tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_core_ibex_sec cfg_tl_*i.a_address[15:8]
+-node tb.dut*.u_rv_core_ibex_sec cfg_tl_*i.a_address[23:21]
+-node tb.dut*.u_rv_core_ibex_sec cfg_tl_*i.a_address[29:25]
+-node tb.dut*.u_rv_core_ibex_sec cfg_tl_*i.a_address[31:31]
+-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[17:5]
+-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[23:21]
+-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[29:25]
+-node tb.dut*.u_sram_ctrl_main regs_tl_*i.a_address[31:31]
+-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[27:17]
+-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[31:29]
+-node tb.dut*.u_tlul_mailbox_sec tl_*i.a_address[22:6]
+-node tb.dut*.u_tlul_mailbox_sec tl_*i.a_address[29:24]
+-node tb.dut*.u_tlul_mailbox_sec tl_*i.a_address[31:31]
+-node tb.dut*.u_uart0 tl_*i.a_address[29:6]
+-node tb.dut*.u_uart0 tl_*i.a_address[31:31]
+-node tb.dut*.u_uart1 tl_*i.a_address[15:6]
+-node tb.dut*.u_uart1 tl_*i.a_address[29:17]
+-node tb.dut*.u_uart1 tl_*i.a_address[31:31]
+-node tb.dut*.u_uart2 tl_*i.a_address[16:6]
+-node tb.dut*.u_uart2 tl_*i.a_address[29:18]
+-node tb.dut*.u_uart2 tl_*i.a_address[31:31]
+-node tb.dut*.u_uart3 tl_*i.a_address[15:6]
+-node tb.dut*.u_uart3 tl_*i.a_address[29:18]
+-node tb.dut*.u_uart3 tl_*i.a_address[31:31]
+-node tb.dut*.u_i2c0 tl_*i.a_address[18:7]
+-node tb.dut*.u_i2c0 tl_*i.a_address[29:20]
+-node tb.dut*.u_i2c0 tl_*i.a_address[31:31]
+-node tb.dut*.u_i2c1 tl_*i.a_address[15:7]
+-node tb.dut*.u_i2c1 tl_*i.a_address[18:17]
+-node tb.dut*.u_i2c1 tl_*i.a_address[29:20]
+-node tb.dut*.u_i2c1 tl_*i.a_address[31:31]
+-node tb.dut*.u_i2c2 tl_*i.a_address[16:7]
+-node tb.dut*.u_i2c2 tl_*i.a_address[18:18]
+-node tb.dut*.u_i2c2 tl_*i.a_address[29:20]
+-node tb.dut*.u_i2c2 tl_*i.a_address[31:31]
+-node tb.dut*.u_pattgen tl_*i.a_address[16:6]
+-node tb.dut*.u_pattgen tl_*i.a_address[29:20]
+-node tb.dut*.u_pattgen tl_*i.a_address[31:31]
+-node tb.dut*.u_pwm_aon tl_*i.a_address[15:7]
+-node tb.dut*.u_pwm_aon tl_*i.a_address[17:17]
+-node tb.dut*.u_pwm_aon tl_*i.a_address[21:19]
+-node tb.dut*.u_pwm_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_pwm_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_gpio tl_*i.a_address[17:6]
+-node tb.dut*.u_gpio tl_*i.a_address[29:19]
+-node tb.dut*.u_gpio tl_*i.a_address[31:31]
+-node tb.dut*.u_spi_device tl_*i.a_address[15:13]
+-node tb.dut*.u_spi_device tl_*i.a_address[17:17]
+-node tb.dut*.u_spi_device tl_*i.a_address[29:19]
+-node tb.dut*.u_spi_device tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_timer tl_*i.a_address[19:9]
+-node tb.dut*.u_rv_timer tl_*i.a_address[29:21]
+-node tb.dut*.u_rv_timer tl_*i.a_address[31:31]
+-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[21:7]
+-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:8]
+-node tb.dut*.u_rstmgr_aon tl_*i.a_address[21:17]
+-node tb.dut*.u_rstmgr_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_rstmgr_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_clkmgr_aon tl_*i.a_address[16:7]
+-node tb.dut*.u_clkmgr_aon tl_*i.a_address[21:18]
+-node tb.dut*.u_clkmgr_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_clkmgr_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_pinmux_aon tl_*i.a_address[16:12]
+-node tb.dut*.u_pinmux_aon tl_*i.a_address[21:19]
+-node tb.dut*.u_pinmux_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_pinmux_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[15:13]
+-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[19:18]
+-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[29:21]
+-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[31:31]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[12:5]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[15:14]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[19:18]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[29:21]
+-node tb.dut*.u_otp_ctrl prim_tl_*i.a_address[31:31]
+-node tb.dut*.u_lc_ctrl tl_*i.a_address[17:8]
+-node tb.dut*.u_lc_ctrl tl_*i.a_address[19:19]
+-node tb.dut*.u_lc_ctrl tl_*i.a_address[29:21]
+-node tb.dut*.u_lc_ctrl tl_*i.a_address[31:31]
+-node tb.dut*.u_sensor_ctrl tl_*i.a_address[15:6]
+-node tb.dut*.u_sensor_ctrl tl_*i.a_address[18:17]
+-node tb.dut*.u_sensor_ctrl tl_*i.a_address[21:20]
+-node tb.dut*.u_sensor_ctrl tl_*i.a_address[29:23]
+-node tb.dut*.u_sensor_ctrl tl_*i.a_address[31:31]
+-node tb.dut*.u_alert_handler tl_*i.a_address[15:11]
+-node tb.dut*.u_alert_handler tl_*i.a_address[17:17]
+-node tb.dut*.u_alert_handler tl_*i.a_address[19:19]
+-node tb.dut*.u_alert_handler tl_*i.a_address[29:21]
+-node tb.dut*.u_alert_handler tl_*i.a_address[31:31]
+-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[19:5]
+-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[21:21]
+-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[29:23]
+-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[31:31]
+-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[20:12]
+-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[29:23]
+-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[31:31]
+-node tb.dut*.u_aon_timer_aon tl_*i.a_address[15:6]
+-node tb.dut*.u_aon_timer_aon tl_*i.a_address[21:19]
+-node tb.dut*.u_aon_timer_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_aon_timer_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_sysrst_ctrl_aon tl_*i.a_address[15:8]
+-node tb.dut*.u_sysrst_ctrl_aon tl_*i.a_address[21:18]
+-node tb.dut*.u_sysrst_ctrl_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_sysrst_ctrl_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_adc_ctrl_aon tl_*i.a_address[17:7]
+-node tb.dut*.u_adc_ctrl_aon tl_*i.a_address[21:19]
+-node tb.dut*.u_adc_ctrl_aon tl_*i.a_address[29:23]
+-node tb.dut*.u_adc_ctrl_aon tl_*i.a_address[31:31]
+-node tb.dut*.u_ast tl_*i.a_address[18:10]
+-node tb.dut*.u_ast tl_*i.a_address[21:20]
+-node tb.dut*.u_ast tl_*i.a_address[29:23]
+-node tb.dut*.u_ast tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_plic_smc tl_*i.a_address[28:27]
+-node tb.dut*.u_rv_plic_smc tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[15:8]
+-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[25:18]
+-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[27:27]
+-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[29:29]
+-node tb.dut*.u_rv_core_ibex_smc cfg_tl_*i.a_address[31:31]
+-node tb.dut*.u_ram_smc tl_*i.a_address[27:22]
+-node tb.dut*.u_ram_smc tl_*i.a_address[29:29]
+-node tb.dut*.u_ram_smc tl_*i.a_address[31:31]
+-node tb.dut*.u_smc_uart tl_*i.a_address[25:6]
+-node tb.dut*.u_smc_uart tl_*i.a_address[27:27]
+-node tb.dut*.u_smc_uart tl_*i.a_address[29:29]
+-node tb.dut*.u_smc_uart tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_timer_smc tl_*i.a_address[15:9]
+-node tb.dut*.u_rv_timer_smc tl_*i.a_address[25:17]
+-node tb.dut*.u_rv_timer_smc tl_*i.a_address[27:27]
+-node tb.dut*.u_rv_timer_smc tl_*i.a_address[29:29]
+-node tb.dut*.u_rv_timer_smc tl_*i.a_address[31:31]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[11:6]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[15:13]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[25:20]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[27:27]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[29:29]
+-node tb.dut*.u_tlul_mailbox_smc tl_*i.a_address[31:31]
+-node tb.dut*.u_smc_ctrl tl_*i.a_address[16:3]
+-node tb.dut*.u_smc_ctrl tl_*i.a_address[25:18]
+-node tb.dut*.u_smc_ctrl tl_*i.a_address[27:27]
+-node tb.dut*.u_smc_ctrl tl_*i.a_address[29:29]
+-node tb.dut*.u_smc_ctrl tl_*i.a_address[31:31]
+-node tb.dut*.u_cam_i2c tl_*i.a_address[17:7]
+-node tb.dut*.u_cam_i2c tl_*i.a_address[25:19]
+-node tb.dut*.u_cam_i2c tl_*i.a_address[27:27]
+-node tb.dut*.u_cam_i2c tl_*i.a_address[29:29]
+-node tb.dut*.u_cam_i2c tl_*i.a_address[31:31]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[15:4]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[17:17]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[25:19]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[27:27]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[29:29]
+-node tb.dut*.u_cam_ctrl tl_*i.a_address[31:31]
+-node tb.dut*.u_ml_top dmem_tl_*i.a_address[24:22]
+-node tb.dut*.u_ml_top dmem_tl_*i.a_address[26:26]
+-node tb.dut*.u_ml_top dmem_tl_*i.a_address[29:29]
+-node tb.dut*.u_ml_top dmem_tl_*i.a_address[31:31]
+-node tb.dut*.u_ml_top core_tl_*i.a_address[25:6]
+-node tb.dut*.u_ml_top core_tl_*i.a_address[29:29]
+-node tb.dut*.u_ml_top core_tl_*i.a_address[31:31]
+-node tb.dut*.u_isp_wrapper tl_*i.a_address[16:13]
+-node tb.dut*.u_isp_wrapper tl_*i.a_address[25:19]
+-node tb.dut*.u_isp_wrapper tl_*i.a_address[27:27]
+-node tb.dut*.u_isp_wrapper tl_*i.a_address[29:29]
+-node tb.dut*.u_isp_wrapper tl_*i.a_address[31:31]
+-node tb.dut*.u_dma_smc tl_*i.a_address[15:6]
+-node tb.dut*.u_dma_smc tl_*i.a_address[25:19]
+-node tb.dut*.u_dma_smc tl_*i.a_address[27:27]
+-node tb.dut*.u_dma_smc tl_*i.a_address[29:29]
+-node tb.dut*.u_dma_smc tl_*i.a_address[31:31]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[15:6]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[18:17]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[25:20]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[27:27]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[29:29]
+-node tb.dut*.u_spi_host2 tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[11:9]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[15:13]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[25:17]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[27:27]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[29:29]
+-node tb.dut*.u_rv_timer_smc2 tl_*i.a_address[31:31]
+-node tb.dut*.u_i2s0 tl_*i.a_address[19:6]
+-node tb.dut*.u_i2s0 tl_*i.a_address[25:21]
+-node tb.dut*.u_i2s0 tl_*i.a_address[27:27]
+-node tb.dut*.u_i2s0 tl_*i.a_address[29:29]
+-node tb.dut*.u_i2s0 tl_*i.a_address[31:31]
+-node tb.dut*.u_rv_dm regs_tl_*i.a_address[12:2]
+-node tb.dut*.u_rv_dm regs_tl_*i.a_address[31:15]
+-node tb.dut*.u_rv_dm mem_tl_*i.a_address[13:12]
+-node tb.dut*.u_rv_dm mem_tl_*i.a_address[31:15]
diff --git a/hw/top_sencha/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_sencha/dv/env/autogen/chip_env_pkg__params.sv
new file mode 100644
index 0000000..87cac99
--- /dev/null
+++ b/hw/top_sencha/dv/env/autogen/chip_env_pkg__params.sv
@@ -0,0 +1,85 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Generated by topgen.py
+
+parameter string LIST_OF_ALERTS[] = {
+ "uart0_fatal_fault",
+ "uart1_fatal_fault",
+ "uart2_fatal_fault",
+ "uart3_fatal_fault",
+ "gpio_fatal_fault",
+ "spi_device_fatal_fault",
+ "i2c0_fatal_fault",
+ "i2c1_fatal_fault",
+ "i2c2_fatal_fault",
+ "pattgen_fatal_fault",
+ "rv_timer_fatal_fault",
+ "otp_ctrl_fatal_macro_error",
+ "otp_ctrl_fatal_check_error",
+ "otp_ctrl_fatal_bus_integ_error",
+ "otp_ctrl_fatal_prim_otp_alert",
+ "otp_ctrl_recov_prim_otp_alert",
+ "lc_ctrl_fatal_prog_error",
+ "lc_ctrl_fatal_state_error",
+ "lc_ctrl_fatal_bus_integ_error",
+ "spi_host0_fatal_fault",
+ "spi_host1_fatal_fault",
+ "usbdev_fatal_fault",
+ "pwrmgr_aon_fatal_fault",
+ "rstmgr_aon_fatal_fault",
+ "rstmgr_aon_fatal_cnsty_fault",
+ "clkmgr_aon_recov_fault",
+ "clkmgr_aon_fatal_fault",
+ "sysrst_ctrl_aon_fatal_fault",
+ "adc_ctrl_aon_fatal_fault",
+ "pwm_aon_fatal_fault",
+ "pinmux_aon_fatal_fault",
+ "aon_timer_aon_fatal_fault",
+ "sensor_ctrl_recov_alert",
+ "sensor_ctrl_fatal_alert",
+ "sram_ctrl_ret_aon_fatal_error",
+ "flash_ctrl_recov_err",
+ "flash_ctrl_fatal_std_err",
+ "flash_ctrl_fatal_err",
+ "flash_ctrl_fatal_prim_flash_alert",
+ "flash_ctrl_recov_prim_flash_alert",
+ "rv_dm_fatal_fault",
+ "rv_plic_fatal_fault",
+ "aes_recov_ctrl_update_err",
+ "aes_fatal_fault",
+ "hmac_fatal_fault",
+ "kmac_recov_operation_err",
+ "kmac_fatal_fault_err",
+ "otbn_fatal",
+ "otbn_recov",
+ "keymgr_recov_operation_err",
+ "keymgr_fatal_fault_err",
+ "csrng_recov_alert",
+ "csrng_fatal_alert",
+ "entropy_src_recov_alert",
+ "entropy_src_fatal_alert",
+ "edn0_recov_alert",
+ "edn0_fatal_alert",
+ "edn1_recov_alert",
+ "edn1_fatal_alert",
+ "sram_ctrl_main_fatal_error",
+ "rom_ctrl_fatal",
+ "rv_core_ibex_sec_fatal_sw_err",
+ "rv_core_ibex_sec_recov_sw_err",
+ "rv_core_ibex_sec_fatal_hw_err",
+ "rv_core_ibex_sec_recov_hw_err",
+ "smc_uart_fatal_fault",
+ "rv_timer_smc_fatal_fault",
+ "cam_i2c_fatal_fault",
+ "rv_plic_smc_fatal_fault",
+ "spi_host2_fatal_fault",
+ "rv_timer_smc2_fatal_fault",
+ "rv_core_ibex_smc_fatal_sw_err",
+ "rv_core_ibex_smc_recov_sw_err",
+ "rv_core_ibex_smc_fatal_hw_err",
+ "rv_core_ibex_smc_recov_hw_err"
+};
+
+parameter uint NUM_ALERTS = 75;
diff --git a/hw/top_sencha/ip/ast/rtl/ast_reg_pkg.sv b/hw/top_sencha/ip/ast/rtl/ast_reg_pkg.sv
new file mode 100644
index 0000000..7c54147
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_reg_pkg.sv
@@ -0,0 +1,380 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package ast_reg_pkg;
+
+ // Param list
+ parameter int NumRegsB = 5;
+ parameter int NumUsbBeaconPulses = 8;
+
+ // Address widths within the block
+ parameter int BlockAw = 10;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega0_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega1_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega2_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega3_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega4_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega5_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega6_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega7_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega8_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega9_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega10_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega11_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega12_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega13_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega14_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega15_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega16_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega17_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega18_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega19_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega20_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega21_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega22_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega23_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega24_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega25_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega26_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega27_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega28_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega29_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega30_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega31_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega32_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega33_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega34_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega35_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega36_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_rega37_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic qe;
+ } ast_reg2hw_regal_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } ast_reg2hw_regb_mreg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } ast_hw2reg_regal_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ ast_reg2hw_rega0_reg_t rega0; // [1408:1377]
+ ast_reg2hw_rega1_reg_t rega1; // [1376:1345]
+ ast_reg2hw_rega2_reg_t rega2; // [1344:1313]
+ ast_reg2hw_rega3_reg_t rega3; // [1312:1281]
+ ast_reg2hw_rega4_reg_t rega4; // [1280:1249]
+ ast_reg2hw_rega5_reg_t rega5; // [1248:1217]
+ ast_reg2hw_rega6_reg_t rega6; // [1216:1185]
+ ast_reg2hw_rega7_reg_t rega7; // [1184:1153]
+ ast_reg2hw_rega8_reg_t rega8; // [1152:1121]
+ ast_reg2hw_rega9_reg_t rega9; // [1120:1089]
+ ast_reg2hw_rega10_reg_t rega10; // [1088:1057]
+ ast_reg2hw_rega11_reg_t rega11; // [1056:1025]
+ ast_reg2hw_rega12_reg_t rega12; // [1024:993]
+ ast_reg2hw_rega13_reg_t rega13; // [992:961]
+ ast_reg2hw_rega14_reg_t rega14; // [960:929]
+ ast_reg2hw_rega15_reg_t rega15; // [928:897]
+ ast_reg2hw_rega16_reg_t rega16; // [896:865]
+ ast_reg2hw_rega17_reg_t rega17; // [864:833]
+ ast_reg2hw_rega18_reg_t rega18; // [832:801]
+ ast_reg2hw_rega19_reg_t rega19; // [800:769]
+ ast_reg2hw_rega20_reg_t rega20; // [768:737]
+ ast_reg2hw_rega21_reg_t rega21; // [736:705]
+ ast_reg2hw_rega22_reg_t rega22; // [704:673]
+ ast_reg2hw_rega23_reg_t rega23; // [672:641]
+ ast_reg2hw_rega24_reg_t rega24; // [640:609]
+ ast_reg2hw_rega25_reg_t rega25; // [608:577]
+ ast_reg2hw_rega26_reg_t rega26; // [576:545]
+ ast_reg2hw_rega27_reg_t rega27; // [544:513]
+ ast_reg2hw_rega28_reg_t rega28; // [512:481]
+ ast_reg2hw_rega29_reg_t rega29; // [480:449]
+ ast_reg2hw_rega30_reg_t rega30; // [448:417]
+ ast_reg2hw_rega31_reg_t rega31; // [416:385]
+ ast_reg2hw_rega32_reg_t rega32; // [384:353]
+ ast_reg2hw_rega33_reg_t rega33; // [352:321]
+ ast_reg2hw_rega34_reg_t rega34; // [320:289]
+ ast_reg2hw_rega35_reg_t rega35; // [288:257]
+ ast_reg2hw_rega36_reg_t rega36; // [256:225]
+ ast_reg2hw_rega37_reg_t rega37; // [224:193]
+ ast_reg2hw_regal_reg_t regal; // [192:160]
+ ast_reg2hw_regb_mreg_t [4:0] regb; // [159:0]
+ } ast_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ ast_hw2reg_regal_reg_t regal; // [31:0]
+ } ast_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] AST_REGA0_OFFSET = 10'h 0;
+ parameter logic [BlockAw-1:0] AST_REGA1_OFFSET = 10'h 4;
+ parameter logic [BlockAw-1:0] AST_REGA2_OFFSET = 10'h 8;
+ parameter logic [BlockAw-1:0] AST_REGA3_OFFSET = 10'h c;
+ parameter logic [BlockAw-1:0] AST_REGA4_OFFSET = 10'h 10;
+ parameter logic [BlockAw-1:0] AST_REGA5_OFFSET = 10'h 14;
+ parameter logic [BlockAw-1:0] AST_REGA6_OFFSET = 10'h 18;
+ parameter logic [BlockAw-1:0] AST_REGA7_OFFSET = 10'h 1c;
+ parameter logic [BlockAw-1:0] AST_REGA8_OFFSET = 10'h 20;
+ parameter logic [BlockAw-1:0] AST_REGA9_OFFSET = 10'h 24;
+ parameter logic [BlockAw-1:0] AST_REGA10_OFFSET = 10'h 28;
+ parameter logic [BlockAw-1:0] AST_REGA11_OFFSET = 10'h 2c;
+ parameter logic [BlockAw-1:0] AST_REGA12_OFFSET = 10'h 30;
+ parameter logic [BlockAw-1:0] AST_REGA13_OFFSET = 10'h 34;
+ parameter logic [BlockAw-1:0] AST_REGA14_OFFSET = 10'h 38;
+ parameter logic [BlockAw-1:0] AST_REGA15_OFFSET = 10'h 3c;
+ parameter logic [BlockAw-1:0] AST_REGA16_OFFSET = 10'h 40;
+ parameter logic [BlockAw-1:0] AST_REGA17_OFFSET = 10'h 44;
+ parameter logic [BlockAw-1:0] AST_REGA18_OFFSET = 10'h 48;
+ parameter logic [BlockAw-1:0] AST_REGA19_OFFSET = 10'h 4c;
+ parameter logic [BlockAw-1:0] AST_REGA20_OFFSET = 10'h 50;
+ parameter logic [BlockAw-1:0] AST_REGA21_OFFSET = 10'h 54;
+ parameter logic [BlockAw-1:0] AST_REGA22_OFFSET = 10'h 58;
+ parameter logic [BlockAw-1:0] AST_REGA23_OFFSET = 10'h 5c;
+ parameter logic [BlockAw-1:0] AST_REGA24_OFFSET = 10'h 60;
+ parameter logic [BlockAw-1:0] AST_REGA25_OFFSET = 10'h 64;
+ parameter logic [BlockAw-1:0] AST_REGA26_OFFSET = 10'h 68;
+ parameter logic [BlockAw-1:0] AST_REGA27_OFFSET = 10'h 6c;
+ parameter logic [BlockAw-1:0] AST_REGA28_OFFSET = 10'h 70;
+ parameter logic [BlockAw-1:0] AST_REGA29_OFFSET = 10'h 74;
+ parameter logic [BlockAw-1:0] AST_REGA30_OFFSET = 10'h 78;
+ parameter logic [BlockAw-1:0] AST_REGA31_OFFSET = 10'h 7c;
+ parameter logic [BlockAw-1:0] AST_REGA32_OFFSET = 10'h 80;
+ parameter logic [BlockAw-1:0] AST_REGA33_OFFSET = 10'h 84;
+ parameter logic [BlockAw-1:0] AST_REGA34_OFFSET = 10'h 88;
+ parameter logic [BlockAw-1:0] AST_REGA35_OFFSET = 10'h 8c;
+ parameter logic [BlockAw-1:0] AST_REGA36_OFFSET = 10'h 90;
+ parameter logic [BlockAw-1:0] AST_REGA37_OFFSET = 10'h 94;
+ parameter logic [BlockAw-1:0] AST_REGAL_OFFSET = 10'h 98;
+ parameter logic [BlockAw-1:0] AST_REGB_0_OFFSET = 10'h 200;
+ parameter logic [BlockAw-1:0] AST_REGB_1_OFFSET = 10'h 204;
+ parameter logic [BlockAw-1:0] AST_REGB_2_OFFSET = 10'h 208;
+ parameter logic [BlockAw-1:0] AST_REGB_3_OFFSET = 10'h 20c;
+ parameter logic [BlockAw-1:0] AST_REGB_4_OFFSET = 10'h 210;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [31:0] AST_REGAL_RESVAL = 32'h 26;
+ parameter logic [31:0] AST_REGAL_REG32_RESVAL = 32'h 26;
+
+ // Register index
+ typedef enum int {
+ AST_REGA0,
+ AST_REGA1,
+ AST_REGA2,
+ AST_REGA3,
+ AST_REGA4,
+ AST_REGA5,
+ AST_REGA6,
+ AST_REGA7,
+ AST_REGA8,
+ AST_REGA9,
+ AST_REGA10,
+ AST_REGA11,
+ AST_REGA12,
+ AST_REGA13,
+ AST_REGA14,
+ AST_REGA15,
+ AST_REGA16,
+ AST_REGA17,
+ AST_REGA18,
+ AST_REGA19,
+ AST_REGA20,
+ AST_REGA21,
+ AST_REGA22,
+ AST_REGA23,
+ AST_REGA24,
+ AST_REGA25,
+ AST_REGA26,
+ AST_REGA27,
+ AST_REGA28,
+ AST_REGA29,
+ AST_REGA30,
+ AST_REGA31,
+ AST_REGA32,
+ AST_REGA33,
+ AST_REGA34,
+ AST_REGA35,
+ AST_REGA36,
+ AST_REGA37,
+ AST_REGAL,
+ AST_REGB_0,
+ AST_REGB_1,
+ AST_REGB_2,
+ AST_REGB_3,
+ AST_REGB_4
+ } ast_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] AST_PERMIT [44] = '{
+ 4'b 1111, // index[ 0] AST_REGA0
+ 4'b 1111, // index[ 1] AST_REGA1
+ 4'b 1111, // index[ 2] AST_REGA2
+ 4'b 1111, // index[ 3] AST_REGA3
+ 4'b 1111, // index[ 4] AST_REGA4
+ 4'b 1111, // index[ 5] AST_REGA5
+ 4'b 1111, // index[ 6] AST_REGA6
+ 4'b 1111, // index[ 7] AST_REGA7
+ 4'b 1111, // index[ 8] AST_REGA8
+ 4'b 1111, // index[ 9] AST_REGA9
+ 4'b 1111, // index[10] AST_REGA10
+ 4'b 1111, // index[11] AST_REGA11
+ 4'b 1111, // index[12] AST_REGA12
+ 4'b 1111, // index[13] AST_REGA13
+ 4'b 1111, // index[14] AST_REGA14
+ 4'b 1111, // index[15] AST_REGA15
+ 4'b 1111, // index[16] AST_REGA16
+ 4'b 1111, // index[17] AST_REGA17
+ 4'b 1111, // index[18] AST_REGA18
+ 4'b 1111, // index[19] AST_REGA19
+ 4'b 1111, // index[20] AST_REGA20
+ 4'b 1111, // index[21] AST_REGA21
+ 4'b 1111, // index[22] AST_REGA22
+ 4'b 1111, // index[23] AST_REGA23
+ 4'b 1111, // index[24] AST_REGA24
+ 4'b 1111, // index[25] AST_REGA25
+ 4'b 1111, // index[26] AST_REGA26
+ 4'b 1111, // index[27] AST_REGA27
+ 4'b 1111, // index[28] AST_REGA28
+ 4'b 1111, // index[29] AST_REGA29
+ 4'b 1111, // index[30] AST_REGA30
+ 4'b 1111, // index[31] AST_REGA31
+ 4'b 1111, // index[32] AST_REGA32
+ 4'b 1111, // index[33] AST_REGA33
+ 4'b 1111, // index[34] AST_REGA34
+ 4'b 1111, // index[35] AST_REGA35
+ 4'b 1111, // index[36] AST_REGA36
+ 4'b 1111, // index[37] AST_REGA37
+ 4'b 1111, // index[38] AST_REGAL
+ 4'b 1111, // index[39] AST_REGB_0
+ 4'b 1111, // index[40] AST_REGB_1
+ 4'b 1111, // index[41] AST_REGB_2
+ 4'b 1111, // index[42] AST_REGB_3
+ 4'b 1111 // index[43] AST_REGB_4
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/ast/rtl/ast_reg_top.sv b/hw/top_sencha/ip/ast/rtl/ast_reg_top.sv
new file mode 100644
index 0000000..78104a9
--- /dev/null
+++ b/hw/top_sencha/ip/ast/rtl/ast_reg_top.sv
@@ -0,0 +1,1929 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module ast_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output ast_reg_pkg::ast_reg2hw_t reg2hw, // Write
+ input ast_reg_pkg::ast_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import ast_reg_pkg::* ;
+
+ localparam int AW = 10;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [43:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(44)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic [31:0] rega0_qs;
+ logic [31:0] rega1_qs;
+ logic rega2_we;
+ logic [31:0] rega2_qs;
+ logic [31:0] rega2_wd;
+ logic rega3_we;
+ logic [31:0] rega3_qs;
+ logic [31:0] rega3_wd;
+ logic rega4_we;
+ logic [31:0] rega4_qs;
+ logic [31:0] rega4_wd;
+ logic rega5_we;
+ logic [31:0] rega5_qs;
+ logic [31:0] rega5_wd;
+ logic rega6_we;
+ logic [31:0] rega6_qs;
+ logic [31:0] rega6_wd;
+ logic rega7_we;
+ logic [31:0] rega7_qs;
+ logic [31:0] rega7_wd;
+ logic rega8_we;
+ logic [31:0] rega8_qs;
+ logic [31:0] rega8_wd;
+ logic rega9_we;
+ logic [31:0] rega9_qs;
+ logic [31:0] rega9_wd;
+ logic rega10_we;
+ logic [31:0] rega10_qs;
+ logic [31:0] rega10_wd;
+ logic rega11_we;
+ logic [31:0] rega11_qs;
+ logic [31:0] rega11_wd;
+ logic rega12_we;
+ logic [31:0] rega12_qs;
+ logic [31:0] rega12_wd;
+ logic rega13_we;
+ logic [31:0] rega13_qs;
+ logic [31:0] rega13_wd;
+ logic rega14_we;
+ logic [31:0] rega14_qs;
+ logic [31:0] rega14_wd;
+ logic rega15_we;
+ logic [31:0] rega15_qs;
+ logic [31:0] rega15_wd;
+ logic rega16_we;
+ logic [31:0] rega16_qs;
+ logic [31:0] rega16_wd;
+ logic rega17_we;
+ logic [31:0] rega17_qs;
+ logic [31:0] rega17_wd;
+ logic rega18_we;
+ logic [31:0] rega18_qs;
+ logic [31:0] rega18_wd;
+ logic rega19_we;
+ logic [31:0] rega19_qs;
+ logic [31:0] rega19_wd;
+ logic rega20_we;
+ logic [31:0] rega20_qs;
+ logic [31:0] rega20_wd;
+ logic rega21_we;
+ logic [31:0] rega21_qs;
+ logic [31:0] rega21_wd;
+ logic rega22_we;
+ logic [31:0] rega22_qs;
+ logic [31:0] rega22_wd;
+ logic rega23_we;
+ logic [31:0] rega23_qs;
+ logic [31:0] rega23_wd;
+ logic rega24_we;
+ logic [31:0] rega24_qs;
+ logic [31:0] rega24_wd;
+ logic rega25_we;
+ logic [31:0] rega25_qs;
+ logic [31:0] rega25_wd;
+ logic rega26_we;
+ logic [31:0] rega26_qs;
+ logic [31:0] rega26_wd;
+ logic rega27_we;
+ logic [31:0] rega27_qs;
+ logic [31:0] rega27_wd;
+ logic [31:0] rega28_qs;
+ logic rega29_we;
+ logic [31:0] rega29_qs;
+ logic [31:0] rega29_wd;
+ logic rega30_we;
+ logic [31:0] rega30_qs;
+ logic [31:0] rega30_wd;
+ logic rega31_we;
+ logic [31:0] rega31_qs;
+ logic [31:0] rega31_wd;
+ logic rega32_we;
+ logic [31:0] rega32_qs;
+ logic [31:0] rega32_wd;
+ logic rega33_we;
+ logic [31:0] rega33_qs;
+ logic [31:0] rega33_wd;
+ logic rega34_we;
+ logic [31:0] rega34_qs;
+ logic [31:0] rega34_wd;
+ logic rega35_we;
+ logic [31:0] rega35_qs;
+ logic [31:0] rega35_wd;
+ logic rega36_we;
+ logic [31:0] rega36_qs;
+ logic [31:0] rega36_wd;
+ logic rega37_we;
+ logic [31:0] rega37_qs;
+ logic [31:0] rega37_wd;
+ logic regal_we;
+ logic [31:0] regal_wd;
+ logic regb_0_we;
+ logic [31:0] regb_0_qs;
+ logic [31:0] regb_0_wd;
+ logic regb_1_we;
+ logic [31:0] regb_1_qs;
+ logic [31:0] regb_1_wd;
+ logic regb_2_we;
+ logic [31:0] regb_2_qs;
+ logic [31:0] regb_2_wd;
+ logic regb_3_we;
+ logic [31:0] regb_3_qs;
+ logic [31:0] regb_3_wd;
+ logic regb_4_we;
+ logic [31:0] regb_4_qs;
+ logic [31:0] regb_4_wd;
+
+ // Register instances
+ // R[rega0]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h0)
+ ) u_rega0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega0_qs)
+ );
+
+
+ // R[rega1]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h1)
+ ) u_rega1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega1_qs)
+ );
+
+
+ // R[rega2]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h2)
+ ) u_rega2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega2_we),
+ .wd (rega2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega2_qs)
+ );
+
+
+ // R[rega3]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h3)
+ ) u_rega3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega3_we),
+ .wd (rega3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega3_qs)
+ );
+
+
+ // R[rega4]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h4)
+ ) u_rega4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega4_we),
+ .wd (rega4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega4_qs)
+ );
+
+
+ // R[rega5]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h5)
+ ) u_rega5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega5_we),
+ .wd (rega5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega5_qs)
+ );
+
+
+ // R[rega6]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h6)
+ ) u_rega6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega6_we),
+ .wd (rega6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega6_qs)
+ );
+
+
+ // R[rega7]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h7)
+ ) u_rega7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega7_we),
+ .wd (rega7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega7_qs)
+ );
+
+
+ // R[rega8]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h8)
+ ) u_rega8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega8_we),
+ .wd (rega8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega8_qs)
+ );
+
+
+ // R[rega9]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h9)
+ ) u_rega9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega9_we),
+ .wd (rega9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega9.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega9_qs)
+ );
+
+
+ // R[rega10]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'ha)
+ ) u_rega10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega10_we),
+ .wd (rega10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega10.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega10_qs)
+ );
+
+
+ // R[rega11]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'hb)
+ ) u_rega11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega11_we),
+ .wd (rega11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega11.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega11_qs)
+ );
+
+
+ // R[rega12]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'hc)
+ ) u_rega12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega12_we),
+ .wd (rega12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega12.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega12_qs)
+ );
+
+
+ // R[rega13]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'hd)
+ ) u_rega13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega13_we),
+ .wd (rega13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega13.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega13_qs)
+ );
+
+
+ // R[rega14]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'he)
+ ) u_rega14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega14_we),
+ .wd (rega14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega14.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega14_qs)
+ );
+
+
+ // R[rega15]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'hf)
+ ) u_rega15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega15_we),
+ .wd (rega15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega15.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega15_qs)
+ );
+
+
+ // R[rega16]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h10)
+ ) u_rega16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega16_we),
+ .wd (rega16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega16.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega16_qs)
+ );
+
+
+ // R[rega17]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h11)
+ ) u_rega17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega17_we),
+ .wd (rega17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega17.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega17_qs)
+ );
+
+
+ // R[rega18]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h12)
+ ) u_rega18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega18_we),
+ .wd (rega18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega18.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega18_qs)
+ );
+
+
+ // R[rega19]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h13)
+ ) u_rega19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega19_we),
+ .wd (rega19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega19.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega19_qs)
+ );
+
+
+ // R[rega20]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h14)
+ ) u_rega20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega20_we),
+ .wd (rega20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega20.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega20_qs)
+ );
+
+
+ // R[rega21]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h15)
+ ) u_rega21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega21_we),
+ .wd (rega21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega21.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega21_qs)
+ );
+
+
+ // R[rega22]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h16)
+ ) u_rega22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega22_we),
+ .wd (rega22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega22.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega22_qs)
+ );
+
+
+ // R[rega23]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h17)
+ ) u_rega23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega23_we),
+ .wd (rega23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega23.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega23_qs)
+ );
+
+
+ // R[rega24]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h18)
+ ) u_rega24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega24_we),
+ .wd (rega24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega24.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega24_qs)
+ );
+
+
+ // R[rega25]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h19)
+ ) u_rega25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega25_we),
+ .wd (rega25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega25.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega25_qs)
+ );
+
+
+ // R[rega26]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h1a)
+ ) u_rega26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega26_we),
+ .wd (rega26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega26.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega26_qs)
+ );
+
+
+ // R[rega27]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h1b)
+ ) u_rega27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega27_we),
+ .wd (rega27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega27.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega27_qs)
+ );
+
+
+ // R[rega28]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (32'h1c)
+ ) u_rega28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega28.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega28_qs)
+ );
+
+
+ // R[rega29]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h1d)
+ ) u_rega29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega29_we),
+ .wd (rega29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega29.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega29_qs)
+ );
+
+
+ // R[rega30]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h1e)
+ ) u_rega30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega30_we),
+ .wd (rega30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega30.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega30_qs)
+ );
+
+
+ // R[rega31]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h1f)
+ ) u_rega31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega31_we),
+ .wd (rega31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega31.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega31_qs)
+ );
+
+
+ // R[rega32]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h20)
+ ) u_rega32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega32_we),
+ .wd (rega32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega32.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega32_qs)
+ );
+
+
+ // R[rega33]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h21)
+ ) u_rega33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega33_we),
+ .wd (rega33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega33.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega33_qs)
+ );
+
+
+ // R[rega34]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h22)
+ ) u_rega34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega34_we),
+ .wd (rega34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega34.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega34_qs)
+ );
+
+
+ // R[rega35]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h23)
+ ) u_rega35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega35_we),
+ .wd (rega35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega35.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega35_qs)
+ );
+
+
+ // R[rega36]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h24)
+ ) u_rega36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega36_we),
+ .wd (rega36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega36.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega36_qs)
+ );
+
+
+ // R[rega37]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h25)
+ ) u_rega37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (rega37_we),
+ .wd (rega37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.rega37.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (rega37_qs)
+ );
+
+
+ // R[regal]: V(True)
+ logic regal_qe;
+ logic [0:0] regal_flds_we;
+ assign regal_qe = ®al_flds_we;
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_regal (
+ .re (1'b0),
+ .we (regal_we),
+ .wd (regal_wd),
+ .d (hw2reg.regal.d),
+ .qre (),
+ .qe (regal_flds_we[0]),
+ .q (reg2hw.regal.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.regal.qe = regal_qe;
+
+
+ // Subregister 0 of Multireg regb
+ // R[regb_0]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_regb_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regb_0_we),
+ .wd (regb_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regb[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (regb_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg regb
+ // R[regb_1]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_regb_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regb_1_we),
+ .wd (regb_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regb[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (regb_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg regb
+ // R[regb_2]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_regb_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regb_2_we),
+ .wd (regb_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regb[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (regb_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg regb
+ // R[regb_3]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_regb_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regb_3_we),
+ .wd (regb_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regb[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (regb_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg regb
+ // R[regb_4]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_regb_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regb_4_we),
+ .wd (regb_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regb[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (regb_4_qs)
+ );
+
+
+
+ logic [43:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == AST_REGA0_OFFSET);
+ addr_hit[ 1] = (reg_addr == AST_REGA1_OFFSET);
+ addr_hit[ 2] = (reg_addr == AST_REGA2_OFFSET);
+ addr_hit[ 3] = (reg_addr == AST_REGA3_OFFSET);
+ addr_hit[ 4] = (reg_addr == AST_REGA4_OFFSET);
+ addr_hit[ 5] = (reg_addr == AST_REGA5_OFFSET);
+ addr_hit[ 6] = (reg_addr == AST_REGA6_OFFSET);
+ addr_hit[ 7] = (reg_addr == AST_REGA7_OFFSET);
+ addr_hit[ 8] = (reg_addr == AST_REGA8_OFFSET);
+ addr_hit[ 9] = (reg_addr == AST_REGA9_OFFSET);
+ addr_hit[10] = (reg_addr == AST_REGA10_OFFSET);
+ addr_hit[11] = (reg_addr == AST_REGA11_OFFSET);
+ addr_hit[12] = (reg_addr == AST_REGA12_OFFSET);
+ addr_hit[13] = (reg_addr == AST_REGA13_OFFSET);
+ addr_hit[14] = (reg_addr == AST_REGA14_OFFSET);
+ addr_hit[15] = (reg_addr == AST_REGA15_OFFSET);
+ addr_hit[16] = (reg_addr == AST_REGA16_OFFSET);
+ addr_hit[17] = (reg_addr == AST_REGA17_OFFSET);
+ addr_hit[18] = (reg_addr == AST_REGA18_OFFSET);
+ addr_hit[19] = (reg_addr == AST_REGA19_OFFSET);
+ addr_hit[20] = (reg_addr == AST_REGA20_OFFSET);
+ addr_hit[21] = (reg_addr == AST_REGA21_OFFSET);
+ addr_hit[22] = (reg_addr == AST_REGA22_OFFSET);
+ addr_hit[23] = (reg_addr == AST_REGA23_OFFSET);
+ addr_hit[24] = (reg_addr == AST_REGA24_OFFSET);
+ addr_hit[25] = (reg_addr == AST_REGA25_OFFSET);
+ addr_hit[26] = (reg_addr == AST_REGA26_OFFSET);
+ addr_hit[27] = (reg_addr == AST_REGA27_OFFSET);
+ addr_hit[28] = (reg_addr == AST_REGA28_OFFSET);
+ addr_hit[29] = (reg_addr == AST_REGA29_OFFSET);
+ addr_hit[30] = (reg_addr == AST_REGA30_OFFSET);
+ addr_hit[31] = (reg_addr == AST_REGA31_OFFSET);
+ addr_hit[32] = (reg_addr == AST_REGA32_OFFSET);
+ addr_hit[33] = (reg_addr == AST_REGA33_OFFSET);
+ addr_hit[34] = (reg_addr == AST_REGA34_OFFSET);
+ addr_hit[35] = (reg_addr == AST_REGA35_OFFSET);
+ addr_hit[36] = (reg_addr == AST_REGA36_OFFSET);
+ addr_hit[37] = (reg_addr == AST_REGA37_OFFSET);
+ addr_hit[38] = (reg_addr == AST_REGAL_OFFSET);
+ addr_hit[39] = (reg_addr == AST_REGB_0_OFFSET);
+ addr_hit[40] = (reg_addr == AST_REGB_1_OFFSET);
+ addr_hit[41] = (reg_addr == AST_REGB_2_OFFSET);
+ addr_hit[42] = (reg_addr == AST_REGB_3_OFFSET);
+ addr_hit[43] = (reg_addr == AST_REGB_4_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(AST_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(AST_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(AST_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(AST_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(AST_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(AST_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(AST_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(AST_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(AST_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(AST_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(AST_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(AST_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(AST_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(AST_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(AST_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(AST_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(AST_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(AST_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(AST_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(AST_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(AST_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(AST_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(AST_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(AST_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(AST_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(AST_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(AST_PERMIT[26] & ~reg_be))) |
+ (addr_hit[27] & (|(AST_PERMIT[27] & ~reg_be))) |
+ (addr_hit[28] & (|(AST_PERMIT[28] & ~reg_be))) |
+ (addr_hit[29] & (|(AST_PERMIT[29] & ~reg_be))) |
+ (addr_hit[30] & (|(AST_PERMIT[30] & ~reg_be))) |
+ (addr_hit[31] & (|(AST_PERMIT[31] & ~reg_be))) |
+ (addr_hit[32] & (|(AST_PERMIT[32] & ~reg_be))) |
+ (addr_hit[33] & (|(AST_PERMIT[33] & ~reg_be))) |
+ (addr_hit[34] & (|(AST_PERMIT[34] & ~reg_be))) |
+ (addr_hit[35] & (|(AST_PERMIT[35] & ~reg_be))) |
+ (addr_hit[36] & (|(AST_PERMIT[36] & ~reg_be))) |
+ (addr_hit[37] & (|(AST_PERMIT[37] & ~reg_be))) |
+ (addr_hit[38] & (|(AST_PERMIT[38] & ~reg_be))) |
+ (addr_hit[39] & (|(AST_PERMIT[39] & ~reg_be))) |
+ (addr_hit[40] & (|(AST_PERMIT[40] & ~reg_be))) |
+ (addr_hit[41] & (|(AST_PERMIT[41] & ~reg_be))) |
+ (addr_hit[42] & (|(AST_PERMIT[42] & ~reg_be))) |
+ (addr_hit[43] & (|(AST_PERMIT[43] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign rega2_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign rega2_wd = reg_wdata[31:0];
+ assign rega3_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign rega3_wd = reg_wdata[31:0];
+ assign rega4_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign rega4_wd = reg_wdata[31:0];
+ assign rega5_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign rega5_wd = reg_wdata[31:0];
+ assign rega6_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign rega6_wd = reg_wdata[31:0];
+ assign rega7_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign rega7_wd = reg_wdata[31:0];
+ assign rega8_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign rega8_wd = reg_wdata[31:0];
+ assign rega9_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign rega9_wd = reg_wdata[31:0];
+ assign rega10_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign rega10_wd = reg_wdata[31:0];
+ assign rega11_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign rega11_wd = reg_wdata[31:0];
+ assign rega12_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign rega12_wd = reg_wdata[31:0];
+ assign rega13_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign rega13_wd = reg_wdata[31:0];
+ assign rega14_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign rega14_wd = reg_wdata[31:0];
+ assign rega15_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign rega15_wd = reg_wdata[31:0];
+ assign rega16_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign rega16_wd = reg_wdata[31:0];
+ assign rega17_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign rega17_wd = reg_wdata[31:0];
+ assign rega18_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign rega18_wd = reg_wdata[31:0];
+ assign rega19_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign rega19_wd = reg_wdata[31:0];
+ assign rega20_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign rega20_wd = reg_wdata[31:0];
+ assign rega21_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign rega21_wd = reg_wdata[31:0];
+ assign rega22_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign rega22_wd = reg_wdata[31:0];
+ assign rega23_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign rega23_wd = reg_wdata[31:0];
+ assign rega24_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign rega24_wd = reg_wdata[31:0];
+ assign rega25_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign rega25_wd = reg_wdata[31:0];
+ assign rega26_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign rega26_wd = reg_wdata[31:0];
+ assign rega27_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign rega27_wd = reg_wdata[31:0];
+ assign rega29_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign rega29_wd = reg_wdata[31:0];
+ assign rega30_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign rega30_wd = reg_wdata[31:0];
+ assign rega31_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign rega31_wd = reg_wdata[31:0];
+ assign rega32_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign rega32_wd = reg_wdata[31:0];
+ assign rega33_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign rega33_wd = reg_wdata[31:0];
+ assign rega34_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign rega34_wd = reg_wdata[31:0];
+ assign rega35_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign rega35_wd = reg_wdata[31:0];
+ assign rega36_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign rega36_wd = reg_wdata[31:0];
+ assign rega37_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign rega37_wd = reg_wdata[31:0];
+ assign regal_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign regal_wd = reg_wdata[31:0];
+ assign regb_0_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign regb_0_wd = reg_wdata[31:0];
+ assign regb_1_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign regb_1_wd = reg_wdata[31:0];
+ assign regb_2_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign regb_2_wd = reg_wdata[31:0];
+ assign regb_3_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign regb_3_wd = reg_wdata[31:0];
+ assign regb_4_we = addr_hit[43] & reg_we & !reg_error;
+
+ assign regb_4_wd = reg_wdata[31:0];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = 1'b0;
+ reg_we_check[1] = 1'b0;
+ reg_we_check[2] = rega2_we;
+ reg_we_check[3] = rega3_we;
+ reg_we_check[4] = rega4_we;
+ reg_we_check[5] = rega5_we;
+ reg_we_check[6] = rega6_we;
+ reg_we_check[7] = rega7_we;
+ reg_we_check[8] = rega8_we;
+ reg_we_check[9] = rega9_we;
+ reg_we_check[10] = rega10_we;
+ reg_we_check[11] = rega11_we;
+ reg_we_check[12] = rega12_we;
+ reg_we_check[13] = rega13_we;
+ reg_we_check[14] = rega14_we;
+ reg_we_check[15] = rega15_we;
+ reg_we_check[16] = rega16_we;
+ reg_we_check[17] = rega17_we;
+ reg_we_check[18] = rega18_we;
+ reg_we_check[19] = rega19_we;
+ reg_we_check[20] = rega20_we;
+ reg_we_check[21] = rega21_we;
+ reg_we_check[22] = rega22_we;
+ reg_we_check[23] = rega23_we;
+ reg_we_check[24] = rega24_we;
+ reg_we_check[25] = rega25_we;
+ reg_we_check[26] = rega26_we;
+ reg_we_check[27] = rega27_we;
+ reg_we_check[28] = 1'b0;
+ reg_we_check[29] = rega29_we;
+ reg_we_check[30] = rega30_we;
+ reg_we_check[31] = rega31_we;
+ reg_we_check[32] = rega32_we;
+ reg_we_check[33] = rega33_we;
+ reg_we_check[34] = rega34_we;
+ reg_we_check[35] = rega35_we;
+ reg_we_check[36] = rega36_we;
+ reg_we_check[37] = rega37_we;
+ reg_we_check[38] = regal_we;
+ reg_we_check[39] = regb_0_we;
+ reg_we_check[40] = regb_1_we;
+ reg_we_check[41] = regb_2_we;
+ reg_we_check[42] = regb_3_we;
+ reg_we_check[43] = regb_4_we;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[31:0] = rega0_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[31:0] = rega1_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[31:0] = rega2_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[31:0] = rega3_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[31:0] = rega4_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[31:0] = rega5_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[31:0] = rega6_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[31:0] = rega7_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[31:0] = rega8_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[31:0] = rega9_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = rega10_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[31:0] = rega11_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[31:0] = rega12_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[31:0] = rega13_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[31:0] = rega14_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[31:0] = rega15_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[31:0] = rega16_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[31:0] = rega17_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[31:0] = rega18_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = rega19_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = rega20_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = rega21_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[31:0] = rega22_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[31:0] = rega23_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[31:0] = rega24_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[31:0] = rega25_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[31:0] = rega26_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[31:0] = rega27_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[31:0] = rega28_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[31:0] = rega29_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[31:0] = rega30_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[31:0] = rega31_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[31:0] = rega32_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[31:0] = rega33_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[31:0] = rega34_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[31:0] = rega35_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[31:0] = rega36_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[31:0] = rega37_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[31:0] = '0;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[31:0] = regb_0_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[31:0] = regb_1_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[31:0] = regb_2_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[31:0] = regb_3_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[31:0] = regb_4_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr.hjson
new file mode 100644
index 0000000..f14357a
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -0,0 +1,1287 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+# CLKMGR register template
+#
+{
+ name: "clkmgr",
+ human_name: "Clock Manager",
+ one_line_desc: "Derives and monitors on-chip clock signals, handles clock gating requests from power manager and software",
+ one_paragraph_desc: '''
+ Clock Manager derives on-chip clocks from root clock signals provided by Analog Sensor Top (AST).
+ Input and output clocks may be asynchronous to each other.
+ During clock derivation, Clock Manager can divide clocks to lower frequencies and gate clocks based on control signals from the power manager and to a limited extent from software.
+ For example, the idle status of relevant hardware blocks is tracked and clock gating requests from software are ignored as long as these blocks are active.
+ Further security features include switchable clock jitter, continuous monitoring of clock frequencies, and various countermeasures to deter fault injection (FI) attacks.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_clkmgr",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2S",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ }
+ ]
+ scan: "true",
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {reset: "rst_root_ni"},
+ {clock: "clk_main_i", reset: "rst_main_ni"},
+ {clock: "clk_io_i", reset: "rst_io_ni"},
+ {clock: "clk_usb_i", reset: "rst_usb_ni"},
+ {clock: "clk_aon_i", reset: "rst_aon_ni"},
+ {clock: "clk_smc_i", reset: "rst_smc_ni"},
+ {clock: "clk_ml_i", reset: "rst_ml_ni"},
+ {clock: "clk_video_i", reset: "rst_video_ni"},
+ {clock: "clk_audio_i", reset: "rst_audio_ni"},
+ {clock: "clk_io_div2_i", reset: "rst_io_div2_ni", internal: true},
+ {clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true},
+ {reset: "rst_root_main_ni"},
+ {reset: "rst_root_io_ni"},
+ {reset: "rst_root_io_div2_ni"},
+ {reset: "rst_root_io_div4_ni"},
+ {reset: "rst_root_usb_ni"},
+ {reset: "rst_root_smc_ni"},
+ {reset: "rst_root_ml_ni"},
+ {reset: "rst_root_video_ni"},
+ {reset: "rst_root_audio_ni"},
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ alert_list: [
+ { name: "recov_fault",
+ desc: '''
+ This recoverable alert is triggered when there are measurement errors.
+ '''
+ }
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+ regwidth: "32",
+ param_list: [
+ { name: "NumGroups",
+ desc: "Number of clock groups",
+ type: "int",
+ default: "7",
+ local: "true"
+ },
+ { name: "NumSwGateableClocks",
+ desc: "Number of SW gateable clocks",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+ { name: "NumHintableClocks",
+ desc: "Number of hintable clocks",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ ],
+
+ inter_signal_list: [
+ { struct: "clkmgr_out",
+ type: "uni",
+ name: "clocks",
+ act: "req",
+ package: "clkmgr_pkg",
+ },
+
+ { struct: "clkmgr_cg_en",
+ type: "uni",
+ name: "cg_en",
+ act: "req",
+ package: "clkmgr_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_hw_debug_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "io_clk_byp_req",
+ act: "req",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "io_clk_byp_ack",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "all_clk_byp_req",
+ act: "req",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "all_clk_byp_ack",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "hi_speed_sel",
+ act: "req",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "div_step_down_req",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_clk_byp_req",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_clk_byp_ack",
+ act: "req",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "jitter_en",
+ act: "req",
+ package: "prim_mubi_pkg"
+ },
+
+ // Exported clocks
+
+ { struct: "pwr_clk",
+ type: "req_rsp",
+ name: "pwr",
+ act: "rsp",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "idle",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ width: "4"
+ },
+
+ { struct: "mubi4",
+ desc: "Indicates clocks are calibrated and frequencies accurate",
+ type: "uni",
+ name: "calib_rdy",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ default: "prim_mubi_pkg::MuBi4True"
+ },
+ ],
+
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ },
+ { name: "TIMEOUT.CLK.BKGN_CHK",
+ desc: "Background check for clock timeout."
+ },
+ { name: "MEAS.CLK.BKGN_CHK",
+ desc: "Background check for clock frequency."
+ },
+ { name: "MEAS.CONFIG.SHADOW",
+ desc: "Measurement configurations are shadowed."
+ }
+ { name: "IDLE.INTERSIG.MUBI",
+ desc: "Idle inputs are multibit encoded."
+ }
+ { name: "LC_CTRL.INTERSIG.MUBI",
+ desc: "The life cycle control signals are multibit encoded."
+ }
+ { name: "LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI",
+ desc: "The life cycle clock req/ack signals are multibit encoded."
+ }
+ { name: "CLK_HANDSHAKE.INTERSIG.MUBI",
+ desc: "The external clock req/ack signals are multibit encoded."
+ }
+ { name: "DIV.INTERSIG.MUBI",
+ desc: "Divider step down request is multibit encoded."
+ }
+ { name: "JITTER.CONFIG.MUBI",
+ desc: "The jitter enable configuration is multibit encoded."
+ }
+ { name: "IDLE.CTR.REDUN",
+ desc: "Idle counter is duplicated."
+ }
+ { name: "MEAS.CONFIG.REGWEN",
+ desc: "The measurement controls protected with regwen."
+ }
+ { name: "CLK_CTRL.CONFIG.REGWEN",
+ desc: "Software controlled clock requests are proteced with regwen."
+ }
+
+ ]
+
+ registers: [
+ { name: "EXTCLK_CTRL_REGWEN",
+ desc: "External clock control write enable",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: "1"
+ desc: '''
+ When 1, the value of !!EXTCLK_CTRL can be set. When 0, writes to !!EXTCLK_CTRL have no
+ effect.
+ '''
+ },
+ ]
+ },
+
+ { name: "EXTCLK_CTRL",
+ desc: '''
+ Select external clock
+ ''',
+ regwen: "EXTCLK_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ {
+ bits: "3:0",
+ name: "SEL",
+ mubi: true,
+ desc: '''
+ When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True
+ selects external clock as clock for the system. Writing any other value has
+ no impact.
+
+ When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False
+ selects internal clock as clock for the system. Writing any other value during this stage
+ has no impact.
+
+ While this register can always be programmed, it only takes effect when debug functions are enabled
+ in life cycle TEST, DEV or RMA states.
+ '''
+ resval: "false"
+ },
+ {
+ bits: "7:4",
+ name: "HI_SPEED_SEL",
+ mubi: true,
+ desc: '''
+ A value of kMultiBitBool4True selects nominal speed external clock.
+ All other values selects low speed clocks.
+
+ Note this field only has an effect when the !!EXTCLK_CTRL.SEL field is set to
+ kMultiBitBool4True.
+
+ Nominal speed means the external clock is approximately the same frequency as
+ the internal oscillator source. When this option is used, all clocks operate
+ at roughly the nominal frequency.
+
+ Low speed means the external clock is approximately half the frequency of the
+ internal oscillator source. When this option is used, the internal dividers are
+ stepped down. As a result, previously undivided clocks now run at half frequency,
+ while previously divided clocks run at roughly the nominal frequency.
+
+ See external clock switch support in documentation for more details.
+ '''
+ resval: false
+ }
+ ]
+ // avoid writing random values to this register as it could trigger transient checks
+ // in mubi sync
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "EXTCLK_STATUS",
+ desc: '''
+ Status of requested external clock switch
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ {
+ bits: "3:0",
+ name: "ACK",
+ mubi: true,
+ desc: '''
+ When !!EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects
+ whether the clock has been switched the external source.
+
+ kMultiBitBool4True indicates the switch is complete.
+ kMultiBitBool4False indicates the switch is either not possible or still ongoing.
+ '''
+ resval: "false"
+ },
+ ]
+ },
+
+ { name: "JITTER_REGWEN",
+ desc: "Jitter write enable",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: "1"
+ desc: '''
+ When 1, the value of !!JITTER_ENABLE can be changed. When 0, writes have no
+ effect.
+ '''
+ },
+ ]
+ },
+
+ { name: "JITTER_ENABLE",
+ desc: '''
+ Enable jittery clock
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ {
+ mubi: true,
+ bits: "3:0",
+ name: "VAL",
+ desc: '''
+ Enable jittery clock.
+ A value of kMultiBitBool4False disables the jittery clock,
+ while all other values enable jittery clock.
+ ''',
+ resval: false
+ // avoid writing random values to this register as it could trigger transient checks
+ // in mubi sync
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ }
+ ]
+ },
+
+ { name: "CLK_ENABLES",
+ desc: '''
+ Clock enable for software gateable clocks.
+ These clocks are directly controlled by software.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ {
+ bits: "0",
+ name: "CLK_IO_DIV4_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_IO_DIV4_PERI is disabled.
+ 1 CLK_IO_DIV4_PERI is enabled.
+ '''
+ }
+ {
+ bits: "1",
+ name: "CLK_IO_DIV2_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_IO_DIV2_PERI is disabled.
+ 1 CLK_IO_DIV2_PERI is enabled.
+ '''
+ }
+ {
+ bits: "2",
+ name: "CLK_IO_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_IO_PERI is disabled.
+ 1 CLK_IO_PERI is enabled.
+ '''
+ }
+ {
+ bits: "3",
+ name: "CLK_USB_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_USB_PERI is disabled.
+ 1 CLK_USB_PERI is enabled.
+ '''
+ }
+ {
+ bits: "4",
+ name: "CLK_VIDEO_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_VIDEO_PERI is disabled.
+ 1 CLK_VIDEO_PERI is enabled.
+ '''
+ }
+ {
+ bits: "5",
+ name: "CLK_ML_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_ML_PERI is disabled.
+ 1 CLK_ML_PERI is enabled.
+ '''
+ }
+ {
+ bits: "6",
+ name: "CLK_AUDIO_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_AUDIO_PERI is disabled.
+ 1 CLK_AUDIO_PERI is enabled.
+ '''
+ }
+ {
+ bits: "7",
+ name: "CLK_SMC_PERI_EN",
+ resval: 1,
+ desc: '''
+ 0 CLK_SMC_PERI is disabled.
+ 1 CLK_SMC_PERI is enabled.
+ '''
+ }
+ ]
+ // the CLK_ENABLE register cannot be written.
+ // During top level randomized tests, it is possible to disable the clocks and then access
+ // a register in the disabled block. This would lead to a top level hang.
+ tags: ["excl:CsrAllTests:CsrExclAll"]
+ },
+
+ { name: "CLK_HINTS",
+ desc: '''
+ Clock hint for software gateable transactional clocks during active mode.
+ During low power mode, all clocks are gated off regardless of the software hint.
+
+ Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.
+
+ When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle.
+ If the hardware block is idle, then the clock is disabled.
+ If the hardware block is not idle, the clock is kept on.
+
+ For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any
+ feedback in this case.
+ ''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ {
+ bits: "0",
+ name: "CLK_MAIN_AES_HINT",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_AES can be disabled.
+ 1 CLK_MAIN_AES is enabled.
+ '''
+ }
+ {
+ bits: "1",
+ name: "CLK_MAIN_HMAC_HINT",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_HMAC can be disabled.
+ 1 CLK_MAIN_HMAC is enabled.
+ '''
+ }
+ {
+ bits: "2",
+ name: "CLK_MAIN_KMAC_HINT",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_KMAC can be disabled.
+ 1 CLK_MAIN_KMAC is enabled.
+ '''
+ }
+ {
+ bits: "3",
+ name: "CLK_MAIN_OTBN_HINT",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_OTBN can be disabled.
+ 1 CLK_MAIN_OTBN is enabled.
+ '''
+ }
+ ]
+ // the CLK_HINT register cannot be written.
+ // During top level randomized tests, it is possible to disable the clocks to transactional blocks
+ // and then access a register in the disabled block. This would lead to a top level hang.
+ tags: ["excl:CsrAllTests:CsrExclAll"]
+ },
+
+ { name: "CLK_HINTS_STATUS",
+ desc: '''
+ Since the final state of !!CLK_HINTS is not always determined by software,
+ this register provides read feedback for the current clock state.
+
+ ''',
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ {
+ bits: "0",
+ name: "CLK_MAIN_AES_VAL",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_AES is disabled.
+ 1 CLK_MAIN_AES is enabled.
+ '''
+ }
+ {
+ bits: "1",
+ name: "CLK_MAIN_HMAC_VAL",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_HMAC is disabled.
+ 1 CLK_MAIN_HMAC is enabled.
+ '''
+ }
+ {
+ bits: "2",
+ name: "CLK_MAIN_KMAC_VAL",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_KMAC is disabled.
+ 1 CLK_MAIN_KMAC is enabled.
+ '''
+ }
+ {
+ bits: "3",
+ name: "CLK_MAIN_OTBN_VAL",
+ resval: 1,
+ desc: '''
+ 0 CLK_MAIN_OTBN is disabled.
+ 1 CLK_MAIN_OTBN is enabled.
+ '''
+ }
+ ]
+ // the CLK_HINT_STATUS register is read-only and cannot be checked.
+ // This register's value depends on the IDLE inputs, so cannot be predicted.
+ tags: ["excl:CsrNonInitTests:CsrExclCheck:CsrExclCheck"]
+ },
+
+ { name: "MEASURE_CTRL_REGWEN",
+ desc: "Measurement control write enable",
+ swaccess: "rw0c",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: "1"
+ desc: '''
+ When 1, the value of the measurement control can be set. When 0, writes have no
+ effect.
+ '''
+ },
+ ]
+ },
+ { name: "AUDIO_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_audio_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for audio",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "AUDIO_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for audio measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_audio_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "8:0",
+ name: "HI",
+ desc: "Max threshold for audio measurement",
+ resval: "250"
+ },
+
+ {
+ bits: "17:9",
+ name: "LO",
+ desc: "Min threshold for audio measurement",
+ resval: "230"
+ },
+ ]
+ },
+ { name: "IO_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_io_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for io",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "IO_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for io measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_io_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "9:0",
+ name: "HI",
+ desc: "Max threshold for io measurement",
+ resval: "490"
+ },
+
+ {
+ bits: "19:10",
+ name: "LO",
+ desc: "Min threshold for io measurement",
+ resval: "470"
+ },
+ ]
+ },
+ { name: "IO_DIV2_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_io_div2_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for io_div2",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "IO_DIV2_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for io_div2 measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_io_div2_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "8:0",
+ name: "HI",
+ desc: "Max threshold for io_div2 measurement",
+ resval: "250"
+ },
+
+ {
+ bits: "17:9",
+ name: "LO",
+ desc: "Min threshold for io_div2 measurement",
+ resval: "230"
+ },
+ ]
+ },
+ { name: "IO_DIV4_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_io_div4_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for io_div4",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "IO_DIV4_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for io_div4 measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_io_div4_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "7:0",
+ name: "HI",
+ desc: "Max threshold for io_div4 measurement",
+ resval: "130"
+ },
+
+ {
+ bits: "15:8",
+ name: "LO",
+ desc: "Min threshold for io_div4 measurement",
+ resval: "110"
+ },
+ ]
+ },
+ { name: "MAIN_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_main_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for main",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "MAIN_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for main measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_main_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "9:0",
+ name: "HI",
+ desc: "Max threshold for main measurement",
+ resval: "490"
+ },
+
+ {
+ bits: "19:10",
+ name: "LO",
+ desc: "Min threshold for main measurement",
+ resval: "470"
+ },
+ ]
+ },
+ { name: "ML_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_ml_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for ml",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "ML_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for ml measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_ml_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "9:0",
+ name: "HI",
+ desc: "Max threshold for ml measurement",
+ resval: "490"
+ },
+
+ {
+ bits: "19:10",
+ name: "LO",
+ desc: "Min threshold for ml measurement",
+ resval: "470"
+ },
+ ]
+ },
+ { name: "SMC_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_smc_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for smc",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "SMC_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for smc measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_smc_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "9:0",
+ name: "HI",
+ desc: "Max threshold for smc measurement",
+ resval: "490"
+ },
+
+ {
+ bits: "19:10",
+ name: "LO",
+ desc: "Min threshold for smc measurement",
+ resval: "470"
+ },
+ ]
+ },
+ { name: "USB_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_usb_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for usb",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "USB_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for usb measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_usb_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "8:0",
+ name: "HI",
+ desc: "Max threshold for usb measurement",
+ resval: "250"
+ },
+
+ {
+ bits: "17:9",
+ name: "LO",
+ desc: "Min threshold for usb measurement",
+ resval: "230"
+ },
+ ]
+ },
+ { name: "VIDEO_MEAS_CTRL_EN",
+ desc: '''
+ Enable for measurement control
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ async: "clk_video_i",
+ fields: [
+ {
+ bits: "3:0",
+ name: "EN",
+ desc: "Enable measurement for video",
+ mubi: true,
+ resval: false,
+ },
+ ]
+ // Measurements can cause recoverable errors depending on the
+ // thresholds which randomized CSR tests will not predict correctly.
+ // To provide better CSR coverage we allow writing the threshold
+ // fields, but not enabling the counters.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "VIDEO_MEAS_CTRL_SHADOWED",
+ desc: '''
+ Configuration controls for video measurement.
+
+ The threshold fields are made wider than required (by 1 bit) to ensure
+ there is room to adjust for measurement inaccuracies.
+ ''',
+ regwen: "MEASURE_CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ async: "clk_video_i",
+ shadowed: "true",
+ update_err_alert: "recov_fault",
+ storage_err_alert: "fatal_fault",
+ fields: [
+ {
+ bits: "9:0",
+ name: "HI",
+ desc: "Max threshold for video measurement",
+ resval: "490"
+ },
+
+ {
+ bits: "19:10",
+ name: "LO",
+ desc: "Min threshold for video measurement",
+ resval: "470"
+ },
+ ]
+ },
+
+ { name: "RECOV_ERR_CODE",
+ desc: "Recoverable Error code ",
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ name: "SHADOW_UPDATE_ERR",
+ resval: 0
+ desc: '''
+ One of the shadow registers encountered an update error.
+ '''
+ },
+ {
+ bits: "1",
+ name: "AUDIO_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ audio has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "2",
+ name: "IO_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ io has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "3",
+ name: "IO_DIV2_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ io_div2 has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "4",
+ name: "IO_DIV4_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ io_div4 has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "5",
+ name: "MAIN_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ main has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "6",
+ name: "ML_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ ml has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "7",
+ name: "SMC_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ smc has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "8",
+ name: "USB_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ usb has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "9",
+ name: "VIDEO_MEASURE_ERR",
+ resval: 0,
+ desc: '''
+ video has encountered a measurement error.
+ '''
+ },
+ {
+ bits: "10",
+ name: "AUDIO_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ audio has timed out.
+ '''
+ }
+ {
+ bits: "11",
+ name: "IO_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ io has timed out.
+ '''
+ }
+ {
+ bits: "12",
+ name: "IO_DIV2_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ io_div2 has timed out.
+ '''
+ }
+ {
+ bits: "13",
+ name: "IO_DIV4_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ io_div4 has timed out.
+ '''
+ }
+ {
+ bits: "14",
+ name: "MAIN_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ main has timed out.
+ '''
+ }
+ {
+ bits: "15",
+ name: "ML_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ ml has timed out.
+ '''
+ }
+ {
+ bits: "16",
+ name: "SMC_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ smc has timed out.
+ '''
+ }
+ {
+ bits: "17",
+ name: "USB_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ usb has timed out.
+ '''
+ }
+ {
+ bits: "18",
+ name: "VIDEO_TIMEOUT_ERR",
+ resval: 0,
+ desc: '''
+ video has timed out.
+ '''
+ }
+ ]
+ },
+
+ { name: "FATAL_ERR_CODE",
+ desc: "Error code ",
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "REG_INTG",
+ resval: 0
+ desc: '''
+ Register file has experienced a fatal integrity error.
+ '''
+ },
+ { bits: "1",
+ name: "IDLE_CNT",
+ resval: 0
+ desc: '''
+ One of the idle counts encountered a duplicate error.
+ '''
+ },
+ { bits: "2",
+ name: "SHADOW_STORAGE_ERR",
+ resval: 0
+ desc: '''
+ One of the shadow registers encountered a storage error.
+ '''
+ },
+ ]
+ },
+ ]
+}
diff --git a/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr.sv
new file mode 100644
index 0000000..2741d0e
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -0,0 +1,1576 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// The overall clock manager
+
+
+`include "prim_assert.sv"
+
+ module clkmgr
+ import clkmgr_pkg::*;
+ import clkmgr_reg_pkg::*;
+ import lc_ctrl_pkg::lc_tx_t;
+ import prim_mubi_pkg::mubi4_t;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
+ // Primary module control clocks and resets
+ // This drives the register interface
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+
+ // System clocks and resets
+ // These are the source clocks for the system
+ input clk_main_i,
+ input rst_main_ni,
+ input clk_io_i,
+ input rst_io_ni,
+ input clk_usb_i,
+ input rst_usb_ni,
+ input clk_aon_i,
+ input rst_aon_ni,
+ input clk_smc_i,
+ input rst_smc_ni,
+ input clk_ml_i,
+ input rst_ml_ni,
+ input clk_video_i,
+ input rst_video_ni,
+ input clk_audio_i,
+ input rst_audio_ni,
+
+ // Resets for derived clocks
+ // clocks are derived locally
+ input rst_io_div2_ni,
+ input rst_io_div4_ni,
+
+ // Resets for derived clock generation, root clock gating and related status
+ input rst_root_ni,
+ input rst_root_main_ni,
+ input rst_root_io_ni,
+ input rst_root_io_div2_ni,
+ input rst_root_io_div4_ni,
+ input rst_root_usb_ni,
+ input rst_root_smc_ni,
+ input rst_root_ml_ni,
+ input rst_root_video_ni,
+ input rst_root_audio_ni,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // pwrmgr interface
+ input pwrmgr_pkg::pwr_clk_req_t pwr_i,
+ output pwrmgr_pkg::pwr_clk_rsp_t pwr_o,
+
+ // dft interface
+ input prim_mubi_pkg::mubi4_t scanmode_i,
+
+ // idle hints
+ // SEC_CM: IDLE.INTERSIG.MUBI
+ input prim_mubi_pkg::mubi4_t [3:0] idle_i,
+
+ // life cycle state output
+ // SEC_CM: LC_CTRL.INTERSIG.MUBI
+ input lc_tx_t lc_hw_debug_en_i,
+
+ // clock bypass control with lc_ctrl
+ // SEC_CM: LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI
+ input lc_tx_t lc_clk_byp_req_i,
+ output lc_tx_t lc_clk_byp_ack_o,
+
+ // clock bypass control with ast
+ // SEC_CM: CLK_HANDSHAKE.INTERSIG.MUBI
+ output mubi4_t io_clk_byp_req_o,
+ input mubi4_t io_clk_byp_ack_i,
+ output mubi4_t all_clk_byp_req_o,
+ input mubi4_t all_clk_byp_ack_i,
+ output mubi4_t hi_speed_sel_o,
+
+ // clock calibration has been done.
+ // If this is signal is 0, assume clock frequencies to be
+ // uncalibrated.
+ input prim_mubi_pkg::mubi4_t calib_rdy_i,
+
+ // jittery enable to ast
+ output mubi4_t jitter_en_o,
+
+ // external indication for whether dividers should be stepped down
+ // SEC_CM: DIV.INTERSIG.MUBI
+ input mubi4_t div_step_down_req_i,
+
+ // clock gated indications going to alert handlers
+ output clkmgr_cg_en_t cg_en_o,
+
+ // clock output interface
+ output clkmgr_out_t clocks_o
+
+);
+
+ import prim_mubi_pkg::MuBi4False;
+ import prim_mubi_pkg::MuBi4True;
+ import prim_mubi_pkg::mubi4_test_true_strict;
+ import prim_mubi_pkg::mubi4_test_true_loose;
+ import prim_mubi_pkg::mubi4_test_false_strict;
+
+ ////////////////////////////////////////////////////
+ // External step down request
+ ////////////////////////////////////////////////////
+ mubi4_t io_step_down_req;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(1),
+ .StabilityCheck(1),
+ .ResetValue(MuBi4False)
+ ) u_io_step_down_req_sync (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .mubi_i(div_step_down_req_i),
+ .mubi_o({io_step_down_req})
+ );
+
+
+ ////////////////////////////////////////////////////
+ // Divided clocks
+ // Note divided clocks must use the por version of
+ // its related reset to ensure clock division
+ // can happen without any dependency
+ ////////////////////////////////////////////////////
+
+ logic [1:0] step_down_acks;
+
+ logic clk_io_div2_i;
+ logic clk_io_div4_i;
+
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] io_div2_div_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_io_div2_div_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o({io_div2_div_scanmode})
+ );
+
+ prim_clock_div #(
+ .Divisor(2)
+ ) u_no_scan_io_div2_div (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_root_io_ni),
+ .step_down_req_i(mubi4_test_true_strict(io_step_down_req)),
+ .step_down_ack_o(step_down_acks[0]),
+ .test_en_i(mubi4_test_true_strict(io_div2_div_scanmode[0])),
+ .clk_o(clk_io_div2_i)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] io_div4_div_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_io_div4_div_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o({io_div4_div_scanmode})
+ );
+
+ prim_clock_div #(
+ .Divisor(4)
+ ) u_no_scan_io_div4_div (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_root_io_ni),
+ .step_down_req_i(mubi4_test_true_strict(io_step_down_req)),
+ .step_down_ack_o(step_down_acks[1]),
+ .test_en_i(mubi4_test_true_strict(io_div4_div_scanmode[0])),
+ .clk_o(clk_io_div4_i)
+ );
+
+ ////////////////////////////////////////////////////
+ // Register Interface
+ ////////////////////////////////////////////////////
+
+ logic [NumAlerts-1:0] alert_test, alerts;
+ clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw;
+ clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg;
+
+ // SEC_CM: MEAS.CONFIG.REGWEN
+ // SEC_CM: MEAS.CONFIG.SHADOW
+ // SEC_CM: CLK_CTRL.CONFIG.REGWEN
+ clkmgr_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .rst_shadowed_ni,
+ .clk_audio_i,
+ .rst_audio_ni,
+ .clk_io_i,
+ .rst_io_ni,
+ .clk_io_div2_i,
+ .rst_io_div2_ni,
+ .clk_io_div4_i,
+ .rst_io_div4_ni,
+ .clk_main_i,
+ .rst_main_ni,
+ .clk_ml_i,
+ .rst_ml_ni,
+ .clk_smc_i,
+ .rst_smc_ni,
+ .clk_usb_i,
+ .rst_usb_ni,
+ .clk_video_i,
+ .rst_video_ni,
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .shadowed_storage_err_o(hw2reg.fatal_err_code.shadow_storage_err.de),
+ .shadowed_update_err_o(hw2reg.recov_err_code.shadow_update_err.de),
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o(hw2reg.fatal_err_code.reg_intg.de),
+ .devmode_i(1'b1)
+ );
+ assign hw2reg.fatal_err_code.reg_intg.d = 1'b1;
+ assign hw2reg.recov_err_code.shadow_update_err.d = 1'b1;
+ assign hw2reg.fatal_err_code.shadow_storage_err.d = 1'b1;
+
+ ////////////////////////////////////////////////////
+ // Alerts
+ ////////////////////////////////////////////////////
+
+ assign alert_test = {
+ reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe,
+ reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe
+ };
+
+ logic recov_alert;
+ assign recov_alert =
+ hw2reg.recov_err_code.audio_measure_err.de |
+ hw2reg.recov_err_code.audio_timeout_err.de |
+ hw2reg.recov_err_code.io_measure_err.de |
+ hw2reg.recov_err_code.io_timeout_err.de |
+ hw2reg.recov_err_code.io_div2_measure_err.de |
+ hw2reg.recov_err_code.io_div2_timeout_err.de |
+ hw2reg.recov_err_code.io_div4_measure_err.de |
+ hw2reg.recov_err_code.io_div4_timeout_err.de |
+ hw2reg.recov_err_code.main_measure_err.de |
+ hw2reg.recov_err_code.main_timeout_err.de |
+ hw2reg.recov_err_code.ml_measure_err.de |
+ hw2reg.recov_err_code.ml_timeout_err.de |
+ hw2reg.recov_err_code.smc_measure_err.de |
+ hw2reg.recov_err_code.smc_timeout_err.de |
+ hw2reg.recov_err_code.usb_measure_err.de |
+ hw2reg.recov_err_code.usb_timeout_err.de |
+ hw2reg.recov_err_code.video_measure_err.de |
+ hw2reg.recov_err_code.video_timeout_err.de |
+ hw2reg.recov_err_code.shadow_update_err.de;
+
+ assign alerts = {
+ |reg2hw.fatal_err_code,
+ recov_alert
+ };
+
+ localparam logic [NumAlerts-1:0] AlertFatal = {1'b1, 1'b0};
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(AlertFatal[i])
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ ////////////////////////////////////////////////////
+ // Clock bypass request
+ ////////////////////////////////////////////////////
+
+ mubi4_t extclk_ctrl_sel;
+ mubi4_t extclk_ctrl_hi_speed_sel;
+
+ assign extclk_ctrl_sel = mubi4_t'(reg2hw.extclk_ctrl.sel.q);
+ assign extclk_ctrl_hi_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q);
+
+ clkmgr_byp #(
+ .NumDivClks(2)
+ ) u_clkmgr_byp (
+ .clk_i,
+ .rst_ni,
+ .en_i(lc_hw_debug_en_i),
+ .lc_clk_byp_req_i,
+ .lc_clk_byp_ack_o,
+ .byp_req_i(extclk_ctrl_sel),
+ .byp_ack_o(hw2reg.extclk_status.d),
+ .hi_speed_sel_i(extclk_ctrl_hi_speed_sel),
+ .all_clk_byp_req_o,
+ .all_clk_byp_ack_i,
+ .io_clk_byp_req_o,
+ .io_clk_byp_ack_i,
+ .hi_speed_sel_o,
+
+ // divider step down controls
+ .step_down_acks_i(step_down_acks)
+ );
+
+ ////////////////////////////////////////////////////
+ // Feed through clocks
+ // Feed through clocks do not actually need to be in clkmgr, as they are
+ // completely untouched. The only reason they are here is for easier
+ // bundling management purposes through clocks_o
+ ////////////////////////////////////////////////////
+ prim_clock_buf u_clk_io_div4_powerup_buf (
+ .clk_i(clk_io_div4_i),
+ .clk_o(clocks_o.clk_io_div4_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.io_div4_powerup = MuBi4False;
+ prim_clock_buf u_clk_aon_powerup_buf (
+ .clk_i(clk_aon_i),
+ .clk_o(clocks_o.clk_aon_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.aon_powerup = MuBi4False;
+ prim_clock_buf u_clk_main_powerup_buf (
+ .clk_i(clk_main_i),
+ .clk_o(clocks_o.clk_main_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.main_powerup = MuBi4False;
+ prim_clock_buf u_clk_io_powerup_buf (
+ .clk_i(clk_io_i),
+ .clk_o(clocks_o.clk_io_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.io_powerup = MuBi4False;
+ prim_clock_buf u_clk_usb_powerup_buf (
+ .clk_i(clk_usb_i),
+ .clk_o(clocks_o.clk_usb_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.usb_powerup = MuBi4False;
+ prim_clock_buf u_clk_io_div2_powerup_buf (
+ .clk_i(clk_io_div2_i),
+ .clk_o(clocks_o.clk_io_div2_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.io_div2_powerup = MuBi4False;
+ prim_clock_buf u_clk_smc_powerup_buf (
+ .clk_i(clk_smc_i),
+ .clk_o(clocks_o.clk_smc_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.smc_powerup = MuBi4False;
+ prim_clock_buf u_clk_ml_powerup_buf (
+ .clk_i(clk_ml_i),
+ .clk_o(clocks_o.clk_ml_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.ml_powerup = MuBi4False;
+ prim_clock_buf u_clk_video_powerup_buf (
+ .clk_i(clk_video_i),
+ .clk_o(clocks_o.clk_video_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.video_powerup = MuBi4False;
+ prim_clock_buf u_clk_audio_powerup_buf (
+ .clk_i(clk_audio_i),
+ .clk_o(clocks_o.clk_audio_powerup)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.audio_powerup = MuBi4False;
+ prim_clock_buf u_clk_aon_secure_buf (
+ .clk_i(clk_aon_i),
+ .clk_o(clocks_o.clk_aon_secure)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.aon_secure = MuBi4False;
+ prim_clock_buf u_clk_aon_peri_buf (
+ .clk_i(clk_aon_i),
+ .clk_o(clocks_o.clk_aon_peri)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.aon_peri = MuBi4False;
+ prim_clock_buf u_clk_aon_timers_buf (
+ .clk_i(clk_aon_i),
+ .clk_o(clocks_o.clk_aon_timers)
+ );
+
+ // clock gated indication for alert handler: these clocks are never gated.
+ assign cg_en_o.aon_timers = MuBi4False;
+
+ ////////////////////////////////////////////////////
+ // Distribute pwrmgr ip_clk_en requests to each family
+ ////////////////////////////////////////////////////
+ // clk_main family
+ logic pwrmgr_main_en;
+ assign pwrmgr_main_en = pwr_i.main_ip_clk_en;
+ // clk_io family
+ logic pwrmgr_io_en;
+ logic pwrmgr_io_div2_en;
+ logic pwrmgr_io_div4_en;
+ assign pwrmgr_io_en = pwr_i.io_ip_clk_en;
+ assign pwrmgr_io_div2_en = pwr_i.io_ip_clk_en;
+ assign pwrmgr_io_div4_en = pwr_i.io_ip_clk_en;
+ // clk_usb family
+ logic pwrmgr_usb_en;
+ assign pwrmgr_usb_en = pwr_i.usb_ip_clk_en;
+ // clk_smc family
+ logic pwrmgr_smc_en;
+ assign pwrmgr_smc_en = pwr_i.smc_ip_clk_en;
+ // clk_ml family
+ logic pwrmgr_ml_en;
+ assign pwrmgr_ml_en = pwr_i.ml_ip_clk_en;
+ // clk_video family
+ logic pwrmgr_video_en;
+ assign pwrmgr_video_en = pwr_i.video_ip_clk_en;
+ // clk_audio family
+ logic pwrmgr_audio_en;
+ assign pwrmgr_audio_en = pwr_i.audio_ip_clk_en;
+
+ ////////////////////////////////////////////////////
+ // Root gating
+ ////////////////////////////////////////////////////
+
+ // clk_main family
+ logic [0:0] main_ens;
+
+ logic clk_main_en;
+ logic clk_main_root;
+ clkmgr_root_ctrl u_main_root_ctrl (
+ .clk_i(clk_main_i),
+ .rst_ni(rst_root_main_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_main_en),
+ .en_o(clk_main_en),
+ .clk_o(clk_main_root)
+ );
+ assign main_ens[0] = clk_main_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_main_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(main_ens),
+ .status_o(pwr_o.main_status)
+ );
+
+ // clk_io family
+ logic [2:0] io_ens;
+
+ logic clk_io_en;
+ logic clk_io_root;
+ clkmgr_root_ctrl u_io_root_ctrl (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_root_io_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_io_en),
+ .en_o(clk_io_en),
+ .clk_o(clk_io_root)
+ );
+ assign io_ens[0] = clk_io_en;
+
+ logic clk_io_div2_en;
+ logic clk_io_div2_root;
+ clkmgr_root_ctrl u_io_div2_root_ctrl (
+ .clk_i(clk_io_div2_i),
+ .rst_ni(rst_root_io_div2_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_io_div2_en),
+ .en_o(clk_io_div2_en),
+ .clk_o(clk_io_div2_root)
+ );
+ assign io_ens[1] = clk_io_div2_en;
+
+ logic clk_io_div4_en;
+ logic clk_io_div4_root;
+ clkmgr_root_ctrl u_io_div4_root_ctrl (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_root_io_div4_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_io_div4_en),
+ .en_o(clk_io_div4_en),
+ .clk_o(clk_io_div4_root)
+ );
+ assign io_ens[2] = clk_io_div4_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(3)
+ ) u_io_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(io_ens),
+ .status_o(pwr_o.io_status)
+ );
+
+ // clk_usb family
+ logic [0:0] usb_ens;
+
+ logic clk_usb_en;
+ logic clk_usb_root;
+ clkmgr_root_ctrl u_usb_root_ctrl (
+ .clk_i(clk_usb_i),
+ .rst_ni(rst_root_usb_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_usb_en),
+ .en_o(clk_usb_en),
+ .clk_o(clk_usb_root)
+ );
+ assign usb_ens[0] = clk_usb_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_usb_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(usb_ens),
+ .status_o(pwr_o.usb_status)
+ );
+
+ // clk_smc family
+ logic [0:0] smc_ens;
+
+ logic clk_smc_en;
+ logic clk_smc_root;
+ clkmgr_root_ctrl u_smc_root_ctrl (
+ .clk_i(clk_smc_i),
+ .rst_ni(rst_root_smc_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_smc_en),
+ .en_o(clk_smc_en),
+ .clk_o(clk_smc_root)
+ );
+ assign smc_ens[0] = clk_smc_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_smc_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(smc_ens),
+ .status_o(pwr_o.smc_status)
+ );
+
+ // clk_ml family
+ logic [0:0] ml_ens;
+
+ logic clk_ml_en;
+ logic clk_ml_root;
+ clkmgr_root_ctrl u_ml_root_ctrl (
+ .clk_i(clk_ml_i),
+ .rst_ni(rst_root_ml_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_ml_en),
+ .en_o(clk_ml_en),
+ .clk_o(clk_ml_root)
+ );
+ assign ml_ens[0] = clk_ml_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_ml_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(ml_ens),
+ .status_o(pwr_o.ml_status)
+ );
+
+ // clk_video family
+ logic [0:0] video_ens;
+
+ logic clk_video_en;
+ logic clk_video_root;
+ clkmgr_root_ctrl u_video_root_ctrl (
+ .clk_i(clk_video_i),
+ .rst_ni(rst_root_video_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_video_en),
+ .en_o(clk_video_en),
+ .clk_o(clk_video_root)
+ );
+ assign video_ens[0] = clk_video_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_video_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(video_ens),
+ .status_o(pwr_o.video_status)
+ );
+
+ // clk_audio family
+ logic [0:0] audio_ens;
+
+ logic clk_audio_en;
+ logic clk_audio_root;
+ clkmgr_root_ctrl u_audio_root_ctrl (
+ .clk_i(clk_audio_i),
+ .rst_ni(rst_root_audio_ni),
+ .scanmode_i,
+ .async_en_i(pwrmgr_audio_en),
+ .en_o(clk_audio_en),
+ .clk_o(clk_audio_root)
+ );
+ assign audio_ens[0] = clk_audio_en;
+
+ // create synchronized status
+ clkmgr_clk_status #(
+ .NumClocks(1)
+ ) u_audio_status (
+ .clk_i,
+ .rst_ni(rst_root_ni),
+ .ens_i(audio_ens),
+ .status_o(pwr_o.audio_status)
+ );
+
+ ////////////////////////////////////////////////////
+ // Clock Measurement for the roots
+ // SEC_CM: TIMEOUT.CLK.BKGN_CHK, MEAS.CLK.BKGN_CHK
+ ////////////////////////////////////////////////////
+
+ typedef enum logic [3:0] {
+ BaseIdx,
+ ClkAudioIdx,
+ ClkIoIdx,
+ ClkIoDiv2Idx,
+ ClkIoDiv4Idx,
+ ClkMainIdx,
+ ClkMlIdx,
+ ClkSmcIdx,
+ ClkUsbIdx,
+ ClkVideoIdx,
+ CalibRdyLastIdx
+ } clkmgr_calib_idx_e;
+
+ // if clocks become uncalibrated, allow the measurement control configurations to change
+ mubi4_t [CalibRdyLastIdx-1:0] calib_rdy;
+ prim_mubi4_sync #(
+ .AsyncOn(1),
+ .NumCopies(int'(CalibRdyLastIdx)),
+ .ResetValue(MuBi4False)
+ ) u_calib_rdy_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(calib_rdy_i),
+ .mubi_o({calib_rdy})
+ );
+
+ always_comb begin
+ hw2reg.measure_ctrl_regwen.de = '0;
+ hw2reg.measure_ctrl_regwen.d = reg2hw.measure_ctrl_regwen;
+
+ if (mubi4_test_false_strict(calib_rdy[BaseIdx])) begin
+ hw2reg.measure_ctrl_regwen.de = 1'b1;
+ hw2reg.measure_ctrl_regwen.d = 1'b1;
+ end
+ end
+
+ clkmgr_meas_chk #(
+ .Cnt(480),
+ .RefCnt(1)
+ ) u_audio_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_audio_i),
+ .rst_src_ni(rst_audio_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_audio_en & mubi4_test_true_loose(mubi4_t'(reg2hw.audio_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.audio_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.audio_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.audio_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.audio_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.audio_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkAudioIdx]),
+ .meas_err_o(hw2reg.recov_err_code.audio_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.audio_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.audio_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.audio_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(960),
+ .RefCnt(1)
+ ) u_io_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_io_i),
+ .rst_src_ni(rst_io_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_io_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.io_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.io_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.io_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.io_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkIoIdx]),
+ .meas_err_o(hw2reg.recov_err_code.io_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.io_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.io_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.io_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(480),
+ .RefCnt(1)
+ ) u_io_div2_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_io_div2_i),
+ .rst_src_ni(rst_io_div2_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_io_div2_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div2_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.io_div2_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.io_div2_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div2_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.io_div2_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.io_div2_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkIoDiv2Idx]),
+ .meas_err_o(hw2reg.recov_err_code.io_div2_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.io_div2_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.io_div2_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.io_div2_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(240),
+ .RefCnt(1)
+ ) u_io_div4_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_io_div4_i),
+ .rst_src_ni(rst_io_div4_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_io_div4_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div4_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div4_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.io_div4_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.io_div4_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkIoDiv4Idx]),
+ .meas_err_o(hw2reg.recov_err_code.io_div4_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.io_div4_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.io_div4_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.io_div4_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(960),
+ .RefCnt(1)
+ ) u_main_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_main_i),
+ .rst_src_ni(rst_main_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_main_en & mubi4_test_true_loose(mubi4_t'(reg2hw.main_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.main_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.main_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.main_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.main_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.main_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkMainIdx]),
+ .meas_err_o(hw2reg.recov_err_code.main_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.main_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.main_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.main_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(960),
+ .RefCnt(1)
+ ) u_ml_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_ml_i),
+ .rst_src_ni(rst_ml_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_ml_en & mubi4_test_true_loose(mubi4_t'(reg2hw.ml_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.ml_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.ml_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.ml_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.ml_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.ml_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkMlIdx]),
+ .meas_err_o(hw2reg.recov_err_code.ml_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.ml_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.ml_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.ml_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(960),
+ .RefCnt(1)
+ ) u_smc_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_smc_i),
+ .rst_src_ni(rst_smc_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_smc_en & mubi4_test_true_loose(mubi4_t'(reg2hw.smc_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.smc_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.smc_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.smc_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.smc_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.smc_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkSmcIdx]),
+ .meas_err_o(hw2reg.recov_err_code.smc_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.smc_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.smc_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.smc_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(480),
+ .RefCnt(1)
+ ) u_usb_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_usb_i),
+ .rst_src_ni(rst_usb_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_usb_en & mubi4_test_true_loose(mubi4_t'(reg2hw.usb_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.usb_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.usb_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.usb_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.usb_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.usb_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkUsbIdx]),
+ .meas_err_o(hw2reg.recov_err_code.usb_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.usb_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.usb_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.usb_timeout_err.d = 1'b1;
+
+
+ clkmgr_meas_chk #(
+ .Cnt(960),
+ .RefCnt(1)
+ ) u_video_meas (
+ .clk_i,
+ .rst_ni,
+ .clk_src_i(clk_video_i),
+ .rst_src_ni(rst_video_ni),
+ .clk_ref_i(clk_aon_i),
+ .rst_ref_ni(rst_aon_ni),
+ // signals on source domain
+ .src_en_i(clk_video_en & mubi4_test_true_loose(mubi4_t'(reg2hw.video_meas_ctrl_en))),
+ .src_max_cnt_i(reg2hw.video_meas_ctrl_shadowed.hi.q),
+ .src_min_cnt_i(reg2hw.video_meas_ctrl_shadowed.lo.q),
+ .src_cfg_meas_en_i(mubi4_t'(reg2hw.video_meas_ctrl_en.q)),
+ .src_cfg_meas_en_valid_o(hw2reg.video_meas_ctrl_en.de),
+ .src_cfg_meas_en_o(hw2reg.video_meas_ctrl_en.d),
+ // signals on local clock domain
+ .calib_rdy_i(calib_rdy[ClkVideoIdx]),
+ .meas_err_o(hw2reg.recov_err_code.video_measure_err.de),
+ .timeout_err_o(hw2reg.recov_err_code.video_timeout_err.de)
+ );
+
+ assign hw2reg.recov_err_code.video_measure_err.d = 1'b1;
+ assign hw2reg.recov_err_code.video_timeout_err.d = 1'b1;
+
+
+ ////////////////////////////////////////////////////
+ // Clocks with only root gate
+ ////////////////////////////////////////////////////
+ assign clocks_o.clk_io_div4_infra = clk_io_div4_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_div4_infra (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_div4_infra)
+ );
+ assign clocks_o.clk_main_infra = clk_main_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_main_infra (
+ .clk_i(clk_main_i),
+ .rst_ni(rst_main_ni),
+ .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.main_infra)
+ );
+ assign clocks_o.clk_smc_infra = clk_smc_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_smc_infra (
+ .clk_i(clk_smc_i),
+ .rst_ni(rst_smc_ni),
+ .mubi_i(((clk_smc_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.smc_infra)
+ );
+ assign clocks_o.clk_usb_infra = clk_usb_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_usb_infra (
+ .clk_i(clk_usb_i),
+ .rst_ni(rst_usb_ni),
+ .mubi_i(((clk_usb_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.usb_infra)
+ );
+ assign clocks_o.clk_io_infra = clk_io_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_infra (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .mubi_i(((clk_io_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_infra)
+ );
+ assign clocks_o.clk_ml_infra = clk_ml_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_ml_infra (
+ .clk_i(clk_ml_i),
+ .rst_ni(rst_ml_ni),
+ .mubi_i(((clk_ml_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.ml_infra)
+ );
+ assign clocks_o.clk_video_infra = clk_video_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_video_infra (
+ .clk_i(clk_video_i),
+ .rst_ni(rst_video_ni),
+ .mubi_i(((clk_video_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.video_infra)
+ );
+ assign clocks_o.clk_audio_infra = clk_audio_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_audio_infra (
+ .clk_i(clk_audio_i),
+ .rst_ni(rst_audio_ni),
+ .mubi_i(((clk_audio_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.audio_infra)
+ );
+ assign clocks_o.clk_io_div4_secure = clk_io_div4_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_div4_secure (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_div4_secure)
+ );
+ assign clocks_o.clk_main_secure = clk_main_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_main_secure (
+ .clk_i(clk_main_i),
+ .rst_ni(rst_main_ni),
+ .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.main_secure)
+ );
+ assign clocks_o.clk_smc_secure = clk_smc_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_smc_secure (
+ .clk_i(clk_smc_i),
+ .rst_ni(rst_smc_ni),
+ .mubi_i(((clk_smc_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.smc_secure)
+ );
+ assign clocks_o.clk_io_div4_timers = clk_io_div4_root;
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_div4_timers (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_div4_timers)
+ );
+
+ ////////////////////////////////////////////////////
+ // Software direct control group
+ ////////////////////////////////////////////////////
+
+ logic clk_io_div4_peri_sw_en;
+ logic clk_io_div2_peri_sw_en;
+ logic clk_io_peri_sw_en;
+ logic clk_usb_peri_sw_en;
+ logic clk_video_peri_sw_en;
+ logic clk_ml_peri_sw_en;
+ logic clk_audio_peri_sw_en;
+ logic clk_smc_peri_sw_en;
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_io_div4_peri_sw_en_sync (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .d_i(reg2hw.clk_enables.clk_io_div4_peri_en.q),
+ .q_o(clk_io_div4_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_io_div4_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_io_div4_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_io_div4_peri_scanmode)
+ );
+
+ logic clk_io_div4_peri_combined_en;
+ assign clk_io_div4_peri_combined_en = clk_io_div4_peri_sw_en & clk_io_div4_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_io_div4_peri_cg (
+ .clk_i(clk_io_div4_i),
+ .en_i(clk_io_div4_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_io_div4_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_div4_peri (
+ .clk_i(clk_io_div4_i),
+ .rst_ni(rst_io_div4_ni),
+ .mubi_i(((clk_io_div4_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_div4_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_io_div2_peri_sw_en_sync (
+ .clk_i(clk_io_div2_i),
+ .rst_ni(rst_io_div2_ni),
+ .d_i(reg2hw.clk_enables.clk_io_div2_peri_en.q),
+ .q_o(clk_io_div2_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_io_div2_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_io_div2_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_io_div2_peri_scanmode)
+ );
+
+ logic clk_io_div2_peri_combined_en;
+ assign clk_io_div2_peri_combined_en = clk_io_div2_peri_sw_en & clk_io_div2_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_io_div2_peri_cg (
+ .clk_i(clk_io_div2_i),
+ .en_i(clk_io_div2_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_io_div2_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_div2_peri (
+ .clk_i(clk_io_div2_i),
+ .rst_ni(rst_io_div2_ni),
+ .mubi_i(((clk_io_div2_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_div2_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_io_peri_sw_en_sync (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .d_i(reg2hw.clk_enables.clk_io_peri_en.q),
+ .q_o(clk_io_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_io_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_io_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_io_peri_scanmode)
+ );
+
+ logic clk_io_peri_combined_en;
+ assign clk_io_peri_combined_en = clk_io_peri_sw_en & clk_io_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_io_peri_cg (
+ .clk_i(clk_io_i),
+ .en_i(clk_io_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_io_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_io_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_io_peri (
+ .clk_i(clk_io_i),
+ .rst_ni(rst_io_ni),
+ .mubi_i(((clk_io_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.io_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_usb_peri_sw_en_sync (
+ .clk_i(clk_usb_i),
+ .rst_ni(rst_usb_ni),
+ .d_i(reg2hw.clk_enables.clk_usb_peri_en.q),
+ .q_o(clk_usb_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_usb_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_usb_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_usb_peri_scanmode)
+ );
+
+ logic clk_usb_peri_combined_en;
+ assign clk_usb_peri_combined_en = clk_usb_peri_sw_en & clk_usb_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_usb_peri_cg (
+ .clk_i(clk_usb_i),
+ .en_i(clk_usb_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_usb_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_usb_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_usb_peri (
+ .clk_i(clk_usb_i),
+ .rst_ni(rst_usb_ni),
+ .mubi_i(((clk_usb_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.usb_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_video_peri_sw_en_sync (
+ .clk_i(clk_video_i),
+ .rst_ni(rst_video_ni),
+ .d_i(reg2hw.clk_enables.clk_video_peri_en.q),
+ .q_o(clk_video_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_video_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_video_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_video_peri_scanmode)
+ );
+
+ logic clk_video_peri_combined_en;
+ assign clk_video_peri_combined_en = clk_video_peri_sw_en & clk_video_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_video_peri_cg (
+ .clk_i(clk_video_i),
+ .en_i(clk_video_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_video_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_video_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_video_peri (
+ .clk_i(clk_video_i),
+ .rst_ni(rst_video_ni),
+ .mubi_i(((clk_video_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.video_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_ml_peri_sw_en_sync (
+ .clk_i(clk_ml_i),
+ .rst_ni(rst_ml_ni),
+ .d_i(reg2hw.clk_enables.clk_ml_peri_en.q),
+ .q_o(clk_ml_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_ml_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_ml_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_ml_peri_scanmode)
+ );
+
+ logic clk_ml_peri_combined_en;
+ assign clk_ml_peri_combined_en = clk_ml_peri_sw_en & clk_ml_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_ml_peri_cg (
+ .clk_i(clk_ml_i),
+ .en_i(clk_ml_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_ml_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_ml_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_ml_peri (
+ .clk_i(clk_ml_i),
+ .rst_ni(rst_ml_ni),
+ .mubi_i(((clk_ml_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.ml_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_audio_peri_sw_en_sync (
+ .clk_i(clk_audio_i),
+ .rst_ni(rst_audio_ni),
+ .d_i(reg2hw.clk_enables.clk_audio_peri_en.q),
+ .q_o(clk_audio_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_audio_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_audio_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_audio_peri_scanmode)
+ );
+
+ logic clk_audio_peri_combined_en;
+ assign clk_audio_peri_combined_en = clk_audio_peri_sw_en & clk_audio_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_audio_peri_cg (
+ .clk_i(clk_audio_i),
+ .en_i(clk_audio_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_audio_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_audio_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_audio_peri (
+ .clk_i(clk_audio_i),
+ .rst_ni(rst_audio_ni),
+ .mubi_i(((clk_audio_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.audio_peri)
+ );
+
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_clk_smc_peri_sw_en_sync (
+ .clk_i(clk_smc_i),
+ .rst_ni(rst_smc_ni),
+ .d_i(reg2hw.clk_enables.clk_smc_peri_en.q),
+ .q_o(clk_smc_peri_sw_en)
+ );
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] clk_smc_peri_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_clk_smc_peri_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(clk_smc_peri_scanmode)
+ );
+
+ logic clk_smc_peri_combined_en;
+ assign clk_smc_peri_combined_en = clk_smc_peri_sw_en & clk_smc_en;
+ prim_clock_gating #(
+ .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
+ ) u_clk_smc_peri_cg (
+ .clk_i(clk_smc_i),
+ .en_i(clk_smc_peri_combined_en),
+ .test_en_i(mubi4_test_true_strict(clk_smc_peri_scanmode[0])),
+ .clk_o(clocks_o.clk_smc_peri)
+ );
+
+ // clock gated indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender_clk_smc_peri (
+ .clk_i(clk_smc_i),
+ .rst_ni(rst_smc_ni),
+ .mubi_i(((clk_smc_peri_combined_en) ? MuBi4False : MuBi4True)),
+ .mubi_o(cg_en_o.smc_peri)
+ );
+
+
+ ////////////////////////////////////////////////////
+ // Software hint group
+ // The idle hint feedback is assumed to be synchronous to the
+ // clock target
+ ////////////////////////////////////////////////////
+
+ logic [3:0] idle_cnt_err;
+
+ clkmgr_trans #(
+ .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
+ ) u_clk_main_aes_trans (
+ .clk_i(clk_main_i),
+ .clk_gated_i(clk_main_root),
+ .rst_ni(rst_main_ni),
+ .en_i(clk_main_en),
+ .idle_i(idle_i[HintMainAes]),
+ .sw_hint_i(reg2hw.clk_hints.clk_main_aes_hint.q),
+ .scanmode_i,
+ .alert_cg_en_o(cg_en_o.main_aes),
+ .clk_o(clocks_o.clk_main_aes),
+ .clk_reg_i(clk_i),
+ .rst_reg_ni(rst_ni),
+ .reg_en_o(hw2reg.clk_hints_status.clk_main_aes_val.d),
+ .reg_cnt_err_o(idle_cnt_err[HintMainAes])
+ );
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
+ ClkMainAesCountCheck_A,
+ u_clk_main_aes_trans.u_idle_cnt,
+ alert_tx_o[1])
+
+ clkmgr_trans #(
+ .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
+ ) u_clk_main_hmac_trans (
+ .clk_i(clk_main_i),
+ .clk_gated_i(clk_main_root),
+ .rst_ni(rst_main_ni),
+ .en_i(clk_main_en),
+ .idle_i(idle_i[HintMainHmac]),
+ .sw_hint_i(reg2hw.clk_hints.clk_main_hmac_hint.q),
+ .scanmode_i,
+ .alert_cg_en_o(cg_en_o.main_hmac),
+ .clk_o(clocks_o.clk_main_hmac),
+ .clk_reg_i(clk_i),
+ .rst_reg_ni(rst_ni),
+ .reg_en_o(hw2reg.clk_hints_status.clk_main_hmac_val.d),
+ .reg_cnt_err_o(idle_cnt_err[HintMainHmac])
+ );
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
+ ClkMainHmacCountCheck_A,
+ u_clk_main_hmac_trans.u_idle_cnt,
+ alert_tx_o[1])
+
+ clkmgr_trans #(
+ .FpgaBufGlobal(1'b1) // KMAC is getting too big for a single clock region.
+ ) u_clk_main_kmac_trans (
+ .clk_i(clk_main_i),
+ .clk_gated_i(clk_main_root),
+ .rst_ni(rst_main_ni),
+ .en_i(clk_main_en),
+ .idle_i(idle_i[HintMainKmac]),
+ .sw_hint_i(reg2hw.clk_hints.clk_main_kmac_hint.q),
+ .scanmode_i,
+ .alert_cg_en_o(cg_en_o.main_kmac),
+ .clk_o(clocks_o.clk_main_kmac),
+ .clk_reg_i(clk_i),
+ .rst_reg_ni(rst_ni),
+ .reg_en_o(hw2reg.clk_hints_status.clk_main_kmac_val.d),
+ .reg_cnt_err_o(idle_cnt_err[HintMainKmac])
+ );
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
+ ClkMainKmacCountCheck_A,
+ u_clk_main_kmac_trans.u_idle_cnt,
+ alert_tx_o[1])
+
+ clkmgr_trans #(
+ .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
+ ) u_clk_main_otbn_trans (
+ .clk_i(clk_main_i),
+ .clk_gated_i(clk_main_root),
+ .rst_ni(rst_main_ni),
+ .en_i(clk_main_en),
+ .idle_i(idle_i[HintMainOtbn]),
+ .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q),
+ .scanmode_i,
+ .alert_cg_en_o(cg_en_o.main_otbn),
+ .clk_o(clocks_o.clk_main_otbn),
+ .clk_reg_i(clk_i),
+ .rst_reg_ni(rst_ni),
+ .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d),
+ .reg_cnt_err_o(idle_cnt_err[HintMainOtbn])
+ );
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
+ ClkMainOtbnCountCheck_A,
+ u_clk_main_otbn_trans.u_idle_cnt,
+ alert_tx_o[1])
+ assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1;
+ assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err;
+
+ // state readback
+ assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1;
+ assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1;
+ assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1;
+ assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1;
+
+ // SEC_CM: JITTER.CONFIG.MUBI
+ assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q);
+
+ ////////////////////////////////////////////////////
+ // Exported clocks
+ ////////////////////////////////////////////////////
+
+
+ ////////////////////////////////////////////////////
+ // Assertions
+ ////////////////////////////////////////////////////
+
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o)
+ `ASSERT_KNOWN(PwrMgrKnownO_A, pwr_o)
+ `ASSERT_KNOWN(AllClkBypReqKnownO_A, all_clk_byp_req_o)
+ `ASSERT_KNOWN(IoClkBypReqKnownO_A, io_clk_byp_req_o)
+ `ASSERT_KNOWN(LcCtrlClkBypAckKnownO_A, lc_clk_byp_ack_o)
+ `ASSERT_KNOWN(JitterEnableKnownO_A, jitter_en_o)
+ `ASSERT_KNOWN(ClocksKownO_A, clocks_o)
+ `ASSERT_KNOWN(CgEnKnownO_A, cg_en_o)
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[1])
+endmodule // clkmgr
diff --git a/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
new file mode 100644
index 0000000..501f2a5
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -0,0 +1,125 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+package clkmgr_pkg;
+
+ typedef enum int {
+ HintMainAes = 0,
+ HintMainHmac = 1,
+ HintMainKmac = 2,
+ HintMainOtbn = 3
+ } hint_names_e;
+
+ // clocks generated and broadcast
+ typedef struct packed {
+ logic clk_io_div4_powerup;
+ logic clk_aon_powerup;
+ logic clk_main_powerup;
+ logic clk_io_powerup;
+ logic clk_usb_powerup;
+ logic clk_io_div2_powerup;
+ logic clk_smc_powerup;
+ logic clk_ml_powerup;
+ logic clk_video_powerup;
+ logic clk_audio_powerup;
+ logic clk_aon_secure;
+ logic clk_aon_peri;
+ logic clk_aon_timers;
+ logic clk_main_aes;
+ logic clk_main_hmac;
+ logic clk_main_kmac;
+ logic clk_main_otbn;
+ logic clk_io_div4_infra;
+ logic clk_main_infra;
+ logic clk_smc_infra;
+ logic clk_usb_infra;
+ logic clk_io_infra;
+ logic clk_ml_infra;
+ logic clk_video_infra;
+ logic clk_audio_infra;
+ logic clk_io_div4_secure;
+ logic clk_main_secure;
+ logic clk_smc_secure;
+ logic clk_io_div4_timers;
+ logic clk_io_div4_peri;
+ logic clk_io_div2_peri;
+ logic clk_io_peri;
+ logic clk_usb_peri;
+ logic clk_video_peri;
+ logic clk_ml_peri;
+ logic clk_audio_peri;
+ logic clk_smc_peri;
+ } clkmgr_out_t;
+
+ // clock gating indication for alert handler
+ typedef struct packed {
+ prim_mubi_pkg::mubi4_t io_div4_powerup;
+ prim_mubi_pkg::mubi4_t aon_powerup;
+ prim_mubi_pkg::mubi4_t main_powerup;
+ prim_mubi_pkg::mubi4_t io_powerup;
+ prim_mubi_pkg::mubi4_t usb_powerup;
+ prim_mubi_pkg::mubi4_t io_div2_powerup;
+ prim_mubi_pkg::mubi4_t smc_powerup;
+ prim_mubi_pkg::mubi4_t ml_powerup;
+ prim_mubi_pkg::mubi4_t video_powerup;
+ prim_mubi_pkg::mubi4_t audio_powerup;
+ prim_mubi_pkg::mubi4_t aon_secure;
+ prim_mubi_pkg::mubi4_t aon_peri;
+ prim_mubi_pkg::mubi4_t aon_timers;
+ prim_mubi_pkg::mubi4_t main_aes;
+ prim_mubi_pkg::mubi4_t main_hmac;
+ prim_mubi_pkg::mubi4_t main_kmac;
+ prim_mubi_pkg::mubi4_t main_otbn;
+ prim_mubi_pkg::mubi4_t io_div4_infra;
+ prim_mubi_pkg::mubi4_t main_infra;
+ prim_mubi_pkg::mubi4_t smc_infra;
+ prim_mubi_pkg::mubi4_t usb_infra;
+ prim_mubi_pkg::mubi4_t io_infra;
+ prim_mubi_pkg::mubi4_t ml_infra;
+ prim_mubi_pkg::mubi4_t video_infra;
+ prim_mubi_pkg::mubi4_t audio_infra;
+ prim_mubi_pkg::mubi4_t io_div4_secure;
+ prim_mubi_pkg::mubi4_t main_secure;
+ prim_mubi_pkg::mubi4_t smc_secure;
+ prim_mubi_pkg::mubi4_t io_div4_timers;
+ prim_mubi_pkg::mubi4_t io_div4_peri;
+ prim_mubi_pkg::mubi4_t io_div2_peri;
+ prim_mubi_pkg::mubi4_t io_peri;
+ prim_mubi_pkg::mubi4_t usb_peri;
+ prim_mubi_pkg::mubi4_t video_peri;
+ prim_mubi_pkg::mubi4_t ml_peri;
+ prim_mubi_pkg::mubi4_t audio_peri;
+ prim_mubi_pkg::mubi4_t smc_peri;
+ } clkmgr_cg_en_t;
+
+ parameter int NumOutputClk = 37;
+
+
+ typedef struct packed {
+ logic [4-1:0] idle;
+ } clk_hint_status_t;
+
+ parameter clk_hint_status_t CLK_HINT_STATUS_DEFAULT = '{
+ idle: {4{1'b1}}
+ };
+
+endpackage // clkmgr_pkg
diff --git a/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
new file mode 100644
index 0000000..b8153f2
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
@@ -0,0 +1,542 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package clkmgr_reg_pkg;
+
+ // Param list
+ parameter int NumGroups = 7;
+ parameter int NumSwGateableClocks = 8;
+ parameter int NumHintableClocks = 4;
+ parameter int NumAlerts = 2;
+
+ // Address widths within the block
+ parameter int BlockAw = 7;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_fault;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_fault;
+ } clkmgr_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } sel;
+ struct packed {
+ logic [3:0] q;
+ } hi_speed_sel;
+ } clkmgr_reg2hw_extclk_ctrl_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_jitter_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } clk_io_div4_peri_en;
+ struct packed {
+ logic q;
+ } clk_io_div2_peri_en;
+ struct packed {
+ logic q;
+ } clk_io_peri_en;
+ struct packed {
+ logic q;
+ } clk_usb_peri_en;
+ struct packed {
+ logic q;
+ } clk_video_peri_en;
+ struct packed {
+ logic q;
+ } clk_ml_peri_en;
+ struct packed {
+ logic q;
+ } clk_audio_peri_en;
+ struct packed {
+ logic q;
+ } clk_smc_peri_en;
+ } clkmgr_reg2hw_clk_enables_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } clk_main_aes_hint;
+ struct packed {
+ logic q;
+ } clk_main_hmac_hint;
+ struct packed {
+ logic q;
+ } clk_main_kmac_hint;
+ struct packed {
+ logic q;
+ } clk_main_otbn_hint;
+ } clkmgr_reg2hw_clk_hints_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } clkmgr_reg2hw_measure_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_audio_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [8:0] q;
+ } hi;
+ struct packed {
+ logic [8:0] q;
+ } lo;
+ } clkmgr_reg2hw_audio_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_io_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } hi;
+ struct packed {
+ logic [9:0] q;
+ } lo;
+ } clkmgr_reg2hw_io_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_io_div2_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [8:0] q;
+ } hi;
+ struct packed {
+ logic [8:0] q;
+ } lo;
+ } clkmgr_reg2hw_io_div2_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } hi;
+ struct packed {
+ logic [7:0] q;
+ } lo;
+ } clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_main_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } hi;
+ struct packed {
+ logic [9:0] q;
+ } lo;
+ } clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_ml_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } hi;
+ struct packed {
+ logic [9:0] q;
+ } lo;
+ } clkmgr_reg2hw_ml_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_smc_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } hi;
+ struct packed {
+ logic [9:0] q;
+ } lo;
+ } clkmgr_reg2hw_smc_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_usb_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [8:0] q;
+ } hi;
+ struct packed {
+ logic [8:0] q;
+ } lo;
+ } clkmgr_reg2hw_usb_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } clkmgr_reg2hw_video_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [9:0] q;
+ } hi;
+ struct packed {
+ logic [9:0] q;
+ } lo;
+ } clkmgr_reg2hw_video_meas_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } reg_intg;
+ struct packed {
+ logic q;
+ } idle_cnt;
+ struct packed {
+ logic q;
+ } shadow_storage_err;
+ } clkmgr_reg2hw_fatal_err_code_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ } clkmgr_hw2reg_extclk_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } clk_main_aes_val;
+ struct packed {
+ logic d;
+ logic de;
+ } clk_main_hmac_val;
+ struct packed {
+ logic d;
+ logic de;
+ } clk_main_kmac_val;
+ struct packed {
+ logic d;
+ logic de;
+ } clk_main_otbn_val;
+ } clkmgr_hw2reg_clk_hints_status_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } clkmgr_hw2reg_measure_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_audio_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_io_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_io_div2_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_main_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_ml_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_smc_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_usb_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } clkmgr_hw2reg_video_meas_ctrl_en_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } shadow_update_err;
+ struct packed {
+ logic d;
+ logic de;
+ } audio_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_div2_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_div4_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } main_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } ml_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } smc_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } usb_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } video_measure_err;
+ struct packed {
+ logic d;
+ logic de;
+ } audio_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_div2_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } io_div4_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } main_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } ml_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } smc_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } usb_timeout_err;
+ struct packed {
+ logic d;
+ logic de;
+ } video_timeout_err;
+ } clkmgr_hw2reg_recov_err_code_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg;
+ struct packed {
+ logic d;
+ logic de;
+ } idle_cnt;
+ struct packed {
+ logic d;
+ logic de;
+ } shadow_storage_err;
+ } clkmgr_hw2reg_fatal_err_code_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ clkmgr_reg2hw_alert_test_reg_t alert_test; // [237:234]
+ clkmgr_reg2hw_extclk_ctrl_reg_t extclk_ctrl; // [233:226]
+ clkmgr_reg2hw_jitter_enable_reg_t jitter_enable; // [225:222]
+ clkmgr_reg2hw_clk_enables_reg_t clk_enables; // [221:214]
+ clkmgr_reg2hw_clk_hints_reg_t clk_hints; // [213:210]
+ clkmgr_reg2hw_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [209:209]
+ clkmgr_reg2hw_audio_meas_ctrl_en_reg_t audio_meas_ctrl_en; // [208:205]
+ clkmgr_reg2hw_audio_meas_ctrl_shadowed_reg_t audio_meas_ctrl_shadowed; // [204:187]
+ clkmgr_reg2hw_io_meas_ctrl_en_reg_t io_meas_ctrl_en; // [186:183]
+ clkmgr_reg2hw_io_meas_ctrl_shadowed_reg_t io_meas_ctrl_shadowed; // [182:163]
+ clkmgr_reg2hw_io_div2_meas_ctrl_en_reg_t io_div2_meas_ctrl_en; // [162:159]
+ clkmgr_reg2hw_io_div2_meas_ctrl_shadowed_reg_t io_div2_meas_ctrl_shadowed; // [158:141]
+ clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [140:137]
+ clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t io_div4_meas_ctrl_shadowed; // [136:121]
+ clkmgr_reg2hw_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [120:117]
+ clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t main_meas_ctrl_shadowed; // [116:97]
+ clkmgr_reg2hw_ml_meas_ctrl_en_reg_t ml_meas_ctrl_en; // [96:93]
+ clkmgr_reg2hw_ml_meas_ctrl_shadowed_reg_t ml_meas_ctrl_shadowed; // [92:73]
+ clkmgr_reg2hw_smc_meas_ctrl_en_reg_t smc_meas_ctrl_en; // [72:69]
+ clkmgr_reg2hw_smc_meas_ctrl_shadowed_reg_t smc_meas_ctrl_shadowed; // [68:49]
+ clkmgr_reg2hw_usb_meas_ctrl_en_reg_t usb_meas_ctrl_en; // [48:45]
+ clkmgr_reg2hw_usb_meas_ctrl_shadowed_reg_t usb_meas_ctrl_shadowed; // [44:27]
+ clkmgr_reg2hw_video_meas_ctrl_en_reg_t video_meas_ctrl_en; // [26:23]
+ clkmgr_reg2hw_video_meas_ctrl_shadowed_reg_t video_meas_ctrl_shadowed; // [22:3]
+ clkmgr_reg2hw_fatal_err_code_reg_t fatal_err_code; // [2:0]
+ } clkmgr_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ clkmgr_hw2reg_extclk_status_reg_t extclk_status; // [102:99]
+ clkmgr_hw2reg_clk_hints_status_reg_t clk_hints_status; // [98:91]
+ clkmgr_hw2reg_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [90:89]
+ clkmgr_hw2reg_audio_meas_ctrl_en_reg_t audio_meas_ctrl_en; // [88:84]
+ clkmgr_hw2reg_io_meas_ctrl_en_reg_t io_meas_ctrl_en; // [83:79]
+ clkmgr_hw2reg_io_div2_meas_ctrl_en_reg_t io_div2_meas_ctrl_en; // [78:74]
+ clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [73:69]
+ clkmgr_hw2reg_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [68:64]
+ clkmgr_hw2reg_ml_meas_ctrl_en_reg_t ml_meas_ctrl_en; // [63:59]
+ clkmgr_hw2reg_smc_meas_ctrl_en_reg_t smc_meas_ctrl_en; // [58:54]
+ clkmgr_hw2reg_usb_meas_ctrl_en_reg_t usb_meas_ctrl_en; // [53:49]
+ clkmgr_hw2reg_video_meas_ctrl_en_reg_t video_meas_ctrl_en; // [48:44]
+ clkmgr_hw2reg_recov_err_code_reg_t recov_err_code; // [43:6]
+ clkmgr_hw2reg_fatal_err_code_reg_t fatal_err_code; // [5:0]
+ } clkmgr_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 7'h 0;
+ parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 7'h 4;
+ parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 7'h 8;
+ parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_STATUS_OFFSET = 7'h c;
+ parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 7'h 10;
+ parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 7'h 14;
+ parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 7'h 18;
+ parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 7'h 1c;
+ parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 7'h 20;
+ parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 7'h 24;
+ parameter logic [BlockAw-1:0] CLKMGR_AUDIO_MEAS_CTRL_EN_OFFSET = 7'h 28;
+ parameter logic [BlockAw-1:0] CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_OFFSET = 7'h 2c;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_EN_OFFSET = 7'h 30;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET = 7'h 34;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET = 7'h 38;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET = 7'h 3c;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET = 7'h 40;
+ parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 7'h 44;
+ parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET = 7'h 48;
+ parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 7'h 4c;
+ parameter logic [BlockAw-1:0] CLKMGR_ML_MEAS_CTRL_EN_OFFSET = 7'h 50;
+ parameter logic [BlockAw-1:0] CLKMGR_ML_MEAS_CTRL_SHADOWED_OFFSET = 7'h 54;
+ parameter logic [BlockAw-1:0] CLKMGR_SMC_MEAS_CTRL_EN_OFFSET = 7'h 58;
+ parameter logic [BlockAw-1:0] CLKMGR_SMC_MEAS_CTRL_SHADOWED_OFFSET = 7'h 5c;
+ parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_EN_OFFSET = 7'h 60;
+ parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 7'h 64;
+ parameter logic [BlockAw-1:0] CLKMGR_VIDEO_MEAS_CTRL_EN_OFFSET = 7'h 68;
+ parameter logic [BlockAw-1:0] CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_OFFSET = 7'h 6c;
+ parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 7'h 70;
+ parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 7'h 74;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [1:0] CLKMGR_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] CLKMGR_ALERT_TEST_RECOV_FAULT_RESVAL = 1'h 0;
+ parameter logic [0:0] CLKMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [3:0] CLKMGR_EXTCLK_STATUS_RESVAL = 4'h 9;
+ parameter logic [3:0] CLKMGR_EXTCLK_STATUS_ACK_RESVAL = 4'h 9;
+
+ // Register index
+ typedef enum int {
+ CLKMGR_ALERT_TEST,
+ CLKMGR_EXTCLK_CTRL_REGWEN,
+ CLKMGR_EXTCLK_CTRL,
+ CLKMGR_EXTCLK_STATUS,
+ CLKMGR_JITTER_REGWEN,
+ CLKMGR_JITTER_ENABLE,
+ CLKMGR_CLK_ENABLES,
+ CLKMGR_CLK_HINTS,
+ CLKMGR_CLK_HINTS_STATUS,
+ CLKMGR_MEASURE_CTRL_REGWEN,
+ CLKMGR_AUDIO_MEAS_CTRL_EN,
+ CLKMGR_AUDIO_MEAS_CTRL_SHADOWED,
+ CLKMGR_IO_MEAS_CTRL_EN,
+ CLKMGR_IO_MEAS_CTRL_SHADOWED,
+ CLKMGR_IO_DIV2_MEAS_CTRL_EN,
+ CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED,
+ CLKMGR_IO_DIV4_MEAS_CTRL_EN,
+ CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED,
+ CLKMGR_MAIN_MEAS_CTRL_EN,
+ CLKMGR_MAIN_MEAS_CTRL_SHADOWED,
+ CLKMGR_ML_MEAS_CTRL_EN,
+ CLKMGR_ML_MEAS_CTRL_SHADOWED,
+ CLKMGR_SMC_MEAS_CTRL_EN,
+ CLKMGR_SMC_MEAS_CTRL_SHADOWED,
+ CLKMGR_USB_MEAS_CTRL_EN,
+ CLKMGR_USB_MEAS_CTRL_SHADOWED,
+ CLKMGR_VIDEO_MEAS_CTRL_EN,
+ CLKMGR_VIDEO_MEAS_CTRL_SHADOWED,
+ CLKMGR_RECOV_ERR_CODE,
+ CLKMGR_FATAL_ERR_CODE
+ } clkmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] CLKMGR_PERMIT [30] = '{
+ 4'b 0001, // index[ 0] CLKMGR_ALERT_TEST
+ 4'b 0001, // index[ 1] CLKMGR_EXTCLK_CTRL_REGWEN
+ 4'b 0001, // index[ 2] CLKMGR_EXTCLK_CTRL
+ 4'b 0001, // index[ 3] CLKMGR_EXTCLK_STATUS
+ 4'b 0001, // index[ 4] CLKMGR_JITTER_REGWEN
+ 4'b 0001, // index[ 5] CLKMGR_JITTER_ENABLE
+ 4'b 0001, // index[ 6] CLKMGR_CLK_ENABLES
+ 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS
+ 4'b 0001, // index[ 8] CLKMGR_CLK_HINTS_STATUS
+ 4'b 0001, // index[ 9] CLKMGR_MEASURE_CTRL_REGWEN
+ 4'b 0001, // index[10] CLKMGR_AUDIO_MEAS_CTRL_EN
+ 4'b 0111, // index[11] CLKMGR_AUDIO_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[12] CLKMGR_IO_MEAS_CTRL_EN
+ 4'b 0111, // index[13] CLKMGR_IO_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[14] CLKMGR_IO_DIV2_MEAS_CTRL_EN
+ 4'b 0111, // index[15] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[16] CLKMGR_IO_DIV4_MEAS_CTRL_EN
+ 4'b 0011, // index[17] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[18] CLKMGR_MAIN_MEAS_CTRL_EN
+ 4'b 0111, // index[19] CLKMGR_MAIN_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[20] CLKMGR_ML_MEAS_CTRL_EN
+ 4'b 0111, // index[21] CLKMGR_ML_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[22] CLKMGR_SMC_MEAS_CTRL_EN
+ 4'b 0111, // index[23] CLKMGR_SMC_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[24] CLKMGR_USB_MEAS_CTRL_EN
+ 4'b 0111, // index[25] CLKMGR_USB_MEAS_CTRL_SHADOWED
+ 4'b 0001, // index[26] CLKMGR_VIDEO_MEAS_CTRL_EN
+ 4'b 0111, // index[27] CLKMGR_VIDEO_MEAS_CTRL_SHADOWED
+ 4'b 0111, // index[28] CLKMGR_RECOV_ERR_CODE
+ 4'b 0001 // index[29] CLKMGR_FATAL_ERR_CODE
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
new file mode 100644
index 0000000..d752025
--- /dev/null
+++ b/hw/top_sencha/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -0,0 +1,4279 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module clkmgr_reg_top (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+ input clk_audio_i,
+ input rst_audio_ni,
+ input clk_io_i,
+ input rst_io_ni,
+ input clk_io_div2_i,
+ input rst_io_div2_ni,
+ input clk_io_div4_i,
+ input rst_io_div4_ni,
+ input clk_main_i,
+ input rst_main_ni,
+ input clk_ml_i,
+ input rst_ml_ni,
+ input clk_smc_i,
+ input rst_smc_ni,
+ input clk_usb_i,
+ input rst_usb_ni,
+ input clk_video_i,
+ input rst_video_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write
+ input clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read
+
+ output logic shadowed_storage_err_o,
+ output logic shadowed_update_err_o,
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import clkmgr_reg_pkg::* ;
+
+ localparam int AW = 7;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [29:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(30)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic alert_test_we;
+ logic alert_test_recov_fault_wd;
+ logic alert_test_fatal_fault_wd;
+ logic extclk_ctrl_regwen_we;
+ logic extclk_ctrl_regwen_qs;
+ logic extclk_ctrl_regwen_wd;
+ logic extclk_ctrl_we;
+ logic [3:0] extclk_ctrl_sel_qs;
+ logic [3:0] extclk_ctrl_sel_wd;
+ logic [3:0] extclk_ctrl_hi_speed_sel_qs;
+ logic [3:0] extclk_ctrl_hi_speed_sel_wd;
+ logic extclk_status_re;
+ logic [3:0] extclk_status_qs;
+ logic jitter_regwen_we;
+ logic jitter_regwen_qs;
+ logic jitter_regwen_wd;
+ logic jitter_enable_we;
+ logic [3:0] jitter_enable_qs;
+ logic [3:0] jitter_enable_wd;
+ logic clk_enables_we;
+ logic clk_enables_clk_io_div4_peri_en_qs;
+ logic clk_enables_clk_io_div4_peri_en_wd;
+ logic clk_enables_clk_io_div2_peri_en_qs;
+ logic clk_enables_clk_io_div2_peri_en_wd;
+ logic clk_enables_clk_io_peri_en_qs;
+ logic clk_enables_clk_io_peri_en_wd;
+ logic clk_enables_clk_usb_peri_en_qs;
+ logic clk_enables_clk_usb_peri_en_wd;
+ logic clk_enables_clk_video_peri_en_qs;
+ logic clk_enables_clk_video_peri_en_wd;
+ logic clk_enables_clk_ml_peri_en_qs;
+ logic clk_enables_clk_ml_peri_en_wd;
+ logic clk_enables_clk_audio_peri_en_qs;
+ logic clk_enables_clk_audio_peri_en_wd;
+ logic clk_enables_clk_smc_peri_en_qs;
+ logic clk_enables_clk_smc_peri_en_wd;
+ logic clk_hints_we;
+ logic clk_hints_clk_main_aes_hint_qs;
+ logic clk_hints_clk_main_aes_hint_wd;
+ logic clk_hints_clk_main_hmac_hint_qs;
+ logic clk_hints_clk_main_hmac_hint_wd;
+ logic clk_hints_clk_main_kmac_hint_qs;
+ logic clk_hints_clk_main_kmac_hint_wd;
+ logic clk_hints_clk_main_otbn_hint_qs;
+ logic clk_hints_clk_main_otbn_hint_wd;
+ logic clk_hints_status_clk_main_aes_val_qs;
+ logic clk_hints_status_clk_main_hmac_val_qs;
+ logic clk_hints_status_clk_main_kmac_val_qs;
+ logic clk_hints_status_clk_main_otbn_val_qs;
+ logic measure_ctrl_regwen_we;
+ logic measure_ctrl_regwen_qs;
+ logic measure_ctrl_regwen_wd;
+ logic audio_meas_ctrl_en_we;
+ logic [3:0] audio_meas_ctrl_en_qs;
+ logic audio_meas_ctrl_en_busy;
+ logic audio_meas_ctrl_shadowed_re;
+ logic audio_meas_ctrl_shadowed_we;
+ logic [17:0] audio_meas_ctrl_shadowed_qs;
+ logic audio_meas_ctrl_shadowed_busy;
+ logic audio_meas_ctrl_shadowed_hi_storage_err;
+ logic audio_meas_ctrl_shadowed_hi_update_err;
+ logic audio_meas_ctrl_shadowed_lo_storage_err;
+ logic audio_meas_ctrl_shadowed_lo_update_err;
+ logic io_meas_ctrl_en_we;
+ logic [3:0] io_meas_ctrl_en_qs;
+ logic io_meas_ctrl_en_busy;
+ logic io_meas_ctrl_shadowed_re;
+ logic io_meas_ctrl_shadowed_we;
+ logic [19:0] io_meas_ctrl_shadowed_qs;
+ logic io_meas_ctrl_shadowed_busy;
+ logic io_meas_ctrl_shadowed_hi_storage_err;
+ logic io_meas_ctrl_shadowed_hi_update_err;
+ logic io_meas_ctrl_shadowed_lo_storage_err;
+ logic io_meas_ctrl_shadowed_lo_update_err;
+ logic io_div2_meas_ctrl_en_we;
+ logic [3:0] io_div2_meas_ctrl_en_qs;
+ logic io_div2_meas_ctrl_en_busy;
+ logic io_div2_meas_ctrl_shadowed_re;
+ logic io_div2_meas_ctrl_shadowed_we;
+ logic [17:0] io_div2_meas_ctrl_shadowed_qs;
+ logic io_div2_meas_ctrl_shadowed_busy;
+ logic io_div2_meas_ctrl_shadowed_hi_storage_err;
+ logic io_div2_meas_ctrl_shadowed_hi_update_err;
+ logic io_div2_meas_ctrl_shadowed_lo_storage_err;
+ logic io_div2_meas_ctrl_shadowed_lo_update_err;
+ logic io_div4_meas_ctrl_en_we;
+ logic [3:0] io_div4_meas_ctrl_en_qs;
+ logic io_div4_meas_ctrl_en_busy;
+ logic io_div4_meas_ctrl_shadowed_re;
+ logic io_div4_meas_ctrl_shadowed_we;
+ logic [15:0] io_div4_meas_ctrl_shadowed_qs;
+ logic io_div4_meas_ctrl_shadowed_busy;
+ logic io_div4_meas_ctrl_shadowed_hi_storage_err;
+ logic io_div4_meas_ctrl_shadowed_hi_update_err;
+ logic io_div4_meas_ctrl_shadowed_lo_storage_err;
+ logic io_div4_meas_ctrl_shadowed_lo_update_err;
+ logic main_meas_ctrl_en_we;
+ logic [3:0] main_meas_ctrl_en_qs;
+ logic main_meas_ctrl_en_busy;
+ logic main_meas_ctrl_shadowed_re;
+ logic main_meas_ctrl_shadowed_we;
+ logic [19:0] main_meas_ctrl_shadowed_qs;
+ logic main_meas_ctrl_shadowed_busy;
+ logic main_meas_ctrl_shadowed_hi_storage_err;
+ logic main_meas_ctrl_shadowed_hi_update_err;
+ logic main_meas_ctrl_shadowed_lo_storage_err;
+ logic main_meas_ctrl_shadowed_lo_update_err;
+ logic ml_meas_ctrl_en_we;
+ logic [3:0] ml_meas_ctrl_en_qs;
+ logic ml_meas_ctrl_en_busy;
+ logic ml_meas_ctrl_shadowed_re;
+ logic ml_meas_ctrl_shadowed_we;
+ logic [19:0] ml_meas_ctrl_shadowed_qs;
+ logic ml_meas_ctrl_shadowed_busy;
+ logic ml_meas_ctrl_shadowed_hi_storage_err;
+ logic ml_meas_ctrl_shadowed_hi_update_err;
+ logic ml_meas_ctrl_shadowed_lo_storage_err;
+ logic ml_meas_ctrl_shadowed_lo_update_err;
+ logic smc_meas_ctrl_en_we;
+ logic [3:0] smc_meas_ctrl_en_qs;
+ logic smc_meas_ctrl_en_busy;
+ logic smc_meas_ctrl_shadowed_re;
+ logic smc_meas_ctrl_shadowed_we;
+ logic [19:0] smc_meas_ctrl_shadowed_qs;
+ logic smc_meas_ctrl_shadowed_busy;
+ logic smc_meas_ctrl_shadowed_hi_storage_err;
+ logic smc_meas_ctrl_shadowed_hi_update_err;
+ logic smc_meas_ctrl_shadowed_lo_storage_err;
+ logic smc_meas_ctrl_shadowed_lo_update_err;
+ logic usb_meas_ctrl_en_we;
+ logic [3:0] usb_meas_ctrl_en_qs;
+ logic usb_meas_ctrl_en_busy;
+ logic usb_meas_ctrl_shadowed_re;
+ logic usb_meas_ctrl_shadowed_we;
+ logic [17:0] usb_meas_ctrl_shadowed_qs;
+ logic usb_meas_ctrl_shadowed_busy;
+ logic usb_meas_ctrl_shadowed_hi_storage_err;
+ logic usb_meas_ctrl_shadowed_hi_update_err;
+ logic usb_meas_ctrl_shadowed_lo_storage_err;
+ logic usb_meas_ctrl_shadowed_lo_update_err;
+ logic video_meas_ctrl_en_we;
+ logic [3:0] video_meas_ctrl_en_qs;
+ logic video_meas_ctrl_en_busy;
+ logic video_meas_ctrl_shadowed_re;
+ logic video_meas_ctrl_shadowed_we;
+ logic [19:0] video_meas_ctrl_shadowed_qs;
+ logic video_meas_ctrl_shadowed_busy;
+ logic video_meas_ctrl_shadowed_hi_storage_err;
+ logic video_meas_ctrl_shadowed_hi_update_err;
+ logic video_meas_ctrl_shadowed_lo_storage_err;
+ logic video_meas_ctrl_shadowed_lo_update_err;
+ logic recov_err_code_we;
+ logic recov_err_code_shadow_update_err_qs;
+ logic recov_err_code_shadow_update_err_wd;
+ logic recov_err_code_audio_measure_err_qs;
+ logic recov_err_code_audio_measure_err_wd;
+ logic recov_err_code_io_measure_err_qs;
+ logic recov_err_code_io_measure_err_wd;
+ logic recov_err_code_io_div2_measure_err_qs;
+ logic recov_err_code_io_div2_measure_err_wd;
+ logic recov_err_code_io_div4_measure_err_qs;
+ logic recov_err_code_io_div4_measure_err_wd;
+ logic recov_err_code_main_measure_err_qs;
+ logic recov_err_code_main_measure_err_wd;
+ logic recov_err_code_ml_measure_err_qs;
+ logic recov_err_code_ml_measure_err_wd;
+ logic recov_err_code_smc_measure_err_qs;
+ logic recov_err_code_smc_measure_err_wd;
+ logic recov_err_code_usb_measure_err_qs;
+ logic recov_err_code_usb_measure_err_wd;
+ logic recov_err_code_video_measure_err_qs;
+ logic recov_err_code_video_measure_err_wd;
+ logic recov_err_code_audio_timeout_err_qs;
+ logic recov_err_code_audio_timeout_err_wd;
+ logic recov_err_code_io_timeout_err_qs;
+ logic recov_err_code_io_timeout_err_wd;
+ logic recov_err_code_io_div2_timeout_err_qs;
+ logic recov_err_code_io_div2_timeout_err_wd;
+ logic recov_err_code_io_div4_timeout_err_qs;
+ logic recov_err_code_io_div4_timeout_err_wd;
+ logic recov_err_code_main_timeout_err_qs;
+ logic recov_err_code_main_timeout_err_wd;
+ logic recov_err_code_ml_timeout_err_qs;
+ logic recov_err_code_ml_timeout_err_wd;
+ logic recov_err_code_smc_timeout_err_qs;
+ logic recov_err_code_smc_timeout_err_wd;
+ logic recov_err_code_usb_timeout_err_qs;
+ logic recov_err_code_usb_timeout_err_wd;
+ logic recov_err_code_video_timeout_err_qs;
+ logic recov_err_code_video_timeout_err_wd;
+ logic fatal_err_code_reg_intg_qs;
+ logic fatal_err_code_idle_cnt_qs;
+ logic fatal_err_code_shadow_storage_err_qs;
+ // Define register CDC handling.
+ // CDC handling is done on a per-reg instead of per-field boundary.
+
+ logic [3:0] audio_audio_meas_ctrl_en_ds_int;
+ logic [3:0] audio_audio_meas_ctrl_en_qs_int;
+ logic [3:0] audio_audio_meas_ctrl_en_ds;
+ logic audio_audio_meas_ctrl_en_qe;
+ logic [3:0] audio_audio_meas_ctrl_en_qs;
+ logic [3:0] audio_audio_meas_ctrl_en_wdata;
+ logic audio_audio_meas_ctrl_en_we;
+ logic unused_audio_audio_meas_ctrl_en_wdata;
+ logic audio_audio_meas_ctrl_en_regwen;
+
+ always_comb begin
+ audio_audio_meas_ctrl_en_qs = 4'h9;
+ audio_audio_meas_ctrl_en_ds = 4'h9;
+ audio_audio_meas_ctrl_en_ds = audio_audio_meas_ctrl_en_ds_int;
+ audio_audio_meas_ctrl_en_qs = audio_audio_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_audio_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_audio_i),
+ .rst_dst_ni (rst_audio_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (audio_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (audio_meas_ctrl_en_busy),
+ .src_qs_o (audio_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (audio_audio_meas_ctrl_en_qe),
+ .dst_ds_i (audio_audio_meas_ctrl_en_ds),
+ .dst_qs_i (audio_audio_meas_ctrl_en_qs),
+ .dst_we_o (audio_audio_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (audio_audio_meas_ctrl_en_regwen),
+ .dst_wd_o (audio_audio_meas_ctrl_en_wdata)
+ );
+ assign unused_audio_audio_meas_ctrl_en_wdata =
+ ^audio_audio_meas_ctrl_en_wdata;
+
+ logic [8:0] audio_audio_meas_ctrl_shadowed_hi_qs_int;
+ logic [8:0] audio_audio_meas_ctrl_shadowed_lo_qs_int;
+ logic [17:0] audio_audio_meas_ctrl_shadowed_qs;
+ logic [17:0] audio_audio_meas_ctrl_shadowed_wdata;
+ logic audio_audio_meas_ctrl_shadowed_we;
+ logic unused_audio_audio_meas_ctrl_shadowed_wdata;
+ logic audio_audio_meas_ctrl_shadowed_re;
+ logic audio_audio_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ audio_audio_meas_ctrl_shadowed_qs = 18'h1ccfa;
+ audio_audio_meas_ctrl_shadowed_qs[8:0] = audio_audio_meas_ctrl_shadowed_hi_qs_int;
+ audio_audio_meas_ctrl_shadowed_qs[17:9] = audio_audio_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(18),
+ .ResetVal(18'h1ccfa),
+ .BitMask(18'h3ffff),
+ .DstWrReq(0)
+ ) u_audio_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_audio_i),
+ .rst_dst_ni (rst_audio_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (audio_meas_ctrl_shadowed_we),
+ .src_re_i (audio_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[17:0]),
+ .src_busy_o (audio_meas_ctrl_shadowed_busy),
+ .src_qs_o (audio_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (audio_audio_meas_ctrl_shadowed_qs),
+ .dst_we_o (audio_audio_meas_ctrl_shadowed_we),
+ .dst_re_o (audio_audio_meas_ctrl_shadowed_re),
+ .dst_regwen_o (audio_audio_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (audio_audio_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_audio_audio_meas_ctrl_shadowed_wdata =
+ ^audio_audio_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] io_io_meas_ctrl_en_ds_int;
+ logic [3:0] io_io_meas_ctrl_en_qs_int;
+ logic [3:0] io_io_meas_ctrl_en_ds;
+ logic io_io_meas_ctrl_en_qe;
+ logic [3:0] io_io_meas_ctrl_en_qs;
+ logic [3:0] io_io_meas_ctrl_en_wdata;
+ logic io_io_meas_ctrl_en_we;
+ logic unused_io_io_meas_ctrl_en_wdata;
+ logic io_io_meas_ctrl_en_regwen;
+
+ always_comb begin
+ io_io_meas_ctrl_en_qs = 4'h9;
+ io_io_meas_ctrl_en_ds = 4'h9;
+ io_io_meas_ctrl_en_ds = io_io_meas_ctrl_en_ds_int;
+ io_io_meas_ctrl_en_qs = io_io_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_io_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_i),
+ .rst_dst_ni (rst_io_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (io_meas_ctrl_en_busy),
+ .src_qs_o (io_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (io_io_meas_ctrl_en_qe),
+ .dst_ds_i (io_io_meas_ctrl_en_ds),
+ .dst_qs_i (io_io_meas_ctrl_en_qs),
+ .dst_we_o (io_io_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (io_io_meas_ctrl_en_regwen),
+ .dst_wd_o (io_io_meas_ctrl_en_wdata)
+ );
+ assign unused_io_io_meas_ctrl_en_wdata =
+ ^io_io_meas_ctrl_en_wdata;
+
+ logic [9:0] io_io_meas_ctrl_shadowed_hi_qs_int;
+ logic [9:0] io_io_meas_ctrl_shadowed_lo_qs_int;
+ logic [19:0] io_io_meas_ctrl_shadowed_qs;
+ logic [19:0] io_io_meas_ctrl_shadowed_wdata;
+ logic io_io_meas_ctrl_shadowed_we;
+ logic unused_io_io_meas_ctrl_shadowed_wdata;
+ logic io_io_meas_ctrl_shadowed_re;
+ logic io_io_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ io_io_meas_ctrl_shadowed_qs = 20'h759ea;
+ io_io_meas_ctrl_shadowed_qs[9:0] = io_io_meas_ctrl_shadowed_hi_qs_int;
+ io_io_meas_ctrl_shadowed_qs[19:10] = io_io_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(20),
+ .ResetVal(20'h759ea),
+ .BitMask(20'hfffff),
+ .DstWrReq(0)
+ ) u_io_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_i),
+ .rst_dst_ni (rst_io_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_meas_ctrl_shadowed_we),
+ .src_re_i (io_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[19:0]),
+ .src_busy_o (io_meas_ctrl_shadowed_busy),
+ .src_qs_o (io_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (io_io_meas_ctrl_shadowed_qs),
+ .dst_we_o (io_io_meas_ctrl_shadowed_we),
+ .dst_re_o (io_io_meas_ctrl_shadowed_re),
+ .dst_regwen_o (io_io_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (io_io_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_io_io_meas_ctrl_shadowed_wdata =
+ ^io_io_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] io_div2_io_div2_meas_ctrl_en_ds_int;
+ logic [3:0] io_div2_io_div2_meas_ctrl_en_qs_int;
+ logic [3:0] io_div2_io_div2_meas_ctrl_en_ds;
+ logic io_div2_io_div2_meas_ctrl_en_qe;
+ logic [3:0] io_div2_io_div2_meas_ctrl_en_qs;
+ logic [3:0] io_div2_io_div2_meas_ctrl_en_wdata;
+ logic io_div2_io_div2_meas_ctrl_en_we;
+ logic unused_io_div2_io_div2_meas_ctrl_en_wdata;
+ logic io_div2_io_div2_meas_ctrl_en_regwen;
+
+ always_comb begin
+ io_div2_io_div2_meas_ctrl_en_qs = 4'h9;
+ io_div2_io_div2_meas_ctrl_en_ds = 4'h9;
+ io_div2_io_div2_meas_ctrl_en_ds = io_div2_io_div2_meas_ctrl_en_ds_int;
+ io_div2_io_div2_meas_ctrl_en_qs = io_div2_io_div2_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_io_div2_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_div2_i),
+ .rst_dst_ni (rst_io_div2_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_div2_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (io_div2_meas_ctrl_en_busy),
+ .src_qs_o (io_div2_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (io_div2_io_div2_meas_ctrl_en_qe),
+ .dst_ds_i (io_div2_io_div2_meas_ctrl_en_ds),
+ .dst_qs_i (io_div2_io_div2_meas_ctrl_en_qs),
+ .dst_we_o (io_div2_io_div2_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (io_div2_io_div2_meas_ctrl_en_regwen),
+ .dst_wd_o (io_div2_io_div2_meas_ctrl_en_wdata)
+ );
+ assign unused_io_div2_io_div2_meas_ctrl_en_wdata =
+ ^io_div2_io_div2_meas_ctrl_en_wdata;
+
+ logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
+ logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
+ logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_qs;
+ logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_wdata;
+ logic io_div2_io_div2_meas_ctrl_shadowed_we;
+ logic unused_io_div2_io_div2_meas_ctrl_shadowed_wdata;
+ logic io_div2_io_div2_meas_ctrl_shadowed_re;
+ logic io_div2_io_div2_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ io_div2_io_div2_meas_ctrl_shadowed_qs = 18'h1ccfa;
+ io_div2_io_div2_meas_ctrl_shadowed_qs[8:0] = io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
+ io_div2_io_div2_meas_ctrl_shadowed_qs[17:9] = io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(18),
+ .ResetVal(18'h1ccfa),
+ .BitMask(18'h3ffff),
+ .DstWrReq(0)
+ ) u_io_div2_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_div2_i),
+ .rst_dst_ni (rst_io_div2_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_div2_meas_ctrl_shadowed_we),
+ .src_re_i (io_div2_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[17:0]),
+ .src_busy_o (io_div2_meas_ctrl_shadowed_busy),
+ .src_qs_o (io_div2_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (io_div2_io_div2_meas_ctrl_shadowed_qs),
+ .dst_we_o (io_div2_io_div2_meas_ctrl_shadowed_we),
+ .dst_re_o (io_div2_io_div2_meas_ctrl_shadowed_re),
+ .dst_regwen_o (io_div2_io_div2_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (io_div2_io_div2_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_io_div2_io_div2_meas_ctrl_shadowed_wdata =
+ ^io_div2_io_div2_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] io_div4_io_div4_meas_ctrl_en_ds_int;
+ logic [3:0] io_div4_io_div4_meas_ctrl_en_qs_int;
+ logic [3:0] io_div4_io_div4_meas_ctrl_en_ds;
+ logic io_div4_io_div4_meas_ctrl_en_qe;
+ logic [3:0] io_div4_io_div4_meas_ctrl_en_qs;
+ logic [3:0] io_div4_io_div4_meas_ctrl_en_wdata;
+ logic io_div4_io_div4_meas_ctrl_en_we;
+ logic unused_io_div4_io_div4_meas_ctrl_en_wdata;
+ logic io_div4_io_div4_meas_ctrl_en_regwen;
+
+ always_comb begin
+ io_div4_io_div4_meas_ctrl_en_qs = 4'h9;
+ io_div4_io_div4_meas_ctrl_en_ds = 4'h9;
+ io_div4_io_div4_meas_ctrl_en_ds = io_div4_io_div4_meas_ctrl_en_ds_int;
+ io_div4_io_div4_meas_ctrl_en_qs = io_div4_io_div4_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_io_div4_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_div4_i),
+ .rst_dst_ni (rst_io_div4_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_div4_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (io_div4_meas_ctrl_en_busy),
+ .src_qs_o (io_div4_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (io_div4_io_div4_meas_ctrl_en_qe),
+ .dst_ds_i (io_div4_io_div4_meas_ctrl_en_ds),
+ .dst_qs_i (io_div4_io_div4_meas_ctrl_en_qs),
+ .dst_we_o (io_div4_io_div4_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (io_div4_io_div4_meas_ctrl_en_regwen),
+ .dst_wd_o (io_div4_io_div4_meas_ctrl_en_wdata)
+ );
+ assign unused_io_div4_io_div4_meas_ctrl_en_wdata =
+ ^io_div4_io_div4_meas_ctrl_en_wdata;
+
+ logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
+ logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
+ logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_qs;
+ logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_wdata;
+ logic io_div4_io_div4_meas_ctrl_shadowed_we;
+ logic unused_io_div4_io_div4_meas_ctrl_shadowed_wdata;
+ logic io_div4_io_div4_meas_ctrl_shadowed_re;
+ logic io_div4_io_div4_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ io_div4_io_div4_meas_ctrl_shadowed_qs = 16'h6e82;
+ io_div4_io_div4_meas_ctrl_shadowed_qs[7:0] = io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
+ io_div4_io_div4_meas_ctrl_shadowed_qs[15:8] = io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(16),
+ .ResetVal(16'h6e82),
+ .BitMask(16'hffff),
+ .DstWrReq(0)
+ ) u_io_div4_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_io_div4_i),
+ .rst_dst_ni (rst_io_div4_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (io_div4_meas_ctrl_shadowed_we),
+ .src_re_i (io_div4_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[15:0]),
+ .src_busy_o (io_div4_meas_ctrl_shadowed_busy),
+ .src_qs_o (io_div4_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (io_div4_io_div4_meas_ctrl_shadowed_qs),
+ .dst_we_o (io_div4_io_div4_meas_ctrl_shadowed_we),
+ .dst_re_o (io_div4_io_div4_meas_ctrl_shadowed_re),
+ .dst_regwen_o (io_div4_io_div4_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (io_div4_io_div4_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_io_div4_io_div4_meas_ctrl_shadowed_wdata =
+ ^io_div4_io_div4_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] main_main_meas_ctrl_en_ds_int;
+ logic [3:0] main_main_meas_ctrl_en_qs_int;
+ logic [3:0] main_main_meas_ctrl_en_ds;
+ logic main_main_meas_ctrl_en_qe;
+ logic [3:0] main_main_meas_ctrl_en_qs;
+ logic [3:0] main_main_meas_ctrl_en_wdata;
+ logic main_main_meas_ctrl_en_we;
+ logic unused_main_main_meas_ctrl_en_wdata;
+ logic main_main_meas_ctrl_en_regwen;
+
+ always_comb begin
+ main_main_meas_ctrl_en_qs = 4'h9;
+ main_main_meas_ctrl_en_ds = 4'h9;
+ main_main_meas_ctrl_en_ds = main_main_meas_ctrl_en_ds_int;
+ main_main_meas_ctrl_en_qs = main_main_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_main_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_main_i),
+ .rst_dst_ni (rst_main_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (main_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (main_meas_ctrl_en_busy),
+ .src_qs_o (main_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (main_main_meas_ctrl_en_qe),
+ .dst_ds_i (main_main_meas_ctrl_en_ds),
+ .dst_qs_i (main_main_meas_ctrl_en_qs),
+ .dst_we_o (main_main_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (main_main_meas_ctrl_en_regwen),
+ .dst_wd_o (main_main_meas_ctrl_en_wdata)
+ );
+ assign unused_main_main_meas_ctrl_en_wdata =
+ ^main_main_meas_ctrl_en_wdata;
+
+ logic [9:0] main_main_meas_ctrl_shadowed_hi_qs_int;
+ logic [9:0] main_main_meas_ctrl_shadowed_lo_qs_int;
+ logic [19:0] main_main_meas_ctrl_shadowed_qs;
+ logic [19:0] main_main_meas_ctrl_shadowed_wdata;
+ logic main_main_meas_ctrl_shadowed_we;
+ logic unused_main_main_meas_ctrl_shadowed_wdata;
+ logic main_main_meas_ctrl_shadowed_re;
+ logic main_main_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ main_main_meas_ctrl_shadowed_qs = 20'h759ea;
+ main_main_meas_ctrl_shadowed_qs[9:0] = main_main_meas_ctrl_shadowed_hi_qs_int;
+ main_main_meas_ctrl_shadowed_qs[19:10] = main_main_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(20),
+ .ResetVal(20'h759ea),
+ .BitMask(20'hfffff),
+ .DstWrReq(0)
+ ) u_main_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_main_i),
+ .rst_dst_ni (rst_main_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (main_meas_ctrl_shadowed_we),
+ .src_re_i (main_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[19:0]),
+ .src_busy_o (main_meas_ctrl_shadowed_busy),
+ .src_qs_o (main_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (main_main_meas_ctrl_shadowed_qs),
+ .dst_we_o (main_main_meas_ctrl_shadowed_we),
+ .dst_re_o (main_main_meas_ctrl_shadowed_re),
+ .dst_regwen_o (main_main_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (main_main_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_main_main_meas_ctrl_shadowed_wdata =
+ ^main_main_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] ml_ml_meas_ctrl_en_ds_int;
+ logic [3:0] ml_ml_meas_ctrl_en_qs_int;
+ logic [3:0] ml_ml_meas_ctrl_en_ds;
+ logic ml_ml_meas_ctrl_en_qe;
+ logic [3:0] ml_ml_meas_ctrl_en_qs;
+ logic [3:0] ml_ml_meas_ctrl_en_wdata;
+ logic ml_ml_meas_ctrl_en_we;
+ logic unused_ml_ml_meas_ctrl_en_wdata;
+ logic ml_ml_meas_ctrl_en_regwen;
+
+ always_comb begin
+ ml_ml_meas_ctrl_en_qs = 4'h9;
+ ml_ml_meas_ctrl_en_ds = 4'h9;
+ ml_ml_meas_ctrl_en_ds = ml_ml_meas_ctrl_en_ds_int;
+ ml_ml_meas_ctrl_en_qs = ml_ml_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_ml_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_ml_i),
+ .rst_dst_ni (rst_ml_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (ml_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (ml_meas_ctrl_en_busy),
+ .src_qs_o (ml_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (ml_ml_meas_ctrl_en_qe),
+ .dst_ds_i (ml_ml_meas_ctrl_en_ds),
+ .dst_qs_i (ml_ml_meas_ctrl_en_qs),
+ .dst_we_o (ml_ml_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (ml_ml_meas_ctrl_en_regwen),
+ .dst_wd_o (ml_ml_meas_ctrl_en_wdata)
+ );
+ assign unused_ml_ml_meas_ctrl_en_wdata =
+ ^ml_ml_meas_ctrl_en_wdata;
+
+ logic [9:0] ml_ml_meas_ctrl_shadowed_hi_qs_int;
+ logic [9:0] ml_ml_meas_ctrl_shadowed_lo_qs_int;
+ logic [19:0] ml_ml_meas_ctrl_shadowed_qs;
+ logic [19:0] ml_ml_meas_ctrl_shadowed_wdata;
+ logic ml_ml_meas_ctrl_shadowed_we;
+ logic unused_ml_ml_meas_ctrl_shadowed_wdata;
+ logic ml_ml_meas_ctrl_shadowed_re;
+ logic ml_ml_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ ml_ml_meas_ctrl_shadowed_qs = 20'h759ea;
+ ml_ml_meas_ctrl_shadowed_qs[9:0] = ml_ml_meas_ctrl_shadowed_hi_qs_int;
+ ml_ml_meas_ctrl_shadowed_qs[19:10] = ml_ml_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(20),
+ .ResetVal(20'h759ea),
+ .BitMask(20'hfffff),
+ .DstWrReq(0)
+ ) u_ml_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_ml_i),
+ .rst_dst_ni (rst_ml_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (ml_meas_ctrl_shadowed_we),
+ .src_re_i (ml_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[19:0]),
+ .src_busy_o (ml_meas_ctrl_shadowed_busy),
+ .src_qs_o (ml_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (ml_ml_meas_ctrl_shadowed_qs),
+ .dst_we_o (ml_ml_meas_ctrl_shadowed_we),
+ .dst_re_o (ml_ml_meas_ctrl_shadowed_re),
+ .dst_regwen_o (ml_ml_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (ml_ml_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_ml_ml_meas_ctrl_shadowed_wdata =
+ ^ml_ml_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] smc_smc_meas_ctrl_en_ds_int;
+ logic [3:0] smc_smc_meas_ctrl_en_qs_int;
+ logic [3:0] smc_smc_meas_ctrl_en_ds;
+ logic smc_smc_meas_ctrl_en_qe;
+ logic [3:0] smc_smc_meas_ctrl_en_qs;
+ logic [3:0] smc_smc_meas_ctrl_en_wdata;
+ logic smc_smc_meas_ctrl_en_we;
+ logic unused_smc_smc_meas_ctrl_en_wdata;
+ logic smc_smc_meas_ctrl_en_regwen;
+
+ always_comb begin
+ smc_smc_meas_ctrl_en_qs = 4'h9;
+ smc_smc_meas_ctrl_en_ds = 4'h9;
+ smc_smc_meas_ctrl_en_ds = smc_smc_meas_ctrl_en_ds_int;
+ smc_smc_meas_ctrl_en_qs = smc_smc_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_smc_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_smc_i),
+ .rst_dst_ni (rst_smc_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (smc_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (smc_meas_ctrl_en_busy),
+ .src_qs_o (smc_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (smc_smc_meas_ctrl_en_qe),
+ .dst_ds_i (smc_smc_meas_ctrl_en_ds),
+ .dst_qs_i (smc_smc_meas_ctrl_en_qs),
+ .dst_we_o (smc_smc_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (smc_smc_meas_ctrl_en_regwen),
+ .dst_wd_o (smc_smc_meas_ctrl_en_wdata)
+ );
+ assign unused_smc_smc_meas_ctrl_en_wdata =
+ ^smc_smc_meas_ctrl_en_wdata;
+
+ logic [9:0] smc_smc_meas_ctrl_shadowed_hi_qs_int;
+ logic [9:0] smc_smc_meas_ctrl_shadowed_lo_qs_int;
+ logic [19:0] smc_smc_meas_ctrl_shadowed_qs;
+ logic [19:0] smc_smc_meas_ctrl_shadowed_wdata;
+ logic smc_smc_meas_ctrl_shadowed_we;
+ logic unused_smc_smc_meas_ctrl_shadowed_wdata;
+ logic smc_smc_meas_ctrl_shadowed_re;
+ logic smc_smc_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ smc_smc_meas_ctrl_shadowed_qs = 20'h759ea;
+ smc_smc_meas_ctrl_shadowed_qs[9:0] = smc_smc_meas_ctrl_shadowed_hi_qs_int;
+ smc_smc_meas_ctrl_shadowed_qs[19:10] = smc_smc_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(20),
+ .ResetVal(20'h759ea),
+ .BitMask(20'hfffff),
+ .DstWrReq(0)
+ ) u_smc_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_smc_i),
+ .rst_dst_ni (rst_smc_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (smc_meas_ctrl_shadowed_we),
+ .src_re_i (smc_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[19:0]),
+ .src_busy_o (smc_meas_ctrl_shadowed_busy),
+ .src_qs_o (smc_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (smc_smc_meas_ctrl_shadowed_qs),
+ .dst_we_o (smc_smc_meas_ctrl_shadowed_we),
+ .dst_re_o (smc_smc_meas_ctrl_shadowed_re),
+ .dst_regwen_o (smc_smc_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (smc_smc_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_smc_smc_meas_ctrl_shadowed_wdata =
+ ^smc_smc_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] usb_usb_meas_ctrl_en_ds_int;
+ logic [3:0] usb_usb_meas_ctrl_en_qs_int;
+ logic [3:0] usb_usb_meas_ctrl_en_ds;
+ logic usb_usb_meas_ctrl_en_qe;
+ logic [3:0] usb_usb_meas_ctrl_en_qs;
+ logic [3:0] usb_usb_meas_ctrl_en_wdata;
+ logic usb_usb_meas_ctrl_en_we;
+ logic unused_usb_usb_meas_ctrl_en_wdata;
+ logic usb_usb_meas_ctrl_en_regwen;
+
+ always_comb begin
+ usb_usb_meas_ctrl_en_qs = 4'h9;
+ usb_usb_meas_ctrl_en_ds = 4'h9;
+ usb_usb_meas_ctrl_en_ds = usb_usb_meas_ctrl_en_ds_int;
+ usb_usb_meas_ctrl_en_qs = usb_usb_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_usb_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_usb_i),
+ .rst_dst_ni (rst_usb_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (usb_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (usb_meas_ctrl_en_busy),
+ .src_qs_o (usb_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (usb_usb_meas_ctrl_en_qe),
+ .dst_ds_i (usb_usb_meas_ctrl_en_ds),
+ .dst_qs_i (usb_usb_meas_ctrl_en_qs),
+ .dst_we_o (usb_usb_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (usb_usb_meas_ctrl_en_regwen),
+ .dst_wd_o (usb_usb_meas_ctrl_en_wdata)
+ );
+ assign unused_usb_usb_meas_ctrl_en_wdata =
+ ^usb_usb_meas_ctrl_en_wdata;
+
+ logic [8:0] usb_usb_meas_ctrl_shadowed_hi_qs_int;
+ logic [8:0] usb_usb_meas_ctrl_shadowed_lo_qs_int;
+ logic [17:0] usb_usb_meas_ctrl_shadowed_qs;
+ logic [17:0] usb_usb_meas_ctrl_shadowed_wdata;
+ logic usb_usb_meas_ctrl_shadowed_we;
+ logic unused_usb_usb_meas_ctrl_shadowed_wdata;
+ logic usb_usb_meas_ctrl_shadowed_re;
+ logic usb_usb_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ usb_usb_meas_ctrl_shadowed_qs = 18'h1ccfa;
+ usb_usb_meas_ctrl_shadowed_qs[8:0] = usb_usb_meas_ctrl_shadowed_hi_qs_int;
+ usb_usb_meas_ctrl_shadowed_qs[17:9] = usb_usb_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(18),
+ .ResetVal(18'h1ccfa),
+ .BitMask(18'h3ffff),
+ .DstWrReq(0)
+ ) u_usb_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_usb_i),
+ .rst_dst_ni (rst_usb_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (usb_meas_ctrl_shadowed_we),
+ .src_re_i (usb_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[17:0]),
+ .src_busy_o (usb_meas_ctrl_shadowed_busy),
+ .src_qs_o (usb_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (usb_usb_meas_ctrl_shadowed_qs),
+ .dst_we_o (usb_usb_meas_ctrl_shadowed_we),
+ .dst_re_o (usb_usb_meas_ctrl_shadowed_re),
+ .dst_regwen_o (usb_usb_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (usb_usb_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_usb_usb_meas_ctrl_shadowed_wdata =
+ ^usb_usb_meas_ctrl_shadowed_wdata;
+
+ logic [3:0] video_video_meas_ctrl_en_ds_int;
+ logic [3:0] video_video_meas_ctrl_en_qs_int;
+ logic [3:0] video_video_meas_ctrl_en_ds;
+ logic video_video_meas_ctrl_en_qe;
+ logic [3:0] video_video_meas_ctrl_en_qs;
+ logic [3:0] video_video_meas_ctrl_en_wdata;
+ logic video_video_meas_ctrl_en_we;
+ logic unused_video_video_meas_ctrl_en_wdata;
+ logic video_video_meas_ctrl_en_regwen;
+
+ always_comb begin
+ video_video_meas_ctrl_en_qs = 4'h9;
+ video_video_meas_ctrl_en_ds = 4'h9;
+ video_video_meas_ctrl_en_ds = video_video_meas_ctrl_en_ds_int;
+ video_video_meas_ctrl_en_qs = video_video_meas_ctrl_en_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(4),
+ .ResetVal(4'h9),
+ .BitMask(4'hf),
+ .DstWrReq(1)
+ ) u_video_meas_ctrl_en_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_video_i),
+ .rst_dst_ni (rst_video_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (video_meas_ctrl_en_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[3:0]),
+ .src_busy_o (video_meas_ctrl_en_busy),
+ .src_qs_o (video_meas_ctrl_en_qs), // for software read back
+ .dst_update_i (video_video_meas_ctrl_en_qe),
+ .dst_ds_i (video_video_meas_ctrl_en_ds),
+ .dst_qs_i (video_video_meas_ctrl_en_qs),
+ .dst_we_o (video_video_meas_ctrl_en_we),
+ .dst_re_o (),
+ .dst_regwen_o (video_video_meas_ctrl_en_regwen),
+ .dst_wd_o (video_video_meas_ctrl_en_wdata)
+ );
+ assign unused_video_video_meas_ctrl_en_wdata =
+ ^video_video_meas_ctrl_en_wdata;
+
+ logic [9:0] video_video_meas_ctrl_shadowed_hi_qs_int;
+ logic [9:0] video_video_meas_ctrl_shadowed_lo_qs_int;
+ logic [19:0] video_video_meas_ctrl_shadowed_qs;
+ logic [19:0] video_video_meas_ctrl_shadowed_wdata;
+ logic video_video_meas_ctrl_shadowed_we;
+ logic unused_video_video_meas_ctrl_shadowed_wdata;
+ logic video_video_meas_ctrl_shadowed_re;
+ logic video_video_meas_ctrl_shadowed_regwen;
+
+ always_comb begin
+ video_video_meas_ctrl_shadowed_qs = 20'h759ea;
+ video_video_meas_ctrl_shadowed_qs[9:0] = video_video_meas_ctrl_shadowed_hi_qs_int;
+ video_video_meas_ctrl_shadowed_qs[19:10] = video_video_meas_ctrl_shadowed_lo_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(20),
+ .ResetVal(20'h759ea),
+ .BitMask(20'hfffff),
+ .DstWrReq(0)
+ ) u_video_meas_ctrl_shadowed_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_video_i),
+ .rst_dst_ni (rst_video_ni),
+ .src_regwen_i (measure_ctrl_regwen_qs),
+ .src_we_i (video_meas_ctrl_shadowed_we),
+ .src_re_i (video_meas_ctrl_shadowed_re),
+ .src_wd_i (reg_wdata[19:0]),
+ .src_busy_o (video_meas_ctrl_shadowed_busy),
+ .src_qs_o (video_meas_ctrl_shadowed_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (video_video_meas_ctrl_shadowed_qs),
+ .dst_we_o (video_video_meas_ctrl_shadowed_we),
+ .dst_re_o (video_video_meas_ctrl_shadowed_re),
+ .dst_regwen_o (video_video_meas_ctrl_shadowed_regwen),
+ .dst_wd_o (video_video_meas_ctrl_shadowed_wdata)
+ );
+ assign unused_video_video_meas_ctrl_shadowed_wdata =
+ ^video_video_meas_ctrl_shadowed_wdata;
+
+ // Register instances
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [1:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ // F[recov_fault]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_fault (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_recov_fault_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.recov_fault.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.recov_fault.qe = alert_test_qe;
+
+ // F[fatal_fault]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_fault (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_fault_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_fault.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;
+
+
+ // R[extclk_ctrl_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_extclk_ctrl_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (extclk_ctrl_regwen_we),
+ .wd (extclk_ctrl_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (extclk_ctrl_regwen_qs)
+ );
+
+
+ // R[extclk_ctrl]: V(False)
+ // Create REGWEN-gated WE signal
+ logic extclk_ctrl_gated_we;
+ assign extclk_ctrl_gated_we = extclk_ctrl_we & extclk_ctrl_regwen_qs;
+ // F[sel]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_extclk_ctrl_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (extclk_ctrl_gated_we),
+ .wd (extclk_ctrl_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.extclk_ctrl.sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (extclk_ctrl_sel_qs)
+ );
+
+ // F[hi_speed_sel]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_extclk_ctrl_hi_speed_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (extclk_ctrl_gated_we),
+ .wd (extclk_ctrl_hi_speed_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.extclk_ctrl.hi_speed_sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (extclk_ctrl_hi_speed_sel_qs)
+ );
+
+
+ // R[extclk_status]: V(True)
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_extclk_status (
+ .re (extclk_status_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.extclk_status.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (extclk_status_qs)
+ );
+
+
+ // R[jitter_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_jitter_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (jitter_regwen_we),
+ .wd (jitter_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (jitter_regwen_qs)
+ );
+
+
+ // R[jitter_enable]: V(False)
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_jitter_enable (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (jitter_enable_we),
+ .wd (jitter_enable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.jitter_enable.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (jitter_enable_qs)
+ );
+
+
+ // R[clk_enables]: V(False)
+ // F[clk_io_div4_peri_en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_io_div4_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_io_div4_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_io_div4_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_io_div4_peri_en_qs)
+ );
+
+ // F[clk_io_div2_peri_en]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_io_div2_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_io_div2_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_io_div2_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_io_div2_peri_en_qs)
+ );
+
+ // F[clk_io_peri_en]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_io_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_io_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_io_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_io_peri_en_qs)
+ );
+
+ // F[clk_usb_peri_en]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_usb_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_usb_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_usb_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_usb_peri_en_qs)
+ );
+
+ // F[clk_video_peri_en]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_video_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_video_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_video_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_video_peri_en_qs)
+ );
+
+ // F[clk_ml_peri_en]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_ml_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_ml_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_ml_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_ml_peri_en_qs)
+ );
+
+ // F[clk_audio_peri_en]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_audio_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_audio_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_audio_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_audio_peri_en_qs)
+ );
+
+ // F[clk_smc_peri_en]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_enables_clk_smc_peri_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_enables_we),
+ .wd (clk_enables_clk_smc_peri_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_enables.clk_smc_peri_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_enables_clk_smc_peri_en_qs)
+ );
+
+
+ // R[clk_hints]: V(False)
+ // F[clk_main_aes_hint]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_hints_clk_main_aes_hint (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_hints_we),
+ .wd (clk_hints_clk_main_aes_hint_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_hints.clk_main_aes_hint.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_clk_main_aes_hint_qs)
+ );
+
+ // F[clk_main_hmac_hint]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_hints_clk_main_hmac_hint (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_hints_we),
+ .wd (clk_hints_clk_main_hmac_hint_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_hints.clk_main_hmac_hint.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_clk_main_hmac_hint_qs)
+ );
+
+ // F[clk_main_kmac_hint]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_hints_clk_main_kmac_hint (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_hints_we),
+ .wd (clk_hints_clk_main_kmac_hint_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_hints.clk_main_kmac_hint.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_clk_main_kmac_hint_qs)
+ );
+
+ // F[clk_main_otbn_hint]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_clk_hints_clk_main_otbn_hint (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (clk_hints_we),
+ .wd (clk_hints_clk_main_otbn_hint_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.clk_hints.clk_main_otbn_hint.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_clk_main_otbn_hint_qs)
+ );
+
+
+ // R[clk_hints_status]: V(False)
+ // F[clk_main_aes_val]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_clk_hints_status_clk_main_aes_val (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.clk_hints_status.clk_main_aes_val.de),
+ .d (hw2reg.clk_hints_status.clk_main_aes_val.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_status_clk_main_aes_val_qs)
+ );
+
+ // F[clk_main_hmac_val]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_clk_hints_status_clk_main_hmac_val (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.clk_hints_status.clk_main_hmac_val.de),
+ .d (hw2reg.clk_hints_status.clk_main_hmac_val.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_status_clk_main_hmac_val_qs)
+ );
+
+ // F[clk_main_kmac_val]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_clk_hints_status_clk_main_kmac_val (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.clk_hints_status.clk_main_kmac_val.de),
+ .d (hw2reg.clk_hints_status.clk_main_kmac_val.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_status_clk_main_kmac_val_qs)
+ );
+
+ // F[clk_main_otbn_val]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_clk_hints_status_clk_main_otbn_val (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.clk_hints_status.clk_main_otbn_val.de),
+ .d (hw2reg.clk_hints_status.clk_main_otbn_val.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (clk_hints_status_clk_main_otbn_val_qs)
+ );
+
+
+ // R[measure_ctrl_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_measure_ctrl_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (measure_ctrl_regwen_we),
+ .wd (measure_ctrl_regwen_wd),
+
+ // from internal hardware
+ .de (hw2reg.measure_ctrl_regwen.de),
+ .d (hw2reg.measure_ctrl_regwen.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.measure_ctrl_regwen.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (measure_ctrl_regwen_qs)
+ );
+
+
+ // R[audio_meas_ctrl_en]: V(False)
+ logic [0:0] audio_meas_ctrl_en_flds_we;
+ assign audio_audio_meas_ctrl_en_qe = |audio_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic audio_audio_meas_ctrl_en_gated_we;
+ assign audio_audio_meas_ctrl_en_gated_we =
+ audio_audio_meas_ctrl_en_we & audio_audio_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_audio_meas_ctrl_en (
+ .clk_i (clk_audio_i),
+ .rst_ni (rst_audio_ni),
+
+ // from register interface
+ .we (audio_audio_meas_ctrl_en_gated_we),
+ .wd (audio_audio_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.audio_meas_ctrl_en.de),
+ .d (hw2reg.audio_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (audio_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.audio_meas_ctrl_en.q),
+ .ds (audio_audio_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (audio_audio_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[audio_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic audio_audio_meas_ctrl_shadowed_gated_we;
+ assign audio_audio_meas_ctrl_shadowed_gated_we =
+ audio_audio_meas_ctrl_shadowed_we & audio_audio_meas_ctrl_shadowed_regwen;
+ // F[hi]: 8:0
+ logic async_audio_meas_ctrl_shadowed_hi_err_update;
+ logic async_audio_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_audio_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_audio_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(audio_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_audio_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_audio_i),
+ .rst_src_ni(rst_audio_ni),
+ .src_pulse_i(async_audio_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(audio_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'hfa)
+ ) u_audio_meas_ctrl_shadowed_hi (
+ .clk_i (clk_audio_i),
+ .rst_ni (rst_audio_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (audio_audio_meas_ctrl_shadowed_re),
+ .we (audio_audio_meas_ctrl_shadowed_gated_we),
+ .wd (audio_audio_meas_ctrl_shadowed_wdata[8:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.audio_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (audio_audio_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_audio_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_audio_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 17:9
+ logic async_audio_meas_ctrl_shadowed_lo_err_update;
+ logic async_audio_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_audio_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_audio_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(audio_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_audio_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_audio_i),
+ .rst_src_ni(rst_audio_ni),
+ .src_pulse_i(async_audio_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(audio_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'he6)
+ ) u_audio_meas_ctrl_shadowed_lo (
+ .clk_i (clk_audio_i),
+ .rst_ni (rst_audio_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (audio_audio_meas_ctrl_shadowed_re),
+ .we (audio_audio_meas_ctrl_shadowed_gated_we),
+ .wd (audio_audio_meas_ctrl_shadowed_wdata[17:9]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.audio_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (audio_audio_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_audio_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_audio_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[io_meas_ctrl_en]: V(False)
+ logic [0:0] io_meas_ctrl_en_flds_we;
+ assign io_io_meas_ctrl_en_qe = |io_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic io_io_meas_ctrl_en_gated_we;
+ assign io_io_meas_ctrl_en_gated_we = io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_io_meas_ctrl_en (
+ .clk_i (clk_io_i),
+ .rst_ni (rst_io_ni),
+
+ // from register interface
+ .we (io_io_meas_ctrl_en_gated_we),
+ .wd (io_io_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.io_meas_ctrl_en.de),
+ .d (hw2reg.io_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (io_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.io_meas_ctrl_en.q),
+ .ds (io_io_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (io_io_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[io_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic io_io_meas_ctrl_shadowed_gated_we;
+ assign io_io_meas_ctrl_shadowed_gated_we =
+ io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen;
+ // F[hi]: 9:0
+ logic async_io_meas_ctrl_shadowed_hi_err_update;
+ logic async_io_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(io_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_io_i),
+ .rst_src_ni(rst_io_ni),
+ .src_pulse_i(async_io_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1ea)
+ ) u_io_meas_ctrl_shadowed_hi (
+ .clk_i (clk_io_i),
+ .rst_ni (rst_io_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_io_meas_ctrl_shadowed_re),
+ .we (io_io_meas_ctrl_shadowed_gated_we),
+ .wd (io_io_meas_ctrl_shadowed_wdata[9:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_io_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_io_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 19:10
+ logic async_io_meas_ctrl_shadowed_lo_err_update;
+ logic async_io_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(io_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_io_i),
+ .rst_src_ni(rst_io_ni),
+ .src_pulse_i(async_io_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1d6)
+ ) u_io_meas_ctrl_shadowed_lo (
+ .clk_i (clk_io_i),
+ .rst_ni (rst_io_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_io_meas_ctrl_shadowed_re),
+ .we (io_io_meas_ctrl_shadowed_gated_we),
+ .wd (io_io_meas_ctrl_shadowed_wdata[19:10]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_io_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_io_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[io_div2_meas_ctrl_en]: V(False)
+ logic [0:0] io_div2_meas_ctrl_en_flds_we;
+ assign io_div2_io_div2_meas_ctrl_en_qe = |io_div2_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic io_div2_io_div2_meas_ctrl_en_gated_we;
+ assign io_div2_io_div2_meas_ctrl_en_gated_we =
+ io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_io_div2_meas_ctrl_en (
+ .clk_i (clk_io_div2_i),
+ .rst_ni (rst_io_div2_ni),
+
+ // from register interface
+ .we (io_div2_io_div2_meas_ctrl_en_gated_we),
+ .wd (io_div2_io_div2_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.io_div2_meas_ctrl_en.de),
+ .d (hw2reg.io_div2_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (io_div2_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.io_div2_meas_ctrl_en.q),
+ .ds (io_div2_io_div2_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (io_div2_io_div2_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[io_div2_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic io_div2_io_div2_meas_ctrl_shadowed_gated_we;
+ assign io_div2_io_div2_meas_ctrl_shadowed_gated_we =
+ io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen;
+ // F[hi]: 8:0
+ logic async_io_div2_meas_ctrl_shadowed_hi_err_update;
+ logic async_io_div2_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_div2_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(io_div2_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_div2_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_io_div2_i),
+ .rst_src_ni(rst_io_div2_ni),
+ .src_pulse_i(async_io_div2_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_div2_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'hfa)
+ ) u_io_div2_meas_ctrl_shadowed_hi (
+ .clk_i (clk_io_div2_i),
+ .rst_ni (rst_io_div2_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_div2_io_div2_meas_ctrl_shadowed_re),
+ .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
+ .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[8:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_div2_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_div2_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_io_div2_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 17:9
+ logic async_io_div2_meas_ctrl_shadowed_lo_err_update;
+ logic async_io_div2_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_div2_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(io_div2_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_div2_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_io_div2_i),
+ .rst_src_ni(rst_io_div2_ni),
+ .src_pulse_i(async_io_div2_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_div2_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'he6)
+ ) u_io_div2_meas_ctrl_shadowed_lo (
+ .clk_i (clk_io_div2_i),
+ .rst_ni (rst_io_div2_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_div2_io_div2_meas_ctrl_shadowed_re),
+ .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
+ .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[17:9]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_div2_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_div2_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_io_div2_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[io_div4_meas_ctrl_en]: V(False)
+ logic [0:0] io_div4_meas_ctrl_en_flds_we;
+ assign io_div4_io_div4_meas_ctrl_en_qe = |io_div4_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic io_div4_io_div4_meas_ctrl_en_gated_we;
+ assign io_div4_io_div4_meas_ctrl_en_gated_we =
+ io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_io_div4_meas_ctrl_en (
+ .clk_i (clk_io_div4_i),
+ .rst_ni (rst_io_div4_ni),
+
+ // from register interface
+ .we (io_div4_io_div4_meas_ctrl_en_gated_we),
+ .wd (io_div4_io_div4_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.io_div4_meas_ctrl_en.de),
+ .d (hw2reg.io_div4_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (io_div4_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.io_div4_meas_ctrl_en.q),
+ .ds (io_div4_io_div4_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (io_div4_io_div4_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[io_div4_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic io_div4_io_div4_meas_ctrl_shadowed_gated_we;
+ assign io_div4_io_div4_meas_ctrl_shadowed_gated_we =
+ io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen;
+ // F[hi]: 7:0
+ logic async_io_div4_meas_ctrl_shadowed_hi_err_update;
+ logic async_io_div4_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(io_div4_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_io_div4_i),
+ .rst_src_ni(rst_io_div4_ni),
+ .src_pulse_i(async_io_div4_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_div4_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h82)
+ ) u_io_div4_meas_ctrl_shadowed_hi (
+ .clk_i (clk_io_div4_i),
+ .rst_ni (rst_io_div4_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_div4_io_div4_meas_ctrl_shadowed_re),
+ .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
+ .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_div4_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_div4_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_io_div4_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 15:8
+ logic async_io_div4_meas_ctrl_shadowed_lo_err_update;
+ logic async_io_div4_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(io_div4_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_io_div4_i),
+ .rst_src_ni(rst_io_div4_ni),
+ .src_pulse_i(async_io_div4_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(io_div4_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h6e)
+ ) u_io_div4_meas_ctrl_shadowed_lo (
+ .clk_i (clk_io_div4_i),
+ .rst_ni (rst_io_div4_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (io_div4_io_div4_meas_ctrl_shadowed_re),
+ .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
+ .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[15:8]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.io_div4_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_io_div4_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_io_div4_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[main_meas_ctrl_en]: V(False)
+ logic [0:0] main_meas_ctrl_en_flds_we;
+ assign main_main_meas_ctrl_en_qe = |main_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic main_main_meas_ctrl_en_gated_we;
+ assign main_main_meas_ctrl_en_gated_we =
+ main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_main_meas_ctrl_en (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+
+ // from register interface
+ .we (main_main_meas_ctrl_en_gated_we),
+ .wd (main_main_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.main_meas_ctrl_en.de),
+ .d (hw2reg.main_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (main_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.main_meas_ctrl_en.q),
+ .ds (main_main_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (main_main_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[main_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic main_main_meas_ctrl_shadowed_gated_we;
+ assign main_main_meas_ctrl_shadowed_gated_we =
+ main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen;
+ // F[hi]: 9:0
+ logic async_main_meas_ctrl_shadowed_hi_err_update;
+ logic async_main_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_main_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(main_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_main_i),
+ .rst_src_ni(rst_main_ni),
+ .src_pulse_i(async_main_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(main_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1ea)
+ ) u_main_meas_ctrl_shadowed_hi (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (main_main_meas_ctrl_shadowed_re),
+ .we (main_main_meas_ctrl_shadowed_gated_we),
+ .wd (main_main_meas_ctrl_shadowed_wdata[9:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.main_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (main_main_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_main_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_main_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 19:10
+ logic async_main_meas_ctrl_shadowed_lo_err_update;
+ logic async_main_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_main_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(main_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_main_i),
+ .rst_src_ni(rst_main_ni),
+ .src_pulse_i(async_main_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(main_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1d6)
+ ) u_main_meas_ctrl_shadowed_lo (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (main_main_meas_ctrl_shadowed_re),
+ .we (main_main_meas_ctrl_shadowed_gated_we),
+ .wd (main_main_meas_ctrl_shadowed_wdata[19:10]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.main_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (main_main_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_main_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_main_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[ml_meas_ctrl_en]: V(False)
+ logic [0:0] ml_meas_ctrl_en_flds_we;
+ assign ml_ml_meas_ctrl_en_qe = |ml_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic ml_ml_meas_ctrl_en_gated_we;
+ assign ml_ml_meas_ctrl_en_gated_we = ml_ml_meas_ctrl_en_we & ml_ml_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_ml_meas_ctrl_en (
+ .clk_i (clk_ml_i),
+ .rst_ni (rst_ml_ni),
+
+ // from register interface
+ .we (ml_ml_meas_ctrl_en_gated_we),
+ .wd (ml_ml_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.ml_meas_ctrl_en.de),
+ .d (hw2reg.ml_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (ml_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.ml_meas_ctrl_en.q),
+ .ds (ml_ml_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (ml_ml_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[ml_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic ml_ml_meas_ctrl_shadowed_gated_we;
+ assign ml_ml_meas_ctrl_shadowed_gated_we =
+ ml_ml_meas_ctrl_shadowed_we & ml_ml_meas_ctrl_shadowed_regwen;
+ // F[hi]: 9:0
+ logic async_ml_meas_ctrl_shadowed_hi_err_update;
+ logic async_ml_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_ml_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_ml_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(ml_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_ml_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_ml_i),
+ .rst_src_ni(rst_ml_ni),
+ .src_pulse_i(async_ml_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(ml_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1ea)
+ ) u_ml_meas_ctrl_shadowed_hi (
+ .clk_i (clk_ml_i),
+ .rst_ni (rst_ml_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (ml_ml_meas_ctrl_shadowed_re),
+ .we (ml_ml_meas_ctrl_shadowed_gated_we),
+ .wd (ml_ml_meas_ctrl_shadowed_wdata[9:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ml_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ml_ml_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_ml_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_ml_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 19:10
+ logic async_ml_meas_ctrl_shadowed_lo_err_update;
+ logic async_ml_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_ml_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_ml_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(ml_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_ml_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_ml_i),
+ .rst_src_ni(rst_ml_ni),
+ .src_pulse_i(async_ml_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(ml_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1d6)
+ ) u_ml_meas_ctrl_shadowed_lo (
+ .clk_i (clk_ml_i),
+ .rst_ni (rst_ml_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (ml_ml_meas_ctrl_shadowed_re),
+ .we (ml_ml_meas_ctrl_shadowed_gated_we),
+ .wd (ml_ml_meas_ctrl_shadowed_wdata[19:10]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ml_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ml_ml_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_ml_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_ml_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[smc_meas_ctrl_en]: V(False)
+ logic [0:0] smc_meas_ctrl_en_flds_we;
+ assign smc_smc_meas_ctrl_en_qe = |smc_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic smc_smc_meas_ctrl_en_gated_we;
+ assign smc_smc_meas_ctrl_en_gated_we = smc_smc_meas_ctrl_en_we & smc_smc_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_smc_meas_ctrl_en (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+
+ // from register interface
+ .we (smc_smc_meas_ctrl_en_gated_we),
+ .wd (smc_smc_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.smc_meas_ctrl_en.de),
+ .d (hw2reg.smc_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (smc_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.smc_meas_ctrl_en.q),
+ .ds (smc_smc_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (smc_smc_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[smc_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic smc_smc_meas_ctrl_shadowed_gated_we;
+ assign smc_smc_meas_ctrl_shadowed_gated_we =
+ smc_smc_meas_ctrl_shadowed_we & smc_smc_meas_ctrl_shadowed_regwen;
+ // F[hi]: 9:0
+ logic async_smc_meas_ctrl_shadowed_hi_err_update;
+ logic async_smc_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_smc_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_smc_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(smc_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_smc_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_smc_i),
+ .rst_src_ni(rst_smc_ni),
+ .src_pulse_i(async_smc_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(smc_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1ea)
+ ) u_smc_meas_ctrl_shadowed_hi (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (smc_smc_meas_ctrl_shadowed_re),
+ .we (smc_smc_meas_ctrl_shadowed_gated_we),
+ .wd (smc_smc_meas_ctrl_shadowed_wdata[9:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.smc_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (smc_smc_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_smc_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_smc_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 19:10
+ logic async_smc_meas_ctrl_shadowed_lo_err_update;
+ logic async_smc_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_smc_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_smc_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(smc_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_smc_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_smc_i),
+ .rst_src_ni(rst_smc_ni),
+ .src_pulse_i(async_smc_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(smc_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1d6)
+ ) u_smc_meas_ctrl_shadowed_lo (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (smc_smc_meas_ctrl_shadowed_re),
+ .we (smc_smc_meas_ctrl_shadowed_gated_we),
+ .wd (smc_smc_meas_ctrl_shadowed_wdata[19:10]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.smc_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (smc_smc_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_smc_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_smc_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[usb_meas_ctrl_en]: V(False)
+ logic [0:0] usb_meas_ctrl_en_flds_we;
+ assign usb_usb_meas_ctrl_en_qe = |usb_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic usb_usb_meas_ctrl_en_gated_we;
+ assign usb_usb_meas_ctrl_en_gated_we = usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_usb_meas_ctrl_en (
+ .clk_i (clk_usb_i),
+ .rst_ni (rst_usb_ni),
+
+ // from register interface
+ .we (usb_usb_meas_ctrl_en_gated_we),
+ .wd (usb_usb_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.usb_meas_ctrl_en.de),
+ .d (hw2reg.usb_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (usb_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.usb_meas_ctrl_en.q),
+ .ds (usb_usb_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (usb_usb_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[usb_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic usb_usb_meas_ctrl_shadowed_gated_we;
+ assign usb_usb_meas_ctrl_shadowed_gated_we =
+ usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen;
+ // F[hi]: 8:0
+ logic async_usb_meas_ctrl_shadowed_hi_err_update;
+ logic async_usb_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_usb_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_usb_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(usb_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_usb_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_usb_i),
+ .rst_src_ni(rst_usb_ni),
+ .src_pulse_i(async_usb_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(usb_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'hfa)
+ ) u_usb_meas_ctrl_shadowed_hi (
+ .clk_i (clk_usb_i),
+ .rst_ni (rst_usb_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (usb_usb_meas_ctrl_shadowed_re),
+ .we (usb_usb_meas_ctrl_shadowed_gated_we),
+ .wd (usb_usb_meas_ctrl_shadowed_wdata[8:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.usb_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (usb_usb_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_usb_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_usb_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 17:9
+ logic async_usb_meas_ctrl_shadowed_lo_err_update;
+ logic async_usb_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_usb_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_usb_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(usb_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_usb_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_usb_i),
+ .rst_src_ni(rst_usb_ni),
+ .src_pulse_i(async_usb_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(usb_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'he6)
+ ) u_usb_meas_ctrl_shadowed_lo (
+ .clk_i (clk_usb_i),
+ .rst_ni (rst_usb_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (usb_usb_meas_ctrl_shadowed_re),
+ .we (usb_usb_meas_ctrl_shadowed_gated_we),
+ .wd (usb_usb_meas_ctrl_shadowed_wdata[17:9]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.usb_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (usb_usb_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_usb_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_usb_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[video_meas_ctrl_en]: V(False)
+ logic [0:0] video_meas_ctrl_en_flds_we;
+ assign video_video_meas_ctrl_en_qe = |video_meas_ctrl_en_flds_we;
+ // Create REGWEN-gated WE signal
+ logic video_video_meas_ctrl_en_gated_we;
+ assign video_video_meas_ctrl_en_gated_we =
+ video_video_meas_ctrl_en_we & video_video_meas_ctrl_en_regwen;
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_video_meas_ctrl_en (
+ .clk_i (clk_video_i),
+ .rst_ni (rst_video_ni),
+
+ // from register interface
+ .we (video_video_meas_ctrl_en_gated_we),
+ .wd (video_video_meas_ctrl_en_wdata[3:0]),
+
+ // from internal hardware
+ .de (hw2reg.video_meas_ctrl_en.de),
+ .d (hw2reg.video_meas_ctrl_en.d),
+
+ // to internal hardware
+ .qe (video_meas_ctrl_en_flds_we[0]),
+ .q (reg2hw.video_meas_ctrl_en.q),
+ .ds (video_video_meas_ctrl_en_ds_int),
+
+ // to register interface (read)
+ .qs (video_video_meas_ctrl_en_qs_int)
+ );
+
+
+ // R[video_meas_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic video_video_meas_ctrl_shadowed_gated_we;
+ assign video_video_meas_ctrl_shadowed_gated_we =
+ video_video_meas_ctrl_shadowed_we & video_video_meas_ctrl_shadowed_regwen;
+ // F[hi]: 9:0
+ logic async_video_meas_ctrl_shadowed_hi_err_update;
+ logic async_video_meas_ctrl_shadowed_hi_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_video_meas_ctrl_shadowed_hi_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_video_meas_ctrl_shadowed_hi_err_storage),
+ .q_o(video_meas_ctrl_shadowed_hi_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_video_meas_ctrl_shadowed_hi_err_update_sync (
+ .clk_src_i(clk_video_i),
+ .rst_src_ni(rst_video_ni),
+ .src_pulse_i(async_video_meas_ctrl_shadowed_hi_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(video_meas_ctrl_shadowed_hi_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1ea)
+ ) u_video_meas_ctrl_shadowed_hi (
+ .clk_i (clk_video_i),
+ .rst_ni (rst_video_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (video_video_meas_ctrl_shadowed_re),
+ .we (video_video_meas_ctrl_shadowed_gated_we),
+ .wd (video_video_meas_ctrl_shadowed_wdata[9:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.video_meas_ctrl_shadowed.hi.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (video_video_meas_ctrl_shadowed_hi_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_video_meas_ctrl_shadowed_hi_err_update),
+ .err_storage (async_video_meas_ctrl_shadowed_hi_err_storage)
+ );
+
+ // F[lo]: 19:10
+ logic async_video_meas_ctrl_shadowed_lo_err_update;
+ logic async_video_meas_ctrl_shadowed_lo_err_storage;
+
+ // storage error is persistent and can be sampled at any time
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_video_meas_ctrl_shadowed_lo_err_storage_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_video_meas_ctrl_shadowed_lo_err_storage),
+ .q_o(video_meas_ctrl_shadowed_lo_storage_err)
+ );
+
+ // update error is transient and must be immediately captured
+ prim_pulse_sync u_video_meas_ctrl_shadowed_lo_err_update_sync (
+ .clk_src_i(clk_video_i),
+ .rst_src_ni(rst_video_ni),
+ .src_pulse_i(async_video_meas_ctrl_shadowed_lo_err_update),
+ .clk_dst_i(clk_i),
+ .rst_dst_ni(rst_ni),
+ .dst_pulse_o(video_meas_ctrl_shadowed_lo_update_err)
+ );
+ prim_subreg_shadow #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h1d6)
+ ) u_video_meas_ctrl_shadowed_lo (
+ .clk_i (clk_video_i),
+ .rst_ni (rst_video_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (video_video_meas_ctrl_shadowed_re),
+ .we (video_video_meas_ctrl_shadowed_gated_we),
+ .wd (video_video_meas_ctrl_shadowed_wdata[19:10]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.video_meas_ctrl_shadowed.lo.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (video_video_meas_ctrl_shadowed_lo_qs_int),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (async_video_meas_ctrl_shadowed_lo_err_update),
+ .err_storage (async_video_meas_ctrl_shadowed_lo_err_storage)
+ );
+
+
+ // R[recov_err_code]: V(False)
+ // F[shadow_update_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_shadow_update_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_shadow_update_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.shadow_update_err.de),
+ .d (hw2reg.recov_err_code.shadow_update_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_shadow_update_err_qs)
+ );
+
+ // F[audio_measure_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_audio_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_audio_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.audio_measure_err.de),
+ .d (hw2reg.recov_err_code.audio_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_audio_measure_err_qs)
+ );
+
+ // F[io_measure_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_measure_err.de),
+ .d (hw2reg.recov_err_code.io_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_measure_err_qs)
+ );
+
+ // F[io_div2_measure_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_div2_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_div2_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_div2_measure_err.de),
+ .d (hw2reg.recov_err_code.io_div2_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_div2_measure_err_qs)
+ );
+
+ // F[io_div4_measure_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_div4_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_div4_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_div4_measure_err.de),
+ .d (hw2reg.recov_err_code.io_div4_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_div4_measure_err_qs)
+ );
+
+ // F[main_measure_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_main_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_main_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.main_measure_err.de),
+ .d (hw2reg.recov_err_code.main_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_main_measure_err_qs)
+ );
+
+ // F[ml_measure_err]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_ml_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_ml_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.ml_measure_err.de),
+ .d (hw2reg.recov_err_code.ml_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_ml_measure_err_qs)
+ );
+
+ // F[smc_measure_err]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_smc_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_smc_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.smc_measure_err.de),
+ .d (hw2reg.recov_err_code.smc_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_smc_measure_err_qs)
+ );
+
+ // F[usb_measure_err]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_usb_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_usb_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.usb_measure_err.de),
+ .d (hw2reg.recov_err_code.usb_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_usb_measure_err_qs)
+ );
+
+ // F[video_measure_err]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_video_measure_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_video_measure_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.video_measure_err.de),
+ .d (hw2reg.recov_err_code.video_measure_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_video_measure_err_qs)
+ );
+
+ // F[audio_timeout_err]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_audio_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_audio_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.audio_timeout_err.de),
+ .d (hw2reg.recov_err_code.audio_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_audio_timeout_err_qs)
+ );
+
+ // F[io_timeout_err]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_timeout_err.de),
+ .d (hw2reg.recov_err_code.io_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_timeout_err_qs)
+ );
+
+ // F[io_div2_timeout_err]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_div2_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_div2_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_div2_timeout_err.de),
+ .d (hw2reg.recov_err_code.io_div2_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_div2_timeout_err_qs)
+ );
+
+ // F[io_div4_timeout_err]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_io_div4_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_io_div4_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.io_div4_timeout_err.de),
+ .d (hw2reg.recov_err_code.io_div4_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_io_div4_timeout_err_qs)
+ );
+
+ // F[main_timeout_err]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_main_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_main_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.main_timeout_err.de),
+ .d (hw2reg.recov_err_code.main_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_main_timeout_err_qs)
+ );
+
+ // F[ml_timeout_err]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_ml_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_ml_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.ml_timeout_err.de),
+ .d (hw2reg.recov_err_code.ml_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_ml_timeout_err_qs)
+ );
+
+ // F[smc_timeout_err]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_smc_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_smc_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.smc_timeout_err.de),
+ .d (hw2reg.recov_err_code.smc_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_smc_timeout_err_qs)
+ );
+
+ // F[usb_timeout_err]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_usb_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_usb_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.usb_timeout_err.de),
+ .d (hw2reg.recov_err_code.usb_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_usb_timeout_err_qs)
+ );
+
+ // F[video_timeout_err]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_err_code_video_timeout_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_err_code_we),
+ .wd (recov_err_code_video_timeout_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_err_code.video_timeout_err.de),
+ .d (hw2reg.recov_err_code.video_timeout_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_err_code_video_timeout_err_qs)
+ );
+
+
+ // R[fatal_err_code]: V(False)
+ // F[reg_intg]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_err_code_reg_intg (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_err_code.reg_intg.de),
+ .d (hw2reg.fatal_err_code.reg_intg.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_err_code.reg_intg.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_err_code_reg_intg_qs)
+ );
+
+ // F[idle_cnt]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_err_code_idle_cnt (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_err_code.idle_cnt.de),
+ .d (hw2reg.fatal_err_code.idle_cnt.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_err_code.idle_cnt.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_err_code_idle_cnt_qs)
+ );
+
+ // F[shadow_storage_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_err_code_shadow_storage_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_err_code.shadow_storage_err.de),
+ .d (hw2reg.fatal_err_code.shadow_storage_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_err_code.shadow_storage_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_err_code_shadow_storage_err_qs)
+ );
+
+
+
+ logic [29:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET);
+ addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET);
+ addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET);
+ addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET);
+ addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET);
+ addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET);
+ addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET);
+ addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET);
+ addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET);
+ addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET);
+ addr_hit[10] = (reg_addr == CLKMGR_AUDIO_MEAS_CTRL_EN_OFFSET);
+ addr_hit[11] = (reg_addr == CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[12] = (reg_addr == CLKMGR_IO_MEAS_CTRL_EN_OFFSET);
+ addr_hit[13] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[14] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET);
+ addr_hit[15] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[16] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET);
+ addr_hit[17] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[18] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET);
+ addr_hit[19] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[20] = (reg_addr == CLKMGR_ML_MEAS_CTRL_EN_OFFSET);
+ addr_hit[21] = (reg_addr == CLKMGR_ML_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[22] = (reg_addr == CLKMGR_SMC_MEAS_CTRL_EN_OFFSET);
+ addr_hit[23] = (reg_addr == CLKMGR_SMC_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[24] = (reg_addr == CLKMGR_USB_MEAS_CTRL_EN_OFFSET);
+ addr_hit[25] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[26] = (reg_addr == CLKMGR_VIDEO_MEAS_CTRL_EN_OFFSET);
+ addr_hit[27] = (reg_addr == CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_OFFSET);
+ addr_hit[28] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET);
+ addr_hit[29] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(CLKMGR_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(CLKMGR_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(CLKMGR_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(CLKMGR_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(CLKMGR_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(CLKMGR_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(CLKMGR_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(CLKMGR_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(CLKMGR_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(CLKMGR_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(CLKMGR_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(CLKMGR_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(CLKMGR_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(CLKMGR_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(CLKMGR_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(CLKMGR_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(CLKMGR_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(CLKMGR_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(CLKMGR_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(CLKMGR_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(CLKMGR_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(CLKMGR_PERMIT[26] & ~reg_be))) |
+ (addr_hit[27] & (|(CLKMGR_PERMIT[27] & ~reg_be))) |
+ (addr_hit[28] & (|(CLKMGR_PERMIT[28] & ~reg_be))) |
+ (addr_hit[29] & (|(CLKMGR_PERMIT[29] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign alert_test_recov_fault_wd = reg_wdata[0];
+
+ assign alert_test_fatal_fault_wd = reg_wdata[1];
+ assign extclk_ctrl_regwen_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign extclk_ctrl_regwen_wd = reg_wdata[0];
+ assign extclk_ctrl_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign extclk_ctrl_sel_wd = reg_wdata[3:0];
+
+ assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4];
+ assign extclk_status_re = addr_hit[3] & reg_re & !reg_error;
+ assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign jitter_regwen_wd = reg_wdata[0];
+ assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign jitter_enable_wd = reg_wdata[3:0];
+ assign clk_enables_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0];
+
+ assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1];
+
+ assign clk_enables_clk_io_peri_en_wd = reg_wdata[2];
+
+ assign clk_enables_clk_usb_peri_en_wd = reg_wdata[3];
+
+ assign clk_enables_clk_video_peri_en_wd = reg_wdata[4];
+
+ assign clk_enables_clk_ml_peri_en_wd = reg_wdata[5];
+
+ assign clk_enables_clk_audio_peri_en_wd = reg_wdata[6];
+
+ assign clk_enables_clk_smc_peri_en_wd = reg_wdata[7];
+ assign clk_hints_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0];
+
+ assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1];
+
+ assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2];
+
+ assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3];
+ assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign measure_ctrl_regwen_wd = reg_wdata[0];
+ assign audio_meas_ctrl_en_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign audio_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error;
+ assign audio_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error;
+
+
+ assign io_meas_ctrl_en_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign io_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error;
+ assign io_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error;
+
+
+ assign io_div2_meas_ctrl_en_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign io_div2_meas_ctrl_shadowed_re = addr_hit[15] & reg_re & !reg_error;
+ assign io_div2_meas_ctrl_shadowed_we = addr_hit[15] & reg_we & !reg_error;
+
+
+ assign io_div4_meas_ctrl_en_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign io_div4_meas_ctrl_shadowed_re = addr_hit[17] & reg_re & !reg_error;
+ assign io_div4_meas_ctrl_shadowed_we = addr_hit[17] & reg_we & !reg_error;
+
+
+ assign main_meas_ctrl_en_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign main_meas_ctrl_shadowed_re = addr_hit[19] & reg_re & !reg_error;
+ assign main_meas_ctrl_shadowed_we = addr_hit[19] & reg_we & !reg_error;
+
+
+ assign ml_meas_ctrl_en_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign ml_meas_ctrl_shadowed_re = addr_hit[21] & reg_re & !reg_error;
+ assign ml_meas_ctrl_shadowed_we = addr_hit[21] & reg_we & !reg_error;
+
+
+ assign smc_meas_ctrl_en_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign smc_meas_ctrl_shadowed_re = addr_hit[23] & reg_re & !reg_error;
+ assign smc_meas_ctrl_shadowed_we = addr_hit[23] & reg_we & !reg_error;
+
+
+ assign usb_meas_ctrl_en_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign usb_meas_ctrl_shadowed_re = addr_hit[25] & reg_re & !reg_error;
+ assign usb_meas_ctrl_shadowed_we = addr_hit[25] & reg_we & !reg_error;
+
+
+ assign video_meas_ctrl_en_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign video_meas_ctrl_shadowed_re = addr_hit[27] & reg_re & !reg_error;
+ assign video_meas_ctrl_shadowed_we = addr_hit[27] & reg_we & !reg_error;
+
+
+ assign recov_err_code_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign recov_err_code_shadow_update_err_wd = reg_wdata[0];
+
+ assign recov_err_code_audio_measure_err_wd = reg_wdata[1];
+
+ assign recov_err_code_io_measure_err_wd = reg_wdata[2];
+
+ assign recov_err_code_io_div2_measure_err_wd = reg_wdata[3];
+
+ assign recov_err_code_io_div4_measure_err_wd = reg_wdata[4];
+
+ assign recov_err_code_main_measure_err_wd = reg_wdata[5];
+
+ assign recov_err_code_ml_measure_err_wd = reg_wdata[6];
+
+ assign recov_err_code_smc_measure_err_wd = reg_wdata[7];
+
+ assign recov_err_code_usb_measure_err_wd = reg_wdata[8];
+
+ assign recov_err_code_video_measure_err_wd = reg_wdata[9];
+
+ assign recov_err_code_audio_timeout_err_wd = reg_wdata[10];
+
+ assign recov_err_code_io_timeout_err_wd = reg_wdata[11];
+
+ assign recov_err_code_io_div2_timeout_err_wd = reg_wdata[12];
+
+ assign recov_err_code_io_div4_timeout_err_wd = reg_wdata[13];
+
+ assign recov_err_code_main_timeout_err_wd = reg_wdata[14];
+
+ assign recov_err_code_ml_timeout_err_wd = reg_wdata[15];
+
+ assign recov_err_code_smc_timeout_err_wd = reg_wdata[16];
+
+ assign recov_err_code_usb_timeout_err_wd = reg_wdata[17];
+
+ assign recov_err_code_video_timeout_err_wd = reg_wdata[18];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = alert_test_we;
+ reg_we_check[1] = extclk_ctrl_regwen_we;
+ reg_we_check[2] = extclk_ctrl_gated_we;
+ reg_we_check[3] = 1'b0;
+ reg_we_check[4] = jitter_regwen_we;
+ reg_we_check[5] = jitter_enable_we;
+ reg_we_check[6] = clk_enables_we;
+ reg_we_check[7] = clk_hints_we;
+ reg_we_check[8] = 1'b0;
+ reg_we_check[9] = measure_ctrl_regwen_we;
+ reg_we_check[10] = audio_meas_ctrl_en_we;
+ reg_we_check[11] = audio_meas_ctrl_shadowed_we;
+ reg_we_check[12] = io_meas_ctrl_en_we;
+ reg_we_check[13] = io_meas_ctrl_shadowed_we;
+ reg_we_check[14] = io_div2_meas_ctrl_en_we;
+ reg_we_check[15] = io_div2_meas_ctrl_shadowed_we;
+ reg_we_check[16] = io_div4_meas_ctrl_en_we;
+ reg_we_check[17] = io_div4_meas_ctrl_shadowed_we;
+ reg_we_check[18] = main_meas_ctrl_en_we;
+ reg_we_check[19] = main_meas_ctrl_shadowed_we;
+ reg_we_check[20] = ml_meas_ctrl_en_we;
+ reg_we_check[21] = ml_meas_ctrl_shadowed_we;
+ reg_we_check[22] = smc_meas_ctrl_en_we;
+ reg_we_check[23] = smc_meas_ctrl_shadowed_we;
+ reg_we_check[24] = usb_meas_ctrl_en_we;
+ reg_we_check[25] = usb_meas_ctrl_shadowed_we;
+ reg_we_check[26] = video_meas_ctrl_en_we;
+ reg_we_check[27] = video_meas_ctrl_shadowed_we;
+ reg_we_check[28] = recov_err_code_we;
+ reg_we_check[29] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = extclk_ctrl_regwen_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
+ reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[3:0] = extclk_status_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = jitter_regwen_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[3:0] = jitter_enable_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
+ reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
+ reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
+ reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
+ reg_rdata_next[4] = clk_enables_clk_video_peri_en_qs;
+ reg_rdata_next[5] = clk_enables_clk_ml_peri_en_qs;
+ reg_rdata_next[6] = clk_enables_clk_audio_peri_en_qs;
+ reg_rdata_next[7] = clk_enables_clk_smc_peri_en_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
+ reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
+ reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
+ reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
+ reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
+ reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
+ reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = measure_ctrl_regwen_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next = DW'(audio_meas_ctrl_en_qs);
+ end
+ addr_hit[11]: begin
+ reg_rdata_next = DW'(audio_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[12]: begin
+ reg_rdata_next = DW'(io_meas_ctrl_en_qs);
+ end
+ addr_hit[13]: begin
+ reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[14]: begin
+ reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
+ end
+ addr_hit[15]: begin
+ reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[16]: begin
+ reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
+ end
+ addr_hit[17]: begin
+ reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[18]: begin
+ reg_rdata_next = DW'(main_meas_ctrl_en_qs);
+ end
+ addr_hit[19]: begin
+ reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[20]: begin
+ reg_rdata_next = DW'(ml_meas_ctrl_en_qs);
+ end
+ addr_hit[21]: begin
+ reg_rdata_next = DW'(ml_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[22]: begin
+ reg_rdata_next = DW'(smc_meas_ctrl_en_qs);
+ end
+ addr_hit[23]: begin
+ reg_rdata_next = DW'(smc_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[24]: begin
+ reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
+ end
+ addr_hit[25]: begin
+ reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[26]: begin
+ reg_rdata_next = DW'(video_meas_ctrl_en_qs);
+ end
+ addr_hit[27]: begin
+ reg_rdata_next = DW'(video_meas_ctrl_shadowed_qs);
+ end
+ addr_hit[28]: begin
+ reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
+ reg_rdata_next[1] = recov_err_code_audio_measure_err_qs;
+ reg_rdata_next[2] = recov_err_code_io_measure_err_qs;
+ reg_rdata_next[3] = recov_err_code_io_div2_measure_err_qs;
+ reg_rdata_next[4] = recov_err_code_io_div4_measure_err_qs;
+ reg_rdata_next[5] = recov_err_code_main_measure_err_qs;
+ reg_rdata_next[6] = recov_err_code_ml_measure_err_qs;
+ reg_rdata_next[7] = recov_err_code_smc_measure_err_qs;
+ reg_rdata_next[8] = recov_err_code_usb_measure_err_qs;
+ reg_rdata_next[9] = recov_err_code_video_measure_err_qs;
+ reg_rdata_next[10] = recov_err_code_audio_timeout_err_qs;
+ reg_rdata_next[11] = recov_err_code_io_timeout_err_qs;
+ reg_rdata_next[12] = recov_err_code_io_div2_timeout_err_qs;
+ reg_rdata_next[13] = recov_err_code_io_div4_timeout_err_qs;
+ reg_rdata_next[14] = recov_err_code_main_timeout_err_qs;
+ reg_rdata_next[15] = recov_err_code_ml_timeout_err_qs;
+ reg_rdata_next[16] = recov_err_code_smc_timeout_err_qs;
+ reg_rdata_next[17] = recov_err_code_usb_timeout_err_qs;
+ reg_rdata_next[18] = recov_err_code_video_timeout_err_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
+ reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
+ reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ logic rst_done;
+ logic shadow_rst_done;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rst_done <= '0;
+ end else begin
+ rst_done <= 1'b1;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
+ if (!rst_shadowed_ni) begin
+ shadow_rst_done <= '0;
+ end else begin
+ shadow_rst_done <= 1'b1;
+ end
+ end
+
+ // both shadow and normal resets have been released
+ assign shadow_busy = ~(rst_done & shadow_rst_done);
+
+ // Collect up storage and update errors
+ assign shadowed_storage_err_o = |{
+ audio_meas_ctrl_shadowed_hi_storage_err,
+ audio_meas_ctrl_shadowed_lo_storage_err,
+ io_meas_ctrl_shadowed_hi_storage_err,
+ io_meas_ctrl_shadowed_lo_storage_err,
+ io_div2_meas_ctrl_shadowed_hi_storage_err,
+ io_div2_meas_ctrl_shadowed_lo_storage_err,
+ io_div4_meas_ctrl_shadowed_hi_storage_err,
+ io_div4_meas_ctrl_shadowed_lo_storage_err,
+ main_meas_ctrl_shadowed_hi_storage_err,
+ main_meas_ctrl_shadowed_lo_storage_err,
+ ml_meas_ctrl_shadowed_hi_storage_err,
+ ml_meas_ctrl_shadowed_lo_storage_err,
+ smc_meas_ctrl_shadowed_hi_storage_err,
+ smc_meas_ctrl_shadowed_lo_storage_err,
+ usb_meas_ctrl_shadowed_hi_storage_err,
+ usb_meas_ctrl_shadowed_lo_storage_err,
+ video_meas_ctrl_shadowed_hi_storage_err,
+ video_meas_ctrl_shadowed_lo_storage_err
+ };
+ assign shadowed_update_err_o = |{
+ audio_meas_ctrl_shadowed_hi_update_err,
+ audio_meas_ctrl_shadowed_lo_update_err,
+ io_meas_ctrl_shadowed_hi_update_err,
+ io_meas_ctrl_shadowed_lo_update_err,
+ io_div2_meas_ctrl_shadowed_hi_update_err,
+ io_div2_meas_ctrl_shadowed_lo_update_err,
+ io_div4_meas_ctrl_shadowed_hi_update_err,
+ io_div4_meas_ctrl_shadowed_lo_update_err,
+ main_meas_ctrl_shadowed_hi_update_err,
+ main_meas_ctrl_shadowed_lo_update_err,
+ ml_meas_ctrl_shadowed_hi_update_err,
+ ml_meas_ctrl_shadowed_lo_update_err,
+ smc_meas_ctrl_shadowed_hi_update_err,
+ smc_meas_ctrl_shadowed_lo_update_err,
+ usb_meas_ctrl_shadowed_hi_update_err,
+ usb_meas_ctrl_shadowed_lo_update_err,
+ video_meas_ctrl_shadowed_hi_update_err,
+ video_meas_ctrl_shadowed_lo_update_err
+ };
+
+ // register busy
+ logic reg_busy_sel;
+ assign reg_busy = reg_busy_sel | shadow_busy;
+ always_comb begin
+ reg_busy_sel = '0;
+ unique case (1'b1)
+ addr_hit[10]: begin
+ reg_busy_sel = audio_meas_ctrl_en_busy;
+ end
+ addr_hit[11]: begin
+ reg_busy_sel = audio_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[12]: begin
+ reg_busy_sel = io_meas_ctrl_en_busy;
+ end
+ addr_hit[13]: begin
+ reg_busy_sel = io_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[14]: begin
+ reg_busy_sel = io_div2_meas_ctrl_en_busy;
+ end
+ addr_hit[15]: begin
+ reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[16]: begin
+ reg_busy_sel = io_div4_meas_ctrl_en_busy;
+ end
+ addr_hit[17]: begin
+ reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[18]: begin
+ reg_busy_sel = main_meas_ctrl_en_busy;
+ end
+ addr_hit[19]: begin
+ reg_busy_sel = main_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[20]: begin
+ reg_busy_sel = ml_meas_ctrl_en_busy;
+ end
+ addr_hit[21]: begin
+ reg_busy_sel = ml_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[22]: begin
+ reg_busy_sel = smc_meas_ctrl_en_busy;
+ end
+ addr_hit[23]: begin
+ reg_busy_sel = smc_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[24]: begin
+ reg_busy_sel = usb_meas_ctrl_en_busy;
+ end
+ addr_hit[25]: begin
+ reg_busy_sel = usb_meas_ctrl_shadowed_busy;
+ end
+ addr_hit[26]: begin
+ reg_busy_sel = video_meas_ctrl_en_busy;
+ end
+ addr_hit[27]: begin
+ reg_busy_sel = video_meas_ctrl_shadowed_busy;
+ end
+ default: begin
+ reg_busy_sel = '0;
+ end
+ endcase
+ end
+
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
new file mode 100644
index 0000000..fbb8b3a
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -0,0 +1,3121 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+
+
+{
+ name: "flash_ctrl",
+ human_name: "Flash Controller",
+ one_line_desc: "Interfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe",
+ one_paragraph_desc: '''
+ Flash Controller interfaces the integrated, non-volatile flash memory with software and other hardware components in the system, such as Life Cycle Controller, Key Manager, and OTP Controller.
+ It consists of the open source flash controller that interfaces with a third party flash module.
+ The protocol controller handles read, program, and erase requests, as well as life cycle RMA entry.
+ It supports differentiation between informational and data flash partitions, flash memory protection at page boundaries, and the handling of key manager secrets inaccessible to software.
+ The actual physical controller is highly parameterized (number of banks, number of pages for each bank, number of words and word size for each page, and number of read buffers) and supports XEX scrambling configurable by software, as well as two types of ECC support configurable on a page boundary.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv"
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_flash_ctrl",
+ revisions: [
+ {
+ version: "0.1",
+ life_stage: "L1",
+ design_stage: "D1",
+ verification_stage: "V1",
+ commit_id: "7049fd0d5d48e20772f8ebf32b240faa0dad5528",
+ },
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2S",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ },
+ ]
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_otp_i", reset: "rst_otp_ni"}
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device", name: "core" }
+ { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top"}
+ { protocol: "tlul", direction: "device", name: "mem" }
+ ],
+ available_input_list: [
+ { name: "tck", desc: "jtag clock" },
+ { name: "tms", desc: "jtag tms" },
+ { name: "tdi", desc: "jtag input" },
+ ],
+ available_output_list: [
+ { name: "tdo", desc: "jtag output" },
+ ],
+ interrupt_list: [
+ { name: "prog_empty", desc: "Program FIFO empty" },
+ { name: "prog_lvl", desc: "Program FIFO drained to level" },
+ { name: "rd_full", desc: "Read FIFO full" },
+ { name: "rd_lvl", desc: "Read FIFO filled to level" },
+ { name: "op_done", desc: "Operation complete" },
+ { name: "corr_err", desc: "Correctable error encountered"},
+ ],
+
+ alert_list: [
+ { name: "recov_err",
+ desc: "flash recoverable errors",
+ },
+ { name: "fatal_std_err",
+ desc: "flash standard fatal errors"
+ },
+ { name: "fatal_err",
+ desc: "flash fatal errors"
+ },
+ { name: "fatal_prim_flash_alert",
+ desc: "Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface."
+ },
+ { name: "recov_prim_flash_alert",
+ desc: "Recoverable alert triggered inside the flash primitive."
+ }
+ ],
+
+ // Define flash_ctrl <-> flash_phy struct package
+ inter_signal_list: [
+ { struct: "flash_otp_key",
+ type: "req_rsp",
+ name: "otp",
+ act: "req",
+ package: "otp_ctrl_pkg"
+ },
+
+ { struct: "lc_tx",
+ package: "lc_ctrl_pkg",
+ type: "uni"
+ act: "rcv"
+ name: "lc_nvm_debug_en"
+ },
+
+ { struct: "mubi4"
+ package: "prim_mubi_pkg"
+ type: "uni"
+ act: "rcv"
+ name: "flash_bist_enable"
+ },
+
+ { struct: "logic"
+ package: ""
+ type: "uni"
+ act: "rcv"
+ name: "flash_power_down_h"
+ },
+ { struct: "logic"
+ package: ""
+ type: "uni"
+ act: "rcv"
+ name: "flash_power_ready_h"
+ },
+ { struct: "",
+ package: "",
+ width: "2",
+ type: "io"
+ act: "none"
+ name: "flash_test_mode_a"
+ },
+ { struct: "",
+ package: "",
+ type: "io"
+ act: "none"
+ name: "flash_test_voltage_h"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_creator_seed_sw_rw_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_owner_seed_sw_rw_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_iso_part_sw_rd_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_iso_part_sw_wr_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_seed_hw_rd_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_escalate_en"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "rma_req"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "rma_ack"
+ act: "req"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_flash_rma_seed"
+ type: "uni"
+ name: "rma_seed"
+ act: "rcv"
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "pwr_flash",
+ type: "uni",
+ name: "pwrmgr",
+ act: "req",
+ package: "pwrmgr_pkg"
+ },
+
+ { struct: "keymgr_flash",
+ type: "uni",
+ name: "keymgr",
+ act: "req",
+ package: "flash_ctrl_pkg"
+ }
+
+ { struct: "ast_obs_ctrl",
+ type: "uni",
+ name: "obs_ctrl",
+ act: "rcv",
+ package: "ast_pkg"
+ }
+
+ { struct: "logic",
+ type: "uni",
+ name: "fla_obs",
+ act: "req",
+ width: "8",
+ package: ""
+ }
+
+ ],
+ countermeasures: [
+ { name: "REG.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "HOST.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "MEM.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "SCRAMBLE.KEY.SIDELOAD",
+ desc: "The scrambling key is sideloaded from OTP and thus unreadable by SW."
+ }
+ { name: "LC_CTRL.INTERSIG.MUBI",
+ desc: '''
+ Life cycle control signals are used control information partition access
+ and flash debug access. See secret information partition, isolated information partitions
+ and jtag connection in documentation for more details.
+ '''
+ }
+ { name: "CTRL.CONFIG.REGWEN",
+ desc: "Configurations cannot be changed when an operation is ongoing."
+ }
+ { name: "DATA_REGIONS.CONFIG.REGWEN",
+ desc: "Each data region has a configurable regwen."
+ }
+ { name: "DATA_REGIONS.CONFIG.SHADOW",
+ desc: "Data region configuration is shadowed."
+ }
+ { name: "INFO_REGIONS.CONFIG.REGWEN",
+ desc: "Each info page of each type in each bank has separate regwen."
+ }
+ { name: "INFO_REGIONS.CONFIG.SHADOW",
+ desc: "Each info page is shadowed."
+ }
+ { name: "BANK.CONFIG.REGWEN",
+ desc: "Each bank has separate regwen for bank erase."
+ }
+ { name: "BANK.CONFIG.SHADOW",
+ desc: "Each bank has separate regwen for bank erase."
+ }
+ { name: "MEM.CTRL.GLOBAL_ESC",
+ desc: "Global escalation causes memory to no longer be accessible."
+ }
+ { name: "MEM.CTRL.LOCAL_ESC",
+ desc: '''
+ A subset of fatal errors cause memory to no longer be accessible.
+ This subset is defined in !!STD_FAULT_STATUS.
+ '''
+ }
+ { name: "MEM_DISABLE.CONFIG.MUBI",
+ desc: '''
+ Software control for flash disable is multibit.
+ The register is !!DIS.
+ '''
+ }
+ { name: "EXEC.CONFIG.REDUN",
+ desc: '''
+ Software control for flash enable is 32-bit constant.
+ The register is !!EXEC.
+ '''
+ }
+ { name: "MEM.SCRAMBLE",
+ desc: '''
+ The flash supports XEX scrambling.
+ The cipher used is PRINCE.
+ The scrambling scheme is enabled by software, please see flash scrambling in documentation for more details.
+ '''
+ }
+ { name: "MEM.INTEGRITY",
+ desc: '''
+ The flash supports two layers of ECC integrity: one layer is for integrity,
+ and the other layer is for reliability.
+ These ECCs are enabled and disabled together by software.
+ Please see Flash ECC in the documentation for more details.
+ '''
+ }
+ { name: "RMA_ENTRY.MEM.SEC_WIPE",
+ desc: "RMA entry entry wipes flash memory with random data."
+ }
+ { name: "CTRL.FSM.SPARSE",
+ desc: '''
+ RMA handling FSMs in flash_ctrl_lcmgr are sparsely encoded.
+ FSM in flash_ctrl_arb is sparsely encoded.
+ '''
+ }
+ { name: "PHY.FSM.SPARSE",
+ desc: "PHY FSMs are sparsely encoded."
+ }
+ { name: "PHY_PROG.FSM.SPARSE",
+ desc: "PHY program FSMs are sparsely encoded."
+ }
+ { name: "CTR.REDUN",
+ desc: '''
+ flash_ctrl_lcmgr handling counters are redundantly encoded.
+ This includes seed count and address count used during seed reading phase,
+ as well as word count, page count and wipe index in RMA entry phase.
+ '''
+ }
+ { name: "PHY_ARBITER.CTRL.REDUN",
+ desc: '''
+ The phy arbiter for controller and host is redundant.
+ The arbiter has two instance underneath that are constantly compared to each other.
+ '''
+ }
+ { name: "PHY_HOST_GRANT.CTRL.CONSISTENCY",
+ desc: '''
+ The host grant is consistency checked.
+ If the host is ever granted with info partition access, it is an error.
+ If the host is ever granted at the same time as a program/erase operation, it is an error.
+ '''
+ }
+ { name: "PHY_ACK.CTRL.CONSISTENCY",
+ desc: '''
+ If the host or controller ever receive an unexpeced transaction acknowledge, it is an error.
+ '''
+ }
+ { name: "FIFO.CTR.REDUN",
+ desc: "The FIFO pointers of several FIFOs are implemented with duplicate counters."
+ }
+ { name: "MEM_TL_LC_GATE.FSM.SPARSE",
+ desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded."
+ }
+ { name: "PROG_TL_LC_GATE.FSM.SPARSE",
+ desc: "The control FSM inside the TL-UL gating primitive is sparsely encoded."
+ }
+ ]
+
+ scan: "true", // Enable `scanmode_i` port
+ scan_en: "true", // Enable `scan_en_i` port
+ scan_reset: "true", // Enable `scan_rst_ni` port
+ param_list: [
+ // The reg parameters can be modified directly through top_*.hjson.
+ // The template will automatically propagate the appropriate values.
+
+ // Random netlist constants
+ { name: "RndCnstAddrKey",
+ desc: "Compile-time random bits for default address key",
+ type: "flash_ctrl_pkg::flash_key_t"
+ randcount: "128",
+ randtype: "data", // randomize randcount databits
+ },
+ { name: "RndCnstDataKey",
+ desc: "Compile-time random bits for default data key",
+ type: "flash_ctrl_pkg::flash_key_t"
+ randcount: "128",
+ randtype: "data", // randomize randcount databits
+ },
+ { name: "RndCnstAllSeeds",
+ desc: "Compile-time random bits for default seeds",
+ type: "flash_ctrl_pkg::all_seeds_t"
+ randcount: "512",
+ randtype: "data", // randomize randcount databits
+ },
+ { name: "RndCnstLfsrSeed",
+ desc: "Compile-time random bits for initial LFSR seed",
+ type: "flash_ctrl_pkg::lfsr_seed_t"
+ randcount: "32",
+ randtype: "data",
+ },
+ { name: "RndCnstLfsrPerm",
+ desc: "Compile-time random permutation for LFSR output",
+ type: "flash_ctrl_pkg::lfsr_perm_t"
+ randcount: "32",
+ randtype: "perm",
+ },
+
+ { name: "RegNumBanks",
+ desc: "Number of flash banks",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "RegPagesPerBank",
+ desc: "Number of pages per bank",
+ type: "int",
+ default: "256",
+ local: "true"
+ },
+
+ { name: "RegBusPgmResBytes",
+ desc: "Program resolution window in bytes",
+ type: "int",
+ default: "64",
+ local: "true"
+ },
+
+ { name: "RegPageWidth",
+ desc: "Number of bits needed to represent the pages within a bank",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ { name: "RegBankWidth",
+ desc: "Number of bits needed to represent the number of banks",
+ type: "int",
+ default: "1",
+ local: "true"
+ },
+
+ { name: "NumRegions",
+ desc: "Number of configurable flash regions",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ // The following parameters are derived from topgen and should not be
+ // directly modified.
+ { name: "NumInfoTypes",
+ desc: "Number of info partition types",
+ type: "int",
+ default: "3",
+ local: "true"
+ },
+ { name: "NumInfos0",
+ desc: "Number of configurable flash info pages for info type 0",
+ type: "int",
+ default: "10",
+ local: "true"
+ },
+ { name: "NumInfos1",
+ desc: "Number of configurable flash info pages for info type 1",
+ type: "int",
+ default: "1",
+ local: "true"
+ },
+ { name: "NumInfos2",
+ desc: "Number of configurable flash info pages for info type 2",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "WordsPerPage",
+ desc: "Number of words per page",
+ type: "int",
+ default: "256",
+ local: "true"
+ },
+
+ { name: "BytesPerWord",
+ desc: "Number of bytes per word",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+
+ { name: "BytesPerPage",
+ desc: "Number of bytes per page",
+ type: "int",
+ default: "2048",
+ local: "true"
+ },
+
+ { name: "BytesPerBank",
+ desc: "Number of bytes per bank",
+ type: "int",
+ default: "524288",
+ local: "true"
+ },
+
+ // hex value of 0xa26a38f7
+ { name: "ExecEn",
+ desc: "Constant value that enables flash execution",
+ type: "int unsigned"
+ default: "2724870391",
+ local: "true"
+ },
+
+ { name: "SecScrambleEn",
+ desc: "Compile-time option to enable flash scrambling",
+ type: "bit",
+ default: "1",
+ local: "false",
+ expose: "true",
+ },
+
+ // Program FIFO depth
+ { name: "ProgFifoDepth",
+ desc: "Depth of program fifo",
+ type: "int"
+ default: "16",
+ local: "false",
+ expose: "true"
+ },
+
+ { name: "RdFifoDepth",
+ desc: "Depth of read fifo",
+ type: "int"
+ default: "16",
+ local: "false",
+ expose: "true"
+ },
+
+ // Maximum FIFO depth allowed
+ { name: "MaxFifoDepth",
+ desc: "Maximum depth for read / program fifos",
+ type: "int"
+ default: "16",
+ },
+
+ { name: "MaxFifoWidth",
+ desc: "Maximum depth for read / program fifos",
+ type: "int"
+ default: "5",
+ },
+ ],
+
+ regwidth: "32",
+ registers: {
+ core: [
+ { name: "DIS",
+ desc: "Disable flash functionality",
+ swaccess: "rw0c",
+ hwaccess: "hro",
+ fields: [
+ { bits: "3:0",
+ name: "VAL",
+ mubi: true,
+ desc: '''
+ Disables flash functionality completely.
+ This is a shortcut mechanism used by the software to completely
+ kill flash in case of emergency.
+
+ Since this register is rw0c instead of rw, to disable, write any value in the form of
+ 0xxx or xxx0, where x could be either 0 or 1.
+
+ '''
+ resval: false,
+ },
+ ]
+ tags: [// Dont touch disable, it has several side effects on the system
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+
+ { name: "EXEC",
+ desc: "Controls whether flash can be used for code execution fetches",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "31:0",
+ name: "EN",
+ desc: '''
+ A value of 0xa26a38f7 allows flash to be used for code execution.
+ Any other value prevents code execution.
+ '''
+ resval: 0
+ },
+ ]
+ },
+
+ { name: "INIT",
+ desc: "Controller init register",
+ swaccess: "rw1s",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Initializes the flash controller.
+
+ During the initialization process, the flash controller requests the address and data
+ scramble keys and reads out the root seeds stored in flash before allowing other usage
+ of the flash controller.
+
+ When the initialization sequence is complete, the flash read buffers are enabled
+ and turned on.
+ '''
+ resval: "0"
+ tags: [// Dont init flash, it has several side effects on the status bits
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+ ]
+ },
+
+ { name: "CTRL_REGWEN",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ desc: '''
+ Controls the configurability of the !!CONTROL register.
+
+ This register ensures the contents of !!CONTROL cannot be changed by software once a flash
+ operation has begun.
+
+ It unlocks whenever the existing flash operation completes, regardless of success or error.
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Configuration enable.
+
+ This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated.
+ When the controller completes the flash operation, this bit is set
+ back to 1 to allow software configuration of !!CONTROL
+ ''',
+ resval: "1",
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+
+ { name: "CONTROL",
+ desc: "Control register",
+ regwen: "CTRL_REGWEN",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ hwaccess: "hrw",
+ name: "START",
+ desc: '''
+ Start flash transaction. This bit shall only be set at the same time or after the other
+ fields of the !!CONTROL register and !!ADDR have been programmed.
+ '''
+ resval: "0"
+ tags: [// Dont enable flash - it causes several side-effects.
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+ { bits: "5:4",
+ name: "OP",
+ desc: "Flash operation selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Read",
+ desc: '''
+ Flash Read.
+
+ Read desired number of flash words
+ '''
+ },
+ { value: "1",
+ name: "Prog",
+ desc: '''
+ Flash Program.
+
+ Program desired number of flash words
+ '''
+ },
+ { value: "2",
+ name: "Erase",
+ desc: '''
+ Flash Erase Operation.
+
+ See ERASE_SEL for details on erase operation
+ '''
+ },
+ ]
+ },
+
+ { bits: "6",
+ name: "PROG_SEL",
+ desc: "Flash program operation type selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Normal program",
+ desc: '''
+ Normal program operation to the flash
+ '''
+ },
+ { value: "1",
+ name: "Program repair",
+ desc: '''
+ Repair program operation to the flash. Whether this is actually
+ supported depends on the underlying flash memory.
+ '''
+ },
+ ]
+ },
+
+ { bits: "7",
+ name: "ERASE_SEL",
+ desc: "Flash erase operation type selection",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Page Erase",
+ desc: '''
+ Erase 1 page of flash
+ '''
+ },
+ { value: "1",
+ name: "Bank Erase",
+ desc: '''
+ Erase 1 bank of flash
+ '''
+ },
+ ]
+ },
+ { bits: "8",
+ name: "PARTITION_SEL",
+ desc: '''
+ When doing a read, program or page erase operation, selects either info or data partition for operation.
+ When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller.
+ When 1, select info partition - this is the portion of flash that is only accessible by the controller.
+
+ When doing a bank erase operation, selects info partition also for erase.
+ When 0, bank erase only erases data partition.
+ When 1, bank erase erases data partition and info partition.
+ '''
+ resval: "0"
+ },
+ { bits: "10:9",
+ name: "INFO_SEL",
+ desc: '''
+ Informational partions can have multiple types.
+
+ This field selects the info type to be accessed.
+ '''
+ resval: "0"
+ },
+ { bits: "27:16",
+ name: "NUM",
+ desc: '''
+ One fewer than the number of bus words the flash operation should read or program.
+ For example, to read 10 words, software should program this field with the value 9.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+ { name: "ADDR",
+ desc: "Address for flash operation",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CTRL_REGWEN",
+ resval: "0",
+ fields: [
+ { bits: "19:0",
+ name: "START",
+ desc: '''
+ Start address of a flash transaction. This is a byte address relative to the flash
+ only. Ie, an address of 0 will access address 0 of the requested partition.
+
+ For read operations, the flash controller will truncate to the closest, lower word
+ aligned address. For example, if 0x13 is supplied, the controller will perform a
+ read at address 0x10.
+
+ Program operations behave similarly, the controller does not have read modified write
+ support.
+
+ For page erases, the controller will truncate to the closest lower page aligned
+ address. Similarly for bank erases, the controller will truncate to the closest
+ lower bank aligned address.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ // Program type
+ { name: "PROG_TYPE_EN",
+ desc: "Enable different program types",
+ regwen: "CTRL_REGWEN",
+ swaccess: "rw0c",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ resval: "1",
+ name: "NORMAL",
+ desc: '''
+ Normal prog type available
+ '''
+ },
+ { bits: "1",
+ resval: "1",
+ name: "REPAIR",
+ desc: '''
+ Repair prog type available
+ '''
+ },
+ ]
+ },
+
+ // erase suspend support
+ { name: "ERASE_SUSPEND",
+ desc: "Suspend erase",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ resval: "0",
+ name: "REQ",
+ desc: '''
+ When 1, request erase suspend.
+ If no erase ongoing, the request is immediately cleared by hardware
+ If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.
+ '''
+ },
+ ],
+ tags: [// Erase suspend must be directly tested
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+
+ // Data partition memory properties region setup
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "REGION_CFG_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumRegions",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Region register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Region locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Region enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "MP_REGION_CFG",
+ desc: "Memory property configuration for data partition",
+ count: "NumRegions",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGION_CFG_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply.
+ If region is disabled, it is not matched against any incoming transaction.
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is integrity checked and reliability ECC enabled.
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "MP_REGION",
+ desc: "Memory base and size configuration for data partition",
+ count: "NumRegions",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGION_CFG_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "8:0",
+ name: "BASE",
+ desc: '''
+ Region base page. Note the granularity is page, not byte or word
+ ''',
+ resval: "0"
+ },
+ { bits: "18:9",
+ name: "SIZE",
+ desc: '''
+ Region size in number of pages.
+ For example, if base is 0 and size is 1, then the region is defined by page 0.
+ If base is 0 and size is 2, then the region is defined by pages 0 and 1.
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ // Default region properties for data partition
+ { name: "DEFAULT_REGION",
+ desc: "Default region properties",
+ swaccess: "rw",
+ hwaccess: "hro",
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "11:8",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ]
+ },
+
+ // Info partition memory properties setup
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO0_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos0",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info0 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO0_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank0,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK0_INFO0_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO1_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos1",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info1 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO1_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank0,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK0_INFO1_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO2_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos2",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info2 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK0_INFO2_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank0,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK0_INFO2_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO0_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos0",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info0 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO0_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank1,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK1_INFO0_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO1_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos1",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info1 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO1_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank1,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK1_INFO1_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO2_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: "NumInfos2",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ compact: false,
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Info2 page write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Page locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Page enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "BANK1_INFO2_PAGE_CFG",
+ desc: '''
+ Memory property configuration for info partition in bank1,
+ Unlike data partition, each page is individually configured.
+ '''
+ count: "NumInfos2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK1_INFO2_REGWEN",
+ regwen_multi: true,
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_err",
+ fields: [
+ { bits: "3:0",
+ name: "EN",
+ mubi: true,
+ desc: '''
+ Region enabled, following fields apply
+ ''',
+ resval: false
+ },
+ { bits: "7:4",
+ name: "RD_EN",
+ mubi: true,
+ desc: '''
+ Region can be read
+ ''',
+ resval: false
+ },
+ { bits: "11:8",
+ name: "PROG_EN",
+ mubi: true,
+ desc: '''
+ Region can be programmed
+ ''',
+ resval: false
+ }
+ { bits: "15:12",
+ name: "ERASE_EN",
+ mubi: true,
+ desc: '''
+ Region can be erased
+ ''',
+ resval: false
+ }
+ { bits: "19:16",
+ name: "SCRAMBLE_EN",
+ mubi: true,
+ desc: '''
+ Region is scramble enabled.
+ ''',
+ resval: false
+ }
+ { bits: "23:20",
+ name: "ECC_EN",
+ mubi: true,
+ desc: '''
+ Region is ECC enabled (both integrity and reliability ECC).
+ ''',
+ resval: false
+ }
+ { bits: "27:24",
+ name: "HE_EN",
+ mubi: true,
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: false
+ }
+ ],
+ },
+ },
+
+ { name: "HW_INFO_CFG_OVERRIDE",
+ desc: "HW interface info configuration rule overrides",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "3:0",
+ name: "SCRAMBLE_DIS",
+ mubi: true,
+ desc: '''
+ The hardwired hardware info configuration rules for scramble enable are logically AND'd with
+ this field.
+ If the hardware rules hardwires scramble to enable, we can disable via software if needed.
+
+ By default this field if false.
+ ''',
+ resval: false
+ }
+ { bits: "7:4",
+ name: "ECC_DIS",
+ mubi: true,
+ desc: '''
+ The hardwired hardware info configuration rules for ECC enable are logically AND'd with
+ this field.
+ If the hardware rules hardwires ECC to enable, we can disable via software if needed.
+
+ By default this field if false.
+ ''',
+ resval: false
+ }
+ ]
+ },
+
+ { name: "BANK_CFG_REGWEN"
+ desc: "Bank configuration registers configuration enable.",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "BANK",
+ resval: "1"
+ desc: "Bank register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Bank locked",
+ desc: '''
+ Bank can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Bank enabled",
+ desc: '''
+ Bank can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "MP_BANK_CFG_SHADOWED",
+ desc: "Memory properties bank configuration",
+ count: "RegNumBanks",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "BANK_CFG_REGWEN",
+ shadowed: "true",
+ update_err_alert: "recov_err",
+ storage_err_alert: "fatal_std_err",
+ fields: [
+ { bits: "0",
+ name: "ERASE_EN",
+ desc: '''
+ Bank wide erase enable
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { name: "OP_STATUS",
+ desc: "Flash Operation Status",
+ swaccess: "rw",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "done",
+ desc: "Flash operation done. Set by HW, cleared by SW" },
+ { bits: "1", name: "err",
+ desc: "Flash operation error. Set by HW, cleared by SW. See !!ERR_CODE for more details."},
+ ]
+ },
+
+ { name: "STATUS",
+ desc: "Flash Controller Status",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "rd_full", desc: "Flash read FIFO full, software must consume data"},
+ { bits: "1", name: "rd_empty", desc: "Flash read FIFO empty", resval: "1"},
+ { bits: "2", name: "prog_full", desc: "Flash program FIFO full"},
+ { bits: "3", name: "prog_empty", desc: "Flash program FIFO empty, software must provide data", resval: "1"},
+ { bits: "4", name: "init_wip", desc: "Flash controller undergoing init, inclusive of phy init"
+ tags: [ // Bit changes immediately after start from reset value to 1b1 due to initialization
+ "excl:CsrAllTests:CsrExclAll"]
+ }
+ { bits: "5", name: "initialized",desc: "Flash controller initialized"
+ tags: [ // Bit changes immediately after start from reset value to 1b1 due to initialization
+ "excl:CsrAllTests:CsrExclAll"]
+ },
+ ]
+ },
+
+ { name: "DEBUG_STATE",
+ desc: "Current flash fsm state",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true"
+ fields: [
+ { bits: "10:0",
+ name: "lcmgr_state",
+ desc: "Current lcmgr interface staet ",
+ tags: [ // Bit changes immediately after start from reset value to 1b1 due to initialization
+ "excl:CsrAllTests:CsrExclAll"]
+ }
+ ]
+ },
+
+ { name: "ERR_CODE",
+ desc: '''
+ Flash error code register.
+ This register tabulates detailed error status of the flash.
+ This is separate from !!OP_STATUS, which is used to indicate the current state of the software initiated
+ flash operation.
+
+ Note, all errors in this register are considered recoverable errors, ie, errors that could have been
+ generated by software.
+ '''
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ name: "op_err",
+ desc: '''
+ Software has supplied an undefined operation.
+ See !!CONTROL.OP for list of valid operations.
+ '''
+ },
+ { bits: "1",
+ name: "mp_err",
+ desc: '''
+ Flash access has encountered an access permission error.
+ Please see !!ERR_ADDR for exact address.
+ This is a synchronous error.
+ '''
+ },
+ { bits: "2",
+ name: "rd_err",
+ desc: '''
+ Flash read has an error.
+ This could be a reliability ECC error or an storage integrity error
+ encountered during a software issued controller read, see !!STD_FAULT_STATUS.
+ See !!ERR_ADDR for exact address.
+ This is a synchronous error.
+ '''
+ },
+ { bits: "3",
+ name: "prog_err",
+ desc: '''
+ Flash program has an error.
+ This could be a program integrity error, see !!STD_FAULT_STATUS.
+ This is a synchronous error.
+ '''
+ },
+ { bits: "4",
+ name: "prog_win_err",
+ desc: '''
+ Flash program has a window resolution error. Ie, the start of program
+ and end of program are in different windows. Please check !!ERR_ADDR.
+ This is a synchronous error.
+ '''
+ },
+ { bits: "5",
+ name: "prog_type_err",
+ desc: '''
+ Flash program selected unavailable type, see !!PROG_TYPE_EN.
+ This is a synchronous error.
+ '''
+ },
+ { bits: "6",
+ name: "update_err",
+ desc: '''
+ A shadow register encountered an update error.
+ This is an asynchronous error.
+ '''
+ },
+ { bits: "7",
+ name: "macro_err",
+ desc: '''
+ A recoverable error has been encountered in the flash macro.
+ Please read the flash macro status registers for more details.
+ '''
+ },
+ ]
+ },
+
+ { name: "STD_FAULT_STATUS",
+ desc: '''
+ This register tabulates standard fault status of the flash.
+
+ These represent errors that occur in the standard structures of the design.
+ For example fsm integrity, counter integrity and tlul integrity.
+ '''
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "reg_intg_err",
+ desc: '''
+ The flash controller encountered a register integrity error.
+ '''
+ },
+ { bits: "1",
+ name: "prog_intg_err",
+ desc: '''
+ The flash controller encountered a program data transmission integrity error.
+ '''
+ },
+ { bits: "2",
+ name: "lcmgr_err",
+ desc: '''
+ The life cycle management interface has encountered a fatal error.
+ The error is either an FSM sparse encoding error or a count error.
+ '''
+ },
+ { bits: "3",
+ name: "lcmgr_intg_err",
+ desc: '''
+ The life cycle management interface has encountered a transmission
+ integrity error. This is an integrity error on the generated integrity
+ during a life cycle management interface read.
+ '''
+ },
+ { bits: "4",
+ name: "arb_fsm_err",
+ desc: '''
+ The arbiter fsm has encountered a sparse encoding error.
+ '''
+ },
+ { bits: "5",
+ name: "storage_err",
+ desc: '''
+ A shadow register encountered a storage error.
+ '''
+ },
+ { bits: "6",
+ name: "phy_fsm_err",
+ desc: '''
+ A flash phy fsm has encountered a sparse encoding error.
+ '''
+ },
+ { bits: "7",
+ name: "ctrl_cnt_err",
+ desc: '''
+ Flash ctrl read/prog has encountered a count error.
+ '''
+ },
+ { bits: "8",
+ name: "fifo_err",
+ desc: '''
+ Flash primitive fifo's have encountered a count error.
+ '''
+ },
+ ]
+ },
+
+ { name: "FAULT_STATUS",
+ desc: '''
+ This register tabulates customized fault status of the flash.
+
+ These are errors that are impossible to have been caused by software or unrecoverable
+ in nature.
+ '''
+ swaccess: "ro",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "op_err",
+ desc: '''
+ The flash life cycle management interface has supplied an undefined operation.
+ See !!CONTROL.OP for list of valid operations.
+ '''
+ },
+ { bits: "1",
+ name: "mp_err",
+ desc: '''
+ The flash life cycle management interface encountered a memory permission error.
+ '''
+ },
+ { bits: "2",
+ name: "rd_err",
+ desc: '''
+ The flash life cycle management interface encountered a read error.
+ This could be a reliability ECC error or an integrity ECC error
+ encountered during a read, see !!STD_FAULT_STATUS for more details.
+ '''
+ },
+ { bits: "3",
+ name: "prog_err",
+ desc: '''
+ The flash life cycle management interface encountered a program error.
+ This could be a program integirty eror, see !!STD_FAULT_STATUS for more details.
+ '''
+ },
+ { bits: "4",
+ name: "prog_win_err",
+ desc: '''
+ The flash life cycle management interface encountered a program resolution error.
+ '''
+ },
+ { bits: "5",
+ name: "prog_type_err",
+ desc: '''
+ The flash life cycle management interface encountered a program type error.
+ A program type not supported by the flash macro was issued.
+ '''
+ },
+ { bits: "6",
+ name: "seed_err",
+ desc: '''
+ The seed reading process encountered an unexpected error.
+ '''
+ },
+ { bits: "7",
+ name: "phy_relbl_err",
+ desc: '''
+ The flash macro encountered a storage reliability ECC error.
+ '''
+ },
+ { bits: "8",
+ name: "phy_storage_err",
+ desc: '''
+ The flash macro encountered a storage integrity ECC error.
+ '''
+ },
+ { bits: "9",
+ name: "spurious_ack",
+ desc: '''
+ The flash emitted an unexpected acknowledgement.
+ '''
+ },
+ { bits: "10",
+ name: "arb_err",
+ desc: '''
+ The phy arbiter encountered inconsistent results.
+ '''
+ },
+ { bits: "11",
+ name: "host_gnt_err",
+ desc: '''
+ A host transaction was granted with illegal properties.
+ '''
+ },
+ ]
+ },
+
+ { name: "ERR_ADDR",
+ desc: "Synchronous error address",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "19:0",
+ resval: 0,
+ },
+ ]
+ },
+
+ { multireg: {
+ cname: "ECC_SINGLE_ERR",
+ name: "ECC_SINGLE_ERR_CNT",
+ desc: "Total number of single bit ECC error count",
+ count: "RegNumBanks",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "7:0",
+ desc: "This count will not wrap when saturated",
+ resval: 0,
+ },
+ ]
+ }
+ },
+
+ { multireg: {
+ cname: "ECC_SINGLE_ERR",
+ name: "ECC_SINGLE_ERR_ADDR",
+ desc: "Latest address of ECC single err",
+ count: "RegNumBanks",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ compact: false,
+ fields: [
+ { bits: "19:0",
+ desc: "Latest single error address for this bank",
+ resval: 0,
+ },
+ ]
+ }
+ }
+
+ { name: "PHY_ALERT_CFG",
+ desc: "Phy alert configuration",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "alert_ack",
+ desc: "Acknowledge flash phy alert"
+ },
+ { bits: "1",
+ name: "alert_trig",
+ desc: "Trigger flash phy alert"
+ }
+ ]
+ tags: [ // alert triggers should be tested by directed tests
+ "excl:CsrAllTests:CsrExclWrite"]
+ },
+
+ { name: "PHY_STATUS",
+ desc: "Flash Phy Status",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ name: "init_wip",
+ desc: "Flash phy controller initializing"
+ tags: [ // Bit changes immediately after start from reset value to 1b1 due to initialization
+ "excl:CsrAllTests:CsrExclAll"]
+ },
+ { bits: "1",
+ name: "prog_normal_avail",
+ resval: "0x1",
+ desc: "Normal program supported"
+ },
+ { bits: "2",
+ name: "prog_repair_avail",
+ resval: "0x1",
+ desc: "Program repair supported"
+ },
+ ]
+ },
+
+ { name: "Scratch",
+ desc: "Flash Controller Scratch",
+ swaccess: "rw",
+ fields: [
+ { bits: "31:0", name: "data", desc: "Flash ctrl scratch register" },
+ ]
+ },
+
+ { name: "FIFO_LVL",
+ desc: "Programmable depth where FIFOs should generate interrupts",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "4:0",
+ name: "PROG",
+ desc: '''
+ When the program FIFO drains to this level, trigger an interrupt.
+ Default value is set such that interrupt does not trigger at reset.
+ '''
+ resval: "0xF"
+ },
+ { bits: "12:8",
+ name: "RD",
+ desc: '''
+ When the read FIFO fills to this level, trigger an interrupt.
+ Default value is set such that interrupt does not trigger at reset.
+ '''
+ resval: "0xF"
+ },
+ ]
+ }
+
+ { name: "FIFO_RST",
+ desc: "Reset for flash controller FIFOs",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Active high resets for both program and read FIFOs. This is especially useful after the controller
+ encounters an error of some kind.
+ This bit will hold the FIFO in reset as long as it is set.
+ '''
+ resval: "0"
+ },
+ ]
+ },
+
+ { name: "CURR_FIFO_LVL",
+ desc: "Current program and read fifo depth",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "4:0",
+ name: "PROG",
+ desc: '''
+ Current program fifo depth
+ '''
+ resval: "0x0"
+ },
+ { bits: "12:8",
+ name: "RD",
+ desc: '''
+ Current read fifo depth
+ '''
+ resval: "0x0"
+ },
+ ]
+ }
+
+ { window: {
+ name: "prog_fifo",
+ items: "1",
+ validbits: "32",
+ data-intg-passthru: "true",
+ byte-write: "false",
+ unusual: "false"
+ swaccess: "wo",
+ desc: '''
+ Flash program FIFO.
+
+ The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed
+ by software after a program operation has been initiated via the !!CONTROL register.
+ This ensures accidental programming of the program FIFO cannot lock up the system.
+ '''
+ },
+ },
+
+ { window: {
+ name: "rd_fifo",
+ items: "1",
+ validbits: "32",
+ data-intg-passthru: "true",
+ byte-write: "false",
+ unusual: "false"
+ swaccess: "ro",
+ desc: '''
+ Flash read FIFO.
+
+ The FIFO is 16 entries of 4B flash words
+ '''
+ },
+ },
+ ],
+
+ prim: [
+ {
+ name: "CSR0_REGWEN",
+ desc: "",
+ fields: [
+ {
+ bits: "0",
+ name: "field0",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ resval: "1",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False"
+ },
+ {
+ name: "CSR1",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "12:8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR2",
+ desc: "",
+ fields: [
+ {
+ bits: "0",
+ name: "field0",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "1",
+ name: "field1",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "2",
+ name: "field2",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "3",
+ name: "field3",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "4",
+ name: "field4",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "5",
+ name: "field5",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "6",
+ name: "field6",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "7",
+ name: "field7",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False"
+ },
+ {
+ name: "CSR3",
+ desc: "",
+ fields: [
+ {
+ bits: "3:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "7:4",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "10:8",
+ name: "field2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "13:11",
+ name: "field3",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "16:14",
+ name: "field4",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "19:17",
+ name: "field5",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "20",
+ name: "field6",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "23:21",
+ name: "field7",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "25:24",
+ name: "field8",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "27:26",
+ name: "field9",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR4",
+ desc: "",
+ fields: [
+ {
+ bits: "2:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "5:3",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "8:6",
+ name: "field2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "11:9",
+ name: "field3",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR5",
+ desc: "",
+ fields: [
+ {
+ bits: "2:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "4:3",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "13:5",
+ name: "field2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "18:14",
+ name: "field3",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "22:19",
+ name: "field4",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR6",
+ desc: "",
+ fields: [
+ {
+ bits: "2:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "5:3",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "13:6",
+ name: "field2",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "16:14",
+ name: "field3",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "18:17",
+ name: "field4",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "20:19",
+ name: "field5",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "22:21",
+ name: "field6",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "23",
+ name: "field7",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "24",
+ name: "field8",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR7",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "16:8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR8",
+ desc: "",
+ fields: [
+ {
+ bits: "31:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR9",
+ desc: "",
+ fields: [
+ {
+ bits: "31:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR10",
+ desc: "",
+ fields: [
+ {
+ bits: "31:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR11",
+ desc: "",
+ fields: [
+ {
+ bits: "31:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR12",
+ desc: "",
+ fields: [
+ {
+ bits: "9:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR13",
+ desc: "",
+ fields: [
+ {
+ bits: "19:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "20",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR14",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR15",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR16",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR17",
+ desc: "",
+ fields: [
+ {
+ bits: "7:0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "8",
+ name: "field1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR18",
+ desc: "",
+ fields: [
+ {
+ bits: "0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR19",
+ desc: "",
+ fields: [
+ {
+ bits: "0",
+ name: "field0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False",
+ regwen: "CSR0_REGWEN"
+ },
+ {
+ name: "CSR20",
+ desc: "",
+ fields: [
+ {
+ bits: "0",
+ name: "field0",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "1",
+ name: "field1",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ },
+ {
+ bits: "2",
+ name: "field2",
+ swaccess: "ro",
+ hwaccess: "hrw",
+ resval: "0",
+ tags: [],
+ desc: "",
+ enum: []
+ }
+ ],
+ hwext: "False",
+ hwqe: "False",
+ hwre: "False",
+ tags: [],
+ shadowed: "False"
+ }
+ ],
+ mem: []
+ }
+}
diff --git a/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson b/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
new file mode 100644
index 0000000..1d5eb57
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
@@ -0,0 +1,201 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../flash_ctrl/data/flash_ctrl.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../flash_ctrl/data/flash_ctrl_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_reg_bus_integrity
+ desc: "Verify the countermeasure(s) REG.BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_host_bus_integrity
+ desc: "Verify the countermeasure(s) HOST.BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_bus_integrity
+ desc: "Verify the countermeasure(s) MEM.BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_scramble_key_sideload
+ desc: "Verify the countermeasure(s) SCRAMBLE.KEY.SIDELOAD."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_lc_ctrl_intersig_mubi
+ desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_ctrl_config_regwen
+ desc: "Verify the countermeasure(s) CTRL.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_data_regions_config_regwen
+ desc: "Verify the countermeasure(s) DATA_REGIONS.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_data_regions_config_shadow
+ desc: "Verify the countermeasure(s) DATA_REGIONS.CONFIG.SHADOW."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_info_regions_config_regwen
+ desc: "Verify the countermeasure(s) INFO_REGIONS.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_info_regions_config_shadow
+ desc: "Verify the countermeasure(s) INFO_REGIONS.CONFIG.SHADOW."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_bank_config_regwen
+ desc: "Verify the countermeasure(s) BANK.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_bank_config_shadow
+ desc: "Verify the countermeasure(s) BANK.CONFIG.SHADOW."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_ctrl_global_esc
+ desc: "Verify the countermeasure(s) MEM.CTRL.GLOBAL_ESC."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_ctrl_local_esc
+ desc: "Verify the countermeasure(s) MEM.CTRL.LOCAL_ESC."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_disable_config_mubi
+ desc: "Verify the countermeasure(s) MEM_DISABLE.CONFIG.MUBI."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_exec_config_redun
+ desc: "Verify the countermeasure(s) EXEC.CONFIG.REDUN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_scramble
+ desc: "Verify the countermeasure(s) MEM.SCRAMBLE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_integrity
+ desc: "Verify the countermeasure(s) MEM.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_rma_entry_mem_sec_wipe
+ desc: "Verify the countermeasure(s) RMA_ENTRY.MEM.SEC_WIPE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_ctrl_fsm_sparse
+ desc: "Verify the countermeasure(s) CTRL.FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_phy_fsm_sparse
+ desc: "Verify the countermeasure(s) PHY.FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_phy_prog_fsm_sparse
+ desc: "Verify the countermeasure(s) PHY_PROG.FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_ctr_redun
+ desc: "Verify the countermeasure(s) CTR.REDUN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_phy_arbiter_ctrl_redun
+ desc: "Verify the countermeasure(s) PHY_ARBITER.CTRL.REDUN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_phy_host_grant_ctrl_consistency
+ desc: "Verify the countermeasure(s) PHY_HOST_GRANT.CTRL.CONSISTENCY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_phy_ack_ctrl_consistency
+ desc: "Verify the countermeasure(s) PHY_ACK.CTRL.CONSISTENCY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_fifo_ctr_redun
+ desc: "Verify the countermeasure(s) FIFO.CTR.REDUN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_tl_lc_gate_fsm_sparse
+ desc: "Verify the countermeasure(s) MEM_TL_LC_GATE.FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_prog_tl_lc_gate_fsm_sparse
+ desc: "Verify the countermeasure(s) PROG_TL_LC_GATE.FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
new file mode 100644
index 0000000..0006367
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -0,0 +1,1515 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller Module
+//
+//
+
+`include "prim_assert.sv"
+
+module flash_ctrl
+ import flash_ctrl_pkg::*; import flash_ctrl_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+ parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
+ parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
+ parameter all_seeds_t RndCnstAllSeeds = RndCnstAllSeedsDefault,
+ parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
+ parameter int ProgFifoDepth = MaxFifoDepth,
+ parameter int RdFifoDepth = MaxFifoDepth,
+ parameter bit SecScrambleEn = 1'b1
+) (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+
+ input clk_otp_i,
+ input rst_otp_ni,
+
+ // life cycle interface
+ // SEC_CM: LC_CTRL.INTERSIG.MUBI
+ input lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_rd_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t core_tl_i,
+ output tlul_pkg::tl_d2h_t core_tl_o,
+ input tlul_pkg::tl_h2d_t prim_tl_i,
+ output tlul_pkg::tl_d2h_t prim_tl_o,
+ input tlul_pkg::tl_h2d_t mem_tl_i,
+ output tlul_pkg::tl_d2h_t mem_tl_o,
+
+ // otp/lc/pwrmgr/keymgr Interface
+ // SEC_CM: SCRAMBLE.KEY.SIDELOAD
+ output otp_ctrl_pkg::flash_otp_key_req_t otp_o,
+ input otp_ctrl_pkg::flash_otp_key_rsp_t otp_i,
+ input lc_ctrl_pkg::lc_tx_t rma_req_i,
+ input lc_ctrl_pkg::lc_flash_rma_seed_t rma_seed_i,
+ output lc_ctrl_pkg::lc_tx_t rma_ack_o,
+ output pwrmgr_pkg::pwr_flash_t pwrmgr_o,
+ output keymgr_flash_t keymgr_o,
+
+ // IOs
+ input cio_tck_i,
+ input cio_tms_i,
+ input cio_tdi_i,
+ output logic cio_tdo_en_o,
+ output logic cio_tdo_o,
+
+ // Interrupts
+ output logic intr_corr_err_o, // Correctable errors encountered
+ output logic intr_prog_empty_o, // Program fifo is empty
+ output logic intr_prog_lvl_o, // Program fifo is empty
+ output logic intr_rd_full_o, // Read fifo is full
+ output logic intr_rd_lvl_o, // Read fifo is full
+ output logic intr_op_done_o, // Requested flash operation (wr/erase) done
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o,
+
+ // Observability
+ input ast_pkg::ast_obs_ctrl_t obs_ctrl_i,
+ output logic [7:0] fla_obs_o,
+
+ // Flash test interface
+ input scan_en_i,
+ input prim_mubi_pkg::mubi4_t scanmode_i,
+ input scan_rst_ni,
+ input prim_mubi_pkg::mubi4_t flash_bist_enable_i,
+ input flash_power_down_h_i,
+ input flash_power_ready_h_i,
+ inout [1:0] flash_test_mode_a_io,
+ inout flash_test_voltage_h_io
+);
+
+ //////////////////////////////////////////////////////////
+ // Double check supplied param is not bigger than allowed
+ //////////////////////////////////////////////////////////
+ `ASSERT_INIT(FifoDepthCheck_A, (ProgFifoDepth <= MaxFifoDepth) &
+ (RdFifoDepth <= MaxFifoDepth))
+
+
+ import flash_ctrl_reg_pkg::*;
+ import prim_mubi_pkg::mubi4_t;
+
+ flash_ctrl_core_reg2hw_t reg2hw;
+ flash_ctrl_core_hw2reg_t hw2reg;
+
+ tlul_pkg::tl_h2d_t tl_win_h2d [2];
+ tlul_pkg::tl_d2h_t tl_win_d2h [2];
+
+ // Register module
+ logic storage_err;
+ logic update_err;
+ logic intg_err;
+ logic eflash_cmd_intg_err;
+ logic tl_gate_intg_err;
+ logic tl_prog_gate_intg_err;
+
+ // SEC_CM: REG.BUS.INTEGRITY
+ // SEC_CM: CTRL.CONFIG.REGWEN
+ // SEC_CM: DATA_REGIONS.CONFIG.REGWEN, DATA_REGIONS.CONFIG.SHADOW
+ // SEC_CM: INFO_REGIONS.CONFIG.REGWEN, INFO_REGIONS.CONFIG.SHADOW
+ // SEC_CM: BANK.CONFIG.REGWEN, BANK.CONFIG.SHADOW
+ flash_ctrl_core_reg_top u_reg_core (
+ .clk_i,
+ .rst_ni,
+ .rst_shadowed_ni,
+
+ .tl_i(core_tl_i),
+ .tl_o(core_tl_o),
+
+ .tl_win_o (tl_win_h2d),
+ .tl_win_i (tl_win_d2h),
+
+ .reg2hw,
+ .hw2reg,
+
+ .shadowed_storage_err_o (storage_err),
+ .shadowed_update_err_o (update_err),
+ .intg_err_o (intg_err),
+
+ .devmode_i (1'b1)
+ );
+
+ bank_cfg_t [NumBanks-1:0] bank_cfgs;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
+
+ flash_ctrl_region_cfg u_region_cfg (
+ .clk_i,
+ .rst_ni,
+ .lc_creator_seed_sw_rw_en_i,
+ .lc_owner_seed_sw_rw_en_i,
+ .lc_iso_part_sw_wr_en_i,
+ .lc_iso_part_sw_rd_en_i,
+ .bank_cfg_i(reg2hw.mp_bank_cfg_shadowed),
+ .region_i(reg2hw.mp_region),
+ .region_cfg_i(reg2hw.mp_region_cfg),
+ .default_cfg_i(reg2hw.default_region),
+ .bank0_info0_cfg_i(reg2hw.bank0_info0_page_cfg),
+ .bank0_info1_cfg_i(reg2hw.bank0_info1_page_cfg),
+ .bank0_info2_cfg_i(reg2hw.bank0_info2_page_cfg),
+ .bank1_info0_cfg_i(reg2hw.bank1_info0_page_cfg),
+ .bank1_info1_cfg_i(reg2hw.bank1_info1_page_cfg),
+ .bank1_info2_cfg_i(reg2hw.bank1_info2_page_cfg),
+ .bank_cfg_o(bank_cfgs),
+ .region_cfgs_o(region_cfgs),
+ .info_page_cfgs_o(info_page_cfgs)
+ );
+
+ // FIFO Connections
+ localparam int ProgDepthW = prim_util_pkg::vbits(ProgFifoDepth+1);
+ localparam int RdDepthW = prim_util_pkg::vbits(RdFifoDepth+1);
+
+ logic prog_fifo_wvalid;
+ logic prog_fifo_wready;
+ logic prog_fifo_rvalid;
+ logic prog_fifo_ren;
+ logic [BusFullWidth-1:0] prog_fifo_wdata;
+ logic [BusFullWidth-1:0] prog_fifo_rdata;
+ logic [ProgDepthW-1:0] prog_fifo_depth;
+
+ // Program Control Connections
+ logic prog_flash_req;
+ logic prog_flash_ovfl;
+ logic [BusAddrW-1:0] prog_flash_addr;
+ logic prog_op_valid;
+
+ // Read Control Connections
+ logic rd_flash_req;
+ logic rd_flash_ovfl;
+ logic [BusAddrW-1:0] rd_flash_addr;
+ logic rd_op_valid;
+ logic rd_ctrl_wen;
+ logic [BusFullWidth-1:0] rd_ctrl_wdata;
+
+
+ // Erase Control Connections
+ logic erase_flash_req;
+ logic [BusAddrW-1:0] erase_flash_addr;
+ flash_erase_e erase_flash_type;
+ logic erase_op_valid;
+
+ // Done / Error signaling from ctrl modules
+ logic prog_done, rd_done, erase_done;
+ flash_ctrl_err_t prog_err, rd_err, erase_err;
+ logic [BusAddrW-1:0] prog_err_addr, rd_err_addr, erase_err_addr;
+
+ // Flash Memory Properties Connections
+ logic [BusAddrW-1:0] flash_addr;
+ logic flash_req;
+ logic flash_rd_done, flash_prog_done, flash_erase_done;
+ logic flash_mp_err;
+ logic [BusFullWidth-1:0] flash_prog_data;
+ logic flash_prog_last;
+ flash_prog_e flash_prog_type;
+ logic [BusFullWidth-1:0] flash_rd_data;
+ logic flash_rd_err;
+ logic flash_phy_busy;
+ logic rd_op;
+ logic prog_op;
+ logic erase_op;
+ flash_lcmgr_phase_e phase;
+
+ // Flash control arbitration connections to hardware interface
+ flash_key_t addr_key;
+ flash_key_t rand_addr_key;
+ flash_key_t data_key;
+ flash_key_t rand_data_key;
+ flash_ctrl_reg2hw_control_reg_t hw_ctrl;
+ logic hw_req;
+ logic [BusAddrByteW-1:0] hw_addr;
+ logic hw_done;
+ flash_ctrl_err_t hw_err;
+ logic hw_wvalid;
+ logic [BusFullWidth-1:0] hw_wdata;
+ logic hw_wready;
+ flash_sel_e if_sel;
+ logic sw_sel;
+ flash_lcmgr_phase_e hw_phase;
+ logic lcmgr_err;
+ logic lcmgr_intg_err;
+ logic arb_fsm_err;
+ logic seed_err;
+
+ // Flash lcmgr interface to direct read fifo
+ logic lcmgr_rready;
+
+ // Flash control arbitration connections to software interface
+ logic sw_ctrl_done;
+ flash_ctrl_err_t sw_ctrl_err;
+
+ // Flash control muxed connections
+ flash_ctrl_reg2hw_control_reg_t muxed_ctrl;
+ logic [BusAddrByteW-1:0] muxed_addr;
+ logic op_start;
+ logic [11:0] op_num_words;
+ logic [BusAddrW-1:0] op_addr;
+ logic [BusAddrW-1:0] ctrl_err_addr;
+ flash_op_e op_type;
+ flash_part_e op_part;
+ logic [InfoTypesWidth-1:0] op_info_sel;
+ flash_erase_e op_erase_type;
+ flash_prog_e op_prog_type;
+
+ logic ctrl_init_busy;
+ logic ctrl_initialized;
+ logic fifo_clr;
+
+ // sw read fifo interface
+ logic sw_rfifo_wen;
+ logic sw_rfifo_wready;
+ logic [BusFullWidth-1:0] sw_rfifo_wdata;
+ logic sw_rfifo_full;
+ logic [RdDepthW-1:0] sw_rfifo_depth;
+ logic sw_rfifo_rvalid;
+ logic sw_rfifo_rready;
+ logic [BusFullWidth-1:0] sw_rfifo_rdata;
+
+ // software tlul interface to read fifo
+ logic adapter_req;
+ logic adapter_rvalid;
+ logic adapter_fifo_err;
+
+ // software tlul interface to prog fifo
+ logic sw_wvalid;
+ logic [BusFullWidth-1:0] sw_wdata;
+ logic sw_wready;
+
+ // lfsr for local entropy usage
+ logic [31:0] rand_val;
+ logic lfsr_en;
+ logic lfsr_seed_en;
+
+ // interface to flash phy
+ flash_rsp_t flash_phy_rsp;
+ flash_req_t flash_phy_req;
+
+ // import commonly used routines
+ import lc_ctrl_pkg::lc_tx_test_true_strict;
+
+ // life cycle connections
+ lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en;
+
+ lc_ctrl_pkg::lc_tx_t dis_access;
+
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_seed_hw_rd_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_seed_hw_rd_en_i),
+ .lc_en_o({lc_seed_hw_rd_en})
+ );
+
+ prim_lfsr #(
+ .EntropyDw(EdnWidth),
+ .LfsrDw(LfsrWidth),
+ .StateOutDw(LfsrWidth),
+ .DefaultSeed(RndCnstLfsrSeed),
+ .StatePermEn(1),
+ .StatePerm(RndCnstLfsrPerm)
+ ) u_lfsr (
+ .clk_i,
+ .rst_ni,
+ .seed_en_i(lfsr_seed_en),
+ .seed_i(rma_seed_i),
+ .lfsr_en_i(lfsr_en),
+ .entropy_i('0),
+ .state_o(rand_val)
+ );
+
+ // flash disable declaration
+ mubi4_t [FlashDisableLast-1:0] flash_disable;
+
+ // flash control arbitration between software and hardware interfaces
+ flash_ctrl_arb u_ctrl_arb (
+ .clk_i,
+ .rst_ni,
+
+ // combined disable
+ .disable_i(flash_disable[ArbFsmDisableIdx]),
+
+ // error output shared by both interfaces
+ .ctrl_err_addr_o(ctrl_err_addr),
+
+ // software interface to rd_ctrl / erase_ctrl
+ .sw_ctrl_i(reg2hw.control),
+ .sw_addr_i(reg2hw.addr.q),
+ .sw_ack_o(sw_ctrl_done),
+ .sw_err_o(sw_ctrl_err),
+
+ // software interface to prog_fifo
+ // if prog operation not selected, software interface
+ // writes have no meaning
+ .sw_wvalid_i(sw_wvalid & prog_op_valid),
+ .sw_wdata_i(sw_wdata),
+ .sw_wready_o(sw_wready),
+
+ // hardware interface to rd_ctrl / erase_ctrl
+ .hw_req_i(hw_req),
+ .hw_ctrl_i(hw_ctrl),
+
+ // hardware interface indicating operation phase
+ .hw_phase_i(hw_phase),
+
+ // hardware works on word address, however software expects byte address
+ .hw_addr_i(hw_addr),
+ .hw_ack_o(hw_done),
+ .hw_err_o(hw_err),
+
+ // hardware interface to rd_fifo
+ .hw_wvalid_i(hw_wvalid),
+ .hw_wdata_i(hw_wdata),
+ .hw_wready_o(hw_wready),
+
+ // hardware interface does not talk to prog_fifo
+
+ // muxed interface to rd_ctrl / erase_ctrl
+ .muxed_ctrl_o(muxed_ctrl),
+ .muxed_addr_o(muxed_addr),
+ .prog_ack_i(prog_done),
+ .prog_err_i(prog_err),
+ .prog_err_addr_i(prog_err_addr),
+ .rd_ack_i(rd_done),
+ .rd_err_i(rd_err),
+ .rd_err_addr_i(rd_err_addr),
+ .erase_ack_i(erase_done),
+ .erase_err_i(erase_err),
+ .erase_err_addr_i(erase_err_addr),
+
+ // muxed interface to prog_fifo
+ .prog_fifo_wvalid_o(prog_fifo_wvalid),
+ .prog_fifo_wdata_o(prog_fifo_wdata),
+ .prog_fifo_wready_i(prog_fifo_wready),
+
+ // flash phy initilization ongoing
+ .flash_phy_busy_i(flash_phy_busy),
+
+ // clear fifos
+ .fifo_clr_o(fifo_clr),
+
+ // phase indication
+ .phase_o(phase),
+
+ // indication that sw has been selected
+ .sel_o(if_sel),
+ .fsm_err_o(arb_fsm_err)
+ );
+
+ assign op_start = muxed_ctrl.start.q;
+ assign op_num_words = muxed_ctrl.num.q;
+ assign op_erase_type = flash_erase_e'(muxed_ctrl.erase_sel.q);
+ assign op_prog_type = flash_prog_e'(muxed_ctrl.prog_sel.q);
+ assign op_addr = muxed_addr[BusByteWidth +: BusAddrW];
+ assign op_type = flash_op_e'(muxed_ctrl.op.q);
+ assign op_part = flash_part_e'(muxed_ctrl.partition_sel.q);
+ assign op_info_sel = muxed_ctrl.info_sel.q;
+ assign rd_op = op_type == FlashOpRead;
+ assign prog_op = op_type == FlashOpProgram;
+ assign erase_op = op_type == FlashOpErase;
+ assign sw_sel = if_sel == SwSel;
+
+ // hardware interface
+ flash_ctrl_lcmgr #(
+ .RndCnstAddrKey(RndCnstAddrKey),
+ .RndCnstDataKey(RndCnstDataKey),
+ .RndCnstAllSeeds(RndCnstAllSeeds)
+ ) u_flash_hw_if (
+ .clk_i,
+ .rst_ni,
+ .clk_otp_i,
+ .rst_otp_ni,
+
+ .init_i(reg2hw.init),
+ .provision_en_i(lc_tx_test_true_strict(lc_seed_hw_rd_en)),
+
+ // combined disable
+ .disable_i(flash_disable[LcMgrDisableIdx]),
+
+ // interface to ctrl arb control ports
+ .ctrl_o(hw_ctrl),
+ .req_o(hw_req),
+ .addr_o(hw_addr),
+ .done_i(hw_done),
+ .err_i(hw_err),
+
+ // interface to ctrl_arb data ports
+ .wready_i(hw_wready),
+ .wvalid_o(hw_wvalid),
+ .wdata_o(hw_wdata),
+
+ // interface to hw interface read fifo
+ .rready_o(lcmgr_rready),
+ .rvalid_i(~sw_sel & rd_ctrl_wen),
+ .rdata_i(rd_ctrl_wdata),
+
+ // external rma request
+ .rma_req_i,
+ .rma_ack_o,
+
+ // outgoing seeds
+ .seeds_o(keymgr_o.seeds),
+ .seed_err_o(seed_err),
+
+ // phase indication
+ .phase_o(hw_phase),
+
+ // phy read buffer enable
+ .rd_buf_en_o(flash_phy_req.rd_buf_en),
+
+ // connection to otp
+ .otp_key_req_o(otp_o),
+ .otp_key_rsp_i(otp_i),
+ .addr_key_o(addr_key),
+ .data_key_o(data_key),
+ .rand_addr_key_o(rand_addr_key),
+ .rand_data_key_o(rand_data_key),
+
+ // entropy interface
+ .edn_req_o(lfsr_seed_en),
+ .edn_ack_i(1'b1),
+ .lfsr_en_o(lfsr_en),
+ .rand_i(rand_val),
+
+ // error indication
+ .fatal_err_o(lcmgr_err),
+ .intg_err_o(lcmgr_intg_err),
+
+ // disable access to flash storage after rma process
+ .dis_access_o(dis_access),
+
+ // init ongoing
+ .init_busy_o(ctrl_init_busy),
+ .initialized_o(ctrl_initialized),
+
+ .debug_state_o(hw2reg.debug_state.d)
+ );
+
+
+
+
+ // Program FIFO
+ // Since the program and read FIFOs are never used at the same time, it should really be one
+ // FIFO with muxed inputs and outputs. This should be addressed once the flash integration
+ // strategy has been identified
+ assign prog_op_valid = op_start & prog_op;
+
+ tlul_pkg::tl_h2d_t prog_tl_h2d;
+ tlul_pkg::tl_d2h_t prog_tl_d2h;
+
+ // the program path also needs an lc gate to error back when flash is disabled.
+ // This is because tlul_adapter_sram does not actually have a way of signaling
+ // write errors, only read errors.
+ // SEC_CM: PROG_TL_LC_GATE.FSM.SPARSE
+ tlul_lc_gate u_prog_tl_gate (
+ .clk_i,
+ .rst_ni,
+ .tl_h2d_i(tl_win_h2d[0]),
+ .tl_d2h_o(tl_win_d2h[0]),
+ .tl_h2d_o(prog_tl_h2d),
+ .tl_d2h_i(prog_tl_d2h),
+ .flush_req_i('0),
+ .flush_ack_o(),
+ .resp_pending_o(),
+ .lc_en_i(lc_ctrl_pkg::mubi4_to_lc_inv(flash_disable[ProgFifoIdx])),
+ .err_o(tl_prog_gate_intg_err)
+ );
+
+ tlul_adapter_sram #(
+ .SramAw(1), //address unused
+ .SramDw(BusWidth),
+ .ByteAccess(0), //flash may not support byte access
+ .ErrOnRead(1), //reads not supported
+ .EnableDataIntgPt(1) //passthrough data integrity
+ ) u_to_prog_fifo (
+ .clk_i,
+ .rst_ni,
+ .tl_i (prog_tl_h2d),
+ .tl_o (prog_tl_d2h),
+ .en_ifetch_i (prim_mubi_pkg::MuBi4False),
+ .req_o (sw_wvalid),
+ .req_type_o (),
+ .gnt_i (sw_wready),
+ .we_o (),
+ .addr_o (),
+ .wmask_o (),
+ .intg_error_o(),
+ .wdata_o (sw_wdata),
+ .rdata_i ('0),
+ .rvalid_i (1'b0),
+ .rerror_i (2'b0)
+ );
+
+ prim_fifo_sync #(
+ .Width(BusFullWidth),
+ .Depth(ProgFifoDepth)
+ ) u_prog_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done),
+ .wvalid_i(prog_fifo_wvalid),
+ .wready_o(prog_fifo_wready),
+ .wdata_i (prog_fifo_wdata),
+ .depth_o (prog_fifo_depth),
+ .full_o (),
+ .rvalid_o(prog_fifo_rvalid),
+ .rready_i(prog_fifo_ren),
+ .rdata_o (prog_fifo_rdata),
+ .err_o ()
+ );
+ assign hw2reg.curr_fifo_lvl.prog.d = MaxFifoWidth'(prog_fifo_depth);
+
+ // Program handler is consumer of prog_fifo
+ logic [1:0] prog_type_en;
+ assign prog_type_en[FlashProgNormal] = flash_phy_rsp.prog_type_avail[FlashProgNormal] &
+ reg2hw.prog_type_en.normal.q;
+ assign prog_type_en[FlashProgRepair] = flash_phy_rsp.prog_type_avail[FlashProgRepair] &
+ reg2hw.prog_type_en.repair.q;
+
+ logic prog_cnt_err;
+ flash_ctrl_prog u_flash_ctrl_prog (
+ .clk_i,
+ .rst_ni,
+
+ // Control interface
+ .op_start_i (prog_op_valid),
+ .op_num_words_i (op_num_words),
+ .op_done_o (prog_done),
+ .op_err_o (prog_err),
+ .op_addr_i (op_addr),
+ .op_addr_oob_i ('0),
+ .op_type_i (op_prog_type),
+ .type_avail_i (prog_type_en),
+ .op_err_addr_o (prog_err_addr),
+ .cnt_err_o (prog_cnt_err),
+
+ // FIFO Interface
+ .data_i (prog_fifo_rdata),
+ .data_rdy_i (prog_fifo_rvalid),
+ .data_rd_o (prog_fifo_ren),
+
+ // Flash Macro Interface
+ .flash_req_o (prog_flash_req),
+ .flash_addr_o (prog_flash_addr),
+ .flash_ovfl_o (prog_flash_ovfl),
+ .flash_data_o (flash_prog_data),
+ .flash_last_o (flash_prog_last),
+ .flash_type_o (flash_prog_type),
+ .flash_done_i (flash_prog_done),
+ .flash_prog_intg_err_i (flash_phy_rsp.prog_intg_err),
+ .flash_mp_err_i (flash_mp_err)
+ );
+
+
+
+ // a read request is seen from software but a read operation is not enabled
+ // AND there are no pending entries to read from the fifo.
+ // This indicates software has issued a read when it should not have.
+ logic rd_no_op_d, rd_no_op_q;
+ logic sw_rd_op;
+ assign sw_rd_op = reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead);
+
+ // If software ever attempts to read when the FIFO is empty AND if it has never
+ // initiated a transaction, OR when flash is disabled, then it is a read that
+ // can never complete, error back immediately.
+ assign rd_no_op_d = adapter_req & ((~sw_rd_op & ~sw_rfifo_rvalid) |
+ (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[RdFifoIdx])));
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ adapter_rvalid <= 1'b0;
+ rd_no_op_q <= 1'b0;
+ end else begin
+ adapter_rvalid <= adapter_req & sw_rfifo_rvalid;
+ rd_no_op_q <= rd_no_op_d;
+ end
+ end
+
+ // tlul adapter represents software's access interface to flash
+ tlul_adapter_sram #(
+ .SramAw(1), //address unused
+ .SramDw(BusWidth),
+ .ByteAccess(0), //flash may not support byte access
+ .ErrOnWrite(1), //writes not supported
+ .EnableDataIntgPt(1),
+ .SecFifoPtr(1) // SEC_CM: FIFO.CTR.REDUN
+ ) u_to_rd_fifo (
+ .clk_i,
+ .rst_ni,
+ .tl_i (tl_win_h2d[1]),
+ .tl_o (tl_win_d2h[1]),
+ .en_ifetch_i (prim_mubi_pkg::MuBi4False),
+ .req_o (adapter_req),
+ .req_type_o (),
+ // if there is no valid read operation, don't hang the
+ // bus, just let things normally return
+ .gnt_i (sw_rfifo_rvalid | rd_no_op_d),
+ .we_o (),
+ .addr_o (),
+ .wmask_o (),
+ .wdata_o (),
+ .intg_error_o(adapter_fifo_err),
+ .rdata_i (sw_rfifo_rdata),
+ .rvalid_i (adapter_rvalid | rd_no_op_q),
+ .rerror_i ({rd_no_op_q, 1'b0})
+ );
+
+ assign sw_rfifo_wen = sw_sel & rd_ctrl_wen;
+ assign sw_rfifo_wdata = rd_ctrl_wdata;
+ assign sw_rfifo_rready = adapter_rvalid;
+
+ // the read fifo below is dedicated to the software read path.
+ prim_fifo_sync #(
+ .Width(BusFullWidth),
+ .Depth(RdFifoDepth)
+ ) u_sw_rd_fifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (reg2hw.fifo_rst.q),
+ .wvalid_i(sw_rfifo_wen),
+ .wready_o(sw_rfifo_wready),
+ .wdata_i (sw_rfifo_wdata),
+ .full_o (sw_rfifo_full),
+ .depth_o (sw_rfifo_depth),
+ .rvalid_o(sw_rfifo_rvalid),
+ .rready_i(sw_rfifo_rready),
+ .rdata_o (sw_rfifo_rdata),
+ .err_o ()
+ );
+ assign hw2reg.curr_fifo_lvl.rd.d = sw_rfifo_depth;
+
+ logic rd_cnt_err;
+ // Read handler is consumer of rd_fifo
+ assign rd_op_valid = op_start & rd_op;
+ flash_ctrl_rd u_flash_ctrl_rd (
+ .clk_i,
+ .rst_ni,
+
+ // To arbiter Interface
+ .op_start_i (rd_op_valid),
+ .op_num_words_i (op_num_words),
+ .op_done_o (rd_done),
+ .op_err_o (rd_err),
+ .op_err_addr_o (rd_err_addr),
+ .op_addr_i (op_addr),
+ .op_addr_oob_i ('0),
+ .cnt_err_o (rd_cnt_err),
+
+ // FIFO Interface
+ .data_rdy_i (sw_sel ? sw_rfifo_wready : lcmgr_rready),
+ .data_o (rd_ctrl_wdata),
+ .data_wr_o (rd_ctrl_wen),
+
+ // Flash Macro Interface
+ .flash_req_o (rd_flash_req),
+ .flash_addr_o (rd_flash_addr),
+ .flash_ovfl_o (rd_flash_ovfl),
+ .flash_data_i (flash_rd_data),
+ .flash_done_i (flash_rd_done),
+ .flash_mp_err_i (flash_mp_err),
+ .flash_rd_err_i (flash_rd_err)
+ );
+
+ // Erase handler does not consume fifo
+ assign erase_op_valid = op_start & erase_op;
+ flash_ctrl_erase u_flash_ctrl_erase (
+ // Software Interface
+ .op_start_i (erase_op_valid),
+ .op_type_i (op_erase_type),
+ .op_done_o (erase_done),
+ .op_err_o (erase_err),
+ .op_addr_i (op_addr),
+ .op_addr_oob_i ('0),
+ .op_err_addr_o (erase_err_addr),
+
+ // Flash Macro Interface
+ .flash_req_o (erase_flash_req),
+ .flash_addr_o (erase_flash_addr),
+ .flash_op_o (erase_flash_type),
+ .flash_done_i (flash_erase_done),
+ .flash_mp_err_i (flash_mp_err)
+ );
+
+ // Final muxing to flash macro module
+ always_comb begin
+ unique case (op_type)
+ FlashOpRead: begin
+ flash_req = rd_flash_req;
+ flash_addr = rd_flash_addr;
+ end
+ FlashOpProgram: begin
+ flash_req = prog_flash_req;
+ flash_addr = prog_flash_addr;
+ end
+ FlashOpErase: begin
+ flash_req = erase_flash_req;
+ flash_addr = erase_flash_addr;
+ end
+ default: begin
+ flash_req = 1'b0;
+ flash_addr = '0;
+ end
+ endcase // unique case (op_type)
+ end
+
+
+
+ //////////////////////////////////////
+ // Info partition properties configuration
+ //////////////////////////////////////
+
+
+ //////////////////////////////////////
+ // flash memory properties
+ //////////////////////////////////////
+ // direct assignment since prog/rd/erase_ctrl do not make use of op_part
+ flash_part_e flash_part_sel;
+ logic [InfoTypesWidth-1:0] flash_info_sel;
+ assign flash_part_sel = op_part;
+ assign flash_info_sel = op_info_sel;
+
+ // tie off hardware clear path
+ assign hw2reg.erase_suspend.d = 1'b0;
+
+ // Flash memory Properties
+ // Memory property is page based and thus should use phy addressing
+ // This should move to flash_phy long term
+ flash_mp u_flash_mp (
+ .clk_i,
+ .rst_ni,
+
+ // disable flash through memory protection
+ .flash_disable_i(flash_disable[MpDisableIdx]),
+
+ // hw info configuration overrides
+ .hw_info_scramble_dis_i(mubi4_t'(reg2hw.hw_info_cfg_override.scramble_dis.q)),
+ .hw_info_ecc_dis_i(mubi4_t'(reg2hw.hw_info_cfg_override.ecc_dis.q)),
+
+ // arbiter interface selection
+ .if_sel_i(if_sel),
+
+ // sw configuration for data partition
+ .region_cfgs_i(region_cfgs),
+ .bank_cfgs_i(bank_cfgs),
+
+ // sw configuration for info partition
+ .info_page_cfgs_i(info_page_cfgs),
+
+ // read / prog / erase controls
+ .req_i(flash_req),
+ .phase_i(phase),
+ .req_addr_i(flash_addr[BusAddrW-1 -: AllPagesW]),
+ .req_part_i(flash_part_sel),
+ .info_sel_i(flash_info_sel),
+ .addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl),
+ .rd_i(rd_op),
+ .prog_i(prog_op),
+ .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
+ .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
+ .erase_suspend_i(reg2hw.erase_suspend),
+ .erase_suspend_done_o(hw2reg.erase_suspend.de),
+ .rd_done_o(flash_rd_done),
+ .prog_done_o(flash_prog_done),
+ .erase_done_o(flash_erase_done),
+ .error_o(flash_mp_err),
+
+ // flash phy interface
+ .req_o(flash_phy_req.req),
+ .scramble_en_o(flash_phy_req.scramble_en),
+ .ecc_en_o(flash_phy_req.ecc_en),
+ .he_en_o(flash_phy_req.he_en),
+ .rd_o(flash_phy_req.rd),
+ .prog_o(flash_phy_req.prog),
+ .pg_erase_o(flash_phy_req.pg_erase),
+ .bk_erase_o(flash_phy_req.bk_erase),
+ .erase_suspend_o(flash_phy_req.erase_suspend),
+ .rd_done_i(flash_phy_rsp.rd_done),
+ .prog_done_i(flash_phy_rsp.prog_done),
+ .erase_done_i(flash_phy_rsp.erase_done)
+ );
+
+
+ // software interface feedback
+ // most values (other than flash_phy_busy) should only update when software operations
+ // are actually selected
+ assign hw2reg.op_status.done.d = 1'b1;
+ assign hw2reg.op_status.done.de = sw_ctrl_done;
+ assign hw2reg.op_status.err.d = 1'b1;
+ assign hw2reg.op_status.err.de = |sw_ctrl_err;
+ assign hw2reg.status.rd_full.d = sw_rfifo_full;
+ assign hw2reg.status.rd_full.de = sw_sel;
+ assign hw2reg.status.rd_empty.d = ~sw_rfifo_rvalid;
+ assign hw2reg.status.rd_empty.de = sw_sel;
+ assign hw2reg.status.prog_full.d = ~prog_fifo_wready;
+ assign hw2reg.status.prog_full.de = sw_sel;
+ assign hw2reg.status.prog_empty.d = ~prog_fifo_rvalid;
+ assign hw2reg.status.prog_empty.de = sw_sel;
+ assign hw2reg.status.init_wip.d = flash_phy_busy | ctrl_init_busy;
+ assign hw2reg.status.init_wip.de = 1'b1;
+ assign hw2reg.status.initialized.d = ctrl_initialized & ~flash_phy_busy;
+ assign hw2reg.status.initialized.de = 1'b1;
+ assign hw2reg.control.start.d = 1'b0;
+ assign hw2reg.control.start.de = sw_ctrl_done;
+ // if software operation selected, based on transaction start
+ // if software operation not selected, software is free to change contents
+ assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1;
+
+ // phy status
+ assign hw2reg.phy_status.init_wip.d = flash_phy_busy;
+ assign hw2reg.phy_status.init_wip.de = 1'b1;
+ assign hw2reg.phy_status.prog_normal_avail.d = flash_phy_rsp.prog_type_avail[FlashProgNormal];
+ assign hw2reg.phy_status.prog_normal_avail.de = 1'b1;
+ assign hw2reg.phy_status.prog_repair_avail.d = flash_phy_rsp.prog_type_avail[FlashProgRepair];
+ assign hw2reg.phy_status.prog_repair_avail.de = 1'b1;
+
+ // Flash Interface
+ assign flash_phy_req.addr = flash_addr;
+ assign flash_phy_req.part = flash_part_sel;
+ assign flash_phy_req.info_sel = flash_info_sel;
+ assign flash_phy_req.prog_type = flash_prog_type;
+ assign flash_phy_req.prog_data = flash_prog_data;
+ assign flash_phy_req.prog_last = flash_prog_last;
+ assign flash_phy_req.region_cfgs = region_cfgs;
+ assign flash_phy_req.addr_key = addr_key;
+ assign flash_phy_req.data_key = data_key;
+ assign flash_phy_req.rand_addr_key = rand_addr_key;
+ assign flash_phy_req.rand_data_key = rand_data_key;
+ assign flash_phy_req.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q;
+ assign flash_phy_req.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q;
+ assign flash_phy_req.jtag_req.tck = cio_tck_i;
+ assign flash_phy_req.jtag_req.tms = cio_tms_i;
+ assign flash_phy_req.jtag_req.tdi = cio_tdi_i;
+ assign flash_phy_req.jtag_req.trst_n = '0;
+ assign cio_tdo_o = flash_phy_rsp.jtag_rsp.tdo;
+ assign cio_tdo_en_o = flash_phy_rsp.jtag_rsp.tdo_oe;
+ assign flash_rd_err = flash_phy_rsp.rd_err;
+ assign flash_rd_data = flash_phy_rsp.rd_data;
+ assign flash_phy_busy = flash_phy_rsp.init_busy;
+
+
+ // Interface to pwrmgr
+ // flash is not idle as long as there is a stateful operation ongoing
+ logic flash_idle_d;
+ assign flash_idle_d = ~(flash_phy_req.req &
+ (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase));
+
+ prim_flop #(
+ .Width(1),
+ .ResetValue(1'b1)
+ ) u_reg_idle (
+ .clk_i,
+ .rst_ni,
+ .d_i(flash_idle_d),
+ .q_o(pwrmgr_o.flash_idle)
+ );
+
+ //////////////////////////////////////
+ // Alert senders
+ //////////////////////////////////////
+
+
+ logic [NumAlerts-1:0] alert_srcs;
+ logic [NumAlerts-1:0] alert_tests;
+ logic fatal_prim_flash_alert, recov_prim_flash_alert;
+
+ // An excessive number of recoverable errors may also indicate an attack
+ logic recov_err;
+ assign recov_err = (sw_ctrl_done & |sw_ctrl_err) |
+ flash_phy_rsp.macro_err |
+ update_err;
+
+ logic fatal_err;
+ assign fatal_err = |reg2hw.fault_status;
+
+ logic fatal_std_err;
+ assign fatal_std_err = |reg2hw.std_fault_status;
+
+ lc_ctrl_pkg::lc_tx_t local_esc;
+ assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err);
+
+ assign alert_srcs = {
+ recov_prim_flash_alert,
+ fatal_prim_flash_alert,
+ fatal_err,
+ fatal_std_err,
+ recov_err
+ };
+
+ assign alert_tests = {
+ reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe,
+ reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe,
+ reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe,
+ reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe,
+ reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe
+ };
+
+ localparam logic [NumAlerts-1:0] IsFatal = {1'b0, 1'b1, 1'b1, 1'b1, 1'b0};
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(IsFatal[i])
+ ) u_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_req_i(alert_srcs[i]),
+ .alert_test_i(alert_tests[i]),
+ .alert_ack_o(),
+ .alert_state_o(),
+ .alert_rx_i(alert_rx_i[i]),
+ .alert_tx_o(alert_tx_o[i])
+ );
+ end
+
+ //////////////////////////////////////
+ // Flash Disable and execute enable
+ //////////////////////////////////////
+
+ lc_ctrl_pkg::lc_tx_t lc_escalate_en;
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_escalation_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_escalate_en_i),
+ .lc_en_o({lc_escalate_en})
+ );
+
+ lc_ctrl_pkg::lc_tx_t escalate_en;
+ // SEC_CM: MEM.CTRL.LOCAL_ESC
+ assign escalate_en = lc_ctrl_pkg::lc_tx_or_hi(dis_access, local_esc);
+
+ // flash functional disable
+ lc_ctrl_pkg::lc_tx_t lc_disable;
+ assign lc_disable = lc_ctrl_pkg::lc_tx_or_hi(lc_escalate_en, escalate_en);
+
+ // Normally, faults (those registered in fault_status) should also cause flash access
+ // to disable. However, most errors encountered by hardware during flash access
+ // are registered as faults (since they functionally never happen). Out of an abundance
+ // of caution for the first iteration, we will not kill flash access based on those
+ // faults immediately just in case there are unexpected corner conditions.
+ // In other words...cowardice.
+ // SEC_CM: MEM.CTRL.GLOBAL_ESC
+ // SEC_CM: MEM_DISABLE.CONFIG.MUBI
+ mubi4_t lc_conv_disable;
+ mubi4_t flash_disable_pre_buf;
+ assign lc_conv_disable = lc_ctrl_pkg::lc_to_mubi4(lc_disable);
+ assign flash_disable_pre_buf = prim_mubi_pkg::mubi4_or_hi(
+ lc_conv_disable,
+ mubi4_t'(reg2hw.dis.q));
+
+ prim_mubi4_sync #(
+ .NumCopies(int'(FlashDisableLast)),
+ .AsyncOn(0)
+ ) u_disable_buf (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(flash_disable_pre_buf),
+ .mubi_o(flash_disable)
+ );
+
+ assign flash_phy_req.flash_disable = flash_disable[PhyDisableIdx];
+
+ logic [prim_mubi_pkg::MuBi4Width-1:0] sw_flash_exec_en;
+ mubi4_t flash_exec_en;
+
+ // SEC_CM: EXEC.CONFIG.REDUN
+ prim_sec_anchor_buf #(
+ .Width(prim_mubi_pkg::MuBi4Width)
+ ) u_exec_en_buf (
+ .in_i(prim_mubi_pkg::mubi4_bool_to_mubi(reg2hw.exec.q == unsigned'(ExecEn))),
+ .out_o(sw_flash_exec_en)
+ );
+
+ mubi4_t disable_exec;
+ assign disable_exec = mubi4_t'(~flash_disable[IFetchDisableIdx]);
+ assign flash_exec_en = prim_mubi_pkg::mubi4_and_hi(
+ disable_exec,
+ mubi4_t'(sw_flash_exec_en)
+ );
+
+ //////////////////////////////////////
+ // Errors and Interrupts
+ //////////////////////////////////////
+
+ // all software interface errors are treated as synchronous errors
+ assign hw2reg.err_code.op_err.d = 1'b1;
+ assign hw2reg.err_code.mp_err.d = 1'b1;
+ assign hw2reg.err_code.rd_err.d = 1'b1;
+ assign hw2reg.err_code.prog_err.d = 1'b1;
+ assign hw2reg.err_code.prog_win_err.d = 1'b1;
+ assign hw2reg.err_code.prog_type_err.d = 1'b1;
+ assign hw2reg.err_code.update_err.d = 1'b1;
+ assign hw2reg.err_code.macro_err.d = 1'b1;
+ assign hw2reg.err_code.op_err.de = sw_ctrl_err.invalid_op_err;
+ assign hw2reg.err_code.mp_err.de = sw_ctrl_err.mp_err;
+ assign hw2reg.err_code.rd_err.de = sw_ctrl_err.rd_err;
+ assign hw2reg.err_code.prog_err.de = sw_ctrl_err.prog_err;
+ assign hw2reg.err_code.prog_win_err.de = sw_ctrl_err.prog_win_err;
+ assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err;
+ assign hw2reg.err_code.update_err.de = update_err;
+ assign hw2reg.err_code.macro_err.de = flash_phy_rsp.macro_err;
+ assign hw2reg.err_addr.d = {ctrl_err_addr, {BusByteWidth{1'h0}}};
+ assign hw2reg.err_addr.de = sw_ctrl_err.mp_err |
+ sw_ctrl_err.rd_err |
+ sw_ctrl_err.prog_err;
+
+
+ // all hardware interface errors are considered faults
+ // There are two types of faults
+ // standard faults - things like fsm / counter / tlul integrity
+ // custom faults - things like hardware interface not working correctly
+ assign hw2reg.fault_status.op_err.d = 1'b1;
+ assign hw2reg.fault_status.mp_err.d = 1'b1;
+ assign hw2reg.fault_status.rd_err.d = 1'b1;
+ assign hw2reg.fault_status.prog_err.d = 1'b1;
+ assign hw2reg.fault_status.prog_win_err.d = 1'b1;
+ assign hw2reg.fault_status.prog_type_err.d = 1'b1;
+ assign hw2reg.fault_status.seed_err.d = 1'b1;
+ assign hw2reg.fault_status.phy_relbl_err.d = 1'b1;
+ assign hw2reg.fault_status.phy_storage_err.d = 1'b1;
+ assign hw2reg.fault_status.spurious_ack.d = 1'b1;
+ assign hw2reg.fault_status.arb_err.d = 1'b1;
+ assign hw2reg.fault_status.host_gnt_err.d = 1'b1;
+ assign hw2reg.fault_status.op_err.de = hw_err.invalid_op_err;
+ assign hw2reg.fault_status.mp_err.de = hw_err.mp_err;
+ assign hw2reg.fault_status.rd_err.de = hw_err.rd_err;
+ assign hw2reg.fault_status.prog_err.de = hw_err.prog_err;
+ assign hw2reg.fault_status.prog_win_err.de = hw_err.prog_win_err;
+ assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err;
+ assign hw2reg.fault_status.seed_err.de = seed_err;
+ assign hw2reg.fault_status.phy_relbl_err.de = flash_phy_rsp.storage_relbl_err;
+ assign hw2reg.fault_status.phy_storage_err.de = flash_phy_rsp.storage_intg_err;
+ assign hw2reg.fault_status.spurious_ack.de = flash_phy_rsp.spurious_ack;
+ assign hw2reg.fault_status.arb_err.de = flash_phy_rsp.arb_err;
+ assign hw2reg.fault_status.host_gnt_err.de = flash_phy_rsp.host_gnt_err;
+
+ // standard faults
+ assign hw2reg.std_fault_status.reg_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.prog_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.lcmgr_err.d = 1'b1;
+ assign hw2reg.std_fault_status.lcmgr_intg_err.d = 1'b1;
+ assign hw2reg.std_fault_status.arb_fsm_err.d = 1'b1;
+ assign hw2reg.std_fault_status.storage_err.d = 1'b1;
+ assign hw2reg.std_fault_status.phy_fsm_err.d = 1'b1;
+ assign hw2reg.std_fault_status.ctrl_cnt_err.d = 1'b1;
+ assign hw2reg.std_fault_status.fifo_err.d = 1'b1;
+ assign hw2reg.std_fault_status.reg_intg_err.de = intg_err | eflash_cmd_intg_err |
+ tl_gate_intg_err | tl_prog_gate_intg_err;
+ assign hw2reg.std_fault_status.prog_intg_err.de = flash_phy_rsp.prog_intg_err;
+ assign hw2reg.std_fault_status.lcmgr_err.de = lcmgr_err;
+ assign hw2reg.std_fault_status.lcmgr_intg_err.de = lcmgr_intg_err;
+ assign hw2reg.std_fault_status.arb_fsm_err.de = arb_fsm_err;
+ assign hw2reg.std_fault_status.storage_err.de = storage_err;
+ assign hw2reg.std_fault_status.phy_fsm_err.de = flash_phy_rsp.fsm_err;
+ assign hw2reg.std_fault_status.ctrl_cnt_err.de = rd_cnt_err | prog_cnt_err;
+ assign hw2reg.std_fault_status.fifo_err.de = flash_phy_rsp.fifo_err | adapter_fifo_err;
+
+ // Correctable ECC count / address
+ for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg
+ assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i];
+ assign hw2reg.ecc_single_err_cnt[i].d = ®2hw.ecc_single_err_cnt[i].q ?
+ reg2hw.ecc_single_err_cnt[i].q :
+ reg2hw.ecc_single_err_cnt[i].q + 1'b1;
+
+ assign hw2reg.ecc_single_err_addr[i].de = flash_phy_rsp.ecc_single_err[i];
+ assign hw2reg.ecc_single_err_addr[i].d = {flash_phy_rsp.ecc_addr[i], {BusByteWidth{1'b0}}};
+ end
+
+ logic sw_rd_fifo_wr_q;
+ logic prog_fifo_rd_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ sw_rd_fifo_wr_q <= '0;
+ prog_fifo_rd_q <= '0;
+ end else begin
+ sw_rd_fifo_wr_q <= sw_rfifo_wen & sw_rfifo_wready;
+ prog_fifo_rd_q <= prog_fifo_rvalid & prog_fifo_ren;
+ end
+ end
+
+ // general interrupt events
+ logic [LastIntrIdx-1:0] intr_event;
+
+ prim_edge_detector #(
+ .Width(1),
+ .ResetValue(1),
+ .EnSync(0)
+ ) u_prog_empty_event (
+ .clk_i,
+ .rst_ni,
+ .d_i(~prog_fifo_rvalid),
+ .q_sync_o(),
+ .q_posedge_pulse_o(intr_event[ProgEmpty]),
+ .q_negedge_pulse_o()
+ );
+
+ prim_intr_hw #(.Width(1)) u_intr_prog_empty (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[ProgEmpty]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.prog_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.prog_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.prog_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.prog_empty.d),
+ .intr_o (intr_prog_empty_o)
+ );
+
+ prim_edge_detector #(
+ .Width(1),
+ .ResetValue(0),
+ .EnSync(0)
+ ) u_prog_lvl_event (
+ .clk_i,
+ .rst_ni,
+ .d_i(prog_fifo_rd_q & (reg2hw.fifo_lvl.prog.q == MaxFifoWidth'(prog_fifo_depth))),
+ .q_sync_o(),
+ .q_posedge_pulse_o(intr_event[ProgLvl]),
+ .q_negedge_pulse_o()
+ );
+
+ prim_intr_hw #(.Width(1)) u_intr_prog_lvl (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[ProgLvl]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_lvl.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.prog_lvl.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.prog_lvl.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.prog_lvl.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_lvl.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.prog_lvl.d),
+ .intr_o (intr_prog_lvl_o)
+ );
+
+ prim_edge_detector #(
+ .Width(1),
+ .ResetValue(0),
+ .EnSync(0)
+ ) u_rd_full_event (
+ .clk_i,
+ .rst_ni,
+ .d_i(sw_rfifo_full),
+ .q_sync_o(),
+ .q_posedge_pulse_o(intr_event[RdFull]),
+ .q_negedge_pulse_o()
+ );
+
+ prim_intr_hw #(.Width(1)) u_intr_rd_full (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[RdFull]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_full.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rd_full.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rd_full.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rd_full.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_full.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rd_full.d),
+ .intr_o (intr_rd_full_o)
+ );
+
+ prim_edge_detector #(
+ .Width(1),
+ .ResetValue(0),
+ .EnSync(0)
+ ) u_rd_lvl_event (
+ .clk_i,
+ .rst_ni,
+ .d_i(sw_rd_fifo_wr_q & (reg2hw.fifo_lvl.rd.q == sw_rfifo_depth)),
+ .q_sync_o(),
+ .q_posedge_pulse_o(intr_event[RdLvl]),
+ .q_negedge_pulse_o()
+ );
+
+ prim_intr_hw #(.Width(1)) u_intr_rd_lvl (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[RdLvl]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_lvl.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rd_lvl.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rd_lvl.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rd_lvl.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_lvl.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rd_lvl.d),
+ .intr_o (intr_rd_lvl_o)
+ );
+
+ assign intr_event[OpDone] = sw_ctrl_done;
+ assign intr_event[CorrErr] = |flash_phy_rsp.ecc_single_err;
+
+ prim_intr_hw #(.Width(1)) u_intr_op_done (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[OpDone]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.op_done.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.op_done.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.op_done.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.op_done.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.op_done.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.op_done.d),
+ .intr_o (intr_op_done_o)
+ );
+
+ prim_intr_hw #(.Width(1)) u_intr_corr_err (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (intr_event[CorrErr]),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.corr_err.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.corr_err.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.corr_err.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.corr_err.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.corr_err.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.corr_err.d),
+ .intr_o (intr_corr_err_o)
+ );
+
+ // Unused bits
+ logic [BusByteWidth-1:0] unused_byte_sel;
+ logic [top_pkg::TL_AW-1:0] unused_scratch;
+
+ // Unused signals
+ assign unused_byte_sel = muxed_addr[BusByteWidth-1:0];
+ assign unused_scratch = reg2hw.scratch;
+
+
+ //////////////////////////////////////
+ // flash phy module
+ //////////////////////////////////////
+ logic flash_host_req;
+ logic flash_host_req_rdy;
+ logic flash_host_req_done;
+ logic flash_host_rderr;
+ logic [flash_ctrl_pkg::BusFullWidth-1:0] flash_host_rdata;
+ logic [flash_ctrl_pkg::BusAddrW-1:0] flash_host_addr;
+
+ lc_ctrl_pkg::lc_tx_t host_enable;
+
+ // if flash disable is activated, error back from the adapter interface immediately
+ assign host_enable = lc_ctrl_pkg::mubi4_to_lc_inv(flash_disable[HostDisableIdx]);
+
+ tlul_pkg::tl_h2d_t gate_tl_h2d;
+ tlul_pkg::tl_d2h_t gate_tl_d2h;
+
+ // SEC_CM: MEM_TL_LC_GATE.FSM.SPARSE
+ tlul_lc_gate u_tl_gate (
+ .clk_i,
+ .rst_ni,
+ .tl_h2d_i(mem_tl_i),
+ .tl_d2h_o(mem_tl_o),
+ .tl_h2d_o(gate_tl_h2d),
+ .tl_d2h_i(gate_tl_d2h),
+ .flush_req_i('0),
+ .flush_ack_o(),
+ .resp_pending_o(),
+ .lc_en_i(host_enable),
+ .err_o(tl_gate_intg_err)
+ );
+
+ // SEC_CM: HOST.BUS.INTEGRITY
+ tlul_adapter_sram #(
+ .SramAw(BusAddrW),
+ .SramDw(BusWidth),
+ .Outstanding(2),
+ .ByteAccess(0),
+ .ErrOnWrite(1),
+ .CmdIntgCheck(1),
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(0),
+ .EnableDataIntgPt(1)
+ ) u_tl_adapter_eflash (
+ .clk_i,
+ .rst_ni,
+ .tl_i (gate_tl_h2d),
+ .tl_o (gate_tl_d2h),
+ .en_ifetch_i (flash_exec_en),
+ .req_o (flash_host_req),
+ .req_type_o (),
+ .gnt_i (flash_host_req_rdy),
+ .we_o (),
+ .addr_o (flash_host_addr),
+ .wdata_o (),
+ .wmask_o (),
+ .intg_error_o(eflash_cmd_intg_err),
+ .rdata_i (flash_host_rdata),
+ .rvalid_i (flash_host_req_done),
+ .rerror_i ({flash_host_rderr,1'b0})
+ );
+
+ flash_phy #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_eflash (
+ .clk_i,
+ .rst_ni,
+ .host_req_i (flash_host_req),
+ .host_addr_i (flash_host_addr),
+ .host_req_rdy_o (flash_host_req_rdy),
+ .host_req_done_o (flash_host_req_done),
+ .host_rderr_o (flash_host_rderr),
+ .host_rdata_o (flash_host_rdata),
+ .flash_ctrl_i (flash_phy_req),
+ .flash_ctrl_o (flash_phy_rsp),
+ .tl_i (prim_tl_i),
+ .tl_o (prim_tl_o),
+ .obs_ctrl_i,
+ .fla_obs_o,
+ .lc_nvm_debug_en_i,
+ .flash_bist_enable_i,
+ .flash_power_down_h_i,
+ .flash_power_ready_h_i,
+ .flash_test_mode_a_io,
+ .flash_test_voltage_h_io,
+ .fatal_prim_flash_alert_o(fatal_prim_flash_alert),
+ .recov_prim_flash_alert_o(recov_prim_flash_alert),
+ .scanmode_i,
+ .scan_en_i,
+ .scan_rst_ni
+ );
+
+ /////////////////////////////////
+ // Assertions
+ /////////////////////////////////
+
+ `ASSERT_KNOWN(TlDValidKnownO_A, core_tl_o.d_valid )
+ `ASSERT_KNOWN(TlAReadyKnownO_A, core_tl_o.a_ready )
+ `ASSERT_KNOWN_IF(RspPayLoad_A, core_tl_o, core_tl_o.d_valid)
+ `ASSERT_KNOWN(PrimTlDValidKnownO_A, prim_tl_o.d_valid )
+ `ASSERT_KNOWN(PrimTlAReadyKnownO_A, prim_tl_o.a_ready )
+ `ASSERT_KNOWN_IF(PrimRspPayLoad_A, prim_tl_o, prim_tl_o.d_valid)
+ `ASSERT_KNOWN(MemTlDValidKnownO_A, mem_tl_o.d_valid )
+ `ASSERT_KNOWN(MemTlAReadyKnownO_A, mem_tl_o.a_ready )
+ `ASSERT_KNOWN_IF(MemRspPayLoad_A, mem_tl_o, mem_tl_o.d_valid)
+ `ASSERT_KNOWN(FlashKnownO_A, {flash_phy_req.req, flash_phy_req.rd,
+ flash_phy_req.prog, flash_phy_req.pg_erase,
+ flash_phy_req.bk_erase})
+ `ASSERT_KNOWN_IF(FlashAddrKnown_A, flash_phy_req.addr, flash_phy_req.req)
+ `ASSERT_KNOWN_IF(FlashProgKnown_A, flash_phy_req.prog_data,
+ flash_phy_req.prog & flash_phy_req.req)
+ `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o)
+ `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o )
+ `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o )
+ `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o )
+ `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o )
+ `ASSERT_KNOWN(IntrErrO_A, intr_corr_err_o )
+ `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o )
+ `ASSERT(TdoEnIsOne_A, cio_tdo_en_o === 1'b1)
+
+ // combined indication that an operation has started
+ // This is used only for assertions
+ logic unused_op_valid;
+ assign unused_op_valid = prog_op_valid | rd_op_valid | erase_op_valid;
+
+ // add more assertions
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(SeedCntAlertCheck_A, u_flash_hw_if.u_seed_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(AddrCntAlertCheck_A, u_flash_hw_if.u_addr_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PageCntAlertCheck_A, u_flash_hw_if.u_page_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(WordCntAlertCheck_A, u_flash_hw_if.u_word_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(WipeIdx_A, u_flash_hw_if.u_wipe_idx_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(ProgCnt_A, u_flash_ctrl_prog.u_cnt,
+ alert_tx_o[1])
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RdCnt_A, u_flash_ctrl_rd.u_cnt,
+ alert_tx_o[1])
+
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(LcCtrlFsmCheck_A,
+ u_flash_hw_if.u_state_regs, alert_tx_o[1])
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(LcCtrlRmaFsmCheck_A,
+ u_flash_hw_if.u_rma_state_regs, alert_tx_o[1])
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(ArbFsmCheck_A,
+ u_ctrl_arb.u_state_regs, alert_tx_o[1])
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(TlLcGateFsm_A,
+ u_tl_gate.u_state_regs, alert_tx_o[1])
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(TlProgLcGateFsm_A,
+ u_prog_tl_gate.u_state_regs, alert_tx_o[1])
+
+ for (genvar i=0; i<NumBanks; i++) begin : gen_phy_assertions
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(PhyFsmCheck_A,
+ u_eflash.gen_flash_cores[i].u_core.u_state_regs, alert_tx_o[1])
+
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(PhyProgFsmCheck_A,
+ u_eflash.gen_flash_cores[i].u_core.gen_prog_data.u_prog.u_state_regs, alert_tx_o[1])
+ end
+
+ `ifdef INC_ASSERT
+ `define PHY u_eflash.gen_flash_cores[i]
+ `define PHY_CORE `PHY.u_core
+ for (genvar i=0; i<NumBanks; i++) begin : gen_phy_cnt_errs
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRspFifoWPtr_A,
+ `PHY.u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr, alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRspFifoRPtr_A,
+ `PHY.u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr, alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRdRspFifoWPtr_A,
+ `PHY_CORE.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+ alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRdRspFifoRPtr_A,
+ `PHY_CORE.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+ alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRdDataFifoWPtr_A,
+ `PHY_CORE.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+ alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyRdDataFifoRPtr_A,
+ `PHY_CORE.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+ alert_tx_o[1])
+
+ // Outstanding count error is merged into host_gnt_err instead of being an
+ // individual count error.
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(PhyHostCnt_A,
+ `PHY_CORE.u_host_outstanding_cnt, alert_tx_o[2])
+ end
+ `endif
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RdFifoWptrCheck_A,
+ u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr,
+ alert_tx_o[1])
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RdFifoRptrCheck_A,
+ u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr,
+ alert_tx_o[1])
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[1])
+
+ // Assertions for countermeasures inside prim_flash
+ `ifndef PRIM_DEFAULT_IMPL
+ `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
+ `endif
+ if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A,
+ u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3])
+ end
+
+endmodule
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
new file mode 100644
index 0000000..5fa1d75
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
@@ -0,0 +1,13384 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_core_reg_top (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Output port for window
+ output tlul_pkg::tl_h2d_t tl_win_o [2],
+ input tlul_pkg::tl_d2h_t tl_win_i [2],
+
+ // To HW
+ output flash_ctrl_reg_pkg::flash_ctrl_core_reg2hw_t reg2hw, // Write
+ input flash_ctrl_reg_pkg::flash_ctrl_core_hw2reg_t hw2reg, // Read
+
+ output logic shadowed_storage_err_o,
+ output logic shadowed_update_err_o,
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+ localparam int AW = 9;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [107:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(108)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(0)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ tlul_pkg::tl_h2d_t tl_socket_h2d [3];
+ tlul_pkg::tl_d2h_t tl_socket_d2h [3];
+
+ logic [1:0] reg_steer;
+
+ // socket_1n connection
+ assign tl_reg_h2d = tl_socket_h2d[2];
+ assign tl_socket_d2h[2] = tl_reg_d2h;
+
+ assign tl_win_o[0] = tl_socket_h2d[0];
+ assign tl_socket_d2h[0] = tl_win_i[0];
+ assign tl_win_o[1] = tl_socket_h2d[1];
+ assign tl_socket_d2h[1] = tl_win_i[1];
+
+ // Create Socket_1n
+ tlul_socket_1n #(
+ .N (3),
+ .HReqPass (1'b1),
+ .HRspPass (1'b1),
+ .DReqPass ({3{1'b1}}),
+ .DRspPass ({3{1'b1}}),
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth ({3{4'h0}}),
+ .DRspDepth ({3{4'h0}}),
+ .ExplicitErrs (1'b0)
+ ) u_socket (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .tl_h_i (tl_i),
+ .tl_h_o (tl_o_pre),
+ .tl_d_o (tl_socket_h2d),
+ .tl_d_i (tl_socket_d2h),
+ .dev_select_i (reg_steer)
+ );
+
+ // Create steering logic
+ always_comb begin
+ reg_steer =
+ tl_i.a_address[AW-1:0] inside {[432:435]} ? 2'd0 :
+ tl_i.a_address[AW-1:0] inside {[436:439]} ? 2'd1 :
+ // Default set to register
+ 2'd2;
+
+ // Override this in case of an integrity error
+ if (intg_err) begin
+ reg_steer = 2'd2;
+ end
+ end
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(1)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_prog_empty_qs;
+ logic intr_state_prog_empty_wd;
+ logic intr_state_prog_lvl_qs;
+ logic intr_state_prog_lvl_wd;
+ logic intr_state_rd_full_qs;
+ logic intr_state_rd_full_wd;
+ logic intr_state_rd_lvl_qs;
+ logic intr_state_rd_lvl_wd;
+ logic intr_state_op_done_qs;
+ logic intr_state_op_done_wd;
+ logic intr_state_corr_err_qs;
+ logic intr_state_corr_err_wd;
+ logic intr_enable_we;
+ logic intr_enable_prog_empty_qs;
+ logic intr_enable_prog_empty_wd;
+ logic intr_enable_prog_lvl_qs;
+ logic intr_enable_prog_lvl_wd;
+ logic intr_enable_rd_full_qs;
+ logic intr_enable_rd_full_wd;
+ logic intr_enable_rd_lvl_qs;
+ logic intr_enable_rd_lvl_wd;
+ logic intr_enable_op_done_qs;
+ logic intr_enable_op_done_wd;
+ logic intr_enable_corr_err_qs;
+ logic intr_enable_corr_err_wd;
+ logic intr_test_we;
+ logic intr_test_prog_empty_wd;
+ logic intr_test_prog_lvl_wd;
+ logic intr_test_rd_full_wd;
+ logic intr_test_rd_lvl_wd;
+ logic intr_test_op_done_wd;
+ logic intr_test_corr_err_wd;
+ logic alert_test_we;
+ logic alert_test_recov_err_wd;
+ logic alert_test_fatal_std_err_wd;
+ logic alert_test_fatal_err_wd;
+ logic alert_test_fatal_prim_flash_alert_wd;
+ logic alert_test_recov_prim_flash_alert_wd;
+ logic dis_we;
+ logic [3:0] dis_qs;
+ logic [3:0] dis_wd;
+ logic exec_we;
+ logic [31:0] exec_qs;
+ logic [31:0] exec_wd;
+ logic init_we;
+ logic init_qs;
+ logic init_wd;
+ logic ctrl_regwen_re;
+ logic ctrl_regwen_qs;
+ logic control_we;
+ logic control_start_qs;
+ logic control_start_wd;
+ logic [1:0] control_op_qs;
+ logic [1:0] control_op_wd;
+ logic control_prog_sel_qs;
+ logic control_prog_sel_wd;
+ logic control_erase_sel_qs;
+ logic control_erase_sel_wd;
+ logic control_partition_sel_qs;
+ logic control_partition_sel_wd;
+ logic [1:0] control_info_sel_qs;
+ logic [1:0] control_info_sel_wd;
+ logic [11:0] control_num_qs;
+ logic [11:0] control_num_wd;
+ logic addr_we;
+ logic [19:0] addr_qs;
+ logic [19:0] addr_wd;
+ logic prog_type_en_we;
+ logic prog_type_en_normal_qs;
+ logic prog_type_en_normal_wd;
+ logic prog_type_en_repair_qs;
+ logic prog_type_en_repair_wd;
+ logic erase_suspend_we;
+ logic erase_suspend_qs;
+ logic erase_suspend_wd;
+ logic region_cfg_regwen_0_we;
+ logic region_cfg_regwen_0_qs;
+ logic region_cfg_regwen_0_wd;
+ logic region_cfg_regwen_1_we;
+ logic region_cfg_regwen_1_qs;
+ logic region_cfg_regwen_1_wd;
+ logic region_cfg_regwen_2_we;
+ logic region_cfg_regwen_2_qs;
+ logic region_cfg_regwen_2_wd;
+ logic region_cfg_regwen_3_we;
+ logic region_cfg_regwen_3_qs;
+ logic region_cfg_regwen_3_wd;
+ logic region_cfg_regwen_4_we;
+ logic region_cfg_regwen_4_qs;
+ logic region_cfg_regwen_4_wd;
+ logic region_cfg_regwen_5_we;
+ logic region_cfg_regwen_5_qs;
+ logic region_cfg_regwen_5_wd;
+ logic region_cfg_regwen_6_we;
+ logic region_cfg_regwen_6_qs;
+ logic region_cfg_regwen_6_wd;
+ logic region_cfg_regwen_7_we;
+ logic region_cfg_regwen_7_qs;
+ logic region_cfg_regwen_7_wd;
+ logic mp_region_cfg_0_we;
+ logic [3:0] mp_region_cfg_0_en_0_qs;
+ logic [3:0] mp_region_cfg_0_en_0_wd;
+ logic [3:0] mp_region_cfg_0_rd_en_0_qs;
+ logic [3:0] mp_region_cfg_0_rd_en_0_wd;
+ logic [3:0] mp_region_cfg_0_prog_en_0_qs;
+ logic [3:0] mp_region_cfg_0_prog_en_0_wd;
+ logic [3:0] mp_region_cfg_0_erase_en_0_qs;
+ logic [3:0] mp_region_cfg_0_erase_en_0_wd;
+ logic [3:0] mp_region_cfg_0_scramble_en_0_qs;
+ logic [3:0] mp_region_cfg_0_scramble_en_0_wd;
+ logic [3:0] mp_region_cfg_0_ecc_en_0_qs;
+ logic [3:0] mp_region_cfg_0_ecc_en_0_wd;
+ logic [3:0] mp_region_cfg_0_he_en_0_qs;
+ logic [3:0] mp_region_cfg_0_he_en_0_wd;
+ logic mp_region_cfg_1_we;
+ logic [3:0] mp_region_cfg_1_en_1_qs;
+ logic [3:0] mp_region_cfg_1_en_1_wd;
+ logic [3:0] mp_region_cfg_1_rd_en_1_qs;
+ logic [3:0] mp_region_cfg_1_rd_en_1_wd;
+ logic [3:0] mp_region_cfg_1_prog_en_1_qs;
+ logic [3:0] mp_region_cfg_1_prog_en_1_wd;
+ logic [3:0] mp_region_cfg_1_erase_en_1_qs;
+ logic [3:0] mp_region_cfg_1_erase_en_1_wd;
+ logic [3:0] mp_region_cfg_1_scramble_en_1_qs;
+ logic [3:0] mp_region_cfg_1_scramble_en_1_wd;
+ logic [3:0] mp_region_cfg_1_ecc_en_1_qs;
+ logic [3:0] mp_region_cfg_1_ecc_en_1_wd;
+ logic [3:0] mp_region_cfg_1_he_en_1_qs;
+ logic [3:0] mp_region_cfg_1_he_en_1_wd;
+ logic mp_region_cfg_2_we;
+ logic [3:0] mp_region_cfg_2_en_2_qs;
+ logic [3:0] mp_region_cfg_2_en_2_wd;
+ logic [3:0] mp_region_cfg_2_rd_en_2_qs;
+ logic [3:0] mp_region_cfg_2_rd_en_2_wd;
+ logic [3:0] mp_region_cfg_2_prog_en_2_qs;
+ logic [3:0] mp_region_cfg_2_prog_en_2_wd;
+ logic [3:0] mp_region_cfg_2_erase_en_2_qs;
+ logic [3:0] mp_region_cfg_2_erase_en_2_wd;
+ logic [3:0] mp_region_cfg_2_scramble_en_2_qs;
+ logic [3:0] mp_region_cfg_2_scramble_en_2_wd;
+ logic [3:0] mp_region_cfg_2_ecc_en_2_qs;
+ logic [3:0] mp_region_cfg_2_ecc_en_2_wd;
+ logic [3:0] mp_region_cfg_2_he_en_2_qs;
+ logic [3:0] mp_region_cfg_2_he_en_2_wd;
+ logic mp_region_cfg_3_we;
+ logic [3:0] mp_region_cfg_3_en_3_qs;
+ logic [3:0] mp_region_cfg_3_en_3_wd;
+ logic [3:0] mp_region_cfg_3_rd_en_3_qs;
+ logic [3:0] mp_region_cfg_3_rd_en_3_wd;
+ logic [3:0] mp_region_cfg_3_prog_en_3_qs;
+ logic [3:0] mp_region_cfg_3_prog_en_3_wd;
+ logic [3:0] mp_region_cfg_3_erase_en_3_qs;
+ logic [3:0] mp_region_cfg_3_erase_en_3_wd;
+ logic [3:0] mp_region_cfg_3_scramble_en_3_qs;
+ logic [3:0] mp_region_cfg_3_scramble_en_3_wd;
+ logic [3:0] mp_region_cfg_3_ecc_en_3_qs;
+ logic [3:0] mp_region_cfg_3_ecc_en_3_wd;
+ logic [3:0] mp_region_cfg_3_he_en_3_qs;
+ logic [3:0] mp_region_cfg_3_he_en_3_wd;
+ logic mp_region_cfg_4_we;
+ logic [3:0] mp_region_cfg_4_en_4_qs;
+ logic [3:0] mp_region_cfg_4_en_4_wd;
+ logic [3:0] mp_region_cfg_4_rd_en_4_qs;
+ logic [3:0] mp_region_cfg_4_rd_en_4_wd;
+ logic [3:0] mp_region_cfg_4_prog_en_4_qs;
+ logic [3:0] mp_region_cfg_4_prog_en_4_wd;
+ logic [3:0] mp_region_cfg_4_erase_en_4_qs;
+ logic [3:0] mp_region_cfg_4_erase_en_4_wd;
+ logic [3:0] mp_region_cfg_4_scramble_en_4_qs;
+ logic [3:0] mp_region_cfg_4_scramble_en_4_wd;
+ logic [3:0] mp_region_cfg_4_ecc_en_4_qs;
+ logic [3:0] mp_region_cfg_4_ecc_en_4_wd;
+ logic [3:0] mp_region_cfg_4_he_en_4_qs;
+ logic [3:0] mp_region_cfg_4_he_en_4_wd;
+ logic mp_region_cfg_5_we;
+ logic [3:0] mp_region_cfg_5_en_5_qs;
+ logic [3:0] mp_region_cfg_5_en_5_wd;
+ logic [3:0] mp_region_cfg_5_rd_en_5_qs;
+ logic [3:0] mp_region_cfg_5_rd_en_5_wd;
+ logic [3:0] mp_region_cfg_5_prog_en_5_qs;
+ logic [3:0] mp_region_cfg_5_prog_en_5_wd;
+ logic [3:0] mp_region_cfg_5_erase_en_5_qs;
+ logic [3:0] mp_region_cfg_5_erase_en_5_wd;
+ logic [3:0] mp_region_cfg_5_scramble_en_5_qs;
+ logic [3:0] mp_region_cfg_5_scramble_en_5_wd;
+ logic [3:0] mp_region_cfg_5_ecc_en_5_qs;
+ logic [3:0] mp_region_cfg_5_ecc_en_5_wd;
+ logic [3:0] mp_region_cfg_5_he_en_5_qs;
+ logic [3:0] mp_region_cfg_5_he_en_5_wd;
+ logic mp_region_cfg_6_we;
+ logic [3:0] mp_region_cfg_6_en_6_qs;
+ logic [3:0] mp_region_cfg_6_en_6_wd;
+ logic [3:0] mp_region_cfg_6_rd_en_6_qs;
+ logic [3:0] mp_region_cfg_6_rd_en_6_wd;
+ logic [3:0] mp_region_cfg_6_prog_en_6_qs;
+ logic [3:0] mp_region_cfg_6_prog_en_6_wd;
+ logic [3:0] mp_region_cfg_6_erase_en_6_qs;
+ logic [3:0] mp_region_cfg_6_erase_en_6_wd;
+ logic [3:0] mp_region_cfg_6_scramble_en_6_qs;
+ logic [3:0] mp_region_cfg_6_scramble_en_6_wd;
+ logic [3:0] mp_region_cfg_6_ecc_en_6_qs;
+ logic [3:0] mp_region_cfg_6_ecc_en_6_wd;
+ logic [3:0] mp_region_cfg_6_he_en_6_qs;
+ logic [3:0] mp_region_cfg_6_he_en_6_wd;
+ logic mp_region_cfg_7_we;
+ logic [3:0] mp_region_cfg_7_en_7_qs;
+ logic [3:0] mp_region_cfg_7_en_7_wd;
+ logic [3:0] mp_region_cfg_7_rd_en_7_qs;
+ logic [3:0] mp_region_cfg_7_rd_en_7_wd;
+ logic [3:0] mp_region_cfg_7_prog_en_7_qs;
+ logic [3:0] mp_region_cfg_7_prog_en_7_wd;
+ logic [3:0] mp_region_cfg_7_erase_en_7_qs;
+ logic [3:0] mp_region_cfg_7_erase_en_7_wd;
+ logic [3:0] mp_region_cfg_7_scramble_en_7_qs;
+ logic [3:0] mp_region_cfg_7_scramble_en_7_wd;
+ logic [3:0] mp_region_cfg_7_ecc_en_7_qs;
+ logic [3:0] mp_region_cfg_7_ecc_en_7_wd;
+ logic [3:0] mp_region_cfg_7_he_en_7_qs;
+ logic [3:0] mp_region_cfg_7_he_en_7_wd;
+ logic mp_region_0_we;
+ logic [8:0] mp_region_0_base_0_qs;
+ logic [8:0] mp_region_0_base_0_wd;
+ logic [9:0] mp_region_0_size_0_qs;
+ logic [9:0] mp_region_0_size_0_wd;
+ logic mp_region_1_we;
+ logic [8:0] mp_region_1_base_1_qs;
+ logic [8:0] mp_region_1_base_1_wd;
+ logic [9:0] mp_region_1_size_1_qs;
+ logic [9:0] mp_region_1_size_1_wd;
+ logic mp_region_2_we;
+ logic [8:0] mp_region_2_base_2_qs;
+ logic [8:0] mp_region_2_base_2_wd;
+ logic [9:0] mp_region_2_size_2_qs;
+ logic [9:0] mp_region_2_size_2_wd;
+ logic mp_region_3_we;
+ logic [8:0] mp_region_3_base_3_qs;
+ logic [8:0] mp_region_3_base_3_wd;
+ logic [9:0] mp_region_3_size_3_qs;
+ logic [9:0] mp_region_3_size_3_wd;
+ logic mp_region_4_we;
+ logic [8:0] mp_region_4_base_4_qs;
+ logic [8:0] mp_region_4_base_4_wd;
+ logic [9:0] mp_region_4_size_4_qs;
+ logic [9:0] mp_region_4_size_4_wd;
+ logic mp_region_5_we;
+ logic [8:0] mp_region_5_base_5_qs;
+ logic [8:0] mp_region_5_base_5_wd;
+ logic [9:0] mp_region_5_size_5_qs;
+ logic [9:0] mp_region_5_size_5_wd;
+ logic mp_region_6_we;
+ logic [8:0] mp_region_6_base_6_qs;
+ logic [8:0] mp_region_6_base_6_wd;
+ logic [9:0] mp_region_6_size_6_qs;
+ logic [9:0] mp_region_6_size_6_wd;
+ logic mp_region_7_we;
+ logic [8:0] mp_region_7_base_7_qs;
+ logic [8:0] mp_region_7_base_7_wd;
+ logic [9:0] mp_region_7_size_7_qs;
+ logic [9:0] mp_region_7_size_7_wd;
+ logic default_region_we;
+ logic [3:0] default_region_rd_en_qs;
+ logic [3:0] default_region_rd_en_wd;
+ logic [3:0] default_region_prog_en_qs;
+ logic [3:0] default_region_prog_en_wd;
+ logic [3:0] default_region_erase_en_qs;
+ logic [3:0] default_region_erase_en_wd;
+ logic [3:0] default_region_scramble_en_qs;
+ logic [3:0] default_region_scramble_en_wd;
+ logic [3:0] default_region_ecc_en_qs;
+ logic [3:0] default_region_ecc_en_wd;
+ logic [3:0] default_region_he_en_qs;
+ logic [3:0] default_region_he_en_wd;
+ logic bank0_info0_regwen_0_we;
+ logic bank0_info0_regwen_0_qs;
+ logic bank0_info0_regwen_0_wd;
+ logic bank0_info0_regwen_1_we;
+ logic bank0_info0_regwen_1_qs;
+ logic bank0_info0_regwen_1_wd;
+ logic bank0_info0_regwen_2_we;
+ logic bank0_info0_regwen_2_qs;
+ logic bank0_info0_regwen_2_wd;
+ logic bank0_info0_regwen_3_we;
+ logic bank0_info0_regwen_3_qs;
+ logic bank0_info0_regwen_3_wd;
+ logic bank0_info0_regwen_4_we;
+ logic bank0_info0_regwen_4_qs;
+ logic bank0_info0_regwen_4_wd;
+ logic bank0_info0_regwen_5_we;
+ logic bank0_info0_regwen_5_qs;
+ logic bank0_info0_regwen_5_wd;
+ logic bank0_info0_regwen_6_we;
+ logic bank0_info0_regwen_6_qs;
+ logic bank0_info0_regwen_6_wd;
+ logic bank0_info0_regwen_7_we;
+ logic bank0_info0_regwen_7_qs;
+ logic bank0_info0_regwen_7_wd;
+ logic bank0_info0_regwen_8_we;
+ logic bank0_info0_regwen_8_qs;
+ logic bank0_info0_regwen_8_wd;
+ logic bank0_info0_regwen_9_we;
+ logic bank0_info0_regwen_9_qs;
+ logic bank0_info0_regwen_9_wd;
+ logic bank0_info0_page_cfg_0_we;
+ logic [3:0] bank0_info0_page_cfg_0_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_rd_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_rd_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_prog_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_prog_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_erase_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_erase_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_wd;
+ logic [3:0] bank0_info0_page_cfg_0_he_en_0_qs;
+ logic [3:0] bank0_info0_page_cfg_0_he_en_0_wd;
+ logic bank0_info0_page_cfg_1_we;
+ logic [3:0] bank0_info0_page_cfg_1_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_rd_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_rd_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_prog_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_prog_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_erase_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_erase_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_wd;
+ logic [3:0] bank0_info0_page_cfg_1_he_en_1_qs;
+ logic [3:0] bank0_info0_page_cfg_1_he_en_1_wd;
+ logic bank0_info0_page_cfg_2_we;
+ logic [3:0] bank0_info0_page_cfg_2_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_rd_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_rd_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_prog_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_prog_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_erase_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_erase_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_wd;
+ logic [3:0] bank0_info0_page_cfg_2_he_en_2_qs;
+ logic [3:0] bank0_info0_page_cfg_2_he_en_2_wd;
+ logic bank0_info0_page_cfg_3_we;
+ logic [3:0] bank0_info0_page_cfg_3_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_rd_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_rd_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_prog_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_prog_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_erase_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_erase_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_wd;
+ logic [3:0] bank0_info0_page_cfg_3_he_en_3_qs;
+ logic [3:0] bank0_info0_page_cfg_3_he_en_3_wd;
+ logic bank0_info0_page_cfg_4_we;
+ logic [3:0] bank0_info0_page_cfg_4_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_rd_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_rd_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_prog_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_prog_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_erase_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_erase_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_wd;
+ logic [3:0] bank0_info0_page_cfg_4_he_en_4_qs;
+ logic [3:0] bank0_info0_page_cfg_4_he_en_4_wd;
+ logic bank0_info0_page_cfg_5_we;
+ logic [3:0] bank0_info0_page_cfg_5_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_rd_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_rd_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_prog_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_prog_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_erase_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_erase_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_wd;
+ logic [3:0] bank0_info0_page_cfg_5_he_en_5_qs;
+ logic [3:0] bank0_info0_page_cfg_5_he_en_5_wd;
+ logic bank0_info0_page_cfg_6_we;
+ logic [3:0] bank0_info0_page_cfg_6_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_rd_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_rd_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_prog_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_prog_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_erase_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_erase_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_wd;
+ logic [3:0] bank0_info0_page_cfg_6_he_en_6_qs;
+ logic [3:0] bank0_info0_page_cfg_6_he_en_6_wd;
+ logic bank0_info0_page_cfg_7_we;
+ logic [3:0] bank0_info0_page_cfg_7_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_rd_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_rd_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_prog_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_prog_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_erase_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_erase_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_wd;
+ logic [3:0] bank0_info0_page_cfg_7_he_en_7_qs;
+ logic [3:0] bank0_info0_page_cfg_7_he_en_7_wd;
+ logic bank0_info0_page_cfg_8_we;
+ logic [3:0] bank0_info0_page_cfg_8_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_rd_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_rd_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_prog_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_prog_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_erase_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_erase_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_wd;
+ logic [3:0] bank0_info0_page_cfg_8_he_en_8_qs;
+ logic [3:0] bank0_info0_page_cfg_8_he_en_8_wd;
+ logic bank0_info0_page_cfg_9_we;
+ logic [3:0] bank0_info0_page_cfg_9_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_rd_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_rd_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_prog_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_prog_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_erase_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_erase_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_wd;
+ logic [3:0] bank0_info0_page_cfg_9_he_en_9_qs;
+ logic [3:0] bank0_info0_page_cfg_9_he_en_9_wd;
+ logic bank0_info1_regwen_we;
+ logic bank0_info1_regwen_qs;
+ logic bank0_info1_regwen_wd;
+ logic bank0_info1_page_cfg_we;
+ logic [3:0] bank0_info1_page_cfg_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_rd_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_rd_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_prog_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_prog_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_erase_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_erase_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_scramble_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_scramble_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_ecc_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_ecc_en_0_wd;
+ logic [3:0] bank0_info1_page_cfg_he_en_0_qs;
+ logic [3:0] bank0_info1_page_cfg_he_en_0_wd;
+ logic bank0_info2_regwen_0_we;
+ logic bank0_info2_regwen_0_qs;
+ logic bank0_info2_regwen_0_wd;
+ logic bank0_info2_regwen_1_we;
+ logic bank0_info2_regwen_1_qs;
+ logic bank0_info2_regwen_1_wd;
+ logic bank0_info2_page_cfg_0_we;
+ logic [3:0] bank0_info2_page_cfg_0_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_rd_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_rd_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_prog_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_prog_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_erase_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_erase_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_wd;
+ logic [3:0] bank0_info2_page_cfg_0_he_en_0_qs;
+ logic [3:0] bank0_info2_page_cfg_0_he_en_0_wd;
+ logic bank0_info2_page_cfg_1_we;
+ logic [3:0] bank0_info2_page_cfg_1_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_rd_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_rd_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_prog_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_prog_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_erase_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_erase_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_wd;
+ logic [3:0] bank0_info2_page_cfg_1_he_en_1_qs;
+ logic [3:0] bank0_info2_page_cfg_1_he_en_1_wd;
+ logic bank1_info0_regwen_0_we;
+ logic bank1_info0_regwen_0_qs;
+ logic bank1_info0_regwen_0_wd;
+ logic bank1_info0_regwen_1_we;
+ logic bank1_info0_regwen_1_qs;
+ logic bank1_info0_regwen_1_wd;
+ logic bank1_info0_regwen_2_we;
+ logic bank1_info0_regwen_2_qs;
+ logic bank1_info0_regwen_2_wd;
+ logic bank1_info0_regwen_3_we;
+ logic bank1_info0_regwen_3_qs;
+ logic bank1_info0_regwen_3_wd;
+ logic bank1_info0_regwen_4_we;
+ logic bank1_info0_regwen_4_qs;
+ logic bank1_info0_regwen_4_wd;
+ logic bank1_info0_regwen_5_we;
+ logic bank1_info0_regwen_5_qs;
+ logic bank1_info0_regwen_5_wd;
+ logic bank1_info0_regwen_6_we;
+ logic bank1_info0_regwen_6_qs;
+ logic bank1_info0_regwen_6_wd;
+ logic bank1_info0_regwen_7_we;
+ logic bank1_info0_regwen_7_qs;
+ logic bank1_info0_regwen_7_wd;
+ logic bank1_info0_regwen_8_we;
+ logic bank1_info0_regwen_8_qs;
+ logic bank1_info0_regwen_8_wd;
+ logic bank1_info0_regwen_9_we;
+ logic bank1_info0_regwen_9_qs;
+ logic bank1_info0_regwen_9_wd;
+ logic bank1_info0_page_cfg_0_we;
+ logic [3:0] bank1_info0_page_cfg_0_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_rd_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_rd_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_prog_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_prog_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_erase_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_erase_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_wd;
+ logic [3:0] bank1_info0_page_cfg_0_he_en_0_qs;
+ logic [3:0] bank1_info0_page_cfg_0_he_en_0_wd;
+ logic bank1_info0_page_cfg_1_we;
+ logic [3:0] bank1_info0_page_cfg_1_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_rd_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_rd_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_prog_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_prog_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_erase_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_erase_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_wd;
+ logic [3:0] bank1_info0_page_cfg_1_he_en_1_qs;
+ logic [3:0] bank1_info0_page_cfg_1_he_en_1_wd;
+ logic bank1_info0_page_cfg_2_we;
+ logic [3:0] bank1_info0_page_cfg_2_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_rd_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_rd_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_prog_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_prog_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_erase_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_erase_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_wd;
+ logic [3:0] bank1_info0_page_cfg_2_he_en_2_qs;
+ logic [3:0] bank1_info0_page_cfg_2_he_en_2_wd;
+ logic bank1_info0_page_cfg_3_we;
+ logic [3:0] bank1_info0_page_cfg_3_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_rd_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_rd_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_prog_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_prog_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_erase_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_erase_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_wd;
+ logic [3:0] bank1_info0_page_cfg_3_he_en_3_qs;
+ logic [3:0] bank1_info0_page_cfg_3_he_en_3_wd;
+ logic bank1_info0_page_cfg_4_we;
+ logic [3:0] bank1_info0_page_cfg_4_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_rd_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_rd_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_prog_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_prog_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_erase_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_erase_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_wd;
+ logic [3:0] bank1_info0_page_cfg_4_he_en_4_qs;
+ logic [3:0] bank1_info0_page_cfg_4_he_en_4_wd;
+ logic bank1_info0_page_cfg_5_we;
+ logic [3:0] bank1_info0_page_cfg_5_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_rd_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_rd_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_prog_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_prog_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_erase_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_erase_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_wd;
+ logic [3:0] bank1_info0_page_cfg_5_he_en_5_qs;
+ logic [3:0] bank1_info0_page_cfg_5_he_en_5_wd;
+ logic bank1_info0_page_cfg_6_we;
+ logic [3:0] bank1_info0_page_cfg_6_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_rd_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_rd_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_prog_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_prog_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_erase_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_erase_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_wd;
+ logic [3:0] bank1_info0_page_cfg_6_he_en_6_qs;
+ logic [3:0] bank1_info0_page_cfg_6_he_en_6_wd;
+ logic bank1_info0_page_cfg_7_we;
+ logic [3:0] bank1_info0_page_cfg_7_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_rd_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_rd_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_prog_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_prog_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_erase_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_erase_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_wd;
+ logic [3:0] bank1_info0_page_cfg_7_he_en_7_qs;
+ logic [3:0] bank1_info0_page_cfg_7_he_en_7_wd;
+ logic bank1_info0_page_cfg_8_we;
+ logic [3:0] bank1_info0_page_cfg_8_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_rd_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_rd_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_prog_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_prog_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_erase_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_erase_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_wd;
+ logic [3:0] bank1_info0_page_cfg_8_he_en_8_qs;
+ logic [3:0] bank1_info0_page_cfg_8_he_en_8_wd;
+ logic bank1_info0_page_cfg_9_we;
+ logic [3:0] bank1_info0_page_cfg_9_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_rd_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_rd_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_prog_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_prog_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_erase_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_erase_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_wd;
+ logic [3:0] bank1_info0_page_cfg_9_he_en_9_qs;
+ logic [3:0] bank1_info0_page_cfg_9_he_en_9_wd;
+ logic bank1_info1_regwen_we;
+ logic bank1_info1_regwen_qs;
+ logic bank1_info1_regwen_wd;
+ logic bank1_info1_page_cfg_we;
+ logic [3:0] bank1_info1_page_cfg_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_rd_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_rd_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_prog_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_prog_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_erase_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_erase_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_scramble_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_scramble_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_ecc_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_ecc_en_0_wd;
+ logic [3:0] bank1_info1_page_cfg_he_en_0_qs;
+ logic [3:0] bank1_info1_page_cfg_he_en_0_wd;
+ logic bank1_info2_regwen_0_we;
+ logic bank1_info2_regwen_0_qs;
+ logic bank1_info2_regwen_0_wd;
+ logic bank1_info2_regwen_1_we;
+ logic bank1_info2_regwen_1_qs;
+ logic bank1_info2_regwen_1_wd;
+ logic bank1_info2_page_cfg_0_we;
+ logic [3:0] bank1_info2_page_cfg_0_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_rd_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_rd_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_prog_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_prog_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_erase_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_erase_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_wd;
+ logic [3:0] bank1_info2_page_cfg_0_he_en_0_qs;
+ logic [3:0] bank1_info2_page_cfg_0_he_en_0_wd;
+ logic bank1_info2_page_cfg_1_we;
+ logic [3:0] bank1_info2_page_cfg_1_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_rd_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_rd_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_prog_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_prog_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_erase_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_erase_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_wd;
+ logic [3:0] bank1_info2_page_cfg_1_he_en_1_qs;
+ logic [3:0] bank1_info2_page_cfg_1_he_en_1_wd;
+ logic hw_info_cfg_override_we;
+ logic [3:0] hw_info_cfg_override_scramble_dis_qs;
+ logic [3:0] hw_info_cfg_override_scramble_dis_wd;
+ logic [3:0] hw_info_cfg_override_ecc_dis_qs;
+ logic [3:0] hw_info_cfg_override_ecc_dis_wd;
+ logic bank_cfg_regwen_we;
+ logic bank_cfg_regwen_qs;
+ logic bank_cfg_regwen_wd;
+ logic mp_bank_cfg_shadowed_re;
+ logic mp_bank_cfg_shadowed_we;
+ logic mp_bank_cfg_shadowed_erase_en_0_qs;
+ logic mp_bank_cfg_shadowed_erase_en_0_wd;
+ logic mp_bank_cfg_shadowed_erase_en_0_storage_err;
+ logic mp_bank_cfg_shadowed_erase_en_0_update_err;
+ logic mp_bank_cfg_shadowed_erase_en_1_qs;
+ logic mp_bank_cfg_shadowed_erase_en_1_wd;
+ logic mp_bank_cfg_shadowed_erase_en_1_storage_err;
+ logic mp_bank_cfg_shadowed_erase_en_1_update_err;
+ logic op_status_we;
+ logic op_status_done_qs;
+ logic op_status_done_wd;
+ logic op_status_err_qs;
+ logic op_status_err_wd;
+ logic status_rd_full_qs;
+ logic status_rd_empty_qs;
+ logic status_prog_full_qs;
+ logic status_prog_empty_qs;
+ logic status_init_wip_qs;
+ logic status_initialized_qs;
+ logic debug_state_re;
+ logic [10:0] debug_state_qs;
+ logic err_code_we;
+ logic err_code_op_err_qs;
+ logic err_code_op_err_wd;
+ logic err_code_mp_err_qs;
+ logic err_code_mp_err_wd;
+ logic err_code_rd_err_qs;
+ logic err_code_rd_err_wd;
+ logic err_code_prog_err_qs;
+ logic err_code_prog_err_wd;
+ logic err_code_prog_win_err_qs;
+ logic err_code_prog_win_err_wd;
+ logic err_code_prog_type_err_qs;
+ logic err_code_prog_type_err_wd;
+ logic err_code_update_err_qs;
+ logic err_code_update_err_wd;
+ logic err_code_macro_err_qs;
+ logic err_code_macro_err_wd;
+ logic std_fault_status_reg_intg_err_qs;
+ logic std_fault_status_prog_intg_err_qs;
+ logic std_fault_status_lcmgr_err_qs;
+ logic std_fault_status_lcmgr_intg_err_qs;
+ logic std_fault_status_arb_fsm_err_qs;
+ logic std_fault_status_storage_err_qs;
+ logic std_fault_status_phy_fsm_err_qs;
+ logic std_fault_status_ctrl_cnt_err_qs;
+ logic std_fault_status_fifo_err_qs;
+ logic fault_status_op_err_qs;
+ logic fault_status_mp_err_qs;
+ logic fault_status_rd_err_qs;
+ logic fault_status_prog_err_qs;
+ logic fault_status_prog_win_err_qs;
+ logic fault_status_prog_type_err_qs;
+ logic fault_status_seed_err_qs;
+ logic fault_status_phy_relbl_err_qs;
+ logic fault_status_phy_storage_err_qs;
+ logic fault_status_spurious_ack_qs;
+ logic fault_status_arb_err_qs;
+ logic fault_status_host_gnt_err_qs;
+ logic [19:0] err_addr_qs;
+ logic ecc_single_err_cnt_we;
+ logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
+ logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_wd;
+ logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
+ logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_wd;
+ logic [19:0] ecc_single_err_addr_0_qs;
+ logic [19:0] ecc_single_err_addr_1_qs;
+ logic phy_alert_cfg_we;
+ logic phy_alert_cfg_alert_ack_qs;
+ logic phy_alert_cfg_alert_ack_wd;
+ logic phy_alert_cfg_alert_trig_qs;
+ logic phy_alert_cfg_alert_trig_wd;
+ logic phy_status_init_wip_qs;
+ logic phy_status_prog_normal_avail_qs;
+ logic phy_status_prog_repair_avail_qs;
+ logic scratch_we;
+ logic [31:0] scratch_qs;
+ logic [31:0] scratch_wd;
+ logic fifo_lvl_we;
+ logic [4:0] fifo_lvl_prog_qs;
+ logic [4:0] fifo_lvl_prog_wd;
+ logic [4:0] fifo_lvl_rd_qs;
+ logic [4:0] fifo_lvl_rd_wd;
+ logic fifo_rst_we;
+ logic fifo_rst_qs;
+ logic fifo_rst_wd;
+ logic curr_fifo_lvl_re;
+ logic [4:0] curr_fifo_lvl_prog_qs;
+ logic [4:0] curr_fifo_lvl_rd_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[prog_empty]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_prog_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_prog_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.prog_empty.de),
+ .d (hw2reg.intr_state.prog_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.prog_empty.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_prog_empty_qs)
+ );
+
+ // F[prog_lvl]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_prog_lvl (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_prog_lvl_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.prog_lvl.de),
+ .d (hw2reg.intr_state.prog_lvl.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.prog_lvl.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_prog_lvl_qs)
+ );
+
+ // F[rd_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_rd_full (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_rd_full_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rd_full.de),
+ .d (hw2reg.intr_state.rd_full.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rd_full.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_rd_full_qs)
+ );
+
+ // F[rd_lvl]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_rd_lvl (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_rd_lvl_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.rd_lvl.de),
+ .d (hw2reg.intr_state.rd_lvl.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.rd_lvl.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_rd_lvl_qs)
+ );
+
+ // F[op_done]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_op_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_op_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.op_done.de),
+ .d (hw2reg.intr_state.op_done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.op_done.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_op_done_qs)
+ );
+
+ // F[corr_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_corr_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_corr_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.corr_err.de),
+ .d (hw2reg.intr_state.corr_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.corr_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_corr_err_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[prog_empty]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_prog_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_prog_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.prog_empty.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_prog_empty_qs)
+ );
+
+ // F[prog_lvl]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_prog_lvl (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_prog_lvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.prog_lvl.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_prog_lvl_qs)
+ );
+
+ // F[rd_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rd_full (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_rd_full_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rd_full.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_rd_full_qs)
+ );
+
+ // F[rd_lvl]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_rd_lvl (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_rd_lvl_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.rd_lvl.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_rd_lvl_qs)
+ );
+
+ // F[op_done]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_op_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_op_done_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.op_done.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_op_done_qs)
+ );
+
+ // F[corr_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_corr_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_corr_err_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.corr_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_corr_err_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ logic intr_test_qe;
+ logic [5:0] intr_test_flds_we;
+ assign intr_test_qe = &intr_test_flds_we;
+ // F[prog_empty]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_prog_empty (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_prog_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[0]),
+ .q (reg2hw.intr_test.prog_empty.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.prog_empty.qe = intr_test_qe;
+
+ // F[prog_lvl]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_prog_lvl (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_prog_lvl_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[1]),
+ .q (reg2hw.intr_test.prog_lvl.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.prog_lvl.qe = intr_test_qe;
+
+ // F[rd_full]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rd_full (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_rd_full_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[2]),
+ .q (reg2hw.intr_test.rd_full.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.rd_full.qe = intr_test_qe;
+
+ // F[rd_lvl]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_rd_lvl (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_rd_lvl_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[3]),
+ .q (reg2hw.intr_test.rd_lvl.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.rd_lvl.qe = intr_test_qe;
+
+ // F[op_done]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_op_done (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_op_done_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[4]),
+ .q (reg2hw.intr_test.op_done.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.op_done.qe = intr_test_qe;
+
+ // F[corr_err]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_corr_err (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_corr_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[5]),
+ .q (reg2hw.intr_test.corr_err.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.corr_err.qe = intr_test_qe;
+
+
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [4:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ // F[recov_err]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_recov_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.recov_err.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.recov_err.qe = alert_test_qe;
+
+ // F[fatal_std_err]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_std_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_std_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_std_err.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_std_err.qe = alert_test_qe;
+
+ // F[fatal_err]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[2]),
+ .q (reg2hw.alert_test.fatal_err.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_err.qe = alert_test_qe;
+
+ // F[fatal_prim_flash_alert]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_prim_flash_alert (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_prim_flash_alert_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[3]),
+ .q (reg2hw.alert_test.fatal_prim_flash_alert.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_prim_flash_alert.qe = alert_test_qe;
+
+ // F[recov_prim_flash_alert]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_prim_flash_alert (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_recov_prim_flash_alert_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[4]),
+ .q (reg2hw.alert_test.recov_prim_flash_alert.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.recov_prim_flash_alert.qe = alert_test_qe;
+
+
+ // R[dis]: V(False)
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (4'h9)
+ ) u_dis (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dis_we),
+ .wd (dis_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dis.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dis_qs)
+ );
+
+
+ // R[exec]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_exec (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (exec_we),
+ .wd (exec_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.exec.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (exec_qs)
+ );
+
+
+ // R[init]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1S),
+ .RESVAL (1'h0)
+ ) u_init (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (init_we),
+ .wd (init_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.init.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (init_qs)
+ );
+
+
+ // R[ctrl_regwen]: V(True)
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_ctrl_regwen (
+ .re (ctrl_regwen_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.ctrl_regwen.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (ctrl_regwen_qs)
+ );
+
+
+ // R[control]: V(False)
+ // Create REGWEN-gated WE signal
+ logic control_gated_we;
+ assign control_gated_we = control_we & ctrl_regwen_qs;
+ // F[start]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_start (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_start_wd),
+
+ // from internal hardware
+ .de (hw2reg.control.start.de),
+ .d (hw2reg.control.start.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.start.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_start_qs)
+ );
+
+ // F[op]: 5:4
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_control_op (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_op_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.op.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_op_qs)
+ );
+
+ // F[prog_sel]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_prog_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_prog_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.prog_sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_prog_sel_qs)
+ );
+
+ // F[erase_sel]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_erase_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_erase_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.erase_sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_erase_sel_qs)
+ );
+
+ // F[partition_sel]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_partition_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_partition_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.partition_sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_partition_sel_qs)
+ );
+
+ // F[info_sel]: 10:9
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_control_info_sel (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_info_sel_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.info_sel.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_info_sel_qs)
+ );
+
+ // F[num]: 27:16
+ prim_subreg #(
+ .DW (12),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (12'h0)
+ ) u_control_num (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_num_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.num.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_num_qs)
+ );
+
+
+ // R[addr]: V(False)
+ // Create REGWEN-gated WE signal
+ logic addr_gated_we;
+ assign addr_gated_we = addr_we & ctrl_regwen_qs;
+ prim_subreg #(
+ .DW (20),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (20'h0)
+ ) u_addr (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (addr_gated_we),
+ .wd (addr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.addr.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (addr_qs)
+ );
+
+
+ // R[prog_type_en]: V(False)
+ // Create REGWEN-gated WE signal
+ logic prog_type_en_gated_we;
+ assign prog_type_en_gated_we = prog_type_en_we & ctrl_regwen_qs;
+ // F[normal]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_prog_type_en_normal (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prog_type_en_gated_we),
+ .wd (prog_type_en_normal_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prog_type_en.normal.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prog_type_en_normal_qs)
+ );
+
+ // F[repair]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_prog_type_en_repair (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prog_type_en_gated_we),
+ .wd (prog_type_en_repair_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prog_type_en.repair.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prog_type_en_repair_qs)
+ );
+
+
+ // R[erase_suspend]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_erase_suspend (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (erase_suspend_we),
+ .wd (erase_suspend_wd),
+
+ // from internal hardware
+ .de (hw2reg.erase_suspend.de),
+ .d (hw2reg.erase_suspend.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.erase_suspend.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (erase_suspend_qs)
+ );
+
+
+ // Subregister 0 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_0_we),
+ .wd (region_cfg_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_1_we),
+ .wd (region_cfg_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_2_we),
+ .wd (region_cfg_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_3_we),
+ .wd (region_cfg_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_4_we),
+ .wd (region_cfg_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_5_we),
+ .wd (region_cfg_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_6_we),
+ .wd (region_cfg_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg region_cfg_regwen
+ // R[region_cfg_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (region_cfg_regwen_7_we),
+ .wd (region_cfg_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_7_qs)
+ );
+
+
+ // Subregister 0 of Multireg mp_region_cfg
+ // R[mp_region_cfg_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_0_gated_we;
+ assign mp_region_cfg_0_gated_we = mp_region_cfg_0_we & region_cfg_regwen_0_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_0_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_0_gated_we),
+ .wd (mp_region_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_he_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mp_region_cfg
+ // R[mp_region_cfg_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_1_gated_we;
+ assign mp_region_cfg_1_gated_we = mp_region_cfg_1_we & region_cfg_regwen_1_qs;
+ // F[en_1]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_en_1_qs)
+ );
+
+ // F[rd_en_1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_rd_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_rd_en_1_qs)
+ );
+
+ // F[prog_en_1]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_prog_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_prog_en_1_qs)
+ );
+
+ // F[erase_en_1]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_erase_en_1_qs)
+ );
+
+ // F[scramble_en_1]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_scramble_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_scramble_en_1_qs)
+ );
+
+ // F[ecc_en_1]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_ecc_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_ecc_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_ecc_en_1_qs)
+ );
+
+ // F[he_en_1]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_1_he_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_1_gated_we),
+ .wd (mp_region_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_he_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mp_region_cfg
+ // R[mp_region_cfg_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_2_gated_we;
+ assign mp_region_cfg_2_gated_we = mp_region_cfg_2_we & region_cfg_regwen_2_qs;
+ // F[en_2]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_en_2_qs)
+ );
+
+ // F[rd_en_2]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_rd_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_rd_en_2_qs)
+ );
+
+ // F[prog_en_2]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_prog_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_prog_en_2_qs)
+ );
+
+ // F[erase_en_2]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_erase_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_erase_en_2_qs)
+ );
+
+ // F[scramble_en_2]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_scramble_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_scramble_en_2_qs)
+ );
+
+ // F[ecc_en_2]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_ecc_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_ecc_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_ecc_en_2_qs)
+ );
+
+ // F[he_en_2]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_2_he_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_2_gated_we),
+ .wd (mp_region_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_he_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mp_region_cfg
+ // R[mp_region_cfg_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_3_gated_we;
+ assign mp_region_cfg_3_gated_we = mp_region_cfg_3_we & region_cfg_regwen_3_qs;
+ // F[en_3]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_en_3_qs)
+ );
+
+ // F[rd_en_3]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_rd_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_rd_en_3_qs)
+ );
+
+ // F[prog_en_3]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_prog_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_prog_en_3_qs)
+ );
+
+ // F[erase_en_3]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_erase_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_erase_en_3_qs)
+ );
+
+ // F[scramble_en_3]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_scramble_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_scramble_en_3_qs)
+ );
+
+ // F[ecc_en_3]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_ecc_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_ecc_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_ecc_en_3_qs)
+ );
+
+ // F[he_en_3]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_3_he_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_3_gated_we),
+ .wd (mp_region_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_he_en_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mp_region_cfg
+ // R[mp_region_cfg_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_4_gated_we;
+ assign mp_region_cfg_4_gated_we = mp_region_cfg_4_we & region_cfg_regwen_4_qs;
+ // F[en_4]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_en_4_qs)
+ );
+
+ // F[rd_en_4]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_rd_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_rd_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_rd_en_4_qs)
+ );
+
+ // F[prog_en_4]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_prog_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_prog_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_prog_en_4_qs)
+ );
+
+ // F[erase_en_4]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_erase_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_erase_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_erase_en_4_qs)
+ );
+
+ // F[scramble_en_4]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_scramble_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_scramble_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_scramble_en_4_qs)
+ );
+
+ // F[ecc_en_4]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_ecc_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_ecc_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_ecc_en_4_qs)
+ );
+
+ // F[he_en_4]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_4_he_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_4_gated_we),
+ .wd (mp_region_cfg_4_he_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_he_en_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mp_region_cfg
+ // R[mp_region_cfg_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_5_gated_we;
+ assign mp_region_cfg_5_gated_we = mp_region_cfg_5_we & region_cfg_regwen_5_qs;
+ // F[en_5]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_en_5_qs)
+ );
+
+ // F[rd_en_5]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_rd_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_rd_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_rd_en_5_qs)
+ );
+
+ // F[prog_en_5]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_prog_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_prog_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_prog_en_5_qs)
+ );
+
+ // F[erase_en_5]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_erase_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_erase_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_erase_en_5_qs)
+ );
+
+ // F[scramble_en_5]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_scramble_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_scramble_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_scramble_en_5_qs)
+ );
+
+ // F[ecc_en_5]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_ecc_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_ecc_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_ecc_en_5_qs)
+ );
+
+ // F[he_en_5]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_5_he_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_5_gated_we),
+ .wd (mp_region_cfg_5_he_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_he_en_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mp_region_cfg
+ // R[mp_region_cfg_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_6_gated_we;
+ assign mp_region_cfg_6_gated_we = mp_region_cfg_6_we & region_cfg_regwen_6_qs;
+ // F[en_6]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_en_6_qs)
+ );
+
+ // F[rd_en_6]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_rd_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_rd_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_rd_en_6_qs)
+ );
+
+ // F[prog_en_6]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_prog_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_prog_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_prog_en_6_qs)
+ );
+
+ // F[erase_en_6]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_erase_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_erase_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_erase_en_6_qs)
+ );
+
+ // F[scramble_en_6]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_scramble_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_scramble_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_scramble_en_6_qs)
+ );
+
+ // F[ecc_en_6]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_ecc_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_ecc_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_ecc_en_6_qs)
+ );
+
+ // F[he_en_6]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_6_he_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_6_gated_we),
+ .wd (mp_region_cfg_6_he_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_he_en_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mp_region_cfg
+ // R[mp_region_cfg_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_cfg_7_gated_we;
+ assign mp_region_cfg_7_gated_we = mp_region_cfg_7_we & region_cfg_regwen_7_qs;
+ // F[en_7]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_en_7_qs)
+ );
+
+ // F[rd_en_7]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_rd_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_rd_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_rd_en_7_qs)
+ );
+
+ // F[prog_en_7]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_prog_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_prog_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_prog_en_7_qs)
+ );
+
+ // F[erase_en_7]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_erase_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_erase_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_erase_en_7_qs)
+ );
+
+ // F[scramble_en_7]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_scramble_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_scramble_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_scramble_en_7_qs)
+ );
+
+ // F[ecc_en_7]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_ecc_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_ecc_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_ecc_en_7_qs)
+ );
+
+ // F[he_en_7]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_mp_region_cfg_7_he_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_cfg_7_gated_we),
+ .wd (mp_region_cfg_7_he_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_he_en_7_qs)
+ );
+
+
+ // Subregister 0 of Multireg mp_region
+ // R[mp_region_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_0_gated_we;
+ assign mp_region_0_gated_we = mp_region_0_we & region_cfg_regwen_0_qs;
+ // F[base_0]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_0_base_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_0_gated_we),
+ .wd (mp_region_0_base_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[0].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_0_base_0_qs)
+ );
+
+ // F[size_0]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_0_size_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_0_gated_we),
+ .wd (mp_region_0_size_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[0].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_0_size_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mp_region
+ // R[mp_region_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_1_gated_we;
+ assign mp_region_1_gated_we = mp_region_1_we & region_cfg_regwen_1_qs;
+ // F[base_1]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_1_base_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_1_gated_we),
+ .wd (mp_region_1_base_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[1].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_1_base_1_qs)
+ );
+
+ // F[size_1]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_1_size_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_1_gated_we),
+ .wd (mp_region_1_size_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[1].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_1_size_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mp_region
+ // R[mp_region_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_2_gated_we;
+ assign mp_region_2_gated_we = mp_region_2_we & region_cfg_regwen_2_qs;
+ // F[base_2]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_2_base_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_2_gated_we),
+ .wd (mp_region_2_base_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[2].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_2_base_2_qs)
+ );
+
+ // F[size_2]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_2_size_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_2_gated_we),
+ .wd (mp_region_2_size_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[2].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_2_size_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mp_region
+ // R[mp_region_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_3_gated_we;
+ assign mp_region_3_gated_we = mp_region_3_we & region_cfg_regwen_3_qs;
+ // F[base_3]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_3_base_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_3_gated_we),
+ .wd (mp_region_3_base_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[3].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_3_base_3_qs)
+ );
+
+ // F[size_3]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_3_size_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_3_gated_we),
+ .wd (mp_region_3_size_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[3].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_3_size_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mp_region
+ // R[mp_region_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_4_gated_we;
+ assign mp_region_4_gated_we = mp_region_4_we & region_cfg_regwen_4_qs;
+ // F[base_4]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_4_base_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_4_gated_we),
+ .wd (mp_region_4_base_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[4].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_4_base_4_qs)
+ );
+
+ // F[size_4]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_4_size_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_4_gated_we),
+ .wd (mp_region_4_size_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[4].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_4_size_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mp_region
+ // R[mp_region_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_5_gated_we;
+ assign mp_region_5_gated_we = mp_region_5_we & region_cfg_regwen_5_qs;
+ // F[base_5]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_5_base_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_5_gated_we),
+ .wd (mp_region_5_base_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[5].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_5_base_5_qs)
+ );
+
+ // F[size_5]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_5_size_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_5_gated_we),
+ .wd (mp_region_5_size_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[5].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_5_size_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mp_region
+ // R[mp_region_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_6_gated_we;
+ assign mp_region_6_gated_we = mp_region_6_we & region_cfg_regwen_6_qs;
+ // F[base_6]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_6_base_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_6_gated_we),
+ .wd (mp_region_6_base_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[6].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_6_base_6_qs)
+ );
+
+ // F[size_6]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_6_size_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_6_gated_we),
+ .wd (mp_region_6_size_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[6].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_6_size_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mp_region
+ // R[mp_region_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_region_7_gated_we;
+ assign mp_region_7_gated_we = mp_region_7_we & region_cfg_regwen_7_qs;
+ // F[base_7]: 8:0
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_mp_region_7_base_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_7_gated_we),
+ .wd (mp_region_7_base_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[7].base.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_7_base_7_qs)
+ );
+
+ // F[size_7]: 18:9
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_mp_region_7_size_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mp_region_7_gated_we),
+ .wd (mp_region_7_size_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region[7].size.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_region_7_size_7_qs)
+ );
+
+
+ // R[default_region]: V(False)
+ // F[rd_en]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_rd_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_rd_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_rd_en_qs)
+ );
+
+ // F[prog_en]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_prog_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_prog_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_prog_en_qs)
+ );
+
+ // F[erase_en]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_erase_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_erase_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_erase_en_qs)
+ );
+
+ // F[scramble_en]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_scramble_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_scramble_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_scramble_en_qs)
+ );
+
+ // F[ecc_en]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_ecc_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_ecc_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_ecc_en_qs)
+ );
+
+ // F[he_en]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_default_region_he_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (default_region_we),
+ .wd (default_region_he_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (default_region_he_en_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_0_we),
+ .wd (bank0_info0_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_1_we),
+ .wd (bank0_info0_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_2_we),
+ .wd (bank0_info0_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_3_we),
+ .wd (bank0_info0_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_4_we),
+ .wd (bank0_info0_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_5_we),
+ .wd (bank0_info0_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_6_we),
+ .wd (bank0_info0_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_7_we),
+ .wd (bank0_info0_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_8_we),
+ .wd (bank0_info0_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg bank0_info0_regwen
+ // R[bank0_info0_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info0_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_regwen_9_we),
+ .wd (bank0_info0_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_regwen_9_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_0_gated_we;
+ assign bank0_info0_page_cfg_0_gated_we = bank0_info0_page_cfg_0_we & bank0_info0_regwen_0_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_0_gated_we),
+ .wd (bank0_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_1_gated_we;
+ assign bank0_info0_page_cfg_1_gated_we = bank0_info0_page_cfg_1_we & bank0_info0_regwen_1_qs;
+ // F[en_1]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_en_1_qs)
+ );
+
+ // F[rd_en_1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_rd_en_1_qs)
+ );
+
+ // F[prog_en_1]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_prog_en_1_qs)
+ );
+
+ // F[erase_en_1]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_erase_en_1_qs)
+ );
+
+ // F[scramble_en_1]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_scramble_en_1_qs)
+ );
+
+ // F[ecc_en_1]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_ecc_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_ecc_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_ecc_en_1_qs)
+ );
+
+ // F[he_en_1]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_1_gated_we),
+ .wd (bank0_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_2_gated_we;
+ assign bank0_info0_page_cfg_2_gated_we = bank0_info0_page_cfg_2_we & bank0_info0_regwen_2_qs;
+ // F[en_2]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_en_2_qs)
+ );
+
+ // F[rd_en_2]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_rd_en_2_qs)
+ );
+
+ // F[prog_en_2]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_prog_en_2_qs)
+ );
+
+ // F[erase_en_2]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_erase_en_2_qs)
+ );
+
+ // F[scramble_en_2]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_scramble_en_2_qs)
+ );
+
+ // F[ecc_en_2]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_ecc_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_ecc_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_ecc_en_2_qs)
+ );
+
+ // F[he_en_2]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_2_gated_we),
+ .wd (bank0_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_3_gated_we;
+ assign bank0_info0_page_cfg_3_gated_we = bank0_info0_page_cfg_3_we & bank0_info0_regwen_3_qs;
+ // F[en_3]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_en_3_qs)
+ );
+
+ // F[rd_en_3]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_rd_en_3_qs)
+ );
+
+ // F[prog_en_3]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_prog_en_3_qs)
+ );
+
+ // F[erase_en_3]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_erase_en_3_qs)
+ );
+
+ // F[scramble_en_3]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_scramble_en_3_qs)
+ );
+
+ // F[ecc_en_3]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_ecc_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_ecc_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_ecc_en_3_qs)
+ );
+
+ // F[he_en_3]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_3_gated_we),
+ .wd (bank0_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_4_gated_we;
+ assign bank0_info0_page_cfg_4_gated_we = bank0_info0_page_cfg_4_we & bank0_info0_regwen_4_qs;
+ // F[en_4]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_en_4_qs)
+ );
+
+ // F[rd_en_4]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_rd_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_rd_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_rd_en_4_qs)
+ );
+
+ // F[prog_en_4]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_prog_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_prog_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_prog_en_4_qs)
+ );
+
+ // F[erase_en_4]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_erase_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_erase_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_erase_en_4_qs)
+ );
+
+ // F[scramble_en_4]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_scramble_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_scramble_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_scramble_en_4_qs)
+ );
+
+ // F[ecc_en_4]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_ecc_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_ecc_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_ecc_en_4_qs)
+ );
+
+ // F[he_en_4]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_4_he_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_4_gated_we),
+ .wd (bank0_info0_page_cfg_4_he_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[4].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_4_he_en_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_5_gated_we;
+ assign bank0_info0_page_cfg_5_gated_we = bank0_info0_page_cfg_5_we & bank0_info0_regwen_5_qs;
+ // F[en_5]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_en_5_qs)
+ );
+
+ // F[rd_en_5]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_rd_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_rd_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_rd_en_5_qs)
+ );
+
+ // F[prog_en_5]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_prog_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_prog_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_prog_en_5_qs)
+ );
+
+ // F[erase_en_5]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_erase_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_erase_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_erase_en_5_qs)
+ );
+
+ // F[scramble_en_5]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_scramble_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_scramble_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_scramble_en_5_qs)
+ );
+
+ // F[ecc_en_5]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_ecc_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_ecc_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_ecc_en_5_qs)
+ );
+
+ // F[he_en_5]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_5_he_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_5_gated_we),
+ .wd (bank0_info0_page_cfg_5_he_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[5].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_5_he_en_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_6_gated_we;
+ assign bank0_info0_page_cfg_6_gated_we = bank0_info0_page_cfg_6_we & bank0_info0_regwen_6_qs;
+ // F[en_6]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_en_6_qs)
+ );
+
+ // F[rd_en_6]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_rd_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_rd_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_rd_en_6_qs)
+ );
+
+ // F[prog_en_6]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_prog_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_prog_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_prog_en_6_qs)
+ );
+
+ // F[erase_en_6]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_erase_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_erase_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_erase_en_6_qs)
+ );
+
+ // F[scramble_en_6]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_scramble_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_scramble_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_scramble_en_6_qs)
+ );
+
+ // F[ecc_en_6]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_ecc_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_ecc_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_ecc_en_6_qs)
+ );
+
+ // F[he_en_6]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_6_he_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_6_gated_we),
+ .wd (bank0_info0_page_cfg_6_he_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[6].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_6_he_en_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_7_gated_we;
+ assign bank0_info0_page_cfg_7_gated_we = bank0_info0_page_cfg_7_we & bank0_info0_regwen_7_qs;
+ // F[en_7]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_en_7_qs)
+ );
+
+ // F[rd_en_7]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_rd_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_rd_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_rd_en_7_qs)
+ );
+
+ // F[prog_en_7]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_prog_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_prog_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_prog_en_7_qs)
+ );
+
+ // F[erase_en_7]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_erase_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_erase_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_erase_en_7_qs)
+ );
+
+ // F[scramble_en_7]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_scramble_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_scramble_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_scramble_en_7_qs)
+ );
+
+ // F[ecc_en_7]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_ecc_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_ecc_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_ecc_en_7_qs)
+ );
+
+ // F[he_en_7]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_7_he_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_7_gated_we),
+ .wd (bank0_info0_page_cfg_7_he_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[7].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_7_he_en_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_8_gated_we;
+ assign bank0_info0_page_cfg_8_gated_we = bank0_info0_page_cfg_8_we & bank0_info0_regwen_8_qs;
+ // F[en_8]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_en_8_qs)
+ );
+
+ // F[rd_en_8]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_rd_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_rd_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_rd_en_8_qs)
+ );
+
+ // F[prog_en_8]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_prog_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_prog_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_prog_en_8_qs)
+ );
+
+ // F[erase_en_8]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_erase_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_erase_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_erase_en_8_qs)
+ );
+
+ // F[scramble_en_8]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_scramble_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_scramble_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_scramble_en_8_qs)
+ );
+
+ // F[ecc_en_8]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_ecc_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_ecc_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_ecc_en_8_qs)
+ );
+
+ // F[he_en_8]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_8_he_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_8_gated_we),
+ .wd (bank0_info0_page_cfg_8_he_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[8].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_8_he_en_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg bank0_info0_page_cfg
+ // R[bank0_info0_page_cfg_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info0_page_cfg_9_gated_we;
+ assign bank0_info0_page_cfg_9_gated_we = bank0_info0_page_cfg_9_we & bank0_info0_regwen_9_qs;
+ // F[en_9]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_en_9_qs)
+ );
+
+ // F[rd_en_9]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_rd_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_rd_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_rd_en_9_qs)
+ );
+
+ // F[prog_en_9]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_prog_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_prog_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_prog_en_9_qs)
+ );
+
+ // F[erase_en_9]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_erase_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_erase_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_erase_en_9_qs)
+ );
+
+ // F[scramble_en_9]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_scramble_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_scramble_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_scramble_en_9_qs)
+ );
+
+ // F[ecc_en_9]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_ecc_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_ecc_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_ecc_en_9_qs)
+ );
+
+ // F[he_en_9]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info0_page_cfg_9_he_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info0_page_cfg_9_gated_we),
+ .wd (bank0_info0_page_cfg_9_he_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[9].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_9_he_en_9_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info1_regwen
+ // R[bank0_info1_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info1_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_regwen_we),
+ .wd (bank0_info1_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info1_page_cfg
+ // R[bank0_info1_page_cfg]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info1_page_cfg_gated_we;
+ assign bank0_info1_page_cfg_gated_we = bank0_info1_page_cfg_we & bank0_info1_regwen_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info1_page_cfg_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info1_page_cfg_gated_we),
+ .wd (bank0_info1_page_cfg_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_he_en_0_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info2_regwen
+ // R[bank0_info2_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info2_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_regwen_0_we),
+ .wd (bank0_info2_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info2_regwen
+ // R[bank0_info2_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank0_info2_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_regwen_1_we),
+ .wd (bank0_info2_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_regwen_1_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank0_info2_page_cfg
+ // R[bank0_info2_page_cfg_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info2_page_cfg_0_gated_we;
+ assign bank0_info2_page_cfg_0_gated_we = bank0_info2_page_cfg_0_we & bank0_info2_regwen_0_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_0_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_0_gated_we),
+ .wd (bank0_info2_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_0_he_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank0_info2_page_cfg
+ // R[bank0_info2_page_cfg_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank0_info2_page_cfg_1_gated_we;
+ assign bank0_info2_page_cfg_1_gated_we = bank0_info2_page_cfg_1_we & bank0_info2_regwen_1_qs;
+ // F[en_1]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_en_1_qs)
+ );
+
+ // F[rd_en_1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_rd_en_1_qs)
+ );
+
+ // F[prog_en_1]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_prog_en_1_qs)
+ );
+
+ // F[erase_en_1]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_erase_en_1_qs)
+ );
+
+ // F[scramble_en_1]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_scramble_en_1_qs)
+ );
+
+ // F[ecc_en_1]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_ecc_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_ecc_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_ecc_en_1_qs)
+ );
+
+ // F[he_en_1]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank0_info2_page_cfg_1_he_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank0_info2_page_cfg_1_gated_we),
+ .wd (bank0_info2_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info2_page_cfg[1].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank0_info2_page_cfg_1_he_en_1_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_0_we),
+ .wd (bank1_info0_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_1_we),
+ .wd (bank1_info0_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_2_we),
+ .wd (bank1_info0_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_3_we),
+ .wd (bank1_info0_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_4_we),
+ .wd (bank1_info0_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_5_we),
+ .wd (bank1_info0_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_6_we),
+ .wd (bank1_info0_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_7_we),
+ .wd (bank1_info0_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_8_we),
+ .wd (bank1_info0_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg bank1_info0_regwen
+ // R[bank1_info0_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info0_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_regwen_9_we),
+ .wd (bank1_info0_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_regwen_9_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_0_gated_we;
+ assign bank1_info0_page_cfg_0_gated_we = bank1_info0_page_cfg_0_we & bank1_info0_regwen_0_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_0_gated_we),
+ .wd (bank1_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_1_gated_we;
+ assign bank1_info0_page_cfg_1_gated_we = bank1_info0_page_cfg_1_we & bank1_info0_regwen_1_qs;
+ // F[en_1]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_en_1_qs)
+ );
+
+ // F[rd_en_1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_rd_en_1_qs)
+ );
+
+ // F[prog_en_1]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_prog_en_1_qs)
+ );
+
+ // F[erase_en_1]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_erase_en_1_qs)
+ );
+
+ // F[scramble_en_1]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_scramble_en_1_qs)
+ );
+
+ // F[ecc_en_1]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_ecc_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_ecc_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_ecc_en_1_qs)
+ );
+
+ // F[he_en_1]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_1_gated_we),
+ .wd (bank1_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_2_gated_we;
+ assign bank1_info0_page_cfg_2_gated_we = bank1_info0_page_cfg_2_we & bank1_info0_regwen_2_qs;
+ // F[en_2]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_en_2_qs)
+ );
+
+ // F[rd_en_2]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_rd_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_rd_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_rd_en_2_qs)
+ );
+
+ // F[prog_en_2]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_prog_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_prog_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_prog_en_2_qs)
+ );
+
+ // F[erase_en_2]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_erase_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_erase_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_erase_en_2_qs)
+ );
+
+ // F[scramble_en_2]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_scramble_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_scramble_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_scramble_en_2_qs)
+ );
+
+ // F[ecc_en_2]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_ecc_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_ecc_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_ecc_en_2_qs)
+ );
+
+ // F[he_en_2]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_2_gated_we),
+ .wd (bank1_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_3_gated_we;
+ assign bank1_info0_page_cfg_3_gated_we = bank1_info0_page_cfg_3_we & bank1_info0_regwen_3_qs;
+ // F[en_3]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_en_3_qs)
+ );
+
+ // F[rd_en_3]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_rd_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_rd_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_rd_en_3_qs)
+ );
+
+ // F[prog_en_3]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_prog_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_prog_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_prog_en_3_qs)
+ );
+
+ // F[erase_en_3]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_erase_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_erase_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_erase_en_3_qs)
+ );
+
+ // F[scramble_en_3]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_scramble_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_scramble_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_scramble_en_3_qs)
+ );
+
+ // F[ecc_en_3]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_ecc_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_ecc_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_ecc_en_3_qs)
+ );
+
+ // F[he_en_3]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_3_gated_we),
+ .wd (bank1_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_4_gated_we;
+ assign bank1_info0_page_cfg_4_gated_we = bank1_info0_page_cfg_4_we & bank1_info0_regwen_4_qs;
+ // F[en_4]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_en_4_qs)
+ );
+
+ // F[rd_en_4]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_rd_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_rd_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_rd_en_4_qs)
+ );
+
+ // F[prog_en_4]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_prog_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_prog_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_prog_en_4_qs)
+ );
+
+ // F[erase_en_4]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_erase_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_erase_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_erase_en_4_qs)
+ );
+
+ // F[scramble_en_4]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_scramble_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_scramble_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_scramble_en_4_qs)
+ );
+
+ // F[ecc_en_4]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_ecc_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_ecc_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_ecc_en_4_qs)
+ );
+
+ // F[he_en_4]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_4_he_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_4_gated_we),
+ .wd (bank1_info0_page_cfg_4_he_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[4].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_4_he_en_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_5_gated_we;
+ assign bank1_info0_page_cfg_5_gated_we = bank1_info0_page_cfg_5_we & bank1_info0_regwen_5_qs;
+ // F[en_5]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_en_5_qs)
+ );
+
+ // F[rd_en_5]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_rd_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_rd_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_rd_en_5_qs)
+ );
+
+ // F[prog_en_5]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_prog_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_prog_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_prog_en_5_qs)
+ );
+
+ // F[erase_en_5]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_erase_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_erase_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_erase_en_5_qs)
+ );
+
+ // F[scramble_en_5]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_scramble_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_scramble_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_scramble_en_5_qs)
+ );
+
+ // F[ecc_en_5]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_ecc_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_ecc_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_ecc_en_5_qs)
+ );
+
+ // F[he_en_5]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_5_he_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_5_gated_we),
+ .wd (bank1_info0_page_cfg_5_he_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[5].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_5_he_en_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_6_gated_we;
+ assign bank1_info0_page_cfg_6_gated_we = bank1_info0_page_cfg_6_we & bank1_info0_regwen_6_qs;
+ // F[en_6]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_en_6_qs)
+ );
+
+ // F[rd_en_6]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_rd_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_rd_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_rd_en_6_qs)
+ );
+
+ // F[prog_en_6]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_prog_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_prog_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_prog_en_6_qs)
+ );
+
+ // F[erase_en_6]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_erase_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_erase_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_erase_en_6_qs)
+ );
+
+ // F[scramble_en_6]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_scramble_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_scramble_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_scramble_en_6_qs)
+ );
+
+ // F[ecc_en_6]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_ecc_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_ecc_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_ecc_en_6_qs)
+ );
+
+ // F[he_en_6]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_6_he_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_6_gated_we),
+ .wd (bank1_info0_page_cfg_6_he_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[6].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_6_he_en_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_7_gated_we;
+ assign bank1_info0_page_cfg_7_gated_we = bank1_info0_page_cfg_7_we & bank1_info0_regwen_7_qs;
+ // F[en_7]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_en_7_qs)
+ );
+
+ // F[rd_en_7]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_rd_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_rd_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_rd_en_7_qs)
+ );
+
+ // F[prog_en_7]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_prog_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_prog_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_prog_en_7_qs)
+ );
+
+ // F[erase_en_7]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_erase_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_erase_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_erase_en_7_qs)
+ );
+
+ // F[scramble_en_7]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_scramble_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_scramble_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_scramble_en_7_qs)
+ );
+
+ // F[ecc_en_7]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_ecc_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_ecc_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_ecc_en_7_qs)
+ );
+
+ // F[he_en_7]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_7_he_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_7_gated_we),
+ .wd (bank1_info0_page_cfg_7_he_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[7].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_7_he_en_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_8_gated_we;
+ assign bank1_info0_page_cfg_8_gated_we = bank1_info0_page_cfg_8_we & bank1_info0_regwen_8_qs;
+ // F[en_8]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_en_8_qs)
+ );
+
+ // F[rd_en_8]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_rd_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_rd_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_rd_en_8_qs)
+ );
+
+ // F[prog_en_8]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_prog_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_prog_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_prog_en_8_qs)
+ );
+
+ // F[erase_en_8]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_erase_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_erase_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_erase_en_8_qs)
+ );
+
+ // F[scramble_en_8]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_scramble_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_scramble_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_scramble_en_8_qs)
+ );
+
+ // F[ecc_en_8]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_ecc_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_ecc_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_ecc_en_8_qs)
+ );
+
+ // F[he_en_8]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_8_he_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_8_gated_we),
+ .wd (bank1_info0_page_cfg_8_he_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[8].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_8_he_en_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg bank1_info0_page_cfg
+ // R[bank1_info0_page_cfg_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info0_page_cfg_9_gated_we;
+ assign bank1_info0_page_cfg_9_gated_we = bank1_info0_page_cfg_9_we & bank1_info0_regwen_9_qs;
+ // F[en_9]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_en_9_qs)
+ );
+
+ // F[rd_en_9]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_rd_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_rd_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_rd_en_9_qs)
+ );
+
+ // F[prog_en_9]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_prog_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_prog_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_prog_en_9_qs)
+ );
+
+ // F[erase_en_9]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_erase_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_erase_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_erase_en_9_qs)
+ );
+
+ // F[scramble_en_9]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_scramble_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_scramble_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_scramble_en_9_qs)
+ );
+
+ // F[ecc_en_9]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_ecc_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_ecc_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_ecc_en_9_qs)
+ );
+
+ // F[he_en_9]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info0_page_cfg_9_he_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info0_page_cfg_9_gated_we),
+ .wd (bank1_info0_page_cfg_9_he_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[9].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_9_he_en_9_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info1_regwen
+ // R[bank1_info1_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info1_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_regwen_we),
+ .wd (bank1_info1_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info1_page_cfg
+ // R[bank1_info1_page_cfg]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info1_page_cfg_gated_we;
+ assign bank1_info1_page_cfg_gated_we = bank1_info1_page_cfg_we & bank1_info1_regwen_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info1_page_cfg_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info1_page_cfg_gated_we),
+ .wd (bank1_info1_page_cfg_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_he_en_0_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info2_regwen
+ // R[bank1_info2_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info2_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_regwen_0_we),
+ .wd (bank1_info2_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info2_regwen
+ // R[bank1_info2_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank1_info2_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_regwen_1_we),
+ .wd (bank1_info2_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_regwen_1_qs)
+ );
+
+
+ // Subregister 0 of Multireg bank1_info2_page_cfg
+ // R[bank1_info2_page_cfg_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info2_page_cfg_0_gated_we;
+ assign bank1_info2_page_cfg_0_gated_we = bank1_info2_page_cfg_0_we & bank1_info2_regwen_0_qs;
+ // F[en_0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_en_0_qs)
+ );
+
+ // F[rd_en_0]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_rd_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_rd_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_rd_en_0_qs)
+ );
+
+ // F[prog_en_0]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_prog_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_prog_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_prog_en_0_qs)
+ );
+
+ // F[erase_en_0]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_erase_en_0_qs)
+ );
+
+ // F[scramble_en_0]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_scramble_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_scramble_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_scramble_en_0_qs)
+ );
+
+ // F[ecc_en_0]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_ecc_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_ecc_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_ecc_en_0_qs)
+ );
+
+ // F[he_en_0]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_0_he_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_0_gated_we),
+ .wd (bank1_info2_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[0].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_0_he_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg bank1_info2_page_cfg
+ // R[bank1_info2_page_cfg_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic bank1_info2_page_cfg_1_gated_we;
+ assign bank1_info2_page_cfg_1_gated_we = bank1_info2_page_cfg_1_we & bank1_info2_regwen_1_qs;
+ // F[en_1]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_en_1_qs)
+ );
+
+ // F[rd_en_1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_rd_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_rd_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_rd_en_1_qs)
+ );
+
+ // F[prog_en_1]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_prog_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_prog_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_prog_en_1_qs)
+ );
+
+ // F[erase_en_1]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_erase_en_1_qs)
+ );
+
+ // F[scramble_en_1]: 19:16
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_scramble_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_scramble_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_scramble_en_1_qs)
+ );
+
+ // F[ecc_en_1]: 23:20
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_ecc_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_ecc_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_ecc_en_1_qs)
+ );
+
+ // F[he_en_1]: 27:24
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_bank1_info2_page_cfg_1_he_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank1_info2_page_cfg_1_gated_we),
+ .wd (bank1_info2_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info2_page_cfg[1].he_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank1_info2_page_cfg_1_he_en_1_qs)
+ );
+
+
+ // R[hw_info_cfg_override]: V(False)
+ // F[scramble_dis]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_hw_info_cfg_override_scramble_dis (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (hw_info_cfg_override_we),
+ .wd (hw_info_cfg_override_scramble_dis_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.hw_info_cfg_override.scramble_dis.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (hw_info_cfg_override_scramble_dis_qs)
+ );
+
+ // F[ecc_dis]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_hw_info_cfg_override_ecc_dis (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (hw_info_cfg_override_we),
+ .wd (hw_info_cfg_override_ecc_dis_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.hw_info_cfg_override.ecc_dis.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (hw_info_cfg_override_ecc_dis_qs)
+ );
+
+
+ // R[bank_cfg_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_bank_cfg_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (bank_cfg_regwen_we),
+ .wd (bank_cfg_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (bank_cfg_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg mp_bank_cfg_shadowed
+ // R[mp_bank_cfg_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mp_bank_cfg_shadowed_gated_we;
+ assign mp_bank_cfg_shadowed_gated_we = mp_bank_cfg_shadowed_we & bank_cfg_regwen_qs;
+ // F[erase_en_0]: 0:0
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mp_bank_cfg_shadowed_erase_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (mp_bank_cfg_shadowed_re),
+ .we (mp_bank_cfg_shadowed_gated_we),
+ .wd (mp_bank_cfg_shadowed_erase_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_bank_cfg_shadowed[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_bank_cfg_shadowed_erase_en_0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (mp_bank_cfg_shadowed_erase_en_0_update_err),
+ .err_storage (mp_bank_cfg_shadowed_erase_en_0_storage_err)
+ );
+
+ // F[erase_en_1]: 1:1
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mp_bank_cfg_shadowed_erase_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (mp_bank_cfg_shadowed_re),
+ .we (mp_bank_cfg_shadowed_gated_we),
+ .wd (mp_bank_cfg_shadowed_erase_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_bank_cfg_shadowed[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mp_bank_cfg_shadowed_erase_en_1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (mp_bank_cfg_shadowed_erase_en_1_update_err),
+ .err_storage (mp_bank_cfg_shadowed_erase_en_1_storage_err)
+ );
+
+
+ // R[op_status]: V(False)
+ // F[done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_op_status_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (op_status_we),
+ .wd (op_status_done_wd),
+
+ // from internal hardware
+ .de (hw2reg.op_status.done.de),
+ .d (hw2reg.op_status.done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (op_status_done_qs)
+ );
+
+ // F[err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_op_status_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (op_status_we),
+ .wd (op_status_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.op_status.err.de),
+ .d (hw2reg.op_status.err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (op_status_err_qs)
+ );
+
+
+ // R[status]: V(False)
+ // F[rd_full]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_status_rd_full (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.rd_full.de),
+ .d (hw2reg.status.rd_full.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_rd_full_qs)
+ );
+
+ // F[rd_empty]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_status_rd_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.rd_empty.de),
+ .d (hw2reg.status.rd_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_rd_empty_qs)
+ );
+
+ // F[prog_full]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_status_prog_full (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.prog_full.de),
+ .d (hw2reg.status.prog_full.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_prog_full_qs)
+ );
+
+ // F[prog_empty]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_status_prog_empty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.prog_empty.de),
+ .d (hw2reg.status.prog_empty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_prog_empty_qs)
+ );
+
+ // F[init_wip]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_status_init_wip (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.init_wip.de),
+ .d (hw2reg.status.init_wip.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_init_wip_qs)
+ );
+
+ // F[initialized]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_status_initialized (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.initialized.de),
+ .d (hw2reg.status.initialized.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_initialized_qs)
+ );
+
+
+ // R[debug_state]: V(True)
+ prim_subreg_ext #(
+ .DW (11)
+ ) u_debug_state (
+ .re (debug_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.debug_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (debug_state_qs)
+ );
+
+
+ // R[err_code]: V(False)
+ // F[op_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_op_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_op_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.op_err.de),
+ .d (hw2reg.err_code.op_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_op_err_qs)
+ );
+
+ // F[mp_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_mp_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_mp_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.mp_err.de),
+ .d (hw2reg.err_code.mp_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_mp_err_qs)
+ );
+
+ // F[rd_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_rd_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_rd_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.rd_err.de),
+ .d (hw2reg.err_code.rd_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_rd_err_qs)
+ );
+
+ // F[prog_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_prog_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_prog_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.prog_err.de),
+ .d (hw2reg.err_code.prog_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_prog_err_qs)
+ );
+
+ // F[prog_win_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_prog_win_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_prog_win_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.prog_win_err.de),
+ .d (hw2reg.err_code.prog_win_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_prog_win_err_qs)
+ );
+
+ // F[prog_type_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_prog_type_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_prog_type_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.prog_type_err.de),
+ .d (hw2reg.err_code.prog_type_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_prog_type_err_qs)
+ );
+
+ // F[update_err]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_update_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_update_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.update_err.de),
+ .d (hw2reg.err_code.update_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_update_err_qs)
+ );
+
+ // F[macro_err]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_err_code_macro_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (err_code_we),
+ .wd (err_code_macro_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.macro_err.de),
+ .d (hw2reg.err_code.macro_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_macro_err_qs)
+ );
+
+
+ // R[std_fault_status]: V(False)
+ // F[reg_intg_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_reg_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.reg_intg_err.de),
+ .d (hw2reg.std_fault_status.reg_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.reg_intg_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_reg_intg_err_qs)
+ );
+
+ // F[prog_intg_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_prog_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.prog_intg_err.de),
+ .d (hw2reg.std_fault_status.prog_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.prog_intg_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_prog_intg_err_qs)
+ );
+
+ // F[lcmgr_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_lcmgr_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.lcmgr_err.de),
+ .d (hw2reg.std_fault_status.lcmgr_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.lcmgr_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_lcmgr_err_qs)
+ );
+
+ // F[lcmgr_intg_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_lcmgr_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.lcmgr_intg_err.de),
+ .d (hw2reg.std_fault_status.lcmgr_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.lcmgr_intg_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_lcmgr_intg_err_qs)
+ );
+
+ // F[arb_fsm_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_arb_fsm_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.arb_fsm_err.de),
+ .d (hw2reg.std_fault_status.arb_fsm_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.arb_fsm_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_arb_fsm_err_qs)
+ );
+
+ // F[storage_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_storage_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.storage_err.de),
+ .d (hw2reg.std_fault_status.storage_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.storage_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_storage_err_qs)
+ );
+
+ // F[phy_fsm_err]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_phy_fsm_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.phy_fsm_err.de),
+ .d (hw2reg.std_fault_status.phy_fsm_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.phy_fsm_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_phy_fsm_err_qs)
+ );
+
+ // F[ctrl_cnt_err]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_ctrl_cnt_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.ctrl_cnt_err.de),
+ .d (hw2reg.std_fault_status.ctrl_cnt_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.ctrl_cnt_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_ctrl_cnt_err_qs)
+ );
+
+ // F[fifo_err]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_std_fault_status_fifo_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.std_fault_status.fifo_err.de),
+ .d (hw2reg.std_fault_status.fifo_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.std_fault_status.fifo_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (std_fault_status_fifo_err_qs)
+ );
+
+
+ // R[fault_status]: V(False)
+ // F[op_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_op_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.op_err.de),
+ .d (hw2reg.fault_status.op_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.op_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_op_err_qs)
+ );
+
+ // F[mp_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_mp_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.mp_err.de),
+ .d (hw2reg.fault_status.mp_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.mp_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_mp_err_qs)
+ );
+
+ // F[rd_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_rd_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.rd_err.de),
+ .d (hw2reg.fault_status.rd_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.rd_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_rd_err_qs)
+ );
+
+ // F[prog_err]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_prog_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.prog_err.de),
+ .d (hw2reg.fault_status.prog_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.prog_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_prog_err_qs)
+ );
+
+ // F[prog_win_err]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_prog_win_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.prog_win_err.de),
+ .d (hw2reg.fault_status.prog_win_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.prog_win_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_prog_win_err_qs)
+ );
+
+ // F[prog_type_err]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_prog_type_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.prog_type_err.de),
+ .d (hw2reg.fault_status.prog_type_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.prog_type_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_prog_type_err_qs)
+ );
+
+ // F[seed_err]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_seed_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.seed_err.de),
+ .d (hw2reg.fault_status.seed_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.seed_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_seed_err_qs)
+ );
+
+ // F[phy_relbl_err]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_phy_relbl_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.phy_relbl_err.de),
+ .d (hw2reg.fault_status.phy_relbl_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.phy_relbl_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_phy_relbl_err_qs)
+ );
+
+ // F[phy_storage_err]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_phy_storage_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.phy_storage_err.de),
+ .d (hw2reg.fault_status.phy_storage_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.phy_storage_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_phy_storage_err_qs)
+ );
+
+ // F[spurious_ack]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_spurious_ack (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.spurious_ack.de),
+ .d (hw2reg.fault_status.spurious_ack.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.spurious_ack.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_spurious_ack_qs)
+ );
+
+ // F[arb_err]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_arb_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.arb_err.de),
+ .d (hw2reg.fault_status.arb_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.arb_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_arb_err_qs)
+ );
+
+ // F[host_gnt_err]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_host_gnt_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.host_gnt_err.de),
+ .d (hw2reg.fault_status.host_gnt_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.host_gnt_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_host_gnt_err_qs)
+ );
+
+
+ // R[err_addr]: V(False)
+ prim_subreg #(
+ .DW (20),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (20'h0)
+ ) u_err_addr (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_addr.de),
+ .d (hw2reg.err_addr.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_addr_qs)
+ );
+
+
+ // Subregister 0 of Multireg ecc_single_err_cnt
+ // R[ecc_single_err_cnt]: V(False)
+ // F[ecc_single_err_cnt_0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_ecc_single_err_cnt_ecc_single_err_cnt_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ecc_single_err_cnt_we),
+ .wd (ecc_single_err_cnt_ecc_single_err_cnt_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.ecc_single_err_cnt[0].de),
+ .d (hw2reg.ecc_single_err_cnt[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ecc_single_err_cnt[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ecc_single_err_cnt_ecc_single_err_cnt_0_qs)
+ );
+
+ // F[ecc_single_err_cnt_1]: 15:8
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_ecc_single_err_cnt_ecc_single_err_cnt_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ecc_single_err_cnt_we),
+ .wd (ecc_single_err_cnt_ecc_single_err_cnt_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.ecc_single_err_cnt[1].de),
+ .d (hw2reg.ecc_single_err_cnt[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ecc_single_err_cnt[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ecc_single_err_cnt_ecc_single_err_cnt_1_qs)
+ );
+
+
+ // Subregister 0 of Multireg ecc_single_err_addr
+ // R[ecc_single_err_addr_0]: V(False)
+ prim_subreg #(
+ .DW (20),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (20'h0)
+ ) u_ecc_single_err_addr_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ecc_single_err_addr[0].de),
+ .d (hw2reg.ecc_single_err_addr[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ecc_single_err_addr_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg ecc_single_err_addr
+ // R[ecc_single_err_addr_1]: V(False)
+ prim_subreg #(
+ .DW (20),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (20'h0)
+ ) u_ecc_single_err_addr_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ecc_single_err_addr[1].de),
+ .d (hw2reg.ecc_single_err_addr[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ecc_single_err_addr_1_qs)
+ );
+
+
+ // R[phy_alert_cfg]: V(False)
+ // F[alert_ack]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_phy_alert_cfg_alert_ack (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (phy_alert_cfg_we),
+ .wd (phy_alert_cfg_alert_ack_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.phy_alert_cfg.alert_ack.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (phy_alert_cfg_alert_ack_qs)
+ );
+
+ // F[alert_trig]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_phy_alert_cfg_alert_trig (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (phy_alert_cfg_we),
+ .wd (phy_alert_cfg_alert_trig_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.phy_alert_cfg.alert_trig.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (phy_alert_cfg_alert_trig_qs)
+ );
+
+
+ // R[phy_status]: V(False)
+ // F[init_wip]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_phy_status_init_wip (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.init_wip.de),
+ .d (hw2reg.phy_status.init_wip.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (phy_status_init_wip_qs)
+ );
+
+ // F[prog_normal_avail]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_phy_status_prog_normal_avail (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.prog_normal_avail.de),
+ .d (hw2reg.phy_status.prog_normal_avail.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (phy_status_prog_normal_avail_qs)
+ );
+
+ // F[prog_repair_avail]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h1)
+ ) u_phy_status_prog_repair_avail (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.phy_status.prog_repair_avail.de),
+ .d (hw2reg.phy_status.prog_repair_avail.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (phy_status_prog_repair_avail_qs)
+ );
+
+
+ // R[scratch]: V(False)
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_scratch (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (scratch_we),
+ .wd (scratch_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.scratch.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (scratch_qs)
+ );
+
+
+ // R[fifo_lvl]: V(False)
+ // F[prog]: 4:0
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (5'hf)
+ ) u_fifo_lvl_prog (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fifo_lvl_we),
+ .wd (fifo_lvl_prog_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_lvl.prog.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fifo_lvl_prog_qs)
+ );
+
+ // F[rd]: 12:8
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (5'hf)
+ ) u_fifo_lvl_rd (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fifo_lvl_we),
+ .wd (fifo_lvl_rd_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_lvl.rd.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fifo_lvl_rd_qs)
+ );
+
+
+ // R[fifo_rst]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fifo_rst (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fifo_rst_we),
+ .wd (fifo_rst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fifo_rst.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fifo_rst_qs)
+ );
+
+
+ // R[curr_fifo_lvl]: V(True)
+ // F[prog]: 4:0
+ prim_subreg_ext #(
+ .DW (5)
+ ) u_curr_fifo_lvl_prog (
+ .re (curr_fifo_lvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.curr_fifo_lvl.prog.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (curr_fifo_lvl_prog_qs)
+ );
+
+ // F[rd]: 12:8
+ prim_subreg_ext #(
+ .DW (5)
+ ) u_curr_fifo_lvl_rd (
+ .re (curr_fifo_lvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.curr_fifo_lvl.rd.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (curr_fifo_lvl_rd_qs)
+ );
+
+
+
+ logic [107:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == FLASH_CTRL_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == FLASH_CTRL_DIS_OFFSET);
+ addr_hit[ 5] = (reg_addr == FLASH_CTRL_EXEC_OFFSET);
+ addr_hit[ 6] = (reg_addr == FLASH_CTRL_INIT_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
+ addr_hit[ 10] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
+ addr_hit[ 11] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
+ addr_hit[ 12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
+ addr_hit[ 13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
+ addr_hit[ 14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
+ addr_hit[ 15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
+ addr_hit[ 16] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
+ addr_hit[ 17] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
+ addr_hit[ 18] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
+ addr_hit[ 19] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
+ addr_hit[ 20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
+ addr_hit[ 21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
+ addr_hit[ 22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
+ addr_hit[ 23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
+ addr_hit[ 24] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
+ addr_hit[ 25] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
+ addr_hit[ 26] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
+ addr_hit[ 27] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
+ addr_hit[ 28] = (reg_addr == FLASH_CTRL_MP_REGION_0_OFFSET);
+ addr_hit[ 29] = (reg_addr == FLASH_CTRL_MP_REGION_1_OFFSET);
+ addr_hit[ 30] = (reg_addr == FLASH_CTRL_MP_REGION_2_OFFSET);
+ addr_hit[ 31] = (reg_addr == FLASH_CTRL_MP_REGION_3_OFFSET);
+ addr_hit[ 32] = (reg_addr == FLASH_CTRL_MP_REGION_4_OFFSET);
+ addr_hit[ 33] = (reg_addr == FLASH_CTRL_MP_REGION_5_OFFSET);
+ addr_hit[ 34] = (reg_addr == FLASH_CTRL_MP_REGION_6_OFFSET);
+ addr_hit[ 35] = (reg_addr == FLASH_CTRL_MP_REGION_7_OFFSET);
+ addr_hit[ 36] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+ addr_hit[ 37] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
+ addr_hit[ 38] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
+ addr_hit[ 39] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
+ addr_hit[ 40] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
+ addr_hit[ 41] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET);
+ addr_hit[ 42] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET);
+ addr_hit[ 43] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET);
+ addr_hit[ 44] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET);
+ addr_hit[ 45] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET);
+ addr_hit[ 46] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET);
+ addr_hit[ 47] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[ 48] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[ 49] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[ 50] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[ 51] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET);
+ addr_hit[ 52] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET);
+ addr_hit[ 53] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET);
+ addr_hit[ 54] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET);
+ addr_hit[ 55] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET);
+ addr_hit[ 56] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET);
+ addr_hit[ 57] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET);
+ addr_hit[ 58] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET);
+ addr_hit[ 59] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET);
+ addr_hit[ 60] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET);
+ addr_hit[ 61] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET);
+ addr_hit[ 62] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET);
+ addr_hit[ 63] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
+ addr_hit[ 64] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
+ addr_hit[ 65] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
+ addr_hit[ 66] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
+ addr_hit[ 67] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET);
+ addr_hit[ 68] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET);
+ addr_hit[ 69] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET);
+ addr_hit[ 70] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET);
+ addr_hit[ 71] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET);
+ addr_hit[ 72] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET);
+ addr_hit[ 73] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[ 74] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[ 75] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[ 76] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[ 77] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET);
+ addr_hit[ 78] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET);
+ addr_hit[ 79] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET);
+ addr_hit[ 80] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET);
+ addr_hit[ 81] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET);
+ addr_hit[ 82] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET);
+ addr_hit[ 83] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET);
+ addr_hit[ 84] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET);
+ addr_hit[ 85] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET);
+ addr_hit[ 86] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET);
+ addr_hit[ 87] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET);
+ addr_hit[ 88] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET);
+ addr_hit[ 89] = (reg_addr == FLASH_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET);
+ addr_hit[ 90] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+ addr_hit[ 91] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET);
+ addr_hit[ 92] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+ addr_hit[ 93] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+ addr_hit[ 94] = (reg_addr == FLASH_CTRL_DEBUG_STATE_OFFSET);
+ addr_hit[ 95] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
+ addr_hit[ 96] = (reg_addr == FLASH_CTRL_STD_FAULT_STATUS_OFFSET);
+ addr_hit[ 97] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
+ addr_hit[ 98] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
+ addr_hit[ 99] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
+ addr_hit[100] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
+ addr_hit[101] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
+ addr_hit[102] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
+ addr_hit[103] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[104] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[105] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[106] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ addr_hit[107] = (reg_addr == FLASH_CTRL_CURR_FIFO_LVL_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(FLASH_CTRL_CORE_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(FLASH_CTRL_CORE_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(FLASH_CTRL_CORE_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(FLASH_CTRL_CORE_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(FLASH_CTRL_CORE_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(FLASH_CTRL_CORE_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(FLASH_CTRL_CORE_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(FLASH_CTRL_CORE_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(FLASH_CTRL_CORE_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(FLASH_CTRL_CORE_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[ 10] & (|(FLASH_CTRL_CORE_PERMIT[ 10] & ~reg_be))) |
+ (addr_hit[ 11] & (|(FLASH_CTRL_CORE_PERMIT[ 11] & ~reg_be))) |
+ (addr_hit[ 12] & (|(FLASH_CTRL_CORE_PERMIT[ 12] & ~reg_be))) |
+ (addr_hit[ 13] & (|(FLASH_CTRL_CORE_PERMIT[ 13] & ~reg_be))) |
+ (addr_hit[ 14] & (|(FLASH_CTRL_CORE_PERMIT[ 14] & ~reg_be))) |
+ (addr_hit[ 15] & (|(FLASH_CTRL_CORE_PERMIT[ 15] & ~reg_be))) |
+ (addr_hit[ 16] & (|(FLASH_CTRL_CORE_PERMIT[ 16] & ~reg_be))) |
+ (addr_hit[ 17] & (|(FLASH_CTRL_CORE_PERMIT[ 17] & ~reg_be))) |
+ (addr_hit[ 18] & (|(FLASH_CTRL_CORE_PERMIT[ 18] & ~reg_be))) |
+ (addr_hit[ 19] & (|(FLASH_CTRL_CORE_PERMIT[ 19] & ~reg_be))) |
+ (addr_hit[ 20] & (|(FLASH_CTRL_CORE_PERMIT[ 20] & ~reg_be))) |
+ (addr_hit[ 21] & (|(FLASH_CTRL_CORE_PERMIT[ 21] & ~reg_be))) |
+ (addr_hit[ 22] & (|(FLASH_CTRL_CORE_PERMIT[ 22] & ~reg_be))) |
+ (addr_hit[ 23] & (|(FLASH_CTRL_CORE_PERMIT[ 23] & ~reg_be))) |
+ (addr_hit[ 24] & (|(FLASH_CTRL_CORE_PERMIT[ 24] & ~reg_be))) |
+ (addr_hit[ 25] & (|(FLASH_CTRL_CORE_PERMIT[ 25] & ~reg_be))) |
+ (addr_hit[ 26] & (|(FLASH_CTRL_CORE_PERMIT[ 26] & ~reg_be))) |
+ (addr_hit[ 27] & (|(FLASH_CTRL_CORE_PERMIT[ 27] & ~reg_be))) |
+ (addr_hit[ 28] & (|(FLASH_CTRL_CORE_PERMIT[ 28] & ~reg_be))) |
+ (addr_hit[ 29] & (|(FLASH_CTRL_CORE_PERMIT[ 29] & ~reg_be))) |
+ (addr_hit[ 30] & (|(FLASH_CTRL_CORE_PERMIT[ 30] & ~reg_be))) |
+ (addr_hit[ 31] & (|(FLASH_CTRL_CORE_PERMIT[ 31] & ~reg_be))) |
+ (addr_hit[ 32] & (|(FLASH_CTRL_CORE_PERMIT[ 32] & ~reg_be))) |
+ (addr_hit[ 33] & (|(FLASH_CTRL_CORE_PERMIT[ 33] & ~reg_be))) |
+ (addr_hit[ 34] & (|(FLASH_CTRL_CORE_PERMIT[ 34] & ~reg_be))) |
+ (addr_hit[ 35] & (|(FLASH_CTRL_CORE_PERMIT[ 35] & ~reg_be))) |
+ (addr_hit[ 36] & (|(FLASH_CTRL_CORE_PERMIT[ 36] & ~reg_be))) |
+ (addr_hit[ 37] & (|(FLASH_CTRL_CORE_PERMIT[ 37] & ~reg_be))) |
+ (addr_hit[ 38] & (|(FLASH_CTRL_CORE_PERMIT[ 38] & ~reg_be))) |
+ (addr_hit[ 39] & (|(FLASH_CTRL_CORE_PERMIT[ 39] & ~reg_be))) |
+ (addr_hit[ 40] & (|(FLASH_CTRL_CORE_PERMIT[ 40] & ~reg_be))) |
+ (addr_hit[ 41] & (|(FLASH_CTRL_CORE_PERMIT[ 41] & ~reg_be))) |
+ (addr_hit[ 42] & (|(FLASH_CTRL_CORE_PERMIT[ 42] & ~reg_be))) |
+ (addr_hit[ 43] & (|(FLASH_CTRL_CORE_PERMIT[ 43] & ~reg_be))) |
+ (addr_hit[ 44] & (|(FLASH_CTRL_CORE_PERMIT[ 44] & ~reg_be))) |
+ (addr_hit[ 45] & (|(FLASH_CTRL_CORE_PERMIT[ 45] & ~reg_be))) |
+ (addr_hit[ 46] & (|(FLASH_CTRL_CORE_PERMIT[ 46] & ~reg_be))) |
+ (addr_hit[ 47] & (|(FLASH_CTRL_CORE_PERMIT[ 47] & ~reg_be))) |
+ (addr_hit[ 48] & (|(FLASH_CTRL_CORE_PERMIT[ 48] & ~reg_be))) |
+ (addr_hit[ 49] & (|(FLASH_CTRL_CORE_PERMIT[ 49] & ~reg_be))) |
+ (addr_hit[ 50] & (|(FLASH_CTRL_CORE_PERMIT[ 50] & ~reg_be))) |
+ (addr_hit[ 51] & (|(FLASH_CTRL_CORE_PERMIT[ 51] & ~reg_be))) |
+ (addr_hit[ 52] & (|(FLASH_CTRL_CORE_PERMIT[ 52] & ~reg_be))) |
+ (addr_hit[ 53] & (|(FLASH_CTRL_CORE_PERMIT[ 53] & ~reg_be))) |
+ (addr_hit[ 54] & (|(FLASH_CTRL_CORE_PERMIT[ 54] & ~reg_be))) |
+ (addr_hit[ 55] & (|(FLASH_CTRL_CORE_PERMIT[ 55] & ~reg_be))) |
+ (addr_hit[ 56] & (|(FLASH_CTRL_CORE_PERMIT[ 56] & ~reg_be))) |
+ (addr_hit[ 57] & (|(FLASH_CTRL_CORE_PERMIT[ 57] & ~reg_be))) |
+ (addr_hit[ 58] & (|(FLASH_CTRL_CORE_PERMIT[ 58] & ~reg_be))) |
+ (addr_hit[ 59] & (|(FLASH_CTRL_CORE_PERMIT[ 59] & ~reg_be))) |
+ (addr_hit[ 60] & (|(FLASH_CTRL_CORE_PERMIT[ 60] & ~reg_be))) |
+ (addr_hit[ 61] & (|(FLASH_CTRL_CORE_PERMIT[ 61] & ~reg_be))) |
+ (addr_hit[ 62] & (|(FLASH_CTRL_CORE_PERMIT[ 62] & ~reg_be))) |
+ (addr_hit[ 63] & (|(FLASH_CTRL_CORE_PERMIT[ 63] & ~reg_be))) |
+ (addr_hit[ 64] & (|(FLASH_CTRL_CORE_PERMIT[ 64] & ~reg_be))) |
+ (addr_hit[ 65] & (|(FLASH_CTRL_CORE_PERMIT[ 65] & ~reg_be))) |
+ (addr_hit[ 66] & (|(FLASH_CTRL_CORE_PERMIT[ 66] & ~reg_be))) |
+ (addr_hit[ 67] & (|(FLASH_CTRL_CORE_PERMIT[ 67] & ~reg_be))) |
+ (addr_hit[ 68] & (|(FLASH_CTRL_CORE_PERMIT[ 68] & ~reg_be))) |
+ (addr_hit[ 69] & (|(FLASH_CTRL_CORE_PERMIT[ 69] & ~reg_be))) |
+ (addr_hit[ 70] & (|(FLASH_CTRL_CORE_PERMIT[ 70] & ~reg_be))) |
+ (addr_hit[ 71] & (|(FLASH_CTRL_CORE_PERMIT[ 71] & ~reg_be))) |
+ (addr_hit[ 72] & (|(FLASH_CTRL_CORE_PERMIT[ 72] & ~reg_be))) |
+ (addr_hit[ 73] & (|(FLASH_CTRL_CORE_PERMIT[ 73] & ~reg_be))) |
+ (addr_hit[ 74] & (|(FLASH_CTRL_CORE_PERMIT[ 74] & ~reg_be))) |
+ (addr_hit[ 75] & (|(FLASH_CTRL_CORE_PERMIT[ 75] & ~reg_be))) |
+ (addr_hit[ 76] & (|(FLASH_CTRL_CORE_PERMIT[ 76] & ~reg_be))) |
+ (addr_hit[ 77] & (|(FLASH_CTRL_CORE_PERMIT[ 77] & ~reg_be))) |
+ (addr_hit[ 78] & (|(FLASH_CTRL_CORE_PERMIT[ 78] & ~reg_be))) |
+ (addr_hit[ 79] & (|(FLASH_CTRL_CORE_PERMIT[ 79] & ~reg_be))) |
+ (addr_hit[ 80] & (|(FLASH_CTRL_CORE_PERMIT[ 80] & ~reg_be))) |
+ (addr_hit[ 81] & (|(FLASH_CTRL_CORE_PERMIT[ 81] & ~reg_be))) |
+ (addr_hit[ 82] & (|(FLASH_CTRL_CORE_PERMIT[ 82] & ~reg_be))) |
+ (addr_hit[ 83] & (|(FLASH_CTRL_CORE_PERMIT[ 83] & ~reg_be))) |
+ (addr_hit[ 84] & (|(FLASH_CTRL_CORE_PERMIT[ 84] & ~reg_be))) |
+ (addr_hit[ 85] & (|(FLASH_CTRL_CORE_PERMIT[ 85] & ~reg_be))) |
+ (addr_hit[ 86] & (|(FLASH_CTRL_CORE_PERMIT[ 86] & ~reg_be))) |
+ (addr_hit[ 87] & (|(FLASH_CTRL_CORE_PERMIT[ 87] & ~reg_be))) |
+ (addr_hit[ 88] & (|(FLASH_CTRL_CORE_PERMIT[ 88] & ~reg_be))) |
+ (addr_hit[ 89] & (|(FLASH_CTRL_CORE_PERMIT[ 89] & ~reg_be))) |
+ (addr_hit[ 90] & (|(FLASH_CTRL_CORE_PERMIT[ 90] & ~reg_be))) |
+ (addr_hit[ 91] & (|(FLASH_CTRL_CORE_PERMIT[ 91] & ~reg_be))) |
+ (addr_hit[ 92] & (|(FLASH_CTRL_CORE_PERMIT[ 92] & ~reg_be))) |
+ (addr_hit[ 93] & (|(FLASH_CTRL_CORE_PERMIT[ 93] & ~reg_be))) |
+ (addr_hit[ 94] & (|(FLASH_CTRL_CORE_PERMIT[ 94] & ~reg_be))) |
+ (addr_hit[ 95] & (|(FLASH_CTRL_CORE_PERMIT[ 95] & ~reg_be))) |
+ (addr_hit[ 96] & (|(FLASH_CTRL_CORE_PERMIT[ 96] & ~reg_be))) |
+ (addr_hit[ 97] & (|(FLASH_CTRL_CORE_PERMIT[ 97] & ~reg_be))) |
+ (addr_hit[ 98] & (|(FLASH_CTRL_CORE_PERMIT[ 98] & ~reg_be))) |
+ (addr_hit[ 99] & (|(FLASH_CTRL_CORE_PERMIT[ 99] & ~reg_be))) |
+ (addr_hit[100] & (|(FLASH_CTRL_CORE_PERMIT[100] & ~reg_be))) |
+ (addr_hit[101] & (|(FLASH_CTRL_CORE_PERMIT[101] & ~reg_be))) |
+ (addr_hit[102] & (|(FLASH_CTRL_CORE_PERMIT[102] & ~reg_be))) |
+ (addr_hit[103] & (|(FLASH_CTRL_CORE_PERMIT[103] & ~reg_be))) |
+ (addr_hit[104] & (|(FLASH_CTRL_CORE_PERMIT[104] & ~reg_be))) |
+ (addr_hit[105] & (|(FLASH_CTRL_CORE_PERMIT[105] & ~reg_be))) |
+ (addr_hit[106] & (|(FLASH_CTRL_CORE_PERMIT[106] & ~reg_be))) |
+ (addr_hit[107] & (|(FLASH_CTRL_CORE_PERMIT[107] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_prog_empty_wd = reg_wdata[0];
+
+ assign intr_state_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_state_rd_full_wd = reg_wdata[2];
+
+ assign intr_state_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_state_op_done_wd = reg_wdata[4];
+
+ assign intr_state_corr_err_wd = reg_wdata[5];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_prog_empty_wd = reg_wdata[0];
+
+ assign intr_enable_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_enable_rd_full_wd = reg_wdata[2];
+
+ assign intr_enable_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_enable_op_done_wd = reg_wdata[4];
+
+ assign intr_enable_corr_err_wd = reg_wdata[5];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_prog_empty_wd = reg_wdata[0];
+
+ assign intr_test_prog_lvl_wd = reg_wdata[1];
+
+ assign intr_test_rd_full_wd = reg_wdata[2];
+
+ assign intr_test_rd_lvl_wd = reg_wdata[3];
+
+ assign intr_test_op_done_wd = reg_wdata[4];
+
+ assign intr_test_corr_err_wd = reg_wdata[5];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_recov_err_wd = reg_wdata[0];
+
+ assign alert_test_fatal_std_err_wd = reg_wdata[1];
+
+ assign alert_test_fatal_err_wd = reg_wdata[2];
+
+ assign alert_test_fatal_prim_flash_alert_wd = reg_wdata[3];
+
+ assign alert_test_recov_prim_flash_alert_wd = reg_wdata[4];
+ assign dis_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign dis_wd = reg_wdata[3:0];
+ assign exec_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign exec_wd = reg_wdata[31:0];
+ assign init_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign init_wd = reg_wdata[0];
+ assign ctrl_regwen_re = addr_hit[7] & reg_re & !reg_error;
+ assign control_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign control_start_wd = reg_wdata[0];
+
+ assign control_op_wd = reg_wdata[5:4];
+
+ assign control_prog_sel_wd = reg_wdata[6];
+
+ assign control_erase_sel_wd = reg_wdata[7];
+
+ assign control_partition_sel_wd = reg_wdata[8];
+
+ assign control_info_sel_wd = reg_wdata[10:9];
+
+ assign control_num_wd = reg_wdata[27:16];
+ assign addr_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign addr_wd = reg_wdata[19:0];
+ assign prog_type_en_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign prog_type_en_normal_wd = reg_wdata[0];
+
+ assign prog_type_en_repair_wd = reg_wdata[1];
+ assign erase_suspend_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign erase_suspend_wd = reg_wdata[0];
+ assign region_cfg_regwen_0_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_0_wd = reg_wdata[0];
+ assign region_cfg_regwen_1_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_1_wd = reg_wdata[0];
+ assign region_cfg_regwen_2_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_2_wd = reg_wdata[0];
+ assign region_cfg_regwen_3_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_3_wd = reg_wdata[0];
+ assign region_cfg_regwen_4_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_4_wd = reg_wdata[0];
+ assign region_cfg_regwen_5_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_5_wd = reg_wdata[0];
+ assign region_cfg_regwen_6_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_6_wd = reg_wdata[0];
+ assign region_cfg_regwen_7_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign region_cfg_regwen_7_wd = reg_wdata[0];
+ assign mp_region_cfg_0_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign mp_region_cfg_0_en_0_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_0_he_en_0_wd = reg_wdata[27:24];
+ assign mp_region_cfg_1_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign mp_region_cfg_1_en_1_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_1_he_en_1_wd = reg_wdata[27:24];
+ assign mp_region_cfg_2_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign mp_region_cfg_2_en_2_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_2_he_en_2_wd = reg_wdata[27:24];
+ assign mp_region_cfg_3_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign mp_region_cfg_3_en_3_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_3_he_en_3_wd = reg_wdata[27:24];
+ assign mp_region_cfg_4_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign mp_region_cfg_4_en_4_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_4_he_en_4_wd = reg_wdata[27:24];
+ assign mp_region_cfg_5_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign mp_region_cfg_5_en_5_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_5_he_en_5_wd = reg_wdata[27:24];
+ assign mp_region_cfg_6_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign mp_region_cfg_6_en_6_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_6_he_en_6_wd = reg_wdata[27:24];
+ assign mp_region_cfg_7_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign mp_region_cfg_7_en_7_wd = reg_wdata[3:0];
+
+ assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[7:4];
+
+ assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[11:8];
+
+ assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[15:12];
+
+ assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
+
+ assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
+
+ assign mp_region_cfg_7_he_en_7_wd = reg_wdata[27:24];
+ assign mp_region_0_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign mp_region_0_base_0_wd = reg_wdata[8:0];
+
+ assign mp_region_0_size_0_wd = reg_wdata[18:9];
+ assign mp_region_1_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign mp_region_1_base_1_wd = reg_wdata[8:0];
+
+ assign mp_region_1_size_1_wd = reg_wdata[18:9];
+ assign mp_region_2_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign mp_region_2_base_2_wd = reg_wdata[8:0];
+
+ assign mp_region_2_size_2_wd = reg_wdata[18:9];
+ assign mp_region_3_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign mp_region_3_base_3_wd = reg_wdata[8:0];
+
+ assign mp_region_3_size_3_wd = reg_wdata[18:9];
+ assign mp_region_4_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign mp_region_4_base_4_wd = reg_wdata[8:0];
+
+ assign mp_region_4_size_4_wd = reg_wdata[18:9];
+ assign mp_region_5_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign mp_region_5_base_5_wd = reg_wdata[8:0];
+
+ assign mp_region_5_size_5_wd = reg_wdata[18:9];
+ assign mp_region_6_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign mp_region_6_base_6_wd = reg_wdata[8:0];
+
+ assign mp_region_6_size_6_wd = reg_wdata[18:9];
+ assign mp_region_7_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign mp_region_7_base_7_wd = reg_wdata[8:0];
+
+ assign mp_region_7_size_7_wd = reg_wdata[18:9];
+ assign default_region_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign default_region_rd_en_wd = reg_wdata[3:0];
+
+ assign default_region_prog_en_wd = reg_wdata[7:4];
+
+ assign default_region_erase_en_wd = reg_wdata[11:8];
+
+ assign default_region_scramble_en_wd = reg_wdata[15:12];
+
+ assign default_region_ecc_en_wd = reg_wdata[19:16];
+
+ assign default_region_he_en_wd = reg_wdata[23:20];
+ assign bank0_info0_regwen_0_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_0_wd = reg_wdata[0];
+ assign bank0_info0_regwen_1_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_1_wd = reg_wdata[0];
+ assign bank0_info0_regwen_2_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_2_wd = reg_wdata[0];
+ assign bank0_info0_regwen_3_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_3_wd = reg_wdata[0];
+ assign bank0_info0_regwen_4_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_4_wd = reg_wdata[0];
+ assign bank0_info0_regwen_5_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_5_wd = reg_wdata[0];
+ assign bank0_info0_regwen_6_we = addr_hit[43] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_6_wd = reg_wdata[0];
+ assign bank0_info0_regwen_7_we = addr_hit[44] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_7_wd = reg_wdata[0];
+ assign bank0_info0_regwen_8_we = addr_hit[45] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_8_wd = reg_wdata[0];
+ assign bank0_info0_regwen_9_we = addr_hit[46] & reg_we & !reg_error;
+
+ assign bank0_info0_regwen_9_wd = reg_wdata[0];
+ assign bank0_info0_page_cfg_0_we = addr_hit[47] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_1_we = addr_hit[48] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_2_we = addr_hit[49] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_3_we = addr_hit[50] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_4_we = addr_hit[51] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_4_en_4_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_4_rd_en_4_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_4_prog_en_4_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_4_erase_en_4_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_4_he_en_4_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_5_we = addr_hit[52] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_5_en_5_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_5_rd_en_5_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_5_prog_en_5_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_5_erase_en_5_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_5_he_en_5_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_6_we = addr_hit[53] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_6_en_6_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_6_rd_en_6_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_6_prog_en_6_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_6_erase_en_6_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_6_he_en_6_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_7_we = addr_hit[54] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_7_en_7_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_7_rd_en_7_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_7_prog_en_7_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_7_erase_en_7_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_7_he_en_7_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_8_we = addr_hit[55] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_8_en_8_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_8_rd_en_8_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_8_prog_en_8_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_8_erase_en_8_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_8_he_en_8_wd = reg_wdata[27:24];
+ assign bank0_info0_page_cfg_9_we = addr_hit[56] & reg_we & !reg_error;
+
+ assign bank0_info0_page_cfg_9_en_9_wd = reg_wdata[3:0];
+
+ assign bank0_info0_page_cfg_9_rd_en_9_wd = reg_wdata[7:4];
+
+ assign bank0_info0_page_cfg_9_prog_en_9_wd = reg_wdata[11:8];
+
+ assign bank0_info0_page_cfg_9_erase_en_9_wd = reg_wdata[15:12];
+
+ assign bank0_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[19:16];
+
+ assign bank0_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[23:20];
+
+ assign bank0_info0_page_cfg_9_he_en_9_wd = reg_wdata[27:24];
+ assign bank0_info1_regwen_we = addr_hit[57] & reg_we & !reg_error;
+
+ assign bank0_info1_regwen_wd = reg_wdata[0];
+ assign bank0_info1_page_cfg_we = addr_hit[58] & reg_we & !reg_error;
+
+ assign bank0_info1_page_cfg_en_0_wd = reg_wdata[3:0];
+
+ assign bank0_info1_page_cfg_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank0_info1_page_cfg_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank0_info1_page_cfg_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank0_info1_page_cfg_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank0_info1_page_cfg_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank0_info1_page_cfg_he_en_0_wd = reg_wdata[27:24];
+ assign bank0_info2_regwen_0_we = addr_hit[59] & reg_we & !reg_error;
+
+ assign bank0_info2_regwen_0_wd = reg_wdata[0];
+ assign bank0_info2_regwen_1_we = addr_hit[60] & reg_we & !reg_error;
+
+ assign bank0_info2_regwen_1_wd = reg_wdata[0];
+ assign bank0_info2_page_cfg_0_we = addr_hit[61] & reg_we & !reg_error;
+
+ assign bank0_info2_page_cfg_0_en_0_wd = reg_wdata[3:0];
+
+ assign bank0_info2_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank0_info2_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank0_info2_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank0_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank0_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank0_info2_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
+ assign bank0_info2_page_cfg_1_we = addr_hit[62] & reg_we & !reg_error;
+
+ assign bank0_info2_page_cfg_1_en_1_wd = reg_wdata[3:0];
+
+ assign bank0_info2_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
+
+ assign bank0_info2_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
+
+ assign bank0_info2_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
+
+ assign bank0_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
+
+ assign bank0_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
+
+ assign bank0_info2_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
+ assign bank1_info0_regwen_0_we = addr_hit[63] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_0_wd = reg_wdata[0];
+ assign bank1_info0_regwen_1_we = addr_hit[64] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_1_wd = reg_wdata[0];
+ assign bank1_info0_regwen_2_we = addr_hit[65] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_2_wd = reg_wdata[0];
+ assign bank1_info0_regwen_3_we = addr_hit[66] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_3_wd = reg_wdata[0];
+ assign bank1_info0_regwen_4_we = addr_hit[67] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_4_wd = reg_wdata[0];
+ assign bank1_info0_regwen_5_we = addr_hit[68] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_5_wd = reg_wdata[0];
+ assign bank1_info0_regwen_6_we = addr_hit[69] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_6_wd = reg_wdata[0];
+ assign bank1_info0_regwen_7_we = addr_hit[70] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_7_wd = reg_wdata[0];
+ assign bank1_info0_regwen_8_we = addr_hit[71] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_8_wd = reg_wdata[0];
+ assign bank1_info0_regwen_9_we = addr_hit[72] & reg_we & !reg_error;
+
+ assign bank1_info0_regwen_9_wd = reg_wdata[0];
+ assign bank1_info0_page_cfg_0_we = addr_hit[73] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_1_we = addr_hit[74] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_2_we = addr_hit[75] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_3_we = addr_hit[76] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_4_we = addr_hit[77] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_4_en_4_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_4_rd_en_4_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_4_prog_en_4_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_4_erase_en_4_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_4_he_en_4_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_5_we = addr_hit[78] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_5_en_5_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_5_rd_en_5_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_5_prog_en_5_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_5_erase_en_5_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_5_he_en_5_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_6_we = addr_hit[79] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_6_en_6_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_6_rd_en_6_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_6_prog_en_6_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_6_erase_en_6_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_6_he_en_6_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_7_we = addr_hit[80] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_7_en_7_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_7_rd_en_7_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_7_prog_en_7_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_7_erase_en_7_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_7_he_en_7_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_8_we = addr_hit[81] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_8_en_8_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_8_rd_en_8_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_8_prog_en_8_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_8_erase_en_8_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_8_he_en_8_wd = reg_wdata[27:24];
+ assign bank1_info0_page_cfg_9_we = addr_hit[82] & reg_we & !reg_error;
+
+ assign bank1_info0_page_cfg_9_en_9_wd = reg_wdata[3:0];
+
+ assign bank1_info0_page_cfg_9_rd_en_9_wd = reg_wdata[7:4];
+
+ assign bank1_info0_page_cfg_9_prog_en_9_wd = reg_wdata[11:8];
+
+ assign bank1_info0_page_cfg_9_erase_en_9_wd = reg_wdata[15:12];
+
+ assign bank1_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[19:16];
+
+ assign bank1_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[23:20];
+
+ assign bank1_info0_page_cfg_9_he_en_9_wd = reg_wdata[27:24];
+ assign bank1_info1_regwen_we = addr_hit[83] & reg_we & !reg_error;
+
+ assign bank1_info1_regwen_wd = reg_wdata[0];
+ assign bank1_info1_page_cfg_we = addr_hit[84] & reg_we & !reg_error;
+
+ assign bank1_info1_page_cfg_en_0_wd = reg_wdata[3:0];
+
+ assign bank1_info1_page_cfg_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank1_info1_page_cfg_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank1_info1_page_cfg_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank1_info1_page_cfg_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank1_info1_page_cfg_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank1_info1_page_cfg_he_en_0_wd = reg_wdata[27:24];
+ assign bank1_info2_regwen_0_we = addr_hit[85] & reg_we & !reg_error;
+
+ assign bank1_info2_regwen_0_wd = reg_wdata[0];
+ assign bank1_info2_regwen_1_we = addr_hit[86] & reg_we & !reg_error;
+
+ assign bank1_info2_regwen_1_wd = reg_wdata[0];
+ assign bank1_info2_page_cfg_0_we = addr_hit[87] & reg_we & !reg_error;
+
+ assign bank1_info2_page_cfg_0_en_0_wd = reg_wdata[3:0];
+
+ assign bank1_info2_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
+
+ assign bank1_info2_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
+
+ assign bank1_info2_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
+
+ assign bank1_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
+
+ assign bank1_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
+
+ assign bank1_info2_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
+ assign bank1_info2_page_cfg_1_we = addr_hit[88] & reg_we & !reg_error;
+
+ assign bank1_info2_page_cfg_1_en_1_wd = reg_wdata[3:0];
+
+ assign bank1_info2_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
+
+ assign bank1_info2_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
+
+ assign bank1_info2_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
+
+ assign bank1_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
+
+ assign bank1_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
+
+ assign bank1_info2_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
+ assign hw_info_cfg_override_we = addr_hit[89] & reg_we & !reg_error;
+
+ assign hw_info_cfg_override_scramble_dis_wd = reg_wdata[3:0];
+
+ assign hw_info_cfg_override_ecc_dis_wd = reg_wdata[7:4];
+ assign bank_cfg_regwen_we = addr_hit[90] & reg_we & !reg_error;
+
+ assign bank_cfg_regwen_wd = reg_wdata[0];
+ assign mp_bank_cfg_shadowed_re = addr_hit[91] & reg_re & !reg_error;
+ assign mp_bank_cfg_shadowed_we = addr_hit[91] & reg_we & !reg_error;
+
+ assign mp_bank_cfg_shadowed_erase_en_0_wd = reg_wdata[0];
+
+ assign mp_bank_cfg_shadowed_erase_en_1_wd = reg_wdata[1];
+ assign op_status_we = addr_hit[92] & reg_we & !reg_error;
+
+ assign op_status_done_wd = reg_wdata[0];
+
+ assign op_status_err_wd = reg_wdata[1];
+ assign debug_state_re = addr_hit[94] & reg_re & !reg_error;
+ assign err_code_we = addr_hit[95] & reg_we & !reg_error;
+
+ assign err_code_op_err_wd = reg_wdata[0];
+
+ assign err_code_mp_err_wd = reg_wdata[1];
+
+ assign err_code_rd_err_wd = reg_wdata[2];
+
+ assign err_code_prog_err_wd = reg_wdata[3];
+
+ assign err_code_prog_win_err_wd = reg_wdata[4];
+
+ assign err_code_prog_type_err_wd = reg_wdata[5];
+
+ assign err_code_update_err_wd = reg_wdata[6];
+
+ assign err_code_macro_err_wd = reg_wdata[7];
+ assign ecc_single_err_cnt_we = addr_hit[99] & reg_we & !reg_error;
+
+ assign ecc_single_err_cnt_ecc_single_err_cnt_0_wd = reg_wdata[7:0];
+
+ assign ecc_single_err_cnt_ecc_single_err_cnt_1_wd = reg_wdata[15:8];
+ assign phy_alert_cfg_we = addr_hit[102] & reg_we & !reg_error;
+
+ assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
+
+ assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
+ assign scratch_we = addr_hit[104] & reg_we & !reg_error;
+
+ assign scratch_wd = reg_wdata[31:0];
+ assign fifo_lvl_we = addr_hit[105] & reg_we & !reg_error;
+
+ assign fifo_lvl_prog_wd = reg_wdata[4:0];
+
+ assign fifo_lvl_rd_wd = reg_wdata[12:8];
+ assign fifo_rst_we = addr_hit[106] & reg_we & !reg_error;
+
+ assign fifo_rst_wd = reg_wdata[0];
+ assign curr_fifo_lvl_re = addr_hit[107] & reg_re & !reg_error;
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = intr_state_we;
+ reg_we_check[1] = intr_enable_we;
+ reg_we_check[2] = intr_test_we;
+ reg_we_check[3] = alert_test_we;
+ reg_we_check[4] = dis_we;
+ reg_we_check[5] = exec_we;
+ reg_we_check[6] = init_we;
+ reg_we_check[7] = 1'b0;
+ reg_we_check[8] = control_gated_we;
+ reg_we_check[9] = addr_gated_we;
+ reg_we_check[10] = prog_type_en_gated_we;
+ reg_we_check[11] = erase_suspend_we;
+ reg_we_check[12] = region_cfg_regwen_0_we;
+ reg_we_check[13] = region_cfg_regwen_1_we;
+ reg_we_check[14] = region_cfg_regwen_2_we;
+ reg_we_check[15] = region_cfg_regwen_3_we;
+ reg_we_check[16] = region_cfg_regwen_4_we;
+ reg_we_check[17] = region_cfg_regwen_5_we;
+ reg_we_check[18] = region_cfg_regwen_6_we;
+ reg_we_check[19] = region_cfg_regwen_7_we;
+ reg_we_check[20] = mp_region_cfg_0_gated_we;
+ reg_we_check[21] = mp_region_cfg_1_gated_we;
+ reg_we_check[22] = mp_region_cfg_2_gated_we;
+ reg_we_check[23] = mp_region_cfg_3_gated_we;
+ reg_we_check[24] = mp_region_cfg_4_gated_we;
+ reg_we_check[25] = mp_region_cfg_5_gated_we;
+ reg_we_check[26] = mp_region_cfg_6_gated_we;
+ reg_we_check[27] = mp_region_cfg_7_gated_we;
+ reg_we_check[28] = mp_region_0_gated_we;
+ reg_we_check[29] = mp_region_1_gated_we;
+ reg_we_check[30] = mp_region_2_gated_we;
+ reg_we_check[31] = mp_region_3_gated_we;
+ reg_we_check[32] = mp_region_4_gated_we;
+ reg_we_check[33] = mp_region_5_gated_we;
+ reg_we_check[34] = mp_region_6_gated_we;
+ reg_we_check[35] = mp_region_7_gated_we;
+ reg_we_check[36] = default_region_we;
+ reg_we_check[37] = bank0_info0_regwen_0_we;
+ reg_we_check[38] = bank0_info0_regwen_1_we;
+ reg_we_check[39] = bank0_info0_regwen_2_we;
+ reg_we_check[40] = bank0_info0_regwen_3_we;
+ reg_we_check[41] = bank0_info0_regwen_4_we;
+ reg_we_check[42] = bank0_info0_regwen_5_we;
+ reg_we_check[43] = bank0_info0_regwen_6_we;
+ reg_we_check[44] = bank0_info0_regwen_7_we;
+ reg_we_check[45] = bank0_info0_regwen_8_we;
+ reg_we_check[46] = bank0_info0_regwen_9_we;
+ reg_we_check[47] = bank0_info0_page_cfg_0_gated_we;
+ reg_we_check[48] = bank0_info0_page_cfg_1_gated_we;
+ reg_we_check[49] = bank0_info0_page_cfg_2_gated_we;
+ reg_we_check[50] = bank0_info0_page_cfg_3_gated_we;
+ reg_we_check[51] = bank0_info0_page_cfg_4_gated_we;
+ reg_we_check[52] = bank0_info0_page_cfg_5_gated_we;
+ reg_we_check[53] = bank0_info0_page_cfg_6_gated_we;
+ reg_we_check[54] = bank0_info0_page_cfg_7_gated_we;
+ reg_we_check[55] = bank0_info0_page_cfg_8_gated_we;
+ reg_we_check[56] = bank0_info0_page_cfg_9_gated_we;
+ reg_we_check[57] = bank0_info1_regwen_we;
+ reg_we_check[58] = bank0_info1_page_cfg_gated_we;
+ reg_we_check[59] = bank0_info2_regwen_0_we;
+ reg_we_check[60] = bank0_info2_regwen_1_we;
+ reg_we_check[61] = bank0_info2_page_cfg_0_gated_we;
+ reg_we_check[62] = bank0_info2_page_cfg_1_gated_we;
+ reg_we_check[63] = bank1_info0_regwen_0_we;
+ reg_we_check[64] = bank1_info0_regwen_1_we;
+ reg_we_check[65] = bank1_info0_regwen_2_we;
+ reg_we_check[66] = bank1_info0_regwen_3_we;
+ reg_we_check[67] = bank1_info0_regwen_4_we;
+ reg_we_check[68] = bank1_info0_regwen_5_we;
+ reg_we_check[69] = bank1_info0_regwen_6_we;
+ reg_we_check[70] = bank1_info0_regwen_7_we;
+ reg_we_check[71] = bank1_info0_regwen_8_we;
+ reg_we_check[72] = bank1_info0_regwen_9_we;
+ reg_we_check[73] = bank1_info0_page_cfg_0_gated_we;
+ reg_we_check[74] = bank1_info0_page_cfg_1_gated_we;
+ reg_we_check[75] = bank1_info0_page_cfg_2_gated_we;
+ reg_we_check[76] = bank1_info0_page_cfg_3_gated_we;
+ reg_we_check[77] = bank1_info0_page_cfg_4_gated_we;
+ reg_we_check[78] = bank1_info0_page_cfg_5_gated_we;
+ reg_we_check[79] = bank1_info0_page_cfg_6_gated_we;
+ reg_we_check[80] = bank1_info0_page_cfg_7_gated_we;
+ reg_we_check[81] = bank1_info0_page_cfg_8_gated_we;
+ reg_we_check[82] = bank1_info0_page_cfg_9_gated_we;
+ reg_we_check[83] = bank1_info1_regwen_we;
+ reg_we_check[84] = bank1_info1_page_cfg_gated_we;
+ reg_we_check[85] = bank1_info2_regwen_0_we;
+ reg_we_check[86] = bank1_info2_regwen_1_we;
+ reg_we_check[87] = bank1_info2_page_cfg_0_gated_we;
+ reg_we_check[88] = bank1_info2_page_cfg_1_gated_we;
+ reg_we_check[89] = hw_info_cfg_override_we;
+ reg_we_check[90] = bank_cfg_regwen_we;
+ reg_we_check[91] = mp_bank_cfg_shadowed_gated_we;
+ reg_we_check[92] = op_status_we;
+ reg_we_check[93] = 1'b0;
+ reg_we_check[94] = 1'b0;
+ reg_we_check[95] = err_code_we;
+ reg_we_check[96] = 1'b0;
+ reg_we_check[97] = 1'b0;
+ reg_we_check[98] = 1'b0;
+ reg_we_check[99] = ecc_single_err_cnt_we;
+ reg_we_check[100] = 1'b0;
+ reg_we_check[101] = 1'b0;
+ reg_we_check[102] = phy_alert_cfg_we;
+ reg_we_check[103] = 1'b0;
+ reg_we_check[104] = scratch_we;
+ reg_we_check[105] = fifo_lvl_we;
+ reg_we_check[106] = fifo_rst_we;
+ reg_we_check[107] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_prog_empty_qs;
+ reg_rdata_next[1] = intr_state_prog_lvl_qs;
+ reg_rdata_next[2] = intr_state_rd_full_qs;
+ reg_rdata_next[3] = intr_state_rd_lvl_qs;
+ reg_rdata_next[4] = intr_state_op_done_qs;
+ reg_rdata_next[5] = intr_state_corr_err_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_prog_empty_qs;
+ reg_rdata_next[1] = intr_enable_prog_lvl_qs;
+ reg_rdata_next[2] = intr_enable_rd_full_qs;
+ reg_rdata_next[3] = intr_enable_rd_lvl_qs;
+ reg_rdata_next[4] = intr_enable_op_done_qs;
+ reg_rdata_next[5] = intr_enable_corr_err_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ reg_rdata_next[4] = '0;
+ reg_rdata_next[5] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ reg_rdata_next[4] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[3:0] = dis_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[31:0] = exec_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = init_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = ctrl_regwen_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = control_start_qs;
+ reg_rdata_next[5:4] = control_op_qs;
+ reg_rdata_next[6] = control_prog_sel_qs;
+ reg_rdata_next[7] = control_erase_sel_qs;
+ reg_rdata_next[8] = control_partition_sel_qs;
+ reg_rdata_next[10:9] = control_info_sel_qs;
+ reg_rdata_next[27:16] = control_num_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[19:0] = addr_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = prog_type_en_normal_qs;
+ reg_rdata_next[1] = prog_type_en_repair_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = erase_suspend_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = region_cfg_regwen_0_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = region_cfg_regwen_1_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = region_cfg_regwen_2_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[0] = region_cfg_regwen_3_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = region_cfg_regwen_4_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[0] = region_cfg_regwen_5_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = region_cfg_regwen_6_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_0_en_0_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_0_rd_en_0_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_0_prog_en_0_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_0_erase_en_0_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_0_he_en_0_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_1_en_1_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_1_rd_en_1_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_1_prog_en_1_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_1_erase_en_1_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_1_he_en_1_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_2_en_2_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_2_rd_en_2_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_2_prog_en_2_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_2_erase_en_2_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_2_scramble_en_2_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_2_he_en_2_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_3_en_3_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_3_rd_en_3_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_3_prog_en_3_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_3_erase_en_3_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_3_scramble_en_3_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_3_he_en_3_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_4_en_4_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_4_rd_en_4_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_4_prog_en_4_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_4_erase_en_4_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_4_scramble_en_4_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_4_ecc_en_4_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_4_he_en_4_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_5_en_5_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_5_rd_en_5_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_5_prog_en_5_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_5_erase_en_5_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_5_scramble_en_5_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_5_ecc_en_5_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_5_he_en_5_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_6_en_6_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_6_rd_en_6_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_6_prog_en_6_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_6_erase_en_6_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_6_scramble_en_6_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_6_ecc_en_6_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_6_he_en_6_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[3:0] = mp_region_cfg_7_en_7_qs;
+ reg_rdata_next[7:4] = mp_region_cfg_7_rd_en_7_qs;
+ reg_rdata_next[11:8] = mp_region_cfg_7_prog_en_7_qs;
+ reg_rdata_next[15:12] = mp_region_cfg_7_erase_en_7_qs;
+ reg_rdata_next[19:16] = mp_region_cfg_7_scramble_en_7_qs;
+ reg_rdata_next[23:20] = mp_region_cfg_7_ecc_en_7_qs;
+ reg_rdata_next[27:24] = mp_region_cfg_7_he_en_7_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[8:0] = mp_region_0_base_0_qs;
+ reg_rdata_next[18:9] = mp_region_0_size_0_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[8:0] = mp_region_1_base_1_qs;
+ reg_rdata_next[18:9] = mp_region_1_size_1_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[8:0] = mp_region_2_base_2_qs;
+ reg_rdata_next[18:9] = mp_region_2_size_2_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[8:0] = mp_region_3_base_3_qs;
+ reg_rdata_next[18:9] = mp_region_3_size_3_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[8:0] = mp_region_4_base_4_qs;
+ reg_rdata_next[18:9] = mp_region_4_size_4_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[8:0] = mp_region_5_base_5_qs;
+ reg_rdata_next[18:9] = mp_region_5_size_5_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[8:0] = mp_region_6_base_6_qs;
+ reg_rdata_next[18:9] = mp_region_6_size_6_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[8:0] = mp_region_7_base_7_qs;
+ reg_rdata_next[18:9] = mp_region_7_size_7_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[3:0] = default_region_rd_en_qs;
+ reg_rdata_next[7:4] = default_region_prog_en_qs;
+ reg_rdata_next[11:8] = default_region_erase_en_qs;
+ reg_rdata_next[15:12] = default_region_scramble_en_qs;
+ reg_rdata_next[19:16] = default_region_ecc_en_qs;
+ reg_rdata_next[23:20] = default_region_he_en_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_0_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_1_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_2_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_3_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_4_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_5_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_6_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_7_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_8_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[0] = bank0_info0_regwen_9_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_0_en_0_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_0_he_en_0_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_1_en_1_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_1_he_en_1_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_2_en_2_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_2_scramble_en_2_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_2_he_en_2_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_3_en_3_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_3_scramble_en_3_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_3_he_en_3_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_4_en_4_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_4_rd_en_4_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_4_prog_en_4_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_4_erase_en_4_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_4_scramble_en_4_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_4_ecc_en_4_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_4_he_en_4_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_5_en_5_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_5_rd_en_5_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_5_prog_en_5_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_5_erase_en_5_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_5_scramble_en_5_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_5_ecc_en_5_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_5_he_en_5_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_6_en_6_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_6_rd_en_6_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_6_prog_en_6_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_6_erase_en_6_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_6_scramble_en_6_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_6_ecc_en_6_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_6_he_en_6_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_7_en_7_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_7_rd_en_7_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_7_prog_en_7_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_7_erase_en_7_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_7_scramble_en_7_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_7_ecc_en_7_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_7_he_en_7_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_8_en_8_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_8_rd_en_8_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_8_prog_en_8_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_8_erase_en_8_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_8_scramble_en_8_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_8_ecc_en_8_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_8_he_en_8_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[3:0] = bank0_info0_page_cfg_9_en_9_qs;
+ reg_rdata_next[7:4] = bank0_info0_page_cfg_9_rd_en_9_qs;
+ reg_rdata_next[11:8] = bank0_info0_page_cfg_9_prog_en_9_qs;
+ reg_rdata_next[15:12] = bank0_info0_page_cfg_9_erase_en_9_qs;
+ reg_rdata_next[19:16] = bank0_info0_page_cfg_9_scramble_en_9_qs;
+ reg_rdata_next[23:20] = bank0_info0_page_cfg_9_ecc_en_9_qs;
+ reg_rdata_next[27:24] = bank0_info0_page_cfg_9_he_en_9_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[0] = bank0_info1_regwen_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[3:0] = bank0_info1_page_cfg_en_0_qs;
+ reg_rdata_next[7:4] = bank0_info1_page_cfg_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank0_info1_page_cfg_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank0_info1_page_cfg_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank0_info1_page_cfg_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank0_info1_page_cfg_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank0_info1_page_cfg_he_en_0_qs;
+ end
+
+ addr_hit[59]: begin
+ reg_rdata_next[0] = bank0_info2_regwen_0_qs;
+ end
+
+ addr_hit[60]: begin
+ reg_rdata_next[0] = bank0_info2_regwen_1_qs;
+ end
+
+ addr_hit[61]: begin
+ reg_rdata_next[3:0] = bank0_info2_page_cfg_0_en_0_qs;
+ reg_rdata_next[7:4] = bank0_info2_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank0_info2_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank0_info2_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank0_info2_page_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank0_info2_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank0_info2_page_cfg_0_he_en_0_qs;
+ end
+
+ addr_hit[62]: begin
+ reg_rdata_next[3:0] = bank0_info2_page_cfg_1_en_1_qs;
+ reg_rdata_next[7:4] = bank0_info2_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[11:8] = bank0_info2_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[15:12] = bank0_info2_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[19:16] = bank0_info2_page_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[23:20] = bank0_info2_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[27:24] = bank0_info2_page_cfg_1_he_en_1_qs;
+ end
+
+ addr_hit[63]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_0_qs;
+ end
+
+ addr_hit[64]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_1_qs;
+ end
+
+ addr_hit[65]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_2_qs;
+ end
+
+ addr_hit[66]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_3_qs;
+ end
+
+ addr_hit[67]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_4_qs;
+ end
+
+ addr_hit[68]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_5_qs;
+ end
+
+ addr_hit[69]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_6_qs;
+ end
+
+ addr_hit[70]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_7_qs;
+ end
+
+ addr_hit[71]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_8_qs;
+ end
+
+ addr_hit[72]: begin
+ reg_rdata_next[0] = bank1_info0_regwen_9_qs;
+ end
+
+ addr_hit[73]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_0_en_0_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_0_he_en_0_qs;
+ end
+
+ addr_hit[74]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_1_en_1_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_1_he_en_1_qs;
+ end
+
+ addr_hit[75]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_2_en_2_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_2_rd_en_2_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_2_prog_en_2_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_2_erase_en_2_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_2_scramble_en_2_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_2_he_en_2_qs;
+ end
+
+ addr_hit[76]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_3_en_3_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_3_rd_en_3_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_3_prog_en_3_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_3_erase_en_3_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_3_scramble_en_3_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_3_he_en_3_qs;
+ end
+
+ addr_hit[77]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_4_en_4_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_4_rd_en_4_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_4_prog_en_4_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_4_erase_en_4_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_4_scramble_en_4_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_4_ecc_en_4_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_4_he_en_4_qs;
+ end
+
+ addr_hit[78]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_5_en_5_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_5_rd_en_5_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_5_prog_en_5_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_5_erase_en_5_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_5_scramble_en_5_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_5_ecc_en_5_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_5_he_en_5_qs;
+ end
+
+ addr_hit[79]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_6_en_6_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_6_rd_en_6_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_6_prog_en_6_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_6_erase_en_6_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_6_scramble_en_6_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_6_ecc_en_6_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_6_he_en_6_qs;
+ end
+
+ addr_hit[80]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_7_en_7_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_7_rd_en_7_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_7_prog_en_7_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_7_erase_en_7_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_7_scramble_en_7_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_7_ecc_en_7_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_7_he_en_7_qs;
+ end
+
+ addr_hit[81]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_8_en_8_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_8_rd_en_8_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_8_prog_en_8_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_8_erase_en_8_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_8_scramble_en_8_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_8_ecc_en_8_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_8_he_en_8_qs;
+ end
+
+ addr_hit[82]: begin
+ reg_rdata_next[3:0] = bank1_info0_page_cfg_9_en_9_qs;
+ reg_rdata_next[7:4] = bank1_info0_page_cfg_9_rd_en_9_qs;
+ reg_rdata_next[11:8] = bank1_info0_page_cfg_9_prog_en_9_qs;
+ reg_rdata_next[15:12] = bank1_info0_page_cfg_9_erase_en_9_qs;
+ reg_rdata_next[19:16] = bank1_info0_page_cfg_9_scramble_en_9_qs;
+ reg_rdata_next[23:20] = bank1_info0_page_cfg_9_ecc_en_9_qs;
+ reg_rdata_next[27:24] = bank1_info0_page_cfg_9_he_en_9_qs;
+ end
+
+ addr_hit[83]: begin
+ reg_rdata_next[0] = bank1_info1_regwen_qs;
+ end
+
+ addr_hit[84]: begin
+ reg_rdata_next[3:0] = bank1_info1_page_cfg_en_0_qs;
+ reg_rdata_next[7:4] = bank1_info1_page_cfg_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank1_info1_page_cfg_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank1_info1_page_cfg_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank1_info1_page_cfg_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank1_info1_page_cfg_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank1_info1_page_cfg_he_en_0_qs;
+ end
+
+ addr_hit[85]: begin
+ reg_rdata_next[0] = bank1_info2_regwen_0_qs;
+ end
+
+ addr_hit[86]: begin
+ reg_rdata_next[0] = bank1_info2_regwen_1_qs;
+ end
+
+ addr_hit[87]: begin
+ reg_rdata_next[3:0] = bank1_info2_page_cfg_0_en_0_qs;
+ reg_rdata_next[7:4] = bank1_info2_page_cfg_0_rd_en_0_qs;
+ reg_rdata_next[11:8] = bank1_info2_page_cfg_0_prog_en_0_qs;
+ reg_rdata_next[15:12] = bank1_info2_page_cfg_0_erase_en_0_qs;
+ reg_rdata_next[19:16] = bank1_info2_page_cfg_0_scramble_en_0_qs;
+ reg_rdata_next[23:20] = bank1_info2_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[27:24] = bank1_info2_page_cfg_0_he_en_0_qs;
+ end
+
+ addr_hit[88]: begin
+ reg_rdata_next[3:0] = bank1_info2_page_cfg_1_en_1_qs;
+ reg_rdata_next[7:4] = bank1_info2_page_cfg_1_rd_en_1_qs;
+ reg_rdata_next[11:8] = bank1_info2_page_cfg_1_prog_en_1_qs;
+ reg_rdata_next[15:12] = bank1_info2_page_cfg_1_erase_en_1_qs;
+ reg_rdata_next[19:16] = bank1_info2_page_cfg_1_scramble_en_1_qs;
+ reg_rdata_next[23:20] = bank1_info2_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[27:24] = bank1_info2_page_cfg_1_he_en_1_qs;
+ end
+
+ addr_hit[89]: begin
+ reg_rdata_next[3:0] = hw_info_cfg_override_scramble_dis_qs;
+ reg_rdata_next[7:4] = hw_info_cfg_override_ecc_dis_qs;
+ end
+
+ addr_hit[90]: begin
+ reg_rdata_next[0] = bank_cfg_regwen_qs;
+ end
+
+ addr_hit[91]: begin
+ reg_rdata_next[0] = mp_bank_cfg_shadowed_erase_en_0_qs;
+ reg_rdata_next[1] = mp_bank_cfg_shadowed_erase_en_1_qs;
+ end
+
+ addr_hit[92]: begin
+ reg_rdata_next[0] = op_status_done_qs;
+ reg_rdata_next[1] = op_status_err_qs;
+ end
+
+ addr_hit[93]: begin
+ reg_rdata_next[0] = status_rd_full_qs;
+ reg_rdata_next[1] = status_rd_empty_qs;
+ reg_rdata_next[2] = status_prog_full_qs;
+ reg_rdata_next[3] = status_prog_empty_qs;
+ reg_rdata_next[4] = status_init_wip_qs;
+ reg_rdata_next[5] = status_initialized_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[10:0] = debug_state_qs;
+ end
+
+ addr_hit[95]: begin
+ reg_rdata_next[0] = err_code_op_err_qs;
+ reg_rdata_next[1] = err_code_mp_err_qs;
+ reg_rdata_next[2] = err_code_rd_err_qs;
+ reg_rdata_next[3] = err_code_prog_err_qs;
+ reg_rdata_next[4] = err_code_prog_win_err_qs;
+ reg_rdata_next[5] = err_code_prog_type_err_qs;
+ reg_rdata_next[6] = err_code_update_err_qs;
+ reg_rdata_next[7] = err_code_macro_err_qs;
+ end
+
+ addr_hit[96]: begin
+ reg_rdata_next[0] = std_fault_status_reg_intg_err_qs;
+ reg_rdata_next[1] = std_fault_status_prog_intg_err_qs;
+ reg_rdata_next[2] = std_fault_status_lcmgr_err_qs;
+ reg_rdata_next[3] = std_fault_status_lcmgr_intg_err_qs;
+ reg_rdata_next[4] = std_fault_status_arb_fsm_err_qs;
+ reg_rdata_next[5] = std_fault_status_storage_err_qs;
+ reg_rdata_next[6] = std_fault_status_phy_fsm_err_qs;
+ reg_rdata_next[7] = std_fault_status_ctrl_cnt_err_qs;
+ reg_rdata_next[8] = std_fault_status_fifo_err_qs;
+ end
+
+ addr_hit[97]: begin
+ reg_rdata_next[0] = fault_status_op_err_qs;
+ reg_rdata_next[1] = fault_status_mp_err_qs;
+ reg_rdata_next[2] = fault_status_rd_err_qs;
+ reg_rdata_next[3] = fault_status_prog_err_qs;
+ reg_rdata_next[4] = fault_status_prog_win_err_qs;
+ reg_rdata_next[5] = fault_status_prog_type_err_qs;
+ reg_rdata_next[6] = fault_status_seed_err_qs;
+ reg_rdata_next[7] = fault_status_phy_relbl_err_qs;
+ reg_rdata_next[8] = fault_status_phy_storage_err_qs;
+ reg_rdata_next[9] = fault_status_spurious_ack_qs;
+ reg_rdata_next[10] = fault_status_arb_err_qs;
+ reg_rdata_next[11] = fault_status_host_gnt_err_qs;
+ end
+
+ addr_hit[98]: begin
+ reg_rdata_next[19:0] = err_addr_qs;
+ end
+
+ addr_hit[99]: begin
+ reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
+ reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
+ end
+
+ addr_hit[100]: begin
+ reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
+ end
+
+ addr_hit[101]: begin
+ reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
+ end
+
+ addr_hit[102]: begin
+ reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
+ reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
+ end
+
+ addr_hit[103]: begin
+ reg_rdata_next[0] = phy_status_init_wip_qs;
+ reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
+ reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
+ end
+
+ addr_hit[104]: begin
+ reg_rdata_next[31:0] = scratch_qs;
+ end
+
+ addr_hit[105]: begin
+ reg_rdata_next[4:0] = fifo_lvl_prog_qs;
+ reg_rdata_next[12:8] = fifo_lvl_rd_qs;
+ end
+
+ addr_hit[106]: begin
+ reg_rdata_next[0] = fifo_rst_qs;
+ end
+
+ addr_hit[107]: begin
+ reg_rdata_next[4:0] = curr_fifo_lvl_prog_qs;
+ reg_rdata_next[12:8] = curr_fifo_lvl_rd_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ logic rst_done;
+ logic shadow_rst_done;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rst_done <= '0;
+ end else begin
+ rst_done <= 1'b1;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
+ if (!rst_shadowed_ni) begin
+ shadow_rst_done <= '0;
+ end else begin
+ shadow_rst_done <= 1'b1;
+ end
+ end
+
+ // both shadow and normal resets have been released
+ assign shadow_busy = ~(rst_done & shadow_rst_done);
+
+ // Collect up storage and update errors
+ assign shadowed_storage_err_o = |{
+ mp_bank_cfg_shadowed_erase_en_0_storage_err,
+ mp_bank_cfg_shadowed_erase_en_1_storage_err
+ };
+ assign shadowed_update_err_o = |{
+ mp_bank_cfg_shadowed_erase_en_0_update_err,
+ mp_bank_cfg_shadowed_erase_en_1_update_err
+ };
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv
new file mode 100644
index 0000000..de7343a
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_mem_reg_top.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_mem_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+
+
+ // Since there are no registers in this block, commands are routed through to windows which
+ // can report their own integrity errors.
+ assign intg_err_o = 1'b0;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ // Unused signal tieoff
+ // devmode_i is not used if there are no registers
+ logic unused_devmode;
+ assign unused_devmode = ^devmode_i;
+endmodule
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
new file mode 100644
index 0000000..4bb4672
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
@@ -0,0 +1,653 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash Controller module.
+//
+
+package flash_ctrl_pkg;
+
+ // design parameters that can be altered through topgen
+ parameter int unsigned NumBanks = flash_ctrl_reg_pkg::RegNumBanks;
+ parameter int unsigned PagesPerBank = flash_ctrl_reg_pkg::RegPagesPerBank;
+ parameter int unsigned BusPgmResBytes = flash_ctrl_reg_pkg::RegBusPgmResBytes;
+ // How many types of info per bank
+ parameter int InfoTypes = flash_ctrl_reg_pkg::NumInfoTypes;
+
+ // fixed parameters of flash derived from topgen parameters
+ parameter int DataWidth = 64;
+ parameter int MetaDataWidth = 12;
+
+// The following hard-wired values are there to work-around verilator.
+// For some reason if the values are assigned through parameters verilator thinks
+// they are not constant
+ parameter int InfoTypeSize [InfoTypes] = '{
+ 10,
+ 1,
+ 2
+ };
+ parameter int InfosPerBank = max_info_pages('{
+ 10,
+ 1,
+ 2
+ });
+ parameter int WordsPerPage = 256; // Number of flash words per page
+ parameter int BusWidth = top_pkg::TL_DW;
+ parameter int BusIntgWidth = tlul_pkg::DataIntgWidth;
+ parameter int BusFullWidth = BusWidth + BusIntgWidth;
+ parameter int MpRegions = 8; // flash controller protection regions
+ //parameter int FifoDepth = 16; // rd / prog fifos
+ parameter int InfoTypesWidth = prim_util_pkg::vbits(InfoTypes);
+
+ // flash phy parameters
+ parameter int DataByteWidth = prim_util_pkg::vbits(DataWidth / 8);
+ parameter int BankW = prim_util_pkg::vbits(NumBanks);
+ parameter int InfoPageW = prim_util_pkg::vbits(InfosPerBank);
+ parameter int PageW = prim_util_pkg::vbits(PagesPerBank);
+ parameter int WordW = prim_util_pkg::vbits(WordsPerPage);
+ parameter int AddrW = BankW + PageW + WordW; // all flash range
+ parameter int BankAddrW = PageW + WordW; // 1 bank of flash range
+ parameter int AllPagesW = BankW + PageW;
+
+ // flash ctrl / bus parameters
+ // flash / bus width may be different from actual flash word width
+ parameter int BusBytes = BusWidth / 8;
+ parameter int BusByteWidth = prim_util_pkg::vbits(BusBytes);
+ parameter int WidthMultiple = DataWidth / BusWidth;
+ // Number of bus words that can be programmed at once
+ parameter int BusPgmRes = BusPgmResBytes / BusBytes;
+ parameter int BusPgmResWidth = prim_util_pkg::vbits(BusPgmRes);
+ parameter int BusWordsPerPage = WordsPerPage * WidthMultiple;
+ parameter int BusWordW = prim_util_pkg::vbits(BusWordsPerPage);
+ parameter int BusAddrW = BankW + PageW + BusWordW;
+ parameter int BusAddrByteW = BusAddrW + BusByteWidth;
+ parameter int BusBankAddrW = PageW + BusWordW;
+ parameter int PhyAddrStart = BusWordW - WordW;
+
+ // fifo parameters
+ //parameter int FifoDepthW = prim_util_pkg::vbits(FifoDepth+1);
+
+ // The end address in bus words for each kind of partition in each bank
+ parameter logic [PageW-1:0] DataPartitionEndAddr = PageW'(PagesPerBank - 1);
+ //parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ // 9,
+ // 0,
+ // 1
+ //};
+ parameter logic [PageW-1:0] InfoPartitionEndAddr [InfoTypes] = '{
+ PageW'(InfoTypeSize[0] - 1),
+ PageW'(InfoTypeSize[1] - 1),
+ PageW'(InfoTypeSize[2] - 1)
+ };
+
+ // Flash Disable usage
+ typedef enum logic [3:0] {
+ PhyDisableIdx,
+ ArbFsmDisableIdx,
+ LcMgrDisableIdx,
+ MpDisableIdx,
+ HostDisableIdx,
+ IFetchDisableIdx,
+ RdFifoIdx,
+ ProgFifoIdx,
+ FlashDisableLast
+ } flash_disable_pos_e;
+
+ ////////////////////////////
+ // All memory protection, seed related parameters
+ // Those related for seed pages should be template candidates
+ ////////////////////////////
+
+ // parameters for connected components
+ parameter int SeedWidth = 256;
+ parameter int KeyWidth = 128;
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
+ typedef logic [KeyWidth-1:0] flash_key_t;
+
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
+ // lcmgr phase enum
+ typedef enum logic [1:0] {
+ PhaseSeed,
+ PhaseRma,
+ PhaseNone,
+ PhaseInvalid
+ } flash_lcmgr_phase_e;
+
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_mp_region_cfg_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t;
+ import flash_ctrl_reg_pkg::flash_ctrl_reg2hw_default_region_reg_t;
+
+ typedef flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t sw_bank_cfg_t;
+ typedef flash_ctrl_reg2hw_mp_region_mreg_t sw_region_t;
+ typedef flash_ctrl_reg2hw_mp_region_cfg_mreg_t sw_region_cfg_t;
+ typedef flash_ctrl_reg2hw_default_region_reg_t sw_default_cfg_t;
+ typedef flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t sw_info_cfg_t;
+
+ // alias for super long reg_pkg typedef
+ typedef struct packed {
+ logic q;
+ } bank_cfg_t;
+
+ import prim_mubi_pkg::mubi4_t;
+ import prim_mubi_pkg::MuBi4True;
+ import prim_mubi_pkg::MuBi4False;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ mubi4_t en;
+ mubi4_t rd_en;
+ mubi4_t prog_en;
+ mubi4_t erase_en;
+ mubi4_t scramble_en;
+ mubi4_t ecc_en;
+ mubi4_t he_en;
+ } info_page_cfg_t;
+
+ // This is identical to the reg structures but do not have err_updates / storage
+ typedef struct packed {
+ mubi4_t en;
+ mubi4_t rd_en;
+ mubi4_t prog_en;
+ mubi4_t erase_en;
+ mubi4_t scramble_en;
+ mubi4_t ecc_en;
+ mubi4_t he_en;
+ logic [8:0] base;
+ logic [9:0] size;
+ } mp_region_cfg_t;
+
+ // memory protection specific structs
+ typedef struct packed {
+ logic [InfoTypesWidth-1:0] sel;
+ logic [AllPagesW-1:0] addr;
+ } page_addr_t;
+
+ typedef struct packed {
+ page_addr_t page;
+ flash_lcmgr_phase_e phase;
+ info_page_cfg_t cfg;
+ } info_page_attr_t;
+
+ typedef struct packed {
+ flash_lcmgr_phase_e phase;
+ mp_region_cfg_t cfg;
+ } data_region_attr_t;
+
+ // flash life cycle / key manager management constants
+ // One page for creator seeds
+ // One page for owner seeds
+ // One page for isolated flash page
+ parameter int NumSeeds = 2;
+ parameter bit [BankW-1:0] SeedBank = 0;
+ parameter bit [InfoTypesWidth-1:0] SeedInfoSel = 0;
+ parameter bit [0:0] CreatorSeedIdx = 0;
+ parameter bit [0:0] OwnerSeedIdx = 1;
+ parameter bit [PageW-1:0] CreatorInfoPage = 1;
+ parameter bit [PageW-1:0] OwnerInfoPage = 2;
+ parameter bit [PageW-1:0] IsolatedInfoPage = 3;
+
+ parameter int TotalSeedWidth = SeedWidth * NumSeeds;
+ typedef logic [TotalSeedWidth-1:0] all_seeds_t;
+
+ // which page of which info type of which bank for seed selection
+ parameter page_addr_t SeedInfoPageSel [NumSeeds] = '{
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, CreatorInfoPage}
+ },
+
+ '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, OwnerInfoPage}
+ }
+ };
+
+ // which page of which info type of which bank for isolated partition
+ parameter page_addr_t IsolatedPageSel = '{
+ sel: SeedInfoSel,
+ addr: {SeedBank, IsolatedInfoPage}
+ };
+
+ // hardware interface memory protection rules
+ parameter int HwInfoRules = 5;
+ parameter int HwDataRules = 1;
+
+ parameter info_page_cfg_t CfgAllowRead = '{
+ en: MuBi4True,
+ rd_en: MuBi4True,
+ prog_en: MuBi4False,
+ erase_en: MuBi4False,
+ scramble_en: MuBi4True,
+ ecc_en: MuBi4True,
+ he_en: MuBi4True
+ };
+
+ parameter info_page_cfg_t CfgAllowReadProgErase = '{
+ en: MuBi4True,
+ rd_en: MuBi4True,
+ prog_en: MuBi4True,
+ erase_en: MuBi4True,
+ scramble_en: MuBi4True,
+ ecc_en: MuBi4True,
+ he_en: MuBi4True // HW assumes high endurance
+ };
+
+ parameter info_page_cfg_t CfgInfoDisable = '{
+ en: MuBi4False,
+ rd_en: MuBi4False,
+ prog_en: MuBi4False,
+ erase_en: MuBi4False,
+ scramble_en: MuBi4False,
+ ecc_en: MuBi4False,
+ he_en: MuBi4False
+ };
+
+ parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseSeed,
+ cfg: CfgAllowRead
+ },
+
+ '{
+ page: SeedInfoPageSel[CreatorSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: SeedInfoPageSel[OwnerSeedIdx],
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ },
+
+ '{
+ page: IsolatedPageSel,
+ phase: PhaseRma,
+ cfg: CfgAllowReadProgErase
+ }
+ };
+
+ parameter data_region_attr_t HwDataAttr[HwDataRules] = '{
+ '{
+ phase: PhaseRma,
+ cfg: '{
+ en: MuBi4True,
+ rd_en: MuBi4True,
+ prog_en: MuBi4True,
+ erase_en: MuBi4True,
+ scramble_en: MuBi4True,
+ ecc_en: MuBi4True,
+ he_en: MuBi4True, // HW assumes high endurance
+ base: '0,
+ size: NumBanks * PagesPerBank
+ }
+ }
+ };
+
+
+ ////////////////////////////
+ // Design time constants
+ ////////////////////////////
+ parameter flash_key_t RndCnstAddrKeyDefault =
+ 128'h5d707f8a2d01d400928fa691c6a6e0a4;
+ parameter flash_key_t RndCnstDataKeyDefault =
+ 128'h39953618f2ca6f674af39f64975ea1f5;
+ parameter all_seeds_t RndCnstAllSeedsDefault = {
+ 256'h3528874c0d9e481ead4d240eb6238a2c6218896f5315edb5ccefe029a6d04091,
+ 256'h9cde77e25a313a76984ab0ebf990983432b03b48186dcd556565fe721b447477
+ };
+
+
+ ////////////////////////////
+ // Flash operation related enums
+ ////////////////////////////
+
+ // Flash Operations Supported
+ typedef enum logic [1:0] {
+ FlashOpRead = 2'h0,
+ FlashOpProgram = 2'h1,
+ FlashOpErase = 2'h2,
+ FlashOpInvalid = 2'h3
+ } flash_op_e;
+
+ // Flash Program Operations Supported
+ typedef enum logic {
+ FlashProgNormal = 0,
+ FlashProgRepair = 1
+ } flash_prog_e;
+ parameter int ProgTypes = 2;
+
+ // Flash Erase Operations Supported
+ typedef enum logic {
+ FlashErasePage = 0,
+ FlashEraseBank = 1
+ } flash_erase_e;
+
+ // Flash function select
+ typedef enum logic [1:0] {
+ NoneSel,
+ SwSel,
+ HwSel
+ } flash_sel_e;
+
+ // Flash tlul to fifo direction
+ typedef enum logic {
+ WriteDir = 1'b0,
+ ReadDir = 1'b1
+ } flash_flfo_dir_e;
+
+ // Flash partition type
+ typedef enum logic {
+ FlashPartData = 1'b0,
+ FlashPartInfo = 1'b1
+ } flash_part_e;
+
+ // Flash controller to memory
+ typedef struct packed {
+ logic req;
+ logic scramble_en;
+ logic ecc_en;
+ logic he_en;
+ logic rd_buf_en;
+ logic rd;
+ logic prog;
+ logic pg_erase;
+ logic bk_erase;
+ logic erase_suspend;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [BusAddrW-1:0] addr;
+ logic [BusFullWidth-1:0] prog_data;
+ logic prog_last;
+ flash_prog_e prog_type;
+ mp_region_cfg_t [MpRegions:0] region_cfgs;
+ logic [KeyWidth-1:0] addr_key;
+ logic [KeyWidth-1:0] data_key;
+ logic [KeyWidth-1:0] rand_addr_key;
+ logic [KeyWidth-1:0] rand_data_key;
+ logic alert_trig;
+ logic alert_ack;
+ jtag_pkg::jtag_req_t jtag_req;
+ prim_mubi_pkg::mubi4_t flash_disable;
+ } flash_req_t;
+
+ // default value of flash_req_t (for dangling ports)
+ parameter flash_req_t FLASH_REQ_DEFAULT = '{
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd_buf_en: 1'b0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rand_addr_key: '0,
+ rand_data_key: '0,
+ alert_trig: 1'b0,
+ alert_ack: 1'b0,
+ jtag_req: '0,
+ flash_disable: prim_mubi_pkg::MuBi4False
+ };
+
+ // memory to flash controller
+ typedef struct packed {
+ logic [ProgTypes-1:0] prog_type_avail;
+ logic rd_done;
+ logic prog_done;
+ logic erase_done;
+ logic rd_err;
+ logic [BusFullWidth-1:0] rd_data;
+ logic init_busy;
+ logic macro_err;
+ logic [NumBanks-1:0] ecc_single_err;
+ logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr;
+ jtag_pkg::jtag_rsp_t jtag_rsp;
+ logic prog_intg_err;
+ logic storage_relbl_err;
+ logic storage_intg_err;
+ logic fsm_err;
+ logic spurious_ack;
+ logic arb_err;
+ logic host_gnt_err;
+ logic fifo_err;
+ } flash_rsp_t;
+
+ // default value of flash_rsp_t (for dangling ports)
+ parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
+ prog_type_avail: {ProgTypes{1'b1}},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ macro_err: 1'b0,
+ ecc_single_err: '0,
+ ecc_addr: '0,
+ jtag_rsp: '0,
+ prog_intg_err: '0,
+ storage_relbl_err: '0,
+ storage_intg_err: '0,
+ fsm_err: '0,
+ spurious_ack: '0,
+ arb_err: '0,
+ host_gnt_err: '0,
+ fifo_err: '0
+ };
+
+ // RMA entries
+ typedef struct packed {
+ logic [BankW-1:0] bank;
+ flash_part_e part;
+ logic [InfoTypesWidth-1:0] info_sel;
+ logic [PageW:0] start_page;
+ logic [PageW:0] num_pages;
+ } rma_wipe_entry_t;
+
+ // entries to be wiped
+ parameter int WipeEntries = 5;
+ parameter rma_wipe_entry_t RmaWipeEntries[WipeEntries] = '{
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, CreatorInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, OwnerInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: SeedBank,
+ part: FlashPartInfo,
+ info_sel: SeedInfoSel,
+ start_page: {1'b0, IsolatedInfoPage},
+ num_pages: 1
+ },
+
+ '{
+ bank: 0,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ },
+
+ '{
+ bank: 1,
+ part: FlashPartData,
+ info_sel: 0,
+ start_page: 0,
+ num_pages: (PageW + 1)'(PagesPerBank)
+ }
+ };
+
+
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
+ parameter keymgr_flash_t KEYMGR_FLASH_DEFAULT = '{
+ seeds: '{
+ 256'h9152e32c9380a4bcc3e0ab263581e6b0e8825186e1e445631646e8bef8c45d47,
+ 256'hfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
+ }
+ };
+
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashBistSel,
+ FlashLcDftLast
+ } flash_lc_jtag_e;
+
+ // Error bit positioning
+ typedef struct packed {
+ logic invalid_op_err;
+ logic oob_err;
+ logic mp_err;
+ logic rd_err;
+ logic prog_err;
+ logic prog_win_err;
+ logic prog_type_err;
+ } flash_ctrl_err_t;
+
+ // interrupt bit positioning
+ typedef enum logic[2:0] {
+ ProgEmpty,
+ ProgLvl,
+ RdFull,
+ RdLvl,
+ OpDone,
+ CorrErr,
+ LastIntrIdx
+ } flash_ctrl_intr_e;
+
+ // find the max number pages among info types
+ function automatic integer max_info_pages(int infos[InfoTypes]);
+ int current_max = 0;
+ for (int i = 0; i < InfoTypes; i++) begin
+ if (infos[i] > current_max) begin
+ current_max = infos[i];
+ end
+ end
+ return current_max;
+ endfunction // max_info_banks
+
+ // RMA control FSM encoding
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 // -s 3319803877 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (47.62%)
+ // 6: |||||||||||||||| (38.10%)
+ // 7: |||| (9.52%)
+ // 8: || (4.76%)
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 8
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 6
+ //
+ localparam int RmaStateWidth = 11;
+ typedef enum logic [RmaStateWidth-1:0] {
+ StRmaIdle = 11'b11110001010,
+ StRmaPageSel = 11'b10111100111,
+ StRmaErase = 11'b11000010111,
+ StRmaEraseWait = 11'b01010100110,
+ StRmaWordSel = 11'b00010011001,
+ StRmaProgram = 11'b11011111101,
+ StRmaProgramWait = 11'b00111110000,
+ StRmaRdVerify = 11'b00101001100,
+ StRmaDisabled = 11'b01001011010,
+ StRmaInvalid = 11'b10100111011
+ } rma_state_e;
+
+
+ // find the max number pages among info types
+ function automatic info_page_cfg_t info_cfg_qual(info_page_cfg_t in_cfg,
+ info_page_cfg_t qual_cfg);
+
+ info_page_cfg_t out_cfg;
+ out_cfg = '{
+ en: prim_mubi_pkg::mubi4_and_hi(in_cfg.en, qual_cfg.en),
+ rd_en: prim_mubi_pkg::mubi4_and_hi(in_cfg.rd_en, qual_cfg.rd_en),
+ prog_en: prim_mubi_pkg::mubi4_and_hi(in_cfg.prog_en, qual_cfg.prog_en),
+ erase_en: prim_mubi_pkg::mubi4_and_hi(in_cfg.erase_en, qual_cfg.erase_en),
+ scramble_en: prim_mubi_pkg::mubi4_and_hi(in_cfg.scramble_en, qual_cfg.scramble_en),
+ ecc_en: prim_mubi_pkg::mubi4_and_hi(in_cfg.ecc_en, qual_cfg.ecc_en),
+ he_en : prim_mubi_pkg::mubi4_and_hi(in_cfg.he_en, qual_cfg.he_en)
+ };
+
+ return out_cfg;
+ endfunction // max_info_banks
+
+endpackage : flash_ctrl_pkg
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv
new file mode 100644
index 0000000..87715af
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_prim_reg_top.sv
@@ -0,0 +1,2331 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module flash_ctrl_prim_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw, // Write
+ input flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import flash_ctrl_reg_pkg::* ;
+
+ localparam int AW = 7;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [20:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(21)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic csr0_regwen_we;
+ logic csr0_regwen_qs;
+ logic csr0_regwen_wd;
+ logic csr1_we;
+ logic [7:0] csr1_field0_qs;
+ logic [7:0] csr1_field0_wd;
+ logic [4:0] csr1_field1_qs;
+ logic [4:0] csr1_field1_wd;
+ logic csr2_we;
+ logic csr2_field0_qs;
+ logic csr2_field0_wd;
+ logic csr2_field1_qs;
+ logic csr2_field1_wd;
+ logic csr2_field2_qs;
+ logic csr2_field2_wd;
+ logic csr2_field3_qs;
+ logic csr2_field3_wd;
+ logic csr2_field4_qs;
+ logic csr2_field4_wd;
+ logic csr2_field5_qs;
+ logic csr2_field5_wd;
+ logic csr2_field6_qs;
+ logic csr2_field6_wd;
+ logic csr2_field7_qs;
+ logic csr2_field7_wd;
+ logic csr3_we;
+ logic [3:0] csr3_field0_qs;
+ logic [3:0] csr3_field0_wd;
+ logic [3:0] csr3_field1_qs;
+ logic [3:0] csr3_field1_wd;
+ logic [2:0] csr3_field2_qs;
+ logic [2:0] csr3_field2_wd;
+ logic [2:0] csr3_field3_qs;
+ logic [2:0] csr3_field3_wd;
+ logic [2:0] csr3_field4_qs;
+ logic [2:0] csr3_field4_wd;
+ logic [2:0] csr3_field5_qs;
+ logic [2:0] csr3_field5_wd;
+ logic csr3_field6_qs;
+ logic csr3_field6_wd;
+ logic [2:0] csr3_field7_qs;
+ logic [2:0] csr3_field7_wd;
+ logic [1:0] csr3_field8_qs;
+ logic [1:0] csr3_field8_wd;
+ logic [1:0] csr3_field9_qs;
+ logic [1:0] csr3_field9_wd;
+ logic csr4_we;
+ logic [2:0] csr4_field0_qs;
+ logic [2:0] csr4_field0_wd;
+ logic [2:0] csr4_field1_qs;
+ logic [2:0] csr4_field1_wd;
+ logic [2:0] csr4_field2_qs;
+ logic [2:0] csr4_field2_wd;
+ logic [2:0] csr4_field3_qs;
+ logic [2:0] csr4_field3_wd;
+ logic csr5_we;
+ logic [2:0] csr5_field0_qs;
+ logic [2:0] csr5_field0_wd;
+ logic [1:0] csr5_field1_qs;
+ logic [1:0] csr5_field1_wd;
+ logic [8:0] csr5_field2_qs;
+ logic [8:0] csr5_field2_wd;
+ logic [4:0] csr5_field3_qs;
+ logic [4:0] csr5_field3_wd;
+ logic [3:0] csr5_field4_qs;
+ logic [3:0] csr5_field4_wd;
+ logic csr6_we;
+ logic [2:0] csr6_field0_qs;
+ logic [2:0] csr6_field0_wd;
+ logic [2:0] csr6_field1_qs;
+ logic [2:0] csr6_field1_wd;
+ logic [7:0] csr6_field2_qs;
+ logic [7:0] csr6_field2_wd;
+ logic [2:0] csr6_field3_qs;
+ logic [2:0] csr6_field3_wd;
+ logic [1:0] csr6_field4_qs;
+ logic [1:0] csr6_field4_wd;
+ logic [1:0] csr6_field5_qs;
+ logic [1:0] csr6_field5_wd;
+ logic [1:0] csr6_field6_qs;
+ logic [1:0] csr6_field6_wd;
+ logic csr6_field7_qs;
+ logic csr6_field7_wd;
+ logic csr6_field8_qs;
+ logic csr6_field8_wd;
+ logic csr7_we;
+ logic [7:0] csr7_field0_qs;
+ logic [7:0] csr7_field0_wd;
+ logic [8:0] csr7_field1_qs;
+ logic [8:0] csr7_field1_wd;
+ logic csr8_we;
+ logic [31:0] csr8_qs;
+ logic [31:0] csr8_wd;
+ logic csr9_we;
+ logic [31:0] csr9_qs;
+ logic [31:0] csr9_wd;
+ logic csr10_we;
+ logic [31:0] csr10_qs;
+ logic [31:0] csr10_wd;
+ logic csr11_we;
+ logic [31:0] csr11_qs;
+ logic [31:0] csr11_wd;
+ logic csr12_we;
+ logic [9:0] csr12_qs;
+ logic [9:0] csr12_wd;
+ logic csr13_we;
+ logic [19:0] csr13_field0_qs;
+ logic [19:0] csr13_field0_wd;
+ logic csr13_field1_qs;
+ logic csr13_field1_wd;
+ logic csr14_we;
+ logic [7:0] csr14_field0_qs;
+ logic [7:0] csr14_field0_wd;
+ logic csr14_field1_qs;
+ logic csr14_field1_wd;
+ logic csr15_we;
+ logic [7:0] csr15_field0_qs;
+ logic [7:0] csr15_field0_wd;
+ logic csr15_field1_qs;
+ logic csr15_field1_wd;
+ logic csr16_we;
+ logic [7:0] csr16_field0_qs;
+ logic [7:0] csr16_field0_wd;
+ logic csr16_field1_qs;
+ logic csr16_field1_wd;
+ logic csr17_we;
+ logic [7:0] csr17_field0_qs;
+ logic [7:0] csr17_field0_wd;
+ logic csr17_field1_qs;
+ logic csr17_field1_wd;
+ logic csr18_we;
+ logic csr18_qs;
+ logic csr18_wd;
+ logic csr19_we;
+ logic csr19_qs;
+ logic csr19_wd;
+ logic csr20_we;
+ logic csr20_field0_qs;
+ logic csr20_field0_wd;
+ logic csr20_field1_qs;
+ logic csr20_field1_wd;
+ logic csr20_field2_qs;
+
+ // Register instances
+ // R[csr0_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_csr0_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr0_regwen_we),
+ .wd (csr0_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr0_regwen_qs)
+ );
+
+
+ // R[csr1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr1_gated_we;
+ assign csr1_gated_we = csr1_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr1_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr1_gated_we),
+ .wd (csr1_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr1.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr1_field0_qs)
+ );
+
+ // F[field1]: 12:8
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (5'h0)
+ ) u_csr1_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr1_gated_we),
+ .wd (csr1_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr1.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr1_field1_qs)
+ );
+
+
+ // R[csr2]: V(False)
+ // F[field0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field0_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field0.de),
+ .d (hw2reg.csr2.field0.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field0_qs)
+ );
+
+ // F[field1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field1_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field1.de),
+ .d (hw2reg.csr2.field1.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field1_qs)
+ );
+
+ // F[field2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field2_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field2.de),
+ .d (hw2reg.csr2.field2.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field2_qs)
+ );
+
+ // F[field3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr2_field3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field3_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field3.de),
+ .d (hw2reg.csr2.field3.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field3_qs)
+ );
+
+ // F[field4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field4_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field4.de),
+ .d (hw2reg.csr2.field4.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field4_qs)
+ );
+
+ // F[field5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field5_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field5.de),
+ .d (hw2reg.csr2.field5.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field5_qs)
+ );
+
+ // F[field6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr2_field6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field6_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field6.de),
+ .d (hw2reg.csr2.field6.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field6_qs)
+ );
+
+ // F[field7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr2_field7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr2_we),
+ .wd (csr2_field7_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr2.field7.de),
+ .d (hw2reg.csr2.field7.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr2.field7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr2_field7_qs)
+ );
+
+
+ // R[csr3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr3_gated_we;
+ assign csr3_gated_we = csr3_we & csr0_regwen_qs;
+ // F[field0]: 3:0
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h0)
+ ) u_csr3_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field0_qs)
+ );
+
+ // F[field1]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h0)
+ ) u_csr3_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field1_qs)
+ );
+
+ // F[field2]: 10:8
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr3_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field2_qs)
+ );
+
+ // F[field3]: 13:11
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr3_field3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field3_qs)
+ );
+
+ // F[field4]: 16:14
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr3_field4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field4_qs)
+ );
+
+ // F[field5]: 19:17
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr3_field5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field5_qs)
+ );
+
+ // F[field6]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr3_field6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field6_qs)
+ );
+
+ // F[field7]: 23:21
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr3_field7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field7_qs)
+ );
+
+ // F[field8]: 25:24
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr3_field8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field8_qs)
+ );
+
+ // F[field9]: 27:26
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr3_field9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr3_gated_we),
+ .wd (csr3_field9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr3.field9.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr3_field9_qs)
+ );
+
+
+ // R[csr4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr4_gated_we;
+ assign csr4_gated_we = csr4_we & csr0_regwen_qs;
+ // F[field0]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr4_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr4_gated_we),
+ .wd (csr4_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr4.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr4_field0_qs)
+ );
+
+ // F[field1]: 5:3
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr4_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr4_gated_we),
+ .wd (csr4_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr4.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr4_field1_qs)
+ );
+
+ // F[field2]: 8:6
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr4_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr4_gated_we),
+ .wd (csr4_field2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr4.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr4_field2_qs)
+ );
+
+ // F[field3]: 11:9
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr4_field3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr4_gated_we),
+ .wd (csr4_field3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr4.field3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr4_field3_qs)
+ );
+
+
+ // R[csr5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr5_gated_we;
+ assign csr5_gated_we = csr5_we & csr0_regwen_qs;
+ // F[field0]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr5_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr5_gated_we),
+ .wd (csr5_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr5.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr5_field0_qs)
+ );
+
+ // F[field1]: 4:3
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr5_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr5_gated_we),
+ .wd (csr5_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr5.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr5_field1_qs)
+ );
+
+ // F[field2]: 13:5
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_csr5_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr5_gated_we),
+ .wd (csr5_field2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr5.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr5_field2_qs)
+ );
+
+ // F[field3]: 18:14
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (5'h0)
+ ) u_csr5_field3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr5_gated_we),
+ .wd (csr5_field3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr5.field3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr5_field3_qs)
+ );
+
+ // F[field4]: 22:19
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h0)
+ ) u_csr5_field4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr5_gated_we),
+ .wd (csr5_field4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr5.field4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr5_field4_qs)
+ );
+
+
+ // R[csr6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr6_gated_we;
+ assign csr6_gated_we = csr6_we & csr0_regwen_qs;
+ // F[field0]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr6_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field0_qs)
+ );
+
+ // F[field1]: 5:3
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr6_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field1_qs)
+ );
+
+ // F[field2]: 13:6
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr6_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field2_qs)
+ );
+
+ // F[field3]: 16:14
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_csr6_field3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field3_qs)
+ );
+
+ // F[field4]: 18:17
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr6_field4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field4_qs)
+ );
+
+ // F[field5]: 20:19
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr6_field5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field5_qs)
+ );
+
+ // F[field6]: 22:21
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_csr6_field6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field6_qs)
+ );
+
+ // F[field7]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr6_field7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field7_qs)
+ );
+
+ // F[field8]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr6_field8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr6_gated_we),
+ .wd (csr6_field8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr6.field8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr6_field8_qs)
+ );
+
+
+ // R[csr7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr7_gated_we;
+ assign csr7_gated_we = csr7_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr7_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr7_gated_we),
+ .wd (csr7_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr7.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr7_field0_qs)
+ );
+
+ // F[field1]: 16:8
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (9'h0)
+ ) u_csr7_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr7_gated_we),
+ .wd (csr7_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr7.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr7_field1_qs)
+ );
+
+
+ // R[csr8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr8_gated_we;
+ assign csr8_gated_we = csr8_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_csr8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr8_gated_we),
+ .wd (csr8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr8_qs)
+ );
+
+
+ // R[csr9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr9_gated_we;
+ assign csr9_gated_we = csr9_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_csr9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr9_gated_we),
+ .wd (csr9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr9.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr9_qs)
+ );
+
+
+ // R[csr10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr10_gated_we;
+ assign csr10_gated_we = csr10_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_csr10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr10_gated_we),
+ .wd (csr10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr10.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr10_qs)
+ );
+
+
+ // R[csr11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr11_gated_we;
+ assign csr11_gated_we = csr11_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_csr11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr11_gated_we),
+ .wd (csr11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr11.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr11_qs)
+ );
+
+
+ // R[csr12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr12_gated_we;
+ assign csr12_gated_we = csr12_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (10),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (10'h0)
+ ) u_csr12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr12_gated_we),
+ .wd (csr12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr12.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr12_qs)
+ );
+
+
+ // R[csr13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr13_gated_we;
+ assign csr13_gated_we = csr13_we & csr0_regwen_qs;
+ // F[field0]: 19:0
+ prim_subreg #(
+ .DW (20),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (20'h0)
+ ) u_csr13_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr13_gated_we),
+ .wd (csr13_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr13.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr13_field0_qs)
+ );
+
+ // F[field1]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr13_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr13_gated_we),
+ .wd (csr13_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr13.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr13_field1_qs)
+ );
+
+
+ // R[csr14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr14_gated_we;
+ assign csr14_gated_we = csr14_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr14_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr14_gated_we),
+ .wd (csr14_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr14.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr14_field0_qs)
+ );
+
+ // F[field1]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr14_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr14_gated_we),
+ .wd (csr14_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr14.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr14_field1_qs)
+ );
+
+
+ // R[csr15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr15_gated_we;
+ assign csr15_gated_we = csr15_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr15_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr15_gated_we),
+ .wd (csr15_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr15.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr15_field0_qs)
+ );
+
+ // F[field1]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr15_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr15_gated_we),
+ .wd (csr15_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr15.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr15_field1_qs)
+ );
+
+
+ // R[csr16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr16_gated_we;
+ assign csr16_gated_we = csr16_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr16_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr16_gated_we),
+ .wd (csr16_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr16.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr16_field0_qs)
+ );
+
+ // F[field1]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr16_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr16_gated_we),
+ .wd (csr16_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr16.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr16_field1_qs)
+ );
+
+
+ // R[csr17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr17_gated_we;
+ assign csr17_gated_we = csr17_we & csr0_regwen_qs;
+ // F[field0]: 7:0
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_csr17_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr17_gated_we),
+ .wd (csr17_field0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr17.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr17_field0_qs)
+ );
+
+ // F[field1]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr17_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr17_gated_we),
+ .wd (csr17_field1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr17.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr17_field1_qs)
+ );
+
+
+ // R[csr18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr18_gated_we;
+ assign csr18_gated_we = csr18_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr18_gated_we),
+ .wd (csr18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr18.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr18_qs)
+ );
+
+
+ // R[csr19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic csr19_gated_we;
+ assign csr19_gated_we = csr19_we & csr0_regwen_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_csr19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr19_gated_we),
+ .wd (csr19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr19.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr19_qs)
+ );
+
+
+ // R[csr20]: V(False)
+ // F[field0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr20_field0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr20_we),
+ .wd (csr20_field0_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr20.field0.de),
+ .d (hw2reg.csr20.field0.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr20.field0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr20_field0_qs)
+ );
+
+ // F[field1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_csr20_field1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (csr20_we),
+ .wd (csr20_field1_wd),
+
+ // from internal hardware
+ .de (hw2reg.csr20.field1.de),
+ .d (hw2reg.csr20.field1.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr20.field1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr20_field1_qs)
+ );
+
+ // F[field2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_csr20_field2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.csr20.field2.de),
+ .d (hw2reg.csr20.field2.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.csr20.field2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (csr20_field2_qs)
+ );
+
+
+
+ logic [20:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == FLASH_CTRL_CSR0_REGWEN_OFFSET);
+ addr_hit[ 1] = (reg_addr == FLASH_CTRL_CSR1_OFFSET);
+ addr_hit[ 2] = (reg_addr == FLASH_CTRL_CSR2_OFFSET);
+ addr_hit[ 3] = (reg_addr == FLASH_CTRL_CSR3_OFFSET);
+ addr_hit[ 4] = (reg_addr == FLASH_CTRL_CSR4_OFFSET);
+ addr_hit[ 5] = (reg_addr == FLASH_CTRL_CSR5_OFFSET);
+ addr_hit[ 6] = (reg_addr == FLASH_CTRL_CSR6_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_CSR7_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_CSR8_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_CSR9_OFFSET);
+ addr_hit[10] = (reg_addr == FLASH_CTRL_CSR10_OFFSET);
+ addr_hit[11] = (reg_addr == FLASH_CTRL_CSR11_OFFSET);
+ addr_hit[12] = (reg_addr == FLASH_CTRL_CSR12_OFFSET);
+ addr_hit[13] = (reg_addr == FLASH_CTRL_CSR13_OFFSET);
+ addr_hit[14] = (reg_addr == FLASH_CTRL_CSR14_OFFSET);
+ addr_hit[15] = (reg_addr == FLASH_CTRL_CSR15_OFFSET);
+ addr_hit[16] = (reg_addr == FLASH_CTRL_CSR16_OFFSET);
+ addr_hit[17] = (reg_addr == FLASH_CTRL_CSR17_OFFSET);
+ addr_hit[18] = (reg_addr == FLASH_CTRL_CSR18_OFFSET);
+ addr_hit[19] = (reg_addr == FLASH_CTRL_CSR19_OFFSET);
+ addr_hit[20] = (reg_addr == FLASH_CTRL_CSR20_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(FLASH_CTRL_PRIM_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(FLASH_CTRL_PRIM_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(FLASH_CTRL_PRIM_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(FLASH_CTRL_PRIM_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(FLASH_CTRL_PRIM_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(FLASH_CTRL_PRIM_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(FLASH_CTRL_PRIM_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(FLASH_CTRL_PRIM_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(FLASH_CTRL_PRIM_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(FLASH_CTRL_PRIM_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(FLASH_CTRL_PRIM_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(FLASH_CTRL_PRIM_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(FLASH_CTRL_PRIM_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(FLASH_CTRL_PRIM_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(FLASH_CTRL_PRIM_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(FLASH_CTRL_PRIM_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(FLASH_CTRL_PRIM_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(FLASH_CTRL_PRIM_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(FLASH_CTRL_PRIM_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(FLASH_CTRL_PRIM_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(FLASH_CTRL_PRIM_PERMIT[20] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign csr0_regwen_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign csr0_regwen_wd = reg_wdata[0];
+ assign csr1_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign csr1_field0_wd = reg_wdata[7:0];
+
+ assign csr1_field1_wd = reg_wdata[12:8];
+ assign csr2_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign csr2_field0_wd = reg_wdata[0];
+
+ assign csr2_field1_wd = reg_wdata[1];
+
+ assign csr2_field2_wd = reg_wdata[2];
+
+ assign csr2_field3_wd = reg_wdata[3];
+
+ assign csr2_field4_wd = reg_wdata[4];
+
+ assign csr2_field5_wd = reg_wdata[5];
+
+ assign csr2_field6_wd = reg_wdata[6];
+
+ assign csr2_field7_wd = reg_wdata[7];
+ assign csr3_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign csr3_field0_wd = reg_wdata[3:0];
+
+ assign csr3_field1_wd = reg_wdata[7:4];
+
+ assign csr3_field2_wd = reg_wdata[10:8];
+
+ assign csr3_field3_wd = reg_wdata[13:11];
+
+ assign csr3_field4_wd = reg_wdata[16:14];
+
+ assign csr3_field5_wd = reg_wdata[19:17];
+
+ assign csr3_field6_wd = reg_wdata[20];
+
+ assign csr3_field7_wd = reg_wdata[23:21];
+
+ assign csr3_field8_wd = reg_wdata[25:24];
+
+ assign csr3_field9_wd = reg_wdata[27:26];
+ assign csr4_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign csr4_field0_wd = reg_wdata[2:0];
+
+ assign csr4_field1_wd = reg_wdata[5:3];
+
+ assign csr4_field2_wd = reg_wdata[8:6];
+
+ assign csr4_field3_wd = reg_wdata[11:9];
+ assign csr5_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign csr5_field0_wd = reg_wdata[2:0];
+
+ assign csr5_field1_wd = reg_wdata[4:3];
+
+ assign csr5_field2_wd = reg_wdata[13:5];
+
+ assign csr5_field3_wd = reg_wdata[18:14];
+
+ assign csr5_field4_wd = reg_wdata[22:19];
+ assign csr6_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign csr6_field0_wd = reg_wdata[2:0];
+
+ assign csr6_field1_wd = reg_wdata[5:3];
+
+ assign csr6_field2_wd = reg_wdata[13:6];
+
+ assign csr6_field3_wd = reg_wdata[16:14];
+
+ assign csr6_field4_wd = reg_wdata[18:17];
+
+ assign csr6_field5_wd = reg_wdata[20:19];
+
+ assign csr6_field6_wd = reg_wdata[22:21];
+
+ assign csr6_field7_wd = reg_wdata[23];
+
+ assign csr6_field8_wd = reg_wdata[24];
+ assign csr7_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign csr7_field0_wd = reg_wdata[7:0];
+
+ assign csr7_field1_wd = reg_wdata[16:8];
+ assign csr8_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign csr8_wd = reg_wdata[31:0];
+ assign csr9_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign csr9_wd = reg_wdata[31:0];
+ assign csr10_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign csr10_wd = reg_wdata[31:0];
+ assign csr11_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign csr11_wd = reg_wdata[31:0];
+ assign csr12_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign csr12_wd = reg_wdata[9:0];
+ assign csr13_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign csr13_field0_wd = reg_wdata[19:0];
+
+ assign csr13_field1_wd = reg_wdata[20];
+ assign csr14_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign csr14_field0_wd = reg_wdata[7:0];
+
+ assign csr14_field1_wd = reg_wdata[8];
+ assign csr15_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign csr15_field0_wd = reg_wdata[7:0];
+
+ assign csr15_field1_wd = reg_wdata[8];
+ assign csr16_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign csr16_field0_wd = reg_wdata[7:0];
+
+ assign csr16_field1_wd = reg_wdata[8];
+ assign csr17_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign csr17_field0_wd = reg_wdata[7:0];
+
+ assign csr17_field1_wd = reg_wdata[8];
+ assign csr18_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign csr18_wd = reg_wdata[0];
+ assign csr19_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign csr19_wd = reg_wdata[0];
+ assign csr20_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign csr20_field0_wd = reg_wdata[0];
+
+ assign csr20_field1_wd = reg_wdata[1];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = csr0_regwen_we;
+ reg_we_check[1] = csr1_gated_we;
+ reg_we_check[2] = csr2_we;
+ reg_we_check[3] = csr3_gated_we;
+ reg_we_check[4] = csr4_gated_we;
+ reg_we_check[5] = csr5_gated_we;
+ reg_we_check[6] = csr6_gated_we;
+ reg_we_check[7] = csr7_gated_we;
+ reg_we_check[8] = csr8_gated_we;
+ reg_we_check[9] = csr9_gated_we;
+ reg_we_check[10] = csr10_gated_we;
+ reg_we_check[11] = csr11_gated_we;
+ reg_we_check[12] = csr12_gated_we;
+ reg_we_check[13] = csr13_gated_we;
+ reg_we_check[14] = csr14_gated_we;
+ reg_we_check[15] = csr15_gated_we;
+ reg_we_check[16] = csr16_gated_we;
+ reg_we_check[17] = csr17_gated_we;
+ reg_we_check[18] = csr18_gated_we;
+ reg_we_check[19] = csr19_gated_we;
+ reg_we_check[20] = csr20_we;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = csr0_regwen_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[7:0] = csr1_field0_qs;
+ reg_rdata_next[12:8] = csr1_field1_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = csr2_field0_qs;
+ reg_rdata_next[1] = csr2_field1_qs;
+ reg_rdata_next[2] = csr2_field2_qs;
+ reg_rdata_next[3] = csr2_field3_qs;
+ reg_rdata_next[4] = csr2_field4_qs;
+ reg_rdata_next[5] = csr2_field5_qs;
+ reg_rdata_next[6] = csr2_field6_qs;
+ reg_rdata_next[7] = csr2_field7_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[3:0] = csr3_field0_qs;
+ reg_rdata_next[7:4] = csr3_field1_qs;
+ reg_rdata_next[10:8] = csr3_field2_qs;
+ reg_rdata_next[13:11] = csr3_field3_qs;
+ reg_rdata_next[16:14] = csr3_field4_qs;
+ reg_rdata_next[19:17] = csr3_field5_qs;
+ reg_rdata_next[20] = csr3_field6_qs;
+ reg_rdata_next[23:21] = csr3_field7_qs;
+ reg_rdata_next[25:24] = csr3_field8_qs;
+ reg_rdata_next[27:26] = csr3_field9_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[2:0] = csr4_field0_qs;
+ reg_rdata_next[5:3] = csr4_field1_qs;
+ reg_rdata_next[8:6] = csr4_field2_qs;
+ reg_rdata_next[11:9] = csr4_field3_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[2:0] = csr5_field0_qs;
+ reg_rdata_next[4:3] = csr5_field1_qs;
+ reg_rdata_next[13:5] = csr5_field2_qs;
+ reg_rdata_next[18:14] = csr5_field3_qs;
+ reg_rdata_next[22:19] = csr5_field4_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[2:0] = csr6_field0_qs;
+ reg_rdata_next[5:3] = csr6_field1_qs;
+ reg_rdata_next[13:6] = csr6_field2_qs;
+ reg_rdata_next[16:14] = csr6_field3_qs;
+ reg_rdata_next[18:17] = csr6_field4_qs;
+ reg_rdata_next[20:19] = csr6_field5_qs;
+ reg_rdata_next[22:21] = csr6_field6_qs;
+ reg_rdata_next[23] = csr6_field7_qs;
+ reg_rdata_next[24] = csr6_field8_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[7:0] = csr7_field0_qs;
+ reg_rdata_next[16:8] = csr7_field1_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[31:0] = csr8_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[31:0] = csr9_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = csr10_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[31:0] = csr11_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[9:0] = csr12_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[19:0] = csr13_field0_qs;
+ reg_rdata_next[20] = csr13_field1_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[7:0] = csr14_field0_qs;
+ reg_rdata_next[8] = csr14_field1_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[7:0] = csr15_field0_qs;
+ reg_rdata_next[8] = csr15_field1_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[7:0] = csr16_field0_qs;
+ reg_rdata_next[8] = csr16_field1_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[7:0] = csr17_field0_qs;
+ reg_rdata_next[8] = csr17_field1_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = csr18_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = csr19_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[0] = csr20_field0_qs;
+ reg_rdata_next[1] = csr20_field1_qs;
+ reg_rdata_next[2] = csr20_field2_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
new file mode 100644
index 0000000..a019aa3
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -0,0 +1,1538 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package flash_ctrl_reg_pkg;
+
+ // Param list
+ parameter int RegNumBanks = 2;
+ parameter int RegPagesPerBank = 256;
+ parameter int RegBusPgmResBytes = 64;
+ parameter int RegPageWidth = 8;
+ parameter int RegBankWidth = 1;
+ parameter int NumRegions = 8;
+ parameter int NumInfoTypes = 3;
+ parameter int NumInfos0 = 10;
+ parameter int NumInfos1 = 1;
+ parameter int NumInfos2 = 2;
+ parameter int WordsPerPage = 256;
+ parameter int BytesPerWord = 8;
+ parameter int BytesPerPage = 2048;
+ parameter int BytesPerBank = 524288;
+ parameter int unsigned ExecEn = 32'ha26a38f7;
+ parameter int MaxFifoDepth = 16;
+ parameter int MaxFifoWidth = 5;
+ parameter int NumAlerts = 5;
+
+ // Address widths within the block
+ parameter int CoreAw = 9;
+ parameter int PrimAw = 7;
+ parameter int MemAw = 1;
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for core interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } prog_empty;
+ struct packed {
+ logic q;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ } rd_full;
+ struct packed {
+ logic q;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ } op_done;
+ struct packed {
+ logic q;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } prog_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_full;
+ struct packed {
+ logic q;
+ logic qe;
+ } rd_lvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } op_done;
+ struct packed {
+ logic q;
+ logic qe;
+ } corr_err;
+ } flash_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_std_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_prim_flash_alert;
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_prim_flash_alert;
+ } flash_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } flash_ctrl_reg2hw_dis_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_exec_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_init_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } start;
+ struct packed {
+ logic [1:0] q;
+ } op;
+ struct packed {
+ logic q;
+ } prog_sel;
+ struct packed {
+ logic q;
+ } erase_sel;
+ struct packed {
+ logic q;
+ } partition_sel;
+ struct packed {
+ logic [1:0] q;
+ } info_sel;
+ struct packed {
+ logic [11:0] q;
+ } num;
+ } flash_ctrl_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic [19:0] q;
+ } flash_ctrl_reg2hw_addr_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } normal;
+ struct packed {
+ logic q;
+ } repair;
+ } flash_ctrl_reg2hw_prog_type_en_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_mp_region_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [8:0] q;
+ } base;
+ struct packed {
+ logic [9:0] q;
+ } size;
+ } flash_ctrl_reg2hw_mp_region_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_default_region_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } rd_en;
+ struct packed {
+ logic [3:0] q;
+ } prog_en;
+ struct packed {
+ logic [3:0] q;
+ } erase_en;
+ struct packed {
+ logic [3:0] q;
+ } scramble_en;
+ struct packed {
+ logic [3:0] q;
+ } ecc_en;
+ struct packed {
+ logic [3:0] q;
+ } he_en;
+ } flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } scramble_dis;
+ struct packed {
+ logic [3:0] q;
+ } ecc_dis;
+ } flash_ctrl_reg2hw_hw_info_cfg_override_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } prog_intg_err;
+ struct packed {
+ logic q;
+ } lcmgr_err;
+ struct packed {
+ logic q;
+ } lcmgr_intg_err;
+ struct packed {
+ logic q;
+ } arb_fsm_err;
+ struct packed {
+ logic q;
+ } storage_err;
+ struct packed {
+ logic q;
+ } phy_fsm_err;
+ struct packed {
+ logic q;
+ } ctrl_cnt_err;
+ struct packed {
+ logic q;
+ } fifo_err;
+ } flash_ctrl_reg2hw_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } op_err;
+ struct packed {
+ logic q;
+ } mp_err;
+ struct packed {
+ logic q;
+ } rd_err;
+ struct packed {
+ logic q;
+ } prog_err;
+ struct packed {
+ logic q;
+ } prog_win_err;
+ struct packed {
+ logic q;
+ } prog_type_err;
+ struct packed {
+ logic q;
+ } seed_err;
+ struct packed {
+ logic q;
+ } phy_relbl_err;
+ struct packed {
+ logic q;
+ } phy_storage_err;
+ struct packed {
+ logic q;
+ } spurious_ack;
+ struct packed {
+ logic q;
+ } arb_err;
+ struct packed {
+ logic q;
+ } host_gnt_err;
+ } flash_ctrl_reg2hw_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ } flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } alert_ack;
+ struct packed {
+ logic q;
+ } alert_trig;
+ } flash_ctrl_reg2hw_phy_alert_cfg_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_scratch_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] q;
+ } prog;
+ struct packed {
+ logic [4:0] q;
+ } rd;
+ } flash_ctrl_reg2hw_fifo_lvl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_fifo_rst_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_lvl;
+ struct packed {
+ logic d;
+ logic de;
+ } op_done;
+ struct packed {
+ logic d;
+ logic de;
+ } corr_err;
+ } flash_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } flash_ctrl_hw2reg_ctrl_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } start;
+ } flash_ctrl_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } done;
+ struct packed {
+ logic d;
+ logic de;
+ } err;
+ } flash_ctrl_hw2reg_op_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } rd_full;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_full;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } initialized;
+ } flash_ctrl_hw2reg_status_reg_t;
+
+ typedef struct packed {
+ logic [10:0] d;
+ } flash_ctrl_hw2reg_debug_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } op_err;
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } update_err;
+ struct packed {
+ logic d;
+ logic de;
+ } macro_err;
+ } flash_ctrl_hw2reg_err_code_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } lcmgr_err;
+ struct packed {
+ logic d;
+ logic de;
+ } lcmgr_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } arb_fsm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } storage_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_fsm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } ctrl_cnt_err;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_err;
+ } flash_ctrl_hw2reg_std_fault_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } op_err;
+ struct packed {
+ logic d;
+ logic de;
+ } mp_err;
+ struct packed {
+ logic d;
+ logic de;
+ } rd_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_win_err;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_type_err;
+ struct packed {
+ logic d;
+ logic de;
+ } seed_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_relbl_err;
+ struct packed {
+ logic d;
+ logic de;
+ } phy_storage_err;
+ struct packed {
+ logic d;
+ logic de;
+ } spurious_ack;
+ struct packed {
+ logic d;
+ logic de;
+ } arb_err;
+ struct packed {
+ logic d;
+ logic de;
+ } host_gnt_err;
+ } flash_ctrl_hw2reg_fault_status_reg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_err_addr_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t;
+
+ typedef struct packed {
+ logic [19:0] d;
+ logic de;
+ } flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } init_wip;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_normal_avail;
+ struct packed {
+ logic d;
+ logic de;
+ } prog_repair_avail;
+ } flash_ctrl_hw2reg_phy_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [4:0] d;
+ } prog;
+ struct packed {
+ logic [4:0] d;
+ } rd;
+ } flash_ctrl_hw2reg_curr_fifo_lvl_reg_t;
+
+ // Register -> HW type for core interface
+ typedef struct packed {
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [1333:1328]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [1327:1322]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [1321:1310]
+ flash_ctrl_reg2hw_alert_test_reg_t alert_test; // [1309:1300]
+ flash_ctrl_reg2hw_dis_reg_t dis; // [1299:1296]
+ flash_ctrl_reg2hw_exec_reg_t exec; // [1295:1264]
+ flash_ctrl_reg2hw_init_reg_t init; // [1263:1263]
+ flash_ctrl_reg2hw_control_reg_t control; // [1262:1243]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [1242:1223]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [1222:1221]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [1220:1220]
+ flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [1219:996]
+ flash_ctrl_reg2hw_mp_region_mreg_t [7:0] mp_region; // [995:844]
+ flash_ctrl_reg2hw_default_region_reg_t default_region; // [843:820]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [9:0] bank0_info0_page_cfg; // [819:540]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [0:0] bank0_info1_page_cfg; // [539:512]
+ flash_ctrl_reg2hw_bank0_info2_page_cfg_mreg_t [1:0] bank0_info2_page_cfg; // [511:456]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [9:0] bank1_info0_page_cfg; // [455:176]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [0:0] bank1_info1_page_cfg; // [175:148]
+ flash_ctrl_reg2hw_bank1_info2_page_cfg_mreg_t [1:0] bank1_info2_page_cfg; // [147:92]
+ flash_ctrl_reg2hw_hw_info_cfg_override_reg_t hw_info_cfg_override; // [91:84]
+ flash_ctrl_reg2hw_mp_bank_cfg_shadowed_mreg_t [1:0] mp_bank_cfg_shadowed; // [83:82]
+ flash_ctrl_reg2hw_std_fault_status_reg_t std_fault_status; // [81:73]
+ flash_ctrl_reg2hw_fault_status_reg_t fault_status; // [72:61]
+ flash_ctrl_reg2hw_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [60:45]
+ flash_ctrl_reg2hw_phy_alert_cfg_reg_t phy_alert_cfg; // [44:43]
+ flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
+ flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
+ flash_ctrl_reg2hw_fifo_rst_reg_t fifo_rst; // [0:0]
+ } flash_ctrl_core_reg2hw_t;
+
+ // HW -> register type for core interface
+ typedef struct packed {
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [198:187]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [186:186]
+ flash_ctrl_hw2reg_control_reg_t control; // [185:184]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [183:182]
+ flash_ctrl_hw2reg_op_status_reg_t op_status; // [181:178]
+ flash_ctrl_hw2reg_status_reg_t status; // [177:166]
+ flash_ctrl_hw2reg_debug_state_reg_t debug_state; // [165:155]
+ flash_ctrl_hw2reg_err_code_reg_t err_code; // [154:139]
+ flash_ctrl_hw2reg_std_fault_status_reg_t std_fault_status; // [138:121]
+ flash_ctrl_hw2reg_fault_status_reg_t fault_status; // [120:97]
+ flash_ctrl_hw2reg_err_addr_reg_t err_addr; // [96:76]
+ flash_ctrl_hw2reg_ecc_single_err_cnt_mreg_t [1:0] ecc_single_err_cnt; // [75:58]
+ flash_ctrl_hw2reg_ecc_single_err_addr_mreg_t [1:0] ecc_single_err_addr; // [57:16]
+ flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [15:10]
+ flash_ctrl_hw2reg_curr_fifo_lvl_reg_t curr_fifo_lvl; // [9:0]
+ } flash_ctrl_core_hw2reg_t;
+
+ // Register offsets for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_STATE_OFFSET = 9'h 0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 9'h 4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INTR_TEST_OFFSET = 9'h 8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ALERT_TEST_OFFSET = 9'h c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DIS_OFFSET = 9'h 10;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_EXEC_OFFSET = 9'h 14;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_INIT_OFFSET = 9'h 18;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 9'h 1c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 20;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ADDR_OFFSET = 9'h 24;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 28;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 2c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 30;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 34;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 38;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 3c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 40;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 44;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 48;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 4c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 50;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 54;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 58;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 5c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 60;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 64;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 68;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 6c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_0_OFFSET = 9'h 70;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_1_OFFSET = 9'h 74;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_2_OFFSET = 9'h 78;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_3_OFFSET = 9'h 7c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_4_OFFSET = 9'h 80;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_5_OFFSET = 9'h 84;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_6_OFFSET = 9'h 88;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_REGION_7_OFFSET = 9'h 8c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 90;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 94;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 98;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 9c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h a0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET = 9'h a4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET = 9'h a8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET = 9'h ac;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET = 9'h b0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET = 9'h b4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET = 9'h b8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h bc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h c0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h c4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h c8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET = 9'h cc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET = 9'h d0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET = 9'h d4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET = 9'h d8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET = 9'h dc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET = 9'h e0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET = 9'h e4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET = 9'h e8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET = 9'h ec;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET = 9'h f0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET = 9'h f4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET = 9'h f8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h fc;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h 100;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h 104;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h 108;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET = 9'h 10c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET = 9'h 110;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET = 9'h 114;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET = 9'h 118;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET = 9'h 11c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET = 9'h 120;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h 124;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h 128;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h 12c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h 130;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET = 9'h 134;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET = 9'h 138;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET = 9'h 13c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET = 9'h 140;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET = 9'h 144;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET = 9'h 148;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET = 9'h 14c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET = 9'h 150;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET = 9'h 154;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET = 9'h 158;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET = 9'h 15c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET = 9'h 160;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET = 9'h 164;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h 168;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET = 9'h 16c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h 170;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STATUS_OFFSET = 9'h 174;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_DEBUG_STATE_OFFSET = 9'h 178;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_CODE_OFFSET = 9'h 17c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_STD_FAULT_STATUS_OFFSET = 9'h 180;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FAULT_STATUS_OFFSET = 9'h 184;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ERR_ADDR_OFFSET = 9'h 188;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET = 9'h 18c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET = 9'h 190;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET = 9'h 194;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_ALERT_CFG_OFFSET = 9'h 198;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h 19c;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h 1a0;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h 1a4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 1a8;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_CURR_FIFO_LVL_OFFSET = 9'h 1ac;
+
+ // Reset values for hwext registers and their fields for core interface
+ parameter logic [5:0] FLASH_CTRL_INTR_TEST_RESVAL = 6'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_EMPTY_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_PROG_LVL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_FULL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_RD_LVL_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_OP_DONE_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_INTR_TEST_CORR_ERR_RESVAL = 1'h 0;
+ parameter logic [4:0] FLASH_CTRL_ALERT_TEST_RESVAL = 5'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_RESVAL = 1'h 0;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_RESVAL = 1'h 1;
+ parameter logic [0:0] FLASH_CTRL_CTRL_REGWEN_EN_RESVAL = 1'h 1;
+ parameter logic [10:0] FLASH_CTRL_DEBUG_STATE_RESVAL = 11'h 0;
+ parameter logic [12:0] FLASH_CTRL_CURR_FIFO_LVL_RESVAL = 13'h 0;
+ parameter logic [4:0] FLASH_CTRL_CURR_FIFO_LVL_PROG_RESVAL = 5'h 0;
+ parameter logic [4:0] FLASH_CTRL_CURR_FIFO_LVL_RD_RESVAL = 5'h 0;
+
+ // Window parameters for core interface
+ parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 1b0;
+ parameter int unsigned FLASH_CTRL_PROG_FIFO_SIZE = 'h 4;
+ parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 1b4;
+ parameter int unsigned FLASH_CTRL_RD_FIFO_SIZE = 'h 4;
+
+ // Register index for core interface
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_ALERT_TEST,
+ FLASH_CTRL_DIS,
+ FLASH_CTRL_EXEC,
+ FLASH_CTRL_INIT,
+ FLASH_CTRL_CTRL_REGWEN,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
+ FLASH_CTRL_REGION_CFG_REGWEN_0,
+ FLASH_CTRL_REGION_CFG_REGWEN_1,
+ FLASH_CTRL_REGION_CFG_REGWEN_2,
+ FLASH_CTRL_REGION_CFG_REGWEN_3,
+ FLASH_CTRL_REGION_CFG_REGWEN_4,
+ FLASH_CTRL_REGION_CFG_REGWEN_5,
+ FLASH_CTRL_REGION_CFG_REGWEN_6,
+ FLASH_CTRL_REGION_CFG_REGWEN_7,
+ FLASH_CTRL_MP_REGION_CFG_0,
+ FLASH_CTRL_MP_REGION_CFG_1,
+ FLASH_CTRL_MP_REGION_CFG_2,
+ FLASH_CTRL_MP_REGION_CFG_3,
+ FLASH_CTRL_MP_REGION_CFG_4,
+ FLASH_CTRL_MP_REGION_CFG_5,
+ FLASH_CTRL_MP_REGION_CFG_6,
+ FLASH_CTRL_MP_REGION_CFG_7,
+ FLASH_CTRL_MP_REGION_0,
+ FLASH_CTRL_MP_REGION_1,
+ FLASH_CTRL_MP_REGION_2,
+ FLASH_CTRL_MP_REGION_3,
+ FLASH_CTRL_MP_REGION_4,
+ FLASH_CTRL_MP_REGION_5,
+ FLASH_CTRL_MP_REGION_6,
+ FLASH_CTRL_MP_REGION_7,
+ FLASH_CTRL_DEFAULT_REGION,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK0_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8,
+ FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9,
+ FLASH_CTRL_BANK0_INFO1_REGWEN,
+ FLASH_CTRL_BANK0_INFO1_PAGE_CFG,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK0_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0,
+ FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_2,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_3,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_4,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_5,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_6,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_7,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_8,
+ FLASH_CTRL_BANK1_INFO0_REGWEN_9,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8,
+ FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9,
+ FLASH_CTRL_BANK1_INFO1_REGWEN,
+ FLASH_CTRL_BANK1_INFO1_PAGE_CFG,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_0,
+ FLASH_CTRL_BANK1_INFO2_REGWEN_1,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0,
+ FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1,
+ FLASH_CTRL_HW_INFO_CFG_OVERRIDE,
+ FLASH_CTRL_BANK_CFG_REGWEN,
+ FLASH_CTRL_MP_BANK_CFG_SHADOWED,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_DEBUG_STATE,
+ FLASH_CTRL_ERR_CODE,
+ FLASH_CTRL_STD_FAULT_STATUS,
+ FLASH_CTRL_FAULT_STATUS,
+ FLASH_CTRL_ERR_ADDR,
+ FLASH_CTRL_ECC_SINGLE_ERR_CNT,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0,
+ FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1,
+ FLASH_CTRL_PHY_ALERT_CFG,
+ FLASH_CTRL_PHY_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL,
+ FLASH_CTRL_FIFO_RST,
+ FLASH_CTRL_CURR_FIFO_LVL
+ } flash_ctrl_core_id_e;
+
+ // Register width information to check illegal writes for core interface
+ parameter logic [3:0] FLASH_CTRL_CORE_PERMIT [108] = '{
+ 4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b 0001, // index[ 3] FLASH_CTRL_ALERT_TEST
+ 4'b 0001, // index[ 4] FLASH_CTRL_DIS
+ 4'b 1111, // index[ 5] FLASH_CTRL_EXEC
+ 4'b 0001, // index[ 6] FLASH_CTRL_INIT
+ 4'b 0001, // index[ 7] FLASH_CTRL_CTRL_REGWEN
+ 4'b 1111, // index[ 8] FLASH_CTRL_CONTROL
+ 4'b 0111, // index[ 9] FLASH_CTRL_ADDR
+ 4'b 0001, // index[ 10] FLASH_CTRL_PROG_TYPE_EN
+ 4'b 0001, // index[ 11] FLASH_CTRL_ERASE_SUSPEND
+ 4'b 0001, // index[ 12] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b 0001, // index[ 13] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b 0001, // index[ 14] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b 0001, // index[ 15] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b 0001, // index[ 16] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b 0001, // index[ 17] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b 0001, // index[ 18] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b 0001, // index[ 19] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b 1111, // index[ 20] FLASH_CTRL_MP_REGION_CFG_0
+ 4'b 1111, // index[ 21] FLASH_CTRL_MP_REGION_CFG_1
+ 4'b 1111, // index[ 22] FLASH_CTRL_MP_REGION_CFG_2
+ 4'b 1111, // index[ 23] FLASH_CTRL_MP_REGION_CFG_3
+ 4'b 1111, // index[ 24] FLASH_CTRL_MP_REGION_CFG_4
+ 4'b 1111, // index[ 25] FLASH_CTRL_MP_REGION_CFG_5
+ 4'b 1111, // index[ 26] FLASH_CTRL_MP_REGION_CFG_6
+ 4'b 1111, // index[ 27] FLASH_CTRL_MP_REGION_CFG_7
+ 4'b 0111, // index[ 28] FLASH_CTRL_MP_REGION_0
+ 4'b 0111, // index[ 29] FLASH_CTRL_MP_REGION_1
+ 4'b 0111, // index[ 30] FLASH_CTRL_MP_REGION_2
+ 4'b 0111, // index[ 31] FLASH_CTRL_MP_REGION_3
+ 4'b 0111, // index[ 32] FLASH_CTRL_MP_REGION_4
+ 4'b 0111, // index[ 33] FLASH_CTRL_MP_REGION_5
+ 4'b 0111, // index[ 34] FLASH_CTRL_MP_REGION_6
+ 4'b 0111, // index[ 35] FLASH_CTRL_MP_REGION_7
+ 4'b 0111, // index[ 36] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[ 37] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b 0001, // index[ 38] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b 0001, // index[ 39] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b 0001, // index[ 40] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b 0001, // index[ 41] FLASH_CTRL_BANK0_INFO0_REGWEN_4
+ 4'b 0001, // index[ 42] FLASH_CTRL_BANK0_INFO0_REGWEN_5
+ 4'b 0001, // index[ 43] FLASH_CTRL_BANK0_INFO0_REGWEN_6
+ 4'b 0001, // index[ 44] FLASH_CTRL_BANK0_INFO0_REGWEN_7
+ 4'b 0001, // index[ 45] FLASH_CTRL_BANK0_INFO0_REGWEN_8
+ 4'b 0001, // index[ 46] FLASH_CTRL_BANK0_INFO0_REGWEN_9
+ 4'b 1111, // index[ 47] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
+ 4'b 1111, // index[ 48] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
+ 4'b 1111, // index[ 49] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
+ 4'b 1111, // index[ 50] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
+ 4'b 1111, // index[ 51] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4
+ 4'b 1111, // index[ 52] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5
+ 4'b 1111, // index[ 53] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6
+ 4'b 1111, // index[ 54] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7
+ 4'b 1111, // index[ 55] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8
+ 4'b 1111, // index[ 56] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9
+ 4'b 0001, // index[ 57] FLASH_CTRL_BANK0_INFO1_REGWEN
+ 4'b 1111, // index[ 58] FLASH_CTRL_BANK0_INFO1_PAGE_CFG
+ 4'b 0001, // index[ 59] FLASH_CTRL_BANK0_INFO2_REGWEN_0
+ 4'b 0001, // index[ 60] FLASH_CTRL_BANK0_INFO2_REGWEN_1
+ 4'b 1111, // index[ 61] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0
+ 4'b 1111, // index[ 62] FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1
+ 4'b 0001, // index[ 63] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b 0001, // index[ 64] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b 0001, // index[ 65] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b 0001, // index[ 66] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b 0001, // index[ 67] FLASH_CTRL_BANK1_INFO0_REGWEN_4
+ 4'b 0001, // index[ 68] FLASH_CTRL_BANK1_INFO0_REGWEN_5
+ 4'b 0001, // index[ 69] FLASH_CTRL_BANK1_INFO0_REGWEN_6
+ 4'b 0001, // index[ 70] FLASH_CTRL_BANK1_INFO0_REGWEN_7
+ 4'b 0001, // index[ 71] FLASH_CTRL_BANK1_INFO0_REGWEN_8
+ 4'b 0001, // index[ 72] FLASH_CTRL_BANK1_INFO0_REGWEN_9
+ 4'b 1111, // index[ 73] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
+ 4'b 1111, // index[ 74] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
+ 4'b 1111, // index[ 75] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
+ 4'b 1111, // index[ 76] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
+ 4'b 1111, // index[ 77] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4
+ 4'b 1111, // index[ 78] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5
+ 4'b 1111, // index[ 79] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6
+ 4'b 1111, // index[ 80] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7
+ 4'b 1111, // index[ 81] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8
+ 4'b 1111, // index[ 82] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9
+ 4'b 0001, // index[ 83] FLASH_CTRL_BANK1_INFO1_REGWEN
+ 4'b 1111, // index[ 84] FLASH_CTRL_BANK1_INFO1_PAGE_CFG
+ 4'b 0001, // index[ 85] FLASH_CTRL_BANK1_INFO2_REGWEN_0
+ 4'b 0001, // index[ 86] FLASH_CTRL_BANK1_INFO2_REGWEN_1
+ 4'b 1111, // index[ 87] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0
+ 4'b 1111, // index[ 88] FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1
+ 4'b 0001, // index[ 89] FLASH_CTRL_HW_INFO_CFG_OVERRIDE
+ 4'b 0001, // index[ 90] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[ 91] FLASH_CTRL_MP_BANK_CFG_SHADOWED
+ 4'b 0001, // index[ 92] FLASH_CTRL_OP_STATUS
+ 4'b 0001, // index[ 93] FLASH_CTRL_STATUS
+ 4'b 0011, // index[ 94] FLASH_CTRL_DEBUG_STATE
+ 4'b 0001, // index[ 95] FLASH_CTRL_ERR_CODE
+ 4'b 0011, // index[ 96] FLASH_CTRL_STD_FAULT_STATUS
+ 4'b 0011, // index[ 97] FLASH_CTRL_FAULT_STATUS
+ 4'b 0111, // index[ 98] FLASH_CTRL_ERR_ADDR
+ 4'b 0011, // index[ 99] FLASH_CTRL_ECC_SINGLE_ERR_CNT
+ 4'b 0111, // index[100] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0
+ 4'b 0111, // index[101] FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1
+ 4'b 0001, // index[102] FLASH_CTRL_PHY_ALERT_CFG
+ 4'b 0001, // index[103] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[104] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[105] FLASH_CTRL_FIFO_LVL
+ 4'b 0001, // index[106] FLASH_CTRL_FIFO_RST
+ 4'b 0011 // index[107] FLASH_CTRL_CURR_FIFO_LVL
+ };
+
+ ///////////////////////////////////////////////
+ // Typedefs for registers for prim interface //
+ ///////////////////////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic [4:0] q;
+ } field1;
+ } flash_ctrl_reg2hw_csr1_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ struct packed {
+ logic q;
+ } field2;
+ struct packed {
+ logic q;
+ } field3;
+ struct packed {
+ logic q;
+ } field4;
+ struct packed {
+ logic q;
+ } field5;
+ struct packed {
+ logic q;
+ } field6;
+ struct packed {
+ logic q;
+ } field7;
+ } flash_ctrl_reg2hw_csr2_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [3:0] q;
+ } field0;
+ struct packed {
+ logic [3:0] q;
+ } field1;
+ struct packed {
+ logic [2:0] q;
+ } field2;
+ struct packed {
+ logic [2:0] q;
+ } field3;
+ struct packed {
+ logic [2:0] q;
+ } field4;
+ struct packed {
+ logic [2:0] q;
+ } field5;
+ struct packed {
+ logic q;
+ } field6;
+ struct packed {
+ logic [2:0] q;
+ } field7;
+ struct packed {
+ logic [1:0] q;
+ } field8;
+ struct packed {
+ logic [1:0] q;
+ } field9;
+ } flash_ctrl_reg2hw_csr3_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [2:0] q;
+ } field0;
+ struct packed {
+ logic [2:0] q;
+ } field1;
+ struct packed {
+ logic [2:0] q;
+ } field2;
+ struct packed {
+ logic [2:0] q;
+ } field3;
+ } flash_ctrl_reg2hw_csr4_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [2:0] q;
+ } field0;
+ struct packed {
+ logic [1:0] q;
+ } field1;
+ struct packed {
+ logic [8:0] q;
+ } field2;
+ struct packed {
+ logic [4:0] q;
+ } field3;
+ struct packed {
+ logic [3:0] q;
+ } field4;
+ } flash_ctrl_reg2hw_csr5_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [2:0] q;
+ } field0;
+ struct packed {
+ logic [2:0] q;
+ } field1;
+ struct packed {
+ logic [7:0] q;
+ } field2;
+ struct packed {
+ logic [2:0] q;
+ } field3;
+ struct packed {
+ logic [1:0] q;
+ } field4;
+ struct packed {
+ logic [1:0] q;
+ } field5;
+ struct packed {
+ logic [1:0] q;
+ } field6;
+ struct packed {
+ logic q;
+ } field7;
+ struct packed {
+ logic q;
+ } field8;
+ } flash_ctrl_reg2hw_csr6_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic [8:0] q;
+ } field1;
+ } flash_ctrl_reg2hw_csr7_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_csr8_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_csr9_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_csr10_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } flash_ctrl_reg2hw_csr11_reg_t;
+
+ typedef struct packed {
+ logic [9:0] q;
+ } flash_ctrl_reg2hw_csr12_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [19:0] q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ } flash_ctrl_reg2hw_csr13_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ } flash_ctrl_reg2hw_csr14_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ } flash_ctrl_reg2hw_csr15_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ } flash_ctrl_reg2hw_csr16_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ } flash_ctrl_reg2hw_csr17_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_csr18_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_csr19_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } field0;
+ struct packed {
+ logic q;
+ } field1;
+ struct packed {
+ logic q;
+ } field2;
+ } flash_ctrl_reg2hw_csr20_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } field0;
+ struct packed {
+ logic d;
+ logic de;
+ } field1;
+ struct packed {
+ logic d;
+ logic de;
+ } field2;
+ struct packed {
+ logic d;
+ logic de;
+ } field3;
+ struct packed {
+ logic d;
+ logic de;
+ } field4;
+ struct packed {
+ logic d;
+ logic de;
+ } field5;
+ struct packed {
+ logic d;
+ logic de;
+ } field6;
+ struct packed {
+ logic d;
+ logic de;
+ } field7;
+ } flash_ctrl_hw2reg_csr2_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } field0;
+ struct packed {
+ logic d;
+ logic de;
+ } field1;
+ struct packed {
+ logic d;
+ logic de;
+ } field2;
+ } flash_ctrl_hw2reg_csr20_reg_t;
+
+ // Register -> HW type for prim interface
+ typedef struct packed {
+ flash_ctrl_reg2hw_csr1_reg_t csr1; // [325:313]
+ flash_ctrl_reg2hw_csr2_reg_t csr2; // [312:305]
+ flash_ctrl_reg2hw_csr3_reg_t csr3; // [304:277]
+ flash_ctrl_reg2hw_csr4_reg_t csr4; // [276:265]
+ flash_ctrl_reg2hw_csr5_reg_t csr5; // [264:242]
+ flash_ctrl_reg2hw_csr6_reg_t csr6; // [241:217]
+ flash_ctrl_reg2hw_csr7_reg_t csr7; // [216:200]
+ flash_ctrl_reg2hw_csr8_reg_t csr8; // [199:168]
+ flash_ctrl_reg2hw_csr9_reg_t csr9; // [167:136]
+ flash_ctrl_reg2hw_csr10_reg_t csr10; // [135:104]
+ flash_ctrl_reg2hw_csr11_reg_t csr11; // [103:72]
+ flash_ctrl_reg2hw_csr12_reg_t csr12; // [71:62]
+ flash_ctrl_reg2hw_csr13_reg_t csr13; // [61:41]
+ flash_ctrl_reg2hw_csr14_reg_t csr14; // [40:32]
+ flash_ctrl_reg2hw_csr15_reg_t csr15; // [31:23]
+ flash_ctrl_reg2hw_csr16_reg_t csr16; // [22:14]
+ flash_ctrl_reg2hw_csr17_reg_t csr17; // [13:5]
+ flash_ctrl_reg2hw_csr18_reg_t csr18; // [4:4]
+ flash_ctrl_reg2hw_csr19_reg_t csr19; // [3:3]
+ flash_ctrl_reg2hw_csr20_reg_t csr20; // [2:0]
+ } flash_ctrl_prim_reg2hw_t;
+
+ // HW -> register type for prim interface
+ typedef struct packed {
+ flash_ctrl_hw2reg_csr2_reg_t csr2; // [21:6]
+ flash_ctrl_hw2reg_csr20_reg_t csr20; // [5:0]
+ } flash_ctrl_prim_hw2reg_t;
+
+ // Register offsets for prim interface
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR0_REGWEN_OFFSET = 7'h 0;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR1_OFFSET = 7'h 4;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR2_OFFSET = 7'h 8;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR3_OFFSET = 7'h c;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR4_OFFSET = 7'h 10;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR5_OFFSET = 7'h 14;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR6_OFFSET = 7'h 18;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR7_OFFSET = 7'h 1c;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR8_OFFSET = 7'h 20;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR9_OFFSET = 7'h 24;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR10_OFFSET = 7'h 28;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR11_OFFSET = 7'h 2c;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR12_OFFSET = 7'h 30;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR13_OFFSET = 7'h 34;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR14_OFFSET = 7'h 38;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR15_OFFSET = 7'h 3c;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR16_OFFSET = 7'h 40;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR17_OFFSET = 7'h 44;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR18_OFFSET = 7'h 48;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR19_OFFSET = 7'h 4c;
+ parameter logic [PrimAw-1:0] FLASH_CTRL_CSR20_OFFSET = 7'h 50;
+
+ // Register index for prim interface
+ typedef enum int {
+ FLASH_CTRL_CSR0_REGWEN,
+ FLASH_CTRL_CSR1,
+ FLASH_CTRL_CSR2,
+ FLASH_CTRL_CSR3,
+ FLASH_CTRL_CSR4,
+ FLASH_CTRL_CSR5,
+ FLASH_CTRL_CSR6,
+ FLASH_CTRL_CSR7,
+ FLASH_CTRL_CSR8,
+ FLASH_CTRL_CSR9,
+ FLASH_CTRL_CSR10,
+ FLASH_CTRL_CSR11,
+ FLASH_CTRL_CSR12,
+ FLASH_CTRL_CSR13,
+ FLASH_CTRL_CSR14,
+ FLASH_CTRL_CSR15,
+ FLASH_CTRL_CSR16,
+ FLASH_CTRL_CSR17,
+ FLASH_CTRL_CSR18,
+ FLASH_CTRL_CSR19,
+ FLASH_CTRL_CSR20
+ } flash_ctrl_prim_id_e;
+
+ // Register width information to check illegal writes for prim interface
+ parameter logic [3:0] FLASH_CTRL_PRIM_PERMIT [21] = '{
+ 4'b 0001, // index[ 0] FLASH_CTRL_CSR0_REGWEN
+ 4'b 0011, // index[ 1] FLASH_CTRL_CSR1
+ 4'b 0001, // index[ 2] FLASH_CTRL_CSR2
+ 4'b 1111, // index[ 3] FLASH_CTRL_CSR3
+ 4'b 0011, // index[ 4] FLASH_CTRL_CSR4
+ 4'b 0111, // index[ 5] FLASH_CTRL_CSR5
+ 4'b 1111, // index[ 6] FLASH_CTRL_CSR6
+ 4'b 0111, // index[ 7] FLASH_CTRL_CSR7
+ 4'b 1111, // index[ 8] FLASH_CTRL_CSR8
+ 4'b 1111, // index[ 9] FLASH_CTRL_CSR9
+ 4'b 1111, // index[10] FLASH_CTRL_CSR10
+ 4'b 1111, // index[11] FLASH_CTRL_CSR11
+ 4'b 0011, // index[12] FLASH_CTRL_CSR12
+ 4'b 0111, // index[13] FLASH_CTRL_CSR13
+ 4'b 0011, // index[14] FLASH_CTRL_CSR14
+ 4'b 0011, // index[15] FLASH_CTRL_CSR15
+ 4'b 0011, // index[16] FLASH_CTRL_CSR16
+ 4'b 0011, // index[17] FLASH_CTRL_CSR17
+ 4'b 0001, // index[18] FLASH_CTRL_CSR18
+ 4'b 0001, // index[19] FLASH_CTRL_CSR19
+ 4'b 0001 // index[20] FLASH_CTRL_CSR20
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv
new file mode 100644
index 0000000..274241d
--- /dev/null
+++ b/hw/top_sencha/ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv
@@ -0,0 +1,187 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Flash control region configuration processing
+//
+// There are two main purpose of this module:
+// 1. strip the error conditions away from reg packages (see #8282)
+// 2. generate shadow update and storage errors
+
+module flash_ctrl_region_cfg
+ import flash_ctrl_pkg::*;
+ import flash_ctrl_reg_pkg::*;
+(
+ input clk_i,
+ input rst_ni,
+ input lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_rd_en_i,
+ input sw_bank_cfg_t [NumBanks-1:0] bank_cfg_i,
+ input sw_region_t [MpRegions-1:0] region_i,
+ input sw_region_cfg_t [MpRegions-1:0] region_cfg_i,
+ input sw_default_cfg_t default_cfg_i,
+ input sw_info_cfg_t [NumInfos0-1:0] bank0_info0_cfg_i,
+ input sw_info_cfg_t [NumInfos1-1:0] bank0_info1_cfg_i,
+ input sw_info_cfg_t [NumInfos2-1:0] bank0_info2_cfg_i,
+ input sw_info_cfg_t [NumInfos0-1:0] bank1_info0_cfg_i,
+ input sw_info_cfg_t [NumInfos1-1:0] bank1_info1_cfg_i,
+ input sw_info_cfg_t [NumInfos2-1:0] bank1_info2_cfg_i,
+
+ output bank_cfg_t [NumBanks-1:0] bank_cfg_o,
+ output mp_region_cfg_t [MpRegions:0] region_cfgs_o,
+ output info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs_o
+);
+
+ import prim_mubi_pkg::mubi4_t;
+
+ //////////////////////////////////////
+ // Life cycle synchronizer
+ //////////////////////////////////////
+
+ lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en;
+ lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en;
+ lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_rd_en;
+ lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en;
+
+ // synchronize enables into local domain
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_creator_seed_sw_rw_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_creator_seed_sw_rw_en_i),
+ .lc_en_o({lc_creator_seed_sw_rw_en})
+ );
+
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_owner_seed_sw_rw_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_owner_seed_sw_rw_en_i),
+ .lc_en_o({lc_owner_seed_sw_rw_en})
+ );
+
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_iso_part_sw_rd_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_iso_part_sw_rd_en_i),
+ .lc_en_o({lc_iso_part_sw_rd_en})
+ );
+
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_iso_part_sw_wr_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_iso_part_sw_wr_en_i),
+ .lc_en_o({lc_iso_part_sw_wr_en})
+ );
+
+ //////////////////////////////////////
+ // Bank speicfic configuration
+ //////////////////////////////////////
+ for (genvar i = 0; i < NumBanks; i++) begin : gen_bank_cfg
+ assign bank_cfg_o[i].q = bank_cfg_i[i].q;
+ end
+
+ //////////////////////////////////////
+ // Data partition regions
+ //////////////////////////////////////
+ // extra region is the default region
+ for (genvar i = 0; i < MpRegions; i++) begin : gen_mp_regions
+ assign region_cfgs_o[i].base = region_i[i].base.q;
+ assign region_cfgs_o[i].size = region_i[i].size.q;
+ assign region_cfgs_o[i].en = mubi4_t'(region_cfg_i[i].en.q);
+ assign region_cfgs_o[i].rd_en = mubi4_t'(region_cfg_i[i].rd_en.q);
+ assign region_cfgs_o[i].prog_en = mubi4_t'(region_cfg_i[i].prog_en.q);
+ assign region_cfgs_o[i].erase_en = mubi4_t'(region_cfg_i[i].erase_en.q);
+ assign region_cfgs_o[i].scramble_en = mubi4_t'(region_cfg_i[i].scramble_en.q);
+ assign region_cfgs_o[i].ecc_en = mubi4_t'(region_cfg_i[i].ecc_en.q);
+ assign region_cfgs_o[i].he_en = mubi4_t'(region_cfg_i[i].he_en.q);
+ end
+
+ //default region
+ assign region_cfgs_o[MpRegions].base = '0;
+ assign region_cfgs_o[MpRegions].size = NumBanks * PagesPerBank;
+ assign region_cfgs_o[MpRegions].en = prim_mubi_pkg::MuBi4True;
+ assign region_cfgs_o[MpRegions].rd_en = mubi4_t'(default_cfg_i.rd_en.q);
+ assign region_cfgs_o[MpRegions].prog_en = mubi4_t'(default_cfg_i.prog_en.q);
+ assign region_cfgs_o[MpRegions].erase_en = mubi4_t'(default_cfg_i.erase_en.q);
+ assign region_cfgs_o[MpRegions].scramble_en = mubi4_t'(default_cfg_i.scramble_en.q);
+ assign region_cfgs_o[MpRegions].ecc_en = mubi4_t'(default_cfg_i.ecc_en.q);
+ assign region_cfgs_o[MpRegions].he_en = mubi4_t'(default_cfg_i.he_en.q);
+
+ //////////////////////////////////////
+ // Info partition properties configuration
+ //////////////////////////////////////
+ sw_info_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] sw_info_cfgs;
+ info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_cfgs;
+ localparam int InfoBits = $bits(sw_info_cfg_t) * InfosPerBank;
+
+ // transform from unique names reg output to structure
+ // Not all types have the maximum number of banks, so those are packed to 0
+ assign sw_info_cfgs[0][0] = InfoBits'(bank0_info0_cfg_i);
+ assign sw_info_cfgs[0][1] = InfoBits'(bank0_info1_cfg_i);
+ assign sw_info_cfgs[0][2] = InfoBits'(bank0_info2_cfg_i);
+ assign sw_info_cfgs[1][0] = InfoBits'(bank1_info0_cfg_i);
+ assign sw_info_cfgs[1][1] = InfoBits'(bank1_info1_cfg_i);
+ assign sw_info_cfgs[1][2] = InfoBits'(bank1_info2_cfg_i);
+
+ // strip error indications
+ for (genvar i = 0; i < NumBanks; i++) begin : gen_info_cfg_bank
+ for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_cfg_type
+ for (genvar k = 0; k < InfosPerBank; k++) begin : gen_info_cfg_page
+ assign info_cfgs[i][j][k].en = mubi4_t'(sw_info_cfgs[i][j][k].en.q);
+ assign info_cfgs[i][j][k].rd_en = mubi4_t'(sw_info_cfgs[i][j][k].rd_en.q);
+ assign info_cfgs[i][j][k].prog_en = mubi4_t'(sw_info_cfgs[i][j][k].prog_en.q);
+ assign info_cfgs[i][j][k].erase_en = mubi4_t'(sw_info_cfgs[i][j][k].erase_en.q);
+ assign info_cfgs[i][j][k].scramble_en = mubi4_t'(sw_info_cfgs[i][j][k].scramble_en.q);
+ assign info_cfgs[i][j][k].ecc_en = mubi4_t'(sw_info_cfgs[i][j][k].ecc_en.q);
+ assign info_cfgs[i][j][k].he_en = mubi4_t'(sw_info_cfgs[i][j][k].he_en.q);
+ end
+ end
+ end
+
+ import lc_ctrl_pkg::lc_tx_test_true_strict;
+
+ // qualify software settings with creator / owner privileges
+ for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
+ for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
+ flash_ctrl_info_cfg # (
+ .Bank(i),
+ .InfoSel(j)
+ ) u_info_cfg (
+ .clk_i,
+ .rst_ni,
+ .cfgs_i(info_cfgs[i][j]),
+ .creator_seed_priv_i(lc_tx_test_true_strict(lc_creator_seed_sw_rw_en)),
+ .owner_seed_priv_i(lc_tx_test_true_strict(lc_owner_seed_sw_rw_en)),
+ .iso_flash_wr_en_i(lc_tx_test_true_strict(lc_iso_part_sw_wr_en)),
+ .iso_flash_rd_en_i(lc_tx_test_true_strict(lc_iso_part_sw_rd_en)),
+ .cfgs_o(info_page_cfgs_o[i][j])
+ );
+ end
+ end
+
+endmodule // flash_ctrl_reg_wrap
diff --git a/hw/top_sencha/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_sencha/ip/pinmux/data/autogen/pinmux.hjson
new file mode 100644
index 0000000..274c8f2
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/data/autogen/pinmux.hjson
@@ -0,0 +1,1095 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+ name: "pinmux",
+ human_name: "Pin Multiplexer",
+ one_line_desc: "Multiplexes between on-chip hardware blocks and pins, and can be configured at runtime",
+ one_paragraph_desc: '''
+ Pin Multiplexer connects on-chip hardware blocks to IC pins and controls the attributes of the pin drivers (such as pull-up/down, open-drain, and drive strength).
+ Large parts of its functionality can be controlled by software through registers.
+ Further features include per-pin programmable sleep behavior and wakeup pattern detectors as well as support for life-cycle-based JTAG (TAP) isolation and muxing.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_pinmux",
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D3",
+ verification_stage: "V2",
+ dif_stage: "S2",
+ notes: "Use FPV to perform block level verification.",
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_aon_i", reset: "rst_aon_ni"},
+ {reset: "rst_sys_ni"}
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ regwidth: "32",
+ scan: "true",
+
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+
+ wakeup_list: [
+ { name: "pin_wkup_req",
+ desc: "pin wake request"
+ },
+ { name: "usb_wkup_req",
+ desc: "usb wake request"
+ },
+ ],
+
+ inter_signal_list: [
+ // Life cycle inputs
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_hw_debug_en"
+ act: "rcv"
+ default: "lc_ctrl_pkg::Off"
+ package: "lc_ctrl_pkg",
+ desc: '''
+ Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
+ '''
+ }
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_dft_en"
+ act: "rcv"
+ default: "lc_ctrl_pkg::Off"
+ package: "lc_ctrl_pkg",
+ desc: '''
+ Test enable qualifier coming from life cycle controller, used for HW strap qualification.
+ '''
+ }
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_escalate_en"
+ act: "rcv"
+ default: "lc_ctrl_pkg::Off"
+ package: "lc_ctrl_pkg",
+ desc: '''
+ Escalation enable signal coming from life cycle controller, used for invalidating
+ the latched lc_hw_debug_en state inside the strap sampling logic.
+ ''',}
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "lc_check_byp_en"
+ act: "rcv"
+ default: "lc_ctrl_pkg::Off"
+ package: "lc_ctrl_pkg",
+ desc: '''
+ Check bypass enable signal coming from life cycle controller, used for invalidating
+ the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted
+ whenever the life cycle controller performs a life cycle transition. Its main use is
+ to skip any background checks inside the life cycle partition of the OTP controller while
+ a life cycle transition is in progress.
+ ''',}
+
+ { struct: "lc_tx"
+ type: "uni"
+ name: "pinmux_hw_debug_en"
+ act: "req"
+ default: "lc_ctrl_pkg::Off"
+ package: "lc_ctrl_pkg",
+ desc: '''
+ This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG
+ signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
+ ''',}
+
+ // JTAG TAPs
+ { struct: "jtag"
+ type: "req_rsp"
+ name: "lc_jtag"
+ act: "req"
+ package: "jtag_pkg"
+ desc: '''
+ Qualified JTAG signals for life cycle controller TAP.
+ ''',}
+
+ { struct: "jtag"
+ type: "req_rsp"
+ name: "rv_jtag"
+ act: "req"
+ package: "jtag_pkg"
+ desc: '''
+ Qualified JTAG signals for RISC-V processor TAP.
+ ''',}
+
+ { struct: "jtag"
+ type: "req_rsp"
+ name: "dft_jtag"
+ act: "req"
+ package: "jtag_pkg"
+ desc: '''
+ Qualified JTAG signals for DFT TAP.
+ ''',}
+
+ // Testmode signals to AST
+ { struct: "dft_strap_test_req",
+ type: "uni",
+ name: "dft_strap_test",
+ act: "req",
+ package: "pinmux_pkg",
+ desc: '''
+ Sampled DFT strap values, going to the DFT TAP.
+ ''',
+ default: "'0"
+ }
+ // DFT indication to stop tap strap sampling
+ { struct: "logic",
+ type: "uni",
+ name: "dft_hold_tap_sel",
+ act: "rcv",
+ package: "",
+ desc: '''
+ TAP selection hold indication, asserted by the DFT TAP during boundary scan.
+ ''',
+ default: "'0"
+ }
+ // Define pwr mgr <-> pinmux signals
+ { struct: "logic",
+ type: "uni",
+ name: "sleep_en",
+ act: "rcv",
+ package: "",
+ desc: '''
+ Level signal that is asserted when the power manager enters sleep.
+ ''',
+ default: "1'b0"
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "strap_en",
+ act: "rcv",
+ package: "",
+ desc: '''
+ This signal is pulsed high by the power manager after reset in order to sample the HW straps.
+ ''',
+ default: "1'b0"
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "pin_wkup_req",
+ act: "req",
+ package: "",
+ desc: '''
+ Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
+ ''',
+ default: "1'b0"
+ },
+ { name: "usbdev_dppullup_en",
+ type: "uni",
+ act: "rcv",
+ package: "",
+ desc: '''
+ Pullup enable signal coming from the USB IP.
+ ''',
+ struct: "logic",
+ width: "1"
+ },
+ { name: "usbdev_dnpullup_en",
+ type: "uni",
+ act: "rcv",
+ package: "",
+ desc: '''
+ Pullup enable signal coming from the USB IP.
+ ''',
+ struct: "logic",
+ width: "1"
+ },
+ { name: "usb_dppullup_en",
+ type: "uni",
+ act: "req",
+ package: "",
+ desc: '''
+ Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
+ ''',
+ struct: "logic",
+ width: "1"
+ default: "1'b0"
+ },
+ { name: "usb_dnpullup_en",
+ type: "uni",
+ act: "req",
+ package: "",
+ desc: '''
+ Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
+ ''',
+ struct: "logic",
+ width: "1"
+ default: "1'b0"
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "usb_wkup_req",
+ act: "req",
+ package: "",
+ desc: '''
+ Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
+ ''',
+ default: "1'b0"
+ },
+ { name: "usbdev_suspend_req",
+ type: "uni",
+ act: "rcv",
+ package: "",
+ desc: '''
+ Indicates whether USB is in suspended state, coming from the USB device.
+ ''',
+ struct: "logic",
+ width: "1"
+ },
+ { name: "usbdev_wake_ack",
+ type: "uni",
+ act: "rcv",
+ package: "",
+ desc: '''
+ Acknowledges the USB wakeup request, coming from the USB device.
+ ''',
+ struct: "logic",
+ width: "1"
+ },
+ { name: "usbdev_bus_reset",
+ type: "uni",
+ act: "req",
+ package: "",
+ desc: '''
+ Event signal that indicates what happened while monitoring.
+ ''',
+ struct: "logic",
+ width: "1",
+ default: "1'b0"
+ },
+ { name: "usbdev_sense_lost",
+ type: "uni",
+ act: "req",
+ package: "",
+ desc: '''
+ Event signal that indicates what happened while monitoring.
+ ''',
+ struct: "logic",
+ width: "1",
+ default: "1'b0"
+ },
+ { name: "usbdev_wake_detect_active",
+ type: "uni",
+ act: "req",
+ package: "",
+ desc: '''
+ State debug information.
+ ''',
+ struct: "logic",
+ width: 1,
+ default: "1'b0"
+ },
+ ]
+
+ param_list: [
+ { name: "AttrDw",
+ desc: "Pad attribute data width",
+ type: "int",
+ default: "13",
+ local: "true"
+ },
+ { name: "NMioPeriphIn",
+ desc: "Number of muxed peripheral inputs",
+ type: "int",
+ default: "76",
+ local: "true"
+ },
+ { name: "NMioPeriphOut",
+ desc: "Number of muxed peripheral outputs",
+ type: "int",
+ default: "89",
+ local: "true"
+ },
+ { name: "NMioPads",
+ desc: "Number of muxed IO pads",
+ type: "int",
+ default: "53",
+ local: "true"
+ },
+ { name: "NDioPads",
+ desc: "Number of dedicated IO pads",
+ type: "int",
+ default: "16",
+ local: "true"
+ },
+ { name: "NWkupDetect",
+ desc: "Number of wakeup detectors",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+ { name: "WkupCntWidth",
+ desc: "Number of wakeup counter bits",
+ type: "int",
+ default: "8",
+ local: "true"
+ },
+ // Since the target-specific top-levels often have slightly
+ // different debug signal positions, we need a way to pass
+ // this info from the target specific top-level into the pinmux
+ // logic. The parameter struct below serves this purpose.
+ { name: "TargetCfg",
+ desc: "Target specific pinmux configuration.",
+ type: "pinmux_pkg::target_cfg_t",
+ default: "pinmux_pkg::DefaultTargetCfg",
+ local: "false",
+ expose: "true"
+ },
+ ],
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ ]
+
+ registers: [
+//////////////////////////
+// MIO Inputs //
+//////////////////////////
+ { multireg: { name: "MIO_PERIPH_INSEL_REGWEN",
+ desc: "Register write enable for MIO peripheral input selects.",
+ count: "NMioPeriphIn",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "MIO_PERIPH_INSEL",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding MIO_PERIPH_INSEL
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_PERIPH_INSEL",
+ desc: "For each peripheral input, this selects the muxable pad input.",
+ count: "NMioPeriphIn",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "MIO_PERIPH_INSEL_REGWEN",
+ regwen_multi: "true",
+ cname: "IN",
+ fields: [
+ { bits: "5:0",
+ name: "IN",
+ desc: '''
+ 0: tie constantly to zero, 1: tie constantly to 1,
+ >=2: MIO pads (i.e., add 2 to the native MIO pad index).
+ '''
+ resval: 0,
+ }
+ ]
+ }
+ },
+
+//////////////////////////
+// MIO Outputs //
+//////////////////////////
+ { multireg: { name: "MIO_OUTSEL_REGWEN",
+ desc: "Register write enable for MIO output selects.",
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "MIO_OUTSEL",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding MIO_OUTSEL
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_OUTSEL",
+ desc: "For each muxable pad, this selects the peripheral output.",
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "MIO_OUTSEL_REGWEN",
+ regwen_multi: "true",
+ cname: "OUT",
+ fields: [
+ { bits: "6:0",
+ name: "OUT",
+ desc: '''
+ 0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z,
+ >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).
+ '''
+ resval: 2,
+ }
+ ]
+ // Random writes to this field may result in pad drive conflicts,
+ // which in turn leads to propagating Xes and assertion failures.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ }
+ },
+
+//////////////////////////
+// MIO PAD attributes //
+//////////////////////////
+ { multireg: { name: "MIO_PAD_ATTR_REGWEN",
+ desc: "Register write enable for MIO PAD attributes.",
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "MIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding !!MIO_PAD_ATTR
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_PAD_ATTR",
+ desc: '''
+ Muxed pad attributes.
+ This register has WARL behavior since not each pad type may support
+ all attributes.
+ ''',
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ regwen: "MIO_PAD_ATTR_REGWEN",
+ regwen_multi: "true",
+ cname: "MIO_PAD",
+ resval: 0
+ fields: [
+ { bits: "0",
+ name: "invert",
+ desc: "Invert input and output levels."
+ },
+ { bits: "1",
+ name: "virtual_od_en",
+ desc: "Enable virtual open drain."
+ },
+ { bits: "2",
+ name: "pull_en",
+ desc: "Enable pull-up or pull-down resistor."
+ },
+ { bits: "3",
+ name: "pull_select",
+ desc: "Pull select (0: pull-down, 1: pull-up)."
+ enum: [
+ { value: "0",
+ name: "pull_down",
+ desc: "Select the pull-down resistor."
+ },
+ { value: "1",
+ name: "pull_up",
+ desc: "Select the pull-up resistor."
+ }
+ ]
+ },
+ { bits: "4",
+ name: "keeper_en",
+ desc: "Enable pull-up or pull-down resistor."
+ },
+ { bits: "5",
+ name: "schmitt_en",
+ desc: "Enable the schmitt trigger."
+ },
+ { bits: "6",
+ name: "od_en",
+ desc: "Enable open drain."
+ },
+ { bits: "17:16",
+ name: "slew_rate",
+ desc: "Slew rate (0x0: slowest, 0x3: fastest)."
+ },
+ { bits: "23:20",
+ name: "drive_strength",
+ desc: "Drive strength (0x0: weakest, 0xf: strongest)"
+ }
+ ],
+ // these CSRs have WARL behavior and may not
+ // read back the same value that was written to them.
+ // further, they have hardware side effects since they drive the
+ // pad attributes, and hence no random data should be written to them.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ }
+ },
+
+//////////////////////////
+// DIO PAD attributes //
+//////////////////////////
+ { multireg: { name: "DIO_PAD_ATTR_REGWEN",
+ desc: "Register write enable for DIO PAD attributes.",
+ count: "NDioPads",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "DIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding !!DIO_PAD_ATTR
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "DIO_PAD_ATTR",
+ desc: '''
+ Dedicated pad attributes.
+ This register has WARL behavior since not each pad type may support
+ all attributes.
+ ''',
+ count: "NDioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ regwen: "DIO_PAD_ATTR_REGWEN",
+ regwen_multi: "true",
+ cname: "DIO_PAD",
+ resval: 0,
+ fields: [
+ { bits: "0",
+ name: "invert",
+ desc: "Invert input and output levels."
+ },
+ { bits: "1",
+ name: "virtual_od_en",
+ desc: "Enable virtual open drain."
+ },
+ { bits: "2",
+ name: "pull_en",
+ desc: "Enable pull-up or pull-down resistor."
+ },
+ { bits: "3",
+ name: "pull_select",
+ desc: "Pull select (0: pull-down, 1: pull-up)."
+ enum: [
+ { value: "0",
+ name: "pull_down",
+ desc: "Select the pull-down resistor."
+ },
+ { value: "1",
+ name: "pull_up",
+ desc: "Select the pull-up resistor."
+ }
+ ]
+ },
+ { bits: "4",
+ name: "keeper_en",
+ desc: "Enable pull-up or pull-down resistor."
+ },
+ { bits: "5",
+ name: "schmitt_en",
+ desc: "Enable the schmitt trigger."
+ },
+ { bits: "6",
+ name: "od_en",
+ desc: "Enable open drain."
+ },
+ { bits: "17:16",
+ name: "slew_rate",
+ desc: "Slew rate (0x0: slowest, 0x3: fastest)."
+ },
+ { bits: "23:20",
+ name: "drive_strength",
+ desc: "Drive strength (0x0: weakest, 0xf: strongest)"
+ }
+ ],
+ // these CSRs have WARL behavior and may not
+ // read back the same value that was written to them.
+ // further, they have hardware side effects since they drive the
+ // pad attributes, and hence no random data should be written to them.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ }
+ },
+
+//////////////////////////
+// MIO PAD sleep mode //
+//////////////////////////
+ { multireg: { name: "MIO_PAD_SLEEP_STATUS",
+ desc: "Register indicating whether the corresponding pad is in sleep mode.",
+ count: "NMioPads",
+ swaccess: "rw0c",
+ hwaccess: "hrw",
+ cname: "MIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ This register is set to 1 if the deep sleep mode of the corresponding
+ pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry.
+ The sleep mode of the corresponding pad will remain active until SW
+ clears this bit.
+ ''',
+ resval: "0",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_PAD_SLEEP_REGWEN",
+ desc: "Register write enable for MIO sleep value configuration.",
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "MIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding !!MIO_PAD_SLEEP_MODE
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_PAD_SLEEP_EN",
+ desc: '''Enables the sleep mode of the corresponding muxed pad.
+ '''
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "MIO_PAD_SLEEP_REGWEN",
+ regwen_multi: "true",
+ cname: "OUT",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: 0,
+ desc: '''
+ Deep sleep mode enable.
+ If this bit is set to 1 the corresponding pad will enable the sleep behavior
+ specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit
+ in !!MIO_PAD_SLEEP_STATUS will be set to 1.
+ The pad remains in deep sleep mode until the corresponding bit in
+ !!MIO_PAD_SLEEP_STATUS is cleared by SW.
+ Note that if an always on peripheral is connected to a specific MIO pad,
+ the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0.
+ '''
+ }
+ ]
+ }
+ },
+ { multireg: { name: "MIO_PAD_SLEEP_MODE",
+ desc: '''Defines sleep behavior of the corresponding muxed pad.
+ '''
+ count: "NMioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "MIO_PAD_SLEEP_REGWEN",
+ regwen_multi: "true",
+ cname: "OUT",
+ fields: [
+ { bits: "1:0",
+ name: "OUT",
+ resval: 2,
+ desc: "Value to drive in deep sleep."
+ enum: [
+ { value: "0",
+ name: "Tie-Low",
+ desc: "The pad is driven actively to zero in deep sleep mode."
+ },
+ { value: "1",
+ name: "Tie-High",
+ desc: "The pad is driven actively to one in deep sleep mode."
+ },
+ { value: "2",
+ name: "High-Z",
+ desc: '''
+ The pad is left undriven in deep sleep mode. Note that the actual
+ driving behavior during deep sleep will then depend on the pull-up/-down
+ configuration of in !!MIO_PAD_ATTR.
+ '''
+ },
+ { value: "3",
+ name: "Keep",
+ desc: "Keep last driven value (including high-Z)."
+ },
+ ]
+ }
+ ]
+ }
+ },
+//////////////////////////
+// DIO PAD sleep mode //
+//////////////////////////
+ { multireg: { name: "DIO_PAD_SLEEP_STATUS",
+ desc: "Register indicating whether the corresponding pad is in sleep mode.",
+ count: "NDioPads",
+ swaccess: "rw0c",
+ hwaccess: "hrw",
+ cname: "DIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ This register is set to 1 if the deep sleep mode of the corresponding
+ pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry.
+ The sleep mode of the corresponding pad will remain active until SW
+ clears this bit.
+ ''',
+ resval: "0",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "DIO_PAD_SLEEP_REGWEN",
+ desc: "Register write enable for DIO sleep value configuration.",
+ count: "NDioPads",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "DIO_PAD",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE
+ is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "DIO_PAD_SLEEP_EN",
+ desc: '''Enables the sleep mode of the corresponding dedicated pad.
+ '''
+ count: "NDioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "DIO_PAD_SLEEP_REGWEN",
+ regwen_multi: "true",
+ cname: "OUT",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ resval: 0,
+ desc: '''
+ Deep sleep mode enable.
+ If this bit is set to 1 the corresponding pad will enable the sleep behavior
+ specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit
+ in !!DIO_PAD_SLEEP_STATUS will be set to 1.
+ The pad remains in deep sleep mode until the corresponding bit in
+ !!DIO_PAD_SLEEP_STATUS is cleared by SW.
+ Note that if an always on peripheral is connected to a specific DIO pad,
+ the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0.
+ '''
+ }
+ ]
+ }
+ },
+ { multireg: { name: "DIO_PAD_SLEEP_MODE",
+ desc: '''Defines sleep behavior of the corresponding dedicated pad.
+ '''
+ count: "NDioPads",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "DIO_PAD_SLEEP_REGWEN",
+ regwen_multi: "true",
+ cname: "OUT",
+ fields: [
+ { bits: "1:0",
+ name: "OUT",
+ resval: 2,
+ desc: "Value to drive in deep sleep."
+ enum: [
+ { value: "0",
+ name: "Tie-Low",
+ desc: "The pad is driven actively to zero in deep sleep mode."
+ },
+ { value: "1",
+ name: "Tie-High",
+ desc: "The pad is driven actively to one in deep sleep mode."
+ },
+ { value: "2",
+ name: "High-Z",
+ desc: '''
+ The pad is left undriven in deep sleep mode. Note that the actual
+ driving behavior during deep sleep will then depend on the pull-up/-down
+ configuration of in !!DIO_PAD_ATTR.
+ '''
+ },
+ { value: "3",
+ name: "Keep",
+ desc: "Keep last driven value (including high-Z)."
+ },
+ ]
+ }
+ ]
+ }
+ },
+////////////////////////
+// Wakeup detectors //
+////////////////////////
+ { multireg: { name: "WKUP_DETECTOR_REGWEN",
+ desc: "Register write enable for wakeup detectors.",
+ count: "NWkupDetect",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "WKUP_DETECTOR",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Register write enable bit.
+ If this is cleared to 0, the corresponding WKUP_DETECTOR
+ configuration is not writable anymore.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "WKUP_DETECTOR_EN",
+ desc: '''
+ Enables for the wakeup detectors.
+ Note that these registers are synced to the always-on clock.
+ The first write access always completes immediately.
+ However, read/write accesses following a write will block until that write has completed.
+ '''
+ count: "NWkupDetect",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WKUP_DETECTOR_REGWEN",
+ regwen_multi: "true",
+ cname: "DETECTOR",
+ async: "clk_aon_i",
+ fields: [
+ { bits: "0:0",
+ name: "EN",
+ resval: 0,
+ desc: '''
+ Setting this bit activates the corresponding wakeup detector.
+ The behavior is as specified in !!WKUP_DETECTOR,
+ !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL.
+ '''
+ // In CSR tests, we do not touch the chip IOs. Thet are either pulled low or
+ // or undriven.
+ //
+ // Random writes to the wkup detect CSRs may result in the case where the
+ // wakeup gets enabled and signaled due to a pin being low for a programmed
+ // time, which results in wkup_cause register to mismatch, OR, result in
+ // assertion error due to a pin programmed for wakeup detection is undriven
+ // Also exclude write for csr_hw_reset, otherwise, X may be detected and propagating.
+ tags: ["excl:CsrAllTests:CsrExclWrite"]
+ }
+ ]
+ }
+
+ },
+ { multireg: { name: "WKUP_DETECTOR",
+ desc: '''
+ Configuration of wakeup condition detectors.
+ Note that these registers are synced to the always-on clock.
+ The first write access always completes immediately.
+ However, read/write accesses following a write will block until that write has completed.
+
+ Note that the wkup detector should be disabled by setting !!WKUP_DETECTOR_EN_0 before changing the detection mode.
+ The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled.
+ '''
+ count: "NWkupDetect",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WKUP_DETECTOR_REGWEN",
+ regwen_multi: "true",
+ cname: "DETECTOR",
+ async: "clk_aon_i",
+ fields: [
+ { bits: "2:0",
+ name: "MODE",
+ resval: 0,
+ desc: "Wakeup detection mode. Out of range values default to Posedge."
+ enum: [
+ { value: "0",
+ name: "Posedge",
+ desc: "Trigger a wakeup request when observing a positive edge."
+ },
+ { value: "1",
+ name: "Negedge",
+ desc: "Trigger a wakeup request when observing a negative edge."
+ },
+ { value: "2",
+ name: "Edge",
+ desc: "Trigger a wakeup request when observing an edge in any direction."
+ },
+ { value: "3",
+ name: "TimedHigh",
+ desc: '''
+ Trigger a wakeup request when pin is driven HIGH for a certain amount
+ of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
+ '''
+ },
+ { value: "4",
+ name: "TimedLow",
+ desc: '''
+ Trigger a wakeup request when pin is driven LOW for a certain amount
+ of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
+ '''
+ },
+
+ ]
+ }
+ { bits: "3",
+ name: "FILTER",
+ resval: 0,
+ desc: '''0: signal filter disabled, 1: signal filter enabled. the signal must
+ be stable for 4 always-on clock cycles before the value is being forwarded.
+ can be used for debouncing.
+ '''
+ }
+ { bits: "4",
+ name: "MIODIO",
+ resval: 0,
+ desc: '''0: select index !!WKUP_DETECTOR_PADSEL from MIO pads,
+ 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads.
+ '''
+ }
+ ]
+ }
+
+ },
+ { multireg: { name: "WKUP_DETECTOR_CNT_TH",
+ desc: '''
+ Counter thresholds for wakeup condition detectors.
+ Note that these registers are synced to the always-on clock.
+ The first write access always completes immediately.
+ However, read/write accesses following a write will block until that write has completed.
+ '''
+ count: "NWkupDetect",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WKUP_DETECTOR_REGWEN",
+ regwen_multi: "true",
+ cname: "DETECTOR",
+ async: "clk_aon_i",
+ fields: [
+ { bits: "WkupCntWidth-1:0",
+ name: "TH",
+ resval: 0,
+ desc: '''Counter threshold for TimedLow and TimedHigh wakeup detector modes (see !!WKUP_DETECTOR).
+ The threshold is in terms of always-on clock cycles.
+ '''
+ }
+ ]
+ }
+
+ },
+ { multireg: { name: "WKUP_DETECTOR_PADSEL",
+ desc: '''
+ Pad selects for pad wakeup condition detectors.
+ This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
+ '''
+ count: "NWkupDetect",
+ compact: "false",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WKUP_DETECTOR_REGWEN",
+ regwen_multi: "true",
+ cname: "DETECTOR",
+ fields: [
+ { bits: "5:0",
+ name: "SEL",
+ resval: 0,
+ desc: '''Selects a specific MIO or DIO pad (depending on !!WKUP_DETECTOR configuration).
+ In case of MIO, the pad select index is the same as used for !!MIO_PERIPH_INSEL, meaning that index
+ 0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads,
+ the pad select index corresponds 1:1 to the DIO pad to be selected.
+ '''
+ }
+ ]
+ }
+
+ },
+ { multireg: { name: "WKUP_CAUSE",
+ desc: '''
+ Cause registers for wakeup detectors.
+ Note that these registers are synced to the always-on clock.
+ The first write access always completes immediately.
+ However, read/write accesses following a write will block until that write has completed.
+ '''
+ count: "NWkupDetect",
+ swaccess: "rw0c",
+ hwaccess: "hrw",
+ cname: "DETECTOR",
+ async: "clk_aon_i",
+ fields: [
+ { bits: "0",
+ name: "CAUSE",
+ resval: 0,
+ desc: '''Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
+ '''
+ }
+ ]
+ }
+
+ },
+ ],
+}
diff --git a/hw/top_sencha/ip/pinmux/doc/autogen/pinout_asic.md b/hw/top_sencha/ip/pinmux/doc/autogen/pinout_asic.md
new file mode 100644
index 0000000..80ad018
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/doc/autogen/pinout_asic.md
@@ -0,0 +1,233 @@
+---
+title: ASIC Target Pinout and Pinmux Connectivity
+---
+<!--
+DO NOT EDIT THIS FILE DIRECTLY.
+It has been generated with the following command:
+util/topgen.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+-->
+
+## Pinout Table
+
+| <p style="font-size:smaller">Pad Name</p> | <p style="font-size:smaller">Type</p> | <p style="font-size:smaller">Bank</p> | <p style="font-size:smaller">Connection</p> | <p style="font-size:smaller">Special Function</p> | <p style="font-size:smaller">Pinmux Insel Constant / Muxed Output Index</p> | <p style="font-size:smaller">Description</p> |
+|:-------------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-----------------------------------------------------------------------------------------:|:----------------------------------------------------------------------------------------:|
+| <p style="font-size:smaller">POR_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">System reset</p> |
+| <p style="font-size:smaller">USB_P</p> | <p style="font-size:smaller">DualBidirTol</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">USB P signal</p> |
+| <p style="font-size:smaller">USB_N</p> | <p style="font-size:smaller">DualBidirTol</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">USB N signal</p> |
+| <p style="font-size:smaller">CC1</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">AVCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">ADC input 1</p> |
+| <p style="font-size:smaller">CC2</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">AVCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">ADC input 2</p> |
+| <p style="font-size:smaller">FLASH_TEST_VOLT</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Flash test voltage input</p> |
+| <p style="font-size:smaller">FLASH_TEST_MODE0</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Flash test mode signal</p> |
+| <p style="font-size:smaller">FLASH_TEST_MODE1</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Flash test mode signal</p> |
+| <p style="font-size:smaller">OTP_EXT_VOLT</p> | <p style="font-size:smaller">AnalogIn1</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">OTP external voltage input</p> |
+| <p style="font-size:smaller">SPI_HOST_D0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_CLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host clock</p> |
+| <p style="font-size:smaller">SPI_HOST_CS_L</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host chip select</p> |
+| <p style="font-size:smaller">SPI_DEV_D0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_CLK</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device clock</p> |
+| <p style="font-size:smaller">SPI_DEV_CS_L</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device chip select</p> |
+| <p style="font-size:smaller">IOA0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa0 / kTopSenchaPinmuxMioOutIoa0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa1 / kTopSenchaPinmuxMioOutIoa1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa2 / kTopSenchaPinmuxMioOutIoa2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa3 / kTopSenchaPinmuxMioOutIoa3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa4 / kTopSenchaPinmuxMioOutIoa4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa5 / kTopSenchaPinmuxMioOutIoa5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA6</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa6 / kTopSenchaPinmuxMioOutIoa6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA7</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa7 / kTopSenchaPinmuxMioOutIoa7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA8</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa8 / kTopSenchaPinmuxMioOutIoa8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob0 / kTopSenchaPinmuxMioOutIob0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob1 / kTopSenchaPinmuxMioOutIob1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob2 / kTopSenchaPinmuxMioOutIob2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob3 / kTopSenchaPinmuxMioOutIob3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob4 / kTopSenchaPinmuxMioOutIob4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob5 / kTopSenchaPinmuxMioOutIob5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob6 / kTopSenchaPinmuxMioOutIob6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob7 / kTopSenchaPinmuxMioOutIob7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob8 / kTopSenchaPinmuxMioOutIob8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB9</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob9 / kTopSenchaPinmuxMioOutIob9</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob10 / kTopSenchaPinmuxMioOutIob10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob11 / kTopSenchaPinmuxMioOutIob11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob12 / kTopSenchaPinmuxMioOutIob12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc0 / kTopSenchaPinmuxMioOutIoc0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc1 / kTopSenchaPinmuxMioOutIoc1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc2 / kTopSenchaPinmuxMioOutIoc2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft0</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc3 / kTopSenchaPinmuxMioOutIoc3</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft1</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc4 / kTopSenchaPinmuxMioOutIoc4</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap1</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc5 / kTopSenchaPinmuxMioOutIoc5</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
+| <p style="font-size:smaller">IOC6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc6 / kTopSenchaPinmuxMioOutIoc6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc7 / kTopSenchaPinmuxMioOutIoc7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap0</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc8 / kTopSenchaPinmuxMioOutIoc8</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
+| <p style="font-size:smaller">IOC9</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc9 / kTopSenchaPinmuxMioOutIoc9</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc10 / kTopSenchaPinmuxMioOutIoc10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc11 / kTopSenchaPinmuxMioOutIoc11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc12 / kTopSenchaPinmuxMioOutIoc12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tms</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor0 / kTopSenchaPinmuxMioOutIor0</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tms signal.</p> |
+| <p style="font-size:smaller">IOR1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tdo</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor1 / kTopSenchaPinmuxMioOutIor1</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tdo signal.</p> |
+| <p style="font-size:smaller">IOR2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tdi</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor2 / kTopSenchaPinmuxMioOutIor2</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tdi signal.</p> |
+| <p style="font-size:smaller">IOR3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tck</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor3 / kTopSenchaPinmuxMioOutIor3</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tck signal.</p> |
+| <p style="font-size:smaller">IOR4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">trst_n</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor4 / kTopSenchaPinmuxMioOutIor4</p> | <p style="font-size:smaller">Muxed IO pad / JTAG trst_n signal.</p> |
+| <p style="font-size:smaller">IOR5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor5 / kTopSenchaPinmuxMioOutIor5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor6 / kTopSenchaPinmuxMioOutIor6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor7 / kTopSenchaPinmuxMioOutIor7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR8</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Dedicated sysrst_ctrl output (ec_rst_l)</p> |
+| <p style="font-size:smaller">IOR9</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Dedicated sysrst_ctrl output (flash_wp_l)</p> |
+| <p style="font-size:smaller">IOR10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor10 / kTopSenchaPinmuxMioOutIor10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor11 / kTopSenchaPinmuxMioOutIor11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor12 / kTopSenchaPinmuxMioOutIor12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR13</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor13 / kTopSenchaPinmuxMioOutIor13</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod0 / kTopSenchaPinmuxMioOutIod0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod1 / kTopSenchaPinmuxMioOutIod1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod2 / kTopSenchaPinmuxMioOutIod2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod3 / kTopSenchaPinmuxMioOutIod3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod4 / kTopSenchaPinmuxMioOutIod4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod5 / kTopSenchaPinmuxMioOutIod5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">AST_MISC</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra infrastructure pad for AST</p> |
+| <p style="font-size:smaller">CLK_EXT</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Ext clock input</p> |
+| <p style="font-size:smaller">CLK_BYP</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Bypass internal clk from PLL, and use CLK_EXT for debug</p> |
+| <p style="font-size:smaller">CLK_200K</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> |
+| <p style="font-size:smaller">XTAL_IN</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">XTAL input</p> |
+| <p style="font-size:smaller">XTAL_OUT</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">XTAL output</p> |
+## Pinmux Connectivity
+
+| <p style="font-size:smaller">Module / Signal</p> | <p style="font-size:smaller">Connection</p> | <p style="font-size:smaller">Pad</p> | <p style="font-size:smaller">Pinmux Outsel Constant / Peripheral Input Index</p> | <p style="font-size:smaller">Description</p> |
+|:-------------------------------------------------------------:|:---------------------------------------------:|:----------------------------------------------:|:------------------------------------------------------------------------------------------------------------:|:----------------------------------------------:|
+| <p style="font-size:smaller">usbdev_usb_dp</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">usbdev_usb_dn</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[0]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D0</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[1]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D1</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[2]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D2</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[3]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D3</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[0]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D0</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[1]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D1</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[2]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D2</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[3]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D3</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio0 / kTopSenchaPinmuxPeripheralInGpioGpio0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio1 / kTopSenchaPinmuxPeripheralInGpioGpio1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio2 / kTopSenchaPinmuxPeripheralInGpioGpio2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio3 / kTopSenchaPinmuxPeripheralInGpioGpio3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio4 / kTopSenchaPinmuxPeripheralInGpioGpio4</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio5 / kTopSenchaPinmuxPeripheralInGpioGpio5</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio6 / kTopSenchaPinmuxPeripheralInGpioGpio6</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio7 / kTopSenchaPinmuxPeripheralInGpioGpio7</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[8]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio8 / kTopSenchaPinmuxPeripheralInGpioGpio8</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[9]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio9 / kTopSenchaPinmuxPeripheralInGpioGpio9</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[10]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio10 / kTopSenchaPinmuxPeripheralInGpioGpio10</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[11]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio11 / kTopSenchaPinmuxPeripheralInGpioGpio11</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[12]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio12 / kTopSenchaPinmuxPeripheralInGpioGpio12</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[13]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio13 / kTopSenchaPinmuxPeripheralInGpioGpio13</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[14]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio14 / kTopSenchaPinmuxPeripheralInGpioGpio14</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[15]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio15 / kTopSenchaPinmuxPeripheralInGpioGpio15</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[16]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio16 / kTopSenchaPinmuxPeripheralInGpioGpio16</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[17]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio17 / kTopSenchaPinmuxPeripheralInGpioGpio17</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[18]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio18 / kTopSenchaPinmuxPeripheralInGpioGpio18</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[19]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio19 / kTopSenchaPinmuxPeripheralInGpioGpio19</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[20]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio20 / kTopSenchaPinmuxPeripheralInGpioGpio20</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[21]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio21 / kTopSenchaPinmuxPeripheralInGpioGpio21</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[22]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio22 / kTopSenchaPinmuxPeripheralInGpioGpio22</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[23]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio23 / kTopSenchaPinmuxPeripheralInGpioGpio23</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[24]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio24 / kTopSenchaPinmuxPeripheralInGpioGpio24</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[25]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio25 / kTopSenchaPinmuxPeripheralInGpioGpio25</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[26]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio26 / kTopSenchaPinmuxPeripheralInGpioGpio26</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[27]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio27 / kTopSenchaPinmuxPeripheralInGpioGpio27</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[28]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio28 / kTopSenchaPinmuxPeripheralInGpioGpio28</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[29]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio29 / kTopSenchaPinmuxPeripheralInGpioGpio29</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[30]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio30 / kTopSenchaPinmuxPeripheralInGpioGpio30</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[31]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio31 / kTopSenchaPinmuxPeripheralInGpioGpio31</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c0_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c0Sda / kTopSenchaPinmuxPeripheralInI2c0Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c0_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c0Scl / kTopSenchaPinmuxPeripheralInI2c0Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c1_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c1Sda / kTopSenchaPinmuxPeripheralInI2c1Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c1_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c1Scl / kTopSenchaPinmuxPeripheralInI2c1Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c2_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c2Sda / kTopSenchaPinmuxPeripheralInI2c2Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c2_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c2Scl / kTopSenchaPinmuxPeripheralInI2c2Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_i2c_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamI2cSda / kTopSenchaPinmuxPeripheralInCamI2cSda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_i2c_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamI2cScl / kTopSenchaPinmuxPeripheralInCamI2cScl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd0 / kTopSenchaPinmuxPeripheralInSpiHost1Sd0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd1 / kTopSenchaPinmuxPeripheralInSpiHost1Sd1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd2 / kTopSenchaPinmuxPeripheralInSpiHost1Sd2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd3 / kTopSenchaPinmuxPeripheralInSpiHost1Sd3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd0 / kTopSenchaPinmuxPeripheralInSpiHost2Sd0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd1 / kTopSenchaPinmuxPeripheralInSpiHost2Sd1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd2 / kTopSenchaPinmuxPeripheralInSpiHost2Sd2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd3 / kTopSenchaPinmuxPeripheralInSpiHost2Sd3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_ec_rst_l</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">IOR8</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_flash_wp_l</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">IOR9</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart0_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart0Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart1_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart1Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart2_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart2Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">smc_uart_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSmcUartRx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_ctrl_cam_int</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInCamCtrlCamInt</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_pclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSPclk</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData4</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData5</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData6</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData7</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_hsync</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSHsync</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_vsync</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSVsync</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInI2s0RxSd</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_tpm_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSpiDeviceTpmCsb</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTck</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tms</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTms</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tdi</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTdi</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_ac_present</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonAcPresent</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key0_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey0In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key1_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey1In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key2_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey2In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonPwrbIn</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_lid_open</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonLidOpen</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">usbdev_sense</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUsbdevSense</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart2_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart2Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">smc_uart_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSmcUartTx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_ctrl_cam_trig</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamCtrlCamTrig / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0RxSclk / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0RxWs / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxSclk / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxWs / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxSd / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pda0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPda0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pcl0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPcl0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pda1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPda1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pcl1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPcl1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sck / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Csb / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sck / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Csb / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tdo</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselFlashCtrlTdo / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut1 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut2 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut3 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut4 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut5 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut6 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut7 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[8]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut8 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm1 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm2 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm3 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm4 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm5 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">otp_ctrl_test[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselOtpCtrlTest0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_bat_disable</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonBatDisable / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key0_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey0Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key2_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey2Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonPwrbOut / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_sencha/ip/pinmux/doc/autogen/pinout_nexus.md b/hw/top_sencha/ip/pinmux/doc/autogen/pinout_nexus.md
new file mode 100644
index 0000000..dd2e318
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/doc/autogen/pinout_nexus.md
@@ -0,0 +1,227 @@
+---
+title: NEXUS Target Pinout and Pinmux Connectivity
+---
+<!--
+DO NOT EDIT THIS FILE DIRECTLY.
+It has been generated with the following command:
+util/topgen.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+-->
+
+## Pinout Table
+
+| <p style="font-size:smaller">Pad Name</p> | <p style="font-size:smaller">Type</p> | <p style="font-size:smaller">Bank</p> | <p style="font-size:smaller">Connection</p> | <p style="font-size:smaller">Special Function</p> | <p style="font-size:smaller">Pinmux Insel Constant / Muxed Output Index</p> | <p style="font-size:smaller">Description</p> |
+|:----------------------------------------------:|:---------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-----------------------------------------------------------------------------------------:|:--------------------------------------------------------------------------:|
+| <p style="font-size:smaller">POR_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">System reset</p> |
+| <p style="font-size:smaller">USB_P</p> | <p style="font-size:smaller">DualBidirTol</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">USB P signal</p> |
+| <p style="font-size:smaller">USB_N</p> | <p style="font-size:smaller">DualBidirTol</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">USB N signal</p> |
+| <p style="font-size:smaller">SPI_HOST_D0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_D3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host data</p> |
+| <p style="font-size:smaller">SPI_HOST_CLK</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host clock</p> |
+| <p style="font-size:smaller">SPI_HOST_CS_L</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI host chip select</p> |
+| <p style="font-size:smaller">SPI_DEV_D0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_D3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device data</p> |
+| <p style="font-size:smaller">SPI_DEV_CLK</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device clock</p> |
+| <p style="font-size:smaller">SPI_DEV_CS_L</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">SPI device chip select</p> |
+| <p style="font-size:smaller">IOA0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa0 / kTopSenchaPinmuxMioOutIoa0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa1 / kTopSenchaPinmuxMioOutIoa1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa2 / kTopSenchaPinmuxMioOutIoa2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa3 / kTopSenchaPinmuxMioOutIoa3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa4 / kTopSenchaPinmuxMioOutIoa4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa5 / kTopSenchaPinmuxMioOutIoa5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA6</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa6 / kTopSenchaPinmuxMioOutIoa6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA7</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa7 / kTopSenchaPinmuxMioOutIoa7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOA8</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOA</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoa8 / kTopSenchaPinmuxMioOutIoa8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob0 / kTopSenchaPinmuxMioOutIob0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob1 / kTopSenchaPinmuxMioOutIob1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob2 / kTopSenchaPinmuxMioOutIob2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob3 / kTopSenchaPinmuxMioOutIob3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob4 / kTopSenchaPinmuxMioOutIob4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob5 / kTopSenchaPinmuxMioOutIob5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob6 / kTopSenchaPinmuxMioOutIob6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob7 / kTopSenchaPinmuxMioOutIob7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob8 / kTopSenchaPinmuxMioOutIob8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB9</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob9 / kTopSenchaPinmuxMioOutIob9</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob10 / kTopSenchaPinmuxMioOutIob10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob11 / kTopSenchaPinmuxMioOutIob11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOB12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIob12 / kTopSenchaPinmuxMioOutIob12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc0 / kTopSenchaPinmuxMioOutIoc0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc1 / kTopSenchaPinmuxMioOutIoc1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc2 / kTopSenchaPinmuxMioOutIoc2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft0</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc3 / kTopSenchaPinmuxMioOutIoc3</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft1</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc4 / kTopSenchaPinmuxMioOutIoc4</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap1</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc5 / kTopSenchaPinmuxMioOutIoc5</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
+| <p style="font-size:smaller">IOC6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc6 / kTopSenchaPinmuxMioOutIoc6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc7 / kTopSenchaPinmuxMioOutIoc7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap0</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc8 / kTopSenchaPinmuxMioOutIoc8</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
+| <p style="font-size:smaller">IOC9</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc9 / kTopSenchaPinmuxMioOutIoc9</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc10 / kTopSenchaPinmuxMioOutIoc10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc11 / kTopSenchaPinmuxMioOutIoc11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIoc12 / kTopSenchaPinmuxMioOutIoc12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tms</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor0 / kTopSenchaPinmuxMioOutIor0</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tms signal.</p> |
+| <p style="font-size:smaller">IOR1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tdo</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor1 / kTopSenchaPinmuxMioOutIor1</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tdo signal.</p> |
+| <p style="font-size:smaller">IOR2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tdi</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor2 / kTopSenchaPinmuxMioOutIor2</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tdi signal.</p> |
+| <p style="font-size:smaller">IOR3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tck</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor3 / kTopSenchaPinmuxMioOutIor3</p> | <p style="font-size:smaller">Muxed IO pad / JTAG tck signal.</p> |
+| <p style="font-size:smaller">IOR4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">trst_n</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor4 / kTopSenchaPinmuxMioOutIor4</p> | <p style="font-size:smaller">Muxed IO pad / JTAG trst_n signal.</p> |
+| <p style="font-size:smaller">IOR5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor5 / kTopSenchaPinmuxMioOutIor5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor6 / kTopSenchaPinmuxMioOutIor6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor7 / kTopSenchaPinmuxMioOutIor7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR8</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Dedicated sysrst_ctrl output (ec_rst_l)</p> |
+| <p style="font-size:smaller">IOR9</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Dedicated sysrst_ctrl output (flash_wp_l)</p> |
+| <p style="font-size:smaller">IOR10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor10 / kTopSenchaPinmuxMioOutIor10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor11 / kTopSenchaPinmuxMioOutIor11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR12</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor12 / kTopSenchaPinmuxMioOutIor12</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR13</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIor13 / kTopSenchaPinmuxMioOutIor13</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod0 / kTopSenchaPinmuxMioOutIod0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod1 / kTopSenchaPinmuxMioOutIod1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod2 / kTopSenchaPinmuxMioOutIod2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod3 / kTopSenchaPinmuxMioOutIod3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod4 / kTopSenchaPinmuxMioOutIod4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOD5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxInselIod5 / kTopSenchaPinmuxMioOutIod5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IO_CLK</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> |
+| <p style="font-size:smaller">IO_CLK_N</p> | <p style="font-size:smaller">AnalogIn0</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> |
+| <p style="font-size:smaller">POR_BUTTON_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Power-on reset button input</p> |
+| <p style="font-size:smaller">JTAG_SRST_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">JTAG header SRST, triggers POR</p> |
+| <p style="font-size:smaller">IO_CLKOUT</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Manual clock output for SCA setup</p> |
+| <p style="font-size:smaller">IO_TRIGGER</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Manual trigger output for SCA setup</p> |
+## Pinmux Connectivity
+
+| <p style="font-size:smaller">Module / Signal</p> | <p style="font-size:smaller">Connection</p> | <p style="font-size:smaller">Pad</p> | <p style="font-size:smaller">Pinmux Outsel Constant / Peripheral Input Index</p> | <p style="font-size:smaller">Description</p> |
+|:-------------------------------------------------------------:|:---------------------------------------------:|:----------------------------------------------:|:------------------------------------------------------------------------------------------------------------:|:----------------------------------------------:|
+| <p style="font-size:smaller">usbdev_usb_dp</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">usbdev_usb_dn</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[0]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D0</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[1]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D1</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[2]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D2</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sd[3]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_D3</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[0]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D0</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[1]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D1</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[2]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D2</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sd[3]</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_D3</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio0 / kTopSenchaPinmuxPeripheralInGpioGpio0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio1 / kTopSenchaPinmuxPeripheralInGpioGpio1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio2 / kTopSenchaPinmuxPeripheralInGpioGpio2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio3 / kTopSenchaPinmuxPeripheralInGpioGpio3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio4 / kTopSenchaPinmuxPeripheralInGpioGpio4</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio5 / kTopSenchaPinmuxPeripheralInGpioGpio5</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio6 / kTopSenchaPinmuxPeripheralInGpioGpio6</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio7 / kTopSenchaPinmuxPeripheralInGpioGpio7</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[8]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio8 / kTopSenchaPinmuxPeripheralInGpioGpio8</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[9]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio9 / kTopSenchaPinmuxPeripheralInGpioGpio9</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[10]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio10 / kTopSenchaPinmuxPeripheralInGpioGpio10</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[11]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio11 / kTopSenchaPinmuxPeripheralInGpioGpio11</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[12]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio12 / kTopSenchaPinmuxPeripheralInGpioGpio12</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[13]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio13 / kTopSenchaPinmuxPeripheralInGpioGpio13</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[14]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio14 / kTopSenchaPinmuxPeripheralInGpioGpio14</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[15]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio15 / kTopSenchaPinmuxPeripheralInGpioGpio15</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[16]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio16 / kTopSenchaPinmuxPeripheralInGpioGpio16</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[17]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio17 / kTopSenchaPinmuxPeripheralInGpioGpio17</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[18]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio18 / kTopSenchaPinmuxPeripheralInGpioGpio18</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[19]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio19 / kTopSenchaPinmuxPeripheralInGpioGpio19</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[20]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio20 / kTopSenchaPinmuxPeripheralInGpioGpio20</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[21]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio21 / kTopSenchaPinmuxPeripheralInGpioGpio21</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[22]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio22 / kTopSenchaPinmuxPeripheralInGpioGpio22</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[23]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio23 / kTopSenchaPinmuxPeripheralInGpioGpio23</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[24]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio24 / kTopSenchaPinmuxPeripheralInGpioGpio24</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[25]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio25 / kTopSenchaPinmuxPeripheralInGpioGpio25</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[26]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio26 / kTopSenchaPinmuxPeripheralInGpioGpio26</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[27]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio27 / kTopSenchaPinmuxPeripheralInGpioGpio27</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[28]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio28 / kTopSenchaPinmuxPeripheralInGpioGpio28</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[29]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio29 / kTopSenchaPinmuxPeripheralInGpioGpio29</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[30]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio30 / kTopSenchaPinmuxPeripheralInGpioGpio30</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">gpio_gpio[31]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselGpioGpio31 / kTopSenchaPinmuxPeripheralInGpioGpio31</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c0_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c0Sda / kTopSenchaPinmuxPeripheralInI2c0Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c0_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c0Scl / kTopSenchaPinmuxPeripheralInI2c0Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c1_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c1Sda / kTopSenchaPinmuxPeripheralInI2c1Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c1_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c1Scl / kTopSenchaPinmuxPeripheralInI2c1Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c2_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c2Sda / kTopSenchaPinmuxPeripheralInI2c2Sda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2c2_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2c2Scl / kTopSenchaPinmuxPeripheralInI2c2Scl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_i2c_sda</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamI2cSda / kTopSenchaPinmuxPeripheralInCamI2cSda</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_i2c_scl</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamI2cScl / kTopSenchaPinmuxPeripheralInCamI2cScl</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd0 / kTopSenchaPinmuxPeripheralInSpiHost1Sd0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd1 / kTopSenchaPinmuxPeripheralInSpiHost1Sd1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd2 / kTopSenchaPinmuxPeripheralInSpiHost1Sd2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sd[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sd3 / kTopSenchaPinmuxPeripheralInSpiHost1Sd3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd0 / kTopSenchaPinmuxPeripheralInSpiHost2Sd0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd1 / kTopSenchaPinmuxPeripheralInSpiHost2Sd1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd2 / kTopSenchaPinmuxPeripheralInSpiHost2Sd2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sd[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sd3 / kTopSenchaPinmuxPeripheralInSpiHost2Sd3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_ec_rst_l</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">IOR8</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_flash_wp_l</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">IOR9</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_DEV_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart0_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart0Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart1_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart1Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart2_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUart2Rx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">smc_uart_rx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSmcUartRx</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_ctrl_cam_int</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInCamCtrlCamInt</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_pclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSPclk</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData0</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData1</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData2</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData3</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData4</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData5</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData6</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_data[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSData7</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_hsync</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSHsync</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">isp_wrapper_s_vsync</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInIspWrapperSVsync</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInI2s0RxSd</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_device_tpm_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSpiDeviceTpmCsb</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTck</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tms</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTms</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tdi</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInFlashCtrlTdi</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_ac_present</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonAcPresent</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key0_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey0In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key1_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey1In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key2_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey2In</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_in</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonPwrbIn</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_lid_open</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInSysrstCtrlAonLidOpen</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">usbdev_sense</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / kTopSenchaPinmuxPeripheralInUsbdevSense</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_sck</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_CLK</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host0_csb</p> | <p style="font-size:smaller">direct</p> | <p style="font-size:smaller">SPI_HOST_CS_L</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">uart2_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselUart2Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">smc_uart_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSmcUartTx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">cam_ctrl_cam_trig</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselCamCtrlCamTrig / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0RxSclk / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_rx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0RxWs / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_sclk</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxSclk / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_ws</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxWs / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">i2s0_tx_sd</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselI2s0TxSd / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pda0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPda0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pcl0_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPcl0Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pda1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPda1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pattgen_pcl1_tx</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPattgenPcl1Tx / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_sck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Sck / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host1_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost1Csb / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_sck</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Sck / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">spi_host2_csb</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSpiHost2Csb / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">flash_ctrl_tdo</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselFlashCtrlTdo / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut1 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut2 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut3 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut4 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut5 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[6]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut6 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[7]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut7 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sensor_ctrl_ast_debug_out[8]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSensorCtrlAstDebugOut8 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[1]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm1 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[2]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm2 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[3]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm3 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[4]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm4 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">pwm_aon_pwm[5]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselPwmAonPwm5 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">otp_ctrl_test[0]</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselOtpCtrlTest0 / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_bat_disable</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonBatDisable / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key0_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey0Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_key2_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonKey2Out / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonPwrbOut / -</p> | <p style="font-size:smaller"></p> |
+| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopSenchaPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_sencha/ip/pinmux/doc/autogen/targets.md b/hw/top_sencha/ip/pinmux/doc/autogen/targets.md
new file mode 100644
index 0000000..b65495a
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/doc/autogen/targets.md
@@ -0,0 +1,11 @@
+<!--
+DO NOT EDIT THIS FILE DIRECTLY.
+It has been generated with the following command:
+util/topgen.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+-->
+
+| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables |
+|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:---------------------------------------------------------------------------------:|
+| ASIC | 4 | 53 | 14 | 15 | 82 | [Pinout Table](../../../top_sencha/ip/pinmux/doc/autogen/pinout_asic/index.html) |
+| NEXUS | 4 | 53 | 14 | 9 | 76 | [Pinout Table](../../../top_sencha/ip/pinmux/doc/autogen/pinout_nexus/index.html) |
diff --git a/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
new file mode 100644
index 0000000..a9e6e53
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -0,0 +1,2921 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pinmux_reg_pkg;
+
+ // Param list
+ parameter int AttrDw = 13;
+ parameter int NMioPeriphIn = 76;
+ parameter int NMioPeriphOut = 89;
+ parameter int NMioPads = 53;
+ parameter int NDioPads = 16;
+ parameter int NWkupDetect = 8;
+ parameter int WkupCntWidth = 8;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 12;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pinmux_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [5:0] q;
+ } pinmux_reg2hw_mio_periph_insel_mreg_t;
+
+ typedef struct packed {
+ logic [6:0] q;
+ } pinmux_reg2hw_mio_outsel_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } invert;
+ struct packed {
+ logic q;
+ logic qe;
+ } virtual_od_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } pull_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } pull_select;
+ struct packed {
+ logic q;
+ logic qe;
+ } keeper_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } schmitt_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } od_en;
+ struct packed {
+ logic [1:0] q;
+ logic qe;
+ } slew_rate;
+ struct packed {
+ logic [3:0] q;
+ logic qe;
+ } drive_strength;
+ } pinmux_reg2hw_mio_pad_attr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } invert;
+ struct packed {
+ logic q;
+ logic qe;
+ } virtual_od_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } pull_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } pull_select;
+ struct packed {
+ logic q;
+ logic qe;
+ } keeper_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } schmitt_en;
+ struct packed {
+ logic q;
+ logic qe;
+ } od_en;
+ struct packed {
+ logic [1:0] q;
+ logic qe;
+ } slew_rate;
+ struct packed {
+ logic [3:0] q;
+ logic qe;
+ } drive_strength;
+ } pinmux_reg2hw_dio_pad_attr_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_mio_pad_sleep_status_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_mio_pad_sleep_en_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } pinmux_reg2hw_mio_pad_sleep_mode_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_dio_pad_sleep_status_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_dio_pad_sleep_en_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } pinmux_reg2hw_dio_pad_sleep_mode_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_wkup_detector_en_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [2:0] q;
+ } mode;
+ struct packed {
+ logic q;
+ } filter;
+ struct packed {
+ logic q;
+ } miodio;
+ } pinmux_reg2hw_wkup_detector_mreg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ } pinmux_reg2hw_wkup_detector_cnt_th_mreg_t;
+
+ typedef struct packed {
+ logic [5:0] q;
+ } pinmux_reg2hw_wkup_detector_padsel_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pinmux_reg2hw_wkup_cause_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } invert;
+ struct packed {
+ logic d;
+ } virtual_od_en;
+ struct packed {
+ logic d;
+ } pull_en;
+ struct packed {
+ logic d;
+ } pull_select;
+ struct packed {
+ logic d;
+ } keeper_en;
+ struct packed {
+ logic d;
+ } schmitt_en;
+ struct packed {
+ logic d;
+ } od_en;
+ struct packed {
+ logic [1:0] d;
+ } slew_rate;
+ struct packed {
+ logic [3:0] d;
+ } drive_strength;
+ } pinmux_hw2reg_mio_pad_attr_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ } invert;
+ struct packed {
+ logic d;
+ } virtual_od_en;
+ struct packed {
+ logic d;
+ } pull_en;
+ struct packed {
+ logic d;
+ } pull_select;
+ struct packed {
+ logic d;
+ } keeper_en;
+ struct packed {
+ logic d;
+ } schmitt_en;
+ struct packed {
+ logic d;
+ } od_en;
+ struct packed {
+ logic [1:0] d;
+ } slew_rate;
+ struct packed {
+ logic [3:0] d;
+ } drive_strength;
+ } pinmux_hw2reg_dio_pad_attr_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pinmux_hw2reg_mio_pad_sleep_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pinmux_hw2reg_dio_pad_sleep_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pinmux_hw2reg_wkup_cause_mreg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ pinmux_reg2hw_alert_test_reg_t alert_test; // [2790:2789]
+ pinmux_reg2hw_mio_periph_insel_mreg_t [75:0] mio_periph_insel; // [2788:2333]
+ pinmux_reg2hw_mio_outsel_mreg_t [52:0] mio_outsel; // [2332:1962]
+ pinmux_reg2hw_mio_pad_attr_mreg_t [52:0] mio_pad_attr; // [1961:796]
+ pinmux_reg2hw_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [795:444]
+ pinmux_reg2hw_mio_pad_sleep_status_mreg_t [52:0] mio_pad_sleep_status; // [443:391]
+ pinmux_reg2hw_mio_pad_sleep_en_mreg_t [52:0] mio_pad_sleep_en; // [390:338]
+ pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [52:0] mio_pad_sleep_mode; // [337:232]
+ pinmux_reg2hw_dio_pad_sleep_status_mreg_t [15:0] dio_pad_sleep_status; // [231:216]
+ pinmux_reg2hw_dio_pad_sleep_en_mreg_t [15:0] dio_pad_sleep_en; // [215:200]
+ pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [15:0] dio_pad_sleep_mode; // [199:168]
+ pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [167:160]
+ pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [159:120]
+ pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [119:56]
+ pinmux_reg2hw_wkup_detector_padsel_mreg_t [7:0] wkup_detector_padsel; // [55:8]
+ pinmux_reg2hw_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0]
+ } pinmux_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ pinmux_hw2reg_mio_pad_attr_mreg_t [52:0] mio_pad_attr; // [1050:362]
+ pinmux_hw2reg_dio_pad_attr_mreg_t [15:0] dio_pad_attr; // [361:154]
+ pinmux_hw2reg_mio_pad_sleep_status_mreg_t [52:0] mio_pad_sleep_status; // [153:48]
+ pinmux_hw2reg_dio_pad_sleep_status_mreg_t [15:0] dio_pad_sleep_status; // [47:16]
+ pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [15:0]
+ } pinmux_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] PINMUX_ALERT_TEST_OFFSET = 12'h 0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 12'h 4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 12'h 8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 12'h c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 12'h 10;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET = 12'h 14;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET = 12'h 18;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET = 12'h 1c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET = 12'h 20;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET = 12'h 24;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET = 12'h 28;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET = 12'h 2c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET = 12'h 30;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET = 12'h 34;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET = 12'h 38;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET = 12'h 3c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET = 12'h 40;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET = 12'h 44;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET = 12'h 48;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET = 12'h 4c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET = 12'h 50;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET = 12'h 54;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET = 12'h 58;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET = 12'h 5c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET = 12'h 60;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET = 12'h 64;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET = 12'h 68;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET = 12'h 6c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET = 12'h 70;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET = 12'h 74;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET = 12'h 78;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET = 12'h 7c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET = 12'h 80;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 12'h 84;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET = 12'h 88;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET = 12'h 8c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET = 12'h 90;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET = 12'h 94;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET = 12'h 98;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET = 12'h 9c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET = 12'h a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET = 12'h a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET = 12'h a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET = 12'h ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET = 12'h b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET = 12'h b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET = 12'h b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET = 12'h bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET = 12'h c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET = 12'h c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET = 12'h c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET = 12'h cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET = 12'h d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET = 12'h d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET = 12'h d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET = 12'h e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET = 12'h e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET = 12'h e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET = 12'h ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET = 12'h f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_60_OFFSET = 12'h f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_61_OFFSET = 12'h f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_62_OFFSET = 12'h fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_63_OFFSET = 12'h 100;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_64_OFFSET = 12'h 104;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_65_OFFSET = 12'h 108;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_66_OFFSET = 12'h 10c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_67_OFFSET = 12'h 110;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_68_OFFSET = 12'h 114;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_69_OFFSET = 12'h 118;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_70_OFFSET = 12'h 11c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_71_OFFSET = 12'h 120;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_72_OFFSET = 12'h 124;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_73_OFFSET = 12'h 128;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_74_OFFSET = 12'h 12c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_75_OFFSET = 12'h 130;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h 134;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h 138;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h 13c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h 140;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h 144;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h 148;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h 14c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h 150;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 154;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 158;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 15c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 160;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 164;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 168;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 16c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 170;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 174;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 178;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 17c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 180;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 184;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 188;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 18c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 190;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 194;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 198;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 19c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 1a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 1a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 1a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 1ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 1b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 1b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 1b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 1bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 1c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 1c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 1c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 1cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 1d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 1d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 1d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 1dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 1e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 1e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 1e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 1ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 1f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 200;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 204;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 208;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 20c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_55_OFFSET = 12'h 210;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_56_OFFSET = 12'h 214;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_57_OFFSET = 12'h 218;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_58_OFFSET = 12'h 21c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_59_OFFSET = 12'h 220;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_60_OFFSET = 12'h 224;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_61_OFFSET = 12'h 228;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_62_OFFSET = 12'h 22c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_63_OFFSET = 12'h 230;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_64_OFFSET = 12'h 234;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_65_OFFSET = 12'h 238;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_66_OFFSET = 12'h 23c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_67_OFFSET = 12'h 240;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_68_OFFSET = 12'h 244;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_69_OFFSET = 12'h 248;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_70_OFFSET = 12'h 24c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_71_OFFSET = 12'h 250;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_72_OFFSET = 12'h 254;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_73_OFFSET = 12'h 258;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_74_OFFSET = 12'h 25c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_75_OFFSET = 12'h 260;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 264;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 268;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 26c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 270;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 274;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 278;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 27c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 280;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 284;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 288;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 28c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 290;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 294;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 298;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 29c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 2a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 2a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 2a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 2ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 2b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 2b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 2b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 2bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 2c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 2c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 2c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 2cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 2d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 2d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 2d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 2dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 2e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 2e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 2e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 2ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 2f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 2f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 2f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 2fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 300;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 304;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 308;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 30c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 310;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 314;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 318;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 31c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_47_OFFSET = 12'h 320;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_48_OFFSET = 12'h 324;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_49_OFFSET = 12'h 328;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_50_OFFSET = 12'h 32c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_51_OFFSET = 12'h 330;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_52_OFFSET = 12'h 334;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 338;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 33c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 340;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 344;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 348;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 34c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 350;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 354;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 358;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 35c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 360;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 364;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 368;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 36c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 370;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 374;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 378;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 37c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 380;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 384;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 388;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 38c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 390;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 394;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 398;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 39c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 3a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 3a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 3a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 3ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 3b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 3b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 3b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 3bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 3c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 3c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 3c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 3cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 3d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 3d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 3d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 3dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 3e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 3e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 3e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 3ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 3f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_47_OFFSET = 12'h 3f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_48_OFFSET = 12'h 3f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_49_OFFSET = 12'h 3fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_50_OFFSET = 12'h 400;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_51_OFFSET = 12'h 404;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_52_OFFSET = 12'h 408;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 40c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 410;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 414;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 418;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 41c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 420;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 424;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 428;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 42c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 430;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 434;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 438;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 43c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 440;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 444;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 448;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 44c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 450;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 454;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 458;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 45c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 460;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 464;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 468;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 46c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 470;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 474;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 478;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 47c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 480;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 484;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 488;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 48c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 490;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 494;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 498;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 49c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 4a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 4a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 4a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 4ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 4b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 4b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 4b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 4bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 4c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 4c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_47_OFFSET = 12'h 4c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_48_OFFSET = 12'h 4cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_49_OFFSET = 12'h 4d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_50_OFFSET = 12'h 4d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_51_OFFSET = 12'h 4d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_52_OFFSET = 12'h 4dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 4e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 4e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 4e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 4ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 4f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 4f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 4f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 4fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 500;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 504;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 508;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 50c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 510;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 514;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 518;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 51c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 520;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 524;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 528;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 52c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 530;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 534;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 538;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 53c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 540;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 544;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 548;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 54c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 550;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 554;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 558;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 55c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 560;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 564;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 568;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 56c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 570;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 574;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 578;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 57c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 580;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 584;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 588;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 58c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 590;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 594;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 598;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_47_OFFSET = 12'h 59c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_48_OFFSET = 12'h 5a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_49_OFFSET = 12'h 5a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_50_OFFSET = 12'h 5a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_51_OFFSET = 12'h 5ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_52_OFFSET = 12'h 5b0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 5b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 5b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 5bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 5c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 5c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 5c8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 5cc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 5d0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 5d4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 5d8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 5dc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 5e0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 5e4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 5e8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 5ec;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 5f0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 5f4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 5f8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 5fc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 600;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 604;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 608;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 60c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 610;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 614;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 618;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 61c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 620;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 624;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 628;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 62c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 630;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 634;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 638;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 63c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 640;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 644;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 648;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 64c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 650;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 654;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 658;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 65c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 660;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 664;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 668;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 66c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 670;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 674;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 678;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 67c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 680;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 684;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 688;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 68c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 690;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 694;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 698;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 69c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 6a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 6a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 6a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 6ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 6b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 6b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 6b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 6bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 6c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 6c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 6c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 6cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 6d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 6d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 6d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 6dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 6e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 6e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 6e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 6ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 6f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 6f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_47_OFFSET = 12'h 6f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_48_OFFSET = 12'h 6fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_49_OFFSET = 12'h 700;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_50_OFFSET = 12'h 704;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_51_OFFSET = 12'h 708;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_52_OFFSET = 12'h 70c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 710;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 714;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 718;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 71c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 720;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 724;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 728;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 72c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 730;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 734;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 738;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 73c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 740;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 744;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 748;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 74c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 750;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 754;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 758;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 75c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 760;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 764;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 768;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 76c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 770;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 774;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 778;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 77c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 780;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 784;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 788;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 78c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 790;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 794;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 798;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 79c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 7a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 7a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 7a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 7ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 7b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 7b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 7b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 7bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 7c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 7c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 7c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_47_OFFSET = 12'h 7cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_48_OFFSET = 12'h 7d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_49_OFFSET = 12'h 7d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_50_OFFSET = 12'h 7d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_51_OFFSET = 12'h 7dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_52_OFFSET = 12'h 7e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 7e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 7e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 7ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 7f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 7f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 7f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 7fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 800;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 804;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 808;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 80c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 810;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 814;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 818;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 81c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 820;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 824;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 828;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 82c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 830;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 834;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 838;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 83c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 840;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 844;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 848;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 84c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 850;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 854;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 858;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 85c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 860;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 864;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 868;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 86c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 870;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 874;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 878;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 87c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 880;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 884;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 888;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 88c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 890;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 894;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 898;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 89c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_47_OFFSET = 12'h 8a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_48_OFFSET = 12'h 8a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_49_OFFSET = 12'h 8a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_50_OFFSET = 12'h 8ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_51_OFFSET = 12'h 8b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_52_OFFSET = 12'h 8b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 8b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 8bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 8c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 8c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 8c8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 8cc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 8d0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 8d4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 8d8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 8dc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 8e0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 8e4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 8e8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 8ec;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 8f0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 8f4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 8f8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 8fc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 900;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 904;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 908;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 90c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 910;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 914;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 918;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 91c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 920;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 924;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 928;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 92c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 930;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 934;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 938;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 93c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 940;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 944;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 948;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 94c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 950;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 954;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 958;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 95c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 960;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 964;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 968;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 96c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 970;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 974;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 978;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 97c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 980;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 984;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 988;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 98c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 990;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 994;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 998;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 99c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 9a0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 9a4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 9a8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 9ac;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 9b0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 9b4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 9b8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 9bc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 9c0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 9c4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 9c8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 9cc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 9d0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 9d4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 9d8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 9dc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 9e0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 9e4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 9e8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 9ec;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 9f0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 9f4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 9f8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 9fc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h a00;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h a04;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h a08;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h a0c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h a10;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h a14;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h a18;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h a1c;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_1_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_2_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_3_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_4_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_5_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_6_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_7_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_8_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_9_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_10_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_11_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_12_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_INVERT_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_PULL_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_PULL_SELECT_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_KEEPER_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_SCHMITT_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_12_OD_EN_12_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_13_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_INVERT_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_PULL_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_PULL_SELECT_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_KEEPER_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_SCHMITT_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_13_OD_EN_13_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_14_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_INVERT_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_PULL_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_PULL_SELECT_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_KEEPER_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_SCHMITT_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_14_OD_EN_14_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_15_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_INVERT_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_PULL_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_PULL_SELECT_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_KEEPER_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_SCHMITT_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_15_OD_EN_15_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_16_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_INVERT_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_PULL_EN_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_PULL_SELECT_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_KEEPER_EN_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_SCHMITT_EN_16_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_16_OD_EN_16_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_17_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_INVERT_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_PULL_EN_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_PULL_SELECT_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_KEEPER_EN_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_SCHMITT_EN_17_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_17_OD_EN_17_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_18_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_INVERT_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_PULL_EN_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_PULL_SELECT_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_KEEPER_EN_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_SCHMITT_EN_18_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_18_OD_EN_18_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_19_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_INVERT_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_PULL_EN_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_PULL_SELECT_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_KEEPER_EN_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_SCHMITT_EN_19_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_19_OD_EN_19_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_20_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_INVERT_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_PULL_EN_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_PULL_SELECT_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_KEEPER_EN_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_SCHMITT_EN_20_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_20_OD_EN_20_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_21_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_INVERT_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_PULL_EN_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_PULL_SELECT_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_KEEPER_EN_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_SCHMITT_EN_21_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_21_OD_EN_21_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_22_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_INVERT_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_PULL_EN_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_PULL_SELECT_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_KEEPER_EN_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_SCHMITT_EN_22_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_22_OD_EN_22_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_23_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_INVERT_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_PULL_EN_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_PULL_SELECT_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_KEEPER_EN_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_SCHMITT_EN_23_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_23_OD_EN_23_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_24_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_INVERT_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_PULL_EN_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_PULL_SELECT_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_KEEPER_EN_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_SCHMITT_EN_24_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_24_OD_EN_24_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_25_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_INVERT_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_PULL_EN_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_PULL_SELECT_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_KEEPER_EN_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_SCHMITT_EN_25_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_25_OD_EN_25_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_26_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_INVERT_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_PULL_EN_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_PULL_SELECT_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_KEEPER_EN_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_SCHMITT_EN_26_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_26_OD_EN_26_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_27_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_INVERT_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_PULL_EN_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_PULL_SELECT_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_KEEPER_EN_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_SCHMITT_EN_27_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_27_OD_EN_27_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_28_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_INVERT_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_PULL_EN_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_PULL_SELECT_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_KEEPER_EN_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_SCHMITT_EN_28_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_28_OD_EN_28_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_29_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_INVERT_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_PULL_EN_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_PULL_SELECT_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_KEEPER_EN_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_SCHMITT_EN_29_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_29_OD_EN_29_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_30_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_INVERT_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_PULL_EN_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_PULL_SELECT_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_KEEPER_EN_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_SCHMITT_EN_30_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_30_OD_EN_30_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_31_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_INVERT_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_PULL_EN_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_PULL_SELECT_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_KEEPER_EN_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_SCHMITT_EN_31_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_31_OD_EN_31_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_32_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_INVERT_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_PULL_EN_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_PULL_SELECT_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_KEEPER_EN_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_SCHMITT_EN_32_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_32_OD_EN_32_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_33_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_INVERT_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_PULL_EN_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_PULL_SELECT_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_KEEPER_EN_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_SCHMITT_EN_33_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_33_OD_EN_33_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_34_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_INVERT_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_PULL_EN_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_PULL_SELECT_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_KEEPER_EN_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_SCHMITT_EN_34_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_34_OD_EN_34_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_35_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_INVERT_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_PULL_EN_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_PULL_SELECT_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_KEEPER_EN_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_SCHMITT_EN_35_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_35_OD_EN_35_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_36_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_INVERT_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_PULL_EN_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_PULL_SELECT_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_KEEPER_EN_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_SCHMITT_EN_36_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_36_OD_EN_36_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_37_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_INVERT_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_PULL_EN_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_PULL_SELECT_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_KEEPER_EN_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_SCHMITT_EN_37_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_37_OD_EN_37_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_38_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_INVERT_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_PULL_EN_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_PULL_SELECT_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_KEEPER_EN_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_SCHMITT_EN_38_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_38_OD_EN_38_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_39_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_INVERT_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_PULL_EN_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_PULL_SELECT_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_KEEPER_EN_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_SCHMITT_EN_39_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_39_OD_EN_39_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_40_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_INVERT_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_PULL_EN_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_PULL_SELECT_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_KEEPER_EN_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_SCHMITT_EN_40_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_40_OD_EN_40_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_41_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_INVERT_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_PULL_EN_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_PULL_SELECT_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_KEEPER_EN_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_SCHMITT_EN_41_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_41_OD_EN_41_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_42_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_INVERT_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_PULL_EN_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_PULL_SELECT_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_KEEPER_EN_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_SCHMITT_EN_42_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_42_OD_EN_42_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_43_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_INVERT_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_PULL_EN_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_PULL_SELECT_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_KEEPER_EN_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_SCHMITT_EN_43_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_43_OD_EN_43_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_44_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_INVERT_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_PULL_EN_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_PULL_SELECT_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_KEEPER_EN_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_SCHMITT_EN_44_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_44_OD_EN_44_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_45_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_INVERT_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_PULL_EN_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_PULL_SELECT_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_KEEPER_EN_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_SCHMITT_EN_45_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_45_OD_EN_45_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_46_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_INVERT_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_PULL_EN_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_PULL_SELECT_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_KEEPER_EN_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_SCHMITT_EN_46_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_46_OD_EN_46_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_47_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_INVERT_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_PULL_EN_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_PULL_SELECT_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_KEEPER_EN_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_SCHMITT_EN_47_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_47_OD_EN_47_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_48_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_INVERT_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_PULL_EN_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_PULL_SELECT_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_KEEPER_EN_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_SCHMITT_EN_48_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_48_OD_EN_48_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_49_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_INVERT_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_PULL_EN_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_PULL_SELECT_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_KEEPER_EN_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_SCHMITT_EN_49_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_49_OD_EN_49_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_50_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_INVERT_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_PULL_EN_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_PULL_SELECT_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_KEEPER_EN_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_SCHMITT_EN_50_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_50_OD_EN_50_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_51_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_INVERT_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_PULL_EN_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_PULL_SELECT_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_KEEPER_EN_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_SCHMITT_EN_51_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_51_OD_EN_51_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_MIO_PAD_ATTR_52_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_INVERT_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_PULL_EN_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_PULL_SELECT_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_KEEPER_EN_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_SCHMITT_EN_52_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_MIO_PAD_ATTR_52_OD_EN_52_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_0_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_1_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_2_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_3_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_4_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_5_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_6_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_7_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_8_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_9_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_10_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_11_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_12_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_INVERT_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_OD_EN_12_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_13_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_INVERT_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_OD_EN_13_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_14_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_INVERT_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_OD_EN_14_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_RESVAL = 4'h 0;
+ parameter logic [23:0] PINMUX_DIO_PAD_ATTR_15_RESVAL = 24'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_INVERT_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_OD_EN_15_RESVAL = 1'h 0;
+ parameter logic [1:0] PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_RESVAL = 2'h 0;
+ parameter logic [3:0] PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_RESVAL = 4'h 0;
+
+ // Register index
+ typedef enum int {
+ PINMUX_ALERT_TEST,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_0,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_1,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_2,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_3,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_4,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_5,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_6,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_7,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_8,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_9,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_10,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_11,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_12,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_13,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_14,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_15,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_16,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_17,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_18,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_19,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_20,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_21,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_22,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_23,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_24,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_25,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_26,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_27,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_28,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_29,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_30,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_31,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_32,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_33,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_34,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_35,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_36,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_37,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_38,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_39,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_40,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_41,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_42,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_43,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_44,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_45,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_46,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_47,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_48,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_49,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_50,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_51,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_52,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_53,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_54,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_55,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_56,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_57,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_58,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_59,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_60,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_61,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_62,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_63,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_64,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_65,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_66,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_67,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_68,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_69,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_70,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_71,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_72,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_73,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_74,
+ PINMUX_MIO_PERIPH_INSEL_REGWEN_75,
+ PINMUX_MIO_PERIPH_INSEL_0,
+ PINMUX_MIO_PERIPH_INSEL_1,
+ PINMUX_MIO_PERIPH_INSEL_2,
+ PINMUX_MIO_PERIPH_INSEL_3,
+ PINMUX_MIO_PERIPH_INSEL_4,
+ PINMUX_MIO_PERIPH_INSEL_5,
+ PINMUX_MIO_PERIPH_INSEL_6,
+ PINMUX_MIO_PERIPH_INSEL_7,
+ PINMUX_MIO_PERIPH_INSEL_8,
+ PINMUX_MIO_PERIPH_INSEL_9,
+ PINMUX_MIO_PERIPH_INSEL_10,
+ PINMUX_MIO_PERIPH_INSEL_11,
+ PINMUX_MIO_PERIPH_INSEL_12,
+ PINMUX_MIO_PERIPH_INSEL_13,
+ PINMUX_MIO_PERIPH_INSEL_14,
+ PINMUX_MIO_PERIPH_INSEL_15,
+ PINMUX_MIO_PERIPH_INSEL_16,
+ PINMUX_MIO_PERIPH_INSEL_17,
+ PINMUX_MIO_PERIPH_INSEL_18,
+ PINMUX_MIO_PERIPH_INSEL_19,
+ PINMUX_MIO_PERIPH_INSEL_20,
+ PINMUX_MIO_PERIPH_INSEL_21,
+ PINMUX_MIO_PERIPH_INSEL_22,
+ PINMUX_MIO_PERIPH_INSEL_23,
+ PINMUX_MIO_PERIPH_INSEL_24,
+ PINMUX_MIO_PERIPH_INSEL_25,
+ PINMUX_MIO_PERIPH_INSEL_26,
+ PINMUX_MIO_PERIPH_INSEL_27,
+ PINMUX_MIO_PERIPH_INSEL_28,
+ PINMUX_MIO_PERIPH_INSEL_29,
+ PINMUX_MIO_PERIPH_INSEL_30,
+ PINMUX_MIO_PERIPH_INSEL_31,
+ PINMUX_MIO_PERIPH_INSEL_32,
+ PINMUX_MIO_PERIPH_INSEL_33,
+ PINMUX_MIO_PERIPH_INSEL_34,
+ PINMUX_MIO_PERIPH_INSEL_35,
+ PINMUX_MIO_PERIPH_INSEL_36,
+ PINMUX_MIO_PERIPH_INSEL_37,
+ PINMUX_MIO_PERIPH_INSEL_38,
+ PINMUX_MIO_PERIPH_INSEL_39,
+ PINMUX_MIO_PERIPH_INSEL_40,
+ PINMUX_MIO_PERIPH_INSEL_41,
+ PINMUX_MIO_PERIPH_INSEL_42,
+ PINMUX_MIO_PERIPH_INSEL_43,
+ PINMUX_MIO_PERIPH_INSEL_44,
+ PINMUX_MIO_PERIPH_INSEL_45,
+ PINMUX_MIO_PERIPH_INSEL_46,
+ PINMUX_MIO_PERIPH_INSEL_47,
+ PINMUX_MIO_PERIPH_INSEL_48,
+ PINMUX_MIO_PERIPH_INSEL_49,
+ PINMUX_MIO_PERIPH_INSEL_50,
+ PINMUX_MIO_PERIPH_INSEL_51,
+ PINMUX_MIO_PERIPH_INSEL_52,
+ PINMUX_MIO_PERIPH_INSEL_53,
+ PINMUX_MIO_PERIPH_INSEL_54,
+ PINMUX_MIO_PERIPH_INSEL_55,
+ PINMUX_MIO_PERIPH_INSEL_56,
+ PINMUX_MIO_PERIPH_INSEL_57,
+ PINMUX_MIO_PERIPH_INSEL_58,
+ PINMUX_MIO_PERIPH_INSEL_59,
+ PINMUX_MIO_PERIPH_INSEL_60,
+ PINMUX_MIO_PERIPH_INSEL_61,
+ PINMUX_MIO_PERIPH_INSEL_62,
+ PINMUX_MIO_PERIPH_INSEL_63,
+ PINMUX_MIO_PERIPH_INSEL_64,
+ PINMUX_MIO_PERIPH_INSEL_65,
+ PINMUX_MIO_PERIPH_INSEL_66,
+ PINMUX_MIO_PERIPH_INSEL_67,
+ PINMUX_MIO_PERIPH_INSEL_68,
+ PINMUX_MIO_PERIPH_INSEL_69,
+ PINMUX_MIO_PERIPH_INSEL_70,
+ PINMUX_MIO_PERIPH_INSEL_71,
+ PINMUX_MIO_PERIPH_INSEL_72,
+ PINMUX_MIO_PERIPH_INSEL_73,
+ PINMUX_MIO_PERIPH_INSEL_74,
+ PINMUX_MIO_PERIPH_INSEL_75,
+ PINMUX_MIO_OUTSEL_REGWEN_0,
+ PINMUX_MIO_OUTSEL_REGWEN_1,
+ PINMUX_MIO_OUTSEL_REGWEN_2,
+ PINMUX_MIO_OUTSEL_REGWEN_3,
+ PINMUX_MIO_OUTSEL_REGWEN_4,
+ PINMUX_MIO_OUTSEL_REGWEN_5,
+ PINMUX_MIO_OUTSEL_REGWEN_6,
+ PINMUX_MIO_OUTSEL_REGWEN_7,
+ PINMUX_MIO_OUTSEL_REGWEN_8,
+ PINMUX_MIO_OUTSEL_REGWEN_9,
+ PINMUX_MIO_OUTSEL_REGWEN_10,
+ PINMUX_MIO_OUTSEL_REGWEN_11,
+ PINMUX_MIO_OUTSEL_REGWEN_12,
+ PINMUX_MIO_OUTSEL_REGWEN_13,
+ PINMUX_MIO_OUTSEL_REGWEN_14,
+ PINMUX_MIO_OUTSEL_REGWEN_15,
+ PINMUX_MIO_OUTSEL_REGWEN_16,
+ PINMUX_MIO_OUTSEL_REGWEN_17,
+ PINMUX_MIO_OUTSEL_REGWEN_18,
+ PINMUX_MIO_OUTSEL_REGWEN_19,
+ PINMUX_MIO_OUTSEL_REGWEN_20,
+ PINMUX_MIO_OUTSEL_REGWEN_21,
+ PINMUX_MIO_OUTSEL_REGWEN_22,
+ PINMUX_MIO_OUTSEL_REGWEN_23,
+ PINMUX_MIO_OUTSEL_REGWEN_24,
+ PINMUX_MIO_OUTSEL_REGWEN_25,
+ PINMUX_MIO_OUTSEL_REGWEN_26,
+ PINMUX_MIO_OUTSEL_REGWEN_27,
+ PINMUX_MIO_OUTSEL_REGWEN_28,
+ PINMUX_MIO_OUTSEL_REGWEN_29,
+ PINMUX_MIO_OUTSEL_REGWEN_30,
+ PINMUX_MIO_OUTSEL_REGWEN_31,
+ PINMUX_MIO_OUTSEL_REGWEN_32,
+ PINMUX_MIO_OUTSEL_REGWEN_33,
+ PINMUX_MIO_OUTSEL_REGWEN_34,
+ PINMUX_MIO_OUTSEL_REGWEN_35,
+ PINMUX_MIO_OUTSEL_REGWEN_36,
+ PINMUX_MIO_OUTSEL_REGWEN_37,
+ PINMUX_MIO_OUTSEL_REGWEN_38,
+ PINMUX_MIO_OUTSEL_REGWEN_39,
+ PINMUX_MIO_OUTSEL_REGWEN_40,
+ PINMUX_MIO_OUTSEL_REGWEN_41,
+ PINMUX_MIO_OUTSEL_REGWEN_42,
+ PINMUX_MIO_OUTSEL_REGWEN_43,
+ PINMUX_MIO_OUTSEL_REGWEN_44,
+ PINMUX_MIO_OUTSEL_REGWEN_45,
+ PINMUX_MIO_OUTSEL_REGWEN_46,
+ PINMUX_MIO_OUTSEL_REGWEN_47,
+ PINMUX_MIO_OUTSEL_REGWEN_48,
+ PINMUX_MIO_OUTSEL_REGWEN_49,
+ PINMUX_MIO_OUTSEL_REGWEN_50,
+ PINMUX_MIO_OUTSEL_REGWEN_51,
+ PINMUX_MIO_OUTSEL_REGWEN_52,
+ PINMUX_MIO_OUTSEL_0,
+ PINMUX_MIO_OUTSEL_1,
+ PINMUX_MIO_OUTSEL_2,
+ PINMUX_MIO_OUTSEL_3,
+ PINMUX_MIO_OUTSEL_4,
+ PINMUX_MIO_OUTSEL_5,
+ PINMUX_MIO_OUTSEL_6,
+ PINMUX_MIO_OUTSEL_7,
+ PINMUX_MIO_OUTSEL_8,
+ PINMUX_MIO_OUTSEL_9,
+ PINMUX_MIO_OUTSEL_10,
+ PINMUX_MIO_OUTSEL_11,
+ PINMUX_MIO_OUTSEL_12,
+ PINMUX_MIO_OUTSEL_13,
+ PINMUX_MIO_OUTSEL_14,
+ PINMUX_MIO_OUTSEL_15,
+ PINMUX_MIO_OUTSEL_16,
+ PINMUX_MIO_OUTSEL_17,
+ PINMUX_MIO_OUTSEL_18,
+ PINMUX_MIO_OUTSEL_19,
+ PINMUX_MIO_OUTSEL_20,
+ PINMUX_MIO_OUTSEL_21,
+ PINMUX_MIO_OUTSEL_22,
+ PINMUX_MIO_OUTSEL_23,
+ PINMUX_MIO_OUTSEL_24,
+ PINMUX_MIO_OUTSEL_25,
+ PINMUX_MIO_OUTSEL_26,
+ PINMUX_MIO_OUTSEL_27,
+ PINMUX_MIO_OUTSEL_28,
+ PINMUX_MIO_OUTSEL_29,
+ PINMUX_MIO_OUTSEL_30,
+ PINMUX_MIO_OUTSEL_31,
+ PINMUX_MIO_OUTSEL_32,
+ PINMUX_MIO_OUTSEL_33,
+ PINMUX_MIO_OUTSEL_34,
+ PINMUX_MIO_OUTSEL_35,
+ PINMUX_MIO_OUTSEL_36,
+ PINMUX_MIO_OUTSEL_37,
+ PINMUX_MIO_OUTSEL_38,
+ PINMUX_MIO_OUTSEL_39,
+ PINMUX_MIO_OUTSEL_40,
+ PINMUX_MIO_OUTSEL_41,
+ PINMUX_MIO_OUTSEL_42,
+ PINMUX_MIO_OUTSEL_43,
+ PINMUX_MIO_OUTSEL_44,
+ PINMUX_MIO_OUTSEL_45,
+ PINMUX_MIO_OUTSEL_46,
+ PINMUX_MIO_OUTSEL_47,
+ PINMUX_MIO_OUTSEL_48,
+ PINMUX_MIO_OUTSEL_49,
+ PINMUX_MIO_OUTSEL_50,
+ PINMUX_MIO_OUTSEL_51,
+ PINMUX_MIO_OUTSEL_52,
+ PINMUX_MIO_PAD_ATTR_REGWEN_0,
+ PINMUX_MIO_PAD_ATTR_REGWEN_1,
+ PINMUX_MIO_PAD_ATTR_REGWEN_2,
+ PINMUX_MIO_PAD_ATTR_REGWEN_3,
+ PINMUX_MIO_PAD_ATTR_REGWEN_4,
+ PINMUX_MIO_PAD_ATTR_REGWEN_5,
+ PINMUX_MIO_PAD_ATTR_REGWEN_6,
+ PINMUX_MIO_PAD_ATTR_REGWEN_7,
+ PINMUX_MIO_PAD_ATTR_REGWEN_8,
+ PINMUX_MIO_PAD_ATTR_REGWEN_9,
+ PINMUX_MIO_PAD_ATTR_REGWEN_10,
+ PINMUX_MIO_PAD_ATTR_REGWEN_11,
+ PINMUX_MIO_PAD_ATTR_REGWEN_12,
+ PINMUX_MIO_PAD_ATTR_REGWEN_13,
+ PINMUX_MIO_PAD_ATTR_REGWEN_14,
+ PINMUX_MIO_PAD_ATTR_REGWEN_15,
+ PINMUX_MIO_PAD_ATTR_REGWEN_16,
+ PINMUX_MIO_PAD_ATTR_REGWEN_17,
+ PINMUX_MIO_PAD_ATTR_REGWEN_18,
+ PINMUX_MIO_PAD_ATTR_REGWEN_19,
+ PINMUX_MIO_PAD_ATTR_REGWEN_20,
+ PINMUX_MIO_PAD_ATTR_REGWEN_21,
+ PINMUX_MIO_PAD_ATTR_REGWEN_22,
+ PINMUX_MIO_PAD_ATTR_REGWEN_23,
+ PINMUX_MIO_PAD_ATTR_REGWEN_24,
+ PINMUX_MIO_PAD_ATTR_REGWEN_25,
+ PINMUX_MIO_PAD_ATTR_REGWEN_26,
+ PINMUX_MIO_PAD_ATTR_REGWEN_27,
+ PINMUX_MIO_PAD_ATTR_REGWEN_28,
+ PINMUX_MIO_PAD_ATTR_REGWEN_29,
+ PINMUX_MIO_PAD_ATTR_REGWEN_30,
+ PINMUX_MIO_PAD_ATTR_REGWEN_31,
+ PINMUX_MIO_PAD_ATTR_REGWEN_32,
+ PINMUX_MIO_PAD_ATTR_REGWEN_33,
+ PINMUX_MIO_PAD_ATTR_REGWEN_34,
+ PINMUX_MIO_PAD_ATTR_REGWEN_35,
+ PINMUX_MIO_PAD_ATTR_REGWEN_36,
+ PINMUX_MIO_PAD_ATTR_REGWEN_37,
+ PINMUX_MIO_PAD_ATTR_REGWEN_38,
+ PINMUX_MIO_PAD_ATTR_REGWEN_39,
+ PINMUX_MIO_PAD_ATTR_REGWEN_40,
+ PINMUX_MIO_PAD_ATTR_REGWEN_41,
+ PINMUX_MIO_PAD_ATTR_REGWEN_42,
+ PINMUX_MIO_PAD_ATTR_REGWEN_43,
+ PINMUX_MIO_PAD_ATTR_REGWEN_44,
+ PINMUX_MIO_PAD_ATTR_REGWEN_45,
+ PINMUX_MIO_PAD_ATTR_REGWEN_46,
+ PINMUX_MIO_PAD_ATTR_REGWEN_47,
+ PINMUX_MIO_PAD_ATTR_REGWEN_48,
+ PINMUX_MIO_PAD_ATTR_REGWEN_49,
+ PINMUX_MIO_PAD_ATTR_REGWEN_50,
+ PINMUX_MIO_PAD_ATTR_REGWEN_51,
+ PINMUX_MIO_PAD_ATTR_REGWEN_52,
+ PINMUX_MIO_PAD_ATTR_0,
+ PINMUX_MIO_PAD_ATTR_1,
+ PINMUX_MIO_PAD_ATTR_2,
+ PINMUX_MIO_PAD_ATTR_3,
+ PINMUX_MIO_PAD_ATTR_4,
+ PINMUX_MIO_PAD_ATTR_5,
+ PINMUX_MIO_PAD_ATTR_6,
+ PINMUX_MIO_PAD_ATTR_7,
+ PINMUX_MIO_PAD_ATTR_8,
+ PINMUX_MIO_PAD_ATTR_9,
+ PINMUX_MIO_PAD_ATTR_10,
+ PINMUX_MIO_PAD_ATTR_11,
+ PINMUX_MIO_PAD_ATTR_12,
+ PINMUX_MIO_PAD_ATTR_13,
+ PINMUX_MIO_PAD_ATTR_14,
+ PINMUX_MIO_PAD_ATTR_15,
+ PINMUX_MIO_PAD_ATTR_16,
+ PINMUX_MIO_PAD_ATTR_17,
+ PINMUX_MIO_PAD_ATTR_18,
+ PINMUX_MIO_PAD_ATTR_19,
+ PINMUX_MIO_PAD_ATTR_20,
+ PINMUX_MIO_PAD_ATTR_21,
+ PINMUX_MIO_PAD_ATTR_22,
+ PINMUX_MIO_PAD_ATTR_23,
+ PINMUX_MIO_PAD_ATTR_24,
+ PINMUX_MIO_PAD_ATTR_25,
+ PINMUX_MIO_PAD_ATTR_26,
+ PINMUX_MIO_PAD_ATTR_27,
+ PINMUX_MIO_PAD_ATTR_28,
+ PINMUX_MIO_PAD_ATTR_29,
+ PINMUX_MIO_PAD_ATTR_30,
+ PINMUX_MIO_PAD_ATTR_31,
+ PINMUX_MIO_PAD_ATTR_32,
+ PINMUX_MIO_PAD_ATTR_33,
+ PINMUX_MIO_PAD_ATTR_34,
+ PINMUX_MIO_PAD_ATTR_35,
+ PINMUX_MIO_PAD_ATTR_36,
+ PINMUX_MIO_PAD_ATTR_37,
+ PINMUX_MIO_PAD_ATTR_38,
+ PINMUX_MIO_PAD_ATTR_39,
+ PINMUX_MIO_PAD_ATTR_40,
+ PINMUX_MIO_PAD_ATTR_41,
+ PINMUX_MIO_PAD_ATTR_42,
+ PINMUX_MIO_PAD_ATTR_43,
+ PINMUX_MIO_PAD_ATTR_44,
+ PINMUX_MIO_PAD_ATTR_45,
+ PINMUX_MIO_PAD_ATTR_46,
+ PINMUX_MIO_PAD_ATTR_47,
+ PINMUX_MIO_PAD_ATTR_48,
+ PINMUX_MIO_PAD_ATTR_49,
+ PINMUX_MIO_PAD_ATTR_50,
+ PINMUX_MIO_PAD_ATTR_51,
+ PINMUX_MIO_PAD_ATTR_52,
+ PINMUX_DIO_PAD_ATTR_REGWEN_0,
+ PINMUX_DIO_PAD_ATTR_REGWEN_1,
+ PINMUX_DIO_PAD_ATTR_REGWEN_2,
+ PINMUX_DIO_PAD_ATTR_REGWEN_3,
+ PINMUX_DIO_PAD_ATTR_REGWEN_4,
+ PINMUX_DIO_PAD_ATTR_REGWEN_5,
+ PINMUX_DIO_PAD_ATTR_REGWEN_6,
+ PINMUX_DIO_PAD_ATTR_REGWEN_7,
+ PINMUX_DIO_PAD_ATTR_REGWEN_8,
+ PINMUX_DIO_PAD_ATTR_REGWEN_9,
+ PINMUX_DIO_PAD_ATTR_REGWEN_10,
+ PINMUX_DIO_PAD_ATTR_REGWEN_11,
+ PINMUX_DIO_PAD_ATTR_REGWEN_12,
+ PINMUX_DIO_PAD_ATTR_REGWEN_13,
+ PINMUX_DIO_PAD_ATTR_REGWEN_14,
+ PINMUX_DIO_PAD_ATTR_REGWEN_15,
+ PINMUX_DIO_PAD_ATTR_0,
+ PINMUX_DIO_PAD_ATTR_1,
+ PINMUX_DIO_PAD_ATTR_2,
+ PINMUX_DIO_PAD_ATTR_3,
+ PINMUX_DIO_PAD_ATTR_4,
+ PINMUX_DIO_PAD_ATTR_5,
+ PINMUX_DIO_PAD_ATTR_6,
+ PINMUX_DIO_PAD_ATTR_7,
+ PINMUX_DIO_PAD_ATTR_8,
+ PINMUX_DIO_PAD_ATTR_9,
+ PINMUX_DIO_PAD_ATTR_10,
+ PINMUX_DIO_PAD_ATTR_11,
+ PINMUX_DIO_PAD_ATTR_12,
+ PINMUX_DIO_PAD_ATTR_13,
+ PINMUX_DIO_PAD_ATTR_14,
+ PINMUX_DIO_PAD_ATTR_15,
+ PINMUX_MIO_PAD_SLEEP_STATUS_0,
+ PINMUX_MIO_PAD_SLEEP_STATUS_1,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_0,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_1,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_2,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_3,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_4,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_5,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_6,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_7,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_8,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_9,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_10,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_11,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_12,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_13,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_14,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_15,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_16,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_17,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_18,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_19,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_20,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_21,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_22,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_23,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_24,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_25,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_26,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_27,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_28,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_29,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_30,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_31,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_32,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_33,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_34,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_35,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_36,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_37,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_38,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_39,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_40,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_41,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_42,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_43,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_44,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_45,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_46,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_47,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_48,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_49,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_50,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_51,
+ PINMUX_MIO_PAD_SLEEP_REGWEN_52,
+ PINMUX_MIO_PAD_SLEEP_EN_0,
+ PINMUX_MIO_PAD_SLEEP_EN_1,
+ PINMUX_MIO_PAD_SLEEP_EN_2,
+ PINMUX_MIO_PAD_SLEEP_EN_3,
+ PINMUX_MIO_PAD_SLEEP_EN_4,
+ PINMUX_MIO_PAD_SLEEP_EN_5,
+ PINMUX_MIO_PAD_SLEEP_EN_6,
+ PINMUX_MIO_PAD_SLEEP_EN_7,
+ PINMUX_MIO_PAD_SLEEP_EN_8,
+ PINMUX_MIO_PAD_SLEEP_EN_9,
+ PINMUX_MIO_PAD_SLEEP_EN_10,
+ PINMUX_MIO_PAD_SLEEP_EN_11,
+ PINMUX_MIO_PAD_SLEEP_EN_12,
+ PINMUX_MIO_PAD_SLEEP_EN_13,
+ PINMUX_MIO_PAD_SLEEP_EN_14,
+ PINMUX_MIO_PAD_SLEEP_EN_15,
+ PINMUX_MIO_PAD_SLEEP_EN_16,
+ PINMUX_MIO_PAD_SLEEP_EN_17,
+ PINMUX_MIO_PAD_SLEEP_EN_18,
+ PINMUX_MIO_PAD_SLEEP_EN_19,
+ PINMUX_MIO_PAD_SLEEP_EN_20,
+ PINMUX_MIO_PAD_SLEEP_EN_21,
+ PINMUX_MIO_PAD_SLEEP_EN_22,
+ PINMUX_MIO_PAD_SLEEP_EN_23,
+ PINMUX_MIO_PAD_SLEEP_EN_24,
+ PINMUX_MIO_PAD_SLEEP_EN_25,
+ PINMUX_MIO_PAD_SLEEP_EN_26,
+ PINMUX_MIO_PAD_SLEEP_EN_27,
+ PINMUX_MIO_PAD_SLEEP_EN_28,
+ PINMUX_MIO_PAD_SLEEP_EN_29,
+ PINMUX_MIO_PAD_SLEEP_EN_30,
+ PINMUX_MIO_PAD_SLEEP_EN_31,
+ PINMUX_MIO_PAD_SLEEP_EN_32,
+ PINMUX_MIO_PAD_SLEEP_EN_33,
+ PINMUX_MIO_PAD_SLEEP_EN_34,
+ PINMUX_MIO_PAD_SLEEP_EN_35,
+ PINMUX_MIO_PAD_SLEEP_EN_36,
+ PINMUX_MIO_PAD_SLEEP_EN_37,
+ PINMUX_MIO_PAD_SLEEP_EN_38,
+ PINMUX_MIO_PAD_SLEEP_EN_39,
+ PINMUX_MIO_PAD_SLEEP_EN_40,
+ PINMUX_MIO_PAD_SLEEP_EN_41,
+ PINMUX_MIO_PAD_SLEEP_EN_42,
+ PINMUX_MIO_PAD_SLEEP_EN_43,
+ PINMUX_MIO_PAD_SLEEP_EN_44,
+ PINMUX_MIO_PAD_SLEEP_EN_45,
+ PINMUX_MIO_PAD_SLEEP_EN_46,
+ PINMUX_MIO_PAD_SLEEP_EN_47,
+ PINMUX_MIO_PAD_SLEEP_EN_48,
+ PINMUX_MIO_PAD_SLEEP_EN_49,
+ PINMUX_MIO_PAD_SLEEP_EN_50,
+ PINMUX_MIO_PAD_SLEEP_EN_51,
+ PINMUX_MIO_PAD_SLEEP_EN_52,
+ PINMUX_MIO_PAD_SLEEP_MODE_0,
+ PINMUX_MIO_PAD_SLEEP_MODE_1,
+ PINMUX_MIO_PAD_SLEEP_MODE_2,
+ PINMUX_MIO_PAD_SLEEP_MODE_3,
+ PINMUX_MIO_PAD_SLEEP_MODE_4,
+ PINMUX_MIO_PAD_SLEEP_MODE_5,
+ PINMUX_MIO_PAD_SLEEP_MODE_6,
+ PINMUX_MIO_PAD_SLEEP_MODE_7,
+ PINMUX_MIO_PAD_SLEEP_MODE_8,
+ PINMUX_MIO_PAD_SLEEP_MODE_9,
+ PINMUX_MIO_PAD_SLEEP_MODE_10,
+ PINMUX_MIO_PAD_SLEEP_MODE_11,
+ PINMUX_MIO_PAD_SLEEP_MODE_12,
+ PINMUX_MIO_PAD_SLEEP_MODE_13,
+ PINMUX_MIO_PAD_SLEEP_MODE_14,
+ PINMUX_MIO_PAD_SLEEP_MODE_15,
+ PINMUX_MIO_PAD_SLEEP_MODE_16,
+ PINMUX_MIO_PAD_SLEEP_MODE_17,
+ PINMUX_MIO_PAD_SLEEP_MODE_18,
+ PINMUX_MIO_PAD_SLEEP_MODE_19,
+ PINMUX_MIO_PAD_SLEEP_MODE_20,
+ PINMUX_MIO_PAD_SLEEP_MODE_21,
+ PINMUX_MIO_PAD_SLEEP_MODE_22,
+ PINMUX_MIO_PAD_SLEEP_MODE_23,
+ PINMUX_MIO_PAD_SLEEP_MODE_24,
+ PINMUX_MIO_PAD_SLEEP_MODE_25,
+ PINMUX_MIO_PAD_SLEEP_MODE_26,
+ PINMUX_MIO_PAD_SLEEP_MODE_27,
+ PINMUX_MIO_PAD_SLEEP_MODE_28,
+ PINMUX_MIO_PAD_SLEEP_MODE_29,
+ PINMUX_MIO_PAD_SLEEP_MODE_30,
+ PINMUX_MIO_PAD_SLEEP_MODE_31,
+ PINMUX_MIO_PAD_SLEEP_MODE_32,
+ PINMUX_MIO_PAD_SLEEP_MODE_33,
+ PINMUX_MIO_PAD_SLEEP_MODE_34,
+ PINMUX_MIO_PAD_SLEEP_MODE_35,
+ PINMUX_MIO_PAD_SLEEP_MODE_36,
+ PINMUX_MIO_PAD_SLEEP_MODE_37,
+ PINMUX_MIO_PAD_SLEEP_MODE_38,
+ PINMUX_MIO_PAD_SLEEP_MODE_39,
+ PINMUX_MIO_PAD_SLEEP_MODE_40,
+ PINMUX_MIO_PAD_SLEEP_MODE_41,
+ PINMUX_MIO_PAD_SLEEP_MODE_42,
+ PINMUX_MIO_PAD_SLEEP_MODE_43,
+ PINMUX_MIO_PAD_SLEEP_MODE_44,
+ PINMUX_MIO_PAD_SLEEP_MODE_45,
+ PINMUX_MIO_PAD_SLEEP_MODE_46,
+ PINMUX_MIO_PAD_SLEEP_MODE_47,
+ PINMUX_MIO_PAD_SLEEP_MODE_48,
+ PINMUX_MIO_PAD_SLEEP_MODE_49,
+ PINMUX_MIO_PAD_SLEEP_MODE_50,
+ PINMUX_MIO_PAD_SLEEP_MODE_51,
+ PINMUX_MIO_PAD_SLEEP_MODE_52,
+ PINMUX_DIO_PAD_SLEEP_STATUS,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_0,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_1,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_2,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_3,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_4,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_5,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_6,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_7,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_8,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_9,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_10,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_11,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_12,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_13,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_14,
+ PINMUX_DIO_PAD_SLEEP_REGWEN_15,
+ PINMUX_DIO_PAD_SLEEP_EN_0,
+ PINMUX_DIO_PAD_SLEEP_EN_1,
+ PINMUX_DIO_PAD_SLEEP_EN_2,
+ PINMUX_DIO_PAD_SLEEP_EN_3,
+ PINMUX_DIO_PAD_SLEEP_EN_4,
+ PINMUX_DIO_PAD_SLEEP_EN_5,
+ PINMUX_DIO_PAD_SLEEP_EN_6,
+ PINMUX_DIO_PAD_SLEEP_EN_7,
+ PINMUX_DIO_PAD_SLEEP_EN_8,
+ PINMUX_DIO_PAD_SLEEP_EN_9,
+ PINMUX_DIO_PAD_SLEEP_EN_10,
+ PINMUX_DIO_PAD_SLEEP_EN_11,
+ PINMUX_DIO_PAD_SLEEP_EN_12,
+ PINMUX_DIO_PAD_SLEEP_EN_13,
+ PINMUX_DIO_PAD_SLEEP_EN_14,
+ PINMUX_DIO_PAD_SLEEP_EN_15,
+ PINMUX_DIO_PAD_SLEEP_MODE_0,
+ PINMUX_DIO_PAD_SLEEP_MODE_1,
+ PINMUX_DIO_PAD_SLEEP_MODE_2,
+ PINMUX_DIO_PAD_SLEEP_MODE_3,
+ PINMUX_DIO_PAD_SLEEP_MODE_4,
+ PINMUX_DIO_PAD_SLEEP_MODE_5,
+ PINMUX_DIO_PAD_SLEEP_MODE_6,
+ PINMUX_DIO_PAD_SLEEP_MODE_7,
+ PINMUX_DIO_PAD_SLEEP_MODE_8,
+ PINMUX_DIO_PAD_SLEEP_MODE_9,
+ PINMUX_DIO_PAD_SLEEP_MODE_10,
+ PINMUX_DIO_PAD_SLEEP_MODE_11,
+ PINMUX_DIO_PAD_SLEEP_MODE_12,
+ PINMUX_DIO_PAD_SLEEP_MODE_13,
+ PINMUX_DIO_PAD_SLEEP_MODE_14,
+ PINMUX_DIO_PAD_SLEEP_MODE_15,
+ PINMUX_WKUP_DETECTOR_REGWEN_0,
+ PINMUX_WKUP_DETECTOR_REGWEN_1,
+ PINMUX_WKUP_DETECTOR_REGWEN_2,
+ PINMUX_WKUP_DETECTOR_REGWEN_3,
+ PINMUX_WKUP_DETECTOR_REGWEN_4,
+ PINMUX_WKUP_DETECTOR_REGWEN_5,
+ PINMUX_WKUP_DETECTOR_REGWEN_6,
+ PINMUX_WKUP_DETECTOR_REGWEN_7,
+ PINMUX_WKUP_DETECTOR_EN_0,
+ PINMUX_WKUP_DETECTOR_EN_1,
+ PINMUX_WKUP_DETECTOR_EN_2,
+ PINMUX_WKUP_DETECTOR_EN_3,
+ PINMUX_WKUP_DETECTOR_EN_4,
+ PINMUX_WKUP_DETECTOR_EN_5,
+ PINMUX_WKUP_DETECTOR_EN_6,
+ PINMUX_WKUP_DETECTOR_EN_7,
+ PINMUX_WKUP_DETECTOR_0,
+ PINMUX_WKUP_DETECTOR_1,
+ PINMUX_WKUP_DETECTOR_2,
+ PINMUX_WKUP_DETECTOR_3,
+ PINMUX_WKUP_DETECTOR_4,
+ PINMUX_WKUP_DETECTOR_5,
+ PINMUX_WKUP_DETECTOR_6,
+ PINMUX_WKUP_DETECTOR_7,
+ PINMUX_WKUP_DETECTOR_CNT_TH_0,
+ PINMUX_WKUP_DETECTOR_CNT_TH_1,
+ PINMUX_WKUP_DETECTOR_CNT_TH_2,
+ PINMUX_WKUP_DETECTOR_CNT_TH_3,
+ PINMUX_WKUP_DETECTOR_CNT_TH_4,
+ PINMUX_WKUP_DETECTOR_CNT_TH_5,
+ PINMUX_WKUP_DETECTOR_CNT_TH_6,
+ PINMUX_WKUP_DETECTOR_CNT_TH_7,
+ PINMUX_WKUP_DETECTOR_PADSEL_0,
+ PINMUX_WKUP_DETECTOR_PADSEL_1,
+ PINMUX_WKUP_DETECTOR_PADSEL_2,
+ PINMUX_WKUP_DETECTOR_PADSEL_3,
+ PINMUX_WKUP_DETECTOR_PADSEL_4,
+ PINMUX_WKUP_DETECTOR_PADSEL_5,
+ PINMUX_WKUP_DETECTOR_PADSEL_6,
+ PINMUX_WKUP_DETECTOR_PADSEL_7,
+ PINMUX_WKUP_CAUSE
+ } pinmux_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] PINMUX_PERMIT [648] = '{
+ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST
+ 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
+ 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
+ 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
+ 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_3
+ 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_REGWEN_4
+ 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_REGWEN_5
+ 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_REGWEN_6
+ 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_REGWEN_7
+ 4'b 0001, // index[ 9] PINMUX_MIO_PERIPH_INSEL_REGWEN_8
+ 4'b 0001, // index[ 10] PINMUX_MIO_PERIPH_INSEL_REGWEN_9
+ 4'b 0001, // index[ 11] PINMUX_MIO_PERIPH_INSEL_REGWEN_10
+ 4'b 0001, // index[ 12] PINMUX_MIO_PERIPH_INSEL_REGWEN_11
+ 4'b 0001, // index[ 13] PINMUX_MIO_PERIPH_INSEL_REGWEN_12
+ 4'b 0001, // index[ 14] PINMUX_MIO_PERIPH_INSEL_REGWEN_13
+ 4'b 0001, // index[ 15] PINMUX_MIO_PERIPH_INSEL_REGWEN_14
+ 4'b 0001, // index[ 16] PINMUX_MIO_PERIPH_INSEL_REGWEN_15
+ 4'b 0001, // index[ 17] PINMUX_MIO_PERIPH_INSEL_REGWEN_16
+ 4'b 0001, // index[ 18] PINMUX_MIO_PERIPH_INSEL_REGWEN_17
+ 4'b 0001, // index[ 19] PINMUX_MIO_PERIPH_INSEL_REGWEN_18
+ 4'b 0001, // index[ 20] PINMUX_MIO_PERIPH_INSEL_REGWEN_19
+ 4'b 0001, // index[ 21] PINMUX_MIO_PERIPH_INSEL_REGWEN_20
+ 4'b 0001, // index[ 22] PINMUX_MIO_PERIPH_INSEL_REGWEN_21
+ 4'b 0001, // index[ 23] PINMUX_MIO_PERIPH_INSEL_REGWEN_22
+ 4'b 0001, // index[ 24] PINMUX_MIO_PERIPH_INSEL_REGWEN_23
+ 4'b 0001, // index[ 25] PINMUX_MIO_PERIPH_INSEL_REGWEN_24
+ 4'b 0001, // index[ 26] PINMUX_MIO_PERIPH_INSEL_REGWEN_25
+ 4'b 0001, // index[ 27] PINMUX_MIO_PERIPH_INSEL_REGWEN_26
+ 4'b 0001, // index[ 28] PINMUX_MIO_PERIPH_INSEL_REGWEN_27
+ 4'b 0001, // index[ 29] PINMUX_MIO_PERIPH_INSEL_REGWEN_28
+ 4'b 0001, // index[ 30] PINMUX_MIO_PERIPH_INSEL_REGWEN_29
+ 4'b 0001, // index[ 31] PINMUX_MIO_PERIPH_INSEL_REGWEN_30
+ 4'b 0001, // index[ 32] PINMUX_MIO_PERIPH_INSEL_REGWEN_31
+ 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_REGWEN_32
+ 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_REGWEN_33
+ 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_REGWEN_34
+ 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_REGWEN_35
+ 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_REGWEN_36
+ 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_REGWEN_37
+ 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_REGWEN_38
+ 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_REGWEN_39
+ 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_REGWEN_40
+ 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_REGWEN_41
+ 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_REGWEN_42
+ 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_REGWEN_43
+ 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_REGWEN_44
+ 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_REGWEN_45
+ 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_REGWEN_46
+ 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_REGWEN_47
+ 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_REGWEN_48
+ 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_REGWEN_49
+ 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_REGWEN_50
+ 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_REGWEN_51
+ 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_REGWEN_52
+ 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_REGWEN_53
+ 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54
+ 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_REGWEN_55
+ 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_REGWEN_56
+ 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_REGWEN_57
+ 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_REGWEN_58
+ 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_REGWEN_59
+ 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_REGWEN_60
+ 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_REGWEN_61
+ 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_REGWEN_62
+ 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_REGWEN_63
+ 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_REGWEN_64
+ 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_REGWEN_65
+ 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_REGWEN_66
+ 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_REGWEN_67
+ 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_REGWEN_68
+ 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_REGWEN_69
+ 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_REGWEN_70
+ 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_REGWEN_71
+ 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_REGWEN_72
+ 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_REGWEN_73
+ 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_REGWEN_74
+ 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_REGWEN_75
+ 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_0
+ 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_1
+ 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_2
+ 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_3
+ 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_4
+ 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_5
+ 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_6
+ 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_7
+ 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_8
+ 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_9
+ 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_10
+ 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_11
+ 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_12
+ 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_13
+ 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_14
+ 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_15
+ 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_16
+ 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_17
+ 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_18
+ 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_19
+ 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_20
+ 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_21
+ 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_22
+ 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_23
+ 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_24
+ 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_25
+ 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_26
+ 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_27
+ 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_28
+ 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_29
+ 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_30
+ 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_31
+ 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_32
+ 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_33
+ 4'b 0001, // index[111] PINMUX_MIO_PERIPH_INSEL_34
+ 4'b 0001, // index[112] PINMUX_MIO_PERIPH_INSEL_35
+ 4'b 0001, // index[113] PINMUX_MIO_PERIPH_INSEL_36
+ 4'b 0001, // index[114] PINMUX_MIO_PERIPH_INSEL_37
+ 4'b 0001, // index[115] PINMUX_MIO_PERIPH_INSEL_38
+ 4'b 0001, // index[116] PINMUX_MIO_PERIPH_INSEL_39
+ 4'b 0001, // index[117] PINMUX_MIO_PERIPH_INSEL_40
+ 4'b 0001, // index[118] PINMUX_MIO_PERIPH_INSEL_41
+ 4'b 0001, // index[119] PINMUX_MIO_PERIPH_INSEL_42
+ 4'b 0001, // index[120] PINMUX_MIO_PERIPH_INSEL_43
+ 4'b 0001, // index[121] PINMUX_MIO_PERIPH_INSEL_44
+ 4'b 0001, // index[122] PINMUX_MIO_PERIPH_INSEL_45
+ 4'b 0001, // index[123] PINMUX_MIO_PERIPH_INSEL_46
+ 4'b 0001, // index[124] PINMUX_MIO_PERIPH_INSEL_47
+ 4'b 0001, // index[125] PINMUX_MIO_PERIPH_INSEL_48
+ 4'b 0001, // index[126] PINMUX_MIO_PERIPH_INSEL_49
+ 4'b 0001, // index[127] PINMUX_MIO_PERIPH_INSEL_50
+ 4'b 0001, // index[128] PINMUX_MIO_PERIPH_INSEL_51
+ 4'b 0001, // index[129] PINMUX_MIO_PERIPH_INSEL_52
+ 4'b 0001, // index[130] PINMUX_MIO_PERIPH_INSEL_53
+ 4'b 0001, // index[131] PINMUX_MIO_PERIPH_INSEL_54
+ 4'b 0001, // index[132] PINMUX_MIO_PERIPH_INSEL_55
+ 4'b 0001, // index[133] PINMUX_MIO_PERIPH_INSEL_56
+ 4'b 0001, // index[134] PINMUX_MIO_PERIPH_INSEL_57
+ 4'b 0001, // index[135] PINMUX_MIO_PERIPH_INSEL_58
+ 4'b 0001, // index[136] PINMUX_MIO_PERIPH_INSEL_59
+ 4'b 0001, // index[137] PINMUX_MIO_PERIPH_INSEL_60
+ 4'b 0001, // index[138] PINMUX_MIO_PERIPH_INSEL_61
+ 4'b 0001, // index[139] PINMUX_MIO_PERIPH_INSEL_62
+ 4'b 0001, // index[140] PINMUX_MIO_PERIPH_INSEL_63
+ 4'b 0001, // index[141] PINMUX_MIO_PERIPH_INSEL_64
+ 4'b 0001, // index[142] PINMUX_MIO_PERIPH_INSEL_65
+ 4'b 0001, // index[143] PINMUX_MIO_PERIPH_INSEL_66
+ 4'b 0001, // index[144] PINMUX_MIO_PERIPH_INSEL_67
+ 4'b 0001, // index[145] PINMUX_MIO_PERIPH_INSEL_68
+ 4'b 0001, // index[146] PINMUX_MIO_PERIPH_INSEL_69
+ 4'b 0001, // index[147] PINMUX_MIO_PERIPH_INSEL_70
+ 4'b 0001, // index[148] PINMUX_MIO_PERIPH_INSEL_71
+ 4'b 0001, // index[149] PINMUX_MIO_PERIPH_INSEL_72
+ 4'b 0001, // index[150] PINMUX_MIO_PERIPH_INSEL_73
+ 4'b 0001, // index[151] PINMUX_MIO_PERIPH_INSEL_74
+ 4'b 0001, // index[152] PINMUX_MIO_PERIPH_INSEL_75
+ 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_0
+ 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_1
+ 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_2
+ 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_3
+ 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_4
+ 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_REGWEN_5
+ 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_REGWEN_6
+ 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_REGWEN_7
+ 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_REGWEN_8
+ 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_REGWEN_9
+ 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_REGWEN_10
+ 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_REGWEN_11
+ 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_REGWEN_12
+ 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_REGWEN_13
+ 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_REGWEN_14
+ 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_REGWEN_15
+ 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_REGWEN_16
+ 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_REGWEN_17
+ 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_REGWEN_18
+ 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_REGWEN_19
+ 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_REGWEN_20
+ 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_REGWEN_21
+ 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_REGWEN_22
+ 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_REGWEN_23
+ 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_REGWEN_24
+ 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_REGWEN_25
+ 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_REGWEN_26
+ 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_REGWEN_27
+ 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_REGWEN_28
+ 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_REGWEN_29
+ 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_REGWEN_30
+ 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_REGWEN_31
+ 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_REGWEN_32
+ 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_REGWEN_33
+ 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_REGWEN_34
+ 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_REGWEN_35
+ 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_REGWEN_36
+ 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_REGWEN_37
+ 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_REGWEN_38
+ 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_REGWEN_39
+ 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_REGWEN_40
+ 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_REGWEN_41
+ 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_REGWEN_42
+ 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_REGWEN_43
+ 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_REGWEN_44
+ 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_REGWEN_45
+ 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_REGWEN_46
+ 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_REGWEN_47
+ 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_REGWEN_48
+ 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_REGWEN_49
+ 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_REGWEN_50
+ 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_REGWEN_51
+ 4'b 0001, // index[205] PINMUX_MIO_OUTSEL_REGWEN_52
+ 4'b 0001, // index[206] PINMUX_MIO_OUTSEL_0
+ 4'b 0001, // index[207] PINMUX_MIO_OUTSEL_1
+ 4'b 0001, // index[208] PINMUX_MIO_OUTSEL_2
+ 4'b 0001, // index[209] PINMUX_MIO_OUTSEL_3
+ 4'b 0001, // index[210] PINMUX_MIO_OUTSEL_4
+ 4'b 0001, // index[211] PINMUX_MIO_OUTSEL_5
+ 4'b 0001, // index[212] PINMUX_MIO_OUTSEL_6
+ 4'b 0001, // index[213] PINMUX_MIO_OUTSEL_7
+ 4'b 0001, // index[214] PINMUX_MIO_OUTSEL_8
+ 4'b 0001, // index[215] PINMUX_MIO_OUTSEL_9
+ 4'b 0001, // index[216] PINMUX_MIO_OUTSEL_10
+ 4'b 0001, // index[217] PINMUX_MIO_OUTSEL_11
+ 4'b 0001, // index[218] PINMUX_MIO_OUTSEL_12
+ 4'b 0001, // index[219] PINMUX_MIO_OUTSEL_13
+ 4'b 0001, // index[220] PINMUX_MIO_OUTSEL_14
+ 4'b 0001, // index[221] PINMUX_MIO_OUTSEL_15
+ 4'b 0001, // index[222] PINMUX_MIO_OUTSEL_16
+ 4'b 0001, // index[223] PINMUX_MIO_OUTSEL_17
+ 4'b 0001, // index[224] PINMUX_MIO_OUTSEL_18
+ 4'b 0001, // index[225] PINMUX_MIO_OUTSEL_19
+ 4'b 0001, // index[226] PINMUX_MIO_OUTSEL_20
+ 4'b 0001, // index[227] PINMUX_MIO_OUTSEL_21
+ 4'b 0001, // index[228] PINMUX_MIO_OUTSEL_22
+ 4'b 0001, // index[229] PINMUX_MIO_OUTSEL_23
+ 4'b 0001, // index[230] PINMUX_MIO_OUTSEL_24
+ 4'b 0001, // index[231] PINMUX_MIO_OUTSEL_25
+ 4'b 0001, // index[232] PINMUX_MIO_OUTSEL_26
+ 4'b 0001, // index[233] PINMUX_MIO_OUTSEL_27
+ 4'b 0001, // index[234] PINMUX_MIO_OUTSEL_28
+ 4'b 0001, // index[235] PINMUX_MIO_OUTSEL_29
+ 4'b 0001, // index[236] PINMUX_MIO_OUTSEL_30
+ 4'b 0001, // index[237] PINMUX_MIO_OUTSEL_31
+ 4'b 0001, // index[238] PINMUX_MIO_OUTSEL_32
+ 4'b 0001, // index[239] PINMUX_MIO_OUTSEL_33
+ 4'b 0001, // index[240] PINMUX_MIO_OUTSEL_34
+ 4'b 0001, // index[241] PINMUX_MIO_OUTSEL_35
+ 4'b 0001, // index[242] PINMUX_MIO_OUTSEL_36
+ 4'b 0001, // index[243] PINMUX_MIO_OUTSEL_37
+ 4'b 0001, // index[244] PINMUX_MIO_OUTSEL_38
+ 4'b 0001, // index[245] PINMUX_MIO_OUTSEL_39
+ 4'b 0001, // index[246] PINMUX_MIO_OUTSEL_40
+ 4'b 0001, // index[247] PINMUX_MIO_OUTSEL_41
+ 4'b 0001, // index[248] PINMUX_MIO_OUTSEL_42
+ 4'b 0001, // index[249] PINMUX_MIO_OUTSEL_43
+ 4'b 0001, // index[250] PINMUX_MIO_OUTSEL_44
+ 4'b 0001, // index[251] PINMUX_MIO_OUTSEL_45
+ 4'b 0001, // index[252] PINMUX_MIO_OUTSEL_46
+ 4'b 0001, // index[253] PINMUX_MIO_OUTSEL_47
+ 4'b 0001, // index[254] PINMUX_MIO_OUTSEL_48
+ 4'b 0001, // index[255] PINMUX_MIO_OUTSEL_49
+ 4'b 0001, // index[256] PINMUX_MIO_OUTSEL_50
+ 4'b 0001, // index[257] PINMUX_MIO_OUTSEL_51
+ 4'b 0001, // index[258] PINMUX_MIO_OUTSEL_52
+ 4'b 0001, // index[259] PINMUX_MIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[260] PINMUX_MIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[261] PINMUX_MIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[262] PINMUX_MIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[263] PINMUX_MIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[264] PINMUX_MIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[265] PINMUX_MIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[266] PINMUX_MIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[267] PINMUX_MIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[268] PINMUX_MIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[269] PINMUX_MIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[270] PINMUX_MIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[271] PINMUX_MIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[272] PINMUX_MIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[273] PINMUX_MIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[274] PINMUX_MIO_PAD_ATTR_REGWEN_15
+ 4'b 0001, // index[275] PINMUX_MIO_PAD_ATTR_REGWEN_16
+ 4'b 0001, // index[276] PINMUX_MIO_PAD_ATTR_REGWEN_17
+ 4'b 0001, // index[277] PINMUX_MIO_PAD_ATTR_REGWEN_18
+ 4'b 0001, // index[278] PINMUX_MIO_PAD_ATTR_REGWEN_19
+ 4'b 0001, // index[279] PINMUX_MIO_PAD_ATTR_REGWEN_20
+ 4'b 0001, // index[280] PINMUX_MIO_PAD_ATTR_REGWEN_21
+ 4'b 0001, // index[281] PINMUX_MIO_PAD_ATTR_REGWEN_22
+ 4'b 0001, // index[282] PINMUX_MIO_PAD_ATTR_REGWEN_23
+ 4'b 0001, // index[283] PINMUX_MIO_PAD_ATTR_REGWEN_24
+ 4'b 0001, // index[284] PINMUX_MIO_PAD_ATTR_REGWEN_25
+ 4'b 0001, // index[285] PINMUX_MIO_PAD_ATTR_REGWEN_26
+ 4'b 0001, // index[286] PINMUX_MIO_PAD_ATTR_REGWEN_27
+ 4'b 0001, // index[287] PINMUX_MIO_PAD_ATTR_REGWEN_28
+ 4'b 0001, // index[288] PINMUX_MIO_PAD_ATTR_REGWEN_29
+ 4'b 0001, // index[289] PINMUX_MIO_PAD_ATTR_REGWEN_30
+ 4'b 0001, // index[290] PINMUX_MIO_PAD_ATTR_REGWEN_31
+ 4'b 0001, // index[291] PINMUX_MIO_PAD_ATTR_REGWEN_32
+ 4'b 0001, // index[292] PINMUX_MIO_PAD_ATTR_REGWEN_33
+ 4'b 0001, // index[293] PINMUX_MIO_PAD_ATTR_REGWEN_34
+ 4'b 0001, // index[294] PINMUX_MIO_PAD_ATTR_REGWEN_35
+ 4'b 0001, // index[295] PINMUX_MIO_PAD_ATTR_REGWEN_36
+ 4'b 0001, // index[296] PINMUX_MIO_PAD_ATTR_REGWEN_37
+ 4'b 0001, // index[297] PINMUX_MIO_PAD_ATTR_REGWEN_38
+ 4'b 0001, // index[298] PINMUX_MIO_PAD_ATTR_REGWEN_39
+ 4'b 0001, // index[299] PINMUX_MIO_PAD_ATTR_REGWEN_40
+ 4'b 0001, // index[300] PINMUX_MIO_PAD_ATTR_REGWEN_41
+ 4'b 0001, // index[301] PINMUX_MIO_PAD_ATTR_REGWEN_42
+ 4'b 0001, // index[302] PINMUX_MIO_PAD_ATTR_REGWEN_43
+ 4'b 0001, // index[303] PINMUX_MIO_PAD_ATTR_REGWEN_44
+ 4'b 0001, // index[304] PINMUX_MIO_PAD_ATTR_REGWEN_45
+ 4'b 0001, // index[305] PINMUX_MIO_PAD_ATTR_REGWEN_46
+ 4'b 0001, // index[306] PINMUX_MIO_PAD_ATTR_REGWEN_47
+ 4'b 0001, // index[307] PINMUX_MIO_PAD_ATTR_REGWEN_48
+ 4'b 0001, // index[308] PINMUX_MIO_PAD_ATTR_REGWEN_49
+ 4'b 0001, // index[309] PINMUX_MIO_PAD_ATTR_REGWEN_50
+ 4'b 0001, // index[310] PINMUX_MIO_PAD_ATTR_REGWEN_51
+ 4'b 0001, // index[311] PINMUX_MIO_PAD_ATTR_REGWEN_52
+ 4'b 0111, // index[312] PINMUX_MIO_PAD_ATTR_0
+ 4'b 0111, // index[313] PINMUX_MIO_PAD_ATTR_1
+ 4'b 0111, // index[314] PINMUX_MIO_PAD_ATTR_2
+ 4'b 0111, // index[315] PINMUX_MIO_PAD_ATTR_3
+ 4'b 0111, // index[316] PINMUX_MIO_PAD_ATTR_4
+ 4'b 0111, // index[317] PINMUX_MIO_PAD_ATTR_5
+ 4'b 0111, // index[318] PINMUX_MIO_PAD_ATTR_6
+ 4'b 0111, // index[319] PINMUX_MIO_PAD_ATTR_7
+ 4'b 0111, // index[320] PINMUX_MIO_PAD_ATTR_8
+ 4'b 0111, // index[321] PINMUX_MIO_PAD_ATTR_9
+ 4'b 0111, // index[322] PINMUX_MIO_PAD_ATTR_10
+ 4'b 0111, // index[323] PINMUX_MIO_PAD_ATTR_11
+ 4'b 0111, // index[324] PINMUX_MIO_PAD_ATTR_12
+ 4'b 0111, // index[325] PINMUX_MIO_PAD_ATTR_13
+ 4'b 0111, // index[326] PINMUX_MIO_PAD_ATTR_14
+ 4'b 0111, // index[327] PINMUX_MIO_PAD_ATTR_15
+ 4'b 0111, // index[328] PINMUX_MIO_PAD_ATTR_16
+ 4'b 0111, // index[329] PINMUX_MIO_PAD_ATTR_17
+ 4'b 0111, // index[330] PINMUX_MIO_PAD_ATTR_18
+ 4'b 0111, // index[331] PINMUX_MIO_PAD_ATTR_19
+ 4'b 0111, // index[332] PINMUX_MIO_PAD_ATTR_20
+ 4'b 0111, // index[333] PINMUX_MIO_PAD_ATTR_21
+ 4'b 0111, // index[334] PINMUX_MIO_PAD_ATTR_22
+ 4'b 0111, // index[335] PINMUX_MIO_PAD_ATTR_23
+ 4'b 0111, // index[336] PINMUX_MIO_PAD_ATTR_24
+ 4'b 0111, // index[337] PINMUX_MIO_PAD_ATTR_25
+ 4'b 0111, // index[338] PINMUX_MIO_PAD_ATTR_26
+ 4'b 0111, // index[339] PINMUX_MIO_PAD_ATTR_27
+ 4'b 0111, // index[340] PINMUX_MIO_PAD_ATTR_28
+ 4'b 0111, // index[341] PINMUX_MIO_PAD_ATTR_29
+ 4'b 0111, // index[342] PINMUX_MIO_PAD_ATTR_30
+ 4'b 0111, // index[343] PINMUX_MIO_PAD_ATTR_31
+ 4'b 0111, // index[344] PINMUX_MIO_PAD_ATTR_32
+ 4'b 0111, // index[345] PINMUX_MIO_PAD_ATTR_33
+ 4'b 0111, // index[346] PINMUX_MIO_PAD_ATTR_34
+ 4'b 0111, // index[347] PINMUX_MIO_PAD_ATTR_35
+ 4'b 0111, // index[348] PINMUX_MIO_PAD_ATTR_36
+ 4'b 0111, // index[349] PINMUX_MIO_PAD_ATTR_37
+ 4'b 0111, // index[350] PINMUX_MIO_PAD_ATTR_38
+ 4'b 0111, // index[351] PINMUX_MIO_PAD_ATTR_39
+ 4'b 0111, // index[352] PINMUX_MIO_PAD_ATTR_40
+ 4'b 0111, // index[353] PINMUX_MIO_PAD_ATTR_41
+ 4'b 0111, // index[354] PINMUX_MIO_PAD_ATTR_42
+ 4'b 0111, // index[355] PINMUX_MIO_PAD_ATTR_43
+ 4'b 0111, // index[356] PINMUX_MIO_PAD_ATTR_44
+ 4'b 0111, // index[357] PINMUX_MIO_PAD_ATTR_45
+ 4'b 0111, // index[358] PINMUX_MIO_PAD_ATTR_46
+ 4'b 0111, // index[359] PINMUX_MIO_PAD_ATTR_47
+ 4'b 0111, // index[360] PINMUX_MIO_PAD_ATTR_48
+ 4'b 0111, // index[361] PINMUX_MIO_PAD_ATTR_49
+ 4'b 0111, // index[362] PINMUX_MIO_PAD_ATTR_50
+ 4'b 0111, // index[363] PINMUX_MIO_PAD_ATTR_51
+ 4'b 0111, // index[364] PINMUX_MIO_PAD_ATTR_52
+ 4'b 0001, // index[365] PINMUX_DIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[366] PINMUX_DIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[367] PINMUX_DIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[368] PINMUX_DIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[369] PINMUX_DIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[370] PINMUX_DIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[371] PINMUX_DIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[372] PINMUX_DIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[373] PINMUX_DIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[374] PINMUX_DIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[375] PINMUX_DIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[376] PINMUX_DIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[377] PINMUX_DIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[378] PINMUX_DIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[379] PINMUX_DIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[380] PINMUX_DIO_PAD_ATTR_REGWEN_15
+ 4'b 0111, // index[381] PINMUX_DIO_PAD_ATTR_0
+ 4'b 0111, // index[382] PINMUX_DIO_PAD_ATTR_1
+ 4'b 0111, // index[383] PINMUX_DIO_PAD_ATTR_2
+ 4'b 0111, // index[384] PINMUX_DIO_PAD_ATTR_3
+ 4'b 0111, // index[385] PINMUX_DIO_PAD_ATTR_4
+ 4'b 0111, // index[386] PINMUX_DIO_PAD_ATTR_5
+ 4'b 0111, // index[387] PINMUX_DIO_PAD_ATTR_6
+ 4'b 0111, // index[388] PINMUX_DIO_PAD_ATTR_7
+ 4'b 0111, // index[389] PINMUX_DIO_PAD_ATTR_8
+ 4'b 0111, // index[390] PINMUX_DIO_PAD_ATTR_9
+ 4'b 0111, // index[391] PINMUX_DIO_PAD_ATTR_10
+ 4'b 0111, // index[392] PINMUX_DIO_PAD_ATTR_11
+ 4'b 0111, // index[393] PINMUX_DIO_PAD_ATTR_12
+ 4'b 0111, // index[394] PINMUX_DIO_PAD_ATTR_13
+ 4'b 0111, // index[395] PINMUX_DIO_PAD_ATTR_14
+ 4'b 0111, // index[396] PINMUX_DIO_PAD_ATTR_15
+ 4'b 1111, // index[397] PINMUX_MIO_PAD_SLEEP_STATUS_0
+ 4'b 0111, // index[398] PINMUX_MIO_PAD_SLEEP_STATUS_1
+ 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_REGWEN_16
+ 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_REGWEN_17
+ 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_REGWEN_18
+ 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_REGWEN_19
+ 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_REGWEN_20
+ 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_REGWEN_21
+ 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_REGWEN_22
+ 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_REGWEN_23
+ 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_REGWEN_24
+ 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_REGWEN_25
+ 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_REGWEN_26
+ 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_REGWEN_27
+ 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_REGWEN_28
+ 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_REGWEN_29
+ 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_REGWEN_30
+ 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_REGWEN_31
+ 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_REGWEN_32
+ 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_REGWEN_33
+ 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_REGWEN_34
+ 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_REGWEN_35
+ 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_REGWEN_36
+ 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_REGWEN_37
+ 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_REGWEN_38
+ 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_REGWEN_39
+ 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_REGWEN_40
+ 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_REGWEN_41
+ 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_REGWEN_42
+ 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_REGWEN_43
+ 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_REGWEN_44
+ 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_REGWEN_45
+ 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_REGWEN_46
+ 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_REGWEN_47
+ 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_REGWEN_48
+ 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_REGWEN_49
+ 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_REGWEN_50
+ 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_REGWEN_51
+ 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_REGWEN_52
+ 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_EN_16
+ 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_EN_17
+ 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_EN_18
+ 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_EN_19
+ 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_EN_20
+ 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_EN_21
+ 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_EN_22
+ 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_EN_23
+ 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_EN_24
+ 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_EN_25
+ 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_EN_26
+ 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_EN_27
+ 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_EN_28
+ 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_EN_29
+ 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_EN_30
+ 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_EN_31
+ 4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_EN_32
+ 4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_EN_33
+ 4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_EN_34
+ 4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_EN_35
+ 4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_EN_36
+ 4'b 0001, // index[489] PINMUX_MIO_PAD_SLEEP_EN_37
+ 4'b 0001, // index[490] PINMUX_MIO_PAD_SLEEP_EN_38
+ 4'b 0001, // index[491] PINMUX_MIO_PAD_SLEEP_EN_39
+ 4'b 0001, // index[492] PINMUX_MIO_PAD_SLEEP_EN_40
+ 4'b 0001, // index[493] PINMUX_MIO_PAD_SLEEP_EN_41
+ 4'b 0001, // index[494] PINMUX_MIO_PAD_SLEEP_EN_42
+ 4'b 0001, // index[495] PINMUX_MIO_PAD_SLEEP_EN_43
+ 4'b 0001, // index[496] PINMUX_MIO_PAD_SLEEP_EN_44
+ 4'b 0001, // index[497] PINMUX_MIO_PAD_SLEEP_EN_45
+ 4'b 0001, // index[498] PINMUX_MIO_PAD_SLEEP_EN_46
+ 4'b 0001, // index[499] PINMUX_MIO_PAD_SLEEP_EN_47
+ 4'b 0001, // index[500] PINMUX_MIO_PAD_SLEEP_EN_48
+ 4'b 0001, // index[501] PINMUX_MIO_PAD_SLEEP_EN_49
+ 4'b 0001, // index[502] PINMUX_MIO_PAD_SLEEP_EN_50
+ 4'b 0001, // index[503] PINMUX_MIO_PAD_SLEEP_EN_51
+ 4'b 0001, // index[504] PINMUX_MIO_PAD_SLEEP_EN_52
+ 4'b 0001, // index[505] PINMUX_MIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[506] PINMUX_MIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[507] PINMUX_MIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[508] PINMUX_MIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[509] PINMUX_MIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[510] PINMUX_MIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[511] PINMUX_MIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[512] PINMUX_MIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[513] PINMUX_MIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[514] PINMUX_MIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[515] PINMUX_MIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[516] PINMUX_MIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[517] PINMUX_MIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[518] PINMUX_MIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[519] PINMUX_MIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[520] PINMUX_MIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[521] PINMUX_MIO_PAD_SLEEP_MODE_16
+ 4'b 0001, // index[522] PINMUX_MIO_PAD_SLEEP_MODE_17
+ 4'b 0001, // index[523] PINMUX_MIO_PAD_SLEEP_MODE_18
+ 4'b 0001, // index[524] PINMUX_MIO_PAD_SLEEP_MODE_19
+ 4'b 0001, // index[525] PINMUX_MIO_PAD_SLEEP_MODE_20
+ 4'b 0001, // index[526] PINMUX_MIO_PAD_SLEEP_MODE_21
+ 4'b 0001, // index[527] PINMUX_MIO_PAD_SLEEP_MODE_22
+ 4'b 0001, // index[528] PINMUX_MIO_PAD_SLEEP_MODE_23
+ 4'b 0001, // index[529] PINMUX_MIO_PAD_SLEEP_MODE_24
+ 4'b 0001, // index[530] PINMUX_MIO_PAD_SLEEP_MODE_25
+ 4'b 0001, // index[531] PINMUX_MIO_PAD_SLEEP_MODE_26
+ 4'b 0001, // index[532] PINMUX_MIO_PAD_SLEEP_MODE_27
+ 4'b 0001, // index[533] PINMUX_MIO_PAD_SLEEP_MODE_28
+ 4'b 0001, // index[534] PINMUX_MIO_PAD_SLEEP_MODE_29
+ 4'b 0001, // index[535] PINMUX_MIO_PAD_SLEEP_MODE_30
+ 4'b 0001, // index[536] PINMUX_MIO_PAD_SLEEP_MODE_31
+ 4'b 0001, // index[537] PINMUX_MIO_PAD_SLEEP_MODE_32
+ 4'b 0001, // index[538] PINMUX_MIO_PAD_SLEEP_MODE_33
+ 4'b 0001, // index[539] PINMUX_MIO_PAD_SLEEP_MODE_34
+ 4'b 0001, // index[540] PINMUX_MIO_PAD_SLEEP_MODE_35
+ 4'b 0001, // index[541] PINMUX_MIO_PAD_SLEEP_MODE_36
+ 4'b 0001, // index[542] PINMUX_MIO_PAD_SLEEP_MODE_37
+ 4'b 0001, // index[543] PINMUX_MIO_PAD_SLEEP_MODE_38
+ 4'b 0001, // index[544] PINMUX_MIO_PAD_SLEEP_MODE_39
+ 4'b 0001, // index[545] PINMUX_MIO_PAD_SLEEP_MODE_40
+ 4'b 0001, // index[546] PINMUX_MIO_PAD_SLEEP_MODE_41
+ 4'b 0001, // index[547] PINMUX_MIO_PAD_SLEEP_MODE_42
+ 4'b 0001, // index[548] PINMUX_MIO_PAD_SLEEP_MODE_43
+ 4'b 0001, // index[549] PINMUX_MIO_PAD_SLEEP_MODE_44
+ 4'b 0001, // index[550] PINMUX_MIO_PAD_SLEEP_MODE_45
+ 4'b 0001, // index[551] PINMUX_MIO_PAD_SLEEP_MODE_46
+ 4'b 0001, // index[552] PINMUX_MIO_PAD_SLEEP_MODE_47
+ 4'b 0001, // index[553] PINMUX_MIO_PAD_SLEEP_MODE_48
+ 4'b 0001, // index[554] PINMUX_MIO_PAD_SLEEP_MODE_49
+ 4'b 0001, // index[555] PINMUX_MIO_PAD_SLEEP_MODE_50
+ 4'b 0001, // index[556] PINMUX_MIO_PAD_SLEEP_MODE_51
+ 4'b 0001, // index[557] PINMUX_MIO_PAD_SLEEP_MODE_52
+ 4'b 0011, // index[558] PINMUX_DIO_PAD_SLEEP_STATUS
+ 4'b 0001, // index[559] PINMUX_DIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[560] PINMUX_DIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[561] PINMUX_DIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[562] PINMUX_DIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[563] PINMUX_DIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[564] PINMUX_DIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[565] PINMUX_DIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[566] PINMUX_DIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[567] PINMUX_DIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[568] PINMUX_DIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[569] PINMUX_DIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[570] PINMUX_DIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[571] PINMUX_DIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[572] PINMUX_DIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[573] PINMUX_DIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[574] PINMUX_DIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[575] PINMUX_DIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[576] PINMUX_DIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[577] PINMUX_DIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[578] PINMUX_DIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[579] PINMUX_DIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[580] PINMUX_DIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[581] PINMUX_DIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[582] PINMUX_DIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[583] PINMUX_DIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[584] PINMUX_DIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[585] PINMUX_DIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[586] PINMUX_DIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[587] PINMUX_DIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[588] PINMUX_DIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[589] PINMUX_DIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[590] PINMUX_DIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[591] PINMUX_DIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[592] PINMUX_DIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[593] PINMUX_DIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[594] PINMUX_DIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[595] PINMUX_DIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[596] PINMUX_DIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[597] PINMUX_DIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[598] PINMUX_DIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[599] PINMUX_DIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[600] PINMUX_DIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[601] PINMUX_DIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[602] PINMUX_DIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[603] PINMUX_DIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[604] PINMUX_DIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[605] PINMUX_DIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[606] PINMUX_DIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[607] PINMUX_WKUP_DETECTOR_REGWEN_0
+ 4'b 0001, // index[608] PINMUX_WKUP_DETECTOR_REGWEN_1
+ 4'b 0001, // index[609] PINMUX_WKUP_DETECTOR_REGWEN_2
+ 4'b 0001, // index[610] PINMUX_WKUP_DETECTOR_REGWEN_3
+ 4'b 0001, // index[611] PINMUX_WKUP_DETECTOR_REGWEN_4
+ 4'b 0001, // index[612] PINMUX_WKUP_DETECTOR_REGWEN_5
+ 4'b 0001, // index[613] PINMUX_WKUP_DETECTOR_REGWEN_6
+ 4'b 0001, // index[614] PINMUX_WKUP_DETECTOR_REGWEN_7
+ 4'b 0001, // index[615] PINMUX_WKUP_DETECTOR_EN_0
+ 4'b 0001, // index[616] PINMUX_WKUP_DETECTOR_EN_1
+ 4'b 0001, // index[617] PINMUX_WKUP_DETECTOR_EN_2
+ 4'b 0001, // index[618] PINMUX_WKUP_DETECTOR_EN_3
+ 4'b 0001, // index[619] PINMUX_WKUP_DETECTOR_EN_4
+ 4'b 0001, // index[620] PINMUX_WKUP_DETECTOR_EN_5
+ 4'b 0001, // index[621] PINMUX_WKUP_DETECTOR_EN_6
+ 4'b 0001, // index[622] PINMUX_WKUP_DETECTOR_EN_7
+ 4'b 0001, // index[623] PINMUX_WKUP_DETECTOR_0
+ 4'b 0001, // index[624] PINMUX_WKUP_DETECTOR_1
+ 4'b 0001, // index[625] PINMUX_WKUP_DETECTOR_2
+ 4'b 0001, // index[626] PINMUX_WKUP_DETECTOR_3
+ 4'b 0001, // index[627] PINMUX_WKUP_DETECTOR_4
+ 4'b 0001, // index[628] PINMUX_WKUP_DETECTOR_5
+ 4'b 0001, // index[629] PINMUX_WKUP_DETECTOR_6
+ 4'b 0001, // index[630] PINMUX_WKUP_DETECTOR_7
+ 4'b 0001, // index[631] PINMUX_WKUP_DETECTOR_CNT_TH_0
+ 4'b 0001, // index[632] PINMUX_WKUP_DETECTOR_CNT_TH_1
+ 4'b 0001, // index[633] PINMUX_WKUP_DETECTOR_CNT_TH_2
+ 4'b 0001, // index[634] PINMUX_WKUP_DETECTOR_CNT_TH_3
+ 4'b 0001, // index[635] PINMUX_WKUP_DETECTOR_CNT_TH_4
+ 4'b 0001, // index[636] PINMUX_WKUP_DETECTOR_CNT_TH_5
+ 4'b 0001, // index[637] PINMUX_WKUP_DETECTOR_CNT_TH_6
+ 4'b 0001, // index[638] PINMUX_WKUP_DETECTOR_CNT_TH_7
+ 4'b 0001, // index[639] PINMUX_WKUP_DETECTOR_PADSEL_0
+ 4'b 0001, // index[640] PINMUX_WKUP_DETECTOR_PADSEL_1
+ 4'b 0001, // index[641] PINMUX_WKUP_DETECTOR_PADSEL_2
+ 4'b 0001, // index[642] PINMUX_WKUP_DETECTOR_PADSEL_3
+ 4'b 0001, // index[643] PINMUX_WKUP_DETECTOR_PADSEL_4
+ 4'b 0001, // index[644] PINMUX_WKUP_DETECTOR_PADSEL_5
+ 4'b 0001, // index[645] PINMUX_WKUP_DETECTOR_PADSEL_6
+ 4'b 0001, // index[646] PINMUX_WKUP_DETECTOR_PADSEL_7
+ 4'b 0001 // index[647] PINMUX_WKUP_CAUSE
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
new file mode 100644
index 0000000..71025d1
--- /dev/null
+++ b/hw/top_sencha/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -0,0 +1,42941 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module pinmux_reg_top (
+ input clk_i,
+ input rst_ni,
+ input clk_aon_i,
+ input rst_aon_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
+ input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import pinmux_reg_pkg::* ;
+
+ localparam int AW = 12;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [647:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(648)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic alert_test_we;
+ logic alert_test_wd;
+ logic mio_periph_insel_regwen_0_we;
+ logic mio_periph_insel_regwen_0_qs;
+ logic mio_periph_insel_regwen_0_wd;
+ logic mio_periph_insel_regwen_1_we;
+ logic mio_periph_insel_regwen_1_qs;
+ logic mio_periph_insel_regwen_1_wd;
+ logic mio_periph_insel_regwen_2_we;
+ logic mio_periph_insel_regwen_2_qs;
+ logic mio_periph_insel_regwen_2_wd;
+ logic mio_periph_insel_regwen_3_we;
+ logic mio_periph_insel_regwen_3_qs;
+ logic mio_periph_insel_regwen_3_wd;
+ logic mio_periph_insel_regwen_4_we;
+ logic mio_periph_insel_regwen_4_qs;
+ logic mio_periph_insel_regwen_4_wd;
+ logic mio_periph_insel_regwen_5_we;
+ logic mio_periph_insel_regwen_5_qs;
+ logic mio_periph_insel_regwen_5_wd;
+ logic mio_periph_insel_regwen_6_we;
+ logic mio_periph_insel_regwen_6_qs;
+ logic mio_periph_insel_regwen_6_wd;
+ logic mio_periph_insel_regwen_7_we;
+ logic mio_periph_insel_regwen_7_qs;
+ logic mio_periph_insel_regwen_7_wd;
+ logic mio_periph_insel_regwen_8_we;
+ logic mio_periph_insel_regwen_8_qs;
+ logic mio_periph_insel_regwen_8_wd;
+ logic mio_periph_insel_regwen_9_we;
+ logic mio_periph_insel_regwen_9_qs;
+ logic mio_periph_insel_regwen_9_wd;
+ logic mio_periph_insel_regwen_10_we;
+ logic mio_periph_insel_regwen_10_qs;
+ logic mio_periph_insel_regwen_10_wd;
+ logic mio_periph_insel_regwen_11_we;
+ logic mio_periph_insel_regwen_11_qs;
+ logic mio_periph_insel_regwen_11_wd;
+ logic mio_periph_insel_regwen_12_we;
+ logic mio_periph_insel_regwen_12_qs;
+ logic mio_periph_insel_regwen_12_wd;
+ logic mio_periph_insel_regwen_13_we;
+ logic mio_periph_insel_regwen_13_qs;
+ logic mio_periph_insel_regwen_13_wd;
+ logic mio_periph_insel_regwen_14_we;
+ logic mio_periph_insel_regwen_14_qs;
+ logic mio_periph_insel_regwen_14_wd;
+ logic mio_periph_insel_regwen_15_we;
+ logic mio_periph_insel_regwen_15_qs;
+ logic mio_periph_insel_regwen_15_wd;
+ logic mio_periph_insel_regwen_16_we;
+ logic mio_periph_insel_regwen_16_qs;
+ logic mio_periph_insel_regwen_16_wd;
+ logic mio_periph_insel_regwen_17_we;
+ logic mio_periph_insel_regwen_17_qs;
+ logic mio_periph_insel_regwen_17_wd;
+ logic mio_periph_insel_regwen_18_we;
+ logic mio_periph_insel_regwen_18_qs;
+ logic mio_periph_insel_regwen_18_wd;
+ logic mio_periph_insel_regwen_19_we;
+ logic mio_periph_insel_regwen_19_qs;
+ logic mio_periph_insel_regwen_19_wd;
+ logic mio_periph_insel_regwen_20_we;
+ logic mio_periph_insel_regwen_20_qs;
+ logic mio_periph_insel_regwen_20_wd;
+ logic mio_periph_insel_regwen_21_we;
+ logic mio_periph_insel_regwen_21_qs;
+ logic mio_periph_insel_regwen_21_wd;
+ logic mio_periph_insel_regwen_22_we;
+ logic mio_periph_insel_regwen_22_qs;
+ logic mio_periph_insel_regwen_22_wd;
+ logic mio_periph_insel_regwen_23_we;
+ logic mio_periph_insel_regwen_23_qs;
+ logic mio_periph_insel_regwen_23_wd;
+ logic mio_periph_insel_regwen_24_we;
+ logic mio_periph_insel_regwen_24_qs;
+ logic mio_periph_insel_regwen_24_wd;
+ logic mio_periph_insel_regwen_25_we;
+ logic mio_periph_insel_regwen_25_qs;
+ logic mio_periph_insel_regwen_25_wd;
+ logic mio_periph_insel_regwen_26_we;
+ logic mio_periph_insel_regwen_26_qs;
+ logic mio_periph_insel_regwen_26_wd;
+ logic mio_periph_insel_regwen_27_we;
+ logic mio_periph_insel_regwen_27_qs;
+ logic mio_periph_insel_regwen_27_wd;
+ logic mio_periph_insel_regwen_28_we;
+ logic mio_periph_insel_regwen_28_qs;
+ logic mio_periph_insel_regwen_28_wd;
+ logic mio_periph_insel_regwen_29_we;
+ logic mio_periph_insel_regwen_29_qs;
+ logic mio_periph_insel_regwen_29_wd;
+ logic mio_periph_insel_regwen_30_we;
+ logic mio_periph_insel_regwen_30_qs;
+ logic mio_periph_insel_regwen_30_wd;
+ logic mio_periph_insel_regwen_31_we;
+ logic mio_periph_insel_regwen_31_qs;
+ logic mio_periph_insel_regwen_31_wd;
+ logic mio_periph_insel_regwen_32_we;
+ logic mio_periph_insel_regwen_32_qs;
+ logic mio_periph_insel_regwen_32_wd;
+ logic mio_periph_insel_regwen_33_we;
+ logic mio_periph_insel_regwen_33_qs;
+ logic mio_periph_insel_regwen_33_wd;
+ logic mio_periph_insel_regwen_34_we;
+ logic mio_periph_insel_regwen_34_qs;
+ logic mio_periph_insel_regwen_34_wd;
+ logic mio_periph_insel_regwen_35_we;
+ logic mio_periph_insel_regwen_35_qs;
+ logic mio_periph_insel_regwen_35_wd;
+ logic mio_periph_insel_regwen_36_we;
+ logic mio_periph_insel_regwen_36_qs;
+ logic mio_periph_insel_regwen_36_wd;
+ logic mio_periph_insel_regwen_37_we;
+ logic mio_periph_insel_regwen_37_qs;
+ logic mio_periph_insel_regwen_37_wd;
+ logic mio_periph_insel_regwen_38_we;
+ logic mio_periph_insel_regwen_38_qs;
+ logic mio_periph_insel_regwen_38_wd;
+ logic mio_periph_insel_regwen_39_we;
+ logic mio_periph_insel_regwen_39_qs;
+ logic mio_periph_insel_regwen_39_wd;
+ logic mio_periph_insel_regwen_40_we;
+ logic mio_periph_insel_regwen_40_qs;
+ logic mio_periph_insel_regwen_40_wd;
+ logic mio_periph_insel_regwen_41_we;
+ logic mio_periph_insel_regwen_41_qs;
+ logic mio_periph_insel_regwen_41_wd;
+ logic mio_periph_insel_regwen_42_we;
+ logic mio_periph_insel_regwen_42_qs;
+ logic mio_periph_insel_regwen_42_wd;
+ logic mio_periph_insel_regwen_43_we;
+ logic mio_periph_insel_regwen_43_qs;
+ logic mio_periph_insel_regwen_43_wd;
+ logic mio_periph_insel_regwen_44_we;
+ logic mio_periph_insel_regwen_44_qs;
+ logic mio_periph_insel_regwen_44_wd;
+ logic mio_periph_insel_regwen_45_we;
+ logic mio_periph_insel_regwen_45_qs;
+ logic mio_periph_insel_regwen_45_wd;
+ logic mio_periph_insel_regwen_46_we;
+ logic mio_periph_insel_regwen_46_qs;
+ logic mio_periph_insel_regwen_46_wd;
+ logic mio_periph_insel_regwen_47_we;
+ logic mio_periph_insel_regwen_47_qs;
+ logic mio_periph_insel_regwen_47_wd;
+ logic mio_periph_insel_regwen_48_we;
+ logic mio_periph_insel_regwen_48_qs;
+ logic mio_periph_insel_regwen_48_wd;
+ logic mio_periph_insel_regwen_49_we;
+ logic mio_periph_insel_regwen_49_qs;
+ logic mio_periph_insel_regwen_49_wd;
+ logic mio_periph_insel_regwen_50_we;
+ logic mio_periph_insel_regwen_50_qs;
+ logic mio_periph_insel_regwen_50_wd;
+ logic mio_periph_insel_regwen_51_we;
+ logic mio_periph_insel_regwen_51_qs;
+ logic mio_periph_insel_regwen_51_wd;
+ logic mio_periph_insel_regwen_52_we;
+ logic mio_periph_insel_regwen_52_qs;
+ logic mio_periph_insel_regwen_52_wd;
+ logic mio_periph_insel_regwen_53_we;
+ logic mio_periph_insel_regwen_53_qs;
+ logic mio_periph_insel_regwen_53_wd;
+ logic mio_periph_insel_regwen_54_we;
+ logic mio_periph_insel_regwen_54_qs;
+ logic mio_periph_insel_regwen_54_wd;
+ logic mio_periph_insel_regwen_55_we;
+ logic mio_periph_insel_regwen_55_qs;
+ logic mio_periph_insel_regwen_55_wd;
+ logic mio_periph_insel_regwen_56_we;
+ logic mio_periph_insel_regwen_56_qs;
+ logic mio_periph_insel_regwen_56_wd;
+ logic mio_periph_insel_regwen_57_we;
+ logic mio_periph_insel_regwen_57_qs;
+ logic mio_periph_insel_regwen_57_wd;
+ logic mio_periph_insel_regwen_58_we;
+ logic mio_periph_insel_regwen_58_qs;
+ logic mio_periph_insel_regwen_58_wd;
+ logic mio_periph_insel_regwen_59_we;
+ logic mio_periph_insel_regwen_59_qs;
+ logic mio_periph_insel_regwen_59_wd;
+ logic mio_periph_insel_regwen_60_we;
+ logic mio_periph_insel_regwen_60_qs;
+ logic mio_periph_insel_regwen_60_wd;
+ logic mio_periph_insel_regwen_61_we;
+ logic mio_periph_insel_regwen_61_qs;
+ logic mio_periph_insel_regwen_61_wd;
+ logic mio_periph_insel_regwen_62_we;
+ logic mio_periph_insel_regwen_62_qs;
+ logic mio_periph_insel_regwen_62_wd;
+ logic mio_periph_insel_regwen_63_we;
+ logic mio_periph_insel_regwen_63_qs;
+ logic mio_periph_insel_regwen_63_wd;
+ logic mio_periph_insel_regwen_64_we;
+ logic mio_periph_insel_regwen_64_qs;
+ logic mio_periph_insel_regwen_64_wd;
+ logic mio_periph_insel_regwen_65_we;
+ logic mio_periph_insel_regwen_65_qs;
+ logic mio_periph_insel_regwen_65_wd;
+ logic mio_periph_insel_regwen_66_we;
+ logic mio_periph_insel_regwen_66_qs;
+ logic mio_periph_insel_regwen_66_wd;
+ logic mio_periph_insel_regwen_67_we;
+ logic mio_periph_insel_regwen_67_qs;
+ logic mio_periph_insel_regwen_67_wd;
+ logic mio_periph_insel_regwen_68_we;
+ logic mio_periph_insel_regwen_68_qs;
+ logic mio_periph_insel_regwen_68_wd;
+ logic mio_periph_insel_regwen_69_we;
+ logic mio_periph_insel_regwen_69_qs;
+ logic mio_periph_insel_regwen_69_wd;
+ logic mio_periph_insel_regwen_70_we;
+ logic mio_periph_insel_regwen_70_qs;
+ logic mio_periph_insel_regwen_70_wd;
+ logic mio_periph_insel_regwen_71_we;
+ logic mio_periph_insel_regwen_71_qs;
+ logic mio_periph_insel_regwen_71_wd;
+ logic mio_periph_insel_regwen_72_we;
+ logic mio_periph_insel_regwen_72_qs;
+ logic mio_periph_insel_regwen_72_wd;
+ logic mio_periph_insel_regwen_73_we;
+ logic mio_periph_insel_regwen_73_qs;
+ logic mio_periph_insel_regwen_73_wd;
+ logic mio_periph_insel_regwen_74_we;
+ logic mio_periph_insel_regwen_74_qs;
+ logic mio_periph_insel_regwen_74_wd;
+ logic mio_periph_insel_regwen_75_we;
+ logic mio_periph_insel_regwen_75_qs;
+ logic mio_periph_insel_regwen_75_wd;
+ logic mio_periph_insel_0_we;
+ logic [5:0] mio_periph_insel_0_qs;
+ logic [5:0] mio_periph_insel_0_wd;
+ logic mio_periph_insel_1_we;
+ logic [5:0] mio_periph_insel_1_qs;
+ logic [5:0] mio_periph_insel_1_wd;
+ logic mio_periph_insel_2_we;
+ logic [5:0] mio_periph_insel_2_qs;
+ logic [5:0] mio_periph_insel_2_wd;
+ logic mio_periph_insel_3_we;
+ logic [5:0] mio_periph_insel_3_qs;
+ logic [5:0] mio_periph_insel_3_wd;
+ logic mio_periph_insel_4_we;
+ logic [5:0] mio_periph_insel_4_qs;
+ logic [5:0] mio_periph_insel_4_wd;
+ logic mio_periph_insel_5_we;
+ logic [5:0] mio_periph_insel_5_qs;
+ logic [5:0] mio_periph_insel_5_wd;
+ logic mio_periph_insel_6_we;
+ logic [5:0] mio_periph_insel_6_qs;
+ logic [5:0] mio_periph_insel_6_wd;
+ logic mio_periph_insel_7_we;
+ logic [5:0] mio_periph_insel_7_qs;
+ logic [5:0] mio_periph_insel_7_wd;
+ logic mio_periph_insel_8_we;
+ logic [5:0] mio_periph_insel_8_qs;
+ logic [5:0] mio_periph_insel_8_wd;
+ logic mio_periph_insel_9_we;
+ logic [5:0] mio_periph_insel_9_qs;
+ logic [5:0] mio_periph_insel_9_wd;
+ logic mio_periph_insel_10_we;
+ logic [5:0] mio_periph_insel_10_qs;
+ logic [5:0] mio_periph_insel_10_wd;
+ logic mio_periph_insel_11_we;
+ logic [5:0] mio_periph_insel_11_qs;
+ logic [5:0] mio_periph_insel_11_wd;
+ logic mio_periph_insel_12_we;
+ logic [5:0] mio_periph_insel_12_qs;
+ logic [5:0] mio_periph_insel_12_wd;
+ logic mio_periph_insel_13_we;
+ logic [5:0] mio_periph_insel_13_qs;
+ logic [5:0] mio_periph_insel_13_wd;
+ logic mio_periph_insel_14_we;
+ logic [5:0] mio_periph_insel_14_qs;
+ logic [5:0] mio_periph_insel_14_wd;
+ logic mio_periph_insel_15_we;
+ logic [5:0] mio_periph_insel_15_qs;
+ logic [5:0] mio_periph_insel_15_wd;
+ logic mio_periph_insel_16_we;
+ logic [5:0] mio_periph_insel_16_qs;
+ logic [5:0] mio_periph_insel_16_wd;
+ logic mio_periph_insel_17_we;
+ logic [5:0] mio_periph_insel_17_qs;
+ logic [5:0] mio_periph_insel_17_wd;
+ logic mio_periph_insel_18_we;
+ logic [5:0] mio_periph_insel_18_qs;
+ logic [5:0] mio_periph_insel_18_wd;
+ logic mio_periph_insel_19_we;
+ logic [5:0] mio_periph_insel_19_qs;
+ logic [5:0] mio_periph_insel_19_wd;
+ logic mio_periph_insel_20_we;
+ logic [5:0] mio_periph_insel_20_qs;
+ logic [5:0] mio_periph_insel_20_wd;
+ logic mio_periph_insel_21_we;
+ logic [5:0] mio_periph_insel_21_qs;
+ logic [5:0] mio_periph_insel_21_wd;
+ logic mio_periph_insel_22_we;
+ logic [5:0] mio_periph_insel_22_qs;
+ logic [5:0] mio_periph_insel_22_wd;
+ logic mio_periph_insel_23_we;
+ logic [5:0] mio_periph_insel_23_qs;
+ logic [5:0] mio_periph_insel_23_wd;
+ logic mio_periph_insel_24_we;
+ logic [5:0] mio_periph_insel_24_qs;
+ logic [5:0] mio_periph_insel_24_wd;
+ logic mio_periph_insel_25_we;
+ logic [5:0] mio_periph_insel_25_qs;
+ logic [5:0] mio_periph_insel_25_wd;
+ logic mio_periph_insel_26_we;
+ logic [5:0] mio_periph_insel_26_qs;
+ logic [5:0] mio_periph_insel_26_wd;
+ logic mio_periph_insel_27_we;
+ logic [5:0] mio_periph_insel_27_qs;
+ logic [5:0] mio_periph_insel_27_wd;
+ logic mio_periph_insel_28_we;
+ logic [5:0] mio_periph_insel_28_qs;
+ logic [5:0] mio_periph_insel_28_wd;
+ logic mio_periph_insel_29_we;
+ logic [5:0] mio_periph_insel_29_qs;
+ logic [5:0] mio_periph_insel_29_wd;
+ logic mio_periph_insel_30_we;
+ logic [5:0] mio_periph_insel_30_qs;
+ logic [5:0] mio_periph_insel_30_wd;
+ logic mio_periph_insel_31_we;
+ logic [5:0] mio_periph_insel_31_qs;
+ logic [5:0] mio_periph_insel_31_wd;
+ logic mio_periph_insel_32_we;
+ logic [5:0] mio_periph_insel_32_qs;
+ logic [5:0] mio_periph_insel_32_wd;
+ logic mio_periph_insel_33_we;
+ logic [5:0] mio_periph_insel_33_qs;
+ logic [5:0] mio_periph_insel_33_wd;
+ logic mio_periph_insel_34_we;
+ logic [5:0] mio_periph_insel_34_qs;
+ logic [5:0] mio_periph_insel_34_wd;
+ logic mio_periph_insel_35_we;
+ logic [5:0] mio_periph_insel_35_qs;
+ logic [5:0] mio_periph_insel_35_wd;
+ logic mio_periph_insel_36_we;
+ logic [5:0] mio_periph_insel_36_qs;
+ logic [5:0] mio_periph_insel_36_wd;
+ logic mio_periph_insel_37_we;
+ logic [5:0] mio_periph_insel_37_qs;
+ logic [5:0] mio_periph_insel_37_wd;
+ logic mio_periph_insel_38_we;
+ logic [5:0] mio_periph_insel_38_qs;
+ logic [5:0] mio_periph_insel_38_wd;
+ logic mio_periph_insel_39_we;
+ logic [5:0] mio_periph_insel_39_qs;
+ logic [5:0] mio_periph_insel_39_wd;
+ logic mio_periph_insel_40_we;
+ logic [5:0] mio_periph_insel_40_qs;
+ logic [5:0] mio_periph_insel_40_wd;
+ logic mio_periph_insel_41_we;
+ logic [5:0] mio_periph_insel_41_qs;
+ logic [5:0] mio_periph_insel_41_wd;
+ logic mio_periph_insel_42_we;
+ logic [5:0] mio_periph_insel_42_qs;
+ logic [5:0] mio_periph_insel_42_wd;
+ logic mio_periph_insel_43_we;
+ logic [5:0] mio_periph_insel_43_qs;
+ logic [5:0] mio_periph_insel_43_wd;
+ logic mio_periph_insel_44_we;
+ logic [5:0] mio_periph_insel_44_qs;
+ logic [5:0] mio_periph_insel_44_wd;
+ logic mio_periph_insel_45_we;
+ logic [5:0] mio_periph_insel_45_qs;
+ logic [5:0] mio_periph_insel_45_wd;
+ logic mio_periph_insel_46_we;
+ logic [5:0] mio_periph_insel_46_qs;
+ logic [5:0] mio_periph_insel_46_wd;
+ logic mio_periph_insel_47_we;
+ logic [5:0] mio_periph_insel_47_qs;
+ logic [5:0] mio_periph_insel_47_wd;
+ logic mio_periph_insel_48_we;
+ logic [5:0] mio_periph_insel_48_qs;
+ logic [5:0] mio_periph_insel_48_wd;
+ logic mio_periph_insel_49_we;
+ logic [5:0] mio_periph_insel_49_qs;
+ logic [5:0] mio_periph_insel_49_wd;
+ logic mio_periph_insel_50_we;
+ logic [5:0] mio_periph_insel_50_qs;
+ logic [5:0] mio_periph_insel_50_wd;
+ logic mio_periph_insel_51_we;
+ logic [5:0] mio_periph_insel_51_qs;
+ logic [5:0] mio_periph_insel_51_wd;
+ logic mio_periph_insel_52_we;
+ logic [5:0] mio_periph_insel_52_qs;
+ logic [5:0] mio_periph_insel_52_wd;
+ logic mio_periph_insel_53_we;
+ logic [5:0] mio_periph_insel_53_qs;
+ logic [5:0] mio_periph_insel_53_wd;
+ logic mio_periph_insel_54_we;
+ logic [5:0] mio_periph_insel_54_qs;
+ logic [5:0] mio_periph_insel_54_wd;
+ logic mio_periph_insel_55_we;
+ logic [5:0] mio_periph_insel_55_qs;
+ logic [5:0] mio_periph_insel_55_wd;
+ logic mio_periph_insel_56_we;
+ logic [5:0] mio_periph_insel_56_qs;
+ logic [5:0] mio_periph_insel_56_wd;
+ logic mio_periph_insel_57_we;
+ logic [5:0] mio_periph_insel_57_qs;
+ logic [5:0] mio_periph_insel_57_wd;
+ logic mio_periph_insel_58_we;
+ logic [5:0] mio_periph_insel_58_qs;
+ logic [5:0] mio_periph_insel_58_wd;
+ logic mio_periph_insel_59_we;
+ logic [5:0] mio_periph_insel_59_qs;
+ logic [5:0] mio_periph_insel_59_wd;
+ logic mio_periph_insel_60_we;
+ logic [5:0] mio_periph_insel_60_qs;
+ logic [5:0] mio_periph_insel_60_wd;
+ logic mio_periph_insel_61_we;
+ logic [5:0] mio_periph_insel_61_qs;
+ logic [5:0] mio_periph_insel_61_wd;
+ logic mio_periph_insel_62_we;
+ logic [5:0] mio_periph_insel_62_qs;
+ logic [5:0] mio_periph_insel_62_wd;
+ logic mio_periph_insel_63_we;
+ logic [5:0] mio_periph_insel_63_qs;
+ logic [5:0] mio_periph_insel_63_wd;
+ logic mio_periph_insel_64_we;
+ logic [5:0] mio_periph_insel_64_qs;
+ logic [5:0] mio_periph_insel_64_wd;
+ logic mio_periph_insel_65_we;
+ logic [5:0] mio_periph_insel_65_qs;
+ logic [5:0] mio_periph_insel_65_wd;
+ logic mio_periph_insel_66_we;
+ logic [5:0] mio_periph_insel_66_qs;
+ logic [5:0] mio_periph_insel_66_wd;
+ logic mio_periph_insel_67_we;
+ logic [5:0] mio_periph_insel_67_qs;
+ logic [5:0] mio_periph_insel_67_wd;
+ logic mio_periph_insel_68_we;
+ logic [5:0] mio_periph_insel_68_qs;
+ logic [5:0] mio_periph_insel_68_wd;
+ logic mio_periph_insel_69_we;
+ logic [5:0] mio_periph_insel_69_qs;
+ logic [5:0] mio_periph_insel_69_wd;
+ logic mio_periph_insel_70_we;
+ logic [5:0] mio_periph_insel_70_qs;
+ logic [5:0] mio_periph_insel_70_wd;
+ logic mio_periph_insel_71_we;
+ logic [5:0] mio_periph_insel_71_qs;
+ logic [5:0] mio_periph_insel_71_wd;
+ logic mio_periph_insel_72_we;
+ logic [5:0] mio_periph_insel_72_qs;
+ logic [5:0] mio_periph_insel_72_wd;
+ logic mio_periph_insel_73_we;
+ logic [5:0] mio_periph_insel_73_qs;
+ logic [5:0] mio_periph_insel_73_wd;
+ logic mio_periph_insel_74_we;
+ logic [5:0] mio_periph_insel_74_qs;
+ logic [5:0] mio_periph_insel_74_wd;
+ logic mio_periph_insel_75_we;
+ logic [5:0] mio_periph_insel_75_qs;
+ logic [5:0] mio_periph_insel_75_wd;
+ logic mio_outsel_regwen_0_we;
+ logic mio_outsel_regwen_0_qs;
+ logic mio_outsel_regwen_0_wd;
+ logic mio_outsel_regwen_1_we;
+ logic mio_outsel_regwen_1_qs;
+ logic mio_outsel_regwen_1_wd;
+ logic mio_outsel_regwen_2_we;
+ logic mio_outsel_regwen_2_qs;
+ logic mio_outsel_regwen_2_wd;
+ logic mio_outsel_regwen_3_we;
+ logic mio_outsel_regwen_3_qs;
+ logic mio_outsel_regwen_3_wd;
+ logic mio_outsel_regwen_4_we;
+ logic mio_outsel_regwen_4_qs;
+ logic mio_outsel_regwen_4_wd;
+ logic mio_outsel_regwen_5_we;
+ logic mio_outsel_regwen_5_qs;
+ logic mio_outsel_regwen_5_wd;
+ logic mio_outsel_regwen_6_we;
+ logic mio_outsel_regwen_6_qs;
+ logic mio_outsel_regwen_6_wd;
+ logic mio_outsel_regwen_7_we;
+ logic mio_outsel_regwen_7_qs;
+ logic mio_outsel_regwen_7_wd;
+ logic mio_outsel_regwen_8_we;
+ logic mio_outsel_regwen_8_qs;
+ logic mio_outsel_regwen_8_wd;
+ logic mio_outsel_regwen_9_we;
+ logic mio_outsel_regwen_9_qs;
+ logic mio_outsel_regwen_9_wd;
+ logic mio_outsel_regwen_10_we;
+ logic mio_outsel_regwen_10_qs;
+ logic mio_outsel_regwen_10_wd;
+ logic mio_outsel_regwen_11_we;
+ logic mio_outsel_regwen_11_qs;
+ logic mio_outsel_regwen_11_wd;
+ logic mio_outsel_regwen_12_we;
+ logic mio_outsel_regwen_12_qs;
+ logic mio_outsel_regwen_12_wd;
+ logic mio_outsel_regwen_13_we;
+ logic mio_outsel_regwen_13_qs;
+ logic mio_outsel_regwen_13_wd;
+ logic mio_outsel_regwen_14_we;
+ logic mio_outsel_regwen_14_qs;
+ logic mio_outsel_regwen_14_wd;
+ logic mio_outsel_regwen_15_we;
+ logic mio_outsel_regwen_15_qs;
+ logic mio_outsel_regwen_15_wd;
+ logic mio_outsel_regwen_16_we;
+ logic mio_outsel_regwen_16_qs;
+ logic mio_outsel_regwen_16_wd;
+ logic mio_outsel_regwen_17_we;
+ logic mio_outsel_regwen_17_qs;
+ logic mio_outsel_regwen_17_wd;
+ logic mio_outsel_regwen_18_we;
+ logic mio_outsel_regwen_18_qs;
+ logic mio_outsel_regwen_18_wd;
+ logic mio_outsel_regwen_19_we;
+ logic mio_outsel_regwen_19_qs;
+ logic mio_outsel_regwen_19_wd;
+ logic mio_outsel_regwen_20_we;
+ logic mio_outsel_regwen_20_qs;
+ logic mio_outsel_regwen_20_wd;
+ logic mio_outsel_regwen_21_we;
+ logic mio_outsel_regwen_21_qs;
+ logic mio_outsel_regwen_21_wd;
+ logic mio_outsel_regwen_22_we;
+ logic mio_outsel_regwen_22_qs;
+ logic mio_outsel_regwen_22_wd;
+ logic mio_outsel_regwen_23_we;
+ logic mio_outsel_regwen_23_qs;
+ logic mio_outsel_regwen_23_wd;
+ logic mio_outsel_regwen_24_we;
+ logic mio_outsel_regwen_24_qs;
+ logic mio_outsel_regwen_24_wd;
+ logic mio_outsel_regwen_25_we;
+ logic mio_outsel_regwen_25_qs;
+ logic mio_outsel_regwen_25_wd;
+ logic mio_outsel_regwen_26_we;
+ logic mio_outsel_regwen_26_qs;
+ logic mio_outsel_regwen_26_wd;
+ logic mio_outsel_regwen_27_we;
+ logic mio_outsel_regwen_27_qs;
+ logic mio_outsel_regwen_27_wd;
+ logic mio_outsel_regwen_28_we;
+ logic mio_outsel_regwen_28_qs;
+ logic mio_outsel_regwen_28_wd;
+ logic mio_outsel_regwen_29_we;
+ logic mio_outsel_regwen_29_qs;
+ logic mio_outsel_regwen_29_wd;
+ logic mio_outsel_regwen_30_we;
+ logic mio_outsel_regwen_30_qs;
+ logic mio_outsel_regwen_30_wd;
+ logic mio_outsel_regwen_31_we;
+ logic mio_outsel_regwen_31_qs;
+ logic mio_outsel_regwen_31_wd;
+ logic mio_outsel_regwen_32_we;
+ logic mio_outsel_regwen_32_qs;
+ logic mio_outsel_regwen_32_wd;
+ logic mio_outsel_regwen_33_we;
+ logic mio_outsel_regwen_33_qs;
+ logic mio_outsel_regwen_33_wd;
+ logic mio_outsel_regwen_34_we;
+ logic mio_outsel_regwen_34_qs;
+ logic mio_outsel_regwen_34_wd;
+ logic mio_outsel_regwen_35_we;
+ logic mio_outsel_regwen_35_qs;
+ logic mio_outsel_regwen_35_wd;
+ logic mio_outsel_regwen_36_we;
+ logic mio_outsel_regwen_36_qs;
+ logic mio_outsel_regwen_36_wd;
+ logic mio_outsel_regwen_37_we;
+ logic mio_outsel_regwen_37_qs;
+ logic mio_outsel_regwen_37_wd;
+ logic mio_outsel_regwen_38_we;
+ logic mio_outsel_regwen_38_qs;
+ logic mio_outsel_regwen_38_wd;
+ logic mio_outsel_regwen_39_we;
+ logic mio_outsel_regwen_39_qs;
+ logic mio_outsel_regwen_39_wd;
+ logic mio_outsel_regwen_40_we;
+ logic mio_outsel_regwen_40_qs;
+ logic mio_outsel_regwen_40_wd;
+ logic mio_outsel_regwen_41_we;
+ logic mio_outsel_regwen_41_qs;
+ logic mio_outsel_regwen_41_wd;
+ logic mio_outsel_regwen_42_we;
+ logic mio_outsel_regwen_42_qs;
+ logic mio_outsel_regwen_42_wd;
+ logic mio_outsel_regwen_43_we;
+ logic mio_outsel_regwen_43_qs;
+ logic mio_outsel_regwen_43_wd;
+ logic mio_outsel_regwen_44_we;
+ logic mio_outsel_regwen_44_qs;
+ logic mio_outsel_regwen_44_wd;
+ logic mio_outsel_regwen_45_we;
+ logic mio_outsel_regwen_45_qs;
+ logic mio_outsel_regwen_45_wd;
+ logic mio_outsel_regwen_46_we;
+ logic mio_outsel_regwen_46_qs;
+ logic mio_outsel_regwen_46_wd;
+ logic mio_outsel_regwen_47_we;
+ logic mio_outsel_regwen_47_qs;
+ logic mio_outsel_regwen_47_wd;
+ logic mio_outsel_regwen_48_we;
+ logic mio_outsel_regwen_48_qs;
+ logic mio_outsel_regwen_48_wd;
+ logic mio_outsel_regwen_49_we;
+ logic mio_outsel_regwen_49_qs;
+ logic mio_outsel_regwen_49_wd;
+ logic mio_outsel_regwen_50_we;
+ logic mio_outsel_regwen_50_qs;
+ logic mio_outsel_regwen_50_wd;
+ logic mio_outsel_regwen_51_we;
+ logic mio_outsel_regwen_51_qs;
+ logic mio_outsel_regwen_51_wd;
+ logic mio_outsel_regwen_52_we;
+ logic mio_outsel_regwen_52_qs;
+ logic mio_outsel_regwen_52_wd;
+ logic mio_outsel_0_we;
+ logic [6:0] mio_outsel_0_qs;
+ logic [6:0] mio_outsel_0_wd;
+ logic mio_outsel_1_we;
+ logic [6:0] mio_outsel_1_qs;
+ logic [6:0] mio_outsel_1_wd;
+ logic mio_outsel_2_we;
+ logic [6:0] mio_outsel_2_qs;
+ logic [6:0] mio_outsel_2_wd;
+ logic mio_outsel_3_we;
+ logic [6:0] mio_outsel_3_qs;
+ logic [6:0] mio_outsel_3_wd;
+ logic mio_outsel_4_we;
+ logic [6:0] mio_outsel_4_qs;
+ logic [6:0] mio_outsel_4_wd;
+ logic mio_outsel_5_we;
+ logic [6:0] mio_outsel_5_qs;
+ logic [6:0] mio_outsel_5_wd;
+ logic mio_outsel_6_we;
+ logic [6:0] mio_outsel_6_qs;
+ logic [6:0] mio_outsel_6_wd;
+ logic mio_outsel_7_we;
+ logic [6:0] mio_outsel_7_qs;
+ logic [6:0] mio_outsel_7_wd;
+ logic mio_outsel_8_we;
+ logic [6:0] mio_outsel_8_qs;
+ logic [6:0] mio_outsel_8_wd;
+ logic mio_outsel_9_we;
+ logic [6:0] mio_outsel_9_qs;
+ logic [6:0] mio_outsel_9_wd;
+ logic mio_outsel_10_we;
+ logic [6:0] mio_outsel_10_qs;
+ logic [6:0] mio_outsel_10_wd;
+ logic mio_outsel_11_we;
+ logic [6:0] mio_outsel_11_qs;
+ logic [6:0] mio_outsel_11_wd;
+ logic mio_outsel_12_we;
+ logic [6:0] mio_outsel_12_qs;
+ logic [6:0] mio_outsel_12_wd;
+ logic mio_outsel_13_we;
+ logic [6:0] mio_outsel_13_qs;
+ logic [6:0] mio_outsel_13_wd;
+ logic mio_outsel_14_we;
+ logic [6:0] mio_outsel_14_qs;
+ logic [6:0] mio_outsel_14_wd;
+ logic mio_outsel_15_we;
+ logic [6:0] mio_outsel_15_qs;
+ logic [6:0] mio_outsel_15_wd;
+ logic mio_outsel_16_we;
+ logic [6:0] mio_outsel_16_qs;
+ logic [6:0] mio_outsel_16_wd;
+ logic mio_outsel_17_we;
+ logic [6:0] mio_outsel_17_qs;
+ logic [6:0] mio_outsel_17_wd;
+ logic mio_outsel_18_we;
+ logic [6:0] mio_outsel_18_qs;
+ logic [6:0] mio_outsel_18_wd;
+ logic mio_outsel_19_we;
+ logic [6:0] mio_outsel_19_qs;
+ logic [6:0] mio_outsel_19_wd;
+ logic mio_outsel_20_we;
+ logic [6:0] mio_outsel_20_qs;
+ logic [6:0] mio_outsel_20_wd;
+ logic mio_outsel_21_we;
+ logic [6:0] mio_outsel_21_qs;
+ logic [6:0] mio_outsel_21_wd;
+ logic mio_outsel_22_we;
+ logic [6:0] mio_outsel_22_qs;
+ logic [6:0] mio_outsel_22_wd;
+ logic mio_outsel_23_we;
+ logic [6:0] mio_outsel_23_qs;
+ logic [6:0] mio_outsel_23_wd;
+ logic mio_outsel_24_we;
+ logic [6:0] mio_outsel_24_qs;
+ logic [6:0] mio_outsel_24_wd;
+ logic mio_outsel_25_we;
+ logic [6:0] mio_outsel_25_qs;
+ logic [6:0] mio_outsel_25_wd;
+ logic mio_outsel_26_we;
+ logic [6:0] mio_outsel_26_qs;
+ logic [6:0] mio_outsel_26_wd;
+ logic mio_outsel_27_we;
+ logic [6:0] mio_outsel_27_qs;
+ logic [6:0] mio_outsel_27_wd;
+ logic mio_outsel_28_we;
+ logic [6:0] mio_outsel_28_qs;
+ logic [6:0] mio_outsel_28_wd;
+ logic mio_outsel_29_we;
+ logic [6:0] mio_outsel_29_qs;
+ logic [6:0] mio_outsel_29_wd;
+ logic mio_outsel_30_we;
+ logic [6:0] mio_outsel_30_qs;
+ logic [6:0] mio_outsel_30_wd;
+ logic mio_outsel_31_we;
+ logic [6:0] mio_outsel_31_qs;
+ logic [6:0] mio_outsel_31_wd;
+ logic mio_outsel_32_we;
+ logic [6:0] mio_outsel_32_qs;
+ logic [6:0] mio_outsel_32_wd;
+ logic mio_outsel_33_we;
+ logic [6:0] mio_outsel_33_qs;
+ logic [6:0] mio_outsel_33_wd;
+ logic mio_outsel_34_we;
+ logic [6:0] mio_outsel_34_qs;
+ logic [6:0] mio_outsel_34_wd;
+ logic mio_outsel_35_we;
+ logic [6:0] mio_outsel_35_qs;
+ logic [6:0] mio_outsel_35_wd;
+ logic mio_outsel_36_we;
+ logic [6:0] mio_outsel_36_qs;
+ logic [6:0] mio_outsel_36_wd;
+ logic mio_outsel_37_we;
+ logic [6:0] mio_outsel_37_qs;
+ logic [6:0] mio_outsel_37_wd;
+ logic mio_outsel_38_we;
+ logic [6:0] mio_outsel_38_qs;
+ logic [6:0] mio_outsel_38_wd;
+ logic mio_outsel_39_we;
+ logic [6:0] mio_outsel_39_qs;
+ logic [6:0] mio_outsel_39_wd;
+ logic mio_outsel_40_we;
+ logic [6:0] mio_outsel_40_qs;
+ logic [6:0] mio_outsel_40_wd;
+ logic mio_outsel_41_we;
+ logic [6:0] mio_outsel_41_qs;
+ logic [6:0] mio_outsel_41_wd;
+ logic mio_outsel_42_we;
+ logic [6:0] mio_outsel_42_qs;
+ logic [6:0] mio_outsel_42_wd;
+ logic mio_outsel_43_we;
+ logic [6:0] mio_outsel_43_qs;
+ logic [6:0] mio_outsel_43_wd;
+ logic mio_outsel_44_we;
+ logic [6:0] mio_outsel_44_qs;
+ logic [6:0] mio_outsel_44_wd;
+ logic mio_outsel_45_we;
+ logic [6:0] mio_outsel_45_qs;
+ logic [6:0] mio_outsel_45_wd;
+ logic mio_outsel_46_we;
+ logic [6:0] mio_outsel_46_qs;
+ logic [6:0] mio_outsel_46_wd;
+ logic mio_outsel_47_we;
+ logic [6:0] mio_outsel_47_qs;
+ logic [6:0] mio_outsel_47_wd;
+ logic mio_outsel_48_we;
+ logic [6:0] mio_outsel_48_qs;
+ logic [6:0] mio_outsel_48_wd;
+ logic mio_outsel_49_we;
+ logic [6:0] mio_outsel_49_qs;
+ logic [6:0] mio_outsel_49_wd;
+ logic mio_outsel_50_we;
+ logic [6:0] mio_outsel_50_qs;
+ logic [6:0] mio_outsel_50_wd;
+ logic mio_outsel_51_we;
+ logic [6:0] mio_outsel_51_qs;
+ logic [6:0] mio_outsel_51_wd;
+ logic mio_outsel_52_we;
+ logic [6:0] mio_outsel_52_qs;
+ logic [6:0] mio_outsel_52_wd;
+ logic mio_pad_attr_regwen_0_we;
+ logic mio_pad_attr_regwen_0_qs;
+ logic mio_pad_attr_regwen_0_wd;
+ logic mio_pad_attr_regwen_1_we;
+ logic mio_pad_attr_regwen_1_qs;
+ logic mio_pad_attr_regwen_1_wd;
+ logic mio_pad_attr_regwen_2_we;
+ logic mio_pad_attr_regwen_2_qs;
+ logic mio_pad_attr_regwen_2_wd;
+ logic mio_pad_attr_regwen_3_we;
+ logic mio_pad_attr_regwen_3_qs;
+ logic mio_pad_attr_regwen_3_wd;
+ logic mio_pad_attr_regwen_4_we;
+ logic mio_pad_attr_regwen_4_qs;
+ logic mio_pad_attr_regwen_4_wd;
+ logic mio_pad_attr_regwen_5_we;
+ logic mio_pad_attr_regwen_5_qs;
+ logic mio_pad_attr_regwen_5_wd;
+ logic mio_pad_attr_regwen_6_we;
+ logic mio_pad_attr_regwen_6_qs;
+ logic mio_pad_attr_regwen_6_wd;
+ logic mio_pad_attr_regwen_7_we;
+ logic mio_pad_attr_regwen_7_qs;
+ logic mio_pad_attr_regwen_7_wd;
+ logic mio_pad_attr_regwen_8_we;
+ logic mio_pad_attr_regwen_8_qs;
+ logic mio_pad_attr_regwen_8_wd;
+ logic mio_pad_attr_regwen_9_we;
+ logic mio_pad_attr_regwen_9_qs;
+ logic mio_pad_attr_regwen_9_wd;
+ logic mio_pad_attr_regwen_10_we;
+ logic mio_pad_attr_regwen_10_qs;
+ logic mio_pad_attr_regwen_10_wd;
+ logic mio_pad_attr_regwen_11_we;
+ logic mio_pad_attr_regwen_11_qs;
+ logic mio_pad_attr_regwen_11_wd;
+ logic mio_pad_attr_regwen_12_we;
+ logic mio_pad_attr_regwen_12_qs;
+ logic mio_pad_attr_regwen_12_wd;
+ logic mio_pad_attr_regwen_13_we;
+ logic mio_pad_attr_regwen_13_qs;
+ logic mio_pad_attr_regwen_13_wd;
+ logic mio_pad_attr_regwen_14_we;
+ logic mio_pad_attr_regwen_14_qs;
+ logic mio_pad_attr_regwen_14_wd;
+ logic mio_pad_attr_regwen_15_we;
+ logic mio_pad_attr_regwen_15_qs;
+ logic mio_pad_attr_regwen_15_wd;
+ logic mio_pad_attr_regwen_16_we;
+ logic mio_pad_attr_regwen_16_qs;
+ logic mio_pad_attr_regwen_16_wd;
+ logic mio_pad_attr_regwen_17_we;
+ logic mio_pad_attr_regwen_17_qs;
+ logic mio_pad_attr_regwen_17_wd;
+ logic mio_pad_attr_regwen_18_we;
+ logic mio_pad_attr_regwen_18_qs;
+ logic mio_pad_attr_regwen_18_wd;
+ logic mio_pad_attr_regwen_19_we;
+ logic mio_pad_attr_regwen_19_qs;
+ logic mio_pad_attr_regwen_19_wd;
+ logic mio_pad_attr_regwen_20_we;
+ logic mio_pad_attr_regwen_20_qs;
+ logic mio_pad_attr_regwen_20_wd;
+ logic mio_pad_attr_regwen_21_we;
+ logic mio_pad_attr_regwen_21_qs;
+ logic mio_pad_attr_regwen_21_wd;
+ logic mio_pad_attr_regwen_22_we;
+ logic mio_pad_attr_regwen_22_qs;
+ logic mio_pad_attr_regwen_22_wd;
+ logic mio_pad_attr_regwen_23_we;
+ logic mio_pad_attr_regwen_23_qs;
+ logic mio_pad_attr_regwen_23_wd;
+ logic mio_pad_attr_regwen_24_we;
+ logic mio_pad_attr_regwen_24_qs;
+ logic mio_pad_attr_regwen_24_wd;
+ logic mio_pad_attr_regwen_25_we;
+ logic mio_pad_attr_regwen_25_qs;
+ logic mio_pad_attr_regwen_25_wd;
+ logic mio_pad_attr_regwen_26_we;
+ logic mio_pad_attr_regwen_26_qs;
+ logic mio_pad_attr_regwen_26_wd;
+ logic mio_pad_attr_regwen_27_we;
+ logic mio_pad_attr_regwen_27_qs;
+ logic mio_pad_attr_regwen_27_wd;
+ logic mio_pad_attr_regwen_28_we;
+ logic mio_pad_attr_regwen_28_qs;
+ logic mio_pad_attr_regwen_28_wd;
+ logic mio_pad_attr_regwen_29_we;
+ logic mio_pad_attr_regwen_29_qs;
+ logic mio_pad_attr_regwen_29_wd;
+ logic mio_pad_attr_regwen_30_we;
+ logic mio_pad_attr_regwen_30_qs;
+ logic mio_pad_attr_regwen_30_wd;
+ logic mio_pad_attr_regwen_31_we;
+ logic mio_pad_attr_regwen_31_qs;
+ logic mio_pad_attr_regwen_31_wd;
+ logic mio_pad_attr_regwen_32_we;
+ logic mio_pad_attr_regwen_32_qs;
+ logic mio_pad_attr_regwen_32_wd;
+ logic mio_pad_attr_regwen_33_we;
+ logic mio_pad_attr_regwen_33_qs;
+ logic mio_pad_attr_regwen_33_wd;
+ logic mio_pad_attr_regwen_34_we;
+ logic mio_pad_attr_regwen_34_qs;
+ logic mio_pad_attr_regwen_34_wd;
+ logic mio_pad_attr_regwen_35_we;
+ logic mio_pad_attr_regwen_35_qs;
+ logic mio_pad_attr_regwen_35_wd;
+ logic mio_pad_attr_regwen_36_we;
+ logic mio_pad_attr_regwen_36_qs;
+ logic mio_pad_attr_regwen_36_wd;
+ logic mio_pad_attr_regwen_37_we;
+ logic mio_pad_attr_regwen_37_qs;
+ logic mio_pad_attr_regwen_37_wd;
+ logic mio_pad_attr_regwen_38_we;
+ logic mio_pad_attr_regwen_38_qs;
+ logic mio_pad_attr_regwen_38_wd;
+ logic mio_pad_attr_regwen_39_we;
+ logic mio_pad_attr_regwen_39_qs;
+ logic mio_pad_attr_regwen_39_wd;
+ logic mio_pad_attr_regwen_40_we;
+ logic mio_pad_attr_regwen_40_qs;
+ logic mio_pad_attr_regwen_40_wd;
+ logic mio_pad_attr_regwen_41_we;
+ logic mio_pad_attr_regwen_41_qs;
+ logic mio_pad_attr_regwen_41_wd;
+ logic mio_pad_attr_regwen_42_we;
+ logic mio_pad_attr_regwen_42_qs;
+ logic mio_pad_attr_regwen_42_wd;
+ logic mio_pad_attr_regwen_43_we;
+ logic mio_pad_attr_regwen_43_qs;
+ logic mio_pad_attr_regwen_43_wd;
+ logic mio_pad_attr_regwen_44_we;
+ logic mio_pad_attr_regwen_44_qs;
+ logic mio_pad_attr_regwen_44_wd;
+ logic mio_pad_attr_regwen_45_we;
+ logic mio_pad_attr_regwen_45_qs;
+ logic mio_pad_attr_regwen_45_wd;
+ logic mio_pad_attr_regwen_46_we;
+ logic mio_pad_attr_regwen_46_qs;
+ logic mio_pad_attr_regwen_46_wd;
+ logic mio_pad_attr_regwen_47_we;
+ logic mio_pad_attr_regwen_47_qs;
+ logic mio_pad_attr_regwen_47_wd;
+ logic mio_pad_attr_regwen_48_we;
+ logic mio_pad_attr_regwen_48_qs;
+ logic mio_pad_attr_regwen_48_wd;
+ logic mio_pad_attr_regwen_49_we;
+ logic mio_pad_attr_regwen_49_qs;
+ logic mio_pad_attr_regwen_49_wd;
+ logic mio_pad_attr_regwen_50_we;
+ logic mio_pad_attr_regwen_50_qs;
+ logic mio_pad_attr_regwen_50_wd;
+ logic mio_pad_attr_regwen_51_we;
+ logic mio_pad_attr_regwen_51_qs;
+ logic mio_pad_attr_regwen_51_wd;
+ logic mio_pad_attr_regwen_52_we;
+ logic mio_pad_attr_regwen_52_qs;
+ logic mio_pad_attr_regwen_52_wd;
+ logic mio_pad_attr_0_re;
+ logic mio_pad_attr_0_we;
+ logic mio_pad_attr_0_invert_0_qs;
+ logic mio_pad_attr_0_invert_0_wd;
+ logic mio_pad_attr_0_virtual_od_en_0_qs;
+ logic mio_pad_attr_0_virtual_od_en_0_wd;
+ logic mio_pad_attr_0_pull_en_0_qs;
+ logic mio_pad_attr_0_pull_en_0_wd;
+ logic mio_pad_attr_0_pull_select_0_qs;
+ logic mio_pad_attr_0_pull_select_0_wd;
+ logic mio_pad_attr_0_keeper_en_0_qs;
+ logic mio_pad_attr_0_keeper_en_0_wd;
+ logic mio_pad_attr_0_schmitt_en_0_qs;
+ logic mio_pad_attr_0_schmitt_en_0_wd;
+ logic mio_pad_attr_0_od_en_0_qs;
+ logic mio_pad_attr_0_od_en_0_wd;
+ logic [1:0] mio_pad_attr_0_slew_rate_0_qs;
+ logic [1:0] mio_pad_attr_0_slew_rate_0_wd;
+ logic [3:0] mio_pad_attr_0_drive_strength_0_qs;
+ logic [3:0] mio_pad_attr_0_drive_strength_0_wd;
+ logic mio_pad_attr_1_re;
+ logic mio_pad_attr_1_we;
+ logic mio_pad_attr_1_invert_1_qs;
+ logic mio_pad_attr_1_invert_1_wd;
+ logic mio_pad_attr_1_virtual_od_en_1_qs;
+ logic mio_pad_attr_1_virtual_od_en_1_wd;
+ logic mio_pad_attr_1_pull_en_1_qs;
+ logic mio_pad_attr_1_pull_en_1_wd;
+ logic mio_pad_attr_1_pull_select_1_qs;
+ logic mio_pad_attr_1_pull_select_1_wd;
+ logic mio_pad_attr_1_keeper_en_1_qs;
+ logic mio_pad_attr_1_keeper_en_1_wd;
+ logic mio_pad_attr_1_schmitt_en_1_qs;
+ logic mio_pad_attr_1_schmitt_en_1_wd;
+ logic mio_pad_attr_1_od_en_1_qs;
+ logic mio_pad_attr_1_od_en_1_wd;
+ logic [1:0] mio_pad_attr_1_slew_rate_1_qs;
+ logic [1:0] mio_pad_attr_1_slew_rate_1_wd;
+ logic [3:0] mio_pad_attr_1_drive_strength_1_qs;
+ logic [3:0] mio_pad_attr_1_drive_strength_1_wd;
+ logic mio_pad_attr_2_re;
+ logic mio_pad_attr_2_we;
+ logic mio_pad_attr_2_invert_2_qs;
+ logic mio_pad_attr_2_invert_2_wd;
+ logic mio_pad_attr_2_virtual_od_en_2_qs;
+ logic mio_pad_attr_2_virtual_od_en_2_wd;
+ logic mio_pad_attr_2_pull_en_2_qs;
+ logic mio_pad_attr_2_pull_en_2_wd;
+ logic mio_pad_attr_2_pull_select_2_qs;
+ logic mio_pad_attr_2_pull_select_2_wd;
+ logic mio_pad_attr_2_keeper_en_2_qs;
+ logic mio_pad_attr_2_keeper_en_2_wd;
+ logic mio_pad_attr_2_schmitt_en_2_qs;
+ logic mio_pad_attr_2_schmitt_en_2_wd;
+ logic mio_pad_attr_2_od_en_2_qs;
+ logic mio_pad_attr_2_od_en_2_wd;
+ logic [1:0] mio_pad_attr_2_slew_rate_2_qs;
+ logic [1:0] mio_pad_attr_2_slew_rate_2_wd;
+ logic [3:0] mio_pad_attr_2_drive_strength_2_qs;
+ logic [3:0] mio_pad_attr_2_drive_strength_2_wd;
+ logic mio_pad_attr_3_re;
+ logic mio_pad_attr_3_we;
+ logic mio_pad_attr_3_invert_3_qs;
+ logic mio_pad_attr_3_invert_3_wd;
+ logic mio_pad_attr_3_virtual_od_en_3_qs;
+ logic mio_pad_attr_3_virtual_od_en_3_wd;
+ logic mio_pad_attr_3_pull_en_3_qs;
+ logic mio_pad_attr_3_pull_en_3_wd;
+ logic mio_pad_attr_3_pull_select_3_qs;
+ logic mio_pad_attr_3_pull_select_3_wd;
+ logic mio_pad_attr_3_keeper_en_3_qs;
+ logic mio_pad_attr_3_keeper_en_3_wd;
+ logic mio_pad_attr_3_schmitt_en_3_qs;
+ logic mio_pad_attr_3_schmitt_en_3_wd;
+ logic mio_pad_attr_3_od_en_3_qs;
+ logic mio_pad_attr_3_od_en_3_wd;
+ logic [1:0] mio_pad_attr_3_slew_rate_3_qs;
+ logic [1:0] mio_pad_attr_3_slew_rate_3_wd;
+ logic [3:0] mio_pad_attr_3_drive_strength_3_qs;
+ logic [3:0] mio_pad_attr_3_drive_strength_3_wd;
+ logic mio_pad_attr_4_re;
+ logic mio_pad_attr_4_we;
+ logic mio_pad_attr_4_invert_4_qs;
+ logic mio_pad_attr_4_invert_4_wd;
+ logic mio_pad_attr_4_virtual_od_en_4_qs;
+ logic mio_pad_attr_4_virtual_od_en_4_wd;
+ logic mio_pad_attr_4_pull_en_4_qs;
+ logic mio_pad_attr_4_pull_en_4_wd;
+ logic mio_pad_attr_4_pull_select_4_qs;
+ logic mio_pad_attr_4_pull_select_4_wd;
+ logic mio_pad_attr_4_keeper_en_4_qs;
+ logic mio_pad_attr_4_keeper_en_4_wd;
+ logic mio_pad_attr_4_schmitt_en_4_qs;
+ logic mio_pad_attr_4_schmitt_en_4_wd;
+ logic mio_pad_attr_4_od_en_4_qs;
+ logic mio_pad_attr_4_od_en_4_wd;
+ logic [1:0] mio_pad_attr_4_slew_rate_4_qs;
+ logic [1:0] mio_pad_attr_4_slew_rate_4_wd;
+ logic [3:0] mio_pad_attr_4_drive_strength_4_qs;
+ logic [3:0] mio_pad_attr_4_drive_strength_4_wd;
+ logic mio_pad_attr_5_re;
+ logic mio_pad_attr_5_we;
+ logic mio_pad_attr_5_invert_5_qs;
+ logic mio_pad_attr_5_invert_5_wd;
+ logic mio_pad_attr_5_virtual_od_en_5_qs;
+ logic mio_pad_attr_5_virtual_od_en_5_wd;
+ logic mio_pad_attr_5_pull_en_5_qs;
+ logic mio_pad_attr_5_pull_en_5_wd;
+ logic mio_pad_attr_5_pull_select_5_qs;
+ logic mio_pad_attr_5_pull_select_5_wd;
+ logic mio_pad_attr_5_keeper_en_5_qs;
+ logic mio_pad_attr_5_keeper_en_5_wd;
+ logic mio_pad_attr_5_schmitt_en_5_qs;
+ logic mio_pad_attr_5_schmitt_en_5_wd;
+ logic mio_pad_attr_5_od_en_5_qs;
+ logic mio_pad_attr_5_od_en_5_wd;
+ logic [1:0] mio_pad_attr_5_slew_rate_5_qs;
+ logic [1:0] mio_pad_attr_5_slew_rate_5_wd;
+ logic [3:0] mio_pad_attr_5_drive_strength_5_qs;
+ logic [3:0] mio_pad_attr_5_drive_strength_5_wd;
+ logic mio_pad_attr_6_re;
+ logic mio_pad_attr_6_we;
+ logic mio_pad_attr_6_invert_6_qs;
+ logic mio_pad_attr_6_invert_6_wd;
+ logic mio_pad_attr_6_virtual_od_en_6_qs;
+ logic mio_pad_attr_6_virtual_od_en_6_wd;
+ logic mio_pad_attr_6_pull_en_6_qs;
+ logic mio_pad_attr_6_pull_en_6_wd;
+ logic mio_pad_attr_6_pull_select_6_qs;
+ logic mio_pad_attr_6_pull_select_6_wd;
+ logic mio_pad_attr_6_keeper_en_6_qs;
+ logic mio_pad_attr_6_keeper_en_6_wd;
+ logic mio_pad_attr_6_schmitt_en_6_qs;
+ logic mio_pad_attr_6_schmitt_en_6_wd;
+ logic mio_pad_attr_6_od_en_6_qs;
+ logic mio_pad_attr_6_od_en_6_wd;
+ logic [1:0] mio_pad_attr_6_slew_rate_6_qs;
+ logic [1:0] mio_pad_attr_6_slew_rate_6_wd;
+ logic [3:0] mio_pad_attr_6_drive_strength_6_qs;
+ logic [3:0] mio_pad_attr_6_drive_strength_6_wd;
+ logic mio_pad_attr_7_re;
+ logic mio_pad_attr_7_we;
+ logic mio_pad_attr_7_invert_7_qs;
+ logic mio_pad_attr_7_invert_7_wd;
+ logic mio_pad_attr_7_virtual_od_en_7_qs;
+ logic mio_pad_attr_7_virtual_od_en_7_wd;
+ logic mio_pad_attr_7_pull_en_7_qs;
+ logic mio_pad_attr_7_pull_en_7_wd;
+ logic mio_pad_attr_7_pull_select_7_qs;
+ logic mio_pad_attr_7_pull_select_7_wd;
+ logic mio_pad_attr_7_keeper_en_7_qs;
+ logic mio_pad_attr_7_keeper_en_7_wd;
+ logic mio_pad_attr_7_schmitt_en_7_qs;
+ logic mio_pad_attr_7_schmitt_en_7_wd;
+ logic mio_pad_attr_7_od_en_7_qs;
+ logic mio_pad_attr_7_od_en_7_wd;
+ logic [1:0] mio_pad_attr_7_slew_rate_7_qs;
+ logic [1:0] mio_pad_attr_7_slew_rate_7_wd;
+ logic [3:0] mio_pad_attr_7_drive_strength_7_qs;
+ logic [3:0] mio_pad_attr_7_drive_strength_7_wd;
+ logic mio_pad_attr_8_re;
+ logic mio_pad_attr_8_we;
+ logic mio_pad_attr_8_invert_8_qs;
+ logic mio_pad_attr_8_invert_8_wd;
+ logic mio_pad_attr_8_virtual_od_en_8_qs;
+ logic mio_pad_attr_8_virtual_od_en_8_wd;
+ logic mio_pad_attr_8_pull_en_8_qs;
+ logic mio_pad_attr_8_pull_en_8_wd;
+ logic mio_pad_attr_8_pull_select_8_qs;
+ logic mio_pad_attr_8_pull_select_8_wd;
+ logic mio_pad_attr_8_keeper_en_8_qs;
+ logic mio_pad_attr_8_keeper_en_8_wd;
+ logic mio_pad_attr_8_schmitt_en_8_qs;
+ logic mio_pad_attr_8_schmitt_en_8_wd;
+ logic mio_pad_attr_8_od_en_8_qs;
+ logic mio_pad_attr_8_od_en_8_wd;
+ logic [1:0] mio_pad_attr_8_slew_rate_8_qs;
+ logic [1:0] mio_pad_attr_8_slew_rate_8_wd;
+ logic [3:0] mio_pad_attr_8_drive_strength_8_qs;
+ logic [3:0] mio_pad_attr_8_drive_strength_8_wd;
+ logic mio_pad_attr_9_re;
+ logic mio_pad_attr_9_we;
+ logic mio_pad_attr_9_invert_9_qs;
+ logic mio_pad_attr_9_invert_9_wd;
+ logic mio_pad_attr_9_virtual_od_en_9_qs;
+ logic mio_pad_attr_9_virtual_od_en_9_wd;
+ logic mio_pad_attr_9_pull_en_9_qs;
+ logic mio_pad_attr_9_pull_en_9_wd;
+ logic mio_pad_attr_9_pull_select_9_qs;
+ logic mio_pad_attr_9_pull_select_9_wd;
+ logic mio_pad_attr_9_keeper_en_9_qs;
+ logic mio_pad_attr_9_keeper_en_9_wd;
+ logic mio_pad_attr_9_schmitt_en_9_qs;
+ logic mio_pad_attr_9_schmitt_en_9_wd;
+ logic mio_pad_attr_9_od_en_9_qs;
+ logic mio_pad_attr_9_od_en_9_wd;
+ logic [1:0] mio_pad_attr_9_slew_rate_9_qs;
+ logic [1:0] mio_pad_attr_9_slew_rate_9_wd;
+ logic [3:0] mio_pad_attr_9_drive_strength_9_qs;
+ logic [3:0] mio_pad_attr_9_drive_strength_9_wd;
+ logic mio_pad_attr_10_re;
+ logic mio_pad_attr_10_we;
+ logic mio_pad_attr_10_invert_10_qs;
+ logic mio_pad_attr_10_invert_10_wd;
+ logic mio_pad_attr_10_virtual_od_en_10_qs;
+ logic mio_pad_attr_10_virtual_od_en_10_wd;
+ logic mio_pad_attr_10_pull_en_10_qs;
+ logic mio_pad_attr_10_pull_en_10_wd;
+ logic mio_pad_attr_10_pull_select_10_qs;
+ logic mio_pad_attr_10_pull_select_10_wd;
+ logic mio_pad_attr_10_keeper_en_10_qs;
+ logic mio_pad_attr_10_keeper_en_10_wd;
+ logic mio_pad_attr_10_schmitt_en_10_qs;
+ logic mio_pad_attr_10_schmitt_en_10_wd;
+ logic mio_pad_attr_10_od_en_10_qs;
+ logic mio_pad_attr_10_od_en_10_wd;
+ logic [1:0] mio_pad_attr_10_slew_rate_10_qs;
+ logic [1:0] mio_pad_attr_10_slew_rate_10_wd;
+ logic [3:0] mio_pad_attr_10_drive_strength_10_qs;
+ logic [3:0] mio_pad_attr_10_drive_strength_10_wd;
+ logic mio_pad_attr_11_re;
+ logic mio_pad_attr_11_we;
+ logic mio_pad_attr_11_invert_11_qs;
+ logic mio_pad_attr_11_invert_11_wd;
+ logic mio_pad_attr_11_virtual_od_en_11_qs;
+ logic mio_pad_attr_11_virtual_od_en_11_wd;
+ logic mio_pad_attr_11_pull_en_11_qs;
+ logic mio_pad_attr_11_pull_en_11_wd;
+ logic mio_pad_attr_11_pull_select_11_qs;
+ logic mio_pad_attr_11_pull_select_11_wd;
+ logic mio_pad_attr_11_keeper_en_11_qs;
+ logic mio_pad_attr_11_keeper_en_11_wd;
+ logic mio_pad_attr_11_schmitt_en_11_qs;
+ logic mio_pad_attr_11_schmitt_en_11_wd;
+ logic mio_pad_attr_11_od_en_11_qs;
+ logic mio_pad_attr_11_od_en_11_wd;
+ logic [1:0] mio_pad_attr_11_slew_rate_11_qs;
+ logic [1:0] mio_pad_attr_11_slew_rate_11_wd;
+ logic [3:0] mio_pad_attr_11_drive_strength_11_qs;
+ logic [3:0] mio_pad_attr_11_drive_strength_11_wd;
+ logic mio_pad_attr_12_re;
+ logic mio_pad_attr_12_we;
+ logic mio_pad_attr_12_invert_12_qs;
+ logic mio_pad_attr_12_invert_12_wd;
+ logic mio_pad_attr_12_virtual_od_en_12_qs;
+ logic mio_pad_attr_12_virtual_od_en_12_wd;
+ logic mio_pad_attr_12_pull_en_12_qs;
+ logic mio_pad_attr_12_pull_en_12_wd;
+ logic mio_pad_attr_12_pull_select_12_qs;
+ logic mio_pad_attr_12_pull_select_12_wd;
+ logic mio_pad_attr_12_keeper_en_12_qs;
+ logic mio_pad_attr_12_keeper_en_12_wd;
+ logic mio_pad_attr_12_schmitt_en_12_qs;
+ logic mio_pad_attr_12_schmitt_en_12_wd;
+ logic mio_pad_attr_12_od_en_12_qs;
+ logic mio_pad_attr_12_od_en_12_wd;
+ logic [1:0] mio_pad_attr_12_slew_rate_12_qs;
+ logic [1:0] mio_pad_attr_12_slew_rate_12_wd;
+ logic [3:0] mio_pad_attr_12_drive_strength_12_qs;
+ logic [3:0] mio_pad_attr_12_drive_strength_12_wd;
+ logic mio_pad_attr_13_re;
+ logic mio_pad_attr_13_we;
+ logic mio_pad_attr_13_invert_13_qs;
+ logic mio_pad_attr_13_invert_13_wd;
+ logic mio_pad_attr_13_virtual_od_en_13_qs;
+ logic mio_pad_attr_13_virtual_od_en_13_wd;
+ logic mio_pad_attr_13_pull_en_13_qs;
+ logic mio_pad_attr_13_pull_en_13_wd;
+ logic mio_pad_attr_13_pull_select_13_qs;
+ logic mio_pad_attr_13_pull_select_13_wd;
+ logic mio_pad_attr_13_keeper_en_13_qs;
+ logic mio_pad_attr_13_keeper_en_13_wd;
+ logic mio_pad_attr_13_schmitt_en_13_qs;
+ logic mio_pad_attr_13_schmitt_en_13_wd;
+ logic mio_pad_attr_13_od_en_13_qs;
+ logic mio_pad_attr_13_od_en_13_wd;
+ logic [1:0] mio_pad_attr_13_slew_rate_13_qs;
+ logic [1:0] mio_pad_attr_13_slew_rate_13_wd;
+ logic [3:0] mio_pad_attr_13_drive_strength_13_qs;
+ logic [3:0] mio_pad_attr_13_drive_strength_13_wd;
+ logic mio_pad_attr_14_re;
+ logic mio_pad_attr_14_we;
+ logic mio_pad_attr_14_invert_14_qs;
+ logic mio_pad_attr_14_invert_14_wd;
+ logic mio_pad_attr_14_virtual_od_en_14_qs;
+ logic mio_pad_attr_14_virtual_od_en_14_wd;
+ logic mio_pad_attr_14_pull_en_14_qs;
+ logic mio_pad_attr_14_pull_en_14_wd;
+ logic mio_pad_attr_14_pull_select_14_qs;
+ logic mio_pad_attr_14_pull_select_14_wd;
+ logic mio_pad_attr_14_keeper_en_14_qs;
+ logic mio_pad_attr_14_keeper_en_14_wd;
+ logic mio_pad_attr_14_schmitt_en_14_qs;
+ logic mio_pad_attr_14_schmitt_en_14_wd;
+ logic mio_pad_attr_14_od_en_14_qs;
+ logic mio_pad_attr_14_od_en_14_wd;
+ logic [1:0] mio_pad_attr_14_slew_rate_14_qs;
+ logic [1:0] mio_pad_attr_14_slew_rate_14_wd;
+ logic [3:0] mio_pad_attr_14_drive_strength_14_qs;
+ logic [3:0] mio_pad_attr_14_drive_strength_14_wd;
+ logic mio_pad_attr_15_re;
+ logic mio_pad_attr_15_we;
+ logic mio_pad_attr_15_invert_15_qs;
+ logic mio_pad_attr_15_invert_15_wd;
+ logic mio_pad_attr_15_virtual_od_en_15_qs;
+ logic mio_pad_attr_15_virtual_od_en_15_wd;
+ logic mio_pad_attr_15_pull_en_15_qs;
+ logic mio_pad_attr_15_pull_en_15_wd;
+ logic mio_pad_attr_15_pull_select_15_qs;
+ logic mio_pad_attr_15_pull_select_15_wd;
+ logic mio_pad_attr_15_keeper_en_15_qs;
+ logic mio_pad_attr_15_keeper_en_15_wd;
+ logic mio_pad_attr_15_schmitt_en_15_qs;
+ logic mio_pad_attr_15_schmitt_en_15_wd;
+ logic mio_pad_attr_15_od_en_15_qs;
+ logic mio_pad_attr_15_od_en_15_wd;
+ logic [1:0] mio_pad_attr_15_slew_rate_15_qs;
+ logic [1:0] mio_pad_attr_15_slew_rate_15_wd;
+ logic [3:0] mio_pad_attr_15_drive_strength_15_qs;
+ logic [3:0] mio_pad_attr_15_drive_strength_15_wd;
+ logic mio_pad_attr_16_re;
+ logic mio_pad_attr_16_we;
+ logic mio_pad_attr_16_invert_16_qs;
+ logic mio_pad_attr_16_invert_16_wd;
+ logic mio_pad_attr_16_virtual_od_en_16_qs;
+ logic mio_pad_attr_16_virtual_od_en_16_wd;
+ logic mio_pad_attr_16_pull_en_16_qs;
+ logic mio_pad_attr_16_pull_en_16_wd;
+ logic mio_pad_attr_16_pull_select_16_qs;
+ logic mio_pad_attr_16_pull_select_16_wd;
+ logic mio_pad_attr_16_keeper_en_16_qs;
+ logic mio_pad_attr_16_keeper_en_16_wd;
+ logic mio_pad_attr_16_schmitt_en_16_qs;
+ logic mio_pad_attr_16_schmitt_en_16_wd;
+ logic mio_pad_attr_16_od_en_16_qs;
+ logic mio_pad_attr_16_od_en_16_wd;
+ logic [1:0] mio_pad_attr_16_slew_rate_16_qs;
+ logic [1:0] mio_pad_attr_16_slew_rate_16_wd;
+ logic [3:0] mio_pad_attr_16_drive_strength_16_qs;
+ logic [3:0] mio_pad_attr_16_drive_strength_16_wd;
+ logic mio_pad_attr_17_re;
+ logic mio_pad_attr_17_we;
+ logic mio_pad_attr_17_invert_17_qs;
+ logic mio_pad_attr_17_invert_17_wd;
+ logic mio_pad_attr_17_virtual_od_en_17_qs;
+ logic mio_pad_attr_17_virtual_od_en_17_wd;
+ logic mio_pad_attr_17_pull_en_17_qs;
+ logic mio_pad_attr_17_pull_en_17_wd;
+ logic mio_pad_attr_17_pull_select_17_qs;
+ logic mio_pad_attr_17_pull_select_17_wd;
+ logic mio_pad_attr_17_keeper_en_17_qs;
+ logic mio_pad_attr_17_keeper_en_17_wd;
+ logic mio_pad_attr_17_schmitt_en_17_qs;
+ logic mio_pad_attr_17_schmitt_en_17_wd;
+ logic mio_pad_attr_17_od_en_17_qs;
+ logic mio_pad_attr_17_od_en_17_wd;
+ logic [1:0] mio_pad_attr_17_slew_rate_17_qs;
+ logic [1:0] mio_pad_attr_17_slew_rate_17_wd;
+ logic [3:0] mio_pad_attr_17_drive_strength_17_qs;
+ logic [3:0] mio_pad_attr_17_drive_strength_17_wd;
+ logic mio_pad_attr_18_re;
+ logic mio_pad_attr_18_we;
+ logic mio_pad_attr_18_invert_18_qs;
+ logic mio_pad_attr_18_invert_18_wd;
+ logic mio_pad_attr_18_virtual_od_en_18_qs;
+ logic mio_pad_attr_18_virtual_od_en_18_wd;
+ logic mio_pad_attr_18_pull_en_18_qs;
+ logic mio_pad_attr_18_pull_en_18_wd;
+ logic mio_pad_attr_18_pull_select_18_qs;
+ logic mio_pad_attr_18_pull_select_18_wd;
+ logic mio_pad_attr_18_keeper_en_18_qs;
+ logic mio_pad_attr_18_keeper_en_18_wd;
+ logic mio_pad_attr_18_schmitt_en_18_qs;
+ logic mio_pad_attr_18_schmitt_en_18_wd;
+ logic mio_pad_attr_18_od_en_18_qs;
+ logic mio_pad_attr_18_od_en_18_wd;
+ logic [1:0] mio_pad_attr_18_slew_rate_18_qs;
+ logic [1:0] mio_pad_attr_18_slew_rate_18_wd;
+ logic [3:0] mio_pad_attr_18_drive_strength_18_qs;
+ logic [3:0] mio_pad_attr_18_drive_strength_18_wd;
+ logic mio_pad_attr_19_re;
+ logic mio_pad_attr_19_we;
+ logic mio_pad_attr_19_invert_19_qs;
+ logic mio_pad_attr_19_invert_19_wd;
+ logic mio_pad_attr_19_virtual_od_en_19_qs;
+ logic mio_pad_attr_19_virtual_od_en_19_wd;
+ logic mio_pad_attr_19_pull_en_19_qs;
+ logic mio_pad_attr_19_pull_en_19_wd;
+ logic mio_pad_attr_19_pull_select_19_qs;
+ logic mio_pad_attr_19_pull_select_19_wd;
+ logic mio_pad_attr_19_keeper_en_19_qs;
+ logic mio_pad_attr_19_keeper_en_19_wd;
+ logic mio_pad_attr_19_schmitt_en_19_qs;
+ logic mio_pad_attr_19_schmitt_en_19_wd;
+ logic mio_pad_attr_19_od_en_19_qs;
+ logic mio_pad_attr_19_od_en_19_wd;
+ logic [1:0] mio_pad_attr_19_slew_rate_19_qs;
+ logic [1:0] mio_pad_attr_19_slew_rate_19_wd;
+ logic [3:0] mio_pad_attr_19_drive_strength_19_qs;
+ logic [3:0] mio_pad_attr_19_drive_strength_19_wd;
+ logic mio_pad_attr_20_re;
+ logic mio_pad_attr_20_we;
+ logic mio_pad_attr_20_invert_20_qs;
+ logic mio_pad_attr_20_invert_20_wd;
+ logic mio_pad_attr_20_virtual_od_en_20_qs;
+ logic mio_pad_attr_20_virtual_od_en_20_wd;
+ logic mio_pad_attr_20_pull_en_20_qs;
+ logic mio_pad_attr_20_pull_en_20_wd;
+ logic mio_pad_attr_20_pull_select_20_qs;
+ logic mio_pad_attr_20_pull_select_20_wd;
+ logic mio_pad_attr_20_keeper_en_20_qs;
+ logic mio_pad_attr_20_keeper_en_20_wd;
+ logic mio_pad_attr_20_schmitt_en_20_qs;
+ logic mio_pad_attr_20_schmitt_en_20_wd;
+ logic mio_pad_attr_20_od_en_20_qs;
+ logic mio_pad_attr_20_od_en_20_wd;
+ logic [1:0] mio_pad_attr_20_slew_rate_20_qs;
+ logic [1:0] mio_pad_attr_20_slew_rate_20_wd;
+ logic [3:0] mio_pad_attr_20_drive_strength_20_qs;
+ logic [3:0] mio_pad_attr_20_drive_strength_20_wd;
+ logic mio_pad_attr_21_re;
+ logic mio_pad_attr_21_we;
+ logic mio_pad_attr_21_invert_21_qs;
+ logic mio_pad_attr_21_invert_21_wd;
+ logic mio_pad_attr_21_virtual_od_en_21_qs;
+ logic mio_pad_attr_21_virtual_od_en_21_wd;
+ logic mio_pad_attr_21_pull_en_21_qs;
+ logic mio_pad_attr_21_pull_en_21_wd;
+ logic mio_pad_attr_21_pull_select_21_qs;
+ logic mio_pad_attr_21_pull_select_21_wd;
+ logic mio_pad_attr_21_keeper_en_21_qs;
+ logic mio_pad_attr_21_keeper_en_21_wd;
+ logic mio_pad_attr_21_schmitt_en_21_qs;
+ logic mio_pad_attr_21_schmitt_en_21_wd;
+ logic mio_pad_attr_21_od_en_21_qs;
+ logic mio_pad_attr_21_od_en_21_wd;
+ logic [1:0] mio_pad_attr_21_slew_rate_21_qs;
+ logic [1:0] mio_pad_attr_21_slew_rate_21_wd;
+ logic [3:0] mio_pad_attr_21_drive_strength_21_qs;
+ logic [3:0] mio_pad_attr_21_drive_strength_21_wd;
+ logic mio_pad_attr_22_re;
+ logic mio_pad_attr_22_we;
+ logic mio_pad_attr_22_invert_22_qs;
+ logic mio_pad_attr_22_invert_22_wd;
+ logic mio_pad_attr_22_virtual_od_en_22_qs;
+ logic mio_pad_attr_22_virtual_od_en_22_wd;
+ logic mio_pad_attr_22_pull_en_22_qs;
+ logic mio_pad_attr_22_pull_en_22_wd;
+ logic mio_pad_attr_22_pull_select_22_qs;
+ logic mio_pad_attr_22_pull_select_22_wd;
+ logic mio_pad_attr_22_keeper_en_22_qs;
+ logic mio_pad_attr_22_keeper_en_22_wd;
+ logic mio_pad_attr_22_schmitt_en_22_qs;
+ logic mio_pad_attr_22_schmitt_en_22_wd;
+ logic mio_pad_attr_22_od_en_22_qs;
+ logic mio_pad_attr_22_od_en_22_wd;
+ logic [1:0] mio_pad_attr_22_slew_rate_22_qs;
+ logic [1:0] mio_pad_attr_22_slew_rate_22_wd;
+ logic [3:0] mio_pad_attr_22_drive_strength_22_qs;
+ logic [3:0] mio_pad_attr_22_drive_strength_22_wd;
+ logic mio_pad_attr_23_re;
+ logic mio_pad_attr_23_we;
+ logic mio_pad_attr_23_invert_23_qs;
+ logic mio_pad_attr_23_invert_23_wd;
+ logic mio_pad_attr_23_virtual_od_en_23_qs;
+ logic mio_pad_attr_23_virtual_od_en_23_wd;
+ logic mio_pad_attr_23_pull_en_23_qs;
+ logic mio_pad_attr_23_pull_en_23_wd;
+ logic mio_pad_attr_23_pull_select_23_qs;
+ logic mio_pad_attr_23_pull_select_23_wd;
+ logic mio_pad_attr_23_keeper_en_23_qs;
+ logic mio_pad_attr_23_keeper_en_23_wd;
+ logic mio_pad_attr_23_schmitt_en_23_qs;
+ logic mio_pad_attr_23_schmitt_en_23_wd;
+ logic mio_pad_attr_23_od_en_23_qs;
+ logic mio_pad_attr_23_od_en_23_wd;
+ logic [1:0] mio_pad_attr_23_slew_rate_23_qs;
+ logic [1:0] mio_pad_attr_23_slew_rate_23_wd;
+ logic [3:0] mio_pad_attr_23_drive_strength_23_qs;
+ logic [3:0] mio_pad_attr_23_drive_strength_23_wd;
+ logic mio_pad_attr_24_re;
+ logic mio_pad_attr_24_we;
+ logic mio_pad_attr_24_invert_24_qs;
+ logic mio_pad_attr_24_invert_24_wd;
+ logic mio_pad_attr_24_virtual_od_en_24_qs;
+ logic mio_pad_attr_24_virtual_od_en_24_wd;
+ logic mio_pad_attr_24_pull_en_24_qs;
+ logic mio_pad_attr_24_pull_en_24_wd;
+ logic mio_pad_attr_24_pull_select_24_qs;
+ logic mio_pad_attr_24_pull_select_24_wd;
+ logic mio_pad_attr_24_keeper_en_24_qs;
+ logic mio_pad_attr_24_keeper_en_24_wd;
+ logic mio_pad_attr_24_schmitt_en_24_qs;
+ logic mio_pad_attr_24_schmitt_en_24_wd;
+ logic mio_pad_attr_24_od_en_24_qs;
+ logic mio_pad_attr_24_od_en_24_wd;
+ logic [1:0] mio_pad_attr_24_slew_rate_24_qs;
+ logic [1:0] mio_pad_attr_24_slew_rate_24_wd;
+ logic [3:0] mio_pad_attr_24_drive_strength_24_qs;
+ logic [3:0] mio_pad_attr_24_drive_strength_24_wd;
+ logic mio_pad_attr_25_re;
+ logic mio_pad_attr_25_we;
+ logic mio_pad_attr_25_invert_25_qs;
+ logic mio_pad_attr_25_invert_25_wd;
+ logic mio_pad_attr_25_virtual_od_en_25_qs;
+ logic mio_pad_attr_25_virtual_od_en_25_wd;
+ logic mio_pad_attr_25_pull_en_25_qs;
+ logic mio_pad_attr_25_pull_en_25_wd;
+ logic mio_pad_attr_25_pull_select_25_qs;
+ logic mio_pad_attr_25_pull_select_25_wd;
+ logic mio_pad_attr_25_keeper_en_25_qs;
+ logic mio_pad_attr_25_keeper_en_25_wd;
+ logic mio_pad_attr_25_schmitt_en_25_qs;
+ logic mio_pad_attr_25_schmitt_en_25_wd;
+ logic mio_pad_attr_25_od_en_25_qs;
+ logic mio_pad_attr_25_od_en_25_wd;
+ logic [1:0] mio_pad_attr_25_slew_rate_25_qs;
+ logic [1:0] mio_pad_attr_25_slew_rate_25_wd;
+ logic [3:0] mio_pad_attr_25_drive_strength_25_qs;
+ logic [3:0] mio_pad_attr_25_drive_strength_25_wd;
+ logic mio_pad_attr_26_re;
+ logic mio_pad_attr_26_we;
+ logic mio_pad_attr_26_invert_26_qs;
+ logic mio_pad_attr_26_invert_26_wd;
+ logic mio_pad_attr_26_virtual_od_en_26_qs;
+ logic mio_pad_attr_26_virtual_od_en_26_wd;
+ logic mio_pad_attr_26_pull_en_26_qs;
+ logic mio_pad_attr_26_pull_en_26_wd;
+ logic mio_pad_attr_26_pull_select_26_qs;
+ logic mio_pad_attr_26_pull_select_26_wd;
+ logic mio_pad_attr_26_keeper_en_26_qs;
+ logic mio_pad_attr_26_keeper_en_26_wd;
+ logic mio_pad_attr_26_schmitt_en_26_qs;
+ logic mio_pad_attr_26_schmitt_en_26_wd;
+ logic mio_pad_attr_26_od_en_26_qs;
+ logic mio_pad_attr_26_od_en_26_wd;
+ logic [1:0] mio_pad_attr_26_slew_rate_26_qs;
+ logic [1:0] mio_pad_attr_26_slew_rate_26_wd;
+ logic [3:0] mio_pad_attr_26_drive_strength_26_qs;
+ logic [3:0] mio_pad_attr_26_drive_strength_26_wd;
+ logic mio_pad_attr_27_re;
+ logic mio_pad_attr_27_we;
+ logic mio_pad_attr_27_invert_27_qs;
+ logic mio_pad_attr_27_invert_27_wd;
+ logic mio_pad_attr_27_virtual_od_en_27_qs;
+ logic mio_pad_attr_27_virtual_od_en_27_wd;
+ logic mio_pad_attr_27_pull_en_27_qs;
+ logic mio_pad_attr_27_pull_en_27_wd;
+ logic mio_pad_attr_27_pull_select_27_qs;
+ logic mio_pad_attr_27_pull_select_27_wd;
+ logic mio_pad_attr_27_keeper_en_27_qs;
+ logic mio_pad_attr_27_keeper_en_27_wd;
+ logic mio_pad_attr_27_schmitt_en_27_qs;
+ logic mio_pad_attr_27_schmitt_en_27_wd;
+ logic mio_pad_attr_27_od_en_27_qs;
+ logic mio_pad_attr_27_od_en_27_wd;
+ logic [1:0] mio_pad_attr_27_slew_rate_27_qs;
+ logic [1:0] mio_pad_attr_27_slew_rate_27_wd;
+ logic [3:0] mio_pad_attr_27_drive_strength_27_qs;
+ logic [3:0] mio_pad_attr_27_drive_strength_27_wd;
+ logic mio_pad_attr_28_re;
+ logic mio_pad_attr_28_we;
+ logic mio_pad_attr_28_invert_28_qs;
+ logic mio_pad_attr_28_invert_28_wd;
+ logic mio_pad_attr_28_virtual_od_en_28_qs;
+ logic mio_pad_attr_28_virtual_od_en_28_wd;
+ logic mio_pad_attr_28_pull_en_28_qs;
+ logic mio_pad_attr_28_pull_en_28_wd;
+ logic mio_pad_attr_28_pull_select_28_qs;
+ logic mio_pad_attr_28_pull_select_28_wd;
+ logic mio_pad_attr_28_keeper_en_28_qs;
+ logic mio_pad_attr_28_keeper_en_28_wd;
+ logic mio_pad_attr_28_schmitt_en_28_qs;
+ logic mio_pad_attr_28_schmitt_en_28_wd;
+ logic mio_pad_attr_28_od_en_28_qs;
+ logic mio_pad_attr_28_od_en_28_wd;
+ logic [1:0] mio_pad_attr_28_slew_rate_28_qs;
+ logic [1:0] mio_pad_attr_28_slew_rate_28_wd;
+ logic [3:0] mio_pad_attr_28_drive_strength_28_qs;
+ logic [3:0] mio_pad_attr_28_drive_strength_28_wd;
+ logic mio_pad_attr_29_re;
+ logic mio_pad_attr_29_we;
+ logic mio_pad_attr_29_invert_29_qs;
+ logic mio_pad_attr_29_invert_29_wd;
+ logic mio_pad_attr_29_virtual_od_en_29_qs;
+ logic mio_pad_attr_29_virtual_od_en_29_wd;
+ logic mio_pad_attr_29_pull_en_29_qs;
+ logic mio_pad_attr_29_pull_en_29_wd;
+ logic mio_pad_attr_29_pull_select_29_qs;
+ logic mio_pad_attr_29_pull_select_29_wd;
+ logic mio_pad_attr_29_keeper_en_29_qs;
+ logic mio_pad_attr_29_keeper_en_29_wd;
+ logic mio_pad_attr_29_schmitt_en_29_qs;
+ logic mio_pad_attr_29_schmitt_en_29_wd;
+ logic mio_pad_attr_29_od_en_29_qs;
+ logic mio_pad_attr_29_od_en_29_wd;
+ logic [1:0] mio_pad_attr_29_slew_rate_29_qs;
+ logic [1:0] mio_pad_attr_29_slew_rate_29_wd;
+ logic [3:0] mio_pad_attr_29_drive_strength_29_qs;
+ logic [3:0] mio_pad_attr_29_drive_strength_29_wd;
+ logic mio_pad_attr_30_re;
+ logic mio_pad_attr_30_we;
+ logic mio_pad_attr_30_invert_30_qs;
+ logic mio_pad_attr_30_invert_30_wd;
+ logic mio_pad_attr_30_virtual_od_en_30_qs;
+ logic mio_pad_attr_30_virtual_od_en_30_wd;
+ logic mio_pad_attr_30_pull_en_30_qs;
+ logic mio_pad_attr_30_pull_en_30_wd;
+ logic mio_pad_attr_30_pull_select_30_qs;
+ logic mio_pad_attr_30_pull_select_30_wd;
+ logic mio_pad_attr_30_keeper_en_30_qs;
+ logic mio_pad_attr_30_keeper_en_30_wd;
+ logic mio_pad_attr_30_schmitt_en_30_qs;
+ logic mio_pad_attr_30_schmitt_en_30_wd;
+ logic mio_pad_attr_30_od_en_30_qs;
+ logic mio_pad_attr_30_od_en_30_wd;
+ logic [1:0] mio_pad_attr_30_slew_rate_30_qs;
+ logic [1:0] mio_pad_attr_30_slew_rate_30_wd;
+ logic [3:0] mio_pad_attr_30_drive_strength_30_qs;
+ logic [3:0] mio_pad_attr_30_drive_strength_30_wd;
+ logic mio_pad_attr_31_re;
+ logic mio_pad_attr_31_we;
+ logic mio_pad_attr_31_invert_31_qs;
+ logic mio_pad_attr_31_invert_31_wd;
+ logic mio_pad_attr_31_virtual_od_en_31_qs;
+ logic mio_pad_attr_31_virtual_od_en_31_wd;
+ logic mio_pad_attr_31_pull_en_31_qs;
+ logic mio_pad_attr_31_pull_en_31_wd;
+ logic mio_pad_attr_31_pull_select_31_qs;
+ logic mio_pad_attr_31_pull_select_31_wd;
+ logic mio_pad_attr_31_keeper_en_31_qs;
+ logic mio_pad_attr_31_keeper_en_31_wd;
+ logic mio_pad_attr_31_schmitt_en_31_qs;
+ logic mio_pad_attr_31_schmitt_en_31_wd;
+ logic mio_pad_attr_31_od_en_31_qs;
+ logic mio_pad_attr_31_od_en_31_wd;
+ logic [1:0] mio_pad_attr_31_slew_rate_31_qs;
+ logic [1:0] mio_pad_attr_31_slew_rate_31_wd;
+ logic [3:0] mio_pad_attr_31_drive_strength_31_qs;
+ logic [3:0] mio_pad_attr_31_drive_strength_31_wd;
+ logic mio_pad_attr_32_re;
+ logic mio_pad_attr_32_we;
+ logic mio_pad_attr_32_invert_32_qs;
+ logic mio_pad_attr_32_invert_32_wd;
+ logic mio_pad_attr_32_virtual_od_en_32_qs;
+ logic mio_pad_attr_32_virtual_od_en_32_wd;
+ logic mio_pad_attr_32_pull_en_32_qs;
+ logic mio_pad_attr_32_pull_en_32_wd;
+ logic mio_pad_attr_32_pull_select_32_qs;
+ logic mio_pad_attr_32_pull_select_32_wd;
+ logic mio_pad_attr_32_keeper_en_32_qs;
+ logic mio_pad_attr_32_keeper_en_32_wd;
+ logic mio_pad_attr_32_schmitt_en_32_qs;
+ logic mio_pad_attr_32_schmitt_en_32_wd;
+ logic mio_pad_attr_32_od_en_32_qs;
+ logic mio_pad_attr_32_od_en_32_wd;
+ logic [1:0] mio_pad_attr_32_slew_rate_32_qs;
+ logic [1:0] mio_pad_attr_32_slew_rate_32_wd;
+ logic [3:0] mio_pad_attr_32_drive_strength_32_qs;
+ logic [3:0] mio_pad_attr_32_drive_strength_32_wd;
+ logic mio_pad_attr_33_re;
+ logic mio_pad_attr_33_we;
+ logic mio_pad_attr_33_invert_33_qs;
+ logic mio_pad_attr_33_invert_33_wd;
+ logic mio_pad_attr_33_virtual_od_en_33_qs;
+ logic mio_pad_attr_33_virtual_od_en_33_wd;
+ logic mio_pad_attr_33_pull_en_33_qs;
+ logic mio_pad_attr_33_pull_en_33_wd;
+ logic mio_pad_attr_33_pull_select_33_qs;
+ logic mio_pad_attr_33_pull_select_33_wd;
+ logic mio_pad_attr_33_keeper_en_33_qs;
+ logic mio_pad_attr_33_keeper_en_33_wd;
+ logic mio_pad_attr_33_schmitt_en_33_qs;
+ logic mio_pad_attr_33_schmitt_en_33_wd;
+ logic mio_pad_attr_33_od_en_33_qs;
+ logic mio_pad_attr_33_od_en_33_wd;
+ logic [1:0] mio_pad_attr_33_slew_rate_33_qs;
+ logic [1:0] mio_pad_attr_33_slew_rate_33_wd;
+ logic [3:0] mio_pad_attr_33_drive_strength_33_qs;
+ logic [3:0] mio_pad_attr_33_drive_strength_33_wd;
+ logic mio_pad_attr_34_re;
+ logic mio_pad_attr_34_we;
+ logic mio_pad_attr_34_invert_34_qs;
+ logic mio_pad_attr_34_invert_34_wd;
+ logic mio_pad_attr_34_virtual_od_en_34_qs;
+ logic mio_pad_attr_34_virtual_od_en_34_wd;
+ logic mio_pad_attr_34_pull_en_34_qs;
+ logic mio_pad_attr_34_pull_en_34_wd;
+ logic mio_pad_attr_34_pull_select_34_qs;
+ logic mio_pad_attr_34_pull_select_34_wd;
+ logic mio_pad_attr_34_keeper_en_34_qs;
+ logic mio_pad_attr_34_keeper_en_34_wd;
+ logic mio_pad_attr_34_schmitt_en_34_qs;
+ logic mio_pad_attr_34_schmitt_en_34_wd;
+ logic mio_pad_attr_34_od_en_34_qs;
+ logic mio_pad_attr_34_od_en_34_wd;
+ logic [1:0] mio_pad_attr_34_slew_rate_34_qs;
+ logic [1:0] mio_pad_attr_34_slew_rate_34_wd;
+ logic [3:0] mio_pad_attr_34_drive_strength_34_qs;
+ logic [3:0] mio_pad_attr_34_drive_strength_34_wd;
+ logic mio_pad_attr_35_re;
+ logic mio_pad_attr_35_we;
+ logic mio_pad_attr_35_invert_35_qs;
+ logic mio_pad_attr_35_invert_35_wd;
+ logic mio_pad_attr_35_virtual_od_en_35_qs;
+ logic mio_pad_attr_35_virtual_od_en_35_wd;
+ logic mio_pad_attr_35_pull_en_35_qs;
+ logic mio_pad_attr_35_pull_en_35_wd;
+ logic mio_pad_attr_35_pull_select_35_qs;
+ logic mio_pad_attr_35_pull_select_35_wd;
+ logic mio_pad_attr_35_keeper_en_35_qs;
+ logic mio_pad_attr_35_keeper_en_35_wd;
+ logic mio_pad_attr_35_schmitt_en_35_qs;
+ logic mio_pad_attr_35_schmitt_en_35_wd;
+ logic mio_pad_attr_35_od_en_35_qs;
+ logic mio_pad_attr_35_od_en_35_wd;
+ logic [1:0] mio_pad_attr_35_slew_rate_35_qs;
+ logic [1:0] mio_pad_attr_35_slew_rate_35_wd;
+ logic [3:0] mio_pad_attr_35_drive_strength_35_qs;
+ logic [3:0] mio_pad_attr_35_drive_strength_35_wd;
+ logic mio_pad_attr_36_re;
+ logic mio_pad_attr_36_we;
+ logic mio_pad_attr_36_invert_36_qs;
+ logic mio_pad_attr_36_invert_36_wd;
+ logic mio_pad_attr_36_virtual_od_en_36_qs;
+ logic mio_pad_attr_36_virtual_od_en_36_wd;
+ logic mio_pad_attr_36_pull_en_36_qs;
+ logic mio_pad_attr_36_pull_en_36_wd;
+ logic mio_pad_attr_36_pull_select_36_qs;
+ logic mio_pad_attr_36_pull_select_36_wd;
+ logic mio_pad_attr_36_keeper_en_36_qs;
+ logic mio_pad_attr_36_keeper_en_36_wd;
+ logic mio_pad_attr_36_schmitt_en_36_qs;
+ logic mio_pad_attr_36_schmitt_en_36_wd;
+ logic mio_pad_attr_36_od_en_36_qs;
+ logic mio_pad_attr_36_od_en_36_wd;
+ logic [1:0] mio_pad_attr_36_slew_rate_36_qs;
+ logic [1:0] mio_pad_attr_36_slew_rate_36_wd;
+ logic [3:0] mio_pad_attr_36_drive_strength_36_qs;
+ logic [3:0] mio_pad_attr_36_drive_strength_36_wd;
+ logic mio_pad_attr_37_re;
+ logic mio_pad_attr_37_we;
+ logic mio_pad_attr_37_invert_37_qs;
+ logic mio_pad_attr_37_invert_37_wd;
+ logic mio_pad_attr_37_virtual_od_en_37_qs;
+ logic mio_pad_attr_37_virtual_od_en_37_wd;
+ logic mio_pad_attr_37_pull_en_37_qs;
+ logic mio_pad_attr_37_pull_en_37_wd;
+ logic mio_pad_attr_37_pull_select_37_qs;
+ logic mio_pad_attr_37_pull_select_37_wd;
+ logic mio_pad_attr_37_keeper_en_37_qs;
+ logic mio_pad_attr_37_keeper_en_37_wd;
+ logic mio_pad_attr_37_schmitt_en_37_qs;
+ logic mio_pad_attr_37_schmitt_en_37_wd;
+ logic mio_pad_attr_37_od_en_37_qs;
+ logic mio_pad_attr_37_od_en_37_wd;
+ logic [1:0] mio_pad_attr_37_slew_rate_37_qs;
+ logic [1:0] mio_pad_attr_37_slew_rate_37_wd;
+ logic [3:0] mio_pad_attr_37_drive_strength_37_qs;
+ logic [3:0] mio_pad_attr_37_drive_strength_37_wd;
+ logic mio_pad_attr_38_re;
+ logic mio_pad_attr_38_we;
+ logic mio_pad_attr_38_invert_38_qs;
+ logic mio_pad_attr_38_invert_38_wd;
+ logic mio_pad_attr_38_virtual_od_en_38_qs;
+ logic mio_pad_attr_38_virtual_od_en_38_wd;
+ logic mio_pad_attr_38_pull_en_38_qs;
+ logic mio_pad_attr_38_pull_en_38_wd;
+ logic mio_pad_attr_38_pull_select_38_qs;
+ logic mio_pad_attr_38_pull_select_38_wd;
+ logic mio_pad_attr_38_keeper_en_38_qs;
+ logic mio_pad_attr_38_keeper_en_38_wd;
+ logic mio_pad_attr_38_schmitt_en_38_qs;
+ logic mio_pad_attr_38_schmitt_en_38_wd;
+ logic mio_pad_attr_38_od_en_38_qs;
+ logic mio_pad_attr_38_od_en_38_wd;
+ logic [1:0] mio_pad_attr_38_slew_rate_38_qs;
+ logic [1:0] mio_pad_attr_38_slew_rate_38_wd;
+ logic [3:0] mio_pad_attr_38_drive_strength_38_qs;
+ logic [3:0] mio_pad_attr_38_drive_strength_38_wd;
+ logic mio_pad_attr_39_re;
+ logic mio_pad_attr_39_we;
+ logic mio_pad_attr_39_invert_39_qs;
+ logic mio_pad_attr_39_invert_39_wd;
+ logic mio_pad_attr_39_virtual_od_en_39_qs;
+ logic mio_pad_attr_39_virtual_od_en_39_wd;
+ logic mio_pad_attr_39_pull_en_39_qs;
+ logic mio_pad_attr_39_pull_en_39_wd;
+ logic mio_pad_attr_39_pull_select_39_qs;
+ logic mio_pad_attr_39_pull_select_39_wd;
+ logic mio_pad_attr_39_keeper_en_39_qs;
+ logic mio_pad_attr_39_keeper_en_39_wd;
+ logic mio_pad_attr_39_schmitt_en_39_qs;
+ logic mio_pad_attr_39_schmitt_en_39_wd;
+ logic mio_pad_attr_39_od_en_39_qs;
+ logic mio_pad_attr_39_od_en_39_wd;
+ logic [1:0] mio_pad_attr_39_slew_rate_39_qs;
+ logic [1:0] mio_pad_attr_39_slew_rate_39_wd;
+ logic [3:0] mio_pad_attr_39_drive_strength_39_qs;
+ logic [3:0] mio_pad_attr_39_drive_strength_39_wd;
+ logic mio_pad_attr_40_re;
+ logic mio_pad_attr_40_we;
+ logic mio_pad_attr_40_invert_40_qs;
+ logic mio_pad_attr_40_invert_40_wd;
+ logic mio_pad_attr_40_virtual_od_en_40_qs;
+ logic mio_pad_attr_40_virtual_od_en_40_wd;
+ logic mio_pad_attr_40_pull_en_40_qs;
+ logic mio_pad_attr_40_pull_en_40_wd;
+ logic mio_pad_attr_40_pull_select_40_qs;
+ logic mio_pad_attr_40_pull_select_40_wd;
+ logic mio_pad_attr_40_keeper_en_40_qs;
+ logic mio_pad_attr_40_keeper_en_40_wd;
+ logic mio_pad_attr_40_schmitt_en_40_qs;
+ logic mio_pad_attr_40_schmitt_en_40_wd;
+ logic mio_pad_attr_40_od_en_40_qs;
+ logic mio_pad_attr_40_od_en_40_wd;
+ logic [1:0] mio_pad_attr_40_slew_rate_40_qs;
+ logic [1:0] mio_pad_attr_40_slew_rate_40_wd;
+ logic [3:0] mio_pad_attr_40_drive_strength_40_qs;
+ logic [3:0] mio_pad_attr_40_drive_strength_40_wd;
+ logic mio_pad_attr_41_re;
+ logic mio_pad_attr_41_we;
+ logic mio_pad_attr_41_invert_41_qs;
+ logic mio_pad_attr_41_invert_41_wd;
+ logic mio_pad_attr_41_virtual_od_en_41_qs;
+ logic mio_pad_attr_41_virtual_od_en_41_wd;
+ logic mio_pad_attr_41_pull_en_41_qs;
+ logic mio_pad_attr_41_pull_en_41_wd;
+ logic mio_pad_attr_41_pull_select_41_qs;
+ logic mio_pad_attr_41_pull_select_41_wd;
+ logic mio_pad_attr_41_keeper_en_41_qs;
+ logic mio_pad_attr_41_keeper_en_41_wd;
+ logic mio_pad_attr_41_schmitt_en_41_qs;
+ logic mio_pad_attr_41_schmitt_en_41_wd;
+ logic mio_pad_attr_41_od_en_41_qs;
+ logic mio_pad_attr_41_od_en_41_wd;
+ logic [1:0] mio_pad_attr_41_slew_rate_41_qs;
+ logic [1:0] mio_pad_attr_41_slew_rate_41_wd;
+ logic [3:0] mio_pad_attr_41_drive_strength_41_qs;
+ logic [3:0] mio_pad_attr_41_drive_strength_41_wd;
+ logic mio_pad_attr_42_re;
+ logic mio_pad_attr_42_we;
+ logic mio_pad_attr_42_invert_42_qs;
+ logic mio_pad_attr_42_invert_42_wd;
+ logic mio_pad_attr_42_virtual_od_en_42_qs;
+ logic mio_pad_attr_42_virtual_od_en_42_wd;
+ logic mio_pad_attr_42_pull_en_42_qs;
+ logic mio_pad_attr_42_pull_en_42_wd;
+ logic mio_pad_attr_42_pull_select_42_qs;
+ logic mio_pad_attr_42_pull_select_42_wd;
+ logic mio_pad_attr_42_keeper_en_42_qs;
+ logic mio_pad_attr_42_keeper_en_42_wd;
+ logic mio_pad_attr_42_schmitt_en_42_qs;
+ logic mio_pad_attr_42_schmitt_en_42_wd;
+ logic mio_pad_attr_42_od_en_42_qs;
+ logic mio_pad_attr_42_od_en_42_wd;
+ logic [1:0] mio_pad_attr_42_slew_rate_42_qs;
+ logic [1:0] mio_pad_attr_42_slew_rate_42_wd;
+ logic [3:0] mio_pad_attr_42_drive_strength_42_qs;
+ logic [3:0] mio_pad_attr_42_drive_strength_42_wd;
+ logic mio_pad_attr_43_re;
+ logic mio_pad_attr_43_we;
+ logic mio_pad_attr_43_invert_43_qs;
+ logic mio_pad_attr_43_invert_43_wd;
+ logic mio_pad_attr_43_virtual_od_en_43_qs;
+ logic mio_pad_attr_43_virtual_od_en_43_wd;
+ logic mio_pad_attr_43_pull_en_43_qs;
+ logic mio_pad_attr_43_pull_en_43_wd;
+ logic mio_pad_attr_43_pull_select_43_qs;
+ logic mio_pad_attr_43_pull_select_43_wd;
+ logic mio_pad_attr_43_keeper_en_43_qs;
+ logic mio_pad_attr_43_keeper_en_43_wd;
+ logic mio_pad_attr_43_schmitt_en_43_qs;
+ logic mio_pad_attr_43_schmitt_en_43_wd;
+ logic mio_pad_attr_43_od_en_43_qs;
+ logic mio_pad_attr_43_od_en_43_wd;
+ logic [1:0] mio_pad_attr_43_slew_rate_43_qs;
+ logic [1:0] mio_pad_attr_43_slew_rate_43_wd;
+ logic [3:0] mio_pad_attr_43_drive_strength_43_qs;
+ logic [3:0] mio_pad_attr_43_drive_strength_43_wd;
+ logic mio_pad_attr_44_re;
+ logic mio_pad_attr_44_we;
+ logic mio_pad_attr_44_invert_44_qs;
+ logic mio_pad_attr_44_invert_44_wd;
+ logic mio_pad_attr_44_virtual_od_en_44_qs;
+ logic mio_pad_attr_44_virtual_od_en_44_wd;
+ logic mio_pad_attr_44_pull_en_44_qs;
+ logic mio_pad_attr_44_pull_en_44_wd;
+ logic mio_pad_attr_44_pull_select_44_qs;
+ logic mio_pad_attr_44_pull_select_44_wd;
+ logic mio_pad_attr_44_keeper_en_44_qs;
+ logic mio_pad_attr_44_keeper_en_44_wd;
+ logic mio_pad_attr_44_schmitt_en_44_qs;
+ logic mio_pad_attr_44_schmitt_en_44_wd;
+ logic mio_pad_attr_44_od_en_44_qs;
+ logic mio_pad_attr_44_od_en_44_wd;
+ logic [1:0] mio_pad_attr_44_slew_rate_44_qs;
+ logic [1:0] mio_pad_attr_44_slew_rate_44_wd;
+ logic [3:0] mio_pad_attr_44_drive_strength_44_qs;
+ logic [3:0] mio_pad_attr_44_drive_strength_44_wd;
+ logic mio_pad_attr_45_re;
+ logic mio_pad_attr_45_we;
+ logic mio_pad_attr_45_invert_45_qs;
+ logic mio_pad_attr_45_invert_45_wd;
+ logic mio_pad_attr_45_virtual_od_en_45_qs;
+ logic mio_pad_attr_45_virtual_od_en_45_wd;
+ logic mio_pad_attr_45_pull_en_45_qs;
+ logic mio_pad_attr_45_pull_en_45_wd;
+ logic mio_pad_attr_45_pull_select_45_qs;
+ logic mio_pad_attr_45_pull_select_45_wd;
+ logic mio_pad_attr_45_keeper_en_45_qs;
+ logic mio_pad_attr_45_keeper_en_45_wd;
+ logic mio_pad_attr_45_schmitt_en_45_qs;
+ logic mio_pad_attr_45_schmitt_en_45_wd;
+ logic mio_pad_attr_45_od_en_45_qs;
+ logic mio_pad_attr_45_od_en_45_wd;
+ logic [1:0] mio_pad_attr_45_slew_rate_45_qs;
+ logic [1:0] mio_pad_attr_45_slew_rate_45_wd;
+ logic [3:0] mio_pad_attr_45_drive_strength_45_qs;
+ logic [3:0] mio_pad_attr_45_drive_strength_45_wd;
+ logic mio_pad_attr_46_re;
+ logic mio_pad_attr_46_we;
+ logic mio_pad_attr_46_invert_46_qs;
+ logic mio_pad_attr_46_invert_46_wd;
+ logic mio_pad_attr_46_virtual_od_en_46_qs;
+ logic mio_pad_attr_46_virtual_od_en_46_wd;
+ logic mio_pad_attr_46_pull_en_46_qs;
+ logic mio_pad_attr_46_pull_en_46_wd;
+ logic mio_pad_attr_46_pull_select_46_qs;
+ logic mio_pad_attr_46_pull_select_46_wd;
+ logic mio_pad_attr_46_keeper_en_46_qs;
+ logic mio_pad_attr_46_keeper_en_46_wd;
+ logic mio_pad_attr_46_schmitt_en_46_qs;
+ logic mio_pad_attr_46_schmitt_en_46_wd;
+ logic mio_pad_attr_46_od_en_46_qs;
+ logic mio_pad_attr_46_od_en_46_wd;
+ logic [1:0] mio_pad_attr_46_slew_rate_46_qs;
+ logic [1:0] mio_pad_attr_46_slew_rate_46_wd;
+ logic [3:0] mio_pad_attr_46_drive_strength_46_qs;
+ logic [3:0] mio_pad_attr_46_drive_strength_46_wd;
+ logic mio_pad_attr_47_re;
+ logic mio_pad_attr_47_we;
+ logic mio_pad_attr_47_invert_47_qs;
+ logic mio_pad_attr_47_invert_47_wd;
+ logic mio_pad_attr_47_virtual_od_en_47_qs;
+ logic mio_pad_attr_47_virtual_od_en_47_wd;
+ logic mio_pad_attr_47_pull_en_47_qs;
+ logic mio_pad_attr_47_pull_en_47_wd;
+ logic mio_pad_attr_47_pull_select_47_qs;
+ logic mio_pad_attr_47_pull_select_47_wd;
+ logic mio_pad_attr_47_keeper_en_47_qs;
+ logic mio_pad_attr_47_keeper_en_47_wd;
+ logic mio_pad_attr_47_schmitt_en_47_qs;
+ logic mio_pad_attr_47_schmitt_en_47_wd;
+ logic mio_pad_attr_47_od_en_47_qs;
+ logic mio_pad_attr_47_od_en_47_wd;
+ logic [1:0] mio_pad_attr_47_slew_rate_47_qs;
+ logic [1:0] mio_pad_attr_47_slew_rate_47_wd;
+ logic [3:0] mio_pad_attr_47_drive_strength_47_qs;
+ logic [3:0] mio_pad_attr_47_drive_strength_47_wd;
+ logic mio_pad_attr_48_re;
+ logic mio_pad_attr_48_we;
+ logic mio_pad_attr_48_invert_48_qs;
+ logic mio_pad_attr_48_invert_48_wd;
+ logic mio_pad_attr_48_virtual_od_en_48_qs;
+ logic mio_pad_attr_48_virtual_od_en_48_wd;
+ logic mio_pad_attr_48_pull_en_48_qs;
+ logic mio_pad_attr_48_pull_en_48_wd;
+ logic mio_pad_attr_48_pull_select_48_qs;
+ logic mio_pad_attr_48_pull_select_48_wd;
+ logic mio_pad_attr_48_keeper_en_48_qs;
+ logic mio_pad_attr_48_keeper_en_48_wd;
+ logic mio_pad_attr_48_schmitt_en_48_qs;
+ logic mio_pad_attr_48_schmitt_en_48_wd;
+ logic mio_pad_attr_48_od_en_48_qs;
+ logic mio_pad_attr_48_od_en_48_wd;
+ logic [1:0] mio_pad_attr_48_slew_rate_48_qs;
+ logic [1:0] mio_pad_attr_48_slew_rate_48_wd;
+ logic [3:0] mio_pad_attr_48_drive_strength_48_qs;
+ logic [3:0] mio_pad_attr_48_drive_strength_48_wd;
+ logic mio_pad_attr_49_re;
+ logic mio_pad_attr_49_we;
+ logic mio_pad_attr_49_invert_49_qs;
+ logic mio_pad_attr_49_invert_49_wd;
+ logic mio_pad_attr_49_virtual_od_en_49_qs;
+ logic mio_pad_attr_49_virtual_od_en_49_wd;
+ logic mio_pad_attr_49_pull_en_49_qs;
+ logic mio_pad_attr_49_pull_en_49_wd;
+ logic mio_pad_attr_49_pull_select_49_qs;
+ logic mio_pad_attr_49_pull_select_49_wd;
+ logic mio_pad_attr_49_keeper_en_49_qs;
+ logic mio_pad_attr_49_keeper_en_49_wd;
+ logic mio_pad_attr_49_schmitt_en_49_qs;
+ logic mio_pad_attr_49_schmitt_en_49_wd;
+ logic mio_pad_attr_49_od_en_49_qs;
+ logic mio_pad_attr_49_od_en_49_wd;
+ logic [1:0] mio_pad_attr_49_slew_rate_49_qs;
+ logic [1:0] mio_pad_attr_49_slew_rate_49_wd;
+ logic [3:0] mio_pad_attr_49_drive_strength_49_qs;
+ logic [3:0] mio_pad_attr_49_drive_strength_49_wd;
+ logic mio_pad_attr_50_re;
+ logic mio_pad_attr_50_we;
+ logic mio_pad_attr_50_invert_50_qs;
+ logic mio_pad_attr_50_invert_50_wd;
+ logic mio_pad_attr_50_virtual_od_en_50_qs;
+ logic mio_pad_attr_50_virtual_od_en_50_wd;
+ logic mio_pad_attr_50_pull_en_50_qs;
+ logic mio_pad_attr_50_pull_en_50_wd;
+ logic mio_pad_attr_50_pull_select_50_qs;
+ logic mio_pad_attr_50_pull_select_50_wd;
+ logic mio_pad_attr_50_keeper_en_50_qs;
+ logic mio_pad_attr_50_keeper_en_50_wd;
+ logic mio_pad_attr_50_schmitt_en_50_qs;
+ logic mio_pad_attr_50_schmitt_en_50_wd;
+ logic mio_pad_attr_50_od_en_50_qs;
+ logic mio_pad_attr_50_od_en_50_wd;
+ logic [1:0] mio_pad_attr_50_slew_rate_50_qs;
+ logic [1:0] mio_pad_attr_50_slew_rate_50_wd;
+ logic [3:0] mio_pad_attr_50_drive_strength_50_qs;
+ logic [3:0] mio_pad_attr_50_drive_strength_50_wd;
+ logic mio_pad_attr_51_re;
+ logic mio_pad_attr_51_we;
+ logic mio_pad_attr_51_invert_51_qs;
+ logic mio_pad_attr_51_invert_51_wd;
+ logic mio_pad_attr_51_virtual_od_en_51_qs;
+ logic mio_pad_attr_51_virtual_od_en_51_wd;
+ logic mio_pad_attr_51_pull_en_51_qs;
+ logic mio_pad_attr_51_pull_en_51_wd;
+ logic mio_pad_attr_51_pull_select_51_qs;
+ logic mio_pad_attr_51_pull_select_51_wd;
+ logic mio_pad_attr_51_keeper_en_51_qs;
+ logic mio_pad_attr_51_keeper_en_51_wd;
+ logic mio_pad_attr_51_schmitt_en_51_qs;
+ logic mio_pad_attr_51_schmitt_en_51_wd;
+ logic mio_pad_attr_51_od_en_51_qs;
+ logic mio_pad_attr_51_od_en_51_wd;
+ logic [1:0] mio_pad_attr_51_slew_rate_51_qs;
+ logic [1:0] mio_pad_attr_51_slew_rate_51_wd;
+ logic [3:0] mio_pad_attr_51_drive_strength_51_qs;
+ logic [3:0] mio_pad_attr_51_drive_strength_51_wd;
+ logic mio_pad_attr_52_re;
+ logic mio_pad_attr_52_we;
+ logic mio_pad_attr_52_invert_52_qs;
+ logic mio_pad_attr_52_invert_52_wd;
+ logic mio_pad_attr_52_virtual_od_en_52_qs;
+ logic mio_pad_attr_52_virtual_od_en_52_wd;
+ logic mio_pad_attr_52_pull_en_52_qs;
+ logic mio_pad_attr_52_pull_en_52_wd;
+ logic mio_pad_attr_52_pull_select_52_qs;
+ logic mio_pad_attr_52_pull_select_52_wd;
+ logic mio_pad_attr_52_keeper_en_52_qs;
+ logic mio_pad_attr_52_keeper_en_52_wd;
+ logic mio_pad_attr_52_schmitt_en_52_qs;
+ logic mio_pad_attr_52_schmitt_en_52_wd;
+ logic mio_pad_attr_52_od_en_52_qs;
+ logic mio_pad_attr_52_od_en_52_wd;
+ logic [1:0] mio_pad_attr_52_slew_rate_52_qs;
+ logic [1:0] mio_pad_attr_52_slew_rate_52_wd;
+ logic [3:0] mio_pad_attr_52_drive_strength_52_qs;
+ logic [3:0] mio_pad_attr_52_drive_strength_52_wd;
+ logic dio_pad_attr_regwen_0_we;
+ logic dio_pad_attr_regwen_0_qs;
+ logic dio_pad_attr_regwen_0_wd;
+ logic dio_pad_attr_regwen_1_we;
+ logic dio_pad_attr_regwen_1_qs;
+ logic dio_pad_attr_regwen_1_wd;
+ logic dio_pad_attr_regwen_2_we;
+ logic dio_pad_attr_regwen_2_qs;
+ logic dio_pad_attr_regwen_2_wd;
+ logic dio_pad_attr_regwen_3_we;
+ logic dio_pad_attr_regwen_3_qs;
+ logic dio_pad_attr_regwen_3_wd;
+ logic dio_pad_attr_regwen_4_we;
+ logic dio_pad_attr_regwen_4_qs;
+ logic dio_pad_attr_regwen_4_wd;
+ logic dio_pad_attr_regwen_5_we;
+ logic dio_pad_attr_regwen_5_qs;
+ logic dio_pad_attr_regwen_5_wd;
+ logic dio_pad_attr_regwen_6_we;
+ logic dio_pad_attr_regwen_6_qs;
+ logic dio_pad_attr_regwen_6_wd;
+ logic dio_pad_attr_regwen_7_we;
+ logic dio_pad_attr_regwen_7_qs;
+ logic dio_pad_attr_regwen_7_wd;
+ logic dio_pad_attr_regwen_8_we;
+ logic dio_pad_attr_regwen_8_qs;
+ logic dio_pad_attr_regwen_8_wd;
+ logic dio_pad_attr_regwen_9_we;
+ logic dio_pad_attr_regwen_9_qs;
+ logic dio_pad_attr_regwen_9_wd;
+ logic dio_pad_attr_regwen_10_we;
+ logic dio_pad_attr_regwen_10_qs;
+ logic dio_pad_attr_regwen_10_wd;
+ logic dio_pad_attr_regwen_11_we;
+ logic dio_pad_attr_regwen_11_qs;
+ logic dio_pad_attr_regwen_11_wd;
+ logic dio_pad_attr_regwen_12_we;
+ logic dio_pad_attr_regwen_12_qs;
+ logic dio_pad_attr_regwen_12_wd;
+ logic dio_pad_attr_regwen_13_we;
+ logic dio_pad_attr_regwen_13_qs;
+ logic dio_pad_attr_regwen_13_wd;
+ logic dio_pad_attr_regwen_14_we;
+ logic dio_pad_attr_regwen_14_qs;
+ logic dio_pad_attr_regwen_14_wd;
+ logic dio_pad_attr_regwen_15_we;
+ logic dio_pad_attr_regwen_15_qs;
+ logic dio_pad_attr_regwen_15_wd;
+ logic dio_pad_attr_0_re;
+ logic dio_pad_attr_0_we;
+ logic dio_pad_attr_0_invert_0_qs;
+ logic dio_pad_attr_0_invert_0_wd;
+ logic dio_pad_attr_0_virtual_od_en_0_qs;
+ logic dio_pad_attr_0_virtual_od_en_0_wd;
+ logic dio_pad_attr_0_pull_en_0_qs;
+ logic dio_pad_attr_0_pull_en_0_wd;
+ logic dio_pad_attr_0_pull_select_0_qs;
+ logic dio_pad_attr_0_pull_select_0_wd;
+ logic dio_pad_attr_0_keeper_en_0_qs;
+ logic dio_pad_attr_0_keeper_en_0_wd;
+ logic dio_pad_attr_0_schmitt_en_0_qs;
+ logic dio_pad_attr_0_schmitt_en_0_wd;
+ logic dio_pad_attr_0_od_en_0_qs;
+ logic dio_pad_attr_0_od_en_0_wd;
+ logic [1:0] dio_pad_attr_0_slew_rate_0_qs;
+ logic [1:0] dio_pad_attr_0_slew_rate_0_wd;
+ logic [3:0] dio_pad_attr_0_drive_strength_0_qs;
+ logic [3:0] dio_pad_attr_0_drive_strength_0_wd;
+ logic dio_pad_attr_1_re;
+ logic dio_pad_attr_1_we;
+ logic dio_pad_attr_1_invert_1_qs;
+ logic dio_pad_attr_1_invert_1_wd;
+ logic dio_pad_attr_1_virtual_od_en_1_qs;
+ logic dio_pad_attr_1_virtual_od_en_1_wd;
+ logic dio_pad_attr_1_pull_en_1_qs;
+ logic dio_pad_attr_1_pull_en_1_wd;
+ logic dio_pad_attr_1_pull_select_1_qs;
+ logic dio_pad_attr_1_pull_select_1_wd;
+ logic dio_pad_attr_1_keeper_en_1_qs;
+ logic dio_pad_attr_1_keeper_en_1_wd;
+ logic dio_pad_attr_1_schmitt_en_1_qs;
+ logic dio_pad_attr_1_schmitt_en_1_wd;
+ logic dio_pad_attr_1_od_en_1_qs;
+ logic dio_pad_attr_1_od_en_1_wd;
+ logic [1:0] dio_pad_attr_1_slew_rate_1_qs;
+ logic [1:0] dio_pad_attr_1_slew_rate_1_wd;
+ logic [3:0] dio_pad_attr_1_drive_strength_1_qs;
+ logic [3:0] dio_pad_attr_1_drive_strength_1_wd;
+ logic dio_pad_attr_2_re;
+ logic dio_pad_attr_2_we;
+ logic dio_pad_attr_2_invert_2_qs;
+ logic dio_pad_attr_2_invert_2_wd;
+ logic dio_pad_attr_2_virtual_od_en_2_qs;
+ logic dio_pad_attr_2_virtual_od_en_2_wd;
+ logic dio_pad_attr_2_pull_en_2_qs;
+ logic dio_pad_attr_2_pull_en_2_wd;
+ logic dio_pad_attr_2_pull_select_2_qs;
+ logic dio_pad_attr_2_pull_select_2_wd;
+ logic dio_pad_attr_2_keeper_en_2_qs;
+ logic dio_pad_attr_2_keeper_en_2_wd;
+ logic dio_pad_attr_2_schmitt_en_2_qs;
+ logic dio_pad_attr_2_schmitt_en_2_wd;
+ logic dio_pad_attr_2_od_en_2_qs;
+ logic dio_pad_attr_2_od_en_2_wd;
+ logic [1:0] dio_pad_attr_2_slew_rate_2_qs;
+ logic [1:0] dio_pad_attr_2_slew_rate_2_wd;
+ logic [3:0] dio_pad_attr_2_drive_strength_2_qs;
+ logic [3:0] dio_pad_attr_2_drive_strength_2_wd;
+ logic dio_pad_attr_3_re;
+ logic dio_pad_attr_3_we;
+ logic dio_pad_attr_3_invert_3_qs;
+ logic dio_pad_attr_3_invert_3_wd;
+ logic dio_pad_attr_3_virtual_od_en_3_qs;
+ logic dio_pad_attr_3_virtual_od_en_3_wd;
+ logic dio_pad_attr_3_pull_en_3_qs;
+ logic dio_pad_attr_3_pull_en_3_wd;
+ logic dio_pad_attr_3_pull_select_3_qs;
+ logic dio_pad_attr_3_pull_select_3_wd;
+ logic dio_pad_attr_3_keeper_en_3_qs;
+ logic dio_pad_attr_3_keeper_en_3_wd;
+ logic dio_pad_attr_3_schmitt_en_3_qs;
+ logic dio_pad_attr_3_schmitt_en_3_wd;
+ logic dio_pad_attr_3_od_en_3_qs;
+ logic dio_pad_attr_3_od_en_3_wd;
+ logic [1:0] dio_pad_attr_3_slew_rate_3_qs;
+ logic [1:0] dio_pad_attr_3_slew_rate_3_wd;
+ logic [3:0] dio_pad_attr_3_drive_strength_3_qs;
+ logic [3:0] dio_pad_attr_3_drive_strength_3_wd;
+ logic dio_pad_attr_4_re;
+ logic dio_pad_attr_4_we;
+ logic dio_pad_attr_4_invert_4_qs;
+ logic dio_pad_attr_4_invert_4_wd;
+ logic dio_pad_attr_4_virtual_od_en_4_qs;
+ logic dio_pad_attr_4_virtual_od_en_4_wd;
+ logic dio_pad_attr_4_pull_en_4_qs;
+ logic dio_pad_attr_4_pull_en_4_wd;
+ logic dio_pad_attr_4_pull_select_4_qs;
+ logic dio_pad_attr_4_pull_select_4_wd;
+ logic dio_pad_attr_4_keeper_en_4_qs;
+ logic dio_pad_attr_4_keeper_en_4_wd;
+ logic dio_pad_attr_4_schmitt_en_4_qs;
+ logic dio_pad_attr_4_schmitt_en_4_wd;
+ logic dio_pad_attr_4_od_en_4_qs;
+ logic dio_pad_attr_4_od_en_4_wd;
+ logic [1:0] dio_pad_attr_4_slew_rate_4_qs;
+ logic [1:0] dio_pad_attr_4_slew_rate_4_wd;
+ logic [3:0] dio_pad_attr_4_drive_strength_4_qs;
+ logic [3:0] dio_pad_attr_4_drive_strength_4_wd;
+ logic dio_pad_attr_5_re;
+ logic dio_pad_attr_5_we;
+ logic dio_pad_attr_5_invert_5_qs;
+ logic dio_pad_attr_5_invert_5_wd;
+ logic dio_pad_attr_5_virtual_od_en_5_qs;
+ logic dio_pad_attr_5_virtual_od_en_5_wd;
+ logic dio_pad_attr_5_pull_en_5_qs;
+ logic dio_pad_attr_5_pull_en_5_wd;
+ logic dio_pad_attr_5_pull_select_5_qs;
+ logic dio_pad_attr_5_pull_select_5_wd;
+ logic dio_pad_attr_5_keeper_en_5_qs;
+ logic dio_pad_attr_5_keeper_en_5_wd;
+ logic dio_pad_attr_5_schmitt_en_5_qs;
+ logic dio_pad_attr_5_schmitt_en_5_wd;
+ logic dio_pad_attr_5_od_en_5_qs;
+ logic dio_pad_attr_5_od_en_5_wd;
+ logic [1:0] dio_pad_attr_5_slew_rate_5_qs;
+ logic [1:0] dio_pad_attr_5_slew_rate_5_wd;
+ logic [3:0] dio_pad_attr_5_drive_strength_5_qs;
+ logic [3:0] dio_pad_attr_5_drive_strength_5_wd;
+ logic dio_pad_attr_6_re;
+ logic dio_pad_attr_6_we;
+ logic dio_pad_attr_6_invert_6_qs;
+ logic dio_pad_attr_6_invert_6_wd;
+ logic dio_pad_attr_6_virtual_od_en_6_qs;
+ logic dio_pad_attr_6_virtual_od_en_6_wd;
+ logic dio_pad_attr_6_pull_en_6_qs;
+ logic dio_pad_attr_6_pull_en_6_wd;
+ logic dio_pad_attr_6_pull_select_6_qs;
+ logic dio_pad_attr_6_pull_select_6_wd;
+ logic dio_pad_attr_6_keeper_en_6_qs;
+ logic dio_pad_attr_6_keeper_en_6_wd;
+ logic dio_pad_attr_6_schmitt_en_6_qs;
+ logic dio_pad_attr_6_schmitt_en_6_wd;
+ logic dio_pad_attr_6_od_en_6_qs;
+ logic dio_pad_attr_6_od_en_6_wd;
+ logic [1:0] dio_pad_attr_6_slew_rate_6_qs;
+ logic [1:0] dio_pad_attr_6_slew_rate_6_wd;
+ logic [3:0] dio_pad_attr_6_drive_strength_6_qs;
+ logic [3:0] dio_pad_attr_6_drive_strength_6_wd;
+ logic dio_pad_attr_7_re;
+ logic dio_pad_attr_7_we;
+ logic dio_pad_attr_7_invert_7_qs;
+ logic dio_pad_attr_7_invert_7_wd;
+ logic dio_pad_attr_7_virtual_od_en_7_qs;
+ logic dio_pad_attr_7_virtual_od_en_7_wd;
+ logic dio_pad_attr_7_pull_en_7_qs;
+ logic dio_pad_attr_7_pull_en_7_wd;
+ logic dio_pad_attr_7_pull_select_7_qs;
+ logic dio_pad_attr_7_pull_select_7_wd;
+ logic dio_pad_attr_7_keeper_en_7_qs;
+ logic dio_pad_attr_7_keeper_en_7_wd;
+ logic dio_pad_attr_7_schmitt_en_7_qs;
+ logic dio_pad_attr_7_schmitt_en_7_wd;
+ logic dio_pad_attr_7_od_en_7_qs;
+ logic dio_pad_attr_7_od_en_7_wd;
+ logic [1:0] dio_pad_attr_7_slew_rate_7_qs;
+ logic [1:0] dio_pad_attr_7_slew_rate_7_wd;
+ logic [3:0] dio_pad_attr_7_drive_strength_7_qs;
+ logic [3:0] dio_pad_attr_7_drive_strength_7_wd;
+ logic dio_pad_attr_8_re;
+ logic dio_pad_attr_8_we;
+ logic dio_pad_attr_8_invert_8_qs;
+ logic dio_pad_attr_8_invert_8_wd;
+ logic dio_pad_attr_8_virtual_od_en_8_qs;
+ logic dio_pad_attr_8_virtual_od_en_8_wd;
+ logic dio_pad_attr_8_pull_en_8_qs;
+ logic dio_pad_attr_8_pull_en_8_wd;
+ logic dio_pad_attr_8_pull_select_8_qs;
+ logic dio_pad_attr_8_pull_select_8_wd;
+ logic dio_pad_attr_8_keeper_en_8_qs;
+ logic dio_pad_attr_8_keeper_en_8_wd;
+ logic dio_pad_attr_8_schmitt_en_8_qs;
+ logic dio_pad_attr_8_schmitt_en_8_wd;
+ logic dio_pad_attr_8_od_en_8_qs;
+ logic dio_pad_attr_8_od_en_8_wd;
+ logic [1:0] dio_pad_attr_8_slew_rate_8_qs;
+ logic [1:0] dio_pad_attr_8_slew_rate_8_wd;
+ logic [3:0] dio_pad_attr_8_drive_strength_8_qs;
+ logic [3:0] dio_pad_attr_8_drive_strength_8_wd;
+ logic dio_pad_attr_9_re;
+ logic dio_pad_attr_9_we;
+ logic dio_pad_attr_9_invert_9_qs;
+ logic dio_pad_attr_9_invert_9_wd;
+ logic dio_pad_attr_9_virtual_od_en_9_qs;
+ logic dio_pad_attr_9_virtual_od_en_9_wd;
+ logic dio_pad_attr_9_pull_en_9_qs;
+ logic dio_pad_attr_9_pull_en_9_wd;
+ logic dio_pad_attr_9_pull_select_9_qs;
+ logic dio_pad_attr_9_pull_select_9_wd;
+ logic dio_pad_attr_9_keeper_en_9_qs;
+ logic dio_pad_attr_9_keeper_en_9_wd;
+ logic dio_pad_attr_9_schmitt_en_9_qs;
+ logic dio_pad_attr_9_schmitt_en_9_wd;
+ logic dio_pad_attr_9_od_en_9_qs;
+ logic dio_pad_attr_9_od_en_9_wd;
+ logic [1:0] dio_pad_attr_9_slew_rate_9_qs;
+ logic [1:0] dio_pad_attr_9_slew_rate_9_wd;
+ logic [3:0] dio_pad_attr_9_drive_strength_9_qs;
+ logic [3:0] dio_pad_attr_9_drive_strength_9_wd;
+ logic dio_pad_attr_10_re;
+ logic dio_pad_attr_10_we;
+ logic dio_pad_attr_10_invert_10_qs;
+ logic dio_pad_attr_10_invert_10_wd;
+ logic dio_pad_attr_10_virtual_od_en_10_qs;
+ logic dio_pad_attr_10_virtual_od_en_10_wd;
+ logic dio_pad_attr_10_pull_en_10_qs;
+ logic dio_pad_attr_10_pull_en_10_wd;
+ logic dio_pad_attr_10_pull_select_10_qs;
+ logic dio_pad_attr_10_pull_select_10_wd;
+ logic dio_pad_attr_10_keeper_en_10_qs;
+ logic dio_pad_attr_10_keeper_en_10_wd;
+ logic dio_pad_attr_10_schmitt_en_10_qs;
+ logic dio_pad_attr_10_schmitt_en_10_wd;
+ logic dio_pad_attr_10_od_en_10_qs;
+ logic dio_pad_attr_10_od_en_10_wd;
+ logic [1:0] dio_pad_attr_10_slew_rate_10_qs;
+ logic [1:0] dio_pad_attr_10_slew_rate_10_wd;
+ logic [3:0] dio_pad_attr_10_drive_strength_10_qs;
+ logic [3:0] dio_pad_attr_10_drive_strength_10_wd;
+ logic dio_pad_attr_11_re;
+ logic dio_pad_attr_11_we;
+ logic dio_pad_attr_11_invert_11_qs;
+ logic dio_pad_attr_11_invert_11_wd;
+ logic dio_pad_attr_11_virtual_od_en_11_qs;
+ logic dio_pad_attr_11_virtual_od_en_11_wd;
+ logic dio_pad_attr_11_pull_en_11_qs;
+ logic dio_pad_attr_11_pull_en_11_wd;
+ logic dio_pad_attr_11_pull_select_11_qs;
+ logic dio_pad_attr_11_pull_select_11_wd;
+ logic dio_pad_attr_11_keeper_en_11_qs;
+ logic dio_pad_attr_11_keeper_en_11_wd;
+ logic dio_pad_attr_11_schmitt_en_11_qs;
+ logic dio_pad_attr_11_schmitt_en_11_wd;
+ logic dio_pad_attr_11_od_en_11_qs;
+ logic dio_pad_attr_11_od_en_11_wd;
+ logic [1:0] dio_pad_attr_11_slew_rate_11_qs;
+ logic [1:0] dio_pad_attr_11_slew_rate_11_wd;
+ logic [3:0] dio_pad_attr_11_drive_strength_11_qs;
+ logic [3:0] dio_pad_attr_11_drive_strength_11_wd;
+ logic dio_pad_attr_12_re;
+ logic dio_pad_attr_12_we;
+ logic dio_pad_attr_12_invert_12_qs;
+ logic dio_pad_attr_12_invert_12_wd;
+ logic dio_pad_attr_12_virtual_od_en_12_qs;
+ logic dio_pad_attr_12_virtual_od_en_12_wd;
+ logic dio_pad_attr_12_pull_en_12_qs;
+ logic dio_pad_attr_12_pull_en_12_wd;
+ logic dio_pad_attr_12_pull_select_12_qs;
+ logic dio_pad_attr_12_pull_select_12_wd;
+ logic dio_pad_attr_12_keeper_en_12_qs;
+ logic dio_pad_attr_12_keeper_en_12_wd;
+ logic dio_pad_attr_12_schmitt_en_12_qs;
+ logic dio_pad_attr_12_schmitt_en_12_wd;
+ logic dio_pad_attr_12_od_en_12_qs;
+ logic dio_pad_attr_12_od_en_12_wd;
+ logic [1:0] dio_pad_attr_12_slew_rate_12_qs;
+ logic [1:0] dio_pad_attr_12_slew_rate_12_wd;
+ logic [3:0] dio_pad_attr_12_drive_strength_12_qs;
+ logic [3:0] dio_pad_attr_12_drive_strength_12_wd;
+ logic dio_pad_attr_13_re;
+ logic dio_pad_attr_13_we;
+ logic dio_pad_attr_13_invert_13_qs;
+ logic dio_pad_attr_13_invert_13_wd;
+ logic dio_pad_attr_13_virtual_od_en_13_qs;
+ logic dio_pad_attr_13_virtual_od_en_13_wd;
+ logic dio_pad_attr_13_pull_en_13_qs;
+ logic dio_pad_attr_13_pull_en_13_wd;
+ logic dio_pad_attr_13_pull_select_13_qs;
+ logic dio_pad_attr_13_pull_select_13_wd;
+ logic dio_pad_attr_13_keeper_en_13_qs;
+ logic dio_pad_attr_13_keeper_en_13_wd;
+ logic dio_pad_attr_13_schmitt_en_13_qs;
+ logic dio_pad_attr_13_schmitt_en_13_wd;
+ logic dio_pad_attr_13_od_en_13_qs;
+ logic dio_pad_attr_13_od_en_13_wd;
+ logic [1:0] dio_pad_attr_13_slew_rate_13_qs;
+ logic [1:0] dio_pad_attr_13_slew_rate_13_wd;
+ logic [3:0] dio_pad_attr_13_drive_strength_13_qs;
+ logic [3:0] dio_pad_attr_13_drive_strength_13_wd;
+ logic dio_pad_attr_14_re;
+ logic dio_pad_attr_14_we;
+ logic dio_pad_attr_14_invert_14_qs;
+ logic dio_pad_attr_14_invert_14_wd;
+ logic dio_pad_attr_14_virtual_od_en_14_qs;
+ logic dio_pad_attr_14_virtual_od_en_14_wd;
+ logic dio_pad_attr_14_pull_en_14_qs;
+ logic dio_pad_attr_14_pull_en_14_wd;
+ logic dio_pad_attr_14_pull_select_14_qs;
+ logic dio_pad_attr_14_pull_select_14_wd;
+ logic dio_pad_attr_14_keeper_en_14_qs;
+ logic dio_pad_attr_14_keeper_en_14_wd;
+ logic dio_pad_attr_14_schmitt_en_14_qs;
+ logic dio_pad_attr_14_schmitt_en_14_wd;
+ logic dio_pad_attr_14_od_en_14_qs;
+ logic dio_pad_attr_14_od_en_14_wd;
+ logic [1:0] dio_pad_attr_14_slew_rate_14_qs;
+ logic [1:0] dio_pad_attr_14_slew_rate_14_wd;
+ logic [3:0] dio_pad_attr_14_drive_strength_14_qs;
+ logic [3:0] dio_pad_attr_14_drive_strength_14_wd;
+ logic dio_pad_attr_15_re;
+ logic dio_pad_attr_15_we;
+ logic dio_pad_attr_15_invert_15_qs;
+ logic dio_pad_attr_15_invert_15_wd;
+ logic dio_pad_attr_15_virtual_od_en_15_qs;
+ logic dio_pad_attr_15_virtual_od_en_15_wd;
+ logic dio_pad_attr_15_pull_en_15_qs;
+ logic dio_pad_attr_15_pull_en_15_wd;
+ logic dio_pad_attr_15_pull_select_15_qs;
+ logic dio_pad_attr_15_pull_select_15_wd;
+ logic dio_pad_attr_15_keeper_en_15_qs;
+ logic dio_pad_attr_15_keeper_en_15_wd;
+ logic dio_pad_attr_15_schmitt_en_15_qs;
+ logic dio_pad_attr_15_schmitt_en_15_wd;
+ logic dio_pad_attr_15_od_en_15_qs;
+ logic dio_pad_attr_15_od_en_15_wd;
+ logic [1:0] dio_pad_attr_15_slew_rate_15_qs;
+ logic [1:0] dio_pad_attr_15_slew_rate_15_wd;
+ logic [3:0] dio_pad_attr_15_drive_strength_15_qs;
+ logic [3:0] dio_pad_attr_15_drive_strength_15_wd;
+ logic mio_pad_sleep_status_0_we;
+ logic mio_pad_sleep_status_0_en_0_qs;
+ logic mio_pad_sleep_status_0_en_0_wd;
+ logic mio_pad_sleep_status_0_en_1_qs;
+ logic mio_pad_sleep_status_0_en_1_wd;
+ logic mio_pad_sleep_status_0_en_2_qs;
+ logic mio_pad_sleep_status_0_en_2_wd;
+ logic mio_pad_sleep_status_0_en_3_qs;
+ logic mio_pad_sleep_status_0_en_3_wd;
+ logic mio_pad_sleep_status_0_en_4_qs;
+ logic mio_pad_sleep_status_0_en_4_wd;
+ logic mio_pad_sleep_status_0_en_5_qs;
+ logic mio_pad_sleep_status_0_en_5_wd;
+ logic mio_pad_sleep_status_0_en_6_qs;
+ logic mio_pad_sleep_status_0_en_6_wd;
+ logic mio_pad_sleep_status_0_en_7_qs;
+ logic mio_pad_sleep_status_0_en_7_wd;
+ logic mio_pad_sleep_status_0_en_8_qs;
+ logic mio_pad_sleep_status_0_en_8_wd;
+ logic mio_pad_sleep_status_0_en_9_qs;
+ logic mio_pad_sleep_status_0_en_9_wd;
+ logic mio_pad_sleep_status_0_en_10_qs;
+ logic mio_pad_sleep_status_0_en_10_wd;
+ logic mio_pad_sleep_status_0_en_11_qs;
+ logic mio_pad_sleep_status_0_en_11_wd;
+ logic mio_pad_sleep_status_0_en_12_qs;
+ logic mio_pad_sleep_status_0_en_12_wd;
+ logic mio_pad_sleep_status_0_en_13_qs;
+ logic mio_pad_sleep_status_0_en_13_wd;
+ logic mio_pad_sleep_status_0_en_14_qs;
+ logic mio_pad_sleep_status_0_en_14_wd;
+ logic mio_pad_sleep_status_0_en_15_qs;
+ logic mio_pad_sleep_status_0_en_15_wd;
+ logic mio_pad_sleep_status_0_en_16_qs;
+ logic mio_pad_sleep_status_0_en_16_wd;
+ logic mio_pad_sleep_status_0_en_17_qs;
+ logic mio_pad_sleep_status_0_en_17_wd;
+ logic mio_pad_sleep_status_0_en_18_qs;
+ logic mio_pad_sleep_status_0_en_18_wd;
+ logic mio_pad_sleep_status_0_en_19_qs;
+ logic mio_pad_sleep_status_0_en_19_wd;
+ logic mio_pad_sleep_status_0_en_20_qs;
+ logic mio_pad_sleep_status_0_en_20_wd;
+ logic mio_pad_sleep_status_0_en_21_qs;
+ logic mio_pad_sleep_status_0_en_21_wd;
+ logic mio_pad_sleep_status_0_en_22_qs;
+ logic mio_pad_sleep_status_0_en_22_wd;
+ logic mio_pad_sleep_status_0_en_23_qs;
+ logic mio_pad_sleep_status_0_en_23_wd;
+ logic mio_pad_sleep_status_0_en_24_qs;
+ logic mio_pad_sleep_status_0_en_24_wd;
+ logic mio_pad_sleep_status_0_en_25_qs;
+ logic mio_pad_sleep_status_0_en_25_wd;
+ logic mio_pad_sleep_status_0_en_26_qs;
+ logic mio_pad_sleep_status_0_en_26_wd;
+ logic mio_pad_sleep_status_0_en_27_qs;
+ logic mio_pad_sleep_status_0_en_27_wd;
+ logic mio_pad_sleep_status_0_en_28_qs;
+ logic mio_pad_sleep_status_0_en_28_wd;
+ logic mio_pad_sleep_status_0_en_29_qs;
+ logic mio_pad_sleep_status_0_en_29_wd;
+ logic mio_pad_sleep_status_0_en_30_qs;
+ logic mio_pad_sleep_status_0_en_30_wd;
+ logic mio_pad_sleep_status_0_en_31_qs;
+ logic mio_pad_sleep_status_0_en_31_wd;
+ logic mio_pad_sleep_status_1_we;
+ logic mio_pad_sleep_status_1_en_32_qs;
+ logic mio_pad_sleep_status_1_en_32_wd;
+ logic mio_pad_sleep_status_1_en_33_qs;
+ logic mio_pad_sleep_status_1_en_33_wd;
+ logic mio_pad_sleep_status_1_en_34_qs;
+ logic mio_pad_sleep_status_1_en_34_wd;
+ logic mio_pad_sleep_status_1_en_35_qs;
+ logic mio_pad_sleep_status_1_en_35_wd;
+ logic mio_pad_sleep_status_1_en_36_qs;
+ logic mio_pad_sleep_status_1_en_36_wd;
+ logic mio_pad_sleep_status_1_en_37_qs;
+ logic mio_pad_sleep_status_1_en_37_wd;
+ logic mio_pad_sleep_status_1_en_38_qs;
+ logic mio_pad_sleep_status_1_en_38_wd;
+ logic mio_pad_sleep_status_1_en_39_qs;
+ logic mio_pad_sleep_status_1_en_39_wd;
+ logic mio_pad_sleep_status_1_en_40_qs;
+ logic mio_pad_sleep_status_1_en_40_wd;
+ logic mio_pad_sleep_status_1_en_41_qs;
+ logic mio_pad_sleep_status_1_en_41_wd;
+ logic mio_pad_sleep_status_1_en_42_qs;
+ logic mio_pad_sleep_status_1_en_42_wd;
+ logic mio_pad_sleep_status_1_en_43_qs;
+ logic mio_pad_sleep_status_1_en_43_wd;
+ logic mio_pad_sleep_status_1_en_44_qs;
+ logic mio_pad_sleep_status_1_en_44_wd;
+ logic mio_pad_sleep_status_1_en_45_qs;
+ logic mio_pad_sleep_status_1_en_45_wd;
+ logic mio_pad_sleep_status_1_en_46_qs;
+ logic mio_pad_sleep_status_1_en_46_wd;
+ logic mio_pad_sleep_status_1_en_47_qs;
+ logic mio_pad_sleep_status_1_en_47_wd;
+ logic mio_pad_sleep_status_1_en_48_qs;
+ logic mio_pad_sleep_status_1_en_48_wd;
+ logic mio_pad_sleep_status_1_en_49_qs;
+ logic mio_pad_sleep_status_1_en_49_wd;
+ logic mio_pad_sleep_status_1_en_50_qs;
+ logic mio_pad_sleep_status_1_en_50_wd;
+ logic mio_pad_sleep_status_1_en_51_qs;
+ logic mio_pad_sleep_status_1_en_51_wd;
+ logic mio_pad_sleep_status_1_en_52_qs;
+ logic mio_pad_sleep_status_1_en_52_wd;
+ logic mio_pad_sleep_regwen_0_we;
+ logic mio_pad_sleep_regwen_0_qs;
+ logic mio_pad_sleep_regwen_0_wd;
+ logic mio_pad_sleep_regwen_1_we;
+ logic mio_pad_sleep_regwen_1_qs;
+ logic mio_pad_sleep_regwen_1_wd;
+ logic mio_pad_sleep_regwen_2_we;
+ logic mio_pad_sleep_regwen_2_qs;
+ logic mio_pad_sleep_regwen_2_wd;
+ logic mio_pad_sleep_regwen_3_we;
+ logic mio_pad_sleep_regwen_3_qs;
+ logic mio_pad_sleep_regwen_3_wd;
+ logic mio_pad_sleep_regwen_4_we;
+ logic mio_pad_sleep_regwen_4_qs;
+ logic mio_pad_sleep_regwen_4_wd;
+ logic mio_pad_sleep_regwen_5_we;
+ logic mio_pad_sleep_regwen_5_qs;
+ logic mio_pad_sleep_regwen_5_wd;
+ logic mio_pad_sleep_regwen_6_we;
+ logic mio_pad_sleep_regwen_6_qs;
+ logic mio_pad_sleep_regwen_6_wd;
+ logic mio_pad_sleep_regwen_7_we;
+ logic mio_pad_sleep_regwen_7_qs;
+ logic mio_pad_sleep_regwen_7_wd;
+ logic mio_pad_sleep_regwen_8_we;
+ logic mio_pad_sleep_regwen_8_qs;
+ logic mio_pad_sleep_regwen_8_wd;
+ logic mio_pad_sleep_regwen_9_we;
+ logic mio_pad_sleep_regwen_9_qs;
+ logic mio_pad_sleep_regwen_9_wd;
+ logic mio_pad_sleep_regwen_10_we;
+ logic mio_pad_sleep_regwen_10_qs;
+ logic mio_pad_sleep_regwen_10_wd;
+ logic mio_pad_sleep_regwen_11_we;
+ logic mio_pad_sleep_regwen_11_qs;
+ logic mio_pad_sleep_regwen_11_wd;
+ logic mio_pad_sleep_regwen_12_we;
+ logic mio_pad_sleep_regwen_12_qs;
+ logic mio_pad_sleep_regwen_12_wd;
+ logic mio_pad_sleep_regwen_13_we;
+ logic mio_pad_sleep_regwen_13_qs;
+ logic mio_pad_sleep_regwen_13_wd;
+ logic mio_pad_sleep_regwen_14_we;
+ logic mio_pad_sleep_regwen_14_qs;
+ logic mio_pad_sleep_regwen_14_wd;
+ logic mio_pad_sleep_regwen_15_we;
+ logic mio_pad_sleep_regwen_15_qs;
+ logic mio_pad_sleep_regwen_15_wd;
+ logic mio_pad_sleep_regwen_16_we;
+ logic mio_pad_sleep_regwen_16_qs;
+ logic mio_pad_sleep_regwen_16_wd;
+ logic mio_pad_sleep_regwen_17_we;
+ logic mio_pad_sleep_regwen_17_qs;
+ logic mio_pad_sleep_regwen_17_wd;
+ logic mio_pad_sleep_regwen_18_we;
+ logic mio_pad_sleep_regwen_18_qs;
+ logic mio_pad_sleep_regwen_18_wd;
+ logic mio_pad_sleep_regwen_19_we;
+ logic mio_pad_sleep_regwen_19_qs;
+ logic mio_pad_sleep_regwen_19_wd;
+ logic mio_pad_sleep_regwen_20_we;
+ logic mio_pad_sleep_regwen_20_qs;
+ logic mio_pad_sleep_regwen_20_wd;
+ logic mio_pad_sleep_regwen_21_we;
+ logic mio_pad_sleep_regwen_21_qs;
+ logic mio_pad_sleep_regwen_21_wd;
+ logic mio_pad_sleep_regwen_22_we;
+ logic mio_pad_sleep_regwen_22_qs;
+ logic mio_pad_sleep_regwen_22_wd;
+ logic mio_pad_sleep_regwen_23_we;
+ logic mio_pad_sleep_regwen_23_qs;
+ logic mio_pad_sleep_regwen_23_wd;
+ logic mio_pad_sleep_regwen_24_we;
+ logic mio_pad_sleep_regwen_24_qs;
+ logic mio_pad_sleep_regwen_24_wd;
+ logic mio_pad_sleep_regwen_25_we;
+ logic mio_pad_sleep_regwen_25_qs;
+ logic mio_pad_sleep_regwen_25_wd;
+ logic mio_pad_sleep_regwen_26_we;
+ logic mio_pad_sleep_regwen_26_qs;
+ logic mio_pad_sleep_regwen_26_wd;
+ logic mio_pad_sleep_regwen_27_we;
+ logic mio_pad_sleep_regwen_27_qs;
+ logic mio_pad_sleep_regwen_27_wd;
+ logic mio_pad_sleep_regwen_28_we;
+ logic mio_pad_sleep_regwen_28_qs;
+ logic mio_pad_sleep_regwen_28_wd;
+ logic mio_pad_sleep_regwen_29_we;
+ logic mio_pad_sleep_regwen_29_qs;
+ logic mio_pad_sleep_regwen_29_wd;
+ logic mio_pad_sleep_regwen_30_we;
+ logic mio_pad_sleep_regwen_30_qs;
+ logic mio_pad_sleep_regwen_30_wd;
+ logic mio_pad_sleep_regwen_31_we;
+ logic mio_pad_sleep_regwen_31_qs;
+ logic mio_pad_sleep_regwen_31_wd;
+ logic mio_pad_sleep_regwen_32_we;
+ logic mio_pad_sleep_regwen_32_qs;
+ logic mio_pad_sleep_regwen_32_wd;
+ logic mio_pad_sleep_regwen_33_we;
+ logic mio_pad_sleep_regwen_33_qs;
+ logic mio_pad_sleep_regwen_33_wd;
+ logic mio_pad_sleep_regwen_34_we;
+ logic mio_pad_sleep_regwen_34_qs;
+ logic mio_pad_sleep_regwen_34_wd;
+ logic mio_pad_sleep_regwen_35_we;
+ logic mio_pad_sleep_regwen_35_qs;
+ logic mio_pad_sleep_regwen_35_wd;
+ logic mio_pad_sleep_regwen_36_we;
+ logic mio_pad_sleep_regwen_36_qs;
+ logic mio_pad_sleep_regwen_36_wd;
+ logic mio_pad_sleep_regwen_37_we;
+ logic mio_pad_sleep_regwen_37_qs;
+ logic mio_pad_sleep_regwen_37_wd;
+ logic mio_pad_sleep_regwen_38_we;
+ logic mio_pad_sleep_regwen_38_qs;
+ logic mio_pad_sleep_regwen_38_wd;
+ logic mio_pad_sleep_regwen_39_we;
+ logic mio_pad_sleep_regwen_39_qs;
+ logic mio_pad_sleep_regwen_39_wd;
+ logic mio_pad_sleep_regwen_40_we;
+ logic mio_pad_sleep_regwen_40_qs;
+ logic mio_pad_sleep_regwen_40_wd;
+ logic mio_pad_sleep_regwen_41_we;
+ logic mio_pad_sleep_regwen_41_qs;
+ logic mio_pad_sleep_regwen_41_wd;
+ logic mio_pad_sleep_regwen_42_we;
+ logic mio_pad_sleep_regwen_42_qs;
+ logic mio_pad_sleep_regwen_42_wd;
+ logic mio_pad_sleep_regwen_43_we;
+ logic mio_pad_sleep_regwen_43_qs;
+ logic mio_pad_sleep_regwen_43_wd;
+ logic mio_pad_sleep_regwen_44_we;
+ logic mio_pad_sleep_regwen_44_qs;
+ logic mio_pad_sleep_regwen_44_wd;
+ logic mio_pad_sleep_regwen_45_we;
+ logic mio_pad_sleep_regwen_45_qs;
+ logic mio_pad_sleep_regwen_45_wd;
+ logic mio_pad_sleep_regwen_46_we;
+ logic mio_pad_sleep_regwen_46_qs;
+ logic mio_pad_sleep_regwen_46_wd;
+ logic mio_pad_sleep_regwen_47_we;
+ logic mio_pad_sleep_regwen_47_qs;
+ logic mio_pad_sleep_regwen_47_wd;
+ logic mio_pad_sleep_regwen_48_we;
+ logic mio_pad_sleep_regwen_48_qs;
+ logic mio_pad_sleep_regwen_48_wd;
+ logic mio_pad_sleep_regwen_49_we;
+ logic mio_pad_sleep_regwen_49_qs;
+ logic mio_pad_sleep_regwen_49_wd;
+ logic mio_pad_sleep_regwen_50_we;
+ logic mio_pad_sleep_regwen_50_qs;
+ logic mio_pad_sleep_regwen_50_wd;
+ logic mio_pad_sleep_regwen_51_we;
+ logic mio_pad_sleep_regwen_51_qs;
+ logic mio_pad_sleep_regwen_51_wd;
+ logic mio_pad_sleep_regwen_52_we;
+ logic mio_pad_sleep_regwen_52_qs;
+ logic mio_pad_sleep_regwen_52_wd;
+ logic mio_pad_sleep_en_0_we;
+ logic mio_pad_sleep_en_0_qs;
+ logic mio_pad_sleep_en_0_wd;
+ logic mio_pad_sleep_en_1_we;
+ logic mio_pad_sleep_en_1_qs;
+ logic mio_pad_sleep_en_1_wd;
+ logic mio_pad_sleep_en_2_we;
+ logic mio_pad_sleep_en_2_qs;
+ logic mio_pad_sleep_en_2_wd;
+ logic mio_pad_sleep_en_3_we;
+ logic mio_pad_sleep_en_3_qs;
+ logic mio_pad_sleep_en_3_wd;
+ logic mio_pad_sleep_en_4_we;
+ logic mio_pad_sleep_en_4_qs;
+ logic mio_pad_sleep_en_4_wd;
+ logic mio_pad_sleep_en_5_we;
+ logic mio_pad_sleep_en_5_qs;
+ logic mio_pad_sleep_en_5_wd;
+ logic mio_pad_sleep_en_6_we;
+ logic mio_pad_sleep_en_6_qs;
+ logic mio_pad_sleep_en_6_wd;
+ logic mio_pad_sleep_en_7_we;
+ logic mio_pad_sleep_en_7_qs;
+ logic mio_pad_sleep_en_7_wd;
+ logic mio_pad_sleep_en_8_we;
+ logic mio_pad_sleep_en_8_qs;
+ logic mio_pad_sleep_en_8_wd;
+ logic mio_pad_sleep_en_9_we;
+ logic mio_pad_sleep_en_9_qs;
+ logic mio_pad_sleep_en_9_wd;
+ logic mio_pad_sleep_en_10_we;
+ logic mio_pad_sleep_en_10_qs;
+ logic mio_pad_sleep_en_10_wd;
+ logic mio_pad_sleep_en_11_we;
+ logic mio_pad_sleep_en_11_qs;
+ logic mio_pad_sleep_en_11_wd;
+ logic mio_pad_sleep_en_12_we;
+ logic mio_pad_sleep_en_12_qs;
+ logic mio_pad_sleep_en_12_wd;
+ logic mio_pad_sleep_en_13_we;
+ logic mio_pad_sleep_en_13_qs;
+ logic mio_pad_sleep_en_13_wd;
+ logic mio_pad_sleep_en_14_we;
+ logic mio_pad_sleep_en_14_qs;
+ logic mio_pad_sleep_en_14_wd;
+ logic mio_pad_sleep_en_15_we;
+ logic mio_pad_sleep_en_15_qs;
+ logic mio_pad_sleep_en_15_wd;
+ logic mio_pad_sleep_en_16_we;
+ logic mio_pad_sleep_en_16_qs;
+ logic mio_pad_sleep_en_16_wd;
+ logic mio_pad_sleep_en_17_we;
+ logic mio_pad_sleep_en_17_qs;
+ logic mio_pad_sleep_en_17_wd;
+ logic mio_pad_sleep_en_18_we;
+ logic mio_pad_sleep_en_18_qs;
+ logic mio_pad_sleep_en_18_wd;
+ logic mio_pad_sleep_en_19_we;
+ logic mio_pad_sleep_en_19_qs;
+ logic mio_pad_sleep_en_19_wd;
+ logic mio_pad_sleep_en_20_we;
+ logic mio_pad_sleep_en_20_qs;
+ logic mio_pad_sleep_en_20_wd;
+ logic mio_pad_sleep_en_21_we;
+ logic mio_pad_sleep_en_21_qs;
+ logic mio_pad_sleep_en_21_wd;
+ logic mio_pad_sleep_en_22_we;
+ logic mio_pad_sleep_en_22_qs;
+ logic mio_pad_sleep_en_22_wd;
+ logic mio_pad_sleep_en_23_we;
+ logic mio_pad_sleep_en_23_qs;
+ logic mio_pad_sleep_en_23_wd;
+ logic mio_pad_sleep_en_24_we;
+ logic mio_pad_sleep_en_24_qs;
+ logic mio_pad_sleep_en_24_wd;
+ logic mio_pad_sleep_en_25_we;
+ logic mio_pad_sleep_en_25_qs;
+ logic mio_pad_sleep_en_25_wd;
+ logic mio_pad_sleep_en_26_we;
+ logic mio_pad_sleep_en_26_qs;
+ logic mio_pad_sleep_en_26_wd;
+ logic mio_pad_sleep_en_27_we;
+ logic mio_pad_sleep_en_27_qs;
+ logic mio_pad_sleep_en_27_wd;
+ logic mio_pad_sleep_en_28_we;
+ logic mio_pad_sleep_en_28_qs;
+ logic mio_pad_sleep_en_28_wd;
+ logic mio_pad_sleep_en_29_we;
+ logic mio_pad_sleep_en_29_qs;
+ logic mio_pad_sleep_en_29_wd;
+ logic mio_pad_sleep_en_30_we;
+ logic mio_pad_sleep_en_30_qs;
+ logic mio_pad_sleep_en_30_wd;
+ logic mio_pad_sleep_en_31_we;
+ logic mio_pad_sleep_en_31_qs;
+ logic mio_pad_sleep_en_31_wd;
+ logic mio_pad_sleep_en_32_we;
+ logic mio_pad_sleep_en_32_qs;
+ logic mio_pad_sleep_en_32_wd;
+ logic mio_pad_sleep_en_33_we;
+ logic mio_pad_sleep_en_33_qs;
+ logic mio_pad_sleep_en_33_wd;
+ logic mio_pad_sleep_en_34_we;
+ logic mio_pad_sleep_en_34_qs;
+ logic mio_pad_sleep_en_34_wd;
+ logic mio_pad_sleep_en_35_we;
+ logic mio_pad_sleep_en_35_qs;
+ logic mio_pad_sleep_en_35_wd;
+ logic mio_pad_sleep_en_36_we;
+ logic mio_pad_sleep_en_36_qs;
+ logic mio_pad_sleep_en_36_wd;
+ logic mio_pad_sleep_en_37_we;
+ logic mio_pad_sleep_en_37_qs;
+ logic mio_pad_sleep_en_37_wd;
+ logic mio_pad_sleep_en_38_we;
+ logic mio_pad_sleep_en_38_qs;
+ logic mio_pad_sleep_en_38_wd;
+ logic mio_pad_sleep_en_39_we;
+ logic mio_pad_sleep_en_39_qs;
+ logic mio_pad_sleep_en_39_wd;
+ logic mio_pad_sleep_en_40_we;
+ logic mio_pad_sleep_en_40_qs;
+ logic mio_pad_sleep_en_40_wd;
+ logic mio_pad_sleep_en_41_we;
+ logic mio_pad_sleep_en_41_qs;
+ logic mio_pad_sleep_en_41_wd;
+ logic mio_pad_sleep_en_42_we;
+ logic mio_pad_sleep_en_42_qs;
+ logic mio_pad_sleep_en_42_wd;
+ logic mio_pad_sleep_en_43_we;
+ logic mio_pad_sleep_en_43_qs;
+ logic mio_pad_sleep_en_43_wd;
+ logic mio_pad_sleep_en_44_we;
+ logic mio_pad_sleep_en_44_qs;
+ logic mio_pad_sleep_en_44_wd;
+ logic mio_pad_sleep_en_45_we;
+ logic mio_pad_sleep_en_45_qs;
+ logic mio_pad_sleep_en_45_wd;
+ logic mio_pad_sleep_en_46_we;
+ logic mio_pad_sleep_en_46_qs;
+ logic mio_pad_sleep_en_46_wd;
+ logic mio_pad_sleep_en_47_we;
+ logic mio_pad_sleep_en_47_qs;
+ logic mio_pad_sleep_en_47_wd;
+ logic mio_pad_sleep_en_48_we;
+ logic mio_pad_sleep_en_48_qs;
+ logic mio_pad_sleep_en_48_wd;
+ logic mio_pad_sleep_en_49_we;
+ logic mio_pad_sleep_en_49_qs;
+ logic mio_pad_sleep_en_49_wd;
+ logic mio_pad_sleep_en_50_we;
+ logic mio_pad_sleep_en_50_qs;
+ logic mio_pad_sleep_en_50_wd;
+ logic mio_pad_sleep_en_51_we;
+ logic mio_pad_sleep_en_51_qs;
+ logic mio_pad_sleep_en_51_wd;
+ logic mio_pad_sleep_en_52_we;
+ logic mio_pad_sleep_en_52_qs;
+ logic mio_pad_sleep_en_52_wd;
+ logic mio_pad_sleep_mode_0_we;
+ logic [1:0] mio_pad_sleep_mode_0_qs;
+ logic [1:0] mio_pad_sleep_mode_0_wd;
+ logic mio_pad_sleep_mode_1_we;
+ logic [1:0] mio_pad_sleep_mode_1_qs;
+ logic [1:0] mio_pad_sleep_mode_1_wd;
+ logic mio_pad_sleep_mode_2_we;
+ logic [1:0] mio_pad_sleep_mode_2_qs;
+ logic [1:0] mio_pad_sleep_mode_2_wd;
+ logic mio_pad_sleep_mode_3_we;
+ logic [1:0] mio_pad_sleep_mode_3_qs;
+ logic [1:0] mio_pad_sleep_mode_3_wd;
+ logic mio_pad_sleep_mode_4_we;
+ logic [1:0] mio_pad_sleep_mode_4_qs;
+ logic [1:0] mio_pad_sleep_mode_4_wd;
+ logic mio_pad_sleep_mode_5_we;
+ logic [1:0] mio_pad_sleep_mode_5_qs;
+ logic [1:0] mio_pad_sleep_mode_5_wd;
+ logic mio_pad_sleep_mode_6_we;
+ logic [1:0] mio_pad_sleep_mode_6_qs;
+ logic [1:0] mio_pad_sleep_mode_6_wd;
+ logic mio_pad_sleep_mode_7_we;
+ logic [1:0] mio_pad_sleep_mode_7_qs;
+ logic [1:0] mio_pad_sleep_mode_7_wd;
+ logic mio_pad_sleep_mode_8_we;
+ logic [1:0] mio_pad_sleep_mode_8_qs;
+ logic [1:0] mio_pad_sleep_mode_8_wd;
+ logic mio_pad_sleep_mode_9_we;
+ logic [1:0] mio_pad_sleep_mode_9_qs;
+ logic [1:0] mio_pad_sleep_mode_9_wd;
+ logic mio_pad_sleep_mode_10_we;
+ logic [1:0] mio_pad_sleep_mode_10_qs;
+ logic [1:0] mio_pad_sleep_mode_10_wd;
+ logic mio_pad_sleep_mode_11_we;
+ logic [1:0] mio_pad_sleep_mode_11_qs;
+ logic [1:0] mio_pad_sleep_mode_11_wd;
+ logic mio_pad_sleep_mode_12_we;
+ logic [1:0] mio_pad_sleep_mode_12_qs;
+ logic [1:0] mio_pad_sleep_mode_12_wd;
+ logic mio_pad_sleep_mode_13_we;
+ logic [1:0] mio_pad_sleep_mode_13_qs;
+ logic [1:0] mio_pad_sleep_mode_13_wd;
+ logic mio_pad_sleep_mode_14_we;
+ logic [1:0] mio_pad_sleep_mode_14_qs;
+ logic [1:0] mio_pad_sleep_mode_14_wd;
+ logic mio_pad_sleep_mode_15_we;
+ logic [1:0] mio_pad_sleep_mode_15_qs;
+ logic [1:0] mio_pad_sleep_mode_15_wd;
+ logic mio_pad_sleep_mode_16_we;
+ logic [1:0] mio_pad_sleep_mode_16_qs;
+ logic [1:0] mio_pad_sleep_mode_16_wd;
+ logic mio_pad_sleep_mode_17_we;
+ logic [1:0] mio_pad_sleep_mode_17_qs;
+ logic [1:0] mio_pad_sleep_mode_17_wd;
+ logic mio_pad_sleep_mode_18_we;
+ logic [1:0] mio_pad_sleep_mode_18_qs;
+ logic [1:0] mio_pad_sleep_mode_18_wd;
+ logic mio_pad_sleep_mode_19_we;
+ logic [1:0] mio_pad_sleep_mode_19_qs;
+ logic [1:0] mio_pad_sleep_mode_19_wd;
+ logic mio_pad_sleep_mode_20_we;
+ logic [1:0] mio_pad_sleep_mode_20_qs;
+ logic [1:0] mio_pad_sleep_mode_20_wd;
+ logic mio_pad_sleep_mode_21_we;
+ logic [1:0] mio_pad_sleep_mode_21_qs;
+ logic [1:0] mio_pad_sleep_mode_21_wd;
+ logic mio_pad_sleep_mode_22_we;
+ logic [1:0] mio_pad_sleep_mode_22_qs;
+ logic [1:0] mio_pad_sleep_mode_22_wd;
+ logic mio_pad_sleep_mode_23_we;
+ logic [1:0] mio_pad_sleep_mode_23_qs;
+ logic [1:0] mio_pad_sleep_mode_23_wd;
+ logic mio_pad_sleep_mode_24_we;
+ logic [1:0] mio_pad_sleep_mode_24_qs;
+ logic [1:0] mio_pad_sleep_mode_24_wd;
+ logic mio_pad_sleep_mode_25_we;
+ logic [1:0] mio_pad_sleep_mode_25_qs;
+ logic [1:0] mio_pad_sleep_mode_25_wd;
+ logic mio_pad_sleep_mode_26_we;
+ logic [1:0] mio_pad_sleep_mode_26_qs;
+ logic [1:0] mio_pad_sleep_mode_26_wd;
+ logic mio_pad_sleep_mode_27_we;
+ logic [1:0] mio_pad_sleep_mode_27_qs;
+ logic [1:0] mio_pad_sleep_mode_27_wd;
+ logic mio_pad_sleep_mode_28_we;
+ logic [1:0] mio_pad_sleep_mode_28_qs;
+ logic [1:0] mio_pad_sleep_mode_28_wd;
+ logic mio_pad_sleep_mode_29_we;
+ logic [1:0] mio_pad_sleep_mode_29_qs;
+ logic [1:0] mio_pad_sleep_mode_29_wd;
+ logic mio_pad_sleep_mode_30_we;
+ logic [1:0] mio_pad_sleep_mode_30_qs;
+ logic [1:0] mio_pad_sleep_mode_30_wd;
+ logic mio_pad_sleep_mode_31_we;
+ logic [1:0] mio_pad_sleep_mode_31_qs;
+ logic [1:0] mio_pad_sleep_mode_31_wd;
+ logic mio_pad_sleep_mode_32_we;
+ logic [1:0] mio_pad_sleep_mode_32_qs;
+ logic [1:0] mio_pad_sleep_mode_32_wd;
+ logic mio_pad_sleep_mode_33_we;
+ logic [1:0] mio_pad_sleep_mode_33_qs;
+ logic [1:0] mio_pad_sleep_mode_33_wd;
+ logic mio_pad_sleep_mode_34_we;
+ logic [1:0] mio_pad_sleep_mode_34_qs;
+ logic [1:0] mio_pad_sleep_mode_34_wd;
+ logic mio_pad_sleep_mode_35_we;
+ logic [1:0] mio_pad_sleep_mode_35_qs;
+ logic [1:0] mio_pad_sleep_mode_35_wd;
+ logic mio_pad_sleep_mode_36_we;
+ logic [1:0] mio_pad_sleep_mode_36_qs;
+ logic [1:0] mio_pad_sleep_mode_36_wd;
+ logic mio_pad_sleep_mode_37_we;
+ logic [1:0] mio_pad_sleep_mode_37_qs;
+ logic [1:0] mio_pad_sleep_mode_37_wd;
+ logic mio_pad_sleep_mode_38_we;
+ logic [1:0] mio_pad_sleep_mode_38_qs;
+ logic [1:0] mio_pad_sleep_mode_38_wd;
+ logic mio_pad_sleep_mode_39_we;
+ logic [1:0] mio_pad_sleep_mode_39_qs;
+ logic [1:0] mio_pad_sleep_mode_39_wd;
+ logic mio_pad_sleep_mode_40_we;
+ logic [1:0] mio_pad_sleep_mode_40_qs;
+ logic [1:0] mio_pad_sleep_mode_40_wd;
+ logic mio_pad_sleep_mode_41_we;
+ logic [1:0] mio_pad_sleep_mode_41_qs;
+ logic [1:0] mio_pad_sleep_mode_41_wd;
+ logic mio_pad_sleep_mode_42_we;
+ logic [1:0] mio_pad_sleep_mode_42_qs;
+ logic [1:0] mio_pad_sleep_mode_42_wd;
+ logic mio_pad_sleep_mode_43_we;
+ logic [1:0] mio_pad_sleep_mode_43_qs;
+ logic [1:0] mio_pad_sleep_mode_43_wd;
+ logic mio_pad_sleep_mode_44_we;
+ logic [1:0] mio_pad_sleep_mode_44_qs;
+ logic [1:0] mio_pad_sleep_mode_44_wd;
+ logic mio_pad_sleep_mode_45_we;
+ logic [1:0] mio_pad_sleep_mode_45_qs;
+ logic [1:0] mio_pad_sleep_mode_45_wd;
+ logic mio_pad_sleep_mode_46_we;
+ logic [1:0] mio_pad_sleep_mode_46_qs;
+ logic [1:0] mio_pad_sleep_mode_46_wd;
+ logic mio_pad_sleep_mode_47_we;
+ logic [1:0] mio_pad_sleep_mode_47_qs;
+ logic [1:0] mio_pad_sleep_mode_47_wd;
+ logic mio_pad_sleep_mode_48_we;
+ logic [1:0] mio_pad_sleep_mode_48_qs;
+ logic [1:0] mio_pad_sleep_mode_48_wd;
+ logic mio_pad_sleep_mode_49_we;
+ logic [1:0] mio_pad_sleep_mode_49_qs;
+ logic [1:0] mio_pad_sleep_mode_49_wd;
+ logic mio_pad_sleep_mode_50_we;
+ logic [1:0] mio_pad_sleep_mode_50_qs;
+ logic [1:0] mio_pad_sleep_mode_50_wd;
+ logic mio_pad_sleep_mode_51_we;
+ logic [1:0] mio_pad_sleep_mode_51_qs;
+ logic [1:0] mio_pad_sleep_mode_51_wd;
+ logic mio_pad_sleep_mode_52_we;
+ logic [1:0] mio_pad_sleep_mode_52_qs;
+ logic [1:0] mio_pad_sleep_mode_52_wd;
+ logic dio_pad_sleep_status_we;
+ logic dio_pad_sleep_status_en_0_qs;
+ logic dio_pad_sleep_status_en_0_wd;
+ logic dio_pad_sleep_status_en_1_qs;
+ logic dio_pad_sleep_status_en_1_wd;
+ logic dio_pad_sleep_status_en_2_qs;
+ logic dio_pad_sleep_status_en_2_wd;
+ logic dio_pad_sleep_status_en_3_qs;
+ logic dio_pad_sleep_status_en_3_wd;
+ logic dio_pad_sleep_status_en_4_qs;
+ logic dio_pad_sleep_status_en_4_wd;
+ logic dio_pad_sleep_status_en_5_qs;
+ logic dio_pad_sleep_status_en_5_wd;
+ logic dio_pad_sleep_status_en_6_qs;
+ logic dio_pad_sleep_status_en_6_wd;
+ logic dio_pad_sleep_status_en_7_qs;
+ logic dio_pad_sleep_status_en_7_wd;
+ logic dio_pad_sleep_status_en_8_qs;
+ logic dio_pad_sleep_status_en_8_wd;
+ logic dio_pad_sleep_status_en_9_qs;
+ logic dio_pad_sleep_status_en_9_wd;
+ logic dio_pad_sleep_status_en_10_qs;
+ logic dio_pad_sleep_status_en_10_wd;
+ logic dio_pad_sleep_status_en_11_qs;
+ logic dio_pad_sleep_status_en_11_wd;
+ logic dio_pad_sleep_status_en_12_qs;
+ logic dio_pad_sleep_status_en_12_wd;
+ logic dio_pad_sleep_status_en_13_qs;
+ logic dio_pad_sleep_status_en_13_wd;
+ logic dio_pad_sleep_status_en_14_qs;
+ logic dio_pad_sleep_status_en_14_wd;
+ logic dio_pad_sleep_status_en_15_qs;
+ logic dio_pad_sleep_status_en_15_wd;
+ logic dio_pad_sleep_regwen_0_we;
+ logic dio_pad_sleep_regwen_0_qs;
+ logic dio_pad_sleep_regwen_0_wd;
+ logic dio_pad_sleep_regwen_1_we;
+ logic dio_pad_sleep_regwen_1_qs;
+ logic dio_pad_sleep_regwen_1_wd;
+ logic dio_pad_sleep_regwen_2_we;
+ logic dio_pad_sleep_regwen_2_qs;
+ logic dio_pad_sleep_regwen_2_wd;
+ logic dio_pad_sleep_regwen_3_we;
+ logic dio_pad_sleep_regwen_3_qs;
+ logic dio_pad_sleep_regwen_3_wd;
+ logic dio_pad_sleep_regwen_4_we;
+ logic dio_pad_sleep_regwen_4_qs;
+ logic dio_pad_sleep_regwen_4_wd;
+ logic dio_pad_sleep_regwen_5_we;
+ logic dio_pad_sleep_regwen_5_qs;
+ logic dio_pad_sleep_regwen_5_wd;
+ logic dio_pad_sleep_regwen_6_we;
+ logic dio_pad_sleep_regwen_6_qs;
+ logic dio_pad_sleep_regwen_6_wd;
+ logic dio_pad_sleep_regwen_7_we;
+ logic dio_pad_sleep_regwen_7_qs;
+ logic dio_pad_sleep_regwen_7_wd;
+ logic dio_pad_sleep_regwen_8_we;
+ logic dio_pad_sleep_regwen_8_qs;
+ logic dio_pad_sleep_regwen_8_wd;
+ logic dio_pad_sleep_regwen_9_we;
+ logic dio_pad_sleep_regwen_9_qs;
+ logic dio_pad_sleep_regwen_9_wd;
+ logic dio_pad_sleep_regwen_10_we;
+ logic dio_pad_sleep_regwen_10_qs;
+ logic dio_pad_sleep_regwen_10_wd;
+ logic dio_pad_sleep_regwen_11_we;
+ logic dio_pad_sleep_regwen_11_qs;
+ logic dio_pad_sleep_regwen_11_wd;
+ logic dio_pad_sleep_regwen_12_we;
+ logic dio_pad_sleep_regwen_12_qs;
+ logic dio_pad_sleep_regwen_12_wd;
+ logic dio_pad_sleep_regwen_13_we;
+ logic dio_pad_sleep_regwen_13_qs;
+ logic dio_pad_sleep_regwen_13_wd;
+ logic dio_pad_sleep_regwen_14_we;
+ logic dio_pad_sleep_regwen_14_qs;
+ logic dio_pad_sleep_regwen_14_wd;
+ logic dio_pad_sleep_regwen_15_we;
+ logic dio_pad_sleep_regwen_15_qs;
+ logic dio_pad_sleep_regwen_15_wd;
+ logic dio_pad_sleep_en_0_we;
+ logic dio_pad_sleep_en_0_qs;
+ logic dio_pad_sleep_en_0_wd;
+ logic dio_pad_sleep_en_1_we;
+ logic dio_pad_sleep_en_1_qs;
+ logic dio_pad_sleep_en_1_wd;
+ logic dio_pad_sleep_en_2_we;
+ logic dio_pad_sleep_en_2_qs;
+ logic dio_pad_sleep_en_2_wd;
+ logic dio_pad_sleep_en_3_we;
+ logic dio_pad_sleep_en_3_qs;
+ logic dio_pad_sleep_en_3_wd;
+ logic dio_pad_sleep_en_4_we;
+ logic dio_pad_sleep_en_4_qs;
+ logic dio_pad_sleep_en_4_wd;
+ logic dio_pad_sleep_en_5_we;
+ logic dio_pad_sleep_en_5_qs;
+ logic dio_pad_sleep_en_5_wd;
+ logic dio_pad_sleep_en_6_we;
+ logic dio_pad_sleep_en_6_qs;
+ logic dio_pad_sleep_en_6_wd;
+ logic dio_pad_sleep_en_7_we;
+ logic dio_pad_sleep_en_7_qs;
+ logic dio_pad_sleep_en_7_wd;
+ logic dio_pad_sleep_en_8_we;
+ logic dio_pad_sleep_en_8_qs;
+ logic dio_pad_sleep_en_8_wd;
+ logic dio_pad_sleep_en_9_we;
+ logic dio_pad_sleep_en_9_qs;
+ logic dio_pad_sleep_en_9_wd;
+ logic dio_pad_sleep_en_10_we;
+ logic dio_pad_sleep_en_10_qs;
+ logic dio_pad_sleep_en_10_wd;
+ logic dio_pad_sleep_en_11_we;
+ logic dio_pad_sleep_en_11_qs;
+ logic dio_pad_sleep_en_11_wd;
+ logic dio_pad_sleep_en_12_we;
+ logic dio_pad_sleep_en_12_qs;
+ logic dio_pad_sleep_en_12_wd;
+ logic dio_pad_sleep_en_13_we;
+ logic dio_pad_sleep_en_13_qs;
+ logic dio_pad_sleep_en_13_wd;
+ logic dio_pad_sleep_en_14_we;
+ logic dio_pad_sleep_en_14_qs;
+ logic dio_pad_sleep_en_14_wd;
+ logic dio_pad_sleep_en_15_we;
+ logic dio_pad_sleep_en_15_qs;
+ logic dio_pad_sleep_en_15_wd;
+ logic dio_pad_sleep_mode_0_we;
+ logic [1:0] dio_pad_sleep_mode_0_qs;
+ logic [1:0] dio_pad_sleep_mode_0_wd;
+ logic dio_pad_sleep_mode_1_we;
+ logic [1:0] dio_pad_sleep_mode_1_qs;
+ logic [1:0] dio_pad_sleep_mode_1_wd;
+ logic dio_pad_sleep_mode_2_we;
+ logic [1:0] dio_pad_sleep_mode_2_qs;
+ logic [1:0] dio_pad_sleep_mode_2_wd;
+ logic dio_pad_sleep_mode_3_we;
+ logic [1:0] dio_pad_sleep_mode_3_qs;
+ logic [1:0] dio_pad_sleep_mode_3_wd;
+ logic dio_pad_sleep_mode_4_we;
+ logic [1:0] dio_pad_sleep_mode_4_qs;
+ logic [1:0] dio_pad_sleep_mode_4_wd;
+ logic dio_pad_sleep_mode_5_we;
+ logic [1:0] dio_pad_sleep_mode_5_qs;
+ logic [1:0] dio_pad_sleep_mode_5_wd;
+ logic dio_pad_sleep_mode_6_we;
+ logic [1:0] dio_pad_sleep_mode_6_qs;
+ logic [1:0] dio_pad_sleep_mode_6_wd;
+ logic dio_pad_sleep_mode_7_we;
+ logic [1:0] dio_pad_sleep_mode_7_qs;
+ logic [1:0] dio_pad_sleep_mode_7_wd;
+ logic dio_pad_sleep_mode_8_we;
+ logic [1:0] dio_pad_sleep_mode_8_qs;
+ logic [1:0] dio_pad_sleep_mode_8_wd;
+ logic dio_pad_sleep_mode_9_we;
+ logic [1:0] dio_pad_sleep_mode_9_qs;
+ logic [1:0] dio_pad_sleep_mode_9_wd;
+ logic dio_pad_sleep_mode_10_we;
+ logic [1:0] dio_pad_sleep_mode_10_qs;
+ logic [1:0] dio_pad_sleep_mode_10_wd;
+ logic dio_pad_sleep_mode_11_we;
+ logic [1:0] dio_pad_sleep_mode_11_qs;
+ logic [1:0] dio_pad_sleep_mode_11_wd;
+ logic dio_pad_sleep_mode_12_we;
+ logic [1:0] dio_pad_sleep_mode_12_qs;
+ logic [1:0] dio_pad_sleep_mode_12_wd;
+ logic dio_pad_sleep_mode_13_we;
+ logic [1:0] dio_pad_sleep_mode_13_qs;
+ logic [1:0] dio_pad_sleep_mode_13_wd;
+ logic dio_pad_sleep_mode_14_we;
+ logic [1:0] dio_pad_sleep_mode_14_qs;
+ logic [1:0] dio_pad_sleep_mode_14_wd;
+ logic dio_pad_sleep_mode_15_we;
+ logic [1:0] dio_pad_sleep_mode_15_qs;
+ logic [1:0] dio_pad_sleep_mode_15_wd;
+ logic wkup_detector_regwen_0_we;
+ logic wkup_detector_regwen_0_qs;
+ logic wkup_detector_regwen_0_wd;
+ logic wkup_detector_regwen_1_we;
+ logic wkup_detector_regwen_1_qs;
+ logic wkup_detector_regwen_1_wd;
+ logic wkup_detector_regwen_2_we;
+ logic wkup_detector_regwen_2_qs;
+ logic wkup_detector_regwen_2_wd;
+ logic wkup_detector_regwen_3_we;
+ logic wkup_detector_regwen_3_qs;
+ logic wkup_detector_regwen_3_wd;
+ logic wkup_detector_regwen_4_we;
+ logic wkup_detector_regwen_4_qs;
+ logic wkup_detector_regwen_4_wd;
+ logic wkup_detector_regwen_5_we;
+ logic wkup_detector_regwen_5_qs;
+ logic wkup_detector_regwen_5_wd;
+ logic wkup_detector_regwen_6_we;
+ logic wkup_detector_regwen_6_qs;
+ logic wkup_detector_regwen_6_wd;
+ logic wkup_detector_regwen_7_we;
+ logic wkup_detector_regwen_7_qs;
+ logic wkup_detector_regwen_7_wd;
+ logic wkup_detector_en_0_we;
+ logic [0:0] wkup_detector_en_0_qs;
+ logic wkup_detector_en_0_busy;
+ logic wkup_detector_en_1_we;
+ logic [0:0] wkup_detector_en_1_qs;
+ logic wkup_detector_en_1_busy;
+ logic wkup_detector_en_2_we;
+ logic [0:0] wkup_detector_en_2_qs;
+ logic wkup_detector_en_2_busy;
+ logic wkup_detector_en_3_we;
+ logic [0:0] wkup_detector_en_3_qs;
+ logic wkup_detector_en_3_busy;
+ logic wkup_detector_en_4_we;
+ logic [0:0] wkup_detector_en_4_qs;
+ logic wkup_detector_en_4_busy;
+ logic wkup_detector_en_5_we;
+ logic [0:0] wkup_detector_en_5_qs;
+ logic wkup_detector_en_5_busy;
+ logic wkup_detector_en_6_we;
+ logic [0:0] wkup_detector_en_6_qs;
+ logic wkup_detector_en_6_busy;
+ logic wkup_detector_en_7_we;
+ logic [0:0] wkup_detector_en_7_qs;
+ logic wkup_detector_en_7_busy;
+ logic wkup_detector_0_we;
+ logic [4:0] wkup_detector_0_qs;
+ logic wkup_detector_0_busy;
+ logic wkup_detector_1_we;
+ logic [4:0] wkup_detector_1_qs;
+ logic wkup_detector_1_busy;
+ logic wkup_detector_2_we;
+ logic [4:0] wkup_detector_2_qs;
+ logic wkup_detector_2_busy;
+ logic wkup_detector_3_we;
+ logic [4:0] wkup_detector_3_qs;
+ logic wkup_detector_3_busy;
+ logic wkup_detector_4_we;
+ logic [4:0] wkup_detector_4_qs;
+ logic wkup_detector_4_busy;
+ logic wkup_detector_5_we;
+ logic [4:0] wkup_detector_5_qs;
+ logic wkup_detector_5_busy;
+ logic wkup_detector_6_we;
+ logic [4:0] wkup_detector_6_qs;
+ logic wkup_detector_6_busy;
+ logic wkup_detector_7_we;
+ logic [4:0] wkup_detector_7_qs;
+ logic wkup_detector_7_busy;
+ logic wkup_detector_cnt_th_0_we;
+ logic [7:0] wkup_detector_cnt_th_0_qs;
+ logic wkup_detector_cnt_th_0_busy;
+ logic wkup_detector_cnt_th_1_we;
+ logic [7:0] wkup_detector_cnt_th_1_qs;
+ logic wkup_detector_cnt_th_1_busy;
+ logic wkup_detector_cnt_th_2_we;
+ logic [7:0] wkup_detector_cnt_th_2_qs;
+ logic wkup_detector_cnt_th_2_busy;
+ logic wkup_detector_cnt_th_3_we;
+ logic [7:0] wkup_detector_cnt_th_3_qs;
+ logic wkup_detector_cnt_th_3_busy;
+ logic wkup_detector_cnt_th_4_we;
+ logic [7:0] wkup_detector_cnt_th_4_qs;
+ logic wkup_detector_cnt_th_4_busy;
+ logic wkup_detector_cnt_th_5_we;
+ logic [7:0] wkup_detector_cnt_th_5_qs;
+ logic wkup_detector_cnt_th_5_busy;
+ logic wkup_detector_cnt_th_6_we;
+ logic [7:0] wkup_detector_cnt_th_6_qs;
+ logic wkup_detector_cnt_th_6_busy;
+ logic wkup_detector_cnt_th_7_we;
+ logic [7:0] wkup_detector_cnt_th_7_qs;
+ logic wkup_detector_cnt_th_7_busy;
+ logic wkup_detector_padsel_0_we;
+ logic [5:0] wkup_detector_padsel_0_qs;
+ logic [5:0] wkup_detector_padsel_0_wd;
+ logic wkup_detector_padsel_1_we;
+ logic [5:0] wkup_detector_padsel_1_qs;
+ logic [5:0] wkup_detector_padsel_1_wd;
+ logic wkup_detector_padsel_2_we;
+ logic [5:0] wkup_detector_padsel_2_qs;
+ logic [5:0] wkup_detector_padsel_2_wd;
+ logic wkup_detector_padsel_3_we;
+ logic [5:0] wkup_detector_padsel_3_qs;
+ logic [5:0] wkup_detector_padsel_3_wd;
+ logic wkup_detector_padsel_4_we;
+ logic [5:0] wkup_detector_padsel_4_qs;
+ logic [5:0] wkup_detector_padsel_4_wd;
+ logic wkup_detector_padsel_5_we;
+ logic [5:0] wkup_detector_padsel_5_qs;
+ logic [5:0] wkup_detector_padsel_5_wd;
+ logic wkup_detector_padsel_6_we;
+ logic [5:0] wkup_detector_padsel_6_qs;
+ logic [5:0] wkup_detector_padsel_6_wd;
+ logic wkup_detector_padsel_7_we;
+ logic [5:0] wkup_detector_padsel_7_qs;
+ logic [5:0] wkup_detector_padsel_7_wd;
+ logic wkup_cause_we;
+ logic [7:0] wkup_cause_qs;
+ logic wkup_cause_busy;
+ // Define register CDC handling.
+ // CDC handling is done on a per-reg instead of per-field boundary.
+
+ logic aon_wkup_detector_en_0_qs_int;
+ logic [0:0] aon_wkup_detector_en_0_qs;
+ logic [0:0] aon_wkup_detector_en_0_wdata;
+ logic aon_wkup_detector_en_0_we;
+ logic unused_aon_wkup_detector_en_0_wdata;
+ logic aon_wkup_detector_en_0_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_0_qs = 1'h0;
+ aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_0_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_0_qs),
+ .src_we_i (wkup_detector_en_0_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_0_busy),
+ .src_qs_o (wkup_detector_en_0_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_0_qs),
+ .dst_we_o (aon_wkup_detector_en_0_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_0_regwen),
+ .dst_wd_o (aon_wkup_detector_en_0_wdata)
+ );
+ assign unused_aon_wkup_detector_en_0_wdata =
+ ^aon_wkup_detector_en_0_wdata;
+
+ logic aon_wkup_detector_en_1_qs_int;
+ logic [0:0] aon_wkup_detector_en_1_qs;
+ logic [0:0] aon_wkup_detector_en_1_wdata;
+ logic aon_wkup_detector_en_1_we;
+ logic unused_aon_wkup_detector_en_1_wdata;
+ logic aon_wkup_detector_en_1_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_1_qs = 1'h0;
+ aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_1_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_1_qs),
+ .src_we_i (wkup_detector_en_1_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_1_busy),
+ .src_qs_o (wkup_detector_en_1_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_1_qs),
+ .dst_we_o (aon_wkup_detector_en_1_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_1_regwen),
+ .dst_wd_o (aon_wkup_detector_en_1_wdata)
+ );
+ assign unused_aon_wkup_detector_en_1_wdata =
+ ^aon_wkup_detector_en_1_wdata;
+
+ logic aon_wkup_detector_en_2_qs_int;
+ logic [0:0] aon_wkup_detector_en_2_qs;
+ logic [0:0] aon_wkup_detector_en_2_wdata;
+ logic aon_wkup_detector_en_2_we;
+ logic unused_aon_wkup_detector_en_2_wdata;
+ logic aon_wkup_detector_en_2_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_2_qs = 1'h0;
+ aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_2_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_2_qs),
+ .src_we_i (wkup_detector_en_2_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_2_busy),
+ .src_qs_o (wkup_detector_en_2_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_2_qs),
+ .dst_we_o (aon_wkup_detector_en_2_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_2_regwen),
+ .dst_wd_o (aon_wkup_detector_en_2_wdata)
+ );
+ assign unused_aon_wkup_detector_en_2_wdata =
+ ^aon_wkup_detector_en_2_wdata;
+
+ logic aon_wkup_detector_en_3_qs_int;
+ logic [0:0] aon_wkup_detector_en_3_qs;
+ logic [0:0] aon_wkup_detector_en_3_wdata;
+ logic aon_wkup_detector_en_3_we;
+ logic unused_aon_wkup_detector_en_3_wdata;
+ logic aon_wkup_detector_en_3_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_3_qs = 1'h0;
+ aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_3_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_3_qs),
+ .src_we_i (wkup_detector_en_3_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_3_busy),
+ .src_qs_o (wkup_detector_en_3_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_3_qs),
+ .dst_we_o (aon_wkup_detector_en_3_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_3_regwen),
+ .dst_wd_o (aon_wkup_detector_en_3_wdata)
+ );
+ assign unused_aon_wkup_detector_en_3_wdata =
+ ^aon_wkup_detector_en_3_wdata;
+
+ logic aon_wkup_detector_en_4_qs_int;
+ logic [0:0] aon_wkup_detector_en_4_qs;
+ logic [0:0] aon_wkup_detector_en_4_wdata;
+ logic aon_wkup_detector_en_4_we;
+ logic unused_aon_wkup_detector_en_4_wdata;
+ logic aon_wkup_detector_en_4_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_4_qs = 1'h0;
+ aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_4_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_4_qs),
+ .src_we_i (wkup_detector_en_4_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_4_busy),
+ .src_qs_o (wkup_detector_en_4_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_4_qs),
+ .dst_we_o (aon_wkup_detector_en_4_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_4_regwen),
+ .dst_wd_o (aon_wkup_detector_en_4_wdata)
+ );
+ assign unused_aon_wkup_detector_en_4_wdata =
+ ^aon_wkup_detector_en_4_wdata;
+
+ logic aon_wkup_detector_en_5_qs_int;
+ logic [0:0] aon_wkup_detector_en_5_qs;
+ logic [0:0] aon_wkup_detector_en_5_wdata;
+ logic aon_wkup_detector_en_5_we;
+ logic unused_aon_wkup_detector_en_5_wdata;
+ logic aon_wkup_detector_en_5_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_5_qs = 1'h0;
+ aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_5_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_5_qs),
+ .src_we_i (wkup_detector_en_5_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_5_busy),
+ .src_qs_o (wkup_detector_en_5_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_5_qs),
+ .dst_we_o (aon_wkup_detector_en_5_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_5_regwen),
+ .dst_wd_o (aon_wkup_detector_en_5_wdata)
+ );
+ assign unused_aon_wkup_detector_en_5_wdata =
+ ^aon_wkup_detector_en_5_wdata;
+
+ logic aon_wkup_detector_en_6_qs_int;
+ logic [0:0] aon_wkup_detector_en_6_qs;
+ logic [0:0] aon_wkup_detector_en_6_wdata;
+ logic aon_wkup_detector_en_6_we;
+ logic unused_aon_wkup_detector_en_6_wdata;
+ logic aon_wkup_detector_en_6_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_6_qs = 1'h0;
+ aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_6_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_6_qs),
+ .src_we_i (wkup_detector_en_6_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_6_busy),
+ .src_qs_o (wkup_detector_en_6_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_6_qs),
+ .dst_we_o (aon_wkup_detector_en_6_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_6_regwen),
+ .dst_wd_o (aon_wkup_detector_en_6_wdata)
+ );
+ assign unused_aon_wkup_detector_en_6_wdata =
+ ^aon_wkup_detector_en_6_wdata;
+
+ logic aon_wkup_detector_en_7_qs_int;
+ logic [0:0] aon_wkup_detector_en_7_qs;
+ logic [0:0] aon_wkup_detector_en_7_wdata;
+ logic aon_wkup_detector_en_7_we;
+ logic unused_aon_wkup_detector_en_7_wdata;
+ logic aon_wkup_detector_en_7_regwen;
+
+ always_comb begin
+ aon_wkup_detector_en_7_qs = 1'h0;
+ aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(1),
+ .ResetVal(1'h0),
+ .BitMask(1'h1),
+ .DstWrReq(0)
+ ) u_wkup_detector_en_7_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_7_qs),
+ .src_we_i (wkup_detector_en_7_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[0:0]),
+ .src_busy_o (wkup_detector_en_7_busy),
+ .src_qs_o (wkup_detector_en_7_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_en_7_qs),
+ .dst_we_o (aon_wkup_detector_en_7_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_en_7_regwen),
+ .dst_wd_o (aon_wkup_detector_en_7_wdata)
+ );
+ assign unused_aon_wkup_detector_en_7_wdata =
+ ^aon_wkup_detector_en_7_wdata;
+
+ logic [2:0] aon_wkup_detector_0_mode_0_qs_int;
+ logic aon_wkup_detector_0_filter_0_qs_int;
+ logic aon_wkup_detector_0_miodio_0_qs_int;
+ logic [4:0] aon_wkup_detector_0_qs;
+ logic [4:0] aon_wkup_detector_0_wdata;
+ logic aon_wkup_detector_0_we;
+ logic unused_aon_wkup_detector_0_wdata;
+ logic aon_wkup_detector_0_regwen;
+
+ always_comb begin
+ aon_wkup_detector_0_qs = 5'h0;
+ aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int;
+ aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int;
+ aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_0_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_0_qs),
+ .src_we_i (wkup_detector_0_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_0_busy),
+ .src_qs_o (wkup_detector_0_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_0_qs),
+ .dst_we_o (aon_wkup_detector_0_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_0_regwen),
+ .dst_wd_o (aon_wkup_detector_0_wdata)
+ );
+ assign unused_aon_wkup_detector_0_wdata =
+ ^aon_wkup_detector_0_wdata;
+
+ logic [2:0] aon_wkup_detector_1_mode_1_qs_int;
+ logic aon_wkup_detector_1_filter_1_qs_int;
+ logic aon_wkup_detector_1_miodio_1_qs_int;
+ logic [4:0] aon_wkup_detector_1_qs;
+ logic [4:0] aon_wkup_detector_1_wdata;
+ logic aon_wkup_detector_1_we;
+ logic unused_aon_wkup_detector_1_wdata;
+ logic aon_wkup_detector_1_regwen;
+
+ always_comb begin
+ aon_wkup_detector_1_qs = 5'h0;
+ aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int;
+ aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int;
+ aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_1_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_1_qs),
+ .src_we_i (wkup_detector_1_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_1_busy),
+ .src_qs_o (wkup_detector_1_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_1_qs),
+ .dst_we_o (aon_wkup_detector_1_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_1_regwen),
+ .dst_wd_o (aon_wkup_detector_1_wdata)
+ );
+ assign unused_aon_wkup_detector_1_wdata =
+ ^aon_wkup_detector_1_wdata;
+
+ logic [2:0] aon_wkup_detector_2_mode_2_qs_int;
+ logic aon_wkup_detector_2_filter_2_qs_int;
+ logic aon_wkup_detector_2_miodio_2_qs_int;
+ logic [4:0] aon_wkup_detector_2_qs;
+ logic [4:0] aon_wkup_detector_2_wdata;
+ logic aon_wkup_detector_2_we;
+ logic unused_aon_wkup_detector_2_wdata;
+ logic aon_wkup_detector_2_regwen;
+
+ always_comb begin
+ aon_wkup_detector_2_qs = 5'h0;
+ aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int;
+ aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int;
+ aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_2_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_2_qs),
+ .src_we_i (wkup_detector_2_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_2_busy),
+ .src_qs_o (wkup_detector_2_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_2_qs),
+ .dst_we_o (aon_wkup_detector_2_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_2_regwen),
+ .dst_wd_o (aon_wkup_detector_2_wdata)
+ );
+ assign unused_aon_wkup_detector_2_wdata =
+ ^aon_wkup_detector_2_wdata;
+
+ logic [2:0] aon_wkup_detector_3_mode_3_qs_int;
+ logic aon_wkup_detector_3_filter_3_qs_int;
+ logic aon_wkup_detector_3_miodio_3_qs_int;
+ logic [4:0] aon_wkup_detector_3_qs;
+ logic [4:0] aon_wkup_detector_3_wdata;
+ logic aon_wkup_detector_3_we;
+ logic unused_aon_wkup_detector_3_wdata;
+ logic aon_wkup_detector_3_regwen;
+
+ always_comb begin
+ aon_wkup_detector_3_qs = 5'h0;
+ aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int;
+ aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int;
+ aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_3_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_3_qs),
+ .src_we_i (wkup_detector_3_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_3_busy),
+ .src_qs_o (wkup_detector_3_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_3_qs),
+ .dst_we_o (aon_wkup_detector_3_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_3_regwen),
+ .dst_wd_o (aon_wkup_detector_3_wdata)
+ );
+ assign unused_aon_wkup_detector_3_wdata =
+ ^aon_wkup_detector_3_wdata;
+
+ logic [2:0] aon_wkup_detector_4_mode_4_qs_int;
+ logic aon_wkup_detector_4_filter_4_qs_int;
+ logic aon_wkup_detector_4_miodio_4_qs_int;
+ logic [4:0] aon_wkup_detector_4_qs;
+ logic [4:0] aon_wkup_detector_4_wdata;
+ logic aon_wkup_detector_4_we;
+ logic unused_aon_wkup_detector_4_wdata;
+ logic aon_wkup_detector_4_regwen;
+
+ always_comb begin
+ aon_wkup_detector_4_qs = 5'h0;
+ aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int;
+ aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int;
+ aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_4_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_4_qs),
+ .src_we_i (wkup_detector_4_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_4_busy),
+ .src_qs_o (wkup_detector_4_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_4_qs),
+ .dst_we_o (aon_wkup_detector_4_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_4_regwen),
+ .dst_wd_o (aon_wkup_detector_4_wdata)
+ );
+ assign unused_aon_wkup_detector_4_wdata =
+ ^aon_wkup_detector_4_wdata;
+
+ logic [2:0] aon_wkup_detector_5_mode_5_qs_int;
+ logic aon_wkup_detector_5_filter_5_qs_int;
+ logic aon_wkup_detector_5_miodio_5_qs_int;
+ logic [4:0] aon_wkup_detector_5_qs;
+ logic [4:0] aon_wkup_detector_5_wdata;
+ logic aon_wkup_detector_5_we;
+ logic unused_aon_wkup_detector_5_wdata;
+ logic aon_wkup_detector_5_regwen;
+
+ always_comb begin
+ aon_wkup_detector_5_qs = 5'h0;
+ aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int;
+ aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int;
+ aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_5_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_5_qs),
+ .src_we_i (wkup_detector_5_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_5_busy),
+ .src_qs_o (wkup_detector_5_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_5_qs),
+ .dst_we_o (aon_wkup_detector_5_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_5_regwen),
+ .dst_wd_o (aon_wkup_detector_5_wdata)
+ );
+ assign unused_aon_wkup_detector_5_wdata =
+ ^aon_wkup_detector_5_wdata;
+
+ logic [2:0] aon_wkup_detector_6_mode_6_qs_int;
+ logic aon_wkup_detector_6_filter_6_qs_int;
+ logic aon_wkup_detector_6_miodio_6_qs_int;
+ logic [4:0] aon_wkup_detector_6_qs;
+ logic [4:0] aon_wkup_detector_6_wdata;
+ logic aon_wkup_detector_6_we;
+ logic unused_aon_wkup_detector_6_wdata;
+ logic aon_wkup_detector_6_regwen;
+
+ always_comb begin
+ aon_wkup_detector_6_qs = 5'h0;
+ aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int;
+ aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int;
+ aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_6_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_6_qs),
+ .src_we_i (wkup_detector_6_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_6_busy),
+ .src_qs_o (wkup_detector_6_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_6_qs),
+ .dst_we_o (aon_wkup_detector_6_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_6_regwen),
+ .dst_wd_o (aon_wkup_detector_6_wdata)
+ );
+ assign unused_aon_wkup_detector_6_wdata =
+ ^aon_wkup_detector_6_wdata;
+
+ logic [2:0] aon_wkup_detector_7_mode_7_qs_int;
+ logic aon_wkup_detector_7_filter_7_qs_int;
+ logic aon_wkup_detector_7_miodio_7_qs_int;
+ logic [4:0] aon_wkup_detector_7_qs;
+ logic [4:0] aon_wkup_detector_7_wdata;
+ logic aon_wkup_detector_7_we;
+ logic unused_aon_wkup_detector_7_wdata;
+ logic aon_wkup_detector_7_regwen;
+
+ always_comb begin
+ aon_wkup_detector_7_qs = 5'h0;
+ aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int;
+ aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int;
+ aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(5),
+ .ResetVal(5'h0),
+ .BitMask(5'h1f),
+ .DstWrReq(0)
+ ) u_wkup_detector_7_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_7_qs),
+ .src_we_i (wkup_detector_7_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[4:0]),
+ .src_busy_o (wkup_detector_7_busy),
+ .src_qs_o (wkup_detector_7_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_7_qs),
+ .dst_we_o (aon_wkup_detector_7_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_7_regwen),
+ .dst_wd_o (aon_wkup_detector_7_wdata)
+ );
+ assign unused_aon_wkup_detector_7_wdata =
+ ^aon_wkup_detector_7_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_0_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_0_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_0_wdata;
+ logic aon_wkup_detector_cnt_th_0_we;
+ logic unused_aon_wkup_detector_cnt_th_0_wdata;
+ logic aon_wkup_detector_cnt_th_0_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_0_qs = 8'h0;
+ aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_0_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_0_qs),
+ .src_we_i (wkup_detector_cnt_th_0_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_0_busy),
+ .src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_0_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_0_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_0_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_0_wdata =
+ ^aon_wkup_detector_cnt_th_0_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_1_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_1_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_1_wdata;
+ logic aon_wkup_detector_cnt_th_1_we;
+ logic unused_aon_wkup_detector_cnt_th_1_wdata;
+ logic aon_wkup_detector_cnt_th_1_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_1_qs = 8'h0;
+ aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_1_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_1_qs),
+ .src_we_i (wkup_detector_cnt_th_1_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_1_busy),
+ .src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_1_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_1_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_1_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_1_wdata =
+ ^aon_wkup_detector_cnt_th_1_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_2_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_2_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_2_wdata;
+ logic aon_wkup_detector_cnt_th_2_we;
+ logic unused_aon_wkup_detector_cnt_th_2_wdata;
+ logic aon_wkup_detector_cnt_th_2_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_2_qs = 8'h0;
+ aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_2_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_2_qs),
+ .src_we_i (wkup_detector_cnt_th_2_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_2_busy),
+ .src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_2_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_2_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_2_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_2_wdata =
+ ^aon_wkup_detector_cnt_th_2_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_3_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_3_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_3_wdata;
+ logic aon_wkup_detector_cnt_th_3_we;
+ logic unused_aon_wkup_detector_cnt_th_3_wdata;
+ logic aon_wkup_detector_cnt_th_3_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_3_qs = 8'h0;
+ aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_3_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_3_qs),
+ .src_we_i (wkup_detector_cnt_th_3_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_3_busy),
+ .src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_3_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_3_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_3_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_3_wdata =
+ ^aon_wkup_detector_cnt_th_3_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_4_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_4_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_4_wdata;
+ logic aon_wkup_detector_cnt_th_4_we;
+ logic unused_aon_wkup_detector_cnt_th_4_wdata;
+ logic aon_wkup_detector_cnt_th_4_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_4_qs = 8'h0;
+ aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_4_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_4_qs),
+ .src_we_i (wkup_detector_cnt_th_4_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_4_busy),
+ .src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_4_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_4_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_4_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_4_wdata =
+ ^aon_wkup_detector_cnt_th_4_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_5_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_5_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_5_wdata;
+ logic aon_wkup_detector_cnt_th_5_we;
+ logic unused_aon_wkup_detector_cnt_th_5_wdata;
+ logic aon_wkup_detector_cnt_th_5_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_5_qs = 8'h0;
+ aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_5_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_5_qs),
+ .src_we_i (wkup_detector_cnt_th_5_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_5_busy),
+ .src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_5_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_5_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_5_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_5_wdata =
+ ^aon_wkup_detector_cnt_th_5_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_6_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_6_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_6_wdata;
+ logic aon_wkup_detector_cnt_th_6_we;
+ logic unused_aon_wkup_detector_cnt_th_6_wdata;
+ logic aon_wkup_detector_cnt_th_6_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_6_qs = 8'h0;
+ aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_6_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_6_qs),
+ .src_we_i (wkup_detector_cnt_th_6_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_6_busy),
+ .src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_6_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_6_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_6_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_6_wdata =
+ ^aon_wkup_detector_cnt_th_6_wdata;
+
+ logic [7:0] aon_wkup_detector_cnt_th_7_qs_int;
+ logic [7:0] aon_wkup_detector_cnt_th_7_qs;
+ logic [7:0] aon_wkup_detector_cnt_th_7_wdata;
+ logic aon_wkup_detector_cnt_th_7_we;
+ logic unused_aon_wkup_detector_cnt_th_7_wdata;
+ logic aon_wkup_detector_cnt_th_7_regwen;
+
+ always_comb begin
+ aon_wkup_detector_cnt_th_7_qs = 8'h0;
+ aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(0)
+ ) u_wkup_detector_cnt_th_7_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i (wkup_detector_regwen_7_qs),
+ .src_we_i (wkup_detector_cnt_th_7_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_detector_cnt_th_7_busy),
+ .src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back
+ .dst_update_i ('0),
+ .dst_ds_i ('0),
+ .dst_qs_i (aon_wkup_detector_cnt_th_7_qs),
+ .dst_we_o (aon_wkup_detector_cnt_th_7_we),
+ .dst_re_o (),
+ .dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen),
+ .dst_wd_o (aon_wkup_detector_cnt_th_7_wdata)
+ );
+ assign unused_aon_wkup_detector_cnt_th_7_wdata =
+ ^aon_wkup_detector_cnt_th_7_wdata;
+
+ logic aon_wkup_cause_cause_0_ds_int;
+ logic aon_wkup_cause_cause_0_qs_int;
+ logic aon_wkup_cause_cause_1_ds_int;
+ logic aon_wkup_cause_cause_1_qs_int;
+ logic aon_wkup_cause_cause_2_ds_int;
+ logic aon_wkup_cause_cause_2_qs_int;
+ logic aon_wkup_cause_cause_3_ds_int;
+ logic aon_wkup_cause_cause_3_qs_int;
+ logic aon_wkup_cause_cause_4_ds_int;
+ logic aon_wkup_cause_cause_4_qs_int;
+ logic aon_wkup_cause_cause_5_ds_int;
+ logic aon_wkup_cause_cause_5_qs_int;
+ logic aon_wkup_cause_cause_6_ds_int;
+ logic aon_wkup_cause_cause_6_qs_int;
+ logic aon_wkup_cause_cause_7_ds_int;
+ logic aon_wkup_cause_cause_7_qs_int;
+ logic [7:0] aon_wkup_cause_ds;
+ logic aon_wkup_cause_qe;
+ logic [7:0] aon_wkup_cause_qs;
+ logic [7:0] aon_wkup_cause_wdata;
+ logic aon_wkup_cause_we;
+ logic unused_aon_wkup_cause_wdata;
+
+ always_comb begin
+ aon_wkup_cause_qs = 8'h0;
+ aon_wkup_cause_ds = 8'h0;
+ aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int;
+ aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int;
+ aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int;
+ aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int;
+ aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int;
+ aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int;
+ aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int;
+ aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int;
+ aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int;
+ aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int;
+ aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int;
+ aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int;
+ aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int;
+ aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int;
+ aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int;
+ aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int;
+ end
+
+ prim_reg_cdc #(
+ .DataWidth(8),
+ .ResetVal(8'h0),
+ .BitMask(8'hff),
+ .DstWrReq(1)
+ ) u_wkup_cause_cdc (
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_regwen_i ('0),
+ .src_we_i (wkup_cause_we),
+ .src_re_i ('0),
+ .src_wd_i (reg_wdata[7:0]),
+ .src_busy_o (wkup_cause_busy),
+ .src_qs_o (wkup_cause_qs), // for software read back
+ .dst_update_i (aon_wkup_cause_qe),
+ .dst_ds_i (aon_wkup_cause_ds),
+ .dst_qs_i (aon_wkup_cause_qs),
+ .dst_we_o (aon_wkup_cause_we),
+ .dst_re_o (),
+ .dst_regwen_o (),
+ .dst_wd_o (aon_wkup_cause_wdata)
+ );
+ assign unused_aon_wkup_cause_wdata =
+ ^aon_wkup_cause_wdata;
+
+ // Register instances
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [0:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.qe = alert_test_qe;
+
+
+ // Subregister 0 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_0_we),
+ .wd (mio_periph_insel_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_1_we),
+ .wd (mio_periph_insel_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_2_we),
+ .wd (mio_periph_insel_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_3_we),
+ .wd (mio_periph_insel_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_4_we),
+ .wd (mio_periph_insel_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_5_we),
+ .wd (mio_periph_insel_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_6_we),
+ .wd (mio_periph_insel_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_7_we),
+ .wd (mio_periph_insel_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_8_we),
+ .wd (mio_periph_insel_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_9_we),
+ .wd (mio_periph_insel_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_10_we),
+ .wd (mio_periph_insel_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_11_we),
+ .wd (mio_periph_insel_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_12_we),
+ .wd (mio_periph_insel_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_13_we),
+ .wd (mio_periph_insel_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_14_we),
+ .wd (mio_periph_insel_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_15_we),
+ .wd (mio_periph_insel_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_16_we),
+ .wd (mio_periph_insel_regwen_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_17_we),
+ .wd (mio_periph_insel_regwen_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_18_we),
+ .wd (mio_periph_insel_regwen_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_19_we),
+ .wd (mio_periph_insel_regwen_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_20_we),
+ .wd (mio_periph_insel_regwen_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_21_we),
+ .wd (mio_periph_insel_regwen_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_22_we),
+ .wd (mio_periph_insel_regwen_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_23_we),
+ .wd (mio_periph_insel_regwen_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_24_we),
+ .wd (mio_periph_insel_regwen_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_25_we),
+ .wd (mio_periph_insel_regwen_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_26_we),
+ .wd (mio_periph_insel_regwen_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_27_we),
+ .wd (mio_periph_insel_regwen_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_28_we),
+ .wd (mio_periph_insel_regwen_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_29_we),
+ .wd (mio_periph_insel_regwen_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_30_we),
+ .wd (mio_periph_insel_regwen_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_31_we),
+ .wd (mio_periph_insel_regwen_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_32_we),
+ .wd (mio_periph_insel_regwen_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_33_we),
+ .wd (mio_periph_insel_regwen_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_34_we),
+ .wd (mio_periph_insel_regwen_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_35_we),
+ .wd (mio_periph_insel_regwen_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_36_we),
+ .wd (mio_periph_insel_regwen_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_37_we),
+ .wd (mio_periph_insel_regwen_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_38_we),
+ .wd (mio_periph_insel_regwen_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_39_we),
+ .wd (mio_periph_insel_regwen_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_40_we),
+ .wd (mio_periph_insel_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_41_we),
+ .wd (mio_periph_insel_regwen_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_42_we),
+ .wd (mio_periph_insel_regwen_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_43_we),
+ .wd (mio_periph_insel_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_44_we),
+ .wd (mio_periph_insel_regwen_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_45_we),
+ .wd (mio_periph_insel_regwen_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_46_we),
+ .wd (mio_periph_insel_regwen_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_47_we),
+ .wd (mio_periph_insel_regwen_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_48_we),
+ .wd (mio_periph_insel_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_49_we),
+ .wd (mio_periph_insel_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_50_we),
+ .wd (mio_periph_insel_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_51_we),
+ .wd (mio_periph_insel_regwen_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_52_we),
+ .wd (mio_periph_insel_regwen_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_52_qs)
+ );
+
+
+ // Subregister 53 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_53]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_53_we),
+ .wd (mio_periph_insel_regwen_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_53_qs)
+ );
+
+
+ // Subregister 54 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_54]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_54_we),
+ .wd (mio_periph_insel_regwen_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_54_qs)
+ );
+
+
+ // Subregister 55 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_55]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_55_we),
+ .wd (mio_periph_insel_regwen_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_55_qs)
+ );
+
+
+ // Subregister 56 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_56]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_56_we),
+ .wd (mio_periph_insel_regwen_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_56_qs)
+ );
+
+
+ // Subregister 57 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_57]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_57_we),
+ .wd (mio_periph_insel_regwen_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_57_qs)
+ );
+
+
+ // Subregister 58 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_58]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_58_we),
+ .wd (mio_periph_insel_regwen_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_58_qs)
+ );
+
+
+ // Subregister 59 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_59]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_59_we),
+ .wd (mio_periph_insel_regwen_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_59_qs)
+ );
+
+
+ // Subregister 60 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_60]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_60_we),
+ .wd (mio_periph_insel_regwen_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_60_qs)
+ );
+
+
+ // Subregister 61 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_61]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_61_we),
+ .wd (mio_periph_insel_regwen_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_61_qs)
+ );
+
+
+ // Subregister 62 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_62]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_62_we),
+ .wd (mio_periph_insel_regwen_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_62_qs)
+ );
+
+
+ // Subregister 63 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_63]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_63_we),
+ .wd (mio_periph_insel_regwen_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_63_qs)
+ );
+
+
+ // Subregister 64 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_64]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_64_we),
+ .wd (mio_periph_insel_regwen_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_64_qs)
+ );
+
+
+ // Subregister 65 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_65]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_65_we),
+ .wd (mio_periph_insel_regwen_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_65_qs)
+ );
+
+
+ // Subregister 66 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_66]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_66_we),
+ .wd (mio_periph_insel_regwen_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_66_qs)
+ );
+
+
+ // Subregister 67 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_67]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_67_we),
+ .wd (mio_periph_insel_regwen_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_67_qs)
+ );
+
+
+ // Subregister 68 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_68]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_68_we),
+ .wd (mio_periph_insel_regwen_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_68_qs)
+ );
+
+
+ // Subregister 69 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_69]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_69_we),
+ .wd (mio_periph_insel_regwen_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_69_qs)
+ );
+
+
+ // Subregister 70 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_70]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_70_we),
+ .wd (mio_periph_insel_regwen_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_70_qs)
+ );
+
+
+ // Subregister 71 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_71]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_71_we),
+ .wd (mio_periph_insel_regwen_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_71_qs)
+ );
+
+
+ // Subregister 72 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_72]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_72_we),
+ .wd (mio_periph_insel_regwen_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_72_qs)
+ );
+
+
+ // Subregister 73 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_73]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_73_we),
+ .wd (mio_periph_insel_regwen_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_73_qs)
+ );
+
+
+ // Subregister 74 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_74]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_74_we),
+ .wd (mio_periph_insel_regwen_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_74_qs)
+ );
+
+
+ // Subregister 75 of Multireg mio_periph_insel_regwen
+ // R[mio_periph_insel_regwen_75]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_periph_insel_regwen_75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_regwen_75_we),
+ .wd (mio_periph_insel_regwen_75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_regwen_75_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_periph_insel
+ // R[mio_periph_insel_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_0_gated_we;
+ assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_0_gated_we),
+ .wd (mio_periph_insel_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_periph_insel
+ // R[mio_periph_insel_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_1_gated_we;
+ assign mio_periph_insel_1_gated_we = mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_1_gated_we),
+ .wd (mio_periph_insel_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_periph_insel
+ // R[mio_periph_insel_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_2_gated_we;
+ assign mio_periph_insel_2_gated_we = mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_2_gated_we),
+ .wd (mio_periph_insel_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_periph_insel
+ // R[mio_periph_insel_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_3_gated_we;
+ assign mio_periph_insel_3_gated_we = mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_3_gated_we),
+ .wd (mio_periph_insel_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_periph_insel
+ // R[mio_periph_insel_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_4_gated_we;
+ assign mio_periph_insel_4_gated_we = mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_4_gated_we),
+ .wd (mio_periph_insel_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_periph_insel
+ // R[mio_periph_insel_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_5_gated_we;
+ assign mio_periph_insel_5_gated_we = mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_5_gated_we),
+ .wd (mio_periph_insel_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_periph_insel
+ // R[mio_periph_insel_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_6_gated_we;
+ assign mio_periph_insel_6_gated_we = mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_6_gated_we),
+ .wd (mio_periph_insel_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_periph_insel
+ // R[mio_periph_insel_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_7_gated_we;
+ assign mio_periph_insel_7_gated_we = mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_7_gated_we),
+ .wd (mio_periph_insel_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_periph_insel
+ // R[mio_periph_insel_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_8_gated_we;
+ assign mio_periph_insel_8_gated_we = mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_8_gated_we),
+ .wd (mio_periph_insel_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_periph_insel
+ // R[mio_periph_insel_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_9_gated_we;
+ assign mio_periph_insel_9_gated_we = mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_9_gated_we),
+ .wd (mio_periph_insel_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_periph_insel
+ // R[mio_periph_insel_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_10_gated_we;
+ assign mio_periph_insel_10_gated_we = mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_10_gated_we),
+ .wd (mio_periph_insel_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_periph_insel
+ // R[mio_periph_insel_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_11_gated_we;
+ assign mio_periph_insel_11_gated_we = mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_11_gated_we),
+ .wd (mio_periph_insel_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_periph_insel
+ // R[mio_periph_insel_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_12_gated_we;
+ assign mio_periph_insel_12_gated_we = mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_12_gated_we),
+ .wd (mio_periph_insel_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_periph_insel
+ // R[mio_periph_insel_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_13_gated_we;
+ assign mio_periph_insel_13_gated_we = mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_13_gated_we),
+ .wd (mio_periph_insel_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_periph_insel
+ // R[mio_periph_insel_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_14_gated_we;
+ assign mio_periph_insel_14_gated_we = mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_14_gated_we),
+ .wd (mio_periph_insel_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_periph_insel
+ // R[mio_periph_insel_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_15_gated_we;
+ assign mio_periph_insel_15_gated_we = mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_15_gated_we),
+ .wd (mio_periph_insel_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_periph_insel
+ // R[mio_periph_insel_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_16_gated_we;
+ assign mio_periph_insel_16_gated_we = mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_16_gated_we),
+ .wd (mio_periph_insel_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_periph_insel
+ // R[mio_periph_insel_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_17_gated_we;
+ assign mio_periph_insel_17_gated_we = mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_17_gated_we),
+ .wd (mio_periph_insel_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_periph_insel
+ // R[mio_periph_insel_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_18_gated_we;
+ assign mio_periph_insel_18_gated_we = mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_18_gated_we),
+ .wd (mio_periph_insel_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_periph_insel
+ // R[mio_periph_insel_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_19_gated_we;
+ assign mio_periph_insel_19_gated_we = mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_19_gated_we),
+ .wd (mio_periph_insel_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_periph_insel
+ // R[mio_periph_insel_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_20_gated_we;
+ assign mio_periph_insel_20_gated_we = mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_20_gated_we),
+ .wd (mio_periph_insel_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_periph_insel
+ // R[mio_periph_insel_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_21_gated_we;
+ assign mio_periph_insel_21_gated_we = mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_21_gated_we),
+ .wd (mio_periph_insel_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_periph_insel
+ // R[mio_periph_insel_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_22_gated_we;
+ assign mio_periph_insel_22_gated_we = mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_22_gated_we),
+ .wd (mio_periph_insel_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_periph_insel
+ // R[mio_periph_insel_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_23_gated_we;
+ assign mio_periph_insel_23_gated_we = mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_23_gated_we),
+ .wd (mio_periph_insel_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_periph_insel
+ // R[mio_periph_insel_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_24_gated_we;
+ assign mio_periph_insel_24_gated_we = mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_24_gated_we),
+ .wd (mio_periph_insel_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_periph_insel
+ // R[mio_periph_insel_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_25_gated_we;
+ assign mio_periph_insel_25_gated_we = mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_25_gated_we),
+ .wd (mio_periph_insel_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_periph_insel
+ // R[mio_periph_insel_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_26_gated_we;
+ assign mio_periph_insel_26_gated_we = mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_26_gated_we),
+ .wd (mio_periph_insel_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_periph_insel
+ // R[mio_periph_insel_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_27_gated_we;
+ assign mio_periph_insel_27_gated_we = mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_27_gated_we),
+ .wd (mio_periph_insel_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_periph_insel
+ // R[mio_periph_insel_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_28_gated_we;
+ assign mio_periph_insel_28_gated_we = mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_28_gated_we),
+ .wd (mio_periph_insel_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_periph_insel
+ // R[mio_periph_insel_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_29_gated_we;
+ assign mio_periph_insel_29_gated_we = mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_29_gated_we),
+ .wd (mio_periph_insel_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_periph_insel
+ // R[mio_periph_insel_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_30_gated_we;
+ assign mio_periph_insel_30_gated_we = mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_30_gated_we),
+ .wd (mio_periph_insel_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_periph_insel
+ // R[mio_periph_insel_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_31_gated_we;
+ assign mio_periph_insel_31_gated_we = mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_31_gated_we),
+ .wd (mio_periph_insel_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_periph_insel
+ // R[mio_periph_insel_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_32_gated_we;
+ assign mio_periph_insel_32_gated_we = mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_32_gated_we),
+ .wd (mio_periph_insel_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_periph_insel
+ // R[mio_periph_insel_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_33_gated_we;
+ assign mio_periph_insel_33_gated_we = mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_33_gated_we),
+ .wd (mio_periph_insel_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_periph_insel
+ // R[mio_periph_insel_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_34_gated_we;
+ assign mio_periph_insel_34_gated_we = mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_34_gated_we),
+ .wd (mio_periph_insel_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_periph_insel
+ // R[mio_periph_insel_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_35_gated_we;
+ assign mio_periph_insel_35_gated_we = mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_35_gated_we),
+ .wd (mio_periph_insel_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_periph_insel
+ // R[mio_periph_insel_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_36_gated_we;
+ assign mio_periph_insel_36_gated_we = mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_36_gated_we),
+ .wd (mio_periph_insel_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_periph_insel
+ // R[mio_periph_insel_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_37_gated_we;
+ assign mio_periph_insel_37_gated_we = mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_37_gated_we),
+ .wd (mio_periph_insel_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_periph_insel
+ // R[mio_periph_insel_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_38_gated_we;
+ assign mio_periph_insel_38_gated_we = mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_38_gated_we),
+ .wd (mio_periph_insel_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_periph_insel
+ // R[mio_periph_insel_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_39_gated_we;
+ assign mio_periph_insel_39_gated_we = mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_39_gated_we),
+ .wd (mio_periph_insel_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_periph_insel
+ // R[mio_periph_insel_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_40_gated_we;
+ assign mio_periph_insel_40_gated_we = mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_40_gated_we),
+ .wd (mio_periph_insel_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_periph_insel
+ // R[mio_periph_insel_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_41_gated_we;
+ assign mio_periph_insel_41_gated_we = mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_41_gated_we),
+ .wd (mio_periph_insel_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_periph_insel
+ // R[mio_periph_insel_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_42_gated_we;
+ assign mio_periph_insel_42_gated_we = mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_42_gated_we),
+ .wd (mio_periph_insel_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_periph_insel
+ // R[mio_periph_insel_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_43_gated_we;
+ assign mio_periph_insel_43_gated_we = mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_43_gated_we),
+ .wd (mio_periph_insel_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_periph_insel
+ // R[mio_periph_insel_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_44_gated_we;
+ assign mio_periph_insel_44_gated_we = mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_44_gated_we),
+ .wd (mio_periph_insel_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_periph_insel
+ // R[mio_periph_insel_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_45_gated_we;
+ assign mio_periph_insel_45_gated_we = mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_45_gated_we),
+ .wd (mio_periph_insel_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_periph_insel
+ // R[mio_periph_insel_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_46_gated_we;
+ assign mio_periph_insel_46_gated_we = mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_46_gated_we),
+ .wd (mio_periph_insel_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_periph_insel
+ // R[mio_periph_insel_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_47_gated_we;
+ assign mio_periph_insel_47_gated_we = mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_47_gated_we),
+ .wd (mio_periph_insel_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_periph_insel
+ // R[mio_periph_insel_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_48_gated_we;
+ assign mio_periph_insel_48_gated_we = mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_48_gated_we),
+ .wd (mio_periph_insel_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_periph_insel
+ // R[mio_periph_insel_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_49_gated_we;
+ assign mio_periph_insel_49_gated_we = mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_49_gated_we),
+ .wd (mio_periph_insel_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_periph_insel
+ // R[mio_periph_insel_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_50_gated_we;
+ assign mio_periph_insel_50_gated_we = mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_50_gated_we),
+ .wd (mio_periph_insel_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_periph_insel
+ // R[mio_periph_insel_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_51_gated_we;
+ assign mio_periph_insel_51_gated_we = mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_51_gated_we),
+ .wd (mio_periph_insel_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_periph_insel
+ // R[mio_periph_insel_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_52_gated_we;
+ assign mio_periph_insel_52_gated_we = mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_52_gated_we),
+ .wd (mio_periph_insel_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_52_qs)
+ );
+
+
+ // Subregister 53 of Multireg mio_periph_insel
+ // R[mio_periph_insel_53]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_53_gated_we;
+ assign mio_periph_insel_53_gated_we = mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_53_gated_we),
+ .wd (mio_periph_insel_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_53_qs)
+ );
+
+
+ // Subregister 54 of Multireg mio_periph_insel
+ // R[mio_periph_insel_54]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_54_gated_we;
+ assign mio_periph_insel_54_gated_we = mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_54_gated_we),
+ .wd (mio_periph_insel_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_54_qs)
+ );
+
+
+ // Subregister 55 of Multireg mio_periph_insel
+ // R[mio_periph_insel_55]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_55_gated_we;
+ assign mio_periph_insel_55_gated_we = mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_55_gated_we),
+ .wd (mio_periph_insel_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_55_qs)
+ );
+
+
+ // Subregister 56 of Multireg mio_periph_insel
+ // R[mio_periph_insel_56]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_56_gated_we;
+ assign mio_periph_insel_56_gated_we = mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_56_gated_we),
+ .wd (mio_periph_insel_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_56_qs)
+ );
+
+
+ // Subregister 57 of Multireg mio_periph_insel
+ // R[mio_periph_insel_57]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_57_gated_we;
+ assign mio_periph_insel_57_gated_we = mio_periph_insel_57_we & mio_periph_insel_regwen_57_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_57_gated_we),
+ .wd (mio_periph_insel_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_57_qs)
+ );
+
+
+ // Subregister 58 of Multireg mio_periph_insel
+ // R[mio_periph_insel_58]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_58_gated_we;
+ assign mio_periph_insel_58_gated_we = mio_periph_insel_58_we & mio_periph_insel_regwen_58_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_58_gated_we),
+ .wd (mio_periph_insel_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_58_qs)
+ );
+
+
+ // Subregister 59 of Multireg mio_periph_insel
+ // R[mio_periph_insel_59]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_59_gated_we;
+ assign mio_periph_insel_59_gated_we = mio_periph_insel_59_we & mio_periph_insel_regwen_59_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_59_gated_we),
+ .wd (mio_periph_insel_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_59_qs)
+ );
+
+
+ // Subregister 60 of Multireg mio_periph_insel
+ // R[mio_periph_insel_60]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_60_gated_we;
+ assign mio_periph_insel_60_gated_we = mio_periph_insel_60_we & mio_periph_insel_regwen_60_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_60_gated_we),
+ .wd (mio_periph_insel_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_60_qs)
+ );
+
+
+ // Subregister 61 of Multireg mio_periph_insel
+ // R[mio_periph_insel_61]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_61_gated_we;
+ assign mio_periph_insel_61_gated_we = mio_periph_insel_61_we & mio_periph_insel_regwen_61_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_61_gated_we),
+ .wd (mio_periph_insel_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_61_qs)
+ );
+
+
+ // Subregister 62 of Multireg mio_periph_insel
+ // R[mio_periph_insel_62]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_62_gated_we;
+ assign mio_periph_insel_62_gated_we = mio_periph_insel_62_we & mio_periph_insel_regwen_62_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_62_gated_we),
+ .wd (mio_periph_insel_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_62_qs)
+ );
+
+
+ // Subregister 63 of Multireg mio_periph_insel
+ // R[mio_periph_insel_63]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_63_gated_we;
+ assign mio_periph_insel_63_gated_we = mio_periph_insel_63_we & mio_periph_insel_regwen_63_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_63_gated_we),
+ .wd (mio_periph_insel_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_63_qs)
+ );
+
+
+ // Subregister 64 of Multireg mio_periph_insel
+ // R[mio_periph_insel_64]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_64_gated_we;
+ assign mio_periph_insel_64_gated_we = mio_periph_insel_64_we & mio_periph_insel_regwen_64_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_64_gated_we),
+ .wd (mio_periph_insel_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_64_qs)
+ );
+
+
+ // Subregister 65 of Multireg mio_periph_insel
+ // R[mio_periph_insel_65]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_65_gated_we;
+ assign mio_periph_insel_65_gated_we = mio_periph_insel_65_we & mio_periph_insel_regwen_65_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_65_gated_we),
+ .wd (mio_periph_insel_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_65_qs)
+ );
+
+
+ // Subregister 66 of Multireg mio_periph_insel
+ // R[mio_periph_insel_66]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_66_gated_we;
+ assign mio_periph_insel_66_gated_we = mio_periph_insel_66_we & mio_periph_insel_regwen_66_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_66_gated_we),
+ .wd (mio_periph_insel_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_66_qs)
+ );
+
+
+ // Subregister 67 of Multireg mio_periph_insel
+ // R[mio_periph_insel_67]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_67_gated_we;
+ assign mio_periph_insel_67_gated_we = mio_periph_insel_67_we & mio_periph_insel_regwen_67_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_67_gated_we),
+ .wd (mio_periph_insel_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_67_qs)
+ );
+
+
+ // Subregister 68 of Multireg mio_periph_insel
+ // R[mio_periph_insel_68]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_68_gated_we;
+ assign mio_periph_insel_68_gated_we = mio_periph_insel_68_we & mio_periph_insel_regwen_68_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_68_gated_we),
+ .wd (mio_periph_insel_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_68_qs)
+ );
+
+
+ // Subregister 69 of Multireg mio_periph_insel
+ // R[mio_periph_insel_69]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_69_gated_we;
+ assign mio_periph_insel_69_gated_we = mio_periph_insel_69_we & mio_periph_insel_regwen_69_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_69_gated_we),
+ .wd (mio_periph_insel_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_69_qs)
+ );
+
+
+ // Subregister 70 of Multireg mio_periph_insel
+ // R[mio_periph_insel_70]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_70_gated_we;
+ assign mio_periph_insel_70_gated_we = mio_periph_insel_70_we & mio_periph_insel_regwen_70_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_70_gated_we),
+ .wd (mio_periph_insel_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_70_qs)
+ );
+
+
+ // Subregister 71 of Multireg mio_periph_insel
+ // R[mio_periph_insel_71]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_71_gated_we;
+ assign mio_periph_insel_71_gated_we = mio_periph_insel_71_we & mio_periph_insel_regwen_71_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_71_gated_we),
+ .wd (mio_periph_insel_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_71_qs)
+ );
+
+
+ // Subregister 72 of Multireg mio_periph_insel
+ // R[mio_periph_insel_72]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_72_gated_we;
+ assign mio_periph_insel_72_gated_we = mio_periph_insel_72_we & mio_periph_insel_regwen_72_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_72_gated_we),
+ .wd (mio_periph_insel_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_72_qs)
+ );
+
+
+ // Subregister 73 of Multireg mio_periph_insel
+ // R[mio_periph_insel_73]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_73_gated_we;
+ assign mio_periph_insel_73_gated_we = mio_periph_insel_73_we & mio_periph_insel_regwen_73_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_73_gated_we),
+ .wd (mio_periph_insel_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_73_qs)
+ );
+
+
+ // Subregister 74 of Multireg mio_periph_insel
+ // R[mio_periph_insel_74]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_74_gated_we;
+ assign mio_periph_insel_74_gated_we = mio_periph_insel_74_we & mio_periph_insel_regwen_74_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_74_gated_we),
+ .wd (mio_periph_insel_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_74_qs)
+ );
+
+
+ // Subregister 75 of Multireg mio_periph_insel
+ // R[mio_periph_insel_75]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_periph_insel_75_gated_we;
+ assign mio_periph_insel_75_gated_we = mio_periph_insel_75_we & mio_periph_insel_regwen_75_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_mio_periph_insel_75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_periph_insel_75_gated_we),
+ .wd (mio_periph_insel_75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_periph_insel[75].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_periph_insel_75_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_0_we),
+ .wd (mio_outsel_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_1_we),
+ .wd (mio_outsel_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_2_we),
+ .wd (mio_outsel_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_3_we),
+ .wd (mio_outsel_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_4_we),
+ .wd (mio_outsel_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_5_we),
+ .wd (mio_outsel_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_6_we),
+ .wd (mio_outsel_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_7_we),
+ .wd (mio_outsel_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_8_we),
+ .wd (mio_outsel_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_9_we),
+ .wd (mio_outsel_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_10_we),
+ .wd (mio_outsel_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_11_we),
+ .wd (mio_outsel_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_12_we),
+ .wd (mio_outsel_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_13_we),
+ .wd (mio_outsel_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_14_we),
+ .wd (mio_outsel_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_15_we),
+ .wd (mio_outsel_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_16_we),
+ .wd (mio_outsel_regwen_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_17_we),
+ .wd (mio_outsel_regwen_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_18_we),
+ .wd (mio_outsel_regwen_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_19_we),
+ .wd (mio_outsel_regwen_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_20_we),
+ .wd (mio_outsel_regwen_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_21_we),
+ .wd (mio_outsel_regwen_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_22_we),
+ .wd (mio_outsel_regwen_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_23_we),
+ .wd (mio_outsel_regwen_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_24_we),
+ .wd (mio_outsel_regwen_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_25_we),
+ .wd (mio_outsel_regwen_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_26_we),
+ .wd (mio_outsel_regwen_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_27_we),
+ .wd (mio_outsel_regwen_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_28_we),
+ .wd (mio_outsel_regwen_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_29_we),
+ .wd (mio_outsel_regwen_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_30_we),
+ .wd (mio_outsel_regwen_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_31_we),
+ .wd (mio_outsel_regwen_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_32_we),
+ .wd (mio_outsel_regwen_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_33_we),
+ .wd (mio_outsel_regwen_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_34_we),
+ .wd (mio_outsel_regwen_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_35_we),
+ .wd (mio_outsel_regwen_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_36_we),
+ .wd (mio_outsel_regwen_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_37_we),
+ .wd (mio_outsel_regwen_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_38_we),
+ .wd (mio_outsel_regwen_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_39_we),
+ .wd (mio_outsel_regwen_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_40_we),
+ .wd (mio_outsel_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_41_we),
+ .wd (mio_outsel_regwen_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_42_we),
+ .wd (mio_outsel_regwen_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_43_we),
+ .wd (mio_outsel_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_44_we),
+ .wd (mio_outsel_regwen_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_45_we),
+ .wd (mio_outsel_regwen_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_46_we),
+ .wd (mio_outsel_regwen_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_47_we),
+ .wd (mio_outsel_regwen_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_48_we),
+ .wd (mio_outsel_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_49_we),
+ .wd (mio_outsel_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_50_we),
+ .wd (mio_outsel_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_51_we),
+ .wd (mio_outsel_regwen_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_outsel_regwen
+ // R[mio_outsel_regwen_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_outsel_regwen_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_regwen_52_we),
+ .wd (mio_outsel_regwen_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_regwen_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_outsel
+ // R[mio_outsel_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_0_gated_we;
+ assign mio_outsel_0_gated_we = mio_outsel_0_we & mio_outsel_regwen_0_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_0_gated_we),
+ .wd (mio_outsel_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_outsel
+ // R[mio_outsel_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_1_gated_we;
+ assign mio_outsel_1_gated_we = mio_outsel_1_we & mio_outsel_regwen_1_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_1_gated_we),
+ .wd (mio_outsel_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_outsel
+ // R[mio_outsel_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_2_gated_we;
+ assign mio_outsel_2_gated_we = mio_outsel_2_we & mio_outsel_regwen_2_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_2_gated_we),
+ .wd (mio_outsel_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_outsel
+ // R[mio_outsel_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_3_gated_we;
+ assign mio_outsel_3_gated_we = mio_outsel_3_we & mio_outsel_regwen_3_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_3_gated_we),
+ .wd (mio_outsel_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_outsel
+ // R[mio_outsel_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_4_gated_we;
+ assign mio_outsel_4_gated_we = mio_outsel_4_we & mio_outsel_regwen_4_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_4_gated_we),
+ .wd (mio_outsel_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_outsel
+ // R[mio_outsel_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_5_gated_we;
+ assign mio_outsel_5_gated_we = mio_outsel_5_we & mio_outsel_regwen_5_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_5_gated_we),
+ .wd (mio_outsel_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_outsel
+ // R[mio_outsel_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_6_gated_we;
+ assign mio_outsel_6_gated_we = mio_outsel_6_we & mio_outsel_regwen_6_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_6_gated_we),
+ .wd (mio_outsel_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_outsel
+ // R[mio_outsel_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_7_gated_we;
+ assign mio_outsel_7_gated_we = mio_outsel_7_we & mio_outsel_regwen_7_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_7_gated_we),
+ .wd (mio_outsel_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_outsel
+ // R[mio_outsel_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_8_gated_we;
+ assign mio_outsel_8_gated_we = mio_outsel_8_we & mio_outsel_regwen_8_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_8_gated_we),
+ .wd (mio_outsel_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_outsel
+ // R[mio_outsel_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_9_gated_we;
+ assign mio_outsel_9_gated_we = mio_outsel_9_we & mio_outsel_regwen_9_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_9_gated_we),
+ .wd (mio_outsel_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_outsel
+ // R[mio_outsel_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_10_gated_we;
+ assign mio_outsel_10_gated_we = mio_outsel_10_we & mio_outsel_regwen_10_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_10_gated_we),
+ .wd (mio_outsel_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_outsel
+ // R[mio_outsel_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_11_gated_we;
+ assign mio_outsel_11_gated_we = mio_outsel_11_we & mio_outsel_regwen_11_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_11_gated_we),
+ .wd (mio_outsel_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_outsel
+ // R[mio_outsel_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_12_gated_we;
+ assign mio_outsel_12_gated_we = mio_outsel_12_we & mio_outsel_regwen_12_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_12_gated_we),
+ .wd (mio_outsel_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_outsel
+ // R[mio_outsel_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_13_gated_we;
+ assign mio_outsel_13_gated_we = mio_outsel_13_we & mio_outsel_regwen_13_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_13_gated_we),
+ .wd (mio_outsel_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_outsel
+ // R[mio_outsel_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_14_gated_we;
+ assign mio_outsel_14_gated_we = mio_outsel_14_we & mio_outsel_regwen_14_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_14_gated_we),
+ .wd (mio_outsel_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_outsel
+ // R[mio_outsel_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_15_gated_we;
+ assign mio_outsel_15_gated_we = mio_outsel_15_we & mio_outsel_regwen_15_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_15_gated_we),
+ .wd (mio_outsel_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_outsel
+ // R[mio_outsel_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_16_gated_we;
+ assign mio_outsel_16_gated_we = mio_outsel_16_we & mio_outsel_regwen_16_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_16_gated_we),
+ .wd (mio_outsel_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_outsel
+ // R[mio_outsel_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_17_gated_we;
+ assign mio_outsel_17_gated_we = mio_outsel_17_we & mio_outsel_regwen_17_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_17_gated_we),
+ .wd (mio_outsel_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_outsel
+ // R[mio_outsel_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_18_gated_we;
+ assign mio_outsel_18_gated_we = mio_outsel_18_we & mio_outsel_regwen_18_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_18_gated_we),
+ .wd (mio_outsel_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_outsel
+ // R[mio_outsel_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_19_gated_we;
+ assign mio_outsel_19_gated_we = mio_outsel_19_we & mio_outsel_regwen_19_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_19_gated_we),
+ .wd (mio_outsel_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_outsel
+ // R[mio_outsel_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_20_gated_we;
+ assign mio_outsel_20_gated_we = mio_outsel_20_we & mio_outsel_regwen_20_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_20_gated_we),
+ .wd (mio_outsel_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_outsel
+ // R[mio_outsel_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_21_gated_we;
+ assign mio_outsel_21_gated_we = mio_outsel_21_we & mio_outsel_regwen_21_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_21_gated_we),
+ .wd (mio_outsel_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_outsel
+ // R[mio_outsel_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_22_gated_we;
+ assign mio_outsel_22_gated_we = mio_outsel_22_we & mio_outsel_regwen_22_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_22_gated_we),
+ .wd (mio_outsel_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_outsel
+ // R[mio_outsel_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_23_gated_we;
+ assign mio_outsel_23_gated_we = mio_outsel_23_we & mio_outsel_regwen_23_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_23_gated_we),
+ .wd (mio_outsel_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_outsel
+ // R[mio_outsel_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_24_gated_we;
+ assign mio_outsel_24_gated_we = mio_outsel_24_we & mio_outsel_regwen_24_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_24_gated_we),
+ .wd (mio_outsel_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_outsel
+ // R[mio_outsel_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_25_gated_we;
+ assign mio_outsel_25_gated_we = mio_outsel_25_we & mio_outsel_regwen_25_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_25_gated_we),
+ .wd (mio_outsel_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_outsel
+ // R[mio_outsel_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_26_gated_we;
+ assign mio_outsel_26_gated_we = mio_outsel_26_we & mio_outsel_regwen_26_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_26_gated_we),
+ .wd (mio_outsel_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_outsel
+ // R[mio_outsel_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_27_gated_we;
+ assign mio_outsel_27_gated_we = mio_outsel_27_we & mio_outsel_regwen_27_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_27_gated_we),
+ .wd (mio_outsel_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_outsel
+ // R[mio_outsel_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_28_gated_we;
+ assign mio_outsel_28_gated_we = mio_outsel_28_we & mio_outsel_regwen_28_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_28_gated_we),
+ .wd (mio_outsel_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_outsel
+ // R[mio_outsel_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_29_gated_we;
+ assign mio_outsel_29_gated_we = mio_outsel_29_we & mio_outsel_regwen_29_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_29_gated_we),
+ .wd (mio_outsel_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_outsel
+ // R[mio_outsel_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_30_gated_we;
+ assign mio_outsel_30_gated_we = mio_outsel_30_we & mio_outsel_regwen_30_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_30_gated_we),
+ .wd (mio_outsel_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_outsel
+ // R[mio_outsel_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_31_gated_we;
+ assign mio_outsel_31_gated_we = mio_outsel_31_we & mio_outsel_regwen_31_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_31_gated_we),
+ .wd (mio_outsel_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_outsel
+ // R[mio_outsel_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_32_gated_we;
+ assign mio_outsel_32_gated_we = mio_outsel_32_we & mio_outsel_regwen_32_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_32_gated_we),
+ .wd (mio_outsel_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_outsel
+ // R[mio_outsel_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_33_gated_we;
+ assign mio_outsel_33_gated_we = mio_outsel_33_we & mio_outsel_regwen_33_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_33_gated_we),
+ .wd (mio_outsel_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_outsel
+ // R[mio_outsel_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_34_gated_we;
+ assign mio_outsel_34_gated_we = mio_outsel_34_we & mio_outsel_regwen_34_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_34_gated_we),
+ .wd (mio_outsel_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_outsel
+ // R[mio_outsel_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_35_gated_we;
+ assign mio_outsel_35_gated_we = mio_outsel_35_we & mio_outsel_regwen_35_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_35_gated_we),
+ .wd (mio_outsel_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_outsel
+ // R[mio_outsel_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_36_gated_we;
+ assign mio_outsel_36_gated_we = mio_outsel_36_we & mio_outsel_regwen_36_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_36_gated_we),
+ .wd (mio_outsel_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_outsel
+ // R[mio_outsel_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_37_gated_we;
+ assign mio_outsel_37_gated_we = mio_outsel_37_we & mio_outsel_regwen_37_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_37_gated_we),
+ .wd (mio_outsel_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_outsel
+ // R[mio_outsel_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_38_gated_we;
+ assign mio_outsel_38_gated_we = mio_outsel_38_we & mio_outsel_regwen_38_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_38_gated_we),
+ .wd (mio_outsel_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_outsel
+ // R[mio_outsel_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_39_gated_we;
+ assign mio_outsel_39_gated_we = mio_outsel_39_we & mio_outsel_regwen_39_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_39_gated_we),
+ .wd (mio_outsel_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_outsel
+ // R[mio_outsel_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_40_gated_we;
+ assign mio_outsel_40_gated_we = mio_outsel_40_we & mio_outsel_regwen_40_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_40_gated_we),
+ .wd (mio_outsel_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_outsel
+ // R[mio_outsel_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_41_gated_we;
+ assign mio_outsel_41_gated_we = mio_outsel_41_we & mio_outsel_regwen_41_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_41_gated_we),
+ .wd (mio_outsel_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_outsel
+ // R[mio_outsel_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_42_gated_we;
+ assign mio_outsel_42_gated_we = mio_outsel_42_we & mio_outsel_regwen_42_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_42_gated_we),
+ .wd (mio_outsel_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_outsel
+ // R[mio_outsel_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_43_gated_we;
+ assign mio_outsel_43_gated_we = mio_outsel_43_we & mio_outsel_regwen_43_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_43_gated_we),
+ .wd (mio_outsel_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_outsel
+ // R[mio_outsel_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_44_gated_we;
+ assign mio_outsel_44_gated_we = mio_outsel_44_we & mio_outsel_regwen_44_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_44_gated_we),
+ .wd (mio_outsel_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_outsel
+ // R[mio_outsel_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_45_gated_we;
+ assign mio_outsel_45_gated_we = mio_outsel_45_we & mio_outsel_regwen_45_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_45_gated_we),
+ .wd (mio_outsel_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_outsel
+ // R[mio_outsel_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_46_gated_we;
+ assign mio_outsel_46_gated_we = mio_outsel_46_we & mio_outsel_regwen_46_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_46_gated_we),
+ .wd (mio_outsel_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_outsel
+ // R[mio_outsel_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_47_gated_we;
+ assign mio_outsel_47_gated_we = mio_outsel_47_we & mio_outsel_regwen_47_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_47_gated_we),
+ .wd (mio_outsel_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_outsel
+ // R[mio_outsel_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_48_gated_we;
+ assign mio_outsel_48_gated_we = mio_outsel_48_we & mio_outsel_regwen_48_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_48_gated_we),
+ .wd (mio_outsel_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_outsel
+ // R[mio_outsel_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_49_gated_we;
+ assign mio_outsel_49_gated_we = mio_outsel_49_we & mio_outsel_regwen_49_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_49_gated_we),
+ .wd (mio_outsel_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_outsel
+ // R[mio_outsel_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_50_gated_we;
+ assign mio_outsel_50_gated_we = mio_outsel_50_we & mio_outsel_regwen_50_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_50_gated_we),
+ .wd (mio_outsel_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_outsel
+ // R[mio_outsel_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_51_gated_we;
+ assign mio_outsel_51_gated_we = mio_outsel_51_we & mio_outsel_regwen_51_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_51_gated_we),
+ .wd (mio_outsel_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_outsel
+ // R[mio_outsel_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_outsel_52_gated_we;
+ assign mio_outsel_52_gated_we = mio_outsel_52_we & mio_outsel_regwen_52_qs;
+ prim_subreg #(
+ .DW (7),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (7'h2)
+ ) u_mio_outsel_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_outsel_52_gated_we),
+ .wd (mio_outsel_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_outsel_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_0_we),
+ .wd (mio_pad_attr_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_1_we),
+ .wd (mio_pad_attr_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_2_we),
+ .wd (mio_pad_attr_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_3_we),
+ .wd (mio_pad_attr_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_4_we),
+ .wd (mio_pad_attr_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_5_we),
+ .wd (mio_pad_attr_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_6_we),
+ .wd (mio_pad_attr_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_7_we),
+ .wd (mio_pad_attr_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_8_we),
+ .wd (mio_pad_attr_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_9_we),
+ .wd (mio_pad_attr_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_10_we),
+ .wd (mio_pad_attr_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_11_we),
+ .wd (mio_pad_attr_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_12_we),
+ .wd (mio_pad_attr_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_13_we),
+ .wd (mio_pad_attr_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_14_we),
+ .wd (mio_pad_attr_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_15_we),
+ .wd (mio_pad_attr_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_16_we),
+ .wd (mio_pad_attr_regwen_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_17_we),
+ .wd (mio_pad_attr_regwen_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_18_we),
+ .wd (mio_pad_attr_regwen_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_19_we),
+ .wd (mio_pad_attr_regwen_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_20_we),
+ .wd (mio_pad_attr_regwen_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_21_we),
+ .wd (mio_pad_attr_regwen_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_22_we),
+ .wd (mio_pad_attr_regwen_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_23_we),
+ .wd (mio_pad_attr_regwen_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_24_we),
+ .wd (mio_pad_attr_regwen_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_25_we),
+ .wd (mio_pad_attr_regwen_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_26_we),
+ .wd (mio_pad_attr_regwen_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_27_we),
+ .wd (mio_pad_attr_regwen_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_28_we),
+ .wd (mio_pad_attr_regwen_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_29_we),
+ .wd (mio_pad_attr_regwen_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_30_we),
+ .wd (mio_pad_attr_regwen_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_31_we),
+ .wd (mio_pad_attr_regwen_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_32_we),
+ .wd (mio_pad_attr_regwen_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_33_we),
+ .wd (mio_pad_attr_regwen_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_34_we),
+ .wd (mio_pad_attr_regwen_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_35_we),
+ .wd (mio_pad_attr_regwen_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_36_we),
+ .wd (mio_pad_attr_regwen_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_37_we),
+ .wd (mio_pad_attr_regwen_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_38_we),
+ .wd (mio_pad_attr_regwen_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_39_we),
+ .wd (mio_pad_attr_regwen_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_40_we),
+ .wd (mio_pad_attr_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_41_we),
+ .wd (mio_pad_attr_regwen_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_42_we),
+ .wd (mio_pad_attr_regwen_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_43_we),
+ .wd (mio_pad_attr_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_44_we),
+ .wd (mio_pad_attr_regwen_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_45_we),
+ .wd (mio_pad_attr_regwen_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_46_we),
+ .wd (mio_pad_attr_regwen_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_47_we),
+ .wd (mio_pad_attr_regwen_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_48_we),
+ .wd (mio_pad_attr_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_49_we),
+ .wd (mio_pad_attr_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_50_we),
+ .wd (mio_pad_attr_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_51_we),
+ .wd (mio_pad_attr_regwen_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_pad_attr_regwen
+ // R[mio_pad_attr_regwen_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_attr_regwen_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_attr_regwen_52_we),
+ .wd (mio_pad_attr_regwen_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_attr_regwen_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_pad_attr
+ // R[mio_pad_attr_0]: V(True)
+ logic mio_pad_attr_0_qe;
+ logic [8:0] mio_pad_attr_0_flds_we;
+ assign mio_pad_attr_0_qe = &mio_pad_attr_0_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_0_gated_we;
+ assign mio_pad_attr_0_gated_we = mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs;
+ // F[invert_0]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_invert_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_invert_0_wd),
+ .d (hw2reg.mio_pad_attr[0].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[0].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_0_invert_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].invert.qe = mio_pad_attr_0_qe;
+
+ // F[virtual_od_en_0]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_virtual_od_en_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_virtual_od_en_0_wd),
+ .d (hw2reg.mio_pad_attr[0].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[0].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_0_virtual_od_en_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].virtual_od_en.qe = mio_pad_attr_0_qe;
+
+ // F[pull_en_0]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_pull_en_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_pull_en_0_wd),
+ .d (hw2reg.mio_pad_attr[0].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[0].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_0_pull_en_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].pull_en.qe = mio_pad_attr_0_qe;
+
+ // F[pull_select_0]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_pull_select_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_pull_select_0_wd),
+ .d (hw2reg.mio_pad_attr[0].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[0].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_0_pull_select_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].pull_select.qe = mio_pad_attr_0_qe;
+
+ // F[keeper_en_0]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_keeper_en_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_keeper_en_0_wd),
+ .d (hw2reg.mio_pad_attr[0].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[0].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_0_keeper_en_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].keeper_en.qe = mio_pad_attr_0_qe;
+
+ // F[schmitt_en_0]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_schmitt_en_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_schmitt_en_0_wd),
+ .d (hw2reg.mio_pad_attr[0].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[0].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_0_schmitt_en_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].schmitt_en.qe = mio_pad_attr_0_qe;
+
+ // F[od_en_0]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_0_od_en_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_od_en_0_wd),
+ .d (hw2reg.mio_pad_attr[0].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[0].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_0_od_en_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].od_en.qe = mio_pad_attr_0_qe;
+
+ // F[slew_rate_0]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_0_slew_rate_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_slew_rate_0_wd),
+ .d (hw2reg.mio_pad_attr[0].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[0].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_0_slew_rate_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].slew_rate.qe = mio_pad_attr_0_qe;
+
+ // F[drive_strength_0]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_0_drive_strength_0 (
+ .re (mio_pad_attr_0_re),
+ .we (mio_pad_attr_0_gated_we),
+ .wd (mio_pad_attr_0_drive_strength_0_wd),
+ .d (hw2reg.mio_pad_attr[0].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_0_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[0].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_0_drive_strength_0_qs)
+ );
+ assign reg2hw.mio_pad_attr[0].drive_strength.qe = mio_pad_attr_0_qe;
+
+
+ // Subregister 1 of Multireg mio_pad_attr
+ // R[mio_pad_attr_1]: V(True)
+ logic mio_pad_attr_1_qe;
+ logic [8:0] mio_pad_attr_1_flds_we;
+ assign mio_pad_attr_1_qe = &mio_pad_attr_1_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_1_gated_we;
+ assign mio_pad_attr_1_gated_we = mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs;
+ // F[invert_1]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_invert_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_invert_1_wd),
+ .d (hw2reg.mio_pad_attr[1].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[1].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_1_invert_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].invert.qe = mio_pad_attr_1_qe;
+
+ // F[virtual_od_en_1]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_virtual_od_en_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_virtual_od_en_1_wd),
+ .d (hw2reg.mio_pad_attr[1].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[1].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_1_virtual_od_en_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].virtual_od_en.qe = mio_pad_attr_1_qe;
+
+ // F[pull_en_1]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_pull_en_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_pull_en_1_wd),
+ .d (hw2reg.mio_pad_attr[1].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[1].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_1_pull_en_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].pull_en.qe = mio_pad_attr_1_qe;
+
+ // F[pull_select_1]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_pull_select_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_pull_select_1_wd),
+ .d (hw2reg.mio_pad_attr[1].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[1].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_1_pull_select_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].pull_select.qe = mio_pad_attr_1_qe;
+
+ // F[keeper_en_1]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_keeper_en_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_keeper_en_1_wd),
+ .d (hw2reg.mio_pad_attr[1].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[1].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_1_keeper_en_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].keeper_en.qe = mio_pad_attr_1_qe;
+
+ // F[schmitt_en_1]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_schmitt_en_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_schmitt_en_1_wd),
+ .d (hw2reg.mio_pad_attr[1].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[1].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_1_schmitt_en_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].schmitt_en.qe = mio_pad_attr_1_qe;
+
+ // F[od_en_1]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_1_od_en_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_od_en_1_wd),
+ .d (hw2reg.mio_pad_attr[1].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[1].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_1_od_en_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].od_en.qe = mio_pad_attr_1_qe;
+
+ // F[slew_rate_1]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_1_slew_rate_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_slew_rate_1_wd),
+ .d (hw2reg.mio_pad_attr[1].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[1].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_1_slew_rate_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].slew_rate.qe = mio_pad_attr_1_qe;
+
+ // F[drive_strength_1]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_1_drive_strength_1 (
+ .re (mio_pad_attr_1_re),
+ .we (mio_pad_attr_1_gated_we),
+ .wd (mio_pad_attr_1_drive_strength_1_wd),
+ .d (hw2reg.mio_pad_attr[1].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_1_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[1].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_1_drive_strength_1_qs)
+ );
+ assign reg2hw.mio_pad_attr[1].drive_strength.qe = mio_pad_attr_1_qe;
+
+
+ // Subregister 2 of Multireg mio_pad_attr
+ // R[mio_pad_attr_2]: V(True)
+ logic mio_pad_attr_2_qe;
+ logic [8:0] mio_pad_attr_2_flds_we;
+ assign mio_pad_attr_2_qe = &mio_pad_attr_2_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_2_gated_we;
+ assign mio_pad_attr_2_gated_we = mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs;
+ // F[invert_2]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_invert_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_invert_2_wd),
+ .d (hw2reg.mio_pad_attr[2].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[2].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_2_invert_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].invert.qe = mio_pad_attr_2_qe;
+
+ // F[virtual_od_en_2]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_virtual_od_en_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_virtual_od_en_2_wd),
+ .d (hw2reg.mio_pad_attr[2].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[2].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_2_virtual_od_en_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].virtual_od_en.qe = mio_pad_attr_2_qe;
+
+ // F[pull_en_2]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_pull_en_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_pull_en_2_wd),
+ .d (hw2reg.mio_pad_attr[2].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[2].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_2_pull_en_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].pull_en.qe = mio_pad_attr_2_qe;
+
+ // F[pull_select_2]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_pull_select_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_pull_select_2_wd),
+ .d (hw2reg.mio_pad_attr[2].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[2].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_2_pull_select_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].pull_select.qe = mio_pad_attr_2_qe;
+
+ // F[keeper_en_2]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_keeper_en_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_keeper_en_2_wd),
+ .d (hw2reg.mio_pad_attr[2].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[2].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_2_keeper_en_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].keeper_en.qe = mio_pad_attr_2_qe;
+
+ // F[schmitt_en_2]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_schmitt_en_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_schmitt_en_2_wd),
+ .d (hw2reg.mio_pad_attr[2].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[2].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_2_schmitt_en_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].schmitt_en.qe = mio_pad_attr_2_qe;
+
+ // F[od_en_2]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_2_od_en_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_od_en_2_wd),
+ .d (hw2reg.mio_pad_attr[2].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[2].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_2_od_en_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].od_en.qe = mio_pad_attr_2_qe;
+
+ // F[slew_rate_2]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_2_slew_rate_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_slew_rate_2_wd),
+ .d (hw2reg.mio_pad_attr[2].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[2].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_2_slew_rate_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].slew_rate.qe = mio_pad_attr_2_qe;
+
+ // F[drive_strength_2]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_2_drive_strength_2 (
+ .re (mio_pad_attr_2_re),
+ .we (mio_pad_attr_2_gated_we),
+ .wd (mio_pad_attr_2_drive_strength_2_wd),
+ .d (hw2reg.mio_pad_attr[2].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_2_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[2].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_2_drive_strength_2_qs)
+ );
+ assign reg2hw.mio_pad_attr[2].drive_strength.qe = mio_pad_attr_2_qe;
+
+
+ // Subregister 3 of Multireg mio_pad_attr
+ // R[mio_pad_attr_3]: V(True)
+ logic mio_pad_attr_3_qe;
+ logic [8:0] mio_pad_attr_3_flds_we;
+ assign mio_pad_attr_3_qe = &mio_pad_attr_3_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_3_gated_we;
+ assign mio_pad_attr_3_gated_we = mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs;
+ // F[invert_3]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_invert_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_invert_3_wd),
+ .d (hw2reg.mio_pad_attr[3].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[3].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_3_invert_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].invert.qe = mio_pad_attr_3_qe;
+
+ // F[virtual_od_en_3]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_virtual_od_en_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_virtual_od_en_3_wd),
+ .d (hw2reg.mio_pad_attr[3].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[3].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_3_virtual_od_en_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].virtual_od_en.qe = mio_pad_attr_3_qe;
+
+ // F[pull_en_3]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_pull_en_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_pull_en_3_wd),
+ .d (hw2reg.mio_pad_attr[3].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[3].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_3_pull_en_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].pull_en.qe = mio_pad_attr_3_qe;
+
+ // F[pull_select_3]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_pull_select_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_pull_select_3_wd),
+ .d (hw2reg.mio_pad_attr[3].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[3].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_3_pull_select_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].pull_select.qe = mio_pad_attr_3_qe;
+
+ // F[keeper_en_3]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_keeper_en_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_keeper_en_3_wd),
+ .d (hw2reg.mio_pad_attr[3].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[3].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_3_keeper_en_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].keeper_en.qe = mio_pad_attr_3_qe;
+
+ // F[schmitt_en_3]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_schmitt_en_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_schmitt_en_3_wd),
+ .d (hw2reg.mio_pad_attr[3].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[3].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_3_schmitt_en_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].schmitt_en.qe = mio_pad_attr_3_qe;
+
+ // F[od_en_3]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_3_od_en_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_od_en_3_wd),
+ .d (hw2reg.mio_pad_attr[3].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[3].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_3_od_en_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].od_en.qe = mio_pad_attr_3_qe;
+
+ // F[slew_rate_3]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_3_slew_rate_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_slew_rate_3_wd),
+ .d (hw2reg.mio_pad_attr[3].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[3].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_3_slew_rate_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].slew_rate.qe = mio_pad_attr_3_qe;
+
+ // F[drive_strength_3]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_3_drive_strength_3 (
+ .re (mio_pad_attr_3_re),
+ .we (mio_pad_attr_3_gated_we),
+ .wd (mio_pad_attr_3_drive_strength_3_wd),
+ .d (hw2reg.mio_pad_attr[3].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_3_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[3].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_3_drive_strength_3_qs)
+ );
+ assign reg2hw.mio_pad_attr[3].drive_strength.qe = mio_pad_attr_3_qe;
+
+
+ // Subregister 4 of Multireg mio_pad_attr
+ // R[mio_pad_attr_4]: V(True)
+ logic mio_pad_attr_4_qe;
+ logic [8:0] mio_pad_attr_4_flds_we;
+ assign mio_pad_attr_4_qe = &mio_pad_attr_4_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_4_gated_we;
+ assign mio_pad_attr_4_gated_we = mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs;
+ // F[invert_4]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_invert_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_invert_4_wd),
+ .d (hw2reg.mio_pad_attr[4].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[4].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_4_invert_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].invert.qe = mio_pad_attr_4_qe;
+
+ // F[virtual_od_en_4]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_virtual_od_en_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_virtual_od_en_4_wd),
+ .d (hw2reg.mio_pad_attr[4].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[4].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_4_virtual_od_en_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].virtual_od_en.qe = mio_pad_attr_4_qe;
+
+ // F[pull_en_4]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_pull_en_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_pull_en_4_wd),
+ .d (hw2reg.mio_pad_attr[4].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[4].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_4_pull_en_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].pull_en.qe = mio_pad_attr_4_qe;
+
+ // F[pull_select_4]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_pull_select_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_pull_select_4_wd),
+ .d (hw2reg.mio_pad_attr[4].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[4].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_4_pull_select_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].pull_select.qe = mio_pad_attr_4_qe;
+
+ // F[keeper_en_4]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_keeper_en_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_keeper_en_4_wd),
+ .d (hw2reg.mio_pad_attr[4].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[4].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_4_keeper_en_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].keeper_en.qe = mio_pad_attr_4_qe;
+
+ // F[schmitt_en_4]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_schmitt_en_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_schmitt_en_4_wd),
+ .d (hw2reg.mio_pad_attr[4].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[4].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_4_schmitt_en_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].schmitt_en.qe = mio_pad_attr_4_qe;
+
+ // F[od_en_4]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_4_od_en_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_od_en_4_wd),
+ .d (hw2reg.mio_pad_attr[4].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[4].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_4_od_en_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].od_en.qe = mio_pad_attr_4_qe;
+
+ // F[slew_rate_4]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_4_slew_rate_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_slew_rate_4_wd),
+ .d (hw2reg.mio_pad_attr[4].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[4].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_4_slew_rate_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].slew_rate.qe = mio_pad_attr_4_qe;
+
+ // F[drive_strength_4]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_4_drive_strength_4 (
+ .re (mio_pad_attr_4_re),
+ .we (mio_pad_attr_4_gated_we),
+ .wd (mio_pad_attr_4_drive_strength_4_wd),
+ .d (hw2reg.mio_pad_attr[4].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_4_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[4].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_4_drive_strength_4_qs)
+ );
+ assign reg2hw.mio_pad_attr[4].drive_strength.qe = mio_pad_attr_4_qe;
+
+
+ // Subregister 5 of Multireg mio_pad_attr
+ // R[mio_pad_attr_5]: V(True)
+ logic mio_pad_attr_5_qe;
+ logic [8:0] mio_pad_attr_5_flds_we;
+ assign mio_pad_attr_5_qe = &mio_pad_attr_5_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_5_gated_we;
+ assign mio_pad_attr_5_gated_we = mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs;
+ // F[invert_5]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_invert_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_invert_5_wd),
+ .d (hw2reg.mio_pad_attr[5].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[5].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_5_invert_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].invert.qe = mio_pad_attr_5_qe;
+
+ // F[virtual_od_en_5]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_virtual_od_en_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_virtual_od_en_5_wd),
+ .d (hw2reg.mio_pad_attr[5].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[5].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_5_virtual_od_en_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].virtual_od_en.qe = mio_pad_attr_5_qe;
+
+ // F[pull_en_5]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_pull_en_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_pull_en_5_wd),
+ .d (hw2reg.mio_pad_attr[5].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[5].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_5_pull_en_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].pull_en.qe = mio_pad_attr_5_qe;
+
+ // F[pull_select_5]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_pull_select_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_pull_select_5_wd),
+ .d (hw2reg.mio_pad_attr[5].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[5].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_5_pull_select_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].pull_select.qe = mio_pad_attr_5_qe;
+
+ // F[keeper_en_5]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_keeper_en_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_keeper_en_5_wd),
+ .d (hw2reg.mio_pad_attr[5].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[5].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_5_keeper_en_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].keeper_en.qe = mio_pad_attr_5_qe;
+
+ // F[schmitt_en_5]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_schmitt_en_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_schmitt_en_5_wd),
+ .d (hw2reg.mio_pad_attr[5].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[5].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_5_schmitt_en_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].schmitt_en.qe = mio_pad_attr_5_qe;
+
+ // F[od_en_5]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_5_od_en_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_od_en_5_wd),
+ .d (hw2reg.mio_pad_attr[5].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[5].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_5_od_en_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].od_en.qe = mio_pad_attr_5_qe;
+
+ // F[slew_rate_5]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_5_slew_rate_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_slew_rate_5_wd),
+ .d (hw2reg.mio_pad_attr[5].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[5].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_5_slew_rate_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].slew_rate.qe = mio_pad_attr_5_qe;
+
+ // F[drive_strength_5]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_5_drive_strength_5 (
+ .re (mio_pad_attr_5_re),
+ .we (mio_pad_attr_5_gated_we),
+ .wd (mio_pad_attr_5_drive_strength_5_wd),
+ .d (hw2reg.mio_pad_attr[5].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_5_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[5].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_5_drive_strength_5_qs)
+ );
+ assign reg2hw.mio_pad_attr[5].drive_strength.qe = mio_pad_attr_5_qe;
+
+
+ // Subregister 6 of Multireg mio_pad_attr
+ // R[mio_pad_attr_6]: V(True)
+ logic mio_pad_attr_6_qe;
+ logic [8:0] mio_pad_attr_6_flds_we;
+ assign mio_pad_attr_6_qe = &mio_pad_attr_6_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_6_gated_we;
+ assign mio_pad_attr_6_gated_we = mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs;
+ // F[invert_6]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_invert_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_invert_6_wd),
+ .d (hw2reg.mio_pad_attr[6].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[6].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_6_invert_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].invert.qe = mio_pad_attr_6_qe;
+
+ // F[virtual_od_en_6]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_virtual_od_en_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_virtual_od_en_6_wd),
+ .d (hw2reg.mio_pad_attr[6].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[6].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_6_virtual_od_en_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].virtual_od_en.qe = mio_pad_attr_6_qe;
+
+ // F[pull_en_6]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_pull_en_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_pull_en_6_wd),
+ .d (hw2reg.mio_pad_attr[6].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[6].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_6_pull_en_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].pull_en.qe = mio_pad_attr_6_qe;
+
+ // F[pull_select_6]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_pull_select_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_pull_select_6_wd),
+ .d (hw2reg.mio_pad_attr[6].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[6].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_6_pull_select_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].pull_select.qe = mio_pad_attr_6_qe;
+
+ // F[keeper_en_6]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_keeper_en_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_keeper_en_6_wd),
+ .d (hw2reg.mio_pad_attr[6].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[6].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_6_keeper_en_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].keeper_en.qe = mio_pad_attr_6_qe;
+
+ // F[schmitt_en_6]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_schmitt_en_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_schmitt_en_6_wd),
+ .d (hw2reg.mio_pad_attr[6].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[6].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_6_schmitt_en_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].schmitt_en.qe = mio_pad_attr_6_qe;
+
+ // F[od_en_6]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_6_od_en_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_od_en_6_wd),
+ .d (hw2reg.mio_pad_attr[6].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[6].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_6_od_en_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].od_en.qe = mio_pad_attr_6_qe;
+
+ // F[slew_rate_6]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_6_slew_rate_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_slew_rate_6_wd),
+ .d (hw2reg.mio_pad_attr[6].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[6].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_6_slew_rate_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].slew_rate.qe = mio_pad_attr_6_qe;
+
+ // F[drive_strength_6]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_6_drive_strength_6 (
+ .re (mio_pad_attr_6_re),
+ .we (mio_pad_attr_6_gated_we),
+ .wd (mio_pad_attr_6_drive_strength_6_wd),
+ .d (hw2reg.mio_pad_attr[6].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_6_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[6].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_6_drive_strength_6_qs)
+ );
+ assign reg2hw.mio_pad_attr[6].drive_strength.qe = mio_pad_attr_6_qe;
+
+
+ // Subregister 7 of Multireg mio_pad_attr
+ // R[mio_pad_attr_7]: V(True)
+ logic mio_pad_attr_7_qe;
+ logic [8:0] mio_pad_attr_7_flds_we;
+ assign mio_pad_attr_7_qe = &mio_pad_attr_7_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_7_gated_we;
+ assign mio_pad_attr_7_gated_we = mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs;
+ // F[invert_7]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_invert_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_invert_7_wd),
+ .d (hw2reg.mio_pad_attr[7].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[7].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_7_invert_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].invert.qe = mio_pad_attr_7_qe;
+
+ // F[virtual_od_en_7]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_virtual_od_en_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_virtual_od_en_7_wd),
+ .d (hw2reg.mio_pad_attr[7].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[7].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_7_virtual_od_en_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].virtual_od_en.qe = mio_pad_attr_7_qe;
+
+ // F[pull_en_7]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_pull_en_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_pull_en_7_wd),
+ .d (hw2reg.mio_pad_attr[7].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[7].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_7_pull_en_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].pull_en.qe = mio_pad_attr_7_qe;
+
+ // F[pull_select_7]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_pull_select_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_pull_select_7_wd),
+ .d (hw2reg.mio_pad_attr[7].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[7].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_7_pull_select_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].pull_select.qe = mio_pad_attr_7_qe;
+
+ // F[keeper_en_7]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_keeper_en_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_keeper_en_7_wd),
+ .d (hw2reg.mio_pad_attr[7].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[7].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_7_keeper_en_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].keeper_en.qe = mio_pad_attr_7_qe;
+
+ // F[schmitt_en_7]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_schmitt_en_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_schmitt_en_7_wd),
+ .d (hw2reg.mio_pad_attr[7].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[7].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_7_schmitt_en_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].schmitt_en.qe = mio_pad_attr_7_qe;
+
+ // F[od_en_7]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_7_od_en_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_od_en_7_wd),
+ .d (hw2reg.mio_pad_attr[7].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[7].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_7_od_en_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].od_en.qe = mio_pad_attr_7_qe;
+
+ // F[slew_rate_7]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_7_slew_rate_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_slew_rate_7_wd),
+ .d (hw2reg.mio_pad_attr[7].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[7].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_7_slew_rate_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].slew_rate.qe = mio_pad_attr_7_qe;
+
+ // F[drive_strength_7]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_7_drive_strength_7 (
+ .re (mio_pad_attr_7_re),
+ .we (mio_pad_attr_7_gated_we),
+ .wd (mio_pad_attr_7_drive_strength_7_wd),
+ .d (hw2reg.mio_pad_attr[7].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_7_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[7].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_7_drive_strength_7_qs)
+ );
+ assign reg2hw.mio_pad_attr[7].drive_strength.qe = mio_pad_attr_7_qe;
+
+
+ // Subregister 8 of Multireg mio_pad_attr
+ // R[mio_pad_attr_8]: V(True)
+ logic mio_pad_attr_8_qe;
+ logic [8:0] mio_pad_attr_8_flds_we;
+ assign mio_pad_attr_8_qe = &mio_pad_attr_8_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_8_gated_we;
+ assign mio_pad_attr_8_gated_we = mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs;
+ // F[invert_8]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_invert_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_invert_8_wd),
+ .d (hw2reg.mio_pad_attr[8].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[8].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_8_invert_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].invert.qe = mio_pad_attr_8_qe;
+
+ // F[virtual_od_en_8]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_virtual_od_en_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_virtual_od_en_8_wd),
+ .d (hw2reg.mio_pad_attr[8].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[8].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_8_virtual_od_en_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].virtual_od_en.qe = mio_pad_attr_8_qe;
+
+ // F[pull_en_8]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_pull_en_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_pull_en_8_wd),
+ .d (hw2reg.mio_pad_attr[8].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[8].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_8_pull_en_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].pull_en.qe = mio_pad_attr_8_qe;
+
+ // F[pull_select_8]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_pull_select_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_pull_select_8_wd),
+ .d (hw2reg.mio_pad_attr[8].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[8].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_8_pull_select_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].pull_select.qe = mio_pad_attr_8_qe;
+
+ // F[keeper_en_8]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_keeper_en_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_keeper_en_8_wd),
+ .d (hw2reg.mio_pad_attr[8].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[8].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_8_keeper_en_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].keeper_en.qe = mio_pad_attr_8_qe;
+
+ // F[schmitt_en_8]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_schmitt_en_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_schmitt_en_8_wd),
+ .d (hw2reg.mio_pad_attr[8].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[8].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_8_schmitt_en_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].schmitt_en.qe = mio_pad_attr_8_qe;
+
+ // F[od_en_8]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_8_od_en_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_od_en_8_wd),
+ .d (hw2reg.mio_pad_attr[8].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[8].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_8_od_en_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].od_en.qe = mio_pad_attr_8_qe;
+
+ // F[slew_rate_8]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_8_slew_rate_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_slew_rate_8_wd),
+ .d (hw2reg.mio_pad_attr[8].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[8].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_8_slew_rate_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].slew_rate.qe = mio_pad_attr_8_qe;
+
+ // F[drive_strength_8]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_8_drive_strength_8 (
+ .re (mio_pad_attr_8_re),
+ .we (mio_pad_attr_8_gated_we),
+ .wd (mio_pad_attr_8_drive_strength_8_wd),
+ .d (hw2reg.mio_pad_attr[8].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_8_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[8].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_8_drive_strength_8_qs)
+ );
+ assign reg2hw.mio_pad_attr[8].drive_strength.qe = mio_pad_attr_8_qe;
+
+
+ // Subregister 9 of Multireg mio_pad_attr
+ // R[mio_pad_attr_9]: V(True)
+ logic mio_pad_attr_9_qe;
+ logic [8:0] mio_pad_attr_9_flds_we;
+ assign mio_pad_attr_9_qe = &mio_pad_attr_9_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_9_gated_we;
+ assign mio_pad_attr_9_gated_we = mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs;
+ // F[invert_9]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_invert_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_invert_9_wd),
+ .d (hw2reg.mio_pad_attr[9].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[9].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_9_invert_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].invert.qe = mio_pad_attr_9_qe;
+
+ // F[virtual_od_en_9]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_virtual_od_en_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_virtual_od_en_9_wd),
+ .d (hw2reg.mio_pad_attr[9].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[9].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_9_virtual_od_en_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].virtual_od_en.qe = mio_pad_attr_9_qe;
+
+ // F[pull_en_9]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_pull_en_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_pull_en_9_wd),
+ .d (hw2reg.mio_pad_attr[9].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[9].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_9_pull_en_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].pull_en.qe = mio_pad_attr_9_qe;
+
+ // F[pull_select_9]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_pull_select_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_pull_select_9_wd),
+ .d (hw2reg.mio_pad_attr[9].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[9].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_9_pull_select_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].pull_select.qe = mio_pad_attr_9_qe;
+
+ // F[keeper_en_9]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_keeper_en_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_keeper_en_9_wd),
+ .d (hw2reg.mio_pad_attr[9].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[9].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_9_keeper_en_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].keeper_en.qe = mio_pad_attr_9_qe;
+
+ // F[schmitt_en_9]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_schmitt_en_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_schmitt_en_9_wd),
+ .d (hw2reg.mio_pad_attr[9].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[9].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_9_schmitt_en_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].schmitt_en.qe = mio_pad_attr_9_qe;
+
+ // F[od_en_9]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_9_od_en_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_od_en_9_wd),
+ .d (hw2reg.mio_pad_attr[9].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[9].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_9_od_en_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].od_en.qe = mio_pad_attr_9_qe;
+
+ // F[slew_rate_9]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_9_slew_rate_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_slew_rate_9_wd),
+ .d (hw2reg.mio_pad_attr[9].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[9].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_9_slew_rate_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].slew_rate.qe = mio_pad_attr_9_qe;
+
+ // F[drive_strength_9]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_9_drive_strength_9 (
+ .re (mio_pad_attr_9_re),
+ .we (mio_pad_attr_9_gated_we),
+ .wd (mio_pad_attr_9_drive_strength_9_wd),
+ .d (hw2reg.mio_pad_attr[9].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_9_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[9].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_9_drive_strength_9_qs)
+ );
+ assign reg2hw.mio_pad_attr[9].drive_strength.qe = mio_pad_attr_9_qe;
+
+
+ // Subregister 10 of Multireg mio_pad_attr
+ // R[mio_pad_attr_10]: V(True)
+ logic mio_pad_attr_10_qe;
+ logic [8:0] mio_pad_attr_10_flds_we;
+ assign mio_pad_attr_10_qe = &mio_pad_attr_10_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_10_gated_we;
+ assign mio_pad_attr_10_gated_we = mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs;
+ // F[invert_10]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_invert_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_invert_10_wd),
+ .d (hw2reg.mio_pad_attr[10].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[10].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_10_invert_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].invert.qe = mio_pad_attr_10_qe;
+
+ // F[virtual_od_en_10]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_virtual_od_en_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_virtual_od_en_10_wd),
+ .d (hw2reg.mio_pad_attr[10].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[10].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_10_virtual_od_en_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].virtual_od_en.qe = mio_pad_attr_10_qe;
+
+ // F[pull_en_10]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_pull_en_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_pull_en_10_wd),
+ .d (hw2reg.mio_pad_attr[10].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[10].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_10_pull_en_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].pull_en.qe = mio_pad_attr_10_qe;
+
+ // F[pull_select_10]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_pull_select_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_pull_select_10_wd),
+ .d (hw2reg.mio_pad_attr[10].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[10].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_10_pull_select_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].pull_select.qe = mio_pad_attr_10_qe;
+
+ // F[keeper_en_10]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_keeper_en_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_keeper_en_10_wd),
+ .d (hw2reg.mio_pad_attr[10].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[10].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_10_keeper_en_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].keeper_en.qe = mio_pad_attr_10_qe;
+
+ // F[schmitt_en_10]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_schmitt_en_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_schmitt_en_10_wd),
+ .d (hw2reg.mio_pad_attr[10].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[10].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_10_schmitt_en_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].schmitt_en.qe = mio_pad_attr_10_qe;
+
+ // F[od_en_10]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_10_od_en_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_od_en_10_wd),
+ .d (hw2reg.mio_pad_attr[10].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[10].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_10_od_en_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].od_en.qe = mio_pad_attr_10_qe;
+
+ // F[slew_rate_10]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_10_slew_rate_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_slew_rate_10_wd),
+ .d (hw2reg.mio_pad_attr[10].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[10].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_10_slew_rate_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].slew_rate.qe = mio_pad_attr_10_qe;
+
+ // F[drive_strength_10]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_10_drive_strength_10 (
+ .re (mio_pad_attr_10_re),
+ .we (mio_pad_attr_10_gated_we),
+ .wd (mio_pad_attr_10_drive_strength_10_wd),
+ .d (hw2reg.mio_pad_attr[10].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_10_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[10].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_10_drive_strength_10_qs)
+ );
+ assign reg2hw.mio_pad_attr[10].drive_strength.qe = mio_pad_attr_10_qe;
+
+
+ // Subregister 11 of Multireg mio_pad_attr
+ // R[mio_pad_attr_11]: V(True)
+ logic mio_pad_attr_11_qe;
+ logic [8:0] mio_pad_attr_11_flds_we;
+ assign mio_pad_attr_11_qe = &mio_pad_attr_11_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_11_gated_we;
+ assign mio_pad_attr_11_gated_we = mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs;
+ // F[invert_11]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_invert_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_invert_11_wd),
+ .d (hw2reg.mio_pad_attr[11].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[11].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_11_invert_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].invert.qe = mio_pad_attr_11_qe;
+
+ // F[virtual_od_en_11]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_virtual_od_en_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_virtual_od_en_11_wd),
+ .d (hw2reg.mio_pad_attr[11].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[11].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_11_virtual_od_en_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].virtual_od_en.qe = mio_pad_attr_11_qe;
+
+ // F[pull_en_11]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_pull_en_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_pull_en_11_wd),
+ .d (hw2reg.mio_pad_attr[11].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[11].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_11_pull_en_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].pull_en.qe = mio_pad_attr_11_qe;
+
+ // F[pull_select_11]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_pull_select_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_pull_select_11_wd),
+ .d (hw2reg.mio_pad_attr[11].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[11].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_11_pull_select_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].pull_select.qe = mio_pad_attr_11_qe;
+
+ // F[keeper_en_11]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_keeper_en_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_keeper_en_11_wd),
+ .d (hw2reg.mio_pad_attr[11].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[11].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_11_keeper_en_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].keeper_en.qe = mio_pad_attr_11_qe;
+
+ // F[schmitt_en_11]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_schmitt_en_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_schmitt_en_11_wd),
+ .d (hw2reg.mio_pad_attr[11].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[11].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_11_schmitt_en_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].schmitt_en.qe = mio_pad_attr_11_qe;
+
+ // F[od_en_11]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_11_od_en_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_od_en_11_wd),
+ .d (hw2reg.mio_pad_attr[11].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[11].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_11_od_en_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].od_en.qe = mio_pad_attr_11_qe;
+
+ // F[slew_rate_11]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_11_slew_rate_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_slew_rate_11_wd),
+ .d (hw2reg.mio_pad_attr[11].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[11].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_11_slew_rate_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].slew_rate.qe = mio_pad_attr_11_qe;
+
+ // F[drive_strength_11]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_11_drive_strength_11 (
+ .re (mio_pad_attr_11_re),
+ .we (mio_pad_attr_11_gated_we),
+ .wd (mio_pad_attr_11_drive_strength_11_wd),
+ .d (hw2reg.mio_pad_attr[11].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_11_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[11].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_11_drive_strength_11_qs)
+ );
+ assign reg2hw.mio_pad_attr[11].drive_strength.qe = mio_pad_attr_11_qe;
+
+
+ // Subregister 12 of Multireg mio_pad_attr
+ // R[mio_pad_attr_12]: V(True)
+ logic mio_pad_attr_12_qe;
+ logic [8:0] mio_pad_attr_12_flds_we;
+ assign mio_pad_attr_12_qe = &mio_pad_attr_12_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_12_gated_we;
+ assign mio_pad_attr_12_gated_we = mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs;
+ // F[invert_12]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_invert_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_invert_12_wd),
+ .d (hw2reg.mio_pad_attr[12].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[12].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_12_invert_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].invert.qe = mio_pad_attr_12_qe;
+
+ // F[virtual_od_en_12]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_virtual_od_en_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_virtual_od_en_12_wd),
+ .d (hw2reg.mio_pad_attr[12].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[12].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_12_virtual_od_en_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].virtual_od_en.qe = mio_pad_attr_12_qe;
+
+ // F[pull_en_12]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_pull_en_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_pull_en_12_wd),
+ .d (hw2reg.mio_pad_attr[12].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[12].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_12_pull_en_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].pull_en.qe = mio_pad_attr_12_qe;
+
+ // F[pull_select_12]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_pull_select_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_pull_select_12_wd),
+ .d (hw2reg.mio_pad_attr[12].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[12].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_12_pull_select_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].pull_select.qe = mio_pad_attr_12_qe;
+
+ // F[keeper_en_12]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_keeper_en_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_keeper_en_12_wd),
+ .d (hw2reg.mio_pad_attr[12].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[12].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_12_keeper_en_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].keeper_en.qe = mio_pad_attr_12_qe;
+
+ // F[schmitt_en_12]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_schmitt_en_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_schmitt_en_12_wd),
+ .d (hw2reg.mio_pad_attr[12].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[12].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_12_schmitt_en_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].schmitt_en.qe = mio_pad_attr_12_qe;
+
+ // F[od_en_12]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_12_od_en_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_od_en_12_wd),
+ .d (hw2reg.mio_pad_attr[12].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[12].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_12_od_en_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].od_en.qe = mio_pad_attr_12_qe;
+
+ // F[slew_rate_12]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_12_slew_rate_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_slew_rate_12_wd),
+ .d (hw2reg.mio_pad_attr[12].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[12].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_12_slew_rate_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].slew_rate.qe = mio_pad_attr_12_qe;
+
+ // F[drive_strength_12]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_12_drive_strength_12 (
+ .re (mio_pad_attr_12_re),
+ .we (mio_pad_attr_12_gated_we),
+ .wd (mio_pad_attr_12_drive_strength_12_wd),
+ .d (hw2reg.mio_pad_attr[12].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_12_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[12].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_12_drive_strength_12_qs)
+ );
+ assign reg2hw.mio_pad_attr[12].drive_strength.qe = mio_pad_attr_12_qe;
+
+
+ // Subregister 13 of Multireg mio_pad_attr
+ // R[mio_pad_attr_13]: V(True)
+ logic mio_pad_attr_13_qe;
+ logic [8:0] mio_pad_attr_13_flds_we;
+ assign mio_pad_attr_13_qe = &mio_pad_attr_13_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_13_gated_we;
+ assign mio_pad_attr_13_gated_we = mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs;
+ // F[invert_13]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_invert_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_invert_13_wd),
+ .d (hw2reg.mio_pad_attr[13].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[13].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_13_invert_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].invert.qe = mio_pad_attr_13_qe;
+
+ // F[virtual_od_en_13]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_virtual_od_en_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_virtual_od_en_13_wd),
+ .d (hw2reg.mio_pad_attr[13].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[13].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_13_virtual_od_en_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].virtual_od_en.qe = mio_pad_attr_13_qe;
+
+ // F[pull_en_13]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_pull_en_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_pull_en_13_wd),
+ .d (hw2reg.mio_pad_attr[13].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[13].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_13_pull_en_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].pull_en.qe = mio_pad_attr_13_qe;
+
+ // F[pull_select_13]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_pull_select_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_pull_select_13_wd),
+ .d (hw2reg.mio_pad_attr[13].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[13].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_13_pull_select_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].pull_select.qe = mio_pad_attr_13_qe;
+
+ // F[keeper_en_13]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_keeper_en_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_keeper_en_13_wd),
+ .d (hw2reg.mio_pad_attr[13].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[13].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_13_keeper_en_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].keeper_en.qe = mio_pad_attr_13_qe;
+
+ // F[schmitt_en_13]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_schmitt_en_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_schmitt_en_13_wd),
+ .d (hw2reg.mio_pad_attr[13].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[13].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_13_schmitt_en_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].schmitt_en.qe = mio_pad_attr_13_qe;
+
+ // F[od_en_13]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_13_od_en_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_od_en_13_wd),
+ .d (hw2reg.mio_pad_attr[13].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[13].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_13_od_en_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].od_en.qe = mio_pad_attr_13_qe;
+
+ // F[slew_rate_13]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_13_slew_rate_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_slew_rate_13_wd),
+ .d (hw2reg.mio_pad_attr[13].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[13].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_13_slew_rate_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].slew_rate.qe = mio_pad_attr_13_qe;
+
+ // F[drive_strength_13]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_13_drive_strength_13 (
+ .re (mio_pad_attr_13_re),
+ .we (mio_pad_attr_13_gated_we),
+ .wd (mio_pad_attr_13_drive_strength_13_wd),
+ .d (hw2reg.mio_pad_attr[13].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_13_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[13].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_13_drive_strength_13_qs)
+ );
+ assign reg2hw.mio_pad_attr[13].drive_strength.qe = mio_pad_attr_13_qe;
+
+
+ // Subregister 14 of Multireg mio_pad_attr
+ // R[mio_pad_attr_14]: V(True)
+ logic mio_pad_attr_14_qe;
+ logic [8:0] mio_pad_attr_14_flds_we;
+ assign mio_pad_attr_14_qe = &mio_pad_attr_14_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_14_gated_we;
+ assign mio_pad_attr_14_gated_we = mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs;
+ // F[invert_14]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_invert_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_invert_14_wd),
+ .d (hw2reg.mio_pad_attr[14].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[14].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_14_invert_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].invert.qe = mio_pad_attr_14_qe;
+
+ // F[virtual_od_en_14]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_virtual_od_en_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_virtual_od_en_14_wd),
+ .d (hw2reg.mio_pad_attr[14].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[14].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_14_virtual_od_en_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].virtual_od_en.qe = mio_pad_attr_14_qe;
+
+ // F[pull_en_14]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_pull_en_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_pull_en_14_wd),
+ .d (hw2reg.mio_pad_attr[14].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[14].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_14_pull_en_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].pull_en.qe = mio_pad_attr_14_qe;
+
+ // F[pull_select_14]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_pull_select_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_pull_select_14_wd),
+ .d (hw2reg.mio_pad_attr[14].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[14].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_14_pull_select_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].pull_select.qe = mio_pad_attr_14_qe;
+
+ // F[keeper_en_14]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_keeper_en_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_keeper_en_14_wd),
+ .d (hw2reg.mio_pad_attr[14].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[14].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_14_keeper_en_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].keeper_en.qe = mio_pad_attr_14_qe;
+
+ // F[schmitt_en_14]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_schmitt_en_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_schmitt_en_14_wd),
+ .d (hw2reg.mio_pad_attr[14].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[14].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_14_schmitt_en_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].schmitt_en.qe = mio_pad_attr_14_qe;
+
+ // F[od_en_14]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_14_od_en_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_od_en_14_wd),
+ .d (hw2reg.mio_pad_attr[14].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[14].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_14_od_en_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].od_en.qe = mio_pad_attr_14_qe;
+
+ // F[slew_rate_14]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_14_slew_rate_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_slew_rate_14_wd),
+ .d (hw2reg.mio_pad_attr[14].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[14].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_14_slew_rate_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].slew_rate.qe = mio_pad_attr_14_qe;
+
+ // F[drive_strength_14]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_14_drive_strength_14 (
+ .re (mio_pad_attr_14_re),
+ .we (mio_pad_attr_14_gated_we),
+ .wd (mio_pad_attr_14_drive_strength_14_wd),
+ .d (hw2reg.mio_pad_attr[14].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_14_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[14].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_14_drive_strength_14_qs)
+ );
+ assign reg2hw.mio_pad_attr[14].drive_strength.qe = mio_pad_attr_14_qe;
+
+
+ // Subregister 15 of Multireg mio_pad_attr
+ // R[mio_pad_attr_15]: V(True)
+ logic mio_pad_attr_15_qe;
+ logic [8:0] mio_pad_attr_15_flds_we;
+ assign mio_pad_attr_15_qe = &mio_pad_attr_15_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_15_gated_we;
+ assign mio_pad_attr_15_gated_we = mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs;
+ // F[invert_15]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_invert_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_invert_15_wd),
+ .d (hw2reg.mio_pad_attr[15].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[15].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_15_invert_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].invert.qe = mio_pad_attr_15_qe;
+
+ // F[virtual_od_en_15]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_virtual_od_en_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_virtual_od_en_15_wd),
+ .d (hw2reg.mio_pad_attr[15].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[15].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_15_virtual_od_en_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].virtual_od_en.qe = mio_pad_attr_15_qe;
+
+ // F[pull_en_15]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_pull_en_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_pull_en_15_wd),
+ .d (hw2reg.mio_pad_attr[15].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[15].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_15_pull_en_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].pull_en.qe = mio_pad_attr_15_qe;
+
+ // F[pull_select_15]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_pull_select_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_pull_select_15_wd),
+ .d (hw2reg.mio_pad_attr[15].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[15].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_15_pull_select_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].pull_select.qe = mio_pad_attr_15_qe;
+
+ // F[keeper_en_15]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_keeper_en_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_keeper_en_15_wd),
+ .d (hw2reg.mio_pad_attr[15].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[15].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_15_keeper_en_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].keeper_en.qe = mio_pad_attr_15_qe;
+
+ // F[schmitt_en_15]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_schmitt_en_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_schmitt_en_15_wd),
+ .d (hw2reg.mio_pad_attr[15].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[15].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_15_schmitt_en_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].schmitt_en.qe = mio_pad_attr_15_qe;
+
+ // F[od_en_15]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_15_od_en_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_od_en_15_wd),
+ .d (hw2reg.mio_pad_attr[15].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[15].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_15_od_en_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].od_en.qe = mio_pad_attr_15_qe;
+
+ // F[slew_rate_15]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_15_slew_rate_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_slew_rate_15_wd),
+ .d (hw2reg.mio_pad_attr[15].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[15].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_15_slew_rate_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].slew_rate.qe = mio_pad_attr_15_qe;
+
+ // F[drive_strength_15]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_15_drive_strength_15 (
+ .re (mio_pad_attr_15_re),
+ .we (mio_pad_attr_15_gated_we),
+ .wd (mio_pad_attr_15_drive_strength_15_wd),
+ .d (hw2reg.mio_pad_attr[15].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_15_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[15].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_15_drive_strength_15_qs)
+ );
+ assign reg2hw.mio_pad_attr[15].drive_strength.qe = mio_pad_attr_15_qe;
+
+
+ // Subregister 16 of Multireg mio_pad_attr
+ // R[mio_pad_attr_16]: V(True)
+ logic mio_pad_attr_16_qe;
+ logic [8:0] mio_pad_attr_16_flds_we;
+ assign mio_pad_attr_16_qe = &mio_pad_attr_16_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_16_gated_we;
+ assign mio_pad_attr_16_gated_we = mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs;
+ // F[invert_16]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_invert_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_invert_16_wd),
+ .d (hw2reg.mio_pad_attr[16].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[16].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_16_invert_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].invert.qe = mio_pad_attr_16_qe;
+
+ // F[virtual_od_en_16]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_virtual_od_en_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_virtual_od_en_16_wd),
+ .d (hw2reg.mio_pad_attr[16].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[16].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_16_virtual_od_en_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].virtual_od_en.qe = mio_pad_attr_16_qe;
+
+ // F[pull_en_16]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_pull_en_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_pull_en_16_wd),
+ .d (hw2reg.mio_pad_attr[16].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[16].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_16_pull_en_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].pull_en.qe = mio_pad_attr_16_qe;
+
+ // F[pull_select_16]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_pull_select_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_pull_select_16_wd),
+ .d (hw2reg.mio_pad_attr[16].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[16].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_16_pull_select_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].pull_select.qe = mio_pad_attr_16_qe;
+
+ // F[keeper_en_16]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_keeper_en_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_keeper_en_16_wd),
+ .d (hw2reg.mio_pad_attr[16].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[16].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_16_keeper_en_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].keeper_en.qe = mio_pad_attr_16_qe;
+
+ // F[schmitt_en_16]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_schmitt_en_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_schmitt_en_16_wd),
+ .d (hw2reg.mio_pad_attr[16].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[16].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_16_schmitt_en_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].schmitt_en.qe = mio_pad_attr_16_qe;
+
+ // F[od_en_16]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_16_od_en_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_od_en_16_wd),
+ .d (hw2reg.mio_pad_attr[16].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[16].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_16_od_en_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].od_en.qe = mio_pad_attr_16_qe;
+
+ // F[slew_rate_16]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_16_slew_rate_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_slew_rate_16_wd),
+ .d (hw2reg.mio_pad_attr[16].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[16].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_16_slew_rate_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].slew_rate.qe = mio_pad_attr_16_qe;
+
+ // F[drive_strength_16]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_16_drive_strength_16 (
+ .re (mio_pad_attr_16_re),
+ .we (mio_pad_attr_16_gated_we),
+ .wd (mio_pad_attr_16_drive_strength_16_wd),
+ .d (hw2reg.mio_pad_attr[16].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_16_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[16].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_16_drive_strength_16_qs)
+ );
+ assign reg2hw.mio_pad_attr[16].drive_strength.qe = mio_pad_attr_16_qe;
+
+
+ // Subregister 17 of Multireg mio_pad_attr
+ // R[mio_pad_attr_17]: V(True)
+ logic mio_pad_attr_17_qe;
+ logic [8:0] mio_pad_attr_17_flds_we;
+ assign mio_pad_attr_17_qe = &mio_pad_attr_17_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_17_gated_we;
+ assign mio_pad_attr_17_gated_we = mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs;
+ // F[invert_17]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_invert_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_invert_17_wd),
+ .d (hw2reg.mio_pad_attr[17].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[17].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_17_invert_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].invert.qe = mio_pad_attr_17_qe;
+
+ // F[virtual_od_en_17]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_virtual_od_en_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_virtual_od_en_17_wd),
+ .d (hw2reg.mio_pad_attr[17].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[17].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_17_virtual_od_en_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].virtual_od_en.qe = mio_pad_attr_17_qe;
+
+ // F[pull_en_17]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_pull_en_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_pull_en_17_wd),
+ .d (hw2reg.mio_pad_attr[17].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[17].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_17_pull_en_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].pull_en.qe = mio_pad_attr_17_qe;
+
+ // F[pull_select_17]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_pull_select_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_pull_select_17_wd),
+ .d (hw2reg.mio_pad_attr[17].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[17].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_17_pull_select_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].pull_select.qe = mio_pad_attr_17_qe;
+
+ // F[keeper_en_17]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_keeper_en_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_keeper_en_17_wd),
+ .d (hw2reg.mio_pad_attr[17].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[17].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_17_keeper_en_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].keeper_en.qe = mio_pad_attr_17_qe;
+
+ // F[schmitt_en_17]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_schmitt_en_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_schmitt_en_17_wd),
+ .d (hw2reg.mio_pad_attr[17].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[17].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_17_schmitt_en_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].schmitt_en.qe = mio_pad_attr_17_qe;
+
+ // F[od_en_17]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_17_od_en_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_od_en_17_wd),
+ .d (hw2reg.mio_pad_attr[17].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[17].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_17_od_en_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].od_en.qe = mio_pad_attr_17_qe;
+
+ // F[slew_rate_17]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_17_slew_rate_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_slew_rate_17_wd),
+ .d (hw2reg.mio_pad_attr[17].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[17].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_17_slew_rate_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].slew_rate.qe = mio_pad_attr_17_qe;
+
+ // F[drive_strength_17]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_17_drive_strength_17 (
+ .re (mio_pad_attr_17_re),
+ .we (mio_pad_attr_17_gated_we),
+ .wd (mio_pad_attr_17_drive_strength_17_wd),
+ .d (hw2reg.mio_pad_attr[17].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_17_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[17].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_17_drive_strength_17_qs)
+ );
+ assign reg2hw.mio_pad_attr[17].drive_strength.qe = mio_pad_attr_17_qe;
+
+
+ // Subregister 18 of Multireg mio_pad_attr
+ // R[mio_pad_attr_18]: V(True)
+ logic mio_pad_attr_18_qe;
+ logic [8:0] mio_pad_attr_18_flds_we;
+ assign mio_pad_attr_18_qe = &mio_pad_attr_18_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_18_gated_we;
+ assign mio_pad_attr_18_gated_we = mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs;
+ // F[invert_18]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_invert_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_invert_18_wd),
+ .d (hw2reg.mio_pad_attr[18].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[18].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_18_invert_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].invert.qe = mio_pad_attr_18_qe;
+
+ // F[virtual_od_en_18]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_virtual_od_en_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_virtual_od_en_18_wd),
+ .d (hw2reg.mio_pad_attr[18].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[18].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_18_virtual_od_en_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].virtual_od_en.qe = mio_pad_attr_18_qe;
+
+ // F[pull_en_18]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_pull_en_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_pull_en_18_wd),
+ .d (hw2reg.mio_pad_attr[18].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[18].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_18_pull_en_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].pull_en.qe = mio_pad_attr_18_qe;
+
+ // F[pull_select_18]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_pull_select_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_pull_select_18_wd),
+ .d (hw2reg.mio_pad_attr[18].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[18].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_18_pull_select_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].pull_select.qe = mio_pad_attr_18_qe;
+
+ // F[keeper_en_18]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_keeper_en_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_keeper_en_18_wd),
+ .d (hw2reg.mio_pad_attr[18].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[18].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_18_keeper_en_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].keeper_en.qe = mio_pad_attr_18_qe;
+
+ // F[schmitt_en_18]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_schmitt_en_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_schmitt_en_18_wd),
+ .d (hw2reg.mio_pad_attr[18].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[18].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_18_schmitt_en_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].schmitt_en.qe = mio_pad_attr_18_qe;
+
+ // F[od_en_18]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_18_od_en_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_od_en_18_wd),
+ .d (hw2reg.mio_pad_attr[18].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[18].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_18_od_en_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].od_en.qe = mio_pad_attr_18_qe;
+
+ // F[slew_rate_18]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_18_slew_rate_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_slew_rate_18_wd),
+ .d (hw2reg.mio_pad_attr[18].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[18].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_18_slew_rate_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].slew_rate.qe = mio_pad_attr_18_qe;
+
+ // F[drive_strength_18]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_18_drive_strength_18 (
+ .re (mio_pad_attr_18_re),
+ .we (mio_pad_attr_18_gated_we),
+ .wd (mio_pad_attr_18_drive_strength_18_wd),
+ .d (hw2reg.mio_pad_attr[18].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_18_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[18].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_18_drive_strength_18_qs)
+ );
+ assign reg2hw.mio_pad_attr[18].drive_strength.qe = mio_pad_attr_18_qe;
+
+
+ // Subregister 19 of Multireg mio_pad_attr
+ // R[mio_pad_attr_19]: V(True)
+ logic mio_pad_attr_19_qe;
+ logic [8:0] mio_pad_attr_19_flds_we;
+ assign mio_pad_attr_19_qe = &mio_pad_attr_19_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_19_gated_we;
+ assign mio_pad_attr_19_gated_we = mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs;
+ // F[invert_19]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_invert_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_invert_19_wd),
+ .d (hw2reg.mio_pad_attr[19].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[19].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_19_invert_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].invert.qe = mio_pad_attr_19_qe;
+
+ // F[virtual_od_en_19]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_virtual_od_en_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_virtual_od_en_19_wd),
+ .d (hw2reg.mio_pad_attr[19].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[19].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_19_virtual_od_en_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].virtual_od_en.qe = mio_pad_attr_19_qe;
+
+ // F[pull_en_19]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_pull_en_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_pull_en_19_wd),
+ .d (hw2reg.mio_pad_attr[19].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[19].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_19_pull_en_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].pull_en.qe = mio_pad_attr_19_qe;
+
+ // F[pull_select_19]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_pull_select_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_pull_select_19_wd),
+ .d (hw2reg.mio_pad_attr[19].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[19].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_19_pull_select_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].pull_select.qe = mio_pad_attr_19_qe;
+
+ // F[keeper_en_19]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_keeper_en_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_keeper_en_19_wd),
+ .d (hw2reg.mio_pad_attr[19].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[19].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_19_keeper_en_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].keeper_en.qe = mio_pad_attr_19_qe;
+
+ // F[schmitt_en_19]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_schmitt_en_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_schmitt_en_19_wd),
+ .d (hw2reg.mio_pad_attr[19].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[19].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_19_schmitt_en_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].schmitt_en.qe = mio_pad_attr_19_qe;
+
+ // F[od_en_19]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_19_od_en_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_od_en_19_wd),
+ .d (hw2reg.mio_pad_attr[19].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[19].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_19_od_en_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].od_en.qe = mio_pad_attr_19_qe;
+
+ // F[slew_rate_19]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_19_slew_rate_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_slew_rate_19_wd),
+ .d (hw2reg.mio_pad_attr[19].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[19].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_19_slew_rate_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].slew_rate.qe = mio_pad_attr_19_qe;
+
+ // F[drive_strength_19]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_19_drive_strength_19 (
+ .re (mio_pad_attr_19_re),
+ .we (mio_pad_attr_19_gated_we),
+ .wd (mio_pad_attr_19_drive_strength_19_wd),
+ .d (hw2reg.mio_pad_attr[19].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_19_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[19].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_19_drive_strength_19_qs)
+ );
+ assign reg2hw.mio_pad_attr[19].drive_strength.qe = mio_pad_attr_19_qe;
+
+
+ // Subregister 20 of Multireg mio_pad_attr
+ // R[mio_pad_attr_20]: V(True)
+ logic mio_pad_attr_20_qe;
+ logic [8:0] mio_pad_attr_20_flds_we;
+ assign mio_pad_attr_20_qe = &mio_pad_attr_20_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_20_gated_we;
+ assign mio_pad_attr_20_gated_we = mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs;
+ // F[invert_20]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_invert_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_invert_20_wd),
+ .d (hw2reg.mio_pad_attr[20].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[20].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_20_invert_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].invert.qe = mio_pad_attr_20_qe;
+
+ // F[virtual_od_en_20]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_virtual_od_en_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_virtual_od_en_20_wd),
+ .d (hw2reg.mio_pad_attr[20].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[20].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_20_virtual_od_en_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].virtual_od_en.qe = mio_pad_attr_20_qe;
+
+ // F[pull_en_20]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_pull_en_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_pull_en_20_wd),
+ .d (hw2reg.mio_pad_attr[20].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[20].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_20_pull_en_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].pull_en.qe = mio_pad_attr_20_qe;
+
+ // F[pull_select_20]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_pull_select_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_pull_select_20_wd),
+ .d (hw2reg.mio_pad_attr[20].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[20].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_20_pull_select_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].pull_select.qe = mio_pad_attr_20_qe;
+
+ // F[keeper_en_20]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_keeper_en_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_keeper_en_20_wd),
+ .d (hw2reg.mio_pad_attr[20].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[20].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_20_keeper_en_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].keeper_en.qe = mio_pad_attr_20_qe;
+
+ // F[schmitt_en_20]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_schmitt_en_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_schmitt_en_20_wd),
+ .d (hw2reg.mio_pad_attr[20].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[20].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_20_schmitt_en_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].schmitt_en.qe = mio_pad_attr_20_qe;
+
+ // F[od_en_20]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_20_od_en_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_od_en_20_wd),
+ .d (hw2reg.mio_pad_attr[20].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[20].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_20_od_en_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].od_en.qe = mio_pad_attr_20_qe;
+
+ // F[slew_rate_20]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_20_slew_rate_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_slew_rate_20_wd),
+ .d (hw2reg.mio_pad_attr[20].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[20].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_20_slew_rate_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].slew_rate.qe = mio_pad_attr_20_qe;
+
+ // F[drive_strength_20]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_20_drive_strength_20 (
+ .re (mio_pad_attr_20_re),
+ .we (mio_pad_attr_20_gated_we),
+ .wd (mio_pad_attr_20_drive_strength_20_wd),
+ .d (hw2reg.mio_pad_attr[20].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_20_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[20].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_20_drive_strength_20_qs)
+ );
+ assign reg2hw.mio_pad_attr[20].drive_strength.qe = mio_pad_attr_20_qe;
+
+
+ // Subregister 21 of Multireg mio_pad_attr
+ // R[mio_pad_attr_21]: V(True)
+ logic mio_pad_attr_21_qe;
+ logic [8:0] mio_pad_attr_21_flds_we;
+ assign mio_pad_attr_21_qe = &mio_pad_attr_21_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_21_gated_we;
+ assign mio_pad_attr_21_gated_we = mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs;
+ // F[invert_21]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_invert_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_invert_21_wd),
+ .d (hw2reg.mio_pad_attr[21].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[21].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_21_invert_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].invert.qe = mio_pad_attr_21_qe;
+
+ // F[virtual_od_en_21]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_virtual_od_en_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_virtual_od_en_21_wd),
+ .d (hw2reg.mio_pad_attr[21].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[21].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_21_virtual_od_en_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].virtual_od_en.qe = mio_pad_attr_21_qe;
+
+ // F[pull_en_21]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_pull_en_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_pull_en_21_wd),
+ .d (hw2reg.mio_pad_attr[21].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[21].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_21_pull_en_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].pull_en.qe = mio_pad_attr_21_qe;
+
+ // F[pull_select_21]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_pull_select_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_pull_select_21_wd),
+ .d (hw2reg.mio_pad_attr[21].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[21].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_21_pull_select_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].pull_select.qe = mio_pad_attr_21_qe;
+
+ // F[keeper_en_21]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_keeper_en_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_keeper_en_21_wd),
+ .d (hw2reg.mio_pad_attr[21].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[21].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_21_keeper_en_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].keeper_en.qe = mio_pad_attr_21_qe;
+
+ // F[schmitt_en_21]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_schmitt_en_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_schmitt_en_21_wd),
+ .d (hw2reg.mio_pad_attr[21].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[21].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_21_schmitt_en_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].schmitt_en.qe = mio_pad_attr_21_qe;
+
+ // F[od_en_21]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_21_od_en_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_od_en_21_wd),
+ .d (hw2reg.mio_pad_attr[21].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[21].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_21_od_en_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].od_en.qe = mio_pad_attr_21_qe;
+
+ // F[slew_rate_21]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_21_slew_rate_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_slew_rate_21_wd),
+ .d (hw2reg.mio_pad_attr[21].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[21].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_21_slew_rate_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].slew_rate.qe = mio_pad_attr_21_qe;
+
+ // F[drive_strength_21]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_21_drive_strength_21 (
+ .re (mio_pad_attr_21_re),
+ .we (mio_pad_attr_21_gated_we),
+ .wd (mio_pad_attr_21_drive_strength_21_wd),
+ .d (hw2reg.mio_pad_attr[21].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_21_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[21].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_21_drive_strength_21_qs)
+ );
+ assign reg2hw.mio_pad_attr[21].drive_strength.qe = mio_pad_attr_21_qe;
+
+
+ // Subregister 22 of Multireg mio_pad_attr
+ // R[mio_pad_attr_22]: V(True)
+ logic mio_pad_attr_22_qe;
+ logic [8:0] mio_pad_attr_22_flds_we;
+ assign mio_pad_attr_22_qe = &mio_pad_attr_22_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_22_gated_we;
+ assign mio_pad_attr_22_gated_we = mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs;
+ // F[invert_22]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_invert_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_invert_22_wd),
+ .d (hw2reg.mio_pad_attr[22].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[22].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_22_invert_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].invert.qe = mio_pad_attr_22_qe;
+
+ // F[virtual_od_en_22]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_virtual_od_en_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_virtual_od_en_22_wd),
+ .d (hw2reg.mio_pad_attr[22].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[22].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_22_virtual_od_en_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].virtual_od_en.qe = mio_pad_attr_22_qe;
+
+ // F[pull_en_22]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_pull_en_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_pull_en_22_wd),
+ .d (hw2reg.mio_pad_attr[22].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[22].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_22_pull_en_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].pull_en.qe = mio_pad_attr_22_qe;
+
+ // F[pull_select_22]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_pull_select_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_pull_select_22_wd),
+ .d (hw2reg.mio_pad_attr[22].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[22].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_22_pull_select_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].pull_select.qe = mio_pad_attr_22_qe;
+
+ // F[keeper_en_22]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_keeper_en_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_keeper_en_22_wd),
+ .d (hw2reg.mio_pad_attr[22].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[22].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_22_keeper_en_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].keeper_en.qe = mio_pad_attr_22_qe;
+
+ // F[schmitt_en_22]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_schmitt_en_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_schmitt_en_22_wd),
+ .d (hw2reg.mio_pad_attr[22].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[22].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_22_schmitt_en_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].schmitt_en.qe = mio_pad_attr_22_qe;
+
+ // F[od_en_22]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_22_od_en_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_od_en_22_wd),
+ .d (hw2reg.mio_pad_attr[22].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[22].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_22_od_en_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].od_en.qe = mio_pad_attr_22_qe;
+
+ // F[slew_rate_22]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_22_slew_rate_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_slew_rate_22_wd),
+ .d (hw2reg.mio_pad_attr[22].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[22].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_22_slew_rate_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].slew_rate.qe = mio_pad_attr_22_qe;
+
+ // F[drive_strength_22]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_22_drive_strength_22 (
+ .re (mio_pad_attr_22_re),
+ .we (mio_pad_attr_22_gated_we),
+ .wd (mio_pad_attr_22_drive_strength_22_wd),
+ .d (hw2reg.mio_pad_attr[22].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_22_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[22].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_22_drive_strength_22_qs)
+ );
+ assign reg2hw.mio_pad_attr[22].drive_strength.qe = mio_pad_attr_22_qe;
+
+
+ // Subregister 23 of Multireg mio_pad_attr
+ // R[mio_pad_attr_23]: V(True)
+ logic mio_pad_attr_23_qe;
+ logic [8:0] mio_pad_attr_23_flds_we;
+ assign mio_pad_attr_23_qe = &mio_pad_attr_23_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_23_gated_we;
+ assign mio_pad_attr_23_gated_we = mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs;
+ // F[invert_23]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_invert_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_invert_23_wd),
+ .d (hw2reg.mio_pad_attr[23].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[23].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_23_invert_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].invert.qe = mio_pad_attr_23_qe;
+
+ // F[virtual_od_en_23]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_virtual_od_en_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_virtual_od_en_23_wd),
+ .d (hw2reg.mio_pad_attr[23].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[23].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_23_virtual_od_en_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].virtual_od_en.qe = mio_pad_attr_23_qe;
+
+ // F[pull_en_23]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_pull_en_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_pull_en_23_wd),
+ .d (hw2reg.mio_pad_attr[23].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[23].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_23_pull_en_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].pull_en.qe = mio_pad_attr_23_qe;
+
+ // F[pull_select_23]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_pull_select_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_pull_select_23_wd),
+ .d (hw2reg.mio_pad_attr[23].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[23].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_23_pull_select_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].pull_select.qe = mio_pad_attr_23_qe;
+
+ // F[keeper_en_23]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_keeper_en_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_keeper_en_23_wd),
+ .d (hw2reg.mio_pad_attr[23].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[23].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_23_keeper_en_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].keeper_en.qe = mio_pad_attr_23_qe;
+
+ // F[schmitt_en_23]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_schmitt_en_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_schmitt_en_23_wd),
+ .d (hw2reg.mio_pad_attr[23].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[23].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_23_schmitt_en_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].schmitt_en.qe = mio_pad_attr_23_qe;
+
+ // F[od_en_23]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_23_od_en_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_od_en_23_wd),
+ .d (hw2reg.mio_pad_attr[23].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[23].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_23_od_en_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].od_en.qe = mio_pad_attr_23_qe;
+
+ // F[slew_rate_23]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_23_slew_rate_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_slew_rate_23_wd),
+ .d (hw2reg.mio_pad_attr[23].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[23].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_23_slew_rate_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].slew_rate.qe = mio_pad_attr_23_qe;
+
+ // F[drive_strength_23]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_23_drive_strength_23 (
+ .re (mio_pad_attr_23_re),
+ .we (mio_pad_attr_23_gated_we),
+ .wd (mio_pad_attr_23_drive_strength_23_wd),
+ .d (hw2reg.mio_pad_attr[23].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_23_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[23].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_23_drive_strength_23_qs)
+ );
+ assign reg2hw.mio_pad_attr[23].drive_strength.qe = mio_pad_attr_23_qe;
+
+
+ // Subregister 24 of Multireg mio_pad_attr
+ // R[mio_pad_attr_24]: V(True)
+ logic mio_pad_attr_24_qe;
+ logic [8:0] mio_pad_attr_24_flds_we;
+ assign mio_pad_attr_24_qe = &mio_pad_attr_24_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_24_gated_we;
+ assign mio_pad_attr_24_gated_we = mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs;
+ // F[invert_24]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_invert_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_invert_24_wd),
+ .d (hw2reg.mio_pad_attr[24].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[24].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_24_invert_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].invert.qe = mio_pad_attr_24_qe;
+
+ // F[virtual_od_en_24]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_virtual_od_en_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_virtual_od_en_24_wd),
+ .d (hw2reg.mio_pad_attr[24].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[24].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_24_virtual_od_en_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].virtual_od_en.qe = mio_pad_attr_24_qe;
+
+ // F[pull_en_24]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_pull_en_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_pull_en_24_wd),
+ .d (hw2reg.mio_pad_attr[24].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[24].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_24_pull_en_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].pull_en.qe = mio_pad_attr_24_qe;
+
+ // F[pull_select_24]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_pull_select_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_pull_select_24_wd),
+ .d (hw2reg.mio_pad_attr[24].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[24].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_24_pull_select_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].pull_select.qe = mio_pad_attr_24_qe;
+
+ // F[keeper_en_24]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_keeper_en_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_keeper_en_24_wd),
+ .d (hw2reg.mio_pad_attr[24].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[24].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_24_keeper_en_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].keeper_en.qe = mio_pad_attr_24_qe;
+
+ // F[schmitt_en_24]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_schmitt_en_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_schmitt_en_24_wd),
+ .d (hw2reg.mio_pad_attr[24].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[24].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_24_schmitt_en_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].schmitt_en.qe = mio_pad_attr_24_qe;
+
+ // F[od_en_24]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_24_od_en_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_od_en_24_wd),
+ .d (hw2reg.mio_pad_attr[24].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[24].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_24_od_en_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].od_en.qe = mio_pad_attr_24_qe;
+
+ // F[slew_rate_24]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_24_slew_rate_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_slew_rate_24_wd),
+ .d (hw2reg.mio_pad_attr[24].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[24].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_24_slew_rate_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].slew_rate.qe = mio_pad_attr_24_qe;
+
+ // F[drive_strength_24]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_24_drive_strength_24 (
+ .re (mio_pad_attr_24_re),
+ .we (mio_pad_attr_24_gated_we),
+ .wd (mio_pad_attr_24_drive_strength_24_wd),
+ .d (hw2reg.mio_pad_attr[24].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_24_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[24].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_24_drive_strength_24_qs)
+ );
+ assign reg2hw.mio_pad_attr[24].drive_strength.qe = mio_pad_attr_24_qe;
+
+
+ // Subregister 25 of Multireg mio_pad_attr
+ // R[mio_pad_attr_25]: V(True)
+ logic mio_pad_attr_25_qe;
+ logic [8:0] mio_pad_attr_25_flds_we;
+ assign mio_pad_attr_25_qe = &mio_pad_attr_25_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_25_gated_we;
+ assign mio_pad_attr_25_gated_we = mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs;
+ // F[invert_25]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_invert_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_invert_25_wd),
+ .d (hw2reg.mio_pad_attr[25].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[25].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_25_invert_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].invert.qe = mio_pad_attr_25_qe;
+
+ // F[virtual_od_en_25]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_virtual_od_en_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_virtual_od_en_25_wd),
+ .d (hw2reg.mio_pad_attr[25].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[25].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_25_virtual_od_en_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].virtual_od_en.qe = mio_pad_attr_25_qe;
+
+ // F[pull_en_25]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_pull_en_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_pull_en_25_wd),
+ .d (hw2reg.mio_pad_attr[25].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[25].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_25_pull_en_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].pull_en.qe = mio_pad_attr_25_qe;
+
+ // F[pull_select_25]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_pull_select_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_pull_select_25_wd),
+ .d (hw2reg.mio_pad_attr[25].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[25].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_25_pull_select_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].pull_select.qe = mio_pad_attr_25_qe;
+
+ // F[keeper_en_25]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_keeper_en_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_keeper_en_25_wd),
+ .d (hw2reg.mio_pad_attr[25].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[25].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_25_keeper_en_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].keeper_en.qe = mio_pad_attr_25_qe;
+
+ // F[schmitt_en_25]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_schmitt_en_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_schmitt_en_25_wd),
+ .d (hw2reg.mio_pad_attr[25].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[25].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_25_schmitt_en_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].schmitt_en.qe = mio_pad_attr_25_qe;
+
+ // F[od_en_25]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_25_od_en_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_od_en_25_wd),
+ .d (hw2reg.mio_pad_attr[25].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[25].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_25_od_en_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].od_en.qe = mio_pad_attr_25_qe;
+
+ // F[slew_rate_25]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_25_slew_rate_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_slew_rate_25_wd),
+ .d (hw2reg.mio_pad_attr[25].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[25].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_25_slew_rate_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].slew_rate.qe = mio_pad_attr_25_qe;
+
+ // F[drive_strength_25]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_25_drive_strength_25 (
+ .re (mio_pad_attr_25_re),
+ .we (mio_pad_attr_25_gated_we),
+ .wd (mio_pad_attr_25_drive_strength_25_wd),
+ .d (hw2reg.mio_pad_attr[25].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_25_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[25].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_25_drive_strength_25_qs)
+ );
+ assign reg2hw.mio_pad_attr[25].drive_strength.qe = mio_pad_attr_25_qe;
+
+
+ // Subregister 26 of Multireg mio_pad_attr
+ // R[mio_pad_attr_26]: V(True)
+ logic mio_pad_attr_26_qe;
+ logic [8:0] mio_pad_attr_26_flds_we;
+ assign mio_pad_attr_26_qe = &mio_pad_attr_26_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_26_gated_we;
+ assign mio_pad_attr_26_gated_we = mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs;
+ // F[invert_26]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_invert_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_invert_26_wd),
+ .d (hw2reg.mio_pad_attr[26].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[26].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_26_invert_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].invert.qe = mio_pad_attr_26_qe;
+
+ // F[virtual_od_en_26]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_virtual_od_en_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_virtual_od_en_26_wd),
+ .d (hw2reg.mio_pad_attr[26].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[26].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_26_virtual_od_en_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].virtual_od_en.qe = mio_pad_attr_26_qe;
+
+ // F[pull_en_26]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_pull_en_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_pull_en_26_wd),
+ .d (hw2reg.mio_pad_attr[26].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[26].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_26_pull_en_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].pull_en.qe = mio_pad_attr_26_qe;
+
+ // F[pull_select_26]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_pull_select_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_pull_select_26_wd),
+ .d (hw2reg.mio_pad_attr[26].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[26].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_26_pull_select_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].pull_select.qe = mio_pad_attr_26_qe;
+
+ // F[keeper_en_26]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_keeper_en_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_keeper_en_26_wd),
+ .d (hw2reg.mio_pad_attr[26].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[26].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_26_keeper_en_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].keeper_en.qe = mio_pad_attr_26_qe;
+
+ // F[schmitt_en_26]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_schmitt_en_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_schmitt_en_26_wd),
+ .d (hw2reg.mio_pad_attr[26].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[26].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_26_schmitt_en_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].schmitt_en.qe = mio_pad_attr_26_qe;
+
+ // F[od_en_26]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_26_od_en_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_od_en_26_wd),
+ .d (hw2reg.mio_pad_attr[26].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[26].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_26_od_en_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].od_en.qe = mio_pad_attr_26_qe;
+
+ // F[slew_rate_26]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_26_slew_rate_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_slew_rate_26_wd),
+ .d (hw2reg.mio_pad_attr[26].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[26].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_26_slew_rate_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].slew_rate.qe = mio_pad_attr_26_qe;
+
+ // F[drive_strength_26]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_26_drive_strength_26 (
+ .re (mio_pad_attr_26_re),
+ .we (mio_pad_attr_26_gated_we),
+ .wd (mio_pad_attr_26_drive_strength_26_wd),
+ .d (hw2reg.mio_pad_attr[26].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_26_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[26].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_26_drive_strength_26_qs)
+ );
+ assign reg2hw.mio_pad_attr[26].drive_strength.qe = mio_pad_attr_26_qe;
+
+
+ // Subregister 27 of Multireg mio_pad_attr
+ // R[mio_pad_attr_27]: V(True)
+ logic mio_pad_attr_27_qe;
+ logic [8:0] mio_pad_attr_27_flds_we;
+ assign mio_pad_attr_27_qe = &mio_pad_attr_27_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_27_gated_we;
+ assign mio_pad_attr_27_gated_we = mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs;
+ // F[invert_27]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_invert_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_invert_27_wd),
+ .d (hw2reg.mio_pad_attr[27].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[27].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_27_invert_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].invert.qe = mio_pad_attr_27_qe;
+
+ // F[virtual_od_en_27]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_virtual_od_en_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_virtual_od_en_27_wd),
+ .d (hw2reg.mio_pad_attr[27].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[27].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_27_virtual_od_en_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].virtual_od_en.qe = mio_pad_attr_27_qe;
+
+ // F[pull_en_27]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_pull_en_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_pull_en_27_wd),
+ .d (hw2reg.mio_pad_attr[27].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[27].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_27_pull_en_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].pull_en.qe = mio_pad_attr_27_qe;
+
+ // F[pull_select_27]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_pull_select_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_pull_select_27_wd),
+ .d (hw2reg.mio_pad_attr[27].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[27].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_27_pull_select_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].pull_select.qe = mio_pad_attr_27_qe;
+
+ // F[keeper_en_27]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_keeper_en_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_keeper_en_27_wd),
+ .d (hw2reg.mio_pad_attr[27].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[27].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_27_keeper_en_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].keeper_en.qe = mio_pad_attr_27_qe;
+
+ // F[schmitt_en_27]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_schmitt_en_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_schmitt_en_27_wd),
+ .d (hw2reg.mio_pad_attr[27].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[27].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_27_schmitt_en_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].schmitt_en.qe = mio_pad_attr_27_qe;
+
+ // F[od_en_27]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_27_od_en_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_od_en_27_wd),
+ .d (hw2reg.mio_pad_attr[27].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[27].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_27_od_en_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].od_en.qe = mio_pad_attr_27_qe;
+
+ // F[slew_rate_27]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_27_slew_rate_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_slew_rate_27_wd),
+ .d (hw2reg.mio_pad_attr[27].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[27].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_27_slew_rate_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].slew_rate.qe = mio_pad_attr_27_qe;
+
+ // F[drive_strength_27]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_27_drive_strength_27 (
+ .re (mio_pad_attr_27_re),
+ .we (mio_pad_attr_27_gated_we),
+ .wd (mio_pad_attr_27_drive_strength_27_wd),
+ .d (hw2reg.mio_pad_attr[27].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_27_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[27].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_27_drive_strength_27_qs)
+ );
+ assign reg2hw.mio_pad_attr[27].drive_strength.qe = mio_pad_attr_27_qe;
+
+
+ // Subregister 28 of Multireg mio_pad_attr
+ // R[mio_pad_attr_28]: V(True)
+ logic mio_pad_attr_28_qe;
+ logic [8:0] mio_pad_attr_28_flds_we;
+ assign mio_pad_attr_28_qe = &mio_pad_attr_28_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_28_gated_we;
+ assign mio_pad_attr_28_gated_we = mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs;
+ // F[invert_28]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_invert_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_invert_28_wd),
+ .d (hw2reg.mio_pad_attr[28].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[28].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_28_invert_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].invert.qe = mio_pad_attr_28_qe;
+
+ // F[virtual_od_en_28]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_virtual_od_en_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_virtual_od_en_28_wd),
+ .d (hw2reg.mio_pad_attr[28].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[28].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_28_virtual_od_en_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].virtual_od_en.qe = mio_pad_attr_28_qe;
+
+ // F[pull_en_28]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_pull_en_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_pull_en_28_wd),
+ .d (hw2reg.mio_pad_attr[28].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[28].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_28_pull_en_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].pull_en.qe = mio_pad_attr_28_qe;
+
+ // F[pull_select_28]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_pull_select_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_pull_select_28_wd),
+ .d (hw2reg.mio_pad_attr[28].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[28].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_28_pull_select_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].pull_select.qe = mio_pad_attr_28_qe;
+
+ // F[keeper_en_28]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_keeper_en_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_keeper_en_28_wd),
+ .d (hw2reg.mio_pad_attr[28].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[28].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_28_keeper_en_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].keeper_en.qe = mio_pad_attr_28_qe;
+
+ // F[schmitt_en_28]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_schmitt_en_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_schmitt_en_28_wd),
+ .d (hw2reg.mio_pad_attr[28].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[28].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_28_schmitt_en_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].schmitt_en.qe = mio_pad_attr_28_qe;
+
+ // F[od_en_28]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_28_od_en_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_od_en_28_wd),
+ .d (hw2reg.mio_pad_attr[28].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[28].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_28_od_en_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].od_en.qe = mio_pad_attr_28_qe;
+
+ // F[slew_rate_28]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_28_slew_rate_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_slew_rate_28_wd),
+ .d (hw2reg.mio_pad_attr[28].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[28].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_28_slew_rate_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].slew_rate.qe = mio_pad_attr_28_qe;
+
+ // F[drive_strength_28]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_28_drive_strength_28 (
+ .re (mio_pad_attr_28_re),
+ .we (mio_pad_attr_28_gated_we),
+ .wd (mio_pad_attr_28_drive_strength_28_wd),
+ .d (hw2reg.mio_pad_attr[28].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_28_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[28].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_28_drive_strength_28_qs)
+ );
+ assign reg2hw.mio_pad_attr[28].drive_strength.qe = mio_pad_attr_28_qe;
+
+
+ // Subregister 29 of Multireg mio_pad_attr
+ // R[mio_pad_attr_29]: V(True)
+ logic mio_pad_attr_29_qe;
+ logic [8:0] mio_pad_attr_29_flds_we;
+ assign mio_pad_attr_29_qe = &mio_pad_attr_29_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_29_gated_we;
+ assign mio_pad_attr_29_gated_we = mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs;
+ // F[invert_29]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_invert_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_invert_29_wd),
+ .d (hw2reg.mio_pad_attr[29].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[29].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_29_invert_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].invert.qe = mio_pad_attr_29_qe;
+
+ // F[virtual_od_en_29]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_virtual_od_en_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_virtual_od_en_29_wd),
+ .d (hw2reg.mio_pad_attr[29].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[29].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_29_virtual_od_en_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].virtual_od_en.qe = mio_pad_attr_29_qe;
+
+ // F[pull_en_29]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_pull_en_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_pull_en_29_wd),
+ .d (hw2reg.mio_pad_attr[29].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[29].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_29_pull_en_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].pull_en.qe = mio_pad_attr_29_qe;
+
+ // F[pull_select_29]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_pull_select_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_pull_select_29_wd),
+ .d (hw2reg.mio_pad_attr[29].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[29].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_29_pull_select_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].pull_select.qe = mio_pad_attr_29_qe;
+
+ // F[keeper_en_29]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_keeper_en_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_keeper_en_29_wd),
+ .d (hw2reg.mio_pad_attr[29].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[29].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_29_keeper_en_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].keeper_en.qe = mio_pad_attr_29_qe;
+
+ // F[schmitt_en_29]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_schmitt_en_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_schmitt_en_29_wd),
+ .d (hw2reg.mio_pad_attr[29].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[29].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_29_schmitt_en_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].schmitt_en.qe = mio_pad_attr_29_qe;
+
+ // F[od_en_29]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_29_od_en_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_od_en_29_wd),
+ .d (hw2reg.mio_pad_attr[29].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[29].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_29_od_en_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].od_en.qe = mio_pad_attr_29_qe;
+
+ // F[slew_rate_29]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_29_slew_rate_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_slew_rate_29_wd),
+ .d (hw2reg.mio_pad_attr[29].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[29].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_29_slew_rate_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].slew_rate.qe = mio_pad_attr_29_qe;
+
+ // F[drive_strength_29]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_29_drive_strength_29 (
+ .re (mio_pad_attr_29_re),
+ .we (mio_pad_attr_29_gated_we),
+ .wd (mio_pad_attr_29_drive_strength_29_wd),
+ .d (hw2reg.mio_pad_attr[29].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_29_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[29].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_29_drive_strength_29_qs)
+ );
+ assign reg2hw.mio_pad_attr[29].drive_strength.qe = mio_pad_attr_29_qe;
+
+
+ // Subregister 30 of Multireg mio_pad_attr
+ // R[mio_pad_attr_30]: V(True)
+ logic mio_pad_attr_30_qe;
+ logic [8:0] mio_pad_attr_30_flds_we;
+ assign mio_pad_attr_30_qe = &mio_pad_attr_30_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_30_gated_we;
+ assign mio_pad_attr_30_gated_we = mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs;
+ // F[invert_30]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_invert_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_invert_30_wd),
+ .d (hw2reg.mio_pad_attr[30].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[30].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_30_invert_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].invert.qe = mio_pad_attr_30_qe;
+
+ // F[virtual_od_en_30]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_virtual_od_en_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_virtual_od_en_30_wd),
+ .d (hw2reg.mio_pad_attr[30].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[30].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_30_virtual_od_en_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].virtual_od_en.qe = mio_pad_attr_30_qe;
+
+ // F[pull_en_30]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_pull_en_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_pull_en_30_wd),
+ .d (hw2reg.mio_pad_attr[30].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[30].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_30_pull_en_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].pull_en.qe = mio_pad_attr_30_qe;
+
+ // F[pull_select_30]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_pull_select_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_pull_select_30_wd),
+ .d (hw2reg.mio_pad_attr[30].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[30].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_30_pull_select_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].pull_select.qe = mio_pad_attr_30_qe;
+
+ // F[keeper_en_30]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_keeper_en_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_keeper_en_30_wd),
+ .d (hw2reg.mio_pad_attr[30].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[30].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_30_keeper_en_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].keeper_en.qe = mio_pad_attr_30_qe;
+
+ // F[schmitt_en_30]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_schmitt_en_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_schmitt_en_30_wd),
+ .d (hw2reg.mio_pad_attr[30].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[30].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_30_schmitt_en_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].schmitt_en.qe = mio_pad_attr_30_qe;
+
+ // F[od_en_30]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_30_od_en_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_od_en_30_wd),
+ .d (hw2reg.mio_pad_attr[30].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[30].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_30_od_en_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].od_en.qe = mio_pad_attr_30_qe;
+
+ // F[slew_rate_30]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_30_slew_rate_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_slew_rate_30_wd),
+ .d (hw2reg.mio_pad_attr[30].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[30].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_30_slew_rate_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].slew_rate.qe = mio_pad_attr_30_qe;
+
+ // F[drive_strength_30]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_30_drive_strength_30 (
+ .re (mio_pad_attr_30_re),
+ .we (mio_pad_attr_30_gated_we),
+ .wd (mio_pad_attr_30_drive_strength_30_wd),
+ .d (hw2reg.mio_pad_attr[30].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_30_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[30].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_30_drive_strength_30_qs)
+ );
+ assign reg2hw.mio_pad_attr[30].drive_strength.qe = mio_pad_attr_30_qe;
+
+
+ // Subregister 31 of Multireg mio_pad_attr
+ // R[mio_pad_attr_31]: V(True)
+ logic mio_pad_attr_31_qe;
+ logic [8:0] mio_pad_attr_31_flds_we;
+ assign mio_pad_attr_31_qe = &mio_pad_attr_31_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_31_gated_we;
+ assign mio_pad_attr_31_gated_we = mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs;
+ // F[invert_31]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_invert_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_invert_31_wd),
+ .d (hw2reg.mio_pad_attr[31].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[31].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_31_invert_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].invert.qe = mio_pad_attr_31_qe;
+
+ // F[virtual_od_en_31]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_virtual_od_en_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_virtual_od_en_31_wd),
+ .d (hw2reg.mio_pad_attr[31].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[31].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_31_virtual_od_en_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].virtual_od_en.qe = mio_pad_attr_31_qe;
+
+ // F[pull_en_31]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_pull_en_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_pull_en_31_wd),
+ .d (hw2reg.mio_pad_attr[31].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[31].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_31_pull_en_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].pull_en.qe = mio_pad_attr_31_qe;
+
+ // F[pull_select_31]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_pull_select_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_pull_select_31_wd),
+ .d (hw2reg.mio_pad_attr[31].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[31].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_31_pull_select_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].pull_select.qe = mio_pad_attr_31_qe;
+
+ // F[keeper_en_31]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_keeper_en_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_keeper_en_31_wd),
+ .d (hw2reg.mio_pad_attr[31].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[31].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_31_keeper_en_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].keeper_en.qe = mio_pad_attr_31_qe;
+
+ // F[schmitt_en_31]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_schmitt_en_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_schmitt_en_31_wd),
+ .d (hw2reg.mio_pad_attr[31].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[31].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_31_schmitt_en_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].schmitt_en.qe = mio_pad_attr_31_qe;
+
+ // F[od_en_31]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_31_od_en_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_od_en_31_wd),
+ .d (hw2reg.mio_pad_attr[31].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[31].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_31_od_en_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].od_en.qe = mio_pad_attr_31_qe;
+
+ // F[slew_rate_31]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_31_slew_rate_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_slew_rate_31_wd),
+ .d (hw2reg.mio_pad_attr[31].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[31].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_31_slew_rate_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].slew_rate.qe = mio_pad_attr_31_qe;
+
+ // F[drive_strength_31]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_31_drive_strength_31 (
+ .re (mio_pad_attr_31_re),
+ .we (mio_pad_attr_31_gated_we),
+ .wd (mio_pad_attr_31_drive_strength_31_wd),
+ .d (hw2reg.mio_pad_attr[31].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_31_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[31].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_31_drive_strength_31_qs)
+ );
+ assign reg2hw.mio_pad_attr[31].drive_strength.qe = mio_pad_attr_31_qe;
+
+
+ // Subregister 32 of Multireg mio_pad_attr
+ // R[mio_pad_attr_32]: V(True)
+ logic mio_pad_attr_32_qe;
+ logic [8:0] mio_pad_attr_32_flds_we;
+ assign mio_pad_attr_32_qe = &mio_pad_attr_32_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_32_gated_we;
+ assign mio_pad_attr_32_gated_we = mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs;
+ // F[invert_32]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_invert_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_invert_32_wd),
+ .d (hw2reg.mio_pad_attr[32].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[32].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_32_invert_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].invert.qe = mio_pad_attr_32_qe;
+
+ // F[virtual_od_en_32]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_virtual_od_en_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_virtual_od_en_32_wd),
+ .d (hw2reg.mio_pad_attr[32].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[32].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_32_virtual_od_en_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].virtual_od_en.qe = mio_pad_attr_32_qe;
+
+ // F[pull_en_32]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_pull_en_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_pull_en_32_wd),
+ .d (hw2reg.mio_pad_attr[32].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[32].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_32_pull_en_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].pull_en.qe = mio_pad_attr_32_qe;
+
+ // F[pull_select_32]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_pull_select_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_pull_select_32_wd),
+ .d (hw2reg.mio_pad_attr[32].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[32].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_32_pull_select_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].pull_select.qe = mio_pad_attr_32_qe;
+
+ // F[keeper_en_32]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_keeper_en_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_keeper_en_32_wd),
+ .d (hw2reg.mio_pad_attr[32].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[32].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_32_keeper_en_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].keeper_en.qe = mio_pad_attr_32_qe;
+
+ // F[schmitt_en_32]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_schmitt_en_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_schmitt_en_32_wd),
+ .d (hw2reg.mio_pad_attr[32].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[32].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_32_schmitt_en_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].schmitt_en.qe = mio_pad_attr_32_qe;
+
+ // F[od_en_32]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_32_od_en_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_od_en_32_wd),
+ .d (hw2reg.mio_pad_attr[32].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[32].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_32_od_en_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].od_en.qe = mio_pad_attr_32_qe;
+
+ // F[slew_rate_32]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_32_slew_rate_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_slew_rate_32_wd),
+ .d (hw2reg.mio_pad_attr[32].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[32].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_32_slew_rate_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].slew_rate.qe = mio_pad_attr_32_qe;
+
+ // F[drive_strength_32]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_32_drive_strength_32 (
+ .re (mio_pad_attr_32_re),
+ .we (mio_pad_attr_32_gated_we),
+ .wd (mio_pad_attr_32_drive_strength_32_wd),
+ .d (hw2reg.mio_pad_attr[32].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_32_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[32].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_32_drive_strength_32_qs)
+ );
+ assign reg2hw.mio_pad_attr[32].drive_strength.qe = mio_pad_attr_32_qe;
+
+
+ // Subregister 33 of Multireg mio_pad_attr
+ // R[mio_pad_attr_33]: V(True)
+ logic mio_pad_attr_33_qe;
+ logic [8:0] mio_pad_attr_33_flds_we;
+ assign mio_pad_attr_33_qe = &mio_pad_attr_33_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_33_gated_we;
+ assign mio_pad_attr_33_gated_we = mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs;
+ // F[invert_33]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_invert_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_invert_33_wd),
+ .d (hw2reg.mio_pad_attr[33].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[33].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_33_invert_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].invert.qe = mio_pad_attr_33_qe;
+
+ // F[virtual_od_en_33]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_virtual_od_en_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_virtual_od_en_33_wd),
+ .d (hw2reg.mio_pad_attr[33].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[33].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_33_virtual_od_en_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].virtual_od_en.qe = mio_pad_attr_33_qe;
+
+ // F[pull_en_33]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_pull_en_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_pull_en_33_wd),
+ .d (hw2reg.mio_pad_attr[33].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[33].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_33_pull_en_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].pull_en.qe = mio_pad_attr_33_qe;
+
+ // F[pull_select_33]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_pull_select_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_pull_select_33_wd),
+ .d (hw2reg.mio_pad_attr[33].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[33].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_33_pull_select_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].pull_select.qe = mio_pad_attr_33_qe;
+
+ // F[keeper_en_33]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_keeper_en_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_keeper_en_33_wd),
+ .d (hw2reg.mio_pad_attr[33].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[33].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_33_keeper_en_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].keeper_en.qe = mio_pad_attr_33_qe;
+
+ // F[schmitt_en_33]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_schmitt_en_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_schmitt_en_33_wd),
+ .d (hw2reg.mio_pad_attr[33].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[33].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_33_schmitt_en_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].schmitt_en.qe = mio_pad_attr_33_qe;
+
+ // F[od_en_33]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_33_od_en_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_od_en_33_wd),
+ .d (hw2reg.mio_pad_attr[33].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[33].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_33_od_en_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].od_en.qe = mio_pad_attr_33_qe;
+
+ // F[slew_rate_33]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_33_slew_rate_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_slew_rate_33_wd),
+ .d (hw2reg.mio_pad_attr[33].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[33].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_33_slew_rate_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].slew_rate.qe = mio_pad_attr_33_qe;
+
+ // F[drive_strength_33]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_33_drive_strength_33 (
+ .re (mio_pad_attr_33_re),
+ .we (mio_pad_attr_33_gated_we),
+ .wd (mio_pad_attr_33_drive_strength_33_wd),
+ .d (hw2reg.mio_pad_attr[33].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_33_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[33].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_33_drive_strength_33_qs)
+ );
+ assign reg2hw.mio_pad_attr[33].drive_strength.qe = mio_pad_attr_33_qe;
+
+
+ // Subregister 34 of Multireg mio_pad_attr
+ // R[mio_pad_attr_34]: V(True)
+ logic mio_pad_attr_34_qe;
+ logic [8:0] mio_pad_attr_34_flds_we;
+ assign mio_pad_attr_34_qe = &mio_pad_attr_34_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_34_gated_we;
+ assign mio_pad_attr_34_gated_we = mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs;
+ // F[invert_34]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_invert_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_invert_34_wd),
+ .d (hw2reg.mio_pad_attr[34].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[34].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_34_invert_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].invert.qe = mio_pad_attr_34_qe;
+
+ // F[virtual_od_en_34]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_virtual_od_en_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_virtual_od_en_34_wd),
+ .d (hw2reg.mio_pad_attr[34].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[34].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_34_virtual_od_en_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].virtual_od_en.qe = mio_pad_attr_34_qe;
+
+ // F[pull_en_34]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_pull_en_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_pull_en_34_wd),
+ .d (hw2reg.mio_pad_attr[34].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[34].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_34_pull_en_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].pull_en.qe = mio_pad_attr_34_qe;
+
+ // F[pull_select_34]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_pull_select_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_pull_select_34_wd),
+ .d (hw2reg.mio_pad_attr[34].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[34].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_34_pull_select_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].pull_select.qe = mio_pad_attr_34_qe;
+
+ // F[keeper_en_34]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_keeper_en_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_keeper_en_34_wd),
+ .d (hw2reg.mio_pad_attr[34].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[34].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_34_keeper_en_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].keeper_en.qe = mio_pad_attr_34_qe;
+
+ // F[schmitt_en_34]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_schmitt_en_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_schmitt_en_34_wd),
+ .d (hw2reg.mio_pad_attr[34].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[34].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_34_schmitt_en_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].schmitt_en.qe = mio_pad_attr_34_qe;
+
+ // F[od_en_34]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_34_od_en_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_od_en_34_wd),
+ .d (hw2reg.mio_pad_attr[34].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[34].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_34_od_en_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].od_en.qe = mio_pad_attr_34_qe;
+
+ // F[slew_rate_34]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_34_slew_rate_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_slew_rate_34_wd),
+ .d (hw2reg.mio_pad_attr[34].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[34].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_34_slew_rate_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].slew_rate.qe = mio_pad_attr_34_qe;
+
+ // F[drive_strength_34]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_34_drive_strength_34 (
+ .re (mio_pad_attr_34_re),
+ .we (mio_pad_attr_34_gated_we),
+ .wd (mio_pad_attr_34_drive_strength_34_wd),
+ .d (hw2reg.mio_pad_attr[34].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_34_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[34].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_34_drive_strength_34_qs)
+ );
+ assign reg2hw.mio_pad_attr[34].drive_strength.qe = mio_pad_attr_34_qe;
+
+
+ // Subregister 35 of Multireg mio_pad_attr
+ // R[mio_pad_attr_35]: V(True)
+ logic mio_pad_attr_35_qe;
+ logic [8:0] mio_pad_attr_35_flds_we;
+ assign mio_pad_attr_35_qe = &mio_pad_attr_35_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_35_gated_we;
+ assign mio_pad_attr_35_gated_we = mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs;
+ // F[invert_35]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_invert_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_invert_35_wd),
+ .d (hw2reg.mio_pad_attr[35].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[35].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_35_invert_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].invert.qe = mio_pad_attr_35_qe;
+
+ // F[virtual_od_en_35]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_virtual_od_en_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_virtual_od_en_35_wd),
+ .d (hw2reg.mio_pad_attr[35].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[35].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_35_virtual_od_en_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].virtual_od_en.qe = mio_pad_attr_35_qe;
+
+ // F[pull_en_35]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_pull_en_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_pull_en_35_wd),
+ .d (hw2reg.mio_pad_attr[35].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[35].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_35_pull_en_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].pull_en.qe = mio_pad_attr_35_qe;
+
+ // F[pull_select_35]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_pull_select_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_pull_select_35_wd),
+ .d (hw2reg.mio_pad_attr[35].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[35].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_35_pull_select_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].pull_select.qe = mio_pad_attr_35_qe;
+
+ // F[keeper_en_35]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_keeper_en_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_keeper_en_35_wd),
+ .d (hw2reg.mio_pad_attr[35].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[35].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_35_keeper_en_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].keeper_en.qe = mio_pad_attr_35_qe;
+
+ // F[schmitt_en_35]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_schmitt_en_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_schmitt_en_35_wd),
+ .d (hw2reg.mio_pad_attr[35].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[35].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_35_schmitt_en_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].schmitt_en.qe = mio_pad_attr_35_qe;
+
+ // F[od_en_35]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_35_od_en_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_od_en_35_wd),
+ .d (hw2reg.mio_pad_attr[35].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[35].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_35_od_en_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].od_en.qe = mio_pad_attr_35_qe;
+
+ // F[slew_rate_35]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_35_slew_rate_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_slew_rate_35_wd),
+ .d (hw2reg.mio_pad_attr[35].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[35].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_35_slew_rate_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].slew_rate.qe = mio_pad_attr_35_qe;
+
+ // F[drive_strength_35]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_35_drive_strength_35 (
+ .re (mio_pad_attr_35_re),
+ .we (mio_pad_attr_35_gated_we),
+ .wd (mio_pad_attr_35_drive_strength_35_wd),
+ .d (hw2reg.mio_pad_attr[35].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_35_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[35].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_35_drive_strength_35_qs)
+ );
+ assign reg2hw.mio_pad_attr[35].drive_strength.qe = mio_pad_attr_35_qe;
+
+
+ // Subregister 36 of Multireg mio_pad_attr
+ // R[mio_pad_attr_36]: V(True)
+ logic mio_pad_attr_36_qe;
+ logic [8:0] mio_pad_attr_36_flds_we;
+ assign mio_pad_attr_36_qe = &mio_pad_attr_36_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_36_gated_we;
+ assign mio_pad_attr_36_gated_we = mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs;
+ // F[invert_36]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_invert_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_invert_36_wd),
+ .d (hw2reg.mio_pad_attr[36].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[36].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_36_invert_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].invert.qe = mio_pad_attr_36_qe;
+
+ // F[virtual_od_en_36]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_virtual_od_en_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_virtual_od_en_36_wd),
+ .d (hw2reg.mio_pad_attr[36].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[36].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_36_virtual_od_en_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].virtual_od_en.qe = mio_pad_attr_36_qe;
+
+ // F[pull_en_36]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_pull_en_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_pull_en_36_wd),
+ .d (hw2reg.mio_pad_attr[36].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[36].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_36_pull_en_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].pull_en.qe = mio_pad_attr_36_qe;
+
+ // F[pull_select_36]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_pull_select_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_pull_select_36_wd),
+ .d (hw2reg.mio_pad_attr[36].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[36].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_36_pull_select_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].pull_select.qe = mio_pad_attr_36_qe;
+
+ // F[keeper_en_36]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_keeper_en_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_keeper_en_36_wd),
+ .d (hw2reg.mio_pad_attr[36].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[36].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_36_keeper_en_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].keeper_en.qe = mio_pad_attr_36_qe;
+
+ // F[schmitt_en_36]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_schmitt_en_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_schmitt_en_36_wd),
+ .d (hw2reg.mio_pad_attr[36].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[36].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_36_schmitt_en_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].schmitt_en.qe = mio_pad_attr_36_qe;
+
+ // F[od_en_36]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_36_od_en_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_od_en_36_wd),
+ .d (hw2reg.mio_pad_attr[36].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[36].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_36_od_en_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].od_en.qe = mio_pad_attr_36_qe;
+
+ // F[slew_rate_36]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_36_slew_rate_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_slew_rate_36_wd),
+ .d (hw2reg.mio_pad_attr[36].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[36].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_36_slew_rate_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].slew_rate.qe = mio_pad_attr_36_qe;
+
+ // F[drive_strength_36]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_36_drive_strength_36 (
+ .re (mio_pad_attr_36_re),
+ .we (mio_pad_attr_36_gated_we),
+ .wd (mio_pad_attr_36_drive_strength_36_wd),
+ .d (hw2reg.mio_pad_attr[36].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_36_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[36].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_36_drive_strength_36_qs)
+ );
+ assign reg2hw.mio_pad_attr[36].drive_strength.qe = mio_pad_attr_36_qe;
+
+
+ // Subregister 37 of Multireg mio_pad_attr
+ // R[mio_pad_attr_37]: V(True)
+ logic mio_pad_attr_37_qe;
+ logic [8:0] mio_pad_attr_37_flds_we;
+ assign mio_pad_attr_37_qe = &mio_pad_attr_37_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_37_gated_we;
+ assign mio_pad_attr_37_gated_we = mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs;
+ // F[invert_37]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_invert_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_invert_37_wd),
+ .d (hw2reg.mio_pad_attr[37].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[37].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_37_invert_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].invert.qe = mio_pad_attr_37_qe;
+
+ // F[virtual_od_en_37]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_virtual_od_en_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_virtual_od_en_37_wd),
+ .d (hw2reg.mio_pad_attr[37].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[37].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_37_virtual_od_en_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].virtual_od_en.qe = mio_pad_attr_37_qe;
+
+ // F[pull_en_37]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_pull_en_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_pull_en_37_wd),
+ .d (hw2reg.mio_pad_attr[37].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[37].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_37_pull_en_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].pull_en.qe = mio_pad_attr_37_qe;
+
+ // F[pull_select_37]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_pull_select_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_pull_select_37_wd),
+ .d (hw2reg.mio_pad_attr[37].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[37].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_37_pull_select_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].pull_select.qe = mio_pad_attr_37_qe;
+
+ // F[keeper_en_37]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_keeper_en_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_keeper_en_37_wd),
+ .d (hw2reg.mio_pad_attr[37].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[37].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_37_keeper_en_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].keeper_en.qe = mio_pad_attr_37_qe;
+
+ // F[schmitt_en_37]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_schmitt_en_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_schmitt_en_37_wd),
+ .d (hw2reg.mio_pad_attr[37].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[37].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_37_schmitt_en_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].schmitt_en.qe = mio_pad_attr_37_qe;
+
+ // F[od_en_37]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_37_od_en_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_od_en_37_wd),
+ .d (hw2reg.mio_pad_attr[37].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[37].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_37_od_en_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].od_en.qe = mio_pad_attr_37_qe;
+
+ // F[slew_rate_37]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_37_slew_rate_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_slew_rate_37_wd),
+ .d (hw2reg.mio_pad_attr[37].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[37].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_37_slew_rate_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].slew_rate.qe = mio_pad_attr_37_qe;
+
+ // F[drive_strength_37]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_37_drive_strength_37 (
+ .re (mio_pad_attr_37_re),
+ .we (mio_pad_attr_37_gated_we),
+ .wd (mio_pad_attr_37_drive_strength_37_wd),
+ .d (hw2reg.mio_pad_attr[37].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_37_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[37].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_37_drive_strength_37_qs)
+ );
+ assign reg2hw.mio_pad_attr[37].drive_strength.qe = mio_pad_attr_37_qe;
+
+
+ // Subregister 38 of Multireg mio_pad_attr
+ // R[mio_pad_attr_38]: V(True)
+ logic mio_pad_attr_38_qe;
+ logic [8:0] mio_pad_attr_38_flds_we;
+ assign mio_pad_attr_38_qe = &mio_pad_attr_38_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_38_gated_we;
+ assign mio_pad_attr_38_gated_we = mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs;
+ // F[invert_38]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_invert_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_invert_38_wd),
+ .d (hw2reg.mio_pad_attr[38].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[38].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_38_invert_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].invert.qe = mio_pad_attr_38_qe;
+
+ // F[virtual_od_en_38]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_virtual_od_en_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_virtual_od_en_38_wd),
+ .d (hw2reg.mio_pad_attr[38].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[38].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_38_virtual_od_en_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].virtual_od_en.qe = mio_pad_attr_38_qe;
+
+ // F[pull_en_38]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_pull_en_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_pull_en_38_wd),
+ .d (hw2reg.mio_pad_attr[38].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[38].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_38_pull_en_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].pull_en.qe = mio_pad_attr_38_qe;
+
+ // F[pull_select_38]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_pull_select_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_pull_select_38_wd),
+ .d (hw2reg.mio_pad_attr[38].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[38].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_38_pull_select_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].pull_select.qe = mio_pad_attr_38_qe;
+
+ // F[keeper_en_38]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_keeper_en_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_keeper_en_38_wd),
+ .d (hw2reg.mio_pad_attr[38].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[38].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_38_keeper_en_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].keeper_en.qe = mio_pad_attr_38_qe;
+
+ // F[schmitt_en_38]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_schmitt_en_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_schmitt_en_38_wd),
+ .d (hw2reg.mio_pad_attr[38].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[38].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_38_schmitt_en_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].schmitt_en.qe = mio_pad_attr_38_qe;
+
+ // F[od_en_38]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_38_od_en_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_od_en_38_wd),
+ .d (hw2reg.mio_pad_attr[38].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[38].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_38_od_en_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].od_en.qe = mio_pad_attr_38_qe;
+
+ // F[slew_rate_38]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_38_slew_rate_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_slew_rate_38_wd),
+ .d (hw2reg.mio_pad_attr[38].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[38].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_38_slew_rate_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].slew_rate.qe = mio_pad_attr_38_qe;
+
+ // F[drive_strength_38]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_38_drive_strength_38 (
+ .re (mio_pad_attr_38_re),
+ .we (mio_pad_attr_38_gated_we),
+ .wd (mio_pad_attr_38_drive_strength_38_wd),
+ .d (hw2reg.mio_pad_attr[38].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_38_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[38].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_38_drive_strength_38_qs)
+ );
+ assign reg2hw.mio_pad_attr[38].drive_strength.qe = mio_pad_attr_38_qe;
+
+
+ // Subregister 39 of Multireg mio_pad_attr
+ // R[mio_pad_attr_39]: V(True)
+ logic mio_pad_attr_39_qe;
+ logic [8:0] mio_pad_attr_39_flds_we;
+ assign mio_pad_attr_39_qe = &mio_pad_attr_39_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_39_gated_we;
+ assign mio_pad_attr_39_gated_we = mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs;
+ // F[invert_39]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_invert_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_invert_39_wd),
+ .d (hw2reg.mio_pad_attr[39].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[39].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_39_invert_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].invert.qe = mio_pad_attr_39_qe;
+
+ // F[virtual_od_en_39]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_virtual_od_en_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_virtual_od_en_39_wd),
+ .d (hw2reg.mio_pad_attr[39].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[39].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_39_virtual_od_en_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].virtual_od_en.qe = mio_pad_attr_39_qe;
+
+ // F[pull_en_39]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_pull_en_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_pull_en_39_wd),
+ .d (hw2reg.mio_pad_attr[39].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[39].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_39_pull_en_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].pull_en.qe = mio_pad_attr_39_qe;
+
+ // F[pull_select_39]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_pull_select_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_pull_select_39_wd),
+ .d (hw2reg.mio_pad_attr[39].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[39].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_39_pull_select_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].pull_select.qe = mio_pad_attr_39_qe;
+
+ // F[keeper_en_39]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_keeper_en_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_keeper_en_39_wd),
+ .d (hw2reg.mio_pad_attr[39].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[39].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_39_keeper_en_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].keeper_en.qe = mio_pad_attr_39_qe;
+
+ // F[schmitt_en_39]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_schmitt_en_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_schmitt_en_39_wd),
+ .d (hw2reg.mio_pad_attr[39].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[39].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_39_schmitt_en_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].schmitt_en.qe = mio_pad_attr_39_qe;
+
+ // F[od_en_39]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_39_od_en_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_od_en_39_wd),
+ .d (hw2reg.mio_pad_attr[39].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[39].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_39_od_en_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].od_en.qe = mio_pad_attr_39_qe;
+
+ // F[slew_rate_39]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_39_slew_rate_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_slew_rate_39_wd),
+ .d (hw2reg.mio_pad_attr[39].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[39].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_39_slew_rate_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].slew_rate.qe = mio_pad_attr_39_qe;
+
+ // F[drive_strength_39]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_39_drive_strength_39 (
+ .re (mio_pad_attr_39_re),
+ .we (mio_pad_attr_39_gated_we),
+ .wd (mio_pad_attr_39_drive_strength_39_wd),
+ .d (hw2reg.mio_pad_attr[39].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_39_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[39].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_39_drive_strength_39_qs)
+ );
+ assign reg2hw.mio_pad_attr[39].drive_strength.qe = mio_pad_attr_39_qe;
+
+
+ // Subregister 40 of Multireg mio_pad_attr
+ // R[mio_pad_attr_40]: V(True)
+ logic mio_pad_attr_40_qe;
+ logic [8:0] mio_pad_attr_40_flds_we;
+ assign mio_pad_attr_40_qe = &mio_pad_attr_40_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_40_gated_we;
+ assign mio_pad_attr_40_gated_we = mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs;
+ // F[invert_40]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_invert_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_invert_40_wd),
+ .d (hw2reg.mio_pad_attr[40].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[40].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_40_invert_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].invert.qe = mio_pad_attr_40_qe;
+
+ // F[virtual_od_en_40]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_virtual_od_en_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_virtual_od_en_40_wd),
+ .d (hw2reg.mio_pad_attr[40].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[40].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_40_virtual_od_en_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].virtual_od_en.qe = mio_pad_attr_40_qe;
+
+ // F[pull_en_40]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_pull_en_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_pull_en_40_wd),
+ .d (hw2reg.mio_pad_attr[40].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[40].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_40_pull_en_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].pull_en.qe = mio_pad_attr_40_qe;
+
+ // F[pull_select_40]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_pull_select_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_pull_select_40_wd),
+ .d (hw2reg.mio_pad_attr[40].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[40].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_40_pull_select_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].pull_select.qe = mio_pad_attr_40_qe;
+
+ // F[keeper_en_40]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_keeper_en_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_keeper_en_40_wd),
+ .d (hw2reg.mio_pad_attr[40].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[40].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_40_keeper_en_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].keeper_en.qe = mio_pad_attr_40_qe;
+
+ // F[schmitt_en_40]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_schmitt_en_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_schmitt_en_40_wd),
+ .d (hw2reg.mio_pad_attr[40].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[40].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_40_schmitt_en_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].schmitt_en.qe = mio_pad_attr_40_qe;
+
+ // F[od_en_40]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_40_od_en_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_od_en_40_wd),
+ .d (hw2reg.mio_pad_attr[40].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[40].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_40_od_en_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].od_en.qe = mio_pad_attr_40_qe;
+
+ // F[slew_rate_40]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_40_slew_rate_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_slew_rate_40_wd),
+ .d (hw2reg.mio_pad_attr[40].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[40].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_40_slew_rate_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].slew_rate.qe = mio_pad_attr_40_qe;
+
+ // F[drive_strength_40]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_40_drive_strength_40 (
+ .re (mio_pad_attr_40_re),
+ .we (mio_pad_attr_40_gated_we),
+ .wd (mio_pad_attr_40_drive_strength_40_wd),
+ .d (hw2reg.mio_pad_attr[40].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_40_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[40].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_40_drive_strength_40_qs)
+ );
+ assign reg2hw.mio_pad_attr[40].drive_strength.qe = mio_pad_attr_40_qe;
+
+
+ // Subregister 41 of Multireg mio_pad_attr
+ // R[mio_pad_attr_41]: V(True)
+ logic mio_pad_attr_41_qe;
+ logic [8:0] mio_pad_attr_41_flds_we;
+ assign mio_pad_attr_41_qe = &mio_pad_attr_41_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_41_gated_we;
+ assign mio_pad_attr_41_gated_we = mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs;
+ // F[invert_41]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_invert_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_invert_41_wd),
+ .d (hw2reg.mio_pad_attr[41].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[41].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_41_invert_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].invert.qe = mio_pad_attr_41_qe;
+
+ // F[virtual_od_en_41]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_virtual_od_en_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_virtual_od_en_41_wd),
+ .d (hw2reg.mio_pad_attr[41].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[41].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_41_virtual_od_en_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].virtual_od_en.qe = mio_pad_attr_41_qe;
+
+ // F[pull_en_41]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_pull_en_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_pull_en_41_wd),
+ .d (hw2reg.mio_pad_attr[41].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[41].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_41_pull_en_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].pull_en.qe = mio_pad_attr_41_qe;
+
+ // F[pull_select_41]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_pull_select_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_pull_select_41_wd),
+ .d (hw2reg.mio_pad_attr[41].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[41].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_41_pull_select_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].pull_select.qe = mio_pad_attr_41_qe;
+
+ // F[keeper_en_41]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_keeper_en_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_keeper_en_41_wd),
+ .d (hw2reg.mio_pad_attr[41].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[41].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_41_keeper_en_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].keeper_en.qe = mio_pad_attr_41_qe;
+
+ // F[schmitt_en_41]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_schmitt_en_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_schmitt_en_41_wd),
+ .d (hw2reg.mio_pad_attr[41].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[41].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_41_schmitt_en_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].schmitt_en.qe = mio_pad_attr_41_qe;
+
+ // F[od_en_41]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_41_od_en_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_od_en_41_wd),
+ .d (hw2reg.mio_pad_attr[41].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[41].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_41_od_en_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].od_en.qe = mio_pad_attr_41_qe;
+
+ // F[slew_rate_41]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_41_slew_rate_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_slew_rate_41_wd),
+ .d (hw2reg.mio_pad_attr[41].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[41].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_41_slew_rate_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].slew_rate.qe = mio_pad_attr_41_qe;
+
+ // F[drive_strength_41]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_41_drive_strength_41 (
+ .re (mio_pad_attr_41_re),
+ .we (mio_pad_attr_41_gated_we),
+ .wd (mio_pad_attr_41_drive_strength_41_wd),
+ .d (hw2reg.mio_pad_attr[41].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_41_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[41].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_41_drive_strength_41_qs)
+ );
+ assign reg2hw.mio_pad_attr[41].drive_strength.qe = mio_pad_attr_41_qe;
+
+
+ // Subregister 42 of Multireg mio_pad_attr
+ // R[mio_pad_attr_42]: V(True)
+ logic mio_pad_attr_42_qe;
+ logic [8:0] mio_pad_attr_42_flds_we;
+ assign mio_pad_attr_42_qe = &mio_pad_attr_42_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_42_gated_we;
+ assign mio_pad_attr_42_gated_we = mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs;
+ // F[invert_42]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_invert_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_invert_42_wd),
+ .d (hw2reg.mio_pad_attr[42].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[42].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_42_invert_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].invert.qe = mio_pad_attr_42_qe;
+
+ // F[virtual_od_en_42]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_virtual_od_en_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_virtual_od_en_42_wd),
+ .d (hw2reg.mio_pad_attr[42].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[42].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_42_virtual_od_en_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].virtual_od_en.qe = mio_pad_attr_42_qe;
+
+ // F[pull_en_42]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_pull_en_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_pull_en_42_wd),
+ .d (hw2reg.mio_pad_attr[42].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[42].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_42_pull_en_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].pull_en.qe = mio_pad_attr_42_qe;
+
+ // F[pull_select_42]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_pull_select_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_pull_select_42_wd),
+ .d (hw2reg.mio_pad_attr[42].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[42].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_42_pull_select_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].pull_select.qe = mio_pad_attr_42_qe;
+
+ // F[keeper_en_42]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_keeper_en_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_keeper_en_42_wd),
+ .d (hw2reg.mio_pad_attr[42].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[42].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_42_keeper_en_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].keeper_en.qe = mio_pad_attr_42_qe;
+
+ // F[schmitt_en_42]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_schmitt_en_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_schmitt_en_42_wd),
+ .d (hw2reg.mio_pad_attr[42].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[42].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_42_schmitt_en_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].schmitt_en.qe = mio_pad_attr_42_qe;
+
+ // F[od_en_42]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_42_od_en_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_od_en_42_wd),
+ .d (hw2reg.mio_pad_attr[42].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[42].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_42_od_en_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].od_en.qe = mio_pad_attr_42_qe;
+
+ // F[slew_rate_42]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_42_slew_rate_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_slew_rate_42_wd),
+ .d (hw2reg.mio_pad_attr[42].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[42].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_42_slew_rate_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].slew_rate.qe = mio_pad_attr_42_qe;
+
+ // F[drive_strength_42]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_42_drive_strength_42 (
+ .re (mio_pad_attr_42_re),
+ .we (mio_pad_attr_42_gated_we),
+ .wd (mio_pad_attr_42_drive_strength_42_wd),
+ .d (hw2reg.mio_pad_attr[42].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_42_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[42].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_42_drive_strength_42_qs)
+ );
+ assign reg2hw.mio_pad_attr[42].drive_strength.qe = mio_pad_attr_42_qe;
+
+
+ // Subregister 43 of Multireg mio_pad_attr
+ // R[mio_pad_attr_43]: V(True)
+ logic mio_pad_attr_43_qe;
+ logic [8:0] mio_pad_attr_43_flds_we;
+ assign mio_pad_attr_43_qe = &mio_pad_attr_43_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_43_gated_we;
+ assign mio_pad_attr_43_gated_we = mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs;
+ // F[invert_43]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_invert_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_invert_43_wd),
+ .d (hw2reg.mio_pad_attr[43].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[43].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_43_invert_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].invert.qe = mio_pad_attr_43_qe;
+
+ // F[virtual_od_en_43]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_virtual_od_en_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_virtual_od_en_43_wd),
+ .d (hw2reg.mio_pad_attr[43].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[43].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_43_virtual_od_en_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].virtual_od_en.qe = mio_pad_attr_43_qe;
+
+ // F[pull_en_43]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_pull_en_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_pull_en_43_wd),
+ .d (hw2reg.mio_pad_attr[43].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[43].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_43_pull_en_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].pull_en.qe = mio_pad_attr_43_qe;
+
+ // F[pull_select_43]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_pull_select_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_pull_select_43_wd),
+ .d (hw2reg.mio_pad_attr[43].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[43].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_43_pull_select_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].pull_select.qe = mio_pad_attr_43_qe;
+
+ // F[keeper_en_43]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_keeper_en_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_keeper_en_43_wd),
+ .d (hw2reg.mio_pad_attr[43].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[43].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_43_keeper_en_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].keeper_en.qe = mio_pad_attr_43_qe;
+
+ // F[schmitt_en_43]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_schmitt_en_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_schmitt_en_43_wd),
+ .d (hw2reg.mio_pad_attr[43].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[43].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_43_schmitt_en_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].schmitt_en.qe = mio_pad_attr_43_qe;
+
+ // F[od_en_43]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_43_od_en_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_od_en_43_wd),
+ .d (hw2reg.mio_pad_attr[43].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[43].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_43_od_en_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].od_en.qe = mio_pad_attr_43_qe;
+
+ // F[slew_rate_43]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_43_slew_rate_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_slew_rate_43_wd),
+ .d (hw2reg.mio_pad_attr[43].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[43].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_43_slew_rate_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].slew_rate.qe = mio_pad_attr_43_qe;
+
+ // F[drive_strength_43]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_43_drive_strength_43 (
+ .re (mio_pad_attr_43_re),
+ .we (mio_pad_attr_43_gated_we),
+ .wd (mio_pad_attr_43_drive_strength_43_wd),
+ .d (hw2reg.mio_pad_attr[43].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_43_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[43].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_43_drive_strength_43_qs)
+ );
+ assign reg2hw.mio_pad_attr[43].drive_strength.qe = mio_pad_attr_43_qe;
+
+
+ // Subregister 44 of Multireg mio_pad_attr
+ // R[mio_pad_attr_44]: V(True)
+ logic mio_pad_attr_44_qe;
+ logic [8:0] mio_pad_attr_44_flds_we;
+ assign mio_pad_attr_44_qe = &mio_pad_attr_44_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_44_gated_we;
+ assign mio_pad_attr_44_gated_we = mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs;
+ // F[invert_44]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_invert_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_invert_44_wd),
+ .d (hw2reg.mio_pad_attr[44].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[44].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_44_invert_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].invert.qe = mio_pad_attr_44_qe;
+
+ // F[virtual_od_en_44]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_virtual_od_en_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_virtual_od_en_44_wd),
+ .d (hw2reg.mio_pad_attr[44].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[44].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_44_virtual_od_en_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].virtual_od_en.qe = mio_pad_attr_44_qe;
+
+ // F[pull_en_44]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_pull_en_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_pull_en_44_wd),
+ .d (hw2reg.mio_pad_attr[44].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[44].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_44_pull_en_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].pull_en.qe = mio_pad_attr_44_qe;
+
+ // F[pull_select_44]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_pull_select_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_pull_select_44_wd),
+ .d (hw2reg.mio_pad_attr[44].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[44].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_44_pull_select_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].pull_select.qe = mio_pad_attr_44_qe;
+
+ // F[keeper_en_44]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_keeper_en_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_keeper_en_44_wd),
+ .d (hw2reg.mio_pad_attr[44].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[44].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_44_keeper_en_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].keeper_en.qe = mio_pad_attr_44_qe;
+
+ // F[schmitt_en_44]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_schmitt_en_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_schmitt_en_44_wd),
+ .d (hw2reg.mio_pad_attr[44].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[44].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_44_schmitt_en_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].schmitt_en.qe = mio_pad_attr_44_qe;
+
+ // F[od_en_44]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_44_od_en_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_od_en_44_wd),
+ .d (hw2reg.mio_pad_attr[44].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[44].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_44_od_en_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].od_en.qe = mio_pad_attr_44_qe;
+
+ // F[slew_rate_44]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_44_slew_rate_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_slew_rate_44_wd),
+ .d (hw2reg.mio_pad_attr[44].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[44].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_44_slew_rate_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].slew_rate.qe = mio_pad_attr_44_qe;
+
+ // F[drive_strength_44]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_44_drive_strength_44 (
+ .re (mio_pad_attr_44_re),
+ .we (mio_pad_attr_44_gated_we),
+ .wd (mio_pad_attr_44_drive_strength_44_wd),
+ .d (hw2reg.mio_pad_attr[44].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_44_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[44].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_44_drive_strength_44_qs)
+ );
+ assign reg2hw.mio_pad_attr[44].drive_strength.qe = mio_pad_attr_44_qe;
+
+
+ // Subregister 45 of Multireg mio_pad_attr
+ // R[mio_pad_attr_45]: V(True)
+ logic mio_pad_attr_45_qe;
+ logic [8:0] mio_pad_attr_45_flds_we;
+ assign mio_pad_attr_45_qe = &mio_pad_attr_45_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_45_gated_we;
+ assign mio_pad_attr_45_gated_we = mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs;
+ // F[invert_45]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_invert_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_invert_45_wd),
+ .d (hw2reg.mio_pad_attr[45].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[45].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_45_invert_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].invert.qe = mio_pad_attr_45_qe;
+
+ // F[virtual_od_en_45]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_virtual_od_en_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_virtual_od_en_45_wd),
+ .d (hw2reg.mio_pad_attr[45].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[45].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_45_virtual_od_en_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].virtual_od_en.qe = mio_pad_attr_45_qe;
+
+ // F[pull_en_45]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_pull_en_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_pull_en_45_wd),
+ .d (hw2reg.mio_pad_attr[45].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[45].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_45_pull_en_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].pull_en.qe = mio_pad_attr_45_qe;
+
+ // F[pull_select_45]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_pull_select_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_pull_select_45_wd),
+ .d (hw2reg.mio_pad_attr[45].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[45].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_45_pull_select_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].pull_select.qe = mio_pad_attr_45_qe;
+
+ // F[keeper_en_45]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_keeper_en_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_keeper_en_45_wd),
+ .d (hw2reg.mio_pad_attr[45].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[45].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_45_keeper_en_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].keeper_en.qe = mio_pad_attr_45_qe;
+
+ // F[schmitt_en_45]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_schmitt_en_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_schmitt_en_45_wd),
+ .d (hw2reg.mio_pad_attr[45].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[45].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_45_schmitt_en_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].schmitt_en.qe = mio_pad_attr_45_qe;
+
+ // F[od_en_45]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_45_od_en_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_od_en_45_wd),
+ .d (hw2reg.mio_pad_attr[45].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[45].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_45_od_en_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].od_en.qe = mio_pad_attr_45_qe;
+
+ // F[slew_rate_45]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_45_slew_rate_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_slew_rate_45_wd),
+ .d (hw2reg.mio_pad_attr[45].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[45].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_45_slew_rate_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].slew_rate.qe = mio_pad_attr_45_qe;
+
+ // F[drive_strength_45]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_45_drive_strength_45 (
+ .re (mio_pad_attr_45_re),
+ .we (mio_pad_attr_45_gated_we),
+ .wd (mio_pad_attr_45_drive_strength_45_wd),
+ .d (hw2reg.mio_pad_attr[45].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_45_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[45].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_45_drive_strength_45_qs)
+ );
+ assign reg2hw.mio_pad_attr[45].drive_strength.qe = mio_pad_attr_45_qe;
+
+
+ // Subregister 46 of Multireg mio_pad_attr
+ // R[mio_pad_attr_46]: V(True)
+ logic mio_pad_attr_46_qe;
+ logic [8:0] mio_pad_attr_46_flds_we;
+ assign mio_pad_attr_46_qe = &mio_pad_attr_46_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_46_gated_we;
+ assign mio_pad_attr_46_gated_we = mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs;
+ // F[invert_46]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_invert_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_invert_46_wd),
+ .d (hw2reg.mio_pad_attr[46].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[46].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_46_invert_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].invert.qe = mio_pad_attr_46_qe;
+
+ // F[virtual_od_en_46]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_virtual_od_en_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_virtual_od_en_46_wd),
+ .d (hw2reg.mio_pad_attr[46].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[46].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_46_virtual_od_en_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].virtual_od_en.qe = mio_pad_attr_46_qe;
+
+ // F[pull_en_46]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_pull_en_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_pull_en_46_wd),
+ .d (hw2reg.mio_pad_attr[46].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[46].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_46_pull_en_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].pull_en.qe = mio_pad_attr_46_qe;
+
+ // F[pull_select_46]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_pull_select_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_pull_select_46_wd),
+ .d (hw2reg.mio_pad_attr[46].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[46].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_46_pull_select_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].pull_select.qe = mio_pad_attr_46_qe;
+
+ // F[keeper_en_46]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_keeper_en_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_keeper_en_46_wd),
+ .d (hw2reg.mio_pad_attr[46].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[46].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_46_keeper_en_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].keeper_en.qe = mio_pad_attr_46_qe;
+
+ // F[schmitt_en_46]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_schmitt_en_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_schmitt_en_46_wd),
+ .d (hw2reg.mio_pad_attr[46].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[46].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_46_schmitt_en_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].schmitt_en.qe = mio_pad_attr_46_qe;
+
+ // F[od_en_46]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_46_od_en_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_od_en_46_wd),
+ .d (hw2reg.mio_pad_attr[46].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[46].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_46_od_en_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].od_en.qe = mio_pad_attr_46_qe;
+
+ // F[slew_rate_46]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_46_slew_rate_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_slew_rate_46_wd),
+ .d (hw2reg.mio_pad_attr[46].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[46].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_46_slew_rate_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].slew_rate.qe = mio_pad_attr_46_qe;
+
+ // F[drive_strength_46]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_46_drive_strength_46 (
+ .re (mio_pad_attr_46_re),
+ .we (mio_pad_attr_46_gated_we),
+ .wd (mio_pad_attr_46_drive_strength_46_wd),
+ .d (hw2reg.mio_pad_attr[46].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_46_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[46].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_46_drive_strength_46_qs)
+ );
+ assign reg2hw.mio_pad_attr[46].drive_strength.qe = mio_pad_attr_46_qe;
+
+
+ // Subregister 47 of Multireg mio_pad_attr
+ // R[mio_pad_attr_47]: V(True)
+ logic mio_pad_attr_47_qe;
+ logic [8:0] mio_pad_attr_47_flds_we;
+ assign mio_pad_attr_47_qe = &mio_pad_attr_47_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_47_gated_we;
+ assign mio_pad_attr_47_gated_we = mio_pad_attr_47_we & mio_pad_attr_regwen_47_qs;
+ // F[invert_47]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_invert_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_invert_47_wd),
+ .d (hw2reg.mio_pad_attr[47].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[47].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_47_invert_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].invert.qe = mio_pad_attr_47_qe;
+
+ // F[virtual_od_en_47]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_virtual_od_en_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_virtual_od_en_47_wd),
+ .d (hw2reg.mio_pad_attr[47].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[47].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_47_virtual_od_en_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].virtual_od_en.qe = mio_pad_attr_47_qe;
+
+ // F[pull_en_47]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_pull_en_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_pull_en_47_wd),
+ .d (hw2reg.mio_pad_attr[47].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[47].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_47_pull_en_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].pull_en.qe = mio_pad_attr_47_qe;
+
+ // F[pull_select_47]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_pull_select_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_pull_select_47_wd),
+ .d (hw2reg.mio_pad_attr[47].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[47].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_47_pull_select_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].pull_select.qe = mio_pad_attr_47_qe;
+
+ // F[keeper_en_47]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_keeper_en_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_keeper_en_47_wd),
+ .d (hw2reg.mio_pad_attr[47].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[47].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_47_keeper_en_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].keeper_en.qe = mio_pad_attr_47_qe;
+
+ // F[schmitt_en_47]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_schmitt_en_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_schmitt_en_47_wd),
+ .d (hw2reg.mio_pad_attr[47].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[47].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_47_schmitt_en_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].schmitt_en.qe = mio_pad_attr_47_qe;
+
+ // F[od_en_47]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_47_od_en_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_od_en_47_wd),
+ .d (hw2reg.mio_pad_attr[47].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[47].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_47_od_en_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].od_en.qe = mio_pad_attr_47_qe;
+
+ // F[slew_rate_47]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_47_slew_rate_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_slew_rate_47_wd),
+ .d (hw2reg.mio_pad_attr[47].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[47].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_47_slew_rate_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].slew_rate.qe = mio_pad_attr_47_qe;
+
+ // F[drive_strength_47]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_47_drive_strength_47 (
+ .re (mio_pad_attr_47_re),
+ .we (mio_pad_attr_47_gated_we),
+ .wd (mio_pad_attr_47_drive_strength_47_wd),
+ .d (hw2reg.mio_pad_attr[47].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_47_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[47].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_47_drive_strength_47_qs)
+ );
+ assign reg2hw.mio_pad_attr[47].drive_strength.qe = mio_pad_attr_47_qe;
+
+
+ // Subregister 48 of Multireg mio_pad_attr
+ // R[mio_pad_attr_48]: V(True)
+ logic mio_pad_attr_48_qe;
+ logic [8:0] mio_pad_attr_48_flds_we;
+ assign mio_pad_attr_48_qe = &mio_pad_attr_48_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_48_gated_we;
+ assign mio_pad_attr_48_gated_we = mio_pad_attr_48_we & mio_pad_attr_regwen_48_qs;
+ // F[invert_48]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_invert_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_invert_48_wd),
+ .d (hw2reg.mio_pad_attr[48].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[48].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_48_invert_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].invert.qe = mio_pad_attr_48_qe;
+
+ // F[virtual_od_en_48]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_virtual_od_en_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_virtual_od_en_48_wd),
+ .d (hw2reg.mio_pad_attr[48].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[48].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_48_virtual_od_en_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].virtual_od_en.qe = mio_pad_attr_48_qe;
+
+ // F[pull_en_48]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_pull_en_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_pull_en_48_wd),
+ .d (hw2reg.mio_pad_attr[48].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[48].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_48_pull_en_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].pull_en.qe = mio_pad_attr_48_qe;
+
+ // F[pull_select_48]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_pull_select_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_pull_select_48_wd),
+ .d (hw2reg.mio_pad_attr[48].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[48].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_48_pull_select_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].pull_select.qe = mio_pad_attr_48_qe;
+
+ // F[keeper_en_48]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_keeper_en_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_keeper_en_48_wd),
+ .d (hw2reg.mio_pad_attr[48].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[48].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_48_keeper_en_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].keeper_en.qe = mio_pad_attr_48_qe;
+
+ // F[schmitt_en_48]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_schmitt_en_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_schmitt_en_48_wd),
+ .d (hw2reg.mio_pad_attr[48].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[48].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_48_schmitt_en_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].schmitt_en.qe = mio_pad_attr_48_qe;
+
+ // F[od_en_48]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_48_od_en_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_od_en_48_wd),
+ .d (hw2reg.mio_pad_attr[48].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[48].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_48_od_en_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].od_en.qe = mio_pad_attr_48_qe;
+
+ // F[slew_rate_48]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_48_slew_rate_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_slew_rate_48_wd),
+ .d (hw2reg.mio_pad_attr[48].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[48].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_48_slew_rate_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].slew_rate.qe = mio_pad_attr_48_qe;
+
+ // F[drive_strength_48]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_48_drive_strength_48 (
+ .re (mio_pad_attr_48_re),
+ .we (mio_pad_attr_48_gated_we),
+ .wd (mio_pad_attr_48_drive_strength_48_wd),
+ .d (hw2reg.mio_pad_attr[48].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_48_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[48].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_48_drive_strength_48_qs)
+ );
+ assign reg2hw.mio_pad_attr[48].drive_strength.qe = mio_pad_attr_48_qe;
+
+
+ // Subregister 49 of Multireg mio_pad_attr
+ // R[mio_pad_attr_49]: V(True)
+ logic mio_pad_attr_49_qe;
+ logic [8:0] mio_pad_attr_49_flds_we;
+ assign mio_pad_attr_49_qe = &mio_pad_attr_49_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_49_gated_we;
+ assign mio_pad_attr_49_gated_we = mio_pad_attr_49_we & mio_pad_attr_regwen_49_qs;
+ // F[invert_49]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_invert_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_invert_49_wd),
+ .d (hw2reg.mio_pad_attr[49].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[49].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_49_invert_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].invert.qe = mio_pad_attr_49_qe;
+
+ // F[virtual_od_en_49]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_virtual_od_en_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_virtual_od_en_49_wd),
+ .d (hw2reg.mio_pad_attr[49].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[49].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_49_virtual_od_en_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].virtual_od_en.qe = mio_pad_attr_49_qe;
+
+ // F[pull_en_49]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_pull_en_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_pull_en_49_wd),
+ .d (hw2reg.mio_pad_attr[49].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[49].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_49_pull_en_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].pull_en.qe = mio_pad_attr_49_qe;
+
+ // F[pull_select_49]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_pull_select_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_pull_select_49_wd),
+ .d (hw2reg.mio_pad_attr[49].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[49].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_49_pull_select_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].pull_select.qe = mio_pad_attr_49_qe;
+
+ // F[keeper_en_49]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_keeper_en_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_keeper_en_49_wd),
+ .d (hw2reg.mio_pad_attr[49].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[49].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_49_keeper_en_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].keeper_en.qe = mio_pad_attr_49_qe;
+
+ // F[schmitt_en_49]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_schmitt_en_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_schmitt_en_49_wd),
+ .d (hw2reg.mio_pad_attr[49].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[49].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_49_schmitt_en_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].schmitt_en.qe = mio_pad_attr_49_qe;
+
+ // F[od_en_49]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_49_od_en_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_od_en_49_wd),
+ .d (hw2reg.mio_pad_attr[49].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[49].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_49_od_en_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].od_en.qe = mio_pad_attr_49_qe;
+
+ // F[slew_rate_49]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_49_slew_rate_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_slew_rate_49_wd),
+ .d (hw2reg.mio_pad_attr[49].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[49].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_49_slew_rate_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].slew_rate.qe = mio_pad_attr_49_qe;
+
+ // F[drive_strength_49]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_49_drive_strength_49 (
+ .re (mio_pad_attr_49_re),
+ .we (mio_pad_attr_49_gated_we),
+ .wd (mio_pad_attr_49_drive_strength_49_wd),
+ .d (hw2reg.mio_pad_attr[49].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_49_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[49].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_49_drive_strength_49_qs)
+ );
+ assign reg2hw.mio_pad_attr[49].drive_strength.qe = mio_pad_attr_49_qe;
+
+
+ // Subregister 50 of Multireg mio_pad_attr
+ // R[mio_pad_attr_50]: V(True)
+ logic mio_pad_attr_50_qe;
+ logic [8:0] mio_pad_attr_50_flds_we;
+ assign mio_pad_attr_50_qe = &mio_pad_attr_50_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_50_gated_we;
+ assign mio_pad_attr_50_gated_we = mio_pad_attr_50_we & mio_pad_attr_regwen_50_qs;
+ // F[invert_50]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_invert_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_invert_50_wd),
+ .d (hw2reg.mio_pad_attr[50].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[50].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_50_invert_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].invert.qe = mio_pad_attr_50_qe;
+
+ // F[virtual_od_en_50]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_virtual_od_en_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_virtual_od_en_50_wd),
+ .d (hw2reg.mio_pad_attr[50].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[50].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_50_virtual_od_en_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].virtual_od_en.qe = mio_pad_attr_50_qe;
+
+ // F[pull_en_50]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_pull_en_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_pull_en_50_wd),
+ .d (hw2reg.mio_pad_attr[50].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[50].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_50_pull_en_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].pull_en.qe = mio_pad_attr_50_qe;
+
+ // F[pull_select_50]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_pull_select_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_pull_select_50_wd),
+ .d (hw2reg.mio_pad_attr[50].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[50].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_50_pull_select_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].pull_select.qe = mio_pad_attr_50_qe;
+
+ // F[keeper_en_50]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_keeper_en_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_keeper_en_50_wd),
+ .d (hw2reg.mio_pad_attr[50].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[50].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_50_keeper_en_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].keeper_en.qe = mio_pad_attr_50_qe;
+
+ // F[schmitt_en_50]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_schmitt_en_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_schmitt_en_50_wd),
+ .d (hw2reg.mio_pad_attr[50].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[50].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_50_schmitt_en_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].schmitt_en.qe = mio_pad_attr_50_qe;
+
+ // F[od_en_50]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_50_od_en_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_od_en_50_wd),
+ .d (hw2reg.mio_pad_attr[50].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[50].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_50_od_en_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].od_en.qe = mio_pad_attr_50_qe;
+
+ // F[slew_rate_50]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_50_slew_rate_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_slew_rate_50_wd),
+ .d (hw2reg.mio_pad_attr[50].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[50].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_50_slew_rate_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].slew_rate.qe = mio_pad_attr_50_qe;
+
+ // F[drive_strength_50]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_50_drive_strength_50 (
+ .re (mio_pad_attr_50_re),
+ .we (mio_pad_attr_50_gated_we),
+ .wd (mio_pad_attr_50_drive_strength_50_wd),
+ .d (hw2reg.mio_pad_attr[50].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_50_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[50].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_50_drive_strength_50_qs)
+ );
+ assign reg2hw.mio_pad_attr[50].drive_strength.qe = mio_pad_attr_50_qe;
+
+
+ // Subregister 51 of Multireg mio_pad_attr
+ // R[mio_pad_attr_51]: V(True)
+ logic mio_pad_attr_51_qe;
+ logic [8:0] mio_pad_attr_51_flds_we;
+ assign mio_pad_attr_51_qe = &mio_pad_attr_51_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_51_gated_we;
+ assign mio_pad_attr_51_gated_we = mio_pad_attr_51_we & mio_pad_attr_regwen_51_qs;
+ // F[invert_51]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_invert_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_invert_51_wd),
+ .d (hw2reg.mio_pad_attr[51].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[51].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_51_invert_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].invert.qe = mio_pad_attr_51_qe;
+
+ // F[virtual_od_en_51]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_virtual_od_en_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_virtual_od_en_51_wd),
+ .d (hw2reg.mio_pad_attr[51].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[51].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_51_virtual_od_en_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].virtual_od_en.qe = mio_pad_attr_51_qe;
+
+ // F[pull_en_51]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_pull_en_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_pull_en_51_wd),
+ .d (hw2reg.mio_pad_attr[51].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[51].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_51_pull_en_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].pull_en.qe = mio_pad_attr_51_qe;
+
+ // F[pull_select_51]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_pull_select_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_pull_select_51_wd),
+ .d (hw2reg.mio_pad_attr[51].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[51].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_51_pull_select_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].pull_select.qe = mio_pad_attr_51_qe;
+
+ // F[keeper_en_51]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_keeper_en_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_keeper_en_51_wd),
+ .d (hw2reg.mio_pad_attr[51].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[51].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_51_keeper_en_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].keeper_en.qe = mio_pad_attr_51_qe;
+
+ // F[schmitt_en_51]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_schmitt_en_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_schmitt_en_51_wd),
+ .d (hw2reg.mio_pad_attr[51].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[51].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_51_schmitt_en_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].schmitt_en.qe = mio_pad_attr_51_qe;
+
+ // F[od_en_51]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_51_od_en_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_od_en_51_wd),
+ .d (hw2reg.mio_pad_attr[51].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[51].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_51_od_en_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].od_en.qe = mio_pad_attr_51_qe;
+
+ // F[slew_rate_51]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_51_slew_rate_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_slew_rate_51_wd),
+ .d (hw2reg.mio_pad_attr[51].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[51].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_51_slew_rate_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].slew_rate.qe = mio_pad_attr_51_qe;
+
+ // F[drive_strength_51]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_51_drive_strength_51 (
+ .re (mio_pad_attr_51_re),
+ .we (mio_pad_attr_51_gated_we),
+ .wd (mio_pad_attr_51_drive_strength_51_wd),
+ .d (hw2reg.mio_pad_attr[51].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_51_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[51].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_51_drive_strength_51_qs)
+ );
+ assign reg2hw.mio_pad_attr[51].drive_strength.qe = mio_pad_attr_51_qe;
+
+
+ // Subregister 52 of Multireg mio_pad_attr
+ // R[mio_pad_attr_52]: V(True)
+ logic mio_pad_attr_52_qe;
+ logic [8:0] mio_pad_attr_52_flds_we;
+ assign mio_pad_attr_52_qe = &mio_pad_attr_52_flds_we;
+ // Create REGWEN-gated WE signal
+ logic mio_pad_attr_52_gated_we;
+ assign mio_pad_attr_52_gated_we = mio_pad_attr_52_we & mio_pad_attr_regwen_52_qs;
+ // F[invert_52]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_invert_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_invert_52_wd),
+ .d (hw2reg.mio_pad_attr[52].invert.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[0]),
+ .q (reg2hw.mio_pad_attr[52].invert.q),
+ .ds (),
+ .qs (mio_pad_attr_52_invert_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].invert.qe = mio_pad_attr_52_qe;
+
+ // F[virtual_od_en_52]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_virtual_od_en_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_virtual_od_en_52_wd),
+ .d (hw2reg.mio_pad_attr[52].virtual_od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[1]),
+ .q (reg2hw.mio_pad_attr[52].virtual_od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_52_virtual_od_en_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].virtual_od_en.qe = mio_pad_attr_52_qe;
+
+ // F[pull_en_52]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_pull_en_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_pull_en_52_wd),
+ .d (hw2reg.mio_pad_attr[52].pull_en.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[2]),
+ .q (reg2hw.mio_pad_attr[52].pull_en.q),
+ .ds (),
+ .qs (mio_pad_attr_52_pull_en_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].pull_en.qe = mio_pad_attr_52_qe;
+
+ // F[pull_select_52]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_pull_select_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_pull_select_52_wd),
+ .d (hw2reg.mio_pad_attr[52].pull_select.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[3]),
+ .q (reg2hw.mio_pad_attr[52].pull_select.q),
+ .ds (),
+ .qs (mio_pad_attr_52_pull_select_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].pull_select.qe = mio_pad_attr_52_qe;
+
+ // F[keeper_en_52]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_keeper_en_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_keeper_en_52_wd),
+ .d (hw2reg.mio_pad_attr[52].keeper_en.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[4]),
+ .q (reg2hw.mio_pad_attr[52].keeper_en.q),
+ .ds (),
+ .qs (mio_pad_attr_52_keeper_en_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].keeper_en.qe = mio_pad_attr_52_qe;
+
+ // F[schmitt_en_52]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_schmitt_en_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_schmitt_en_52_wd),
+ .d (hw2reg.mio_pad_attr[52].schmitt_en.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[5]),
+ .q (reg2hw.mio_pad_attr[52].schmitt_en.q),
+ .ds (),
+ .qs (mio_pad_attr_52_schmitt_en_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].schmitt_en.qe = mio_pad_attr_52_qe;
+
+ // F[od_en_52]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_mio_pad_attr_52_od_en_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_od_en_52_wd),
+ .d (hw2reg.mio_pad_attr[52].od_en.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[6]),
+ .q (reg2hw.mio_pad_attr[52].od_en.q),
+ .ds (),
+ .qs (mio_pad_attr_52_od_en_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].od_en.qe = mio_pad_attr_52_qe;
+
+ // F[slew_rate_52]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_mio_pad_attr_52_slew_rate_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_slew_rate_52_wd),
+ .d (hw2reg.mio_pad_attr[52].slew_rate.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[7]),
+ .q (reg2hw.mio_pad_attr[52].slew_rate.q),
+ .ds (),
+ .qs (mio_pad_attr_52_slew_rate_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].slew_rate.qe = mio_pad_attr_52_qe;
+
+ // F[drive_strength_52]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_mio_pad_attr_52_drive_strength_52 (
+ .re (mio_pad_attr_52_re),
+ .we (mio_pad_attr_52_gated_we),
+ .wd (mio_pad_attr_52_drive_strength_52_wd),
+ .d (hw2reg.mio_pad_attr[52].drive_strength.d),
+ .qre (),
+ .qe (mio_pad_attr_52_flds_we[8]),
+ .q (reg2hw.mio_pad_attr[52].drive_strength.q),
+ .ds (),
+ .qs (mio_pad_attr_52_drive_strength_52_qs)
+ );
+ assign reg2hw.mio_pad_attr[52].drive_strength.qe = mio_pad_attr_52_qe;
+
+
+ // Subregister 0 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_0_we),
+ .wd (dio_pad_attr_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_1_we),
+ .wd (dio_pad_attr_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_2_we),
+ .wd (dio_pad_attr_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_3_we),
+ .wd (dio_pad_attr_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_4_we),
+ .wd (dio_pad_attr_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_5_we),
+ .wd (dio_pad_attr_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_6_we),
+ .wd (dio_pad_attr_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_7_we),
+ .wd (dio_pad_attr_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_8_we),
+ .wd (dio_pad_attr_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_9_we),
+ .wd (dio_pad_attr_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_10_we),
+ .wd (dio_pad_attr_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_11_we),
+ .wd (dio_pad_attr_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_12_we),
+ .wd (dio_pad_attr_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_13_we),
+ .wd (dio_pad_attr_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_14_we),
+ .wd (dio_pad_attr_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg dio_pad_attr_regwen
+ // R[dio_pad_attr_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_attr_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_attr_regwen_15_we),
+ .wd (dio_pad_attr_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_attr_regwen_15_qs)
+ );
+
+
+ // Subregister 0 of Multireg dio_pad_attr
+ // R[dio_pad_attr_0]: V(True)
+ logic dio_pad_attr_0_qe;
+ logic [8:0] dio_pad_attr_0_flds_we;
+ assign dio_pad_attr_0_qe = &dio_pad_attr_0_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_0_gated_we;
+ assign dio_pad_attr_0_gated_we = dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs;
+ // F[invert_0]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_invert_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_invert_0_wd),
+ .d (hw2reg.dio_pad_attr[0].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[0].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_0_invert_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].invert.qe = dio_pad_attr_0_qe;
+
+ // F[virtual_od_en_0]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_virtual_od_en_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_virtual_od_en_0_wd),
+ .d (hw2reg.dio_pad_attr[0].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[0].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_0_virtual_od_en_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].virtual_od_en.qe = dio_pad_attr_0_qe;
+
+ // F[pull_en_0]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_pull_en_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_pull_en_0_wd),
+ .d (hw2reg.dio_pad_attr[0].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[0].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_0_pull_en_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].pull_en.qe = dio_pad_attr_0_qe;
+
+ // F[pull_select_0]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_pull_select_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_pull_select_0_wd),
+ .d (hw2reg.dio_pad_attr[0].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[0].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_0_pull_select_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].pull_select.qe = dio_pad_attr_0_qe;
+
+ // F[keeper_en_0]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_keeper_en_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_keeper_en_0_wd),
+ .d (hw2reg.dio_pad_attr[0].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[0].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_0_keeper_en_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].keeper_en.qe = dio_pad_attr_0_qe;
+
+ // F[schmitt_en_0]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_schmitt_en_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_schmitt_en_0_wd),
+ .d (hw2reg.dio_pad_attr[0].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[0].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_0_schmitt_en_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].schmitt_en.qe = dio_pad_attr_0_qe;
+
+ // F[od_en_0]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_0_od_en_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_od_en_0_wd),
+ .d (hw2reg.dio_pad_attr[0].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[0].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_0_od_en_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].od_en.qe = dio_pad_attr_0_qe;
+
+ // F[slew_rate_0]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_0_slew_rate_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_slew_rate_0_wd),
+ .d (hw2reg.dio_pad_attr[0].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[0].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_0_slew_rate_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].slew_rate.qe = dio_pad_attr_0_qe;
+
+ // F[drive_strength_0]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_0_drive_strength_0 (
+ .re (dio_pad_attr_0_re),
+ .we (dio_pad_attr_0_gated_we),
+ .wd (dio_pad_attr_0_drive_strength_0_wd),
+ .d (hw2reg.dio_pad_attr[0].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_0_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[0].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_0_drive_strength_0_qs)
+ );
+ assign reg2hw.dio_pad_attr[0].drive_strength.qe = dio_pad_attr_0_qe;
+
+
+ // Subregister 1 of Multireg dio_pad_attr
+ // R[dio_pad_attr_1]: V(True)
+ logic dio_pad_attr_1_qe;
+ logic [8:0] dio_pad_attr_1_flds_we;
+ assign dio_pad_attr_1_qe = &dio_pad_attr_1_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_1_gated_we;
+ assign dio_pad_attr_1_gated_we = dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs;
+ // F[invert_1]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_invert_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_invert_1_wd),
+ .d (hw2reg.dio_pad_attr[1].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[1].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_1_invert_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].invert.qe = dio_pad_attr_1_qe;
+
+ // F[virtual_od_en_1]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_virtual_od_en_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_virtual_od_en_1_wd),
+ .d (hw2reg.dio_pad_attr[1].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[1].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_1_virtual_od_en_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].virtual_od_en.qe = dio_pad_attr_1_qe;
+
+ // F[pull_en_1]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_pull_en_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_pull_en_1_wd),
+ .d (hw2reg.dio_pad_attr[1].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[1].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_1_pull_en_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].pull_en.qe = dio_pad_attr_1_qe;
+
+ // F[pull_select_1]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_pull_select_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_pull_select_1_wd),
+ .d (hw2reg.dio_pad_attr[1].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[1].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_1_pull_select_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].pull_select.qe = dio_pad_attr_1_qe;
+
+ // F[keeper_en_1]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_keeper_en_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_keeper_en_1_wd),
+ .d (hw2reg.dio_pad_attr[1].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[1].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_1_keeper_en_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].keeper_en.qe = dio_pad_attr_1_qe;
+
+ // F[schmitt_en_1]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_schmitt_en_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_schmitt_en_1_wd),
+ .d (hw2reg.dio_pad_attr[1].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[1].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_1_schmitt_en_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].schmitt_en.qe = dio_pad_attr_1_qe;
+
+ // F[od_en_1]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_1_od_en_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_od_en_1_wd),
+ .d (hw2reg.dio_pad_attr[1].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[1].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_1_od_en_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].od_en.qe = dio_pad_attr_1_qe;
+
+ // F[slew_rate_1]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_1_slew_rate_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_slew_rate_1_wd),
+ .d (hw2reg.dio_pad_attr[1].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[1].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_1_slew_rate_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].slew_rate.qe = dio_pad_attr_1_qe;
+
+ // F[drive_strength_1]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_1_drive_strength_1 (
+ .re (dio_pad_attr_1_re),
+ .we (dio_pad_attr_1_gated_we),
+ .wd (dio_pad_attr_1_drive_strength_1_wd),
+ .d (hw2reg.dio_pad_attr[1].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_1_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[1].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_1_drive_strength_1_qs)
+ );
+ assign reg2hw.dio_pad_attr[1].drive_strength.qe = dio_pad_attr_1_qe;
+
+
+ // Subregister 2 of Multireg dio_pad_attr
+ // R[dio_pad_attr_2]: V(True)
+ logic dio_pad_attr_2_qe;
+ logic [8:0] dio_pad_attr_2_flds_we;
+ assign dio_pad_attr_2_qe = &dio_pad_attr_2_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_2_gated_we;
+ assign dio_pad_attr_2_gated_we = dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs;
+ // F[invert_2]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_invert_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_invert_2_wd),
+ .d (hw2reg.dio_pad_attr[2].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[2].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_2_invert_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].invert.qe = dio_pad_attr_2_qe;
+
+ // F[virtual_od_en_2]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_virtual_od_en_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_virtual_od_en_2_wd),
+ .d (hw2reg.dio_pad_attr[2].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[2].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_2_virtual_od_en_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].virtual_od_en.qe = dio_pad_attr_2_qe;
+
+ // F[pull_en_2]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_pull_en_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_pull_en_2_wd),
+ .d (hw2reg.dio_pad_attr[2].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[2].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_2_pull_en_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].pull_en.qe = dio_pad_attr_2_qe;
+
+ // F[pull_select_2]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_pull_select_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_pull_select_2_wd),
+ .d (hw2reg.dio_pad_attr[2].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[2].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_2_pull_select_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].pull_select.qe = dio_pad_attr_2_qe;
+
+ // F[keeper_en_2]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_keeper_en_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_keeper_en_2_wd),
+ .d (hw2reg.dio_pad_attr[2].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[2].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_2_keeper_en_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].keeper_en.qe = dio_pad_attr_2_qe;
+
+ // F[schmitt_en_2]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_schmitt_en_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_schmitt_en_2_wd),
+ .d (hw2reg.dio_pad_attr[2].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[2].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_2_schmitt_en_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].schmitt_en.qe = dio_pad_attr_2_qe;
+
+ // F[od_en_2]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_2_od_en_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_od_en_2_wd),
+ .d (hw2reg.dio_pad_attr[2].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[2].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_2_od_en_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].od_en.qe = dio_pad_attr_2_qe;
+
+ // F[slew_rate_2]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_2_slew_rate_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_slew_rate_2_wd),
+ .d (hw2reg.dio_pad_attr[2].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[2].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_2_slew_rate_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].slew_rate.qe = dio_pad_attr_2_qe;
+
+ // F[drive_strength_2]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_2_drive_strength_2 (
+ .re (dio_pad_attr_2_re),
+ .we (dio_pad_attr_2_gated_we),
+ .wd (dio_pad_attr_2_drive_strength_2_wd),
+ .d (hw2reg.dio_pad_attr[2].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_2_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[2].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_2_drive_strength_2_qs)
+ );
+ assign reg2hw.dio_pad_attr[2].drive_strength.qe = dio_pad_attr_2_qe;
+
+
+ // Subregister 3 of Multireg dio_pad_attr
+ // R[dio_pad_attr_3]: V(True)
+ logic dio_pad_attr_3_qe;
+ logic [8:0] dio_pad_attr_3_flds_we;
+ assign dio_pad_attr_3_qe = &dio_pad_attr_3_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_3_gated_we;
+ assign dio_pad_attr_3_gated_we = dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs;
+ // F[invert_3]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_invert_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_invert_3_wd),
+ .d (hw2reg.dio_pad_attr[3].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[3].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_3_invert_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].invert.qe = dio_pad_attr_3_qe;
+
+ // F[virtual_od_en_3]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_virtual_od_en_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_virtual_od_en_3_wd),
+ .d (hw2reg.dio_pad_attr[3].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[3].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_3_virtual_od_en_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].virtual_od_en.qe = dio_pad_attr_3_qe;
+
+ // F[pull_en_3]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_pull_en_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_pull_en_3_wd),
+ .d (hw2reg.dio_pad_attr[3].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[3].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_3_pull_en_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].pull_en.qe = dio_pad_attr_3_qe;
+
+ // F[pull_select_3]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_pull_select_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_pull_select_3_wd),
+ .d (hw2reg.dio_pad_attr[3].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[3].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_3_pull_select_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].pull_select.qe = dio_pad_attr_3_qe;
+
+ // F[keeper_en_3]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_keeper_en_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_keeper_en_3_wd),
+ .d (hw2reg.dio_pad_attr[3].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[3].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_3_keeper_en_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].keeper_en.qe = dio_pad_attr_3_qe;
+
+ // F[schmitt_en_3]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_schmitt_en_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_schmitt_en_3_wd),
+ .d (hw2reg.dio_pad_attr[3].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[3].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_3_schmitt_en_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].schmitt_en.qe = dio_pad_attr_3_qe;
+
+ // F[od_en_3]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_3_od_en_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_od_en_3_wd),
+ .d (hw2reg.dio_pad_attr[3].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[3].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_3_od_en_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].od_en.qe = dio_pad_attr_3_qe;
+
+ // F[slew_rate_3]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_3_slew_rate_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_slew_rate_3_wd),
+ .d (hw2reg.dio_pad_attr[3].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[3].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_3_slew_rate_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].slew_rate.qe = dio_pad_attr_3_qe;
+
+ // F[drive_strength_3]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_3_drive_strength_3 (
+ .re (dio_pad_attr_3_re),
+ .we (dio_pad_attr_3_gated_we),
+ .wd (dio_pad_attr_3_drive_strength_3_wd),
+ .d (hw2reg.dio_pad_attr[3].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_3_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[3].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_3_drive_strength_3_qs)
+ );
+ assign reg2hw.dio_pad_attr[3].drive_strength.qe = dio_pad_attr_3_qe;
+
+
+ // Subregister 4 of Multireg dio_pad_attr
+ // R[dio_pad_attr_4]: V(True)
+ logic dio_pad_attr_4_qe;
+ logic [8:0] dio_pad_attr_4_flds_we;
+ assign dio_pad_attr_4_qe = &dio_pad_attr_4_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_4_gated_we;
+ assign dio_pad_attr_4_gated_we = dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs;
+ // F[invert_4]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_invert_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_invert_4_wd),
+ .d (hw2reg.dio_pad_attr[4].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[4].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_4_invert_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].invert.qe = dio_pad_attr_4_qe;
+
+ // F[virtual_od_en_4]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_virtual_od_en_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_virtual_od_en_4_wd),
+ .d (hw2reg.dio_pad_attr[4].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[4].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_4_virtual_od_en_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].virtual_od_en.qe = dio_pad_attr_4_qe;
+
+ // F[pull_en_4]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_pull_en_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_pull_en_4_wd),
+ .d (hw2reg.dio_pad_attr[4].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[4].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_4_pull_en_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].pull_en.qe = dio_pad_attr_4_qe;
+
+ // F[pull_select_4]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_pull_select_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_pull_select_4_wd),
+ .d (hw2reg.dio_pad_attr[4].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[4].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_4_pull_select_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].pull_select.qe = dio_pad_attr_4_qe;
+
+ // F[keeper_en_4]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_keeper_en_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_keeper_en_4_wd),
+ .d (hw2reg.dio_pad_attr[4].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[4].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_4_keeper_en_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].keeper_en.qe = dio_pad_attr_4_qe;
+
+ // F[schmitt_en_4]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_schmitt_en_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_schmitt_en_4_wd),
+ .d (hw2reg.dio_pad_attr[4].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[4].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_4_schmitt_en_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].schmitt_en.qe = dio_pad_attr_4_qe;
+
+ // F[od_en_4]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_4_od_en_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_od_en_4_wd),
+ .d (hw2reg.dio_pad_attr[4].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[4].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_4_od_en_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].od_en.qe = dio_pad_attr_4_qe;
+
+ // F[slew_rate_4]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_4_slew_rate_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_slew_rate_4_wd),
+ .d (hw2reg.dio_pad_attr[4].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[4].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_4_slew_rate_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].slew_rate.qe = dio_pad_attr_4_qe;
+
+ // F[drive_strength_4]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_4_drive_strength_4 (
+ .re (dio_pad_attr_4_re),
+ .we (dio_pad_attr_4_gated_we),
+ .wd (dio_pad_attr_4_drive_strength_4_wd),
+ .d (hw2reg.dio_pad_attr[4].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_4_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[4].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_4_drive_strength_4_qs)
+ );
+ assign reg2hw.dio_pad_attr[4].drive_strength.qe = dio_pad_attr_4_qe;
+
+
+ // Subregister 5 of Multireg dio_pad_attr
+ // R[dio_pad_attr_5]: V(True)
+ logic dio_pad_attr_5_qe;
+ logic [8:0] dio_pad_attr_5_flds_we;
+ assign dio_pad_attr_5_qe = &dio_pad_attr_5_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_5_gated_we;
+ assign dio_pad_attr_5_gated_we = dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs;
+ // F[invert_5]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_invert_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_invert_5_wd),
+ .d (hw2reg.dio_pad_attr[5].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[5].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_5_invert_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].invert.qe = dio_pad_attr_5_qe;
+
+ // F[virtual_od_en_5]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_virtual_od_en_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_virtual_od_en_5_wd),
+ .d (hw2reg.dio_pad_attr[5].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[5].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_5_virtual_od_en_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].virtual_od_en.qe = dio_pad_attr_5_qe;
+
+ // F[pull_en_5]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_pull_en_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_pull_en_5_wd),
+ .d (hw2reg.dio_pad_attr[5].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[5].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_5_pull_en_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].pull_en.qe = dio_pad_attr_5_qe;
+
+ // F[pull_select_5]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_pull_select_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_pull_select_5_wd),
+ .d (hw2reg.dio_pad_attr[5].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[5].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_5_pull_select_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].pull_select.qe = dio_pad_attr_5_qe;
+
+ // F[keeper_en_5]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_keeper_en_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_keeper_en_5_wd),
+ .d (hw2reg.dio_pad_attr[5].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[5].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_5_keeper_en_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].keeper_en.qe = dio_pad_attr_5_qe;
+
+ // F[schmitt_en_5]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_schmitt_en_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_schmitt_en_5_wd),
+ .d (hw2reg.dio_pad_attr[5].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[5].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_5_schmitt_en_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].schmitt_en.qe = dio_pad_attr_5_qe;
+
+ // F[od_en_5]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_5_od_en_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_od_en_5_wd),
+ .d (hw2reg.dio_pad_attr[5].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[5].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_5_od_en_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].od_en.qe = dio_pad_attr_5_qe;
+
+ // F[slew_rate_5]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_5_slew_rate_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_slew_rate_5_wd),
+ .d (hw2reg.dio_pad_attr[5].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[5].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_5_slew_rate_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].slew_rate.qe = dio_pad_attr_5_qe;
+
+ // F[drive_strength_5]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_5_drive_strength_5 (
+ .re (dio_pad_attr_5_re),
+ .we (dio_pad_attr_5_gated_we),
+ .wd (dio_pad_attr_5_drive_strength_5_wd),
+ .d (hw2reg.dio_pad_attr[5].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_5_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[5].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_5_drive_strength_5_qs)
+ );
+ assign reg2hw.dio_pad_attr[5].drive_strength.qe = dio_pad_attr_5_qe;
+
+
+ // Subregister 6 of Multireg dio_pad_attr
+ // R[dio_pad_attr_6]: V(True)
+ logic dio_pad_attr_6_qe;
+ logic [8:0] dio_pad_attr_6_flds_we;
+ assign dio_pad_attr_6_qe = &dio_pad_attr_6_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_6_gated_we;
+ assign dio_pad_attr_6_gated_we = dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs;
+ // F[invert_6]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_invert_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_invert_6_wd),
+ .d (hw2reg.dio_pad_attr[6].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[6].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_6_invert_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].invert.qe = dio_pad_attr_6_qe;
+
+ // F[virtual_od_en_6]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_virtual_od_en_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_virtual_od_en_6_wd),
+ .d (hw2reg.dio_pad_attr[6].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[6].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_6_virtual_od_en_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].virtual_od_en.qe = dio_pad_attr_6_qe;
+
+ // F[pull_en_6]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_pull_en_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_pull_en_6_wd),
+ .d (hw2reg.dio_pad_attr[6].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[6].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_6_pull_en_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].pull_en.qe = dio_pad_attr_6_qe;
+
+ // F[pull_select_6]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_pull_select_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_pull_select_6_wd),
+ .d (hw2reg.dio_pad_attr[6].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[6].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_6_pull_select_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].pull_select.qe = dio_pad_attr_6_qe;
+
+ // F[keeper_en_6]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_keeper_en_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_keeper_en_6_wd),
+ .d (hw2reg.dio_pad_attr[6].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[6].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_6_keeper_en_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].keeper_en.qe = dio_pad_attr_6_qe;
+
+ // F[schmitt_en_6]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_schmitt_en_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_schmitt_en_6_wd),
+ .d (hw2reg.dio_pad_attr[6].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[6].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_6_schmitt_en_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].schmitt_en.qe = dio_pad_attr_6_qe;
+
+ // F[od_en_6]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_6_od_en_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_od_en_6_wd),
+ .d (hw2reg.dio_pad_attr[6].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[6].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_6_od_en_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].od_en.qe = dio_pad_attr_6_qe;
+
+ // F[slew_rate_6]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_6_slew_rate_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_slew_rate_6_wd),
+ .d (hw2reg.dio_pad_attr[6].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[6].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_6_slew_rate_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].slew_rate.qe = dio_pad_attr_6_qe;
+
+ // F[drive_strength_6]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_6_drive_strength_6 (
+ .re (dio_pad_attr_6_re),
+ .we (dio_pad_attr_6_gated_we),
+ .wd (dio_pad_attr_6_drive_strength_6_wd),
+ .d (hw2reg.dio_pad_attr[6].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_6_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[6].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_6_drive_strength_6_qs)
+ );
+ assign reg2hw.dio_pad_attr[6].drive_strength.qe = dio_pad_attr_6_qe;
+
+
+ // Subregister 7 of Multireg dio_pad_attr
+ // R[dio_pad_attr_7]: V(True)
+ logic dio_pad_attr_7_qe;
+ logic [8:0] dio_pad_attr_7_flds_we;
+ assign dio_pad_attr_7_qe = &dio_pad_attr_7_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_7_gated_we;
+ assign dio_pad_attr_7_gated_we = dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs;
+ // F[invert_7]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_invert_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_invert_7_wd),
+ .d (hw2reg.dio_pad_attr[7].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[7].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_7_invert_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].invert.qe = dio_pad_attr_7_qe;
+
+ // F[virtual_od_en_7]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_virtual_od_en_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_virtual_od_en_7_wd),
+ .d (hw2reg.dio_pad_attr[7].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[7].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_7_virtual_od_en_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].virtual_od_en.qe = dio_pad_attr_7_qe;
+
+ // F[pull_en_7]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_pull_en_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_pull_en_7_wd),
+ .d (hw2reg.dio_pad_attr[7].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[7].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_7_pull_en_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].pull_en.qe = dio_pad_attr_7_qe;
+
+ // F[pull_select_7]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_pull_select_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_pull_select_7_wd),
+ .d (hw2reg.dio_pad_attr[7].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[7].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_7_pull_select_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].pull_select.qe = dio_pad_attr_7_qe;
+
+ // F[keeper_en_7]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_keeper_en_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_keeper_en_7_wd),
+ .d (hw2reg.dio_pad_attr[7].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[7].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_7_keeper_en_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].keeper_en.qe = dio_pad_attr_7_qe;
+
+ // F[schmitt_en_7]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_schmitt_en_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_schmitt_en_7_wd),
+ .d (hw2reg.dio_pad_attr[7].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[7].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_7_schmitt_en_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].schmitt_en.qe = dio_pad_attr_7_qe;
+
+ // F[od_en_7]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_7_od_en_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_od_en_7_wd),
+ .d (hw2reg.dio_pad_attr[7].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[7].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_7_od_en_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].od_en.qe = dio_pad_attr_7_qe;
+
+ // F[slew_rate_7]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_7_slew_rate_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_slew_rate_7_wd),
+ .d (hw2reg.dio_pad_attr[7].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[7].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_7_slew_rate_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].slew_rate.qe = dio_pad_attr_7_qe;
+
+ // F[drive_strength_7]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_7_drive_strength_7 (
+ .re (dio_pad_attr_7_re),
+ .we (dio_pad_attr_7_gated_we),
+ .wd (dio_pad_attr_7_drive_strength_7_wd),
+ .d (hw2reg.dio_pad_attr[7].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_7_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[7].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_7_drive_strength_7_qs)
+ );
+ assign reg2hw.dio_pad_attr[7].drive_strength.qe = dio_pad_attr_7_qe;
+
+
+ // Subregister 8 of Multireg dio_pad_attr
+ // R[dio_pad_attr_8]: V(True)
+ logic dio_pad_attr_8_qe;
+ logic [8:0] dio_pad_attr_8_flds_we;
+ assign dio_pad_attr_8_qe = &dio_pad_attr_8_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_8_gated_we;
+ assign dio_pad_attr_8_gated_we = dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs;
+ // F[invert_8]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_invert_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_invert_8_wd),
+ .d (hw2reg.dio_pad_attr[8].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[8].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_8_invert_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].invert.qe = dio_pad_attr_8_qe;
+
+ // F[virtual_od_en_8]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_virtual_od_en_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_virtual_od_en_8_wd),
+ .d (hw2reg.dio_pad_attr[8].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[8].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_8_virtual_od_en_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].virtual_od_en.qe = dio_pad_attr_8_qe;
+
+ // F[pull_en_8]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_pull_en_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_pull_en_8_wd),
+ .d (hw2reg.dio_pad_attr[8].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[8].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_8_pull_en_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].pull_en.qe = dio_pad_attr_8_qe;
+
+ // F[pull_select_8]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_pull_select_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_pull_select_8_wd),
+ .d (hw2reg.dio_pad_attr[8].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[8].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_8_pull_select_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].pull_select.qe = dio_pad_attr_8_qe;
+
+ // F[keeper_en_8]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_keeper_en_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_keeper_en_8_wd),
+ .d (hw2reg.dio_pad_attr[8].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[8].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_8_keeper_en_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].keeper_en.qe = dio_pad_attr_8_qe;
+
+ // F[schmitt_en_8]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_schmitt_en_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_schmitt_en_8_wd),
+ .d (hw2reg.dio_pad_attr[8].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[8].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_8_schmitt_en_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].schmitt_en.qe = dio_pad_attr_8_qe;
+
+ // F[od_en_8]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_8_od_en_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_od_en_8_wd),
+ .d (hw2reg.dio_pad_attr[8].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[8].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_8_od_en_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].od_en.qe = dio_pad_attr_8_qe;
+
+ // F[slew_rate_8]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_8_slew_rate_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_slew_rate_8_wd),
+ .d (hw2reg.dio_pad_attr[8].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[8].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_8_slew_rate_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].slew_rate.qe = dio_pad_attr_8_qe;
+
+ // F[drive_strength_8]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_8_drive_strength_8 (
+ .re (dio_pad_attr_8_re),
+ .we (dio_pad_attr_8_gated_we),
+ .wd (dio_pad_attr_8_drive_strength_8_wd),
+ .d (hw2reg.dio_pad_attr[8].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_8_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[8].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_8_drive_strength_8_qs)
+ );
+ assign reg2hw.dio_pad_attr[8].drive_strength.qe = dio_pad_attr_8_qe;
+
+
+ // Subregister 9 of Multireg dio_pad_attr
+ // R[dio_pad_attr_9]: V(True)
+ logic dio_pad_attr_9_qe;
+ logic [8:0] dio_pad_attr_9_flds_we;
+ assign dio_pad_attr_9_qe = &dio_pad_attr_9_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_9_gated_we;
+ assign dio_pad_attr_9_gated_we = dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs;
+ // F[invert_9]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_invert_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_invert_9_wd),
+ .d (hw2reg.dio_pad_attr[9].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[9].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_9_invert_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].invert.qe = dio_pad_attr_9_qe;
+
+ // F[virtual_od_en_9]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_virtual_od_en_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_virtual_od_en_9_wd),
+ .d (hw2reg.dio_pad_attr[9].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[9].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_9_virtual_od_en_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].virtual_od_en.qe = dio_pad_attr_9_qe;
+
+ // F[pull_en_9]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_pull_en_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_pull_en_9_wd),
+ .d (hw2reg.dio_pad_attr[9].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[9].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_9_pull_en_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].pull_en.qe = dio_pad_attr_9_qe;
+
+ // F[pull_select_9]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_pull_select_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_pull_select_9_wd),
+ .d (hw2reg.dio_pad_attr[9].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[9].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_9_pull_select_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].pull_select.qe = dio_pad_attr_9_qe;
+
+ // F[keeper_en_9]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_keeper_en_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_keeper_en_9_wd),
+ .d (hw2reg.dio_pad_attr[9].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[9].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_9_keeper_en_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].keeper_en.qe = dio_pad_attr_9_qe;
+
+ // F[schmitt_en_9]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_schmitt_en_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_schmitt_en_9_wd),
+ .d (hw2reg.dio_pad_attr[9].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[9].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_9_schmitt_en_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].schmitt_en.qe = dio_pad_attr_9_qe;
+
+ // F[od_en_9]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_9_od_en_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_od_en_9_wd),
+ .d (hw2reg.dio_pad_attr[9].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[9].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_9_od_en_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].od_en.qe = dio_pad_attr_9_qe;
+
+ // F[slew_rate_9]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_9_slew_rate_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_slew_rate_9_wd),
+ .d (hw2reg.dio_pad_attr[9].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[9].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_9_slew_rate_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].slew_rate.qe = dio_pad_attr_9_qe;
+
+ // F[drive_strength_9]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_9_drive_strength_9 (
+ .re (dio_pad_attr_9_re),
+ .we (dio_pad_attr_9_gated_we),
+ .wd (dio_pad_attr_9_drive_strength_9_wd),
+ .d (hw2reg.dio_pad_attr[9].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_9_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[9].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_9_drive_strength_9_qs)
+ );
+ assign reg2hw.dio_pad_attr[9].drive_strength.qe = dio_pad_attr_9_qe;
+
+
+ // Subregister 10 of Multireg dio_pad_attr
+ // R[dio_pad_attr_10]: V(True)
+ logic dio_pad_attr_10_qe;
+ logic [8:0] dio_pad_attr_10_flds_we;
+ assign dio_pad_attr_10_qe = &dio_pad_attr_10_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_10_gated_we;
+ assign dio_pad_attr_10_gated_we = dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs;
+ // F[invert_10]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_invert_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_invert_10_wd),
+ .d (hw2reg.dio_pad_attr[10].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[10].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_10_invert_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].invert.qe = dio_pad_attr_10_qe;
+
+ // F[virtual_od_en_10]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_virtual_od_en_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_virtual_od_en_10_wd),
+ .d (hw2reg.dio_pad_attr[10].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[10].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_10_virtual_od_en_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].virtual_od_en.qe = dio_pad_attr_10_qe;
+
+ // F[pull_en_10]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_pull_en_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_pull_en_10_wd),
+ .d (hw2reg.dio_pad_attr[10].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[10].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_10_pull_en_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].pull_en.qe = dio_pad_attr_10_qe;
+
+ // F[pull_select_10]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_pull_select_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_pull_select_10_wd),
+ .d (hw2reg.dio_pad_attr[10].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[10].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_10_pull_select_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].pull_select.qe = dio_pad_attr_10_qe;
+
+ // F[keeper_en_10]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_keeper_en_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_keeper_en_10_wd),
+ .d (hw2reg.dio_pad_attr[10].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[10].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_10_keeper_en_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].keeper_en.qe = dio_pad_attr_10_qe;
+
+ // F[schmitt_en_10]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_schmitt_en_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_schmitt_en_10_wd),
+ .d (hw2reg.dio_pad_attr[10].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[10].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_10_schmitt_en_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].schmitt_en.qe = dio_pad_attr_10_qe;
+
+ // F[od_en_10]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_10_od_en_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_od_en_10_wd),
+ .d (hw2reg.dio_pad_attr[10].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[10].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_10_od_en_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].od_en.qe = dio_pad_attr_10_qe;
+
+ // F[slew_rate_10]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_10_slew_rate_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_slew_rate_10_wd),
+ .d (hw2reg.dio_pad_attr[10].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[10].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_10_slew_rate_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].slew_rate.qe = dio_pad_attr_10_qe;
+
+ // F[drive_strength_10]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_10_drive_strength_10 (
+ .re (dio_pad_attr_10_re),
+ .we (dio_pad_attr_10_gated_we),
+ .wd (dio_pad_attr_10_drive_strength_10_wd),
+ .d (hw2reg.dio_pad_attr[10].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_10_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[10].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_10_drive_strength_10_qs)
+ );
+ assign reg2hw.dio_pad_attr[10].drive_strength.qe = dio_pad_attr_10_qe;
+
+
+ // Subregister 11 of Multireg dio_pad_attr
+ // R[dio_pad_attr_11]: V(True)
+ logic dio_pad_attr_11_qe;
+ logic [8:0] dio_pad_attr_11_flds_we;
+ assign dio_pad_attr_11_qe = &dio_pad_attr_11_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_11_gated_we;
+ assign dio_pad_attr_11_gated_we = dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs;
+ // F[invert_11]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_invert_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_invert_11_wd),
+ .d (hw2reg.dio_pad_attr[11].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[11].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_11_invert_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].invert.qe = dio_pad_attr_11_qe;
+
+ // F[virtual_od_en_11]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_virtual_od_en_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_virtual_od_en_11_wd),
+ .d (hw2reg.dio_pad_attr[11].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[11].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_11_virtual_od_en_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].virtual_od_en.qe = dio_pad_attr_11_qe;
+
+ // F[pull_en_11]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_pull_en_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_pull_en_11_wd),
+ .d (hw2reg.dio_pad_attr[11].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[11].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_11_pull_en_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].pull_en.qe = dio_pad_attr_11_qe;
+
+ // F[pull_select_11]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_pull_select_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_pull_select_11_wd),
+ .d (hw2reg.dio_pad_attr[11].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[11].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_11_pull_select_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].pull_select.qe = dio_pad_attr_11_qe;
+
+ // F[keeper_en_11]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_keeper_en_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_keeper_en_11_wd),
+ .d (hw2reg.dio_pad_attr[11].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[11].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_11_keeper_en_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].keeper_en.qe = dio_pad_attr_11_qe;
+
+ // F[schmitt_en_11]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_schmitt_en_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_schmitt_en_11_wd),
+ .d (hw2reg.dio_pad_attr[11].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[11].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_11_schmitt_en_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].schmitt_en.qe = dio_pad_attr_11_qe;
+
+ // F[od_en_11]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_11_od_en_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_od_en_11_wd),
+ .d (hw2reg.dio_pad_attr[11].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[11].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_11_od_en_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].od_en.qe = dio_pad_attr_11_qe;
+
+ // F[slew_rate_11]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_11_slew_rate_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_slew_rate_11_wd),
+ .d (hw2reg.dio_pad_attr[11].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[11].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_11_slew_rate_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].slew_rate.qe = dio_pad_attr_11_qe;
+
+ // F[drive_strength_11]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_11_drive_strength_11 (
+ .re (dio_pad_attr_11_re),
+ .we (dio_pad_attr_11_gated_we),
+ .wd (dio_pad_attr_11_drive_strength_11_wd),
+ .d (hw2reg.dio_pad_attr[11].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_11_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[11].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_11_drive_strength_11_qs)
+ );
+ assign reg2hw.dio_pad_attr[11].drive_strength.qe = dio_pad_attr_11_qe;
+
+
+ // Subregister 12 of Multireg dio_pad_attr
+ // R[dio_pad_attr_12]: V(True)
+ logic dio_pad_attr_12_qe;
+ logic [8:0] dio_pad_attr_12_flds_we;
+ assign dio_pad_attr_12_qe = &dio_pad_attr_12_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_12_gated_we;
+ assign dio_pad_attr_12_gated_we = dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs;
+ // F[invert_12]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_invert_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_invert_12_wd),
+ .d (hw2reg.dio_pad_attr[12].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[12].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_12_invert_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].invert.qe = dio_pad_attr_12_qe;
+
+ // F[virtual_od_en_12]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_virtual_od_en_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_virtual_od_en_12_wd),
+ .d (hw2reg.dio_pad_attr[12].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[12].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_12_virtual_od_en_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].virtual_od_en.qe = dio_pad_attr_12_qe;
+
+ // F[pull_en_12]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_pull_en_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_pull_en_12_wd),
+ .d (hw2reg.dio_pad_attr[12].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[12].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_12_pull_en_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].pull_en.qe = dio_pad_attr_12_qe;
+
+ // F[pull_select_12]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_pull_select_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_pull_select_12_wd),
+ .d (hw2reg.dio_pad_attr[12].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[12].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_12_pull_select_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].pull_select.qe = dio_pad_attr_12_qe;
+
+ // F[keeper_en_12]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_keeper_en_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_keeper_en_12_wd),
+ .d (hw2reg.dio_pad_attr[12].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[12].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_12_keeper_en_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].keeper_en.qe = dio_pad_attr_12_qe;
+
+ // F[schmitt_en_12]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_schmitt_en_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_schmitt_en_12_wd),
+ .d (hw2reg.dio_pad_attr[12].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[12].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_12_schmitt_en_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].schmitt_en.qe = dio_pad_attr_12_qe;
+
+ // F[od_en_12]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_12_od_en_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_od_en_12_wd),
+ .d (hw2reg.dio_pad_attr[12].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[12].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_12_od_en_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].od_en.qe = dio_pad_attr_12_qe;
+
+ // F[slew_rate_12]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_12_slew_rate_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_slew_rate_12_wd),
+ .d (hw2reg.dio_pad_attr[12].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[12].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_12_slew_rate_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].slew_rate.qe = dio_pad_attr_12_qe;
+
+ // F[drive_strength_12]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_12_drive_strength_12 (
+ .re (dio_pad_attr_12_re),
+ .we (dio_pad_attr_12_gated_we),
+ .wd (dio_pad_attr_12_drive_strength_12_wd),
+ .d (hw2reg.dio_pad_attr[12].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_12_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[12].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_12_drive_strength_12_qs)
+ );
+ assign reg2hw.dio_pad_attr[12].drive_strength.qe = dio_pad_attr_12_qe;
+
+
+ // Subregister 13 of Multireg dio_pad_attr
+ // R[dio_pad_attr_13]: V(True)
+ logic dio_pad_attr_13_qe;
+ logic [8:0] dio_pad_attr_13_flds_we;
+ assign dio_pad_attr_13_qe = &dio_pad_attr_13_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_13_gated_we;
+ assign dio_pad_attr_13_gated_we = dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs;
+ // F[invert_13]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_invert_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_invert_13_wd),
+ .d (hw2reg.dio_pad_attr[13].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[13].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_13_invert_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].invert.qe = dio_pad_attr_13_qe;
+
+ // F[virtual_od_en_13]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_virtual_od_en_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_virtual_od_en_13_wd),
+ .d (hw2reg.dio_pad_attr[13].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[13].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_13_virtual_od_en_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].virtual_od_en.qe = dio_pad_attr_13_qe;
+
+ // F[pull_en_13]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_pull_en_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_pull_en_13_wd),
+ .d (hw2reg.dio_pad_attr[13].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[13].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_13_pull_en_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].pull_en.qe = dio_pad_attr_13_qe;
+
+ // F[pull_select_13]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_pull_select_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_pull_select_13_wd),
+ .d (hw2reg.dio_pad_attr[13].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[13].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_13_pull_select_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].pull_select.qe = dio_pad_attr_13_qe;
+
+ // F[keeper_en_13]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_keeper_en_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_keeper_en_13_wd),
+ .d (hw2reg.dio_pad_attr[13].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[13].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_13_keeper_en_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].keeper_en.qe = dio_pad_attr_13_qe;
+
+ // F[schmitt_en_13]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_schmitt_en_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_schmitt_en_13_wd),
+ .d (hw2reg.dio_pad_attr[13].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[13].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_13_schmitt_en_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].schmitt_en.qe = dio_pad_attr_13_qe;
+
+ // F[od_en_13]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_13_od_en_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_od_en_13_wd),
+ .d (hw2reg.dio_pad_attr[13].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[13].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_13_od_en_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].od_en.qe = dio_pad_attr_13_qe;
+
+ // F[slew_rate_13]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_13_slew_rate_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_slew_rate_13_wd),
+ .d (hw2reg.dio_pad_attr[13].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[13].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_13_slew_rate_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].slew_rate.qe = dio_pad_attr_13_qe;
+
+ // F[drive_strength_13]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_13_drive_strength_13 (
+ .re (dio_pad_attr_13_re),
+ .we (dio_pad_attr_13_gated_we),
+ .wd (dio_pad_attr_13_drive_strength_13_wd),
+ .d (hw2reg.dio_pad_attr[13].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_13_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[13].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_13_drive_strength_13_qs)
+ );
+ assign reg2hw.dio_pad_attr[13].drive_strength.qe = dio_pad_attr_13_qe;
+
+
+ // Subregister 14 of Multireg dio_pad_attr
+ // R[dio_pad_attr_14]: V(True)
+ logic dio_pad_attr_14_qe;
+ logic [8:0] dio_pad_attr_14_flds_we;
+ assign dio_pad_attr_14_qe = &dio_pad_attr_14_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_14_gated_we;
+ assign dio_pad_attr_14_gated_we = dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs;
+ // F[invert_14]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_invert_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_invert_14_wd),
+ .d (hw2reg.dio_pad_attr[14].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[14].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_14_invert_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].invert.qe = dio_pad_attr_14_qe;
+
+ // F[virtual_od_en_14]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_virtual_od_en_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_virtual_od_en_14_wd),
+ .d (hw2reg.dio_pad_attr[14].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[14].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_14_virtual_od_en_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].virtual_od_en.qe = dio_pad_attr_14_qe;
+
+ // F[pull_en_14]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_pull_en_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_pull_en_14_wd),
+ .d (hw2reg.dio_pad_attr[14].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[14].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_14_pull_en_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].pull_en.qe = dio_pad_attr_14_qe;
+
+ // F[pull_select_14]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_pull_select_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_pull_select_14_wd),
+ .d (hw2reg.dio_pad_attr[14].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[14].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_14_pull_select_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].pull_select.qe = dio_pad_attr_14_qe;
+
+ // F[keeper_en_14]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_keeper_en_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_keeper_en_14_wd),
+ .d (hw2reg.dio_pad_attr[14].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[14].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_14_keeper_en_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].keeper_en.qe = dio_pad_attr_14_qe;
+
+ // F[schmitt_en_14]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_schmitt_en_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_schmitt_en_14_wd),
+ .d (hw2reg.dio_pad_attr[14].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[14].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_14_schmitt_en_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].schmitt_en.qe = dio_pad_attr_14_qe;
+
+ // F[od_en_14]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_14_od_en_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_od_en_14_wd),
+ .d (hw2reg.dio_pad_attr[14].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[14].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_14_od_en_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].od_en.qe = dio_pad_attr_14_qe;
+
+ // F[slew_rate_14]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_14_slew_rate_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_slew_rate_14_wd),
+ .d (hw2reg.dio_pad_attr[14].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[14].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_14_slew_rate_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].slew_rate.qe = dio_pad_attr_14_qe;
+
+ // F[drive_strength_14]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_14_drive_strength_14 (
+ .re (dio_pad_attr_14_re),
+ .we (dio_pad_attr_14_gated_we),
+ .wd (dio_pad_attr_14_drive_strength_14_wd),
+ .d (hw2reg.dio_pad_attr[14].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_14_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[14].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_14_drive_strength_14_qs)
+ );
+ assign reg2hw.dio_pad_attr[14].drive_strength.qe = dio_pad_attr_14_qe;
+
+
+ // Subregister 15 of Multireg dio_pad_attr
+ // R[dio_pad_attr_15]: V(True)
+ logic dio_pad_attr_15_qe;
+ logic [8:0] dio_pad_attr_15_flds_we;
+ assign dio_pad_attr_15_qe = &dio_pad_attr_15_flds_we;
+ // Create REGWEN-gated WE signal
+ logic dio_pad_attr_15_gated_we;
+ assign dio_pad_attr_15_gated_we = dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs;
+ // F[invert_15]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_invert_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_invert_15_wd),
+ .d (hw2reg.dio_pad_attr[15].invert.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[0]),
+ .q (reg2hw.dio_pad_attr[15].invert.q),
+ .ds (),
+ .qs (dio_pad_attr_15_invert_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].invert.qe = dio_pad_attr_15_qe;
+
+ // F[virtual_od_en_15]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_virtual_od_en_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_virtual_od_en_15_wd),
+ .d (hw2reg.dio_pad_attr[15].virtual_od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[1]),
+ .q (reg2hw.dio_pad_attr[15].virtual_od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_15_virtual_od_en_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].virtual_od_en.qe = dio_pad_attr_15_qe;
+
+ // F[pull_en_15]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_pull_en_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_pull_en_15_wd),
+ .d (hw2reg.dio_pad_attr[15].pull_en.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[2]),
+ .q (reg2hw.dio_pad_attr[15].pull_en.q),
+ .ds (),
+ .qs (dio_pad_attr_15_pull_en_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].pull_en.qe = dio_pad_attr_15_qe;
+
+ // F[pull_select_15]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_pull_select_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_pull_select_15_wd),
+ .d (hw2reg.dio_pad_attr[15].pull_select.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[3]),
+ .q (reg2hw.dio_pad_attr[15].pull_select.q),
+ .ds (),
+ .qs (dio_pad_attr_15_pull_select_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].pull_select.qe = dio_pad_attr_15_qe;
+
+ // F[keeper_en_15]: 4:4
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_keeper_en_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_keeper_en_15_wd),
+ .d (hw2reg.dio_pad_attr[15].keeper_en.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[4]),
+ .q (reg2hw.dio_pad_attr[15].keeper_en.q),
+ .ds (),
+ .qs (dio_pad_attr_15_keeper_en_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].keeper_en.qe = dio_pad_attr_15_qe;
+
+ // F[schmitt_en_15]: 5:5
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_schmitt_en_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_schmitt_en_15_wd),
+ .d (hw2reg.dio_pad_attr[15].schmitt_en.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[5]),
+ .q (reg2hw.dio_pad_attr[15].schmitt_en.q),
+ .ds (),
+ .qs (dio_pad_attr_15_schmitt_en_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].schmitt_en.qe = dio_pad_attr_15_qe;
+
+ // F[od_en_15]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_dio_pad_attr_15_od_en_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_od_en_15_wd),
+ .d (hw2reg.dio_pad_attr[15].od_en.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[6]),
+ .q (reg2hw.dio_pad_attr[15].od_en.q),
+ .ds (),
+ .qs (dio_pad_attr_15_od_en_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].od_en.qe = dio_pad_attr_15_qe;
+
+ // F[slew_rate_15]: 17:16
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_dio_pad_attr_15_slew_rate_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_slew_rate_15_wd),
+ .d (hw2reg.dio_pad_attr[15].slew_rate.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[7]),
+ .q (reg2hw.dio_pad_attr[15].slew_rate.q),
+ .ds (),
+ .qs (dio_pad_attr_15_slew_rate_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].slew_rate.qe = dio_pad_attr_15_qe;
+
+ // F[drive_strength_15]: 23:20
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_dio_pad_attr_15_drive_strength_15 (
+ .re (dio_pad_attr_15_re),
+ .we (dio_pad_attr_15_gated_we),
+ .wd (dio_pad_attr_15_drive_strength_15_wd),
+ .d (hw2reg.dio_pad_attr[15].drive_strength.d),
+ .qre (),
+ .qe (dio_pad_attr_15_flds_we[8]),
+ .q (reg2hw.dio_pad_attr[15].drive_strength.q),
+ .ds (),
+ .qs (dio_pad_attr_15_drive_strength_15_qs)
+ );
+ assign reg2hw.dio_pad_attr[15].drive_strength.qe = dio_pad_attr_15_qe;
+
+
+ // Subregister 0 of Multireg mio_pad_sleep_status
+ // R[mio_pad_sleep_status_0]: V(False)
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[0].de),
+ .d (hw2reg.mio_pad_sleep_status[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_0_qs)
+ );
+
+ // F[en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[1].de),
+ .d (hw2reg.mio_pad_sleep_status[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_1_qs)
+ );
+
+ // F[en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_2_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[2].de),
+ .d (hw2reg.mio_pad_sleep_status[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_2_qs)
+ );
+
+ // F[en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_3_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[3].de),
+ .d (hw2reg.mio_pad_sleep_status[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_3_qs)
+ );
+
+ // F[en_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_4_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[4].de),
+ .d (hw2reg.mio_pad_sleep_status[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_4_qs)
+ );
+
+ // F[en_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_5_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[5].de),
+ .d (hw2reg.mio_pad_sleep_status[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_5_qs)
+ );
+
+ // F[en_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_6_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[6].de),
+ .d (hw2reg.mio_pad_sleep_status[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_6_qs)
+ );
+
+ // F[en_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_7_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[7].de),
+ .d (hw2reg.mio_pad_sleep_status[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_7_qs)
+ );
+
+ // F[en_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_8_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[8].de),
+ .d (hw2reg.mio_pad_sleep_status[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_8_qs)
+ );
+
+ // F[en_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_9_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[9].de),
+ .d (hw2reg.mio_pad_sleep_status[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_9_qs)
+ );
+
+ // F[en_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_10_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[10].de),
+ .d (hw2reg.mio_pad_sleep_status[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_10_qs)
+ );
+
+ // F[en_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_11_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[11].de),
+ .d (hw2reg.mio_pad_sleep_status[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_11_qs)
+ );
+
+ // F[en_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_12_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[12].de),
+ .d (hw2reg.mio_pad_sleep_status[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_12_qs)
+ );
+
+ // F[en_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_13_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[13].de),
+ .d (hw2reg.mio_pad_sleep_status[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_13_qs)
+ );
+
+ // F[en_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_14_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[14].de),
+ .d (hw2reg.mio_pad_sleep_status[14].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_14_qs)
+ );
+
+ // F[en_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_15_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[15].de),
+ .d (hw2reg.mio_pad_sleep_status[15].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_15_qs)
+ );
+
+ // F[en_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_16_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[16].de),
+ .d (hw2reg.mio_pad_sleep_status[16].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_16_qs)
+ );
+
+ // F[en_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_17_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[17].de),
+ .d (hw2reg.mio_pad_sleep_status[17].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_17_qs)
+ );
+
+ // F[en_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_18_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[18].de),
+ .d (hw2reg.mio_pad_sleep_status[18].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_18_qs)
+ );
+
+ // F[en_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_19_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[19].de),
+ .d (hw2reg.mio_pad_sleep_status[19].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_19_qs)
+ );
+
+ // F[en_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_20_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[20].de),
+ .d (hw2reg.mio_pad_sleep_status[20].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_20_qs)
+ );
+
+ // F[en_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_21_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[21].de),
+ .d (hw2reg.mio_pad_sleep_status[21].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_21_qs)
+ );
+
+ // F[en_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_22_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[22].de),
+ .d (hw2reg.mio_pad_sleep_status[22].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_22_qs)
+ );
+
+ // F[en_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_23_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[23].de),
+ .d (hw2reg.mio_pad_sleep_status[23].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_23_qs)
+ );
+
+ // F[en_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_24_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[24].de),
+ .d (hw2reg.mio_pad_sleep_status[24].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_24_qs)
+ );
+
+ // F[en_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_25_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[25].de),
+ .d (hw2reg.mio_pad_sleep_status[25].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_25_qs)
+ );
+
+ // F[en_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_26_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[26].de),
+ .d (hw2reg.mio_pad_sleep_status[26].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_26_qs)
+ );
+
+ // F[en_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_27_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[27].de),
+ .d (hw2reg.mio_pad_sleep_status[27].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_27_qs)
+ );
+
+ // F[en_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_28_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[28].de),
+ .d (hw2reg.mio_pad_sleep_status[28].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_28_qs)
+ );
+
+ // F[en_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_29_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[29].de),
+ .d (hw2reg.mio_pad_sleep_status[29].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_29_qs)
+ );
+
+ // F[en_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_30_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[30].de),
+ .d (hw2reg.mio_pad_sleep_status[30].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_30_qs)
+ );
+
+ // F[en_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_0_en_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_0_we),
+ .wd (mio_pad_sleep_status_0_en_31_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[31].de),
+ .d (hw2reg.mio_pad_sleep_status[31].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_0_en_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_pad_sleep_status
+ // R[mio_pad_sleep_status_1]: V(False)
+ // F[en_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_32_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[32].de),
+ .d (hw2reg.mio_pad_sleep_status[32].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_32_qs)
+ );
+
+ // F[en_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_33_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[33].de),
+ .d (hw2reg.mio_pad_sleep_status[33].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_33_qs)
+ );
+
+ // F[en_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_34_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[34].de),
+ .d (hw2reg.mio_pad_sleep_status[34].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_34_qs)
+ );
+
+ // F[en_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_35_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[35].de),
+ .d (hw2reg.mio_pad_sleep_status[35].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_35_qs)
+ );
+
+ // F[en_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_36_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[36].de),
+ .d (hw2reg.mio_pad_sleep_status[36].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_36_qs)
+ );
+
+ // F[en_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_37_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[37].de),
+ .d (hw2reg.mio_pad_sleep_status[37].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_37_qs)
+ );
+
+ // F[en_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_38_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[38].de),
+ .d (hw2reg.mio_pad_sleep_status[38].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_38_qs)
+ );
+
+ // F[en_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_39_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[39].de),
+ .d (hw2reg.mio_pad_sleep_status[39].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_39_qs)
+ );
+
+ // F[en_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_40_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[40].de),
+ .d (hw2reg.mio_pad_sleep_status[40].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_40_qs)
+ );
+
+ // F[en_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_41_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[41].de),
+ .d (hw2reg.mio_pad_sleep_status[41].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_41_qs)
+ );
+
+ // F[en_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_42_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[42].de),
+ .d (hw2reg.mio_pad_sleep_status[42].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_42_qs)
+ );
+
+ // F[en_43]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_43_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[43].de),
+ .d (hw2reg.mio_pad_sleep_status[43].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_43_qs)
+ );
+
+ // F[en_44]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_44_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[44].de),
+ .d (hw2reg.mio_pad_sleep_status[44].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_44_qs)
+ );
+
+ // F[en_45]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_45_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[45].de),
+ .d (hw2reg.mio_pad_sleep_status[45].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_45_qs)
+ );
+
+ // F[en_46]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_46_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[46].de),
+ .d (hw2reg.mio_pad_sleep_status[46].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_46_qs)
+ );
+
+ // F[en_47]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_47_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[47].de),
+ .d (hw2reg.mio_pad_sleep_status[47].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_47_qs)
+ );
+
+ // F[en_48]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_48_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[48].de),
+ .d (hw2reg.mio_pad_sleep_status[48].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_48_qs)
+ );
+
+ // F[en_49]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_49_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[49].de),
+ .d (hw2reg.mio_pad_sleep_status[49].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_49_qs)
+ );
+
+ // F[en_50]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_50_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[50].de),
+ .d (hw2reg.mio_pad_sleep_status[50].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_50_qs)
+ );
+
+ // F[en_51]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_51_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[51].de),
+ .d (hw2reg.mio_pad_sleep_status[51].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_51_qs)
+ );
+
+ // F[en_52]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_status_1_en_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_status_1_we),
+ .wd (mio_pad_sleep_status_1_en_52_wd),
+
+ // from internal hardware
+ .de (hw2reg.mio_pad_sleep_status[52].de),
+ .d (hw2reg.mio_pad_sleep_status[52].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_status[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_status_1_en_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_0_we),
+ .wd (mio_pad_sleep_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_1_we),
+ .wd (mio_pad_sleep_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_2_we),
+ .wd (mio_pad_sleep_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_3_we),
+ .wd (mio_pad_sleep_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_4_we),
+ .wd (mio_pad_sleep_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_5_we),
+ .wd (mio_pad_sleep_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_6_we),
+ .wd (mio_pad_sleep_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_7_we),
+ .wd (mio_pad_sleep_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_8_we),
+ .wd (mio_pad_sleep_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_9_we),
+ .wd (mio_pad_sleep_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_10_we),
+ .wd (mio_pad_sleep_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_11_we),
+ .wd (mio_pad_sleep_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_12_we),
+ .wd (mio_pad_sleep_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_13_we),
+ .wd (mio_pad_sleep_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_14_we),
+ .wd (mio_pad_sleep_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_15_we),
+ .wd (mio_pad_sleep_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_16_we),
+ .wd (mio_pad_sleep_regwen_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_17_we),
+ .wd (mio_pad_sleep_regwen_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_18_we),
+ .wd (mio_pad_sleep_regwen_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_19_we),
+ .wd (mio_pad_sleep_regwen_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_20_we),
+ .wd (mio_pad_sleep_regwen_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_21_we),
+ .wd (mio_pad_sleep_regwen_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_22_we),
+ .wd (mio_pad_sleep_regwen_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_23_we),
+ .wd (mio_pad_sleep_regwen_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_24_we),
+ .wd (mio_pad_sleep_regwen_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_25_we),
+ .wd (mio_pad_sleep_regwen_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_26_we),
+ .wd (mio_pad_sleep_regwen_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_27_we),
+ .wd (mio_pad_sleep_regwen_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_28_we),
+ .wd (mio_pad_sleep_regwen_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_29_we),
+ .wd (mio_pad_sleep_regwen_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_30_we),
+ .wd (mio_pad_sleep_regwen_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_31_we),
+ .wd (mio_pad_sleep_regwen_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_32_we),
+ .wd (mio_pad_sleep_regwen_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_33_we),
+ .wd (mio_pad_sleep_regwen_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_34_we),
+ .wd (mio_pad_sleep_regwen_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_35_we),
+ .wd (mio_pad_sleep_regwen_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_36_we),
+ .wd (mio_pad_sleep_regwen_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_37_we),
+ .wd (mio_pad_sleep_regwen_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_38_we),
+ .wd (mio_pad_sleep_regwen_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_39_we),
+ .wd (mio_pad_sleep_regwen_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_40_we),
+ .wd (mio_pad_sleep_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_41_we),
+ .wd (mio_pad_sleep_regwen_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_42_we),
+ .wd (mio_pad_sleep_regwen_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_43_we),
+ .wd (mio_pad_sleep_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_44_we),
+ .wd (mio_pad_sleep_regwen_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_45_we),
+ .wd (mio_pad_sleep_regwen_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_46_we),
+ .wd (mio_pad_sleep_regwen_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_47_we),
+ .wd (mio_pad_sleep_regwen_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_48_we),
+ .wd (mio_pad_sleep_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_49_we),
+ .wd (mio_pad_sleep_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_50_we),
+ .wd (mio_pad_sleep_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_51_we),
+ .wd (mio_pad_sleep_regwen_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_pad_sleep_regwen
+ // R[mio_pad_sleep_regwen_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_mio_pad_sleep_regwen_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_regwen_52_we),
+ .wd (mio_pad_sleep_regwen_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_regwen_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_0_gated_we;
+ assign mio_pad_sleep_en_0_gated_we = mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_0_gated_we),
+ .wd (mio_pad_sleep_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_1_gated_we;
+ assign mio_pad_sleep_en_1_gated_we = mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_1_gated_we),
+ .wd (mio_pad_sleep_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_2_gated_we;
+ assign mio_pad_sleep_en_2_gated_we = mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_2_gated_we),
+ .wd (mio_pad_sleep_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_3_gated_we;
+ assign mio_pad_sleep_en_3_gated_we = mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_3_gated_we),
+ .wd (mio_pad_sleep_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_4_gated_we;
+ assign mio_pad_sleep_en_4_gated_we = mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_4_gated_we),
+ .wd (mio_pad_sleep_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_5_gated_we;
+ assign mio_pad_sleep_en_5_gated_we = mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_5_gated_we),
+ .wd (mio_pad_sleep_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_6_gated_we;
+ assign mio_pad_sleep_en_6_gated_we = mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_6_gated_we),
+ .wd (mio_pad_sleep_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_7_gated_we;
+ assign mio_pad_sleep_en_7_gated_we = mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_7_gated_we),
+ .wd (mio_pad_sleep_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_8_gated_we;
+ assign mio_pad_sleep_en_8_gated_we = mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_8_gated_we),
+ .wd (mio_pad_sleep_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_9_gated_we;
+ assign mio_pad_sleep_en_9_gated_we = mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_9_gated_we),
+ .wd (mio_pad_sleep_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_10_gated_we;
+ assign mio_pad_sleep_en_10_gated_we = mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_10_gated_we),
+ .wd (mio_pad_sleep_en_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_11_gated_we;
+ assign mio_pad_sleep_en_11_gated_we = mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_11_gated_we),
+ .wd (mio_pad_sleep_en_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_12_gated_we;
+ assign mio_pad_sleep_en_12_gated_we = mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_12_gated_we),
+ .wd (mio_pad_sleep_en_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_13_gated_we;
+ assign mio_pad_sleep_en_13_gated_we = mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_13_gated_we),
+ .wd (mio_pad_sleep_en_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_14_gated_we;
+ assign mio_pad_sleep_en_14_gated_we = mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_14_gated_we),
+ .wd (mio_pad_sleep_en_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_15_gated_we;
+ assign mio_pad_sleep_en_15_gated_we = mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_15_gated_we),
+ .wd (mio_pad_sleep_en_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_16_gated_we;
+ assign mio_pad_sleep_en_16_gated_we = mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_16_gated_we),
+ .wd (mio_pad_sleep_en_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_17_gated_we;
+ assign mio_pad_sleep_en_17_gated_we = mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_17_gated_we),
+ .wd (mio_pad_sleep_en_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_18_gated_we;
+ assign mio_pad_sleep_en_18_gated_we = mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_18_gated_we),
+ .wd (mio_pad_sleep_en_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_19_gated_we;
+ assign mio_pad_sleep_en_19_gated_we = mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_19_gated_we),
+ .wd (mio_pad_sleep_en_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_20_gated_we;
+ assign mio_pad_sleep_en_20_gated_we = mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_20_gated_we),
+ .wd (mio_pad_sleep_en_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_21_gated_we;
+ assign mio_pad_sleep_en_21_gated_we = mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_21_gated_we),
+ .wd (mio_pad_sleep_en_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_22_gated_we;
+ assign mio_pad_sleep_en_22_gated_we = mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_22_gated_we),
+ .wd (mio_pad_sleep_en_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_23_gated_we;
+ assign mio_pad_sleep_en_23_gated_we = mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_23_gated_we),
+ .wd (mio_pad_sleep_en_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_24_gated_we;
+ assign mio_pad_sleep_en_24_gated_we = mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_24_gated_we),
+ .wd (mio_pad_sleep_en_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_25_gated_we;
+ assign mio_pad_sleep_en_25_gated_we = mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_25_gated_we),
+ .wd (mio_pad_sleep_en_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_26_gated_we;
+ assign mio_pad_sleep_en_26_gated_we = mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_26_gated_we),
+ .wd (mio_pad_sleep_en_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_27_gated_we;
+ assign mio_pad_sleep_en_27_gated_we = mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_27_gated_we),
+ .wd (mio_pad_sleep_en_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_28_gated_we;
+ assign mio_pad_sleep_en_28_gated_we = mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_28_gated_we),
+ .wd (mio_pad_sleep_en_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_29_gated_we;
+ assign mio_pad_sleep_en_29_gated_we = mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_29_gated_we),
+ .wd (mio_pad_sleep_en_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_30_gated_we;
+ assign mio_pad_sleep_en_30_gated_we = mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_30_gated_we),
+ .wd (mio_pad_sleep_en_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_31_gated_we;
+ assign mio_pad_sleep_en_31_gated_we = mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_31_gated_we),
+ .wd (mio_pad_sleep_en_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_32_gated_we;
+ assign mio_pad_sleep_en_32_gated_we = mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_32_gated_we),
+ .wd (mio_pad_sleep_en_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_33_gated_we;
+ assign mio_pad_sleep_en_33_gated_we = mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_33_gated_we),
+ .wd (mio_pad_sleep_en_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_34_gated_we;
+ assign mio_pad_sleep_en_34_gated_we = mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_34_gated_we),
+ .wd (mio_pad_sleep_en_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_35_gated_we;
+ assign mio_pad_sleep_en_35_gated_we = mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_35_gated_we),
+ .wd (mio_pad_sleep_en_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_36_gated_we;
+ assign mio_pad_sleep_en_36_gated_we = mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_36_gated_we),
+ .wd (mio_pad_sleep_en_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_37_gated_we;
+ assign mio_pad_sleep_en_37_gated_we = mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_37_gated_we),
+ .wd (mio_pad_sleep_en_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_38_gated_we;
+ assign mio_pad_sleep_en_38_gated_we = mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_38_gated_we),
+ .wd (mio_pad_sleep_en_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_39_gated_we;
+ assign mio_pad_sleep_en_39_gated_we = mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_39_gated_we),
+ .wd (mio_pad_sleep_en_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_40_gated_we;
+ assign mio_pad_sleep_en_40_gated_we = mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_40_gated_we),
+ .wd (mio_pad_sleep_en_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_41_gated_we;
+ assign mio_pad_sleep_en_41_gated_we = mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_41_gated_we),
+ .wd (mio_pad_sleep_en_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_42_gated_we;
+ assign mio_pad_sleep_en_42_gated_we = mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_42_gated_we),
+ .wd (mio_pad_sleep_en_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_43_gated_we;
+ assign mio_pad_sleep_en_43_gated_we = mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_43_gated_we),
+ .wd (mio_pad_sleep_en_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_44_gated_we;
+ assign mio_pad_sleep_en_44_gated_we = mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_44_gated_we),
+ .wd (mio_pad_sleep_en_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_45_gated_we;
+ assign mio_pad_sleep_en_45_gated_we = mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_45_gated_we),
+ .wd (mio_pad_sleep_en_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_46_gated_we;
+ assign mio_pad_sleep_en_46_gated_we = mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_46_gated_we),
+ .wd (mio_pad_sleep_en_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_47_gated_we;
+ assign mio_pad_sleep_en_47_gated_we = mio_pad_sleep_en_47_we & mio_pad_sleep_regwen_47_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_47_gated_we),
+ .wd (mio_pad_sleep_en_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_48_gated_we;
+ assign mio_pad_sleep_en_48_gated_we = mio_pad_sleep_en_48_we & mio_pad_sleep_regwen_48_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_48_gated_we),
+ .wd (mio_pad_sleep_en_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_49_gated_we;
+ assign mio_pad_sleep_en_49_gated_we = mio_pad_sleep_en_49_we & mio_pad_sleep_regwen_49_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_49_gated_we),
+ .wd (mio_pad_sleep_en_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_50_gated_we;
+ assign mio_pad_sleep_en_50_gated_we = mio_pad_sleep_en_50_we & mio_pad_sleep_regwen_50_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_50_gated_we),
+ .wd (mio_pad_sleep_en_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_51_gated_we;
+ assign mio_pad_sleep_en_51_gated_we = mio_pad_sleep_en_51_we & mio_pad_sleep_regwen_51_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_51_gated_we),
+ .wd (mio_pad_sleep_en_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_pad_sleep_en
+ // R[mio_pad_sleep_en_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_en_52_gated_we;
+ assign mio_pad_sleep_en_52_gated_we = mio_pad_sleep_en_52_we & mio_pad_sleep_regwen_52_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_mio_pad_sleep_en_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_en_52_gated_we),
+ .wd (mio_pad_sleep_en_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_en[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_en_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_0_gated_we;
+ assign mio_pad_sleep_mode_0_gated_we = mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_0_gated_we),
+ .wd (mio_pad_sleep_mode_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_1_gated_we;
+ assign mio_pad_sleep_mode_1_gated_we = mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_1_gated_we),
+ .wd (mio_pad_sleep_mode_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_2_gated_we;
+ assign mio_pad_sleep_mode_2_gated_we = mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_2_gated_we),
+ .wd (mio_pad_sleep_mode_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_3_gated_we;
+ assign mio_pad_sleep_mode_3_gated_we = mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_3_gated_we),
+ .wd (mio_pad_sleep_mode_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_4_gated_we;
+ assign mio_pad_sleep_mode_4_gated_we = mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_4_gated_we),
+ .wd (mio_pad_sleep_mode_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_5_gated_we;
+ assign mio_pad_sleep_mode_5_gated_we = mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_5_gated_we),
+ .wd (mio_pad_sleep_mode_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_6_gated_we;
+ assign mio_pad_sleep_mode_6_gated_we = mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_6_gated_we),
+ .wd (mio_pad_sleep_mode_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_7_gated_we;
+ assign mio_pad_sleep_mode_7_gated_we = mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_7_gated_we),
+ .wd (mio_pad_sleep_mode_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_8_gated_we;
+ assign mio_pad_sleep_mode_8_gated_we = mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_8_gated_we),
+ .wd (mio_pad_sleep_mode_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_9_gated_we;
+ assign mio_pad_sleep_mode_9_gated_we = mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_9_gated_we),
+ .wd (mio_pad_sleep_mode_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_10_gated_we;
+ assign mio_pad_sleep_mode_10_gated_we = mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_10_gated_we),
+ .wd (mio_pad_sleep_mode_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_11_gated_we;
+ assign mio_pad_sleep_mode_11_gated_we = mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_11_gated_we),
+ .wd (mio_pad_sleep_mode_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_12_gated_we;
+ assign mio_pad_sleep_mode_12_gated_we = mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_12_gated_we),
+ .wd (mio_pad_sleep_mode_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_13_gated_we;
+ assign mio_pad_sleep_mode_13_gated_we = mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_13_gated_we),
+ .wd (mio_pad_sleep_mode_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_14_gated_we;
+ assign mio_pad_sleep_mode_14_gated_we = mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_14_gated_we),
+ .wd (mio_pad_sleep_mode_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_15_gated_we;
+ assign mio_pad_sleep_mode_15_gated_we = mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_15_gated_we),
+ .wd (mio_pad_sleep_mode_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_16_gated_we;
+ assign mio_pad_sleep_mode_16_gated_we = mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_16_gated_we),
+ .wd (mio_pad_sleep_mode_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_17_gated_we;
+ assign mio_pad_sleep_mode_17_gated_we = mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_17_gated_we),
+ .wd (mio_pad_sleep_mode_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_18_gated_we;
+ assign mio_pad_sleep_mode_18_gated_we = mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_18_gated_we),
+ .wd (mio_pad_sleep_mode_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_19_gated_we;
+ assign mio_pad_sleep_mode_19_gated_we = mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_19_gated_we),
+ .wd (mio_pad_sleep_mode_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_20_gated_we;
+ assign mio_pad_sleep_mode_20_gated_we = mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_20_gated_we),
+ .wd (mio_pad_sleep_mode_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_21_gated_we;
+ assign mio_pad_sleep_mode_21_gated_we = mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_21_gated_we),
+ .wd (mio_pad_sleep_mode_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_22_gated_we;
+ assign mio_pad_sleep_mode_22_gated_we = mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_22_gated_we),
+ .wd (mio_pad_sleep_mode_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_23_gated_we;
+ assign mio_pad_sleep_mode_23_gated_we = mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_23_gated_we),
+ .wd (mio_pad_sleep_mode_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_24_gated_we;
+ assign mio_pad_sleep_mode_24_gated_we = mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_24_gated_we),
+ .wd (mio_pad_sleep_mode_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_25_gated_we;
+ assign mio_pad_sleep_mode_25_gated_we = mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_25_gated_we),
+ .wd (mio_pad_sleep_mode_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_26_gated_we;
+ assign mio_pad_sleep_mode_26_gated_we = mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_26_gated_we),
+ .wd (mio_pad_sleep_mode_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_27_gated_we;
+ assign mio_pad_sleep_mode_27_gated_we = mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_27_gated_we),
+ .wd (mio_pad_sleep_mode_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_28_gated_we;
+ assign mio_pad_sleep_mode_28_gated_we = mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_28_gated_we),
+ .wd (mio_pad_sleep_mode_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_29_gated_we;
+ assign mio_pad_sleep_mode_29_gated_we = mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_29_gated_we),
+ .wd (mio_pad_sleep_mode_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_30_gated_we;
+ assign mio_pad_sleep_mode_30_gated_we = mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_30_gated_we),
+ .wd (mio_pad_sleep_mode_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_31_gated_we;
+ assign mio_pad_sleep_mode_31_gated_we = mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_31_gated_we),
+ .wd (mio_pad_sleep_mode_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_32_gated_we;
+ assign mio_pad_sleep_mode_32_gated_we = mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_32_gated_we),
+ .wd (mio_pad_sleep_mode_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_33_gated_we;
+ assign mio_pad_sleep_mode_33_gated_we = mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_33_gated_we),
+ .wd (mio_pad_sleep_mode_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_34_gated_we;
+ assign mio_pad_sleep_mode_34_gated_we = mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_34_gated_we),
+ .wd (mio_pad_sleep_mode_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_35_gated_we;
+ assign mio_pad_sleep_mode_35_gated_we = mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_35_gated_we),
+ .wd (mio_pad_sleep_mode_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_36_gated_we;
+ assign mio_pad_sleep_mode_36_gated_we = mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_36_gated_we),
+ .wd (mio_pad_sleep_mode_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_37_gated_we;
+ assign mio_pad_sleep_mode_37_gated_we = mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_37_gated_we),
+ .wd (mio_pad_sleep_mode_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_38_gated_we;
+ assign mio_pad_sleep_mode_38_gated_we = mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_38_gated_we),
+ .wd (mio_pad_sleep_mode_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_39_gated_we;
+ assign mio_pad_sleep_mode_39_gated_we = mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_39_gated_we),
+ .wd (mio_pad_sleep_mode_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_40_gated_we;
+ assign mio_pad_sleep_mode_40_gated_we = mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_40_gated_we),
+ .wd (mio_pad_sleep_mode_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_41_gated_we;
+ assign mio_pad_sleep_mode_41_gated_we = mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_41_gated_we),
+ .wd (mio_pad_sleep_mode_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_42_gated_we;
+ assign mio_pad_sleep_mode_42_gated_we = mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_42_gated_we),
+ .wd (mio_pad_sleep_mode_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_43_gated_we;
+ assign mio_pad_sleep_mode_43_gated_we = mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_43_gated_we),
+ .wd (mio_pad_sleep_mode_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_44_gated_we;
+ assign mio_pad_sleep_mode_44_gated_we = mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_44_gated_we),
+ .wd (mio_pad_sleep_mode_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_45_gated_we;
+ assign mio_pad_sleep_mode_45_gated_we = mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_45_gated_we),
+ .wd (mio_pad_sleep_mode_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_46_gated_we;
+ assign mio_pad_sleep_mode_46_gated_we = mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_46_gated_we),
+ .wd (mio_pad_sleep_mode_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_47_gated_we;
+ assign mio_pad_sleep_mode_47_gated_we = mio_pad_sleep_mode_47_we & mio_pad_sleep_regwen_47_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_47_gated_we),
+ .wd (mio_pad_sleep_mode_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_48_gated_we;
+ assign mio_pad_sleep_mode_48_gated_we = mio_pad_sleep_mode_48_we & mio_pad_sleep_regwen_48_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_48_gated_we),
+ .wd (mio_pad_sleep_mode_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_49_gated_we;
+ assign mio_pad_sleep_mode_49_gated_we = mio_pad_sleep_mode_49_we & mio_pad_sleep_regwen_49_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_49_gated_we),
+ .wd (mio_pad_sleep_mode_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_50_gated_we;
+ assign mio_pad_sleep_mode_50_gated_we = mio_pad_sleep_mode_50_we & mio_pad_sleep_regwen_50_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_50_gated_we),
+ .wd (mio_pad_sleep_mode_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_51_gated_we;
+ assign mio_pad_sleep_mode_51_gated_we = mio_pad_sleep_mode_51_we & mio_pad_sleep_regwen_51_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_51_gated_we),
+ .wd (mio_pad_sleep_mode_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg mio_pad_sleep_mode
+ // R[mio_pad_sleep_mode_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic mio_pad_sleep_mode_52_gated_we;
+ assign mio_pad_sleep_mode_52_gated_we = mio_pad_sleep_mode_52_we & mio_pad_sleep_regwen_52_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_mio_pad_sleep_mode_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (mio_pad_sleep_mode_52_gated_we),
+ .wd (mio_pad_sleep_mode_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_pad_sleep_mode[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (mio_pad_sleep_mode_52_qs)
+ );
+
+
+ // Subregister 0 of Multireg dio_pad_sleep_status
+ // R[dio_pad_sleep_status]: V(False)
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[0].de),
+ .d (hw2reg.dio_pad_sleep_status[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_0_qs)
+ );
+
+ // F[en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[1].de),
+ .d (hw2reg.dio_pad_sleep_status[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_1_qs)
+ );
+
+ // F[en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_2_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[2].de),
+ .d (hw2reg.dio_pad_sleep_status[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_2_qs)
+ );
+
+ // F[en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_3_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[3].de),
+ .d (hw2reg.dio_pad_sleep_status[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_3_qs)
+ );
+
+ // F[en_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_4_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[4].de),
+ .d (hw2reg.dio_pad_sleep_status[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_4_qs)
+ );
+
+ // F[en_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_5_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[5].de),
+ .d (hw2reg.dio_pad_sleep_status[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_5_qs)
+ );
+
+ // F[en_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_6_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[6].de),
+ .d (hw2reg.dio_pad_sleep_status[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_6_qs)
+ );
+
+ // F[en_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_7_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[7].de),
+ .d (hw2reg.dio_pad_sleep_status[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_7_qs)
+ );
+
+ // F[en_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_8_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[8].de),
+ .d (hw2reg.dio_pad_sleep_status[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_8_qs)
+ );
+
+ // F[en_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_9_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[9].de),
+ .d (hw2reg.dio_pad_sleep_status[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_9_qs)
+ );
+
+ // F[en_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_10_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[10].de),
+ .d (hw2reg.dio_pad_sleep_status[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_10_qs)
+ );
+
+ // F[en_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_11_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[11].de),
+ .d (hw2reg.dio_pad_sleep_status[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_11_qs)
+ );
+
+ // F[en_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_12_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[12].de),
+ .d (hw2reg.dio_pad_sleep_status[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_12_qs)
+ );
+
+ // F[en_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_13_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[13].de),
+ .d (hw2reg.dio_pad_sleep_status[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_13_qs)
+ );
+
+ // F[en_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_14_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[14].de),
+ .d (hw2reg.dio_pad_sleep_status[14].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_14_qs)
+ );
+
+ // F[en_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_status_en_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_status_we),
+ .wd (dio_pad_sleep_status_en_15_wd),
+
+ // from internal hardware
+ .de (hw2reg.dio_pad_sleep_status[15].de),
+ .d (hw2reg.dio_pad_sleep_status[15].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_status[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_status_en_15_qs)
+ );
+
+
+ // Subregister 0 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_0_we),
+ .wd (dio_pad_sleep_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_1_we),
+ .wd (dio_pad_sleep_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_2_we),
+ .wd (dio_pad_sleep_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_3_we),
+ .wd (dio_pad_sleep_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_4_we),
+ .wd (dio_pad_sleep_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_5_we),
+ .wd (dio_pad_sleep_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_6_we),
+ .wd (dio_pad_sleep_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_7_we),
+ .wd (dio_pad_sleep_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_8_we),
+ .wd (dio_pad_sleep_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_9_we),
+ .wd (dio_pad_sleep_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_10_we),
+ .wd (dio_pad_sleep_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_11_we),
+ .wd (dio_pad_sleep_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_12_we),
+ .wd (dio_pad_sleep_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_13_we),
+ .wd (dio_pad_sleep_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_14_we),
+ .wd (dio_pad_sleep_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg dio_pad_sleep_regwen
+ // R[dio_pad_sleep_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_dio_pad_sleep_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_regwen_15_we),
+ .wd (dio_pad_sleep_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_regwen_15_qs)
+ );
+
+
+ // Subregister 0 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_0_gated_we;
+ assign dio_pad_sleep_en_0_gated_we = dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_0_gated_we),
+ .wd (dio_pad_sleep_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_1_gated_we;
+ assign dio_pad_sleep_en_1_gated_we = dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_1_gated_we),
+ .wd (dio_pad_sleep_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_2_gated_we;
+ assign dio_pad_sleep_en_2_gated_we = dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_2_gated_we),
+ .wd (dio_pad_sleep_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_3_gated_we;
+ assign dio_pad_sleep_en_3_gated_we = dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_3_gated_we),
+ .wd (dio_pad_sleep_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_4_gated_we;
+ assign dio_pad_sleep_en_4_gated_we = dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_4_gated_we),
+ .wd (dio_pad_sleep_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_5_gated_we;
+ assign dio_pad_sleep_en_5_gated_we = dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_5_gated_we),
+ .wd (dio_pad_sleep_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_6_gated_we;
+ assign dio_pad_sleep_en_6_gated_we = dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_6_gated_we),
+ .wd (dio_pad_sleep_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_7_gated_we;
+ assign dio_pad_sleep_en_7_gated_we = dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_7_gated_we),
+ .wd (dio_pad_sleep_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_8_gated_we;
+ assign dio_pad_sleep_en_8_gated_we = dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_8_gated_we),
+ .wd (dio_pad_sleep_en_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_9_gated_we;
+ assign dio_pad_sleep_en_9_gated_we = dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_9_gated_we),
+ .wd (dio_pad_sleep_en_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_10_gated_we;
+ assign dio_pad_sleep_en_10_gated_we = dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_10_gated_we),
+ .wd (dio_pad_sleep_en_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_11_gated_we;
+ assign dio_pad_sleep_en_11_gated_we = dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_11_gated_we),
+ .wd (dio_pad_sleep_en_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_12_gated_we;
+ assign dio_pad_sleep_en_12_gated_we = dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_12_gated_we),
+ .wd (dio_pad_sleep_en_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_13_gated_we;
+ assign dio_pad_sleep_en_13_gated_we = dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_13_gated_we),
+ .wd (dio_pad_sleep_en_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_14_gated_we;
+ assign dio_pad_sleep_en_14_gated_we = dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_14_gated_we),
+ .wd (dio_pad_sleep_en_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg dio_pad_sleep_en
+ // R[dio_pad_sleep_en_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_en_15_gated_we;
+ assign dio_pad_sleep_en_15_gated_we = dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_dio_pad_sleep_en_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_en_15_gated_we),
+ .wd (dio_pad_sleep_en_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_en[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_en_15_qs)
+ );
+
+
+ // Subregister 0 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_0_gated_we;
+ assign dio_pad_sleep_mode_0_gated_we = dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_0_gated_we),
+ .wd (dio_pad_sleep_mode_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_1_gated_we;
+ assign dio_pad_sleep_mode_1_gated_we = dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_1_gated_we),
+ .wd (dio_pad_sleep_mode_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_2_gated_we;
+ assign dio_pad_sleep_mode_2_gated_we = dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_2_gated_we),
+ .wd (dio_pad_sleep_mode_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_3_gated_we;
+ assign dio_pad_sleep_mode_3_gated_we = dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_3_gated_we),
+ .wd (dio_pad_sleep_mode_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_4_gated_we;
+ assign dio_pad_sleep_mode_4_gated_we = dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_4_gated_we),
+ .wd (dio_pad_sleep_mode_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_5_gated_we;
+ assign dio_pad_sleep_mode_5_gated_we = dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_5_gated_we),
+ .wd (dio_pad_sleep_mode_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_6_gated_we;
+ assign dio_pad_sleep_mode_6_gated_we = dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_6_gated_we),
+ .wd (dio_pad_sleep_mode_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_7_gated_we;
+ assign dio_pad_sleep_mode_7_gated_we = dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_7_gated_we),
+ .wd (dio_pad_sleep_mode_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_8_gated_we;
+ assign dio_pad_sleep_mode_8_gated_we = dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_8_gated_we),
+ .wd (dio_pad_sleep_mode_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_9_gated_we;
+ assign dio_pad_sleep_mode_9_gated_we = dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_9_gated_we),
+ .wd (dio_pad_sleep_mode_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_10_gated_we;
+ assign dio_pad_sleep_mode_10_gated_we = dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_10_gated_we),
+ .wd (dio_pad_sleep_mode_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_11_gated_we;
+ assign dio_pad_sleep_mode_11_gated_we = dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_11_gated_we),
+ .wd (dio_pad_sleep_mode_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_12_gated_we;
+ assign dio_pad_sleep_mode_12_gated_we = dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_12_gated_we),
+ .wd (dio_pad_sleep_mode_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_13_gated_we;
+ assign dio_pad_sleep_mode_13_gated_we = dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_13_gated_we),
+ .wd (dio_pad_sleep_mode_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_14_gated_we;
+ assign dio_pad_sleep_mode_14_gated_we = dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_14_gated_we),
+ .wd (dio_pad_sleep_mode_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg dio_pad_sleep_mode
+ // R[dio_pad_sleep_mode_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic dio_pad_sleep_mode_15_gated_we;
+ assign dio_pad_sleep_mode_15_gated_we = dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs;
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_dio_pad_sleep_mode_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (dio_pad_sleep_mode_15_gated_we),
+ .wd (dio_pad_sleep_mode_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.dio_pad_sleep_mode[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (dio_pad_sleep_mode_15_qs)
+ );
+
+
+ // Subregister 0 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_0_we),
+ .wd (wkup_detector_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_1_we),
+ .wd (wkup_detector_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_2_we),
+ .wd (wkup_detector_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_3_we),
+ .wd (wkup_detector_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_4_we),
+ .wd (wkup_detector_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_5_we),
+ .wd (wkup_detector_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_6_we),
+ .wd (wkup_detector_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg wkup_detector_regwen
+ // R[wkup_detector_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wkup_detector_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_regwen_7_we),
+ .wd (wkup_detector_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_regwen_7_qs)
+ );
+
+
+ // Subregister 0 of Multireg wkup_detector_en
+ // R[wkup_detector_en_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_0_gated_we;
+ assign aon_wkup_detector_en_0_gated_we =
+ aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_0_gated_we),
+ .wd (aon_wkup_detector_en_0_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_0_qs_int)
+ );
+
+
+ // Subregister 1 of Multireg wkup_detector_en
+ // R[wkup_detector_en_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_1_gated_we;
+ assign aon_wkup_detector_en_1_gated_we =
+ aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_1_gated_we),
+ .wd (aon_wkup_detector_en_1_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_1_qs_int)
+ );
+
+
+ // Subregister 2 of Multireg wkup_detector_en
+ // R[wkup_detector_en_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_2_gated_we;
+ assign aon_wkup_detector_en_2_gated_we =
+ aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_2_gated_we),
+ .wd (aon_wkup_detector_en_2_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_2_qs_int)
+ );
+
+
+ // Subregister 3 of Multireg wkup_detector_en
+ // R[wkup_detector_en_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_3_gated_we;
+ assign aon_wkup_detector_en_3_gated_we =
+ aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_3_gated_we),
+ .wd (aon_wkup_detector_en_3_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_3_qs_int)
+ );
+
+
+ // Subregister 4 of Multireg wkup_detector_en
+ // R[wkup_detector_en_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_4_gated_we;
+ assign aon_wkup_detector_en_4_gated_we =
+ aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_4_gated_we),
+ .wd (aon_wkup_detector_en_4_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_4_qs_int)
+ );
+
+
+ // Subregister 5 of Multireg wkup_detector_en
+ // R[wkup_detector_en_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_5_gated_we;
+ assign aon_wkup_detector_en_5_gated_we =
+ aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_5_gated_we),
+ .wd (aon_wkup_detector_en_5_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_5_qs_int)
+ );
+
+
+ // Subregister 6 of Multireg wkup_detector_en
+ // R[wkup_detector_en_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_6_gated_we;
+ assign aon_wkup_detector_en_6_gated_we =
+ aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_6_gated_we),
+ .wd (aon_wkup_detector_en_6_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_6_qs_int)
+ );
+
+
+ // Subregister 7 of Multireg wkup_detector_en
+ // R[wkup_detector_en_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_en_7_gated_we;
+ assign aon_wkup_detector_en_7_gated_we =
+ aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_en_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_en_7_gated_we),
+ .wd (aon_wkup_detector_en_7_wdata[0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_en[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_en_7_qs_int)
+ );
+
+
+ // Subregister 0 of Multireg wkup_detector
+ // R[wkup_detector_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_0_gated_we;
+ assign aon_wkup_detector_0_gated_we = aon_wkup_detector_0_we & aon_wkup_detector_0_regwen;
+ // F[mode_0]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_0_mode_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_0_gated_we),
+ .wd (aon_wkup_detector_0_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[0].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_0_mode_0_qs_int)
+ );
+
+ // F[filter_0]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_0_filter_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_0_gated_we),
+ .wd (aon_wkup_detector_0_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[0].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_0_filter_0_qs_int)
+ );
+
+ // F[miodio_0]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_0_miodio_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_0_gated_we),
+ .wd (aon_wkup_detector_0_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[0].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_0_miodio_0_qs_int)
+ );
+
+
+ // Subregister 1 of Multireg wkup_detector
+ // R[wkup_detector_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_1_gated_we;
+ assign aon_wkup_detector_1_gated_we = aon_wkup_detector_1_we & aon_wkup_detector_1_regwen;
+ // F[mode_1]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_1_mode_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_1_gated_we),
+ .wd (aon_wkup_detector_1_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[1].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_1_mode_1_qs_int)
+ );
+
+ // F[filter_1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_1_filter_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_1_gated_we),
+ .wd (aon_wkup_detector_1_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[1].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_1_filter_1_qs_int)
+ );
+
+ // F[miodio_1]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_1_miodio_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_1_gated_we),
+ .wd (aon_wkup_detector_1_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[1].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_1_miodio_1_qs_int)
+ );
+
+
+ // Subregister 2 of Multireg wkup_detector
+ // R[wkup_detector_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_2_gated_we;
+ assign aon_wkup_detector_2_gated_we = aon_wkup_detector_2_we & aon_wkup_detector_2_regwen;
+ // F[mode_2]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_2_mode_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_2_gated_we),
+ .wd (aon_wkup_detector_2_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[2].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_2_mode_2_qs_int)
+ );
+
+ // F[filter_2]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_2_filter_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_2_gated_we),
+ .wd (aon_wkup_detector_2_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[2].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_2_filter_2_qs_int)
+ );
+
+ // F[miodio_2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_2_miodio_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_2_gated_we),
+ .wd (aon_wkup_detector_2_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[2].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_2_miodio_2_qs_int)
+ );
+
+
+ // Subregister 3 of Multireg wkup_detector
+ // R[wkup_detector_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_3_gated_we;
+ assign aon_wkup_detector_3_gated_we = aon_wkup_detector_3_we & aon_wkup_detector_3_regwen;
+ // F[mode_3]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_3_mode_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_3_gated_we),
+ .wd (aon_wkup_detector_3_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[3].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_3_mode_3_qs_int)
+ );
+
+ // F[filter_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_3_filter_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_3_gated_we),
+ .wd (aon_wkup_detector_3_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[3].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_3_filter_3_qs_int)
+ );
+
+ // F[miodio_3]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_3_miodio_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_3_gated_we),
+ .wd (aon_wkup_detector_3_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[3].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_3_miodio_3_qs_int)
+ );
+
+
+ // Subregister 4 of Multireg wkup_detector
+ // R[wkup_detector_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_4_gated_we;
+ assign aon_wkup_detector_4_gated_we = aon_wkup_detector_4_we & aon_wkup_detector_4_regwen;
+ // F[mode_4]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_4_mode_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_4_gated_we),
+ .wd (aon_wkup_detector_4_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[4].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_4_mode_4_qs_int)
+ );
+
+ // F[filter_4]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_4_filter_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_4_gated_we),
+ .wd (aon_wkup_detector_4_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[4].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_4_filter_4_qs_int)
+ );
+
+ // F[miodio_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_4_miodio_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_4_gated_we),
+ .wd (aon_wkup_detector_4_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[4].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_4_miodio_4_qs_int)
+ );
+
+
+ // Subregister 5 of Multireg wkup_detector
+ // R[wkup_detector_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_5_gated_we;
+ assign aon_wkup_detector_5_gated_we = aon_wkup_detector_5_we & aon_wkup_detector_5_regwen;
+ // F[mode_5]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_5_mode_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_5_gated_we),
+ .wd (aon_wkup_detector_5_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[5].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_5_mode_5_qs_int)
+ );
+
+ // F[filter_5]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_5_filter_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_5_gated_we),
+ .wd (aon_wkup_detector_5_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[5].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_5_filter_5_qs_int)
+ );
+
+ // F[miodio_5]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_5_miodio_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_5_gated_we),
+ .wd (aon_wkup_detector_5_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[5].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_5_miodio_5_qs_int)
+ );
+
+
+ // Subregister 6 of Multireg wkup_detector
+ // R[wkup_detector_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_6_gated_we;
+ assign aon_wkup_detector_6_gated_we = aon_wkup_detector_6_we & aon_wkup_detector_6_regwen;
+ // F[mode_6]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_6_mode_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_6_gated_we),
+ .wd (aon_wkup_detector_6_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[6].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_6_mode_6_qs_int)
+ );
+
+ // F[filter_6]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_6_filter_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_6_gated_we),
+ .wd (aon_wkup_detector_6_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[6].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_6_filter_6_qs_int)
+ );
+
+ // F[miodio_6]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_6_miodio_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_6_gated_we),
+ .wd (aon_wkup_detector_6_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[6].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_6_miodio_6_qs_int)
+ );
+
+
+ // Subregister 7 of Multireg wkup_detector
+ // R[wkup_detector_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_7_gated_we;
+ assign aon_wkup_detector_7_gated_we = aon_wkup_detector_7_we & aon_wkup_detector_7_regwen;
+ // F[mode_7]: 2:0
+ prim_subreg #(
+ .DW (3),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (3'h0)
+ ) u_wkup_detector_7_mode_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_7_gated_we),
+ .wd (aon_wkup_detector_7_wdata[2:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[7].mode.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_7_mode_7_qs_int)
+ );
+
+ // F[filter_7]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_7_filter_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_7_gated_we),
+ .wd (aon_wkup_detector_7_wdata[3]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[7].filter.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_7_filter_7_qs_int)
+ );
+
+ // F[miodio_7]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wkup_detector_7_miodio_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_7_gated_we),
+ .wd (aon_wkup_detector_7_wdata[4]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector[7].miodio.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_7_miodio_7_qs_int)
+ );
+
+
+ // Subregister 0 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_0_gated_we;
+ assign aon_wkup_detector_cnt_th_0_gated_we =
+ aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_0_gated_we),
+ .wd (aon_wkup_detector_cnt_th_0_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_0_qs_int)
+ );
+
+
+ // Subregister 1 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_1_gated_we;
+ assign aon_wkup_detector_cnt_th_1_gated_we =
+ aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_1_gated_we),
+ .wd (aon_wkup_detector_cnt_th_1_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_1_qs_int)
+ );
+
+
+ // Subregister 2 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_2_gated_we;
+ assign aon_wkup_detector_cnt_th_2_gated_we =
+ aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_2_gated_we),
+ .wd (aon_wkup_detector_cnt_th_2_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_2_qs_int)
+ );
+
+
+ // Subregister 3 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_3_gated_we;
+ assign aon_wkup_detector_cnt_th_3_gated_we =
+ aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_3_gated_we),
+ .wd (aon_wkup_detector_cnt_th_3_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_3_qs_int)
+ );
+
+
+ // Subregister 4 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_4_gated_we;
+ assign aon_wkup_detector_cnt_th_4_gated_we =
+ aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_4_gated_we),
+ .wd (aon_wkup_detector_cnt_th_4_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_4_qs_int)
+ );
+
+
+ // Subregister 5 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_5_gated_we;
+ assign aon_wkup_detector_cnt_th_5_gated_we =
+ aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_5_gated_we),
+ .wd (aon_wkup_detector_cnt_th_5_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_5_qs_int)
+ );
+
+
+ // Subregister 6 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_6_gated_we;
+ assign aon_wkup_detector_cnt_th_6_gated_we =
+ aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_6_gated_we),
+ .wd (aon_wkup_detector_cnt_th_6_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_6_qs_int)
+ );
+
+
+ // Subregister 7 of Multireg wkup_detector_cnt_th
+ // R[wkup_detector_cnt_th_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic aon_wkup_detector_cnt_th_7_gated_we;
+ assign aon_wkup_detector_cnt_th_7_gated_we =
+ aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen;
+ prim_subreg #(
+ .DW (8),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (8'h0)
+ ) u_wkup_detector_cnt_th_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_detector_cnt_th_7_gated_we),
+ .wd (aon_wkup_detector_cnt_th_7_wdata[7:0]),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_cnt_th[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (aon_wkup_detector_cnt_th_7_qs_int)
+ );
+
+
+ // Subregister 0 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_0_gated_we;
+ assign wkup_detector_padsel_0_gated_we = wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_0_gated_we),
+ .wd (wkup_detector_padsel_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_1_gated_we;
+ assign wkup_detector_padsel_1_gated_we = wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_1_gated_we),
+ .wd (wkup_detector_padsel_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_2_gated_we;
+ assign wkup_detector_padsel_2_gated_we = wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_2_gated_we),
+ .wd (wkup_detector_padsel_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_3_gated_we;
+ assign wkup_detector_padsel_3_gated_we = wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_3_gated_we),
+ .wd (wkup_detector_padsel_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_4_gated_we;
+ assign wkup_detector_padsel_4_gated_we = wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_4_gated_we),
+ .wd (wkup_detector_padsel_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_5_gated_we;
+ assign wkup_detector_padsel_5_gated_we = wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_5_gated_we),
+ .wd (wkup_detector_padsel_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_6_gated_we;
+ assign wkup_detector_padsel_6_gated_we = wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_6_gated_we),
+ .wd (wkup_detector_padsel_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg wkup_detector_padsel
+ // R[wkup_detector_padsel_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wkup_detector_padsel_7_gated_we;
+ assign wkup_detector_padsel_7_gated_we = wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs;
+ prim_subreg #(
+ .DW (6),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (6'h0)
+ ) u_wkup_detector_padsel_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wkup_detector_padsel_7_gated_we),
+ .wd (wkup_detector_padsel_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wkup_detector_padsel[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wkup_detector_padsel_7_qs)
+ );
+
+
+ // Subregister 0 of Multireg wkup_cause
+ // R[wkup_cause]: V(False)
+ logic [7:0] wkup_cause_flds_we;
+ assign aon_wkup_cause_qe = |wkup_cause_flds_we;
+ // F[cause_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_0 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[0]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[0].de),
+ .d (hw2reg.wkup_cause[0].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[0]),
+ .q (reg2hw.wkup_cause[0].q),
+ .ds (aon_wkup_cause_cause_0_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_0_qs_int)
+ );
+
+ // F[cause_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_1 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[1]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[1].de),
+ .d (hw2reg.wkup_cause[1].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[1]),
+ .q (reg2hw.wkup_cause[1].q),
+ .ds (aon_wkup_cause_cause_1_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_1_qs_int)
+ );
+
+ // F[cause_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_2 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[2]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[2].de),
+ .d (hw2reg.wkup_cause[2].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[2]),
+ .q (reg2hw.wkup_cause[2].q),
+ .ds (aon_wkup_cause_cause_2_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_2_qs_int)
+ );
+
+ // F[cause_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_3 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[3]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[3].de),
+ .d (hw2reg.wkup_cause[3].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[3]),
+ .q (reg2hw.wkup_cause[3].q),
+ .ds (aon_wkup_cause_cause_3_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_3_qs_int)
+ );
+
+ // F[cause_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_4 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[4]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[4].de),
+ .d (hw2reg.wkup_cause[4].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[4]),
+ .q (reg2hw.wkup_cause[4].q),
+ .ds (aon_wkup_cause_cause_4_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_4_qs_int)
+ );
+
+ // F[cause_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_5 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[5]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[5].de),
+ .d (hw2reg.wkup_cause[5].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[5]),
+ .q (reg2hw.wkup_cause[5].q),
+ .ds (aon_wkup_cause_cause_5_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_5_qs_int)
+ );
+
+ // F[cause_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_6 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[6]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[6].de),
+ .d (hw2reg.wkup_cause[6].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[6]),
+ .q (reg2hw.wkup_cause[6].q),
+ .ds (aon_wkup_cause_cause_6_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_6_qs_int)
+ );
+
+ // F[cause_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h0)
+ ) u_wkup_cause_cause_7 (
+ .clk_i (clk_aon_i),
+ .rst_ni (rst_aon_ni),
+
+ // from register interface
+ .we (aon_wkup_cause_we),
+ .wd (aon_wkup_cause_wdata[7]),
+
+ // from internal hardware
+ .de (hw2reg.wkup_cause[7].de),
+ .d (hw2reg.wkup_cause[7].d),
+
+ // to internal hardware
+ .qe (wkup_cause_flds_we[7]),
+ .q (reg2hw.wkup_cause[7].q),
+ .ds (aon_wkup_cause_cause_7_ds_int),
+
+ // to register interface (read)
+ .qs (aon_wkup_cause_cause_7_qs_int)
+ );
+
+
+
+ logic [647:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET);
+ addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
+ addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
+ addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
+ addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
+ addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
+ addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
+ addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
+ addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
+ addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
+ addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
+ addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
+ addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
+ addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
+ addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
+ addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
+ addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
+ addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
+ addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
+ addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
+ addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
+ addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
+ addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
+ addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
+ addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
+ addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
+ addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
+ addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
+ addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
+ addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
+ addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
+ addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
+ addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
+ addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
+ addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET);
+ addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET);
+ addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET);
+ addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET);
+ addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET);
+ addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET);
+ addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET);
+ addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET);
+ addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET);
+ addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET);
+ addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET);
+ addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET);
+ addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET);
+ addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET);
+ addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET);
+ addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET);
+ addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET);
+ addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET);
+ addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET);
+ addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET);
+ addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET);
+ addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET);
+ addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET);
+ addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET);
+ addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_57_OFFSET);
+ addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_58_OFFSET);
+ addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_59_OFFSET);
+ addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_60_OFFSET);
+ addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_61_OFFSET);
+ addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_62_OFFSET);
+ addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_63_OFFSET);
+ addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_64_OFFSET);
+ addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_65_OFFSET);
+ addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_66_OFFSET);
+ addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_67_OFFSET);
+ addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_68_OFFSET);
+ addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_69_OFFSET);
+ addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_70_OFFSET);
+ addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_71_OFFSET);
+ addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_72_OFFSET);
+ addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_73_OFFSET);
+ addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_74_OFFSET);
+ addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_75_OFFSET);
+ addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
+ addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
+ addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
+ addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
+ addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
+ addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
+ addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
+ addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
+ addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
+ addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
+ addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
+ addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
+ addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
+ addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
+ addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
+ addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
+ addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
+ addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
+ addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
+ addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
+ addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
+ addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
+ addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
+ addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
+ addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
+ addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
+ addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
+ addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
+ addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
+ addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
+ addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
+ addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
+ addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
+ addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
+ addr_hit[111] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
+ addr_hit[112] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
+ addr_hit[113] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
+ addr_hit[114] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
+ addr_hit[115] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
+ addr_hit[116] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
+ addr_hit[117] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
+ addr_hit[118] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET);
+ addr_hit[119] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET);
+ addr_hit[120] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET);
+ addr_hit[121] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET);
+ addr_hit[122] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET);
+ addr_hit[123] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET);
+ addr_hit[124] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET);
+ addr_hit[125] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET);
+ addr_hit[126] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET);
+ addr_hit[127] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET);
+ addr_hit[128] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET);
+ addr_hit[129] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET);
+ addr_hit[130] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET);
+ addr_hit[131] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET);
+ addr_hit[132] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_55_OFFSET);
+ addr_hit[133] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_56_OFFSET);
+ addr_hit[134] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_57_OFFSET);
+ addr_hit[135] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_58_OFFSET);
+ addr_hit[136] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_59_OFFSET);
+ addr_hit[137] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_60_OFFSET);
+ addr_hit[138] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_61_OFFSET);
+ addr_hit[139] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_62_OFFSET);
+ addr_hit[140] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_63_OFFSET);
+ addr_hit[141] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_64_OFFSET);
+ addr_hit[142] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_65_OFFSET);
+ addr_hit[143] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_66_OFFSET);
+ addr_hit[144] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_67_OFFSET);
+ addr_hit[145] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_68_OFFSET);
+ addr_hit[146] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_69_OFFSET);
+ addr_hit[147] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_70_OFFSET);
+ addr_hit[148] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_71_OFFSET);
+ addr_hit[149] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_72_OFFSET);
+ addr_hit[150] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_73_OFFSET);
+ addr_hit[151] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_74_OFFSET);
+ addr_hit[152] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_75_OFFSET);
+ addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
+ addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
+ addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
+ addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
+ addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
+ addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
+ addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
+ addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
+ addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
+ addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
+ addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
+ addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
+ addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
+ addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
+ addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
+ addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
+ addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
+ addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
+ addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
+ addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
+ addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
+ addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
+ addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
+ addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
+ addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
+ addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
+ addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
+ addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
+ addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
+ addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
+ addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
+ addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
+ addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET);
+ addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET);
+ addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET);
+ addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET);
+ addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET);
+ addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET);
+ addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET);
+ addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET);
+ addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET);
+ addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET);
+ addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET);
+ addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET);
+ addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET);
+ addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET);
+ addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET);
+ addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_47_OFFSET);
+ addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_48_OFFSET);
+ addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_49_OFFSET);
+ addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_50_OFFSET);
+ addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_51_OFFSET);
+ addr_hit[205] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_52_OFFSET);
+ addr_hit[206] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
+ addr_hit[207] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
+ addr_hit[208] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
+ addr_hit[209] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
+ addr_hit[210] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
+ addr_hit[211] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
+ addr_hit[212] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
+ addr_hit[213] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
+ addr_hit[214] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
+ addr_hit[215] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
+ addr_hit[216] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
+ addr_hit[217] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
+ addr_hit[218] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
+ addr_hit[219] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
+ addr_hit[220] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
+ addr_hit[221] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
+ addr_hit[222] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
+ addr_hit[223] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
+ addr_hit[224] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
+ addr_hit[225] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
+ addr_hit[226] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
+ addr_hit[227] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
+ addr_hit[228] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
+ addr_hit[229] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
+ addr_hit[230] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
+ addr_hit[231] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
+ addr_hit[232] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
+ addr_hit[233] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
+ addr_hit[234] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
+ addr_hit[235] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
+ addr_hit[236] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
+ addr_hit[237] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
+ addr_hit[238] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
+ addr_hit[239] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
+ addr_hit[240] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
+ addr_hit[241] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
+ addr_hit[242] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
+ addr_hit[243] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
+ addr_hit[244] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
+ addr_hit[245] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
+ addr_hit[246] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
+ addr_hit[247] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
+ addr_hit[248] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
+ addr_hit[249] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET);
+ addr_hit[250] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET);
+ addr_hit[251] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET);
+ addr_hit[252] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET);
+ addr_hit[253] = (reg_addr == PINMUX_MIO_OUTSEL_47_OFFSET);
+ addr_hit[254] = (reg_addr == PINMUX_MIO_OUTSEL_48_OFFSET);
+ addr_hit[255] = (reg_addr == PINMUX_MIO_OUTSEL_49_OFFSET);
+ addr_hit[256] = (reg_addr == PINMUX_MIO_OUTSEL_50_OFFSET);
+ addr_hit[257] = (reg_addr == PINMUX_MIO_OUTSEL_51_OFFSET);
+ addr_hit[258] = (reg_addr == PINMUX_MIO_OUTSEL_52_OFFSET);
+ addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
+ addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
+ addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
+ addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
+ addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
+ addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
+ addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
+ addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
+ addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
+ addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
+ addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
+ addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
+ addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
+ addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
+ addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
+ addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
+ addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
+ addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
+ addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
+ addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
+ addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
+ addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
+ addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
+ addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
+ addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
+ addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
+ addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
+ addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET);
+ addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET);
+ addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET);
+ addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET);
+ addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_47_OFFSET);
+ addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_48_OFFSET);
+ addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_49_OFFSET);
+ addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_50_OFFSET);
+ addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_51_OFFSET);
+ addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_52_OFFSET);
+ addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
+ addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
+ addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
+ addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
+ addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
+ addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
+ addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
+ addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
+ addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
+ addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
+ addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
+ addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
+ addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
+ addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
+ addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
+ addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
+ addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
+ addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
+ addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
+ addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
+ addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
+ addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
+ addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
+ addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
+ addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
+ addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
+ addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
+ addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
+ addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
+ addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
+ addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
+ addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
+ addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
+ addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
+ addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
+ addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
+ addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
+ addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
+ addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
+ addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
+ addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
+ addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
+ addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
+ addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET);
+ addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET);
+ addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET);
+ addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET);
+ addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_ATTR_47_OFFSET);
+ addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_ATTR_48_OFFSET);
+ addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_ATTR_49_OFFSET);
+ addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_ATTR_50_OFFSET);
+ addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_ATTR_51_OFFSET);
+ addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_ATTR_52_OFFSET);
+ addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
+ addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
+ addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
+ addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
+ addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
+ addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
+ addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
+ addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
+ addr_hit[389] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
+ addr_hit[390] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
+ addr_hit[391] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
+ addr_hit[392] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
+ addr_hit[393] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
+ addr_hit[394] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
+ addr_hit[395] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
+ addr_hit[396] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
+ addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
+ addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
+ addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
+ addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
+ addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
+ addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
+ addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
+ addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
+ addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
+ addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
+ addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
+ addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
+ addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
+ addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
+ addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
+ addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
+ addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
+ addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
+ addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
+ addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
+ addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
+ addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
+ addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
+ addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
+ addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
+ addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
+ addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
+ addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
+ addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
+ addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET);
+ addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET);
+ addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET);
+ addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET);
+ addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_47_OFFSET);
+ addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_48_OFFSET);
+ addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_49_OFFSET);
+ addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_50_OFFSET);
+ addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_51_OFFSET);
+ addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_52_OFFSET);
+ addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
+ addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
+ addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
+ addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
+ addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
+ addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
+ addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
+ addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
+ addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
+ addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
+ addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
+ addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
+ addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
+ addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
+ addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
+ addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
+ addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
+ addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
+ addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
+ addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
+ addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
+ addr_hit[489] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
+ addr_hit[490] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
+ addr_hit[491] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
+ addr_hit[492] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
+ addr_hit[493] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
+ addr_hit[494] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
+ addr_hit[495] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET);
+ addr_hit[496] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET);
+ addr_hit[497] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET);
+ addr_hit[498] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET);
+ addr_hit[499] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_47_OFFSET);
+ addr_hit[500] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_48_OFFSET);
+ addr_hit[501] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_49_OFFSET);
+ addr_hit[502] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_50_OFFSET);
+ addr_hit[503] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_51_OFFSET);
+ addr_hit[504] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_52_OFFSET);
+ addr_hit[505] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[506] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[507] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[508] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[509] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[510] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[511] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[512] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[513] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[514] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[515] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[516] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[517] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[518] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[519] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[520] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[521] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
+ addr_hit[522] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
+ addr_hit[523] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
+ addr_hit[524] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
+ addr_hit[525] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
+ addr_hit[526] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
+ addr_hit[527] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
+ addr_hit[528] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
+ addr_hit[529] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
+ addr_hit[530] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
+ addr_hit[531] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
+ addr_hit[532] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
+ addr_hit[533] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
+ addr_hit[534] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
+ addr_hit[535] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
+ addr_hit[536] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
+ addr_hit[537] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
+ addr_hit[538] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
+ addr_hit[539] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
+ addr_hit[540] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
+ addr_hit[541] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
+ addr_hit[542] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
+ addr_hit[543] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
+ addr_hit[544] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
+ addr_hit[545] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
+ addr_hit[546] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
+ addr_hit[547] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
+ addr_hit[548] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET);
+ addr_hit[549] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET);
+ addr_hit[550] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET);
+ addr_hit[551] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET);
+ addr_hit[552] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_47_OFFSET);
+ addr_hit[553] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_48_OFFSET);
+ addr_hit[554] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_49_OFFSET);
+ addr_hit[555] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_50_OFFSET);
+ addr_hit[556] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_51_OFFSET);
+ addr_hit[557] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_52_OFFSET);
+ addr_hit[558] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
+ addr_hit[559] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[560] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[561] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[562] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[563] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[564] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[565] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[566] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[567] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[568] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[569] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[570] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[571] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[572] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[573] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[574] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[575] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[576] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[577] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[578] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[579] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[580] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[581] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[582] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[583] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[584] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[585] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[586] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[587] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[588] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[589] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[590] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[591] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[592] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[593] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[594] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[595] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[596] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[597] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[598] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[599] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[600] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[601] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[602] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[603] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[604] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[605] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[606] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[607] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
+ addr_hit[608] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
+ addr_hit[609] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
+ addr_hit[610] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
+ addr_hit[611] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
+ addr_hit[612] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
+ addr_hit[613] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
+ addr_hit[614] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
+ addr_hit[615] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
+ addr_hit[616] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
+ addr_hit[617] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
+ addr_hit[618] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
+ addr_hit[619] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
+ addr_hit[620] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
+ addr_hit[621] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
+ addr_hit[622] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
+ addr_hit[623] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
+ addr_hit[624] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
+ addr_hit[625] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
+ addr_hit[626] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
+ addr_hit[627] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
+ addr_hit[628] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
+ addr_hit[629] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
+ addr_hit[630] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
+ addr_hit[631] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
+ addr_hit[632] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
+ addr_hit[633] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
+ addr_hit[634] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
+ addr_hit[635] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
+ addr_hit[636] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
+ addr_hit[637] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
+ addr_hit[638] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
+ addr_hit[639] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
+ addr_hit[640] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
+ addr_hit[641] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
+ addr_hit[642] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
+ addr_hit[643] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
+ addr_hit[644] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
+ addr_hit[645] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
+ addr_hit[646] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
+ addr_hit[647] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(PINMUX_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(PINMUX_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(PINMUX_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(PINMUX_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(PINMUX_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(PINMUX_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(PINMUX_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(PINMUX_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(PINMUX_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(PINMUX_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[ 10] & (|(PINMUX_PERMIT[ 10] & ~reg_be))) |
+ (addr_hit[ 11] & (|(PINMUX_PERMIT[ 11] & ~reg_be))) |
+ (addr_hit[ 12] & (|(PINMUX_PERMIT[ 12] & ~reg_be))) |
+ (addr_hit[ 13] & (|(PINMUX_PERMIT[ 13] & ~reg_be))) |
+ (addr_hit[ 14] & (|(PINMUX_PERMIT[ 14] & ~reg_be))) |
+ (addr_hit[ 15] & (|(PINMUX_PERMIT[ 15] & ~reg_be))) |
+ (addr_hit[ 16] & (|(PINMUX_PERMIT[ 16] & ~reg_be))) |
+ (addr_hit[ 17] & (|(PINMUX_PERMIT[ 17] & ~reg_be))) |
+ (addr_hit[ 18] & (|(PINMUX_PERMIT[ 18] & ~reg_be))) |
+ (addr_hit[ 19] & (|(PINMUX_PERMIT[ 19] & ~reg_be))) |
+ (addr_hit[ 20] & (|(PINMUX_PERMIT[ 20] & ~reg_be))) |
+ (addr_hit[ 21] & (|(PINMUX_PERMIT[ 21] & ~reg_be))) |
+ (addr_hit[ 22] & (|(PINMUX_PERMIT[ 22] & ~reg_be))) |
+ (addr_hit[ 23] & (|(PINMUX_PERMIT[ 23] & ~reg_be))) |
+ (addr_hit[ 24] & (|(PINMUX_PERMIT[ 24] & ~reg_be))) |
+ (addr_hit[ 25] & (|(PINMUX_PERMIT[ 25] & ~reg_be))) |
+ (addr_hit[ 26] & (|(PINMUX_PERMIT[ 26] & ~reg_be))) |
+ (addr_hit[ 27] & (|(PINMUX_PERMIT[ 27] & ~reg_be))) |
+ (addr_hit[ 28] & (|(PINMUX_PERMIT[ 28] & ~reg_be))) |
+ (addr_hit[ 29] & (|(PINMUX_PERMIT[ 29] & ~reg_be))) |
+ (addr_hit[ 30] & (|(PINMUX_PERMIT[ 30] & ~reg_be))) |
+ (addr_hit[ 31] & (|(PINMUX_PERMIT[ 31] & ~reg_be))) |
+ (addr_hit[ 32] & (|(PINMUX_PERMIT[ 32] & ~reg_be))) |
+ (addr_hit[ 33] & (|(PINMUX_PERMIT[ 33] & ~reg_be))) |
+ (addr_hit[ 34] & (|(PINMUX_PERMIT[ 34] & ~reg_be))) |
+ (addr_hit[ 35] & (|(PINMUX_PERMIT[ 35] & ~reg_be))) |
+ (addr_hit[ 36] & (|(PINMUX_PERMIT[ 36] & ~reg_be))) |
+ (addr_hit[ 37] & (|(PINMUX_PERMIT[ 37] & ~reg_be))) |
+ (addr_hit[ 38] & (|(PINMUX_PERMIT[ 38] & ~reg_be))) |
+ (addr_hit[ 39] & (|(PINMUX_PERMIT[ 39] & ~reg_be))) |
+ (addr_hit[ 40] & (|(PINMUX_PERMIT[ 40] & ~reg_be))) |
+ (addr_hit[ 41] & (|(PINMUX_PERMIT[ 41] & ~reg_be))) |
+ (addr_hit[ 42] & (|(PINMUX_PERMIT[ 42] & ~reg_be))) |
+ (addr_hit[ 43] & (|(PINMUX_PERMIT[ 43] & ~reg_be))) |
+ (addr_hit[ 44] & (|(PINMUX_PERMIT[ 44] & ~reg_be))) |
+ (addr_hit[ 45] & (|(PINMUX_PERMIT[ 45] & ~reg_be))) |
+ (addr_hit[ 46] & (|(PINMUX_PERMIT[ 46] & ~reg_be))) |
+ (addr_hit[ 47] & (|(PINMUX_PERMIT[ 47] & ~reg_be))) |
+ (addr_hit[ 48] & (|(PINMUX_PERMIT[ 48] & ~reg_be))) |
+ (addr_hit[ 49] & (|(PINMUX_PERMIT[ 49] & ~reg_be))) |
+ (addr_hit[ 50] & (|(PINMUX_PERMIT[ 50] & ~reg_be))) |
+ (addr_hit[ 51] & (|(PINMUX_PERMIT[ 51] & ~reg_be))) |
+ (addr_hit[ 52] & (|(PINMUX_PERMIT[ 52] & ~reg_be))) |
+ (addr_hit[ 53] & (|(PINMUX_PERMIT[ 53] & ~reg_be))) |
+ (addr_hit[ 54] & (|(PINMUX_PERMIT[ 54] & ~reg_be))) |
+ (addr_hit[ 55] & (|(PINMUX_PERMIT[ 55] & ~reg_be))) |
+ (addr_hit[ 56] & (|(PINMUX_PERMIT[ 56] & ~reg_be))) |
+ (addr_hit[ 57] & (|(PINMUX_PERMIT[ 57] & ~reg_be))) |
+ (addr_hit[ 58] & (|(PINMUX_PERMIT[ 58] & ~reg_be))) |
+ (addr_hit[ 59] & (|(PINMUX_PERMIT[ 59] & ~reg_be))) |
+ (addr_hit[ 60] & (|(PINMUX_PERMIT[ 60] & ~reg_be))) |
+ (addr_hit[ 61] & (|(PINMUX_PERMIT[ 61] & ~reg_be))) |
+ (addr_hit[ 62] & (|(PINMUX_PERMIT[ 62] & ~reg_be))) |
+ (addr_hit[ 63] & (|(PINMUX_PERMIT[ 63] & ~reg_be))) |
+ (addr_hit[ 64] & (|(PINMUX_PERMIT[ 64] & ~reg_be))) |
+ (addr_hit[ 65] & (|(PINMUX_PERMIT[ 65] & ~reg_be))) |
+ (addr_hit[ 66] & (|(PINMUX_PERMIT[ 66] & ~reg_be))) |
+ (addr_hit[ 67] & (|(PINMUX_PERMIT[ 67] & ~reg_be))) |
+ (addr_hit[ 68] & (|(PINMUX_PERMIT[ 68] & ~reg_be))) |
+ (addr_hit[ 69] & (|(PINMUX_PERMIT[ 69] & ~reg_be))) |
+ (addr_hit[ 70] & (|(PINMUX_PERMIT[ 70] & ~reg_be))) |
+ (addr_hit[ 71] & (|(PINMUX_PERMIT[ 71] & ~reg_be))) |
+ (addr_hit[ 72] & (|(PINMUX_PERMIT[ 72] & ~reg_be))) |
+ (addr_hit[ 73] & (|(PINMUX_PERMIT[ 73] & ~reg_be))) |
+ (addr_hit[ 74] & (|(PINMUX_PERMIT[ 74] & ~reg_be))) |
+ (addr_hit[ 75] & (|(PINMUX_PERMIT[ 75] & ~reg_be))) |
+ (addr_hit[ 76] & (|(PINMUX_PERMIT[ 76] & ~reg_be))) |
+ (addr_hit[ 77] & (|(PINMUX_PERMIT[ 77] & ~reg_be))) |
+ (addr_hit[ 78] & (|(PINMUX_PERMIT[ 78] & ~reg_be))) |
+ (addr_hit[ 79] & (|(PINMUX_PERMIT[ 79] & ~reg_be))) |
+ (addr_hit[ 80] & (|(PINMUX_PERMIT[ 80] & ~reg_be))) |
+ (addr_hit[ 81] & (|(PINMUX_PERMIT[ 81] & ~reg_be))) |
+ (addr_hit[ 82] & (|(PINMUX_PERMIT[ 82] & ~reg_be))) |
+ (addr_hit[ 83] & (|(PINMUX_PERMIT[ 83] & ~reg_be))) |
+ (addr_hit[ 84] & (|(PINMUX_PERMIT[ 84] & ~reg_be))) |
+ (addr_hit[ 85] & (|(PINMUX_PERMIT[ 85] & ~reg_be))) |
+ (addr_hit[ 86] & (|(PINMUX_PERMIT[ 86] & ~reg_be))) |
+ (addr_hit[ 87] & (|(PINMUX_PERMIT[ 87] & ~reg_be))) |
+ (addr_hit[ 88] & (|(PINMUX_PERMIT[ 88] & ~reg_be))) |
+ (addr_hit[ 89] & (|(PINMUX_PERMIT[ 89] & ~reg_be))) |
+ (addr_hit[ 90] & (|(PINMUX_PERMIT[ 90] & ~reg_be))) |
+ (addr_hit[ 91] & (|(PINMUX_PERMIT[ 91] & ~reg_be))) |
+ (addr_hit[ 92] & (|(PINMUX_PERMIT[ 92] & ~reg_be))) |
+ (addr_hit[ 93] & (|(PINMUX_PERMIT[ 93] & ~reg_be))) |
+ (addr_hit[ 94] & (|(PINMUX_PERMIT[ 94] & ~reg_be))) |
+ (addr_hit[ 95] & (|(PINMUX_PERMIT[ 95] & ~reg_be))) |
+ (addr_hit[ 96] & (|(PINMUX_PERMIT[ 96] & ~reg_be))) |
+ (addr_hit[ 97] & (|(PINMUX_PERMIT[ 97] & ~reg_be))) |
+ (addr_hit[ 98] & (|(PINMUX_PERMIT[ 98] & ~reg_be))) |
+ (addr_hit[ 99] & (|(PINMUX_PERMIT[ 99] & ~reg_be))) |
+ (addr_hit[100] & (|(PINMUX_PERMIT[100] & ~reg_be))) |
+ (addr_hit[101] & (|(PINMUX_PERMIT[101] & ~reg_be))) |
+ (addr_hit[102] & (|(PINMUX_PERMIT[102] & ~reg_be))) |
+ (addr_hit[103] & (|(PINMUX_PERMIT[103] & ~reg_be))) |
+ (addr_hit[104] & (|(PINMUX_PERMIT[104] & ~reg_be))) |
+ (addr_hit[105] & (|(PINMUX_PERMIT[105] & ~reg_be))) |
+ (addr_hit[106] & (|(PINMUX_PERMIT[106] & ~reg_be))) |
+ (addr_hit[107] & (|(PINMUX_PERMIT[107] & ~reg_be))) |
+ (addr_hit[108] & (|(PINMUX_PERMIT[108] & ~reg_be))) |
+ (addr_hit[109] & (|(PINMUX_PERMIT[109] & ~reg_be))) |
+ (addr_hit[110] & (|(PINMUX_PERMIT[110] & ~reg_be))) |
+ (addr_hit[111] & (|(PINMUX_PERMIT[111] & ~reg_be))) |
+ (addr_hit[112] & (|(PINMUX_PERMIT[112] & ~reg_be))) |
+ (addr_hit[113] & (|(PINMUX_PERMIT[113] & ~reg_be))) |
+ (addr_hit[114] & (|(PINMUX_PERMIT[114] & ~reg_be))) |
+ (addr_hit[115] & (|(PINMUX_PERMIT[115] & ~reg_be))) |
+ (addr_hit[116] & (|(PINMUX_PERMIT[116] & ~reg_be))) |
+ (addr_hit[117] & (|(PINMUX_PERMIT[117] & ~reg_be))) |
+ (addr_hit[118] & (|(PINMUX_PERMIT[118] & ~reg_be))) |
+ (addr_hit[119] & (|(PINMUX_PERMIT[119] & ~reg_be))) |
+ (addr_hit[120] & (|(PINMUX_PERMIT[120] & ~reg_be))) |
+ (addr_hit[121] & (|(PINMUX_PERMIT[121] & ~reg_be))) |
+ (addr_hit[122] & (|(PINMUX_PERMIT[122] & ~reg_be))) |
+ (addr_hit[123] & (|(PINMUX_PERMIT[123] & ~reg_be))) |
+ (addr_hit[124] & (|(PINMUX_PERMIT[124] & ~reg_be))) |
+ (addr_hit[125] & (|(PINMUX_PERMIT[125] & ~reg_be))) |
+ (addr_hit[126] & (|(PINMUX_PERMIT[126] & ~reg_be))) |
+ (addr_hit[127] & (|(PINMUX_PERMIT[127] & ~reg_be))) |
+ (addr_hit[128] & (|(PINMUX_PERMIT[128] & ~reg_be))) |
+ (addr_hit[129] & (|(PINMUX_PERMIT[129] & ~reg_be))) |
+ (addr_hit[130] & (|(PINMUX_PERMIT[130] & ~reg_be))) |
+ (addr_hit[131] & (|(PINMUX_PERMIT[131] & ~reg_be))) |
+ (addr_hit[132] & (|(PINMUX_PERMIT[132] & ~reg_be))) |
+ (addr_hit[133] & (|(PINMUX_PERMIT[133] & ~reg_be))) |
+ (addr_hit[134] & (|(PINMUX_PERMIT[134] & ~reg_be))) |
+ (addr_hit[135] & (|(PINMUX_PERMIT[135] & ~reg_be))) |
+ (addr_hit[136] & (|(PINMUX_PERMIT[136] & ~reg_be))) |
+ (addr_hit[137] & (|(PINMUX_PERMIT[137] & ~reg_be))) |
+ (addr_hit[138] & (|(PINMUX_PERMIT[138] & ~reg_be))) |
+ (addr_hit[139] & (|(PINMUX_PERMIT[139] & ~reg_be))) |
+ (addr_hit[140] & (|(PINMUX_PERMIT[140] & ~reg_be))) |
+ (addr_hit[141] & (|(PINMUX_PERMIT[141] & ~reg_be))) |
+ (addr_hit[142] & (|(PINMUX_PERMIT[142] & ~reg_be))) |
+ (addr_hit[143] & (|(PINMUX_PERMIT[143] & ~reg_be))) |
+ (addr_hit[144] & (|(PINMUX_PERMIT[144] & ~reg_be))) |
+ (addr_hit[145] & (|(PINMUX_PERMIT[145] & ~reg_be))) |
+ (addr_hit[146] & (|(PINMUX_PERMIT[146] & ~reg_be))) |
+ (addr_hit[147] & (|(PINMUX_PERMIT[147] & ~reg_be))) |
+ (addr_hit[148] & (|(PINMUX_PERMIT[148] & ~reg_be))) |
+ (addr_hit[149] & (|(PINMUX_PERMIT[149] & ~reg_be))) |
+ (addr_hit[150] & (|(PINMUX_PERMIT[150] & ~reg_be))) |
+ (addr_hit[151] & (|(PINMUX_PERMIT[151] & ~reg_be))) |
+ (addr_hit[152] & (|(PINMUX_PERMIT[152] & ~reg_be))) |
+ (addr_hit[153] & (|(PINMUX_PERMIT[153] & ~reg_be))) |
+ (addr_hit[154] & (|(PINMUX_PERMIT[154] & ~reg_be))) |
+ (addr_hit[155] & (|(PINMUX_PERMIT[155] & ~reg_be))) |
+ (addr_hit[156] & (|(PINMUX_PERMIT[156] & ~reg_be))) |
+ (addr_hit[157] & (|(PINMUX_PERMIT[157] & ~reg_be))) |
+ (addr_hit[158] & (|(PINMUX_PERMIT[158] & ~reg_be))) |
+ (addr_hit[159] & (|(PINMUX_PERMIT[159] & ~reg_be))) |
+ (addr_hit[160] & (|(PINMUX_PERMIT[160] & ~reg_be))) |
+ (addr_hit[161] & (|(PINMUX_PERMIT[161] & ~reg_be))) |
+ (addr_hit[162] & (|(PINMUX_PERMIT[162] & ~reg_be))) |
+ (addr_hit[163] & (|(PINMUX_PERMIT[163] & ~reg_be))) |
+ (addr_hit[164] & (|(PINMUX_PERMIT[164] & ~reg_be))) |
+ (addr_hit[165] & (|(PINMUX_PERMIT[165] & ~reg_be))) |
+ (addr_hit[166] & (|(PINMUX_PERMIT[166] & ~reg_be))) |
+ (addr_hit[167] & (|(PINMUX_PERMIT[167] & ~reg_be))) |
+ (addr_hit[168] & (|(PINMUX_PERMIT[168] & ~reg_be))) |
+ (addr_hit[169] & (|(PINMUX_PERMIT[169] & ~reg_be))) |
+ (addr_hit[170] & (|(PINMUX_PERMIT[170] & ~reg_be))) |
+ (addr_hit[171] & (|(PINMUX_PERMIT[171] & ~reg_be))) |
+ (addr_hit[172] & (|(PINMUX_PERMIT[172] & ~reg_be))) |
+ (addr_hit[173] & (|(PINMUX_PERMIT[173] & ~reg_be))) |
+ (addr_hit[174] & (|(PINMUX_PERMIT[174] & ~reg_be))) |
+ (addr_hit[175] & (|(PINMUX_PERMIT[175] & ~reg_be))) |
+ (addr_hit[176] & (|(PINMUX_PERMIT[176] & ~reg_be))) |
+ (addr_hit[177] & (|(PINMUX_PERMIT[177] & ~reg_be))) |
+ (addr_hit[178] & (|(PINMUX_PERMIT[178] & ~reg_be))) |
+ (addr_hit[179] & (|(PINMUX_PERMIT[179] & ~reg_be))) |
+ (addr_hit[180] & (|(PINMUX_PERMIT[180] & ~reg_be))) |
+ (addr_hit[181] & (|(PINMUX_PERMIT[181] & ~reg_be))) |
+ (addr_hit[182] & (|(PINMUX_PERMIT[182] & ~reg_be))) |
+ (addr_hit[183] & (|(PINMUX_PERMIT[183] & ~reg_be))) |
+ (addr_hit[184] & (|(PINMUX_PERMIT[184] & ~reg_be))) |
+ (addr_hit[185] & (|(PINMUX_PERMIT[185] & ~reg_be))) |
+ (addr_hit[186] & (|(PINMUX_PERMIT[186] & ~reg_be))) |
+ (addr_hit[187] & (|(PINMUX_PERMIT[187] & ~reg_be))) |
+ (addr_hit[188] & (|(PINMUX_PERMIT[188] & ~reg_be))) |
+ (addr_hit[189] & (|(PINMUX_PERMIT[189] & ~reg_be))) |
+ (addr_hit[190] & (|(PINMUX_PERMIT[190] & ~reg_be))) |
+ (addr_hit[191] & (|(PINMUX_PERMIT[191] & ~reg_be))) |
+ (addr_hit[192] & (|(PINMUX_PERMIT[192] & ~reg_be))) |
+ (addr_hit[193] & (|(PINMUX_PERMIT[193] & ~reg_be))) |
+ (addr_hit[194] & (|(PINMUX_PERMIT[194] & ~reg_be))) |
+ (addr_hit[195] & (|(PINMUX_PERMIT[195] & ~reg_be))) |
+ (addr_hit[196] & (|(PINMUX_PERMIT[196] & ~reg_be))) |
+ (addr_hit[197] & (|(PINMUX_PERMIT[197] & ~reg_be))) |
+ (addr_hit[198] & (|(PINMUX_PERMIT[198] & ~reg_be))) |
+ (addr_hit[199] & (|(PINMUX_PERMIT[199] & ~reg_be))) |
+ (addr_hit[200] & (|(PINMUX_PERMIT[200] & ~reg_be))) |
+ (addr_hit[201] & (|(PINMUX_PERMIT[201] & ~reg_be))) |
+ (addr_hit[202] & (|(PINMUX_PERMIT[202] & ~reg_be))) |
+ (addr_hit[203] & (|(PINMUX_PERMIT[203] & ~reg_be))) |
+ (addr_hit[204] & (|(PINMUX_PERMIT[204] & ~reg_be))) |
+ (addr_hit[205] & (|(PINMUX_PERMIT[205] & ~reg_be))) |
+ (addr_hit[206] & (|(PINMUX_PERMIT[206] & ~reg_be))) |
+ (addr_hit[207] & (|(PINMUX_PERMIT[207] & ~reg_be))) |
+ (addr_hit[208] & (|(PINMUX_PERMIT[208] & ~reg_be))) |
+ (addr_hit[209] & (|(PINMUX_PERMIT[209] & ~reg_be))) |
+ (addr_hit[210] & (|(PINMUX_PERMIT[210] & ~reg_be))) |
+ (addr_hit[211] & (|(PINMUX_PERMIT[211] & ~reg_be))) |
+ (addr_hit[212] & (|(PINMUX_PERMIT[212] & ~reg_be))) |
+ (addr_hit[213] & (|(PINMUX_PERMIT[213] & ~reg_be))) |
+ (addr_hit[214] & (|(PINMUX_PERMIT[214] & ~reg_be))) |
+ (addr_hit[215] & (|(PINMUX_PERMIT[215] & ~reg_be))) |
+ (addr_hit[216] & (|(PINMUX_PERMIT[216] & ~reg_be))) |
+ (addr_hit[217] & (|(PINMUX_PERMIT[217] & ~reg_be))) |
+ (addr_hit[218] & (|(PINMUX_PERMIT[218] & ~reg_be))) |
+ (addr_hit[219] & (|(PINMUX_PERMIT[219] & ~reg_be))) |
+ (addr_hit[220] & (|(PINMUX_PERMIT[220] & ~reg_be))) |
+ (addr_hit[221] & (|(PINMUX_PERMIT[221] & ~reg_be))) |
+ (addr_hit[222] & (|(PINMUX_PERMIT[222] & ~reg_be))) |
+ (addr_hit[223] & (|(PINMUX_PERMIT[223] & ~reg_be))) |
+ (addr_hit[224] & (|(PINMUX_PERMIT[224] & ~reg_be))) |
+ (addr_hit[225] & (|(PINMUX_PERMIT[225] & ~reg_be))) |
+ (addr_hit[226] & (|(PINMUX_PERMIT[226] & ~reg_be))) |
+ (addr_hit[227] & (|(PINMUX_PERMIT[227] & ~reg_be))) |
+ (addr_hit[228] & (|(PINMUX_PERMIT[228] & ~reg_be))) |
+ (addr_hit[229] & (|(PINMUX_PERMIT[229] & ~reg_be))) |
+ (addr_hit[230] & (|(PINMUX_PERMIT[230] & ~reg_be))) |
+ (addr_hit[231] & (|(PINMUX_PERMIT[231] & ~reg_be))) |
+ (addr_hit[232] & (|(PINMUX_PERMIT[232] & ~reg_be))) |
+ (addr_hit[233] & (|(PINMUX_PERMIT[233] & ~reg_be))) |
+ (addr_hit[234] & (|(PINMUX_PERMIT[234] & ~reg_be))) |
+ (addr_hit[235] & (|(PINMUX_PERMIT[235] & ~reg_be))) |
+ (addr_hit[236] & (|(PINMUX_PERMIT[236] & ~reg_be))) |
+ (addr_hit[237] & (|(PINMUX_PERMIT[237] & ~reg_be))) |
+ (addr_hit[238] & (|(PINMUX_PERMIT[238] & ~reg_be))) |
+ (addr_hit[239] & (|(PINMUX_PERMIT[239] & ~reg_be))) |
+ (addr_hit[240] & (|(PINMUX_PERMIT[240] & ~reg_be))) |
+ (addr_hit[241] & (|(PINMUX_PERMIT[241] & ~reg_be))) |
+ (addr_hit[242] & (|(PINMUX_PERMIT[242] & ~reg_be))) |
+ (addr_hit[243] & (|(PINMUX_PERMIT[243] & ~reg_be))) |
+ (addr_hit[244] & (|(PINMUX_PERMIT[244] & ~reg_be))) |
+ (addr_hit[245] & (|(PINMUX_PERMIT[245] & ~reg_be))) |
+ (addr_hit[246] & (|(PINMUX_PERMIT[246] & ~reg_be))) |
+ (addr_hit[247] & (|(PINMUX_PERMIT[247] & ~reg_be))) |
+ (addr_hit[248] & (|(PINMUX_PERMIT[248] & ~reg_be))) |
+ (addr_hit[249] & (|(PINMUX_PERMIT[249] & ~reg_be))) |
+ (addr_hit[250] & (|(PINMUX_PERMIT[250] & ~reg_be))) |
+ (addr_hit[251] & (|(PINMUX_PERMIT[251] & ~reg_be))) |
+ (addr_hit[252] & (|(PINMUX_PERMIT[252] & ~reg_be))) |
+ (addr_hit[253] & (|(PINMUX_PERMIT[253] & ~reg_be))) |
+ (addr_hit[254] & (|(PINMUX_PERMIT[254] & ~reg_be))) |
+ (addr_hit[255] & (|(PINMUX_PERMIT[255] & ~reg_be))) |
+ (addr_hit[256] & (|(PINMUX_PERMIT[256] & ~reg_be))) |
+ (addr_hit[257] & (|(PINMUX_PERMIT[257] & ~reg_be))) |
+ (addr_hit[258] & (|(PINMUX_PERMIT[258] & ~reg_be))) |
+ (addr_hit[259] & (|(PINMUX_PERMIT[259] & ~reg_be))) |
+ (addr_hit[260] & (|(PINMUX_PERMIT[260] & ~reg_be))) |
+ (addr_hit[261] & (|(PINMUX_PERMIT[261] & ~reg_be))) |
+ (addr_hit[262] & (|(PINMUX_PERMIT[262] & ~reg_be))) |
+ (addr_hit[263] & (|(PINMUX_PERMIT[263] & ~reg_be))) |
+ (addr_hit[264] & (|(PINMUX_PERMIT[264] & ~reg_be))) |
+ (addr_hit[265] & (|(PINMUX_PERMIT[265] & ~reg_be))) |
+ (addr_hit[266] & (|(PINMUX_PERMIT[266] & ~reg_be))) |
+ (addr_hit[267] & (|(PINMUX_PERMIT[267] & ~reg_be))) |
+ (addr_hit[268] & (|(PINMUX_PERMIT[268] & ~reg_be))) |
+ (addr_hit[269] & (|(PINMUX_PERMIT[269] & ~reg_be))) |
+ (addr_hit[270] & (|(PINMUX_PERMIT[270] & ~reg_be))) |
+ (addr_hit[271] & (|(PINMUX_PERMIT[271] & ~reg_be))) |
+ (addr_hit[272] & (|(PINMUX_PERMIT[272] & ~reg_be))) |
+ (addr_hit[273] & (|(PINMUX_PERMIT[273] & ~reg_be))) |
+ (addr_hit[274] & (|(PINMUX_PERMIT[274] & ~reg_be))) |
+ (addr_hit[275] & (|(PINMUX_PERMIT[275] & ~reg_be))) |
+ (addr_hit[276] & (|(PINMUX_PERMIT[276] & ~reg_be))) |
+ (addr_hit[277] & (|(PINMUX_PERMIT[277] & ~reg_be))) |
+ (addr_hit[278] & (|(PINMUX_PERMIT[278] & ~reg_be))) |
+ (addr_hit[279] & (|(PINMUX_PERMIT[279] & ~reg_be))) |
+ (addr_hit[280] & (|(PINMUX_PERMIT[280] & ~reg_be))) |
+ (addr_hit[281] & (|(PINMUX_PERMIT[281] & ~reg_be))) |
+ (addr_hit[282] & (|(PINMUX_PERMIT[282] & ~reg_be))) |
+ (addr_hit[283] & (|(PINMUX_PERMIT[283] & ~reg_be))) |
+ (addr_hit[284] & (|(PINMUX_PERMIT[284] & ~reg_be))) |
+ (addr_hit[285] & (|(PINMUX_PERMIT[285] & ~reg_be))) |
+ (addr_hit[286] & (|(PINMUX_PERMIT[286] & ~reg_be))) |
+ (addr_hit[287] & (|(PINMUX_PERMIT[287] & ~reg_be))) |
+ (addr_hit[288] & (|(PINMUX_PERMIT[288] & ~reg_be))) |
+ (addr_hit[289] & (|(PINMUX_PERMIT[289] & ~reg_be))) |
+ (addr_hit[290] & (|(PINMUX_PERMIT[290] & ~reg_be))) |
+ (addr_hit[291] & (|(PINMUX_PERMIT[291] & ~reg_be))) |
+ (addr_hit[292] & (|(PINMUX_PERMIT[292] & ~reg_be))) |
+ (addr_hit[293] & (|(PINMUX_PERMIT[293] & ~reg_be))) |
+ (addr_hit[294] & (|(PINMUX_PERMIT[294] & ~reg_be))) |
+ (addr_hit[295] & (|(PINMUX_PERMIT[295] & ~reg_be))) |
+ (addr_hit[296] & (|(PINMUX_PERMIT[296] & ~reg_be))) |
+ (addr_hit[297] & (|(PINMUX_PERMIT[297] & ~reg_be))) |
+ (addr_hit[298] & (|(PINMUX_PERMIT[298] & ~reg_be))) |
+ (addr_hit[299] & (|(PINMUX_PERMIT[299] & ~reg_be))) |
+ (addr_hit[300] & (|(PINMUX_PERMIT[300] & ~reg_be))) |
+ (addr_hit[301] & (|(PINMUX_PERMIT[301] & ~reg_be))) |
+ (addr_hit[302] & (|(PINMUX_PERMIT[302] & ~reg_be))) |
+ (addr_hit[303] & (|(PINMUX_PERMIT[303] & ~reg_be))) |
+ (addr_hit[304] & (|(PINMUX_PERMIT[304] & ~reg_be))) |
+ (addr_hit[305] & (|(PINMUX_PERMIT[305] & ~reg_be))) |
+ (addr_hit[306] & (|(PINMUX_PERMIT[306] & ~reg_be))) |
+ (addr_hit[307] & (|(PINMUX_PERMIT[307] & ~reg_be))) |
+ (addr_hit[308] & (|(PINMUX_PERMIT[308] & ~reg_be))) |
+ (addr_hit[309] & (|(PINMUX_PERMIT[309] & ~reg_be))) |
+ (addr_hit[310] & (|(PINMUX_PERMIT[310] & ~reg_be))) |
+ (addr_hit[311] & (|(PINMUX_PERMIT[311] & ~reg_be))) |
+ (addr_hit[312] & (|(PINMUX_PERMIT[312] & ~reg_be))) |
+ (addr_hit[313] & (|(PINMUX_PERMIT[313] & ~reg_be))) |
+ (addr_hit[314] & (|(PINMUX_PERMIT[314] & ~reg_be))) |
+ (addr_hit[315] & (|(PINMUX_PERMIT[315] & ~reg_be))) |
+ (addr_hit[316] & (|(PINMUX_PERMIT[316] & ~reg_be))) |
+ (addr_hit[317] & (|(PINMUX_PERMIT[317] & ~reg_be))) |
+ (addr_hit[318] & (|(PINMUX_PERMIT[318] & ~reg_be))) |
+ (addr_hit[319] & (|(PINMUX_PERMIT[319] & ~reg_be))) |
+ (addr_hit[320] & (|(PINMUX_PERMIT[320] & ~reg_be))) |
+ (addr_hit[321] & (|(PINMUX_PERMIT[321] & ~reg_be))) |
+ (addr_hit[322] & (|(PINMUX_PERMIT[322] & ~reg_be))) |
+ (addr_hit[323] & (|(PINMUX_PERMIT[323] & ~reg_be))) |
+ (addr_hit[324] & (|(PINMUX_PERMIT[324] & ~reg_be))) |
+ (addr_hit[325] & (|(PINMUX_PERMIT[325] & ~reg_be))) |
+ (addr_hit[326] & (|(PINMUX_PERMIT[326] & ~reg_be))) |
+ (addr_hit[327] & (|(PINMUX_PERMIT[327] & ~reg_be))) |
+ (addr_hit[328] & (|(PINMUX_PERMIT[328] & ~reg_be))) |
+ (addr_hit[329] & (|(PINMUX_PERMIT[329] & ~reg_be))) |
+ (addr_hit[330] & (|(PINMUX_PERMIT[330] & ~reg_be))) |
+ (addr_hit[331] & (|(PINMUX_PERMIT[331] & ~reg_be))) |
+ (addr_hit[332] & (|(PINMUX_PERMIT[332] & ~reg_be))) |
+ (addr_hit[333] & (|(PINMUX_PERMIT[333] & ~reg_be))) |
+ (addr_hit[334] & (|(PINMUX_PERMIT[334] & ~reg_be))) |
+ (addr_hit[335] & (|(PINMUX_PERMIT[335] & ~reg_be))) |
+ (addr_hit[336] & (|(PINMUX_PERMIT[336] & ~reg_be))) |
+ (addr_hit[337] & (|(PINMUX_PERMIT[337] & ~reg_be))) |
+ (addr_hit[338] & (|(PINMUX_PERMIT[338] & ~reg_be))) |
+ (addr_hit[339] & (|(PINMUX_PERMIT[339] & ~reg_be))) |
+ (addr_hit[340] & (|(PINMUX_PERMIT[340] & ~reg_be))) |
+ (addr_hit[341] & (|(PINMUX_PERMIT[341] & ~reg_be))) |
+ (addr_hit[342] & (|(PINMUX_PERMIT[342] & ~reg_be))) |
+ (addr_hit[343] & (|(PINMUX_PERMIT[343] & ~reg_be))) |
+ (addr_hit[344] & (|(PINMUX_PERMIT[344] & ~reg_be))) |
+ (addr_hit[345] & (|(PINMUX_PERMIT[345] & ~reg_be))) |
+ (addr_hit[346] & (|(PINMUX_PERMIT[346] & ~reg_be))) |
+ (addr_hit[347] & (|(PINMUX_PERMIT[347] & ~reg_be))) |
+ (addr_hit[348] & (|(PINMUX_PERMIT[348] & ~reg_be))) |
+ (addr_hit[349] & (|(PINMUX_PERMIT[349] & ~reg_be))) |
+ (addr_hit[350] & (|(PINMUX_PERMIT[350] & ~reg_be))) |
+ (addr_hit[351] & (|(PINMUX_PERMIT[351] & ~reg_be))) |
+ (addr_hit[352] & (|(PINMUX_PERMIT[352] & ~reg_be))) |
+ (addr_hit[353] & (|(PINMUX_PERMIT[353] & ~reg_be))) |
+ (addr_hit[354] & (|(PINMUX_PERMIT[354] & ~reg_be))) |
+ (addr_hit[355] & (|(PINMUX_PERMIT[355] & ~reg_be))) |
+ (addr_hit[356] & (|(PINMUX_PERMIT[356] & ~reg_be))) |
+ (addr_hit[357] & (|(PINMUX_PERMIT[357] & ~reg_be))) |
+ (addr_hit[358] & (|(PINMUX_PERMIT[358] & ~reg_be))) |
+ (addr_hit[359] & (|(PINMUX_PERMIT[359] & ~reg_be))) |
+ (addr_hit[360] & (|(PINMUX_PERMIT[360] & ~reg_be))) |
+ (addr_hit[361] & (|(PINMUX_PERMIT[361] & ~reg_be))) |
+ (addr_hit[362] & (|(PINMUX_PERMIT[362] & ~reg_be))) |
+ (addr_hit[363] & (|(PINMUX_PERMIT[363] & ~reg_be))) |
+ (addr_hit[364] & (|(PINMUX_PERMIT[364] & ~reg_be))) |
+ (addr_hit[365] & (|(PINMUX_PERMIT[365] & ~reg_be))) |
+ (addr_hit[366] & (|(PINMUX_PERMIT[366] & ~reg_be))) |
+ (addr_hit[367] & (|(PINMUX_PERMIT[367] & ~reg_be))) |
+ (addr_hit[368] & (|(PINMUX_PERMIT[368] & ~reg_be))) |
+ (addr_hit[369] & (|(PINMUX_PERMIT[369] & ~reg_be))) |
+ (addr_hit[370] & (|(PINMUX_PERMIT[370] & ~reg_be))) |
+ (addr_hit[371] & (|(PINMUX_PERMIT[371] & ~reg_be))) |
+ (addr_hit[372] & (|(PINMUX_PERMIT[372] & ~reg_be))) |
+ (addr_hit[373] & (|(PINMUX_PERMIT[373] & ~reg_be))) |
+ (addr_hit[374] & (|(PINMUX_PERMIT[374] & ~reg_be))) |
+ (addr_hit[375] & (|(PINMUX_PERMIT[375] & ~reg_be))) |
+ (addr_hit[376] & (|(PINMUX_PERMIT[376] & ~reg_be))) |
+ (addr_hit[377] & (|(PINMUX_PERMIT[377] & ~reg_be))) |
+ (addr_hit[378] & (|(PINMUX_PERMIT[378] & ~reg_be))) |
+ (addr_hit[379] & (|(PINMUX_PERMIT[379] & ~reg_be))) |
+ (addr_hit[380] & (|(PINMUX_PERMIT[380] & ~reg_be))) |
+ (addr_hit[381] & (|(PINMUX_PERMIT[381] & ~reg_be))) |
+ (addr_hit[382] & (|(PINMUX_PERMIT[382] & ~reg_be))) |
+ (addr_hit[383] & (|(PINMUX_PERMIT[383] & ~reg_be))) |
+ (addr_hit[384] & (|(PINMUX_PERMIT[384] & ~reg_be))) |
+ (addr_hit[385] & (|(PINMUX_PERMIT[385] & ~reg_be))) |
+ (addr_hit[386] & (|(PINMUX_PERMIT[386] & ~reg_be))) |
+ (addr_hit[387] & (|(PINMUX_PERMIT[387] & ~reg_be))) |
+ (addr_hit[388] & (|(PINMUX_PERMIT[388] & ~reg_be))) |
+ (addr_hit[389] & (|(PINMUX_PERMIT[389] & ~reg_be))) |
+ (addr_hit[390] & (|(PINMUX_PERMIT[390] & ~reg_be))) |
+ (addr_hit[391] & (|(PINMUX_PERMIT[391] & ~reg_be))) |
+ (addr_hit[392] & (|(PINMUX_PERMIT[392] & ~reg_be))) |
+ (addr_hit[393] & (|(PINMUX_PERMIT[393] & ~reg_be))) |
+ (addr_hit[394] & (|(PINMUX_PERMIT[394] & ~reg_be))) |
+ (addr_hit[395] & (|(PINMUX_PERMIT[395] & ~reg_be))) |
+ (addr_hit[396] & (|(PINMUX_PERMIT[396] & ~reg_be))) |
+ (addr_hit[397] & (|(PINMUX_PERMIT[397] & ~reg_be))) |
+ (addr_hit[398] & (|(PINMUX_PERMIT[398] & ~reg_be))) |
+ (addr_hit[399] & (|(PINMUX_PERMIT[399] & ~reg_be))) |
+ (addr_hit[400] & (|(PINMUX_PERMIT[400] & ~reg_be))) |
+ (addr_hit[401] & (|(PINMUX_PERMIT[401] & ~reg_be))) |
+ (addr_hit[402] & (|(PINMUX_PERMIT[402] & ~reg_be))) |
+ (addr_hit[403] & (|(PINMUX_PERMIT[403] & ~reg_be))) |
+ (addr_hit[404] & (|(PINMUX_PERMIT[404] & ~reg_be))) |
+ (addr_hit[405] & (|(PINMUX_PERMIT[405] & ~reg_be))) |
+ (addr_hit[406] & (|(PINMUX_PERMIT[406] & ~reg_be))) |
+ (addr_hit[407] & (|(PINMUX_PERMIT[407] & ~reg_be))) |
+ (addr_hit[408] & (|(PINMUX_PERMIT[408] & ~reg_be))) |
+ (addr_hit[409] & (|(PINMUX_PERMIT[409] & ~reg_be))) |
+ (addr_hit[410] & (|(PINMUX_PERMIT[410] & ~reg_be))) |
+ (addr_hit[411] & (|(PINMUX_PERMIT[411] & ~reg_be))) |
+ (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be))) |
+ (addr_hit[413] & (|(PINMUX_PERMIT[413] & ~reg_be))) |
+ (addr_hit[414] & (|(PINMUX_PERMIT[414] & ~reg_be))) |
+ (addr_hit[415] & (|(PINMUX_PERMIT[415] & ~reg_be))) |
+ (addr_hit[416] & (|(PINMUX_PERMIT[416] & ~reg_be))) |
+ (addr_hit[417] & (|(PINMUX_PERMIT[417] & ~reg_be))) |
+ (addr_hit[418] & (|(PINMUX_PERMIT[418] & ~reg_be))) |
+ (addr_hit[419] & (|(PINMUX_PERMIT[419] & ~reg_be))) |
+ (addr_hit[420] & (|(PINMUX_PERMIT[420] & ~reg_be))) |
+ (addr_hit[421] & (|(PINMUX_PERMIT[421] & ~reg_be))) |
+ (addr_hit[422] & (|(PINMUX_PERMIT[422] & ~reg_be))) |
+ (addr_hit[423] & (|(PINMUX_PERMIT[423] & ~reg_be))) |
+ (addr_hit[424] & (|(PINMUX_PERMIT[424] & ~reg_be))) |
+ (addr_hit[425] & (|(PINMUX_PERMIT[425] & ~reg_be))) |
+ (addr_hit[426] & (|(PINMUX_PERMIT[426] & ~reg_be))) |
+ (addr_hit[427] & (|(PINMUX_PERMIT[427] & ~reg_be))) |
+ (addr_hit[428] & (|(PINMUX_PERMIT[428] & ~reg_be))) |
+ (addr_hit[429] & (|(PINMUX_PERMIT[429] & ~reg_be))) |
+ (addr_hit[430] & (|(PINMUX_PERMIT[430] & ~reg_be))) |
+ (addr_hit[431] & (|(PINMUX_PERMIT[431] & ~reg_be))) |
+ (addr_hit[432] & (|(PINMUX_PERMIT[432] & ~reg_be))) |
+ (addr_hit[433] & (|(PINMUX_PERMIT[433] & ~reg_be))) |
+ (addr_hit[434] & (|(PINMUX_PERMIT[434] & ~reg_be))) |
+ (addr_hit[435] & (|(PINMUX_PERMIT[435] & ~reg_be))) |
+ (addr_hit[436] & (|(PINMUX_PERMIT[436] & ~reg_be))) |
+ (addr_hit[437] & (|(PINMUX_PERMIT[437] & ~reg_be))) |
+ (addr_hit[438] & (|(PINMUX_PERMIT[438] & ~reg_be))) |
+ (addr_hit[439] & (|(PINMUX_PERMIT[439] & ~reg_be))) |
+ (addr_hit[440] & (|(PINMUX_PERMIT[440] & ~reg_be))) |
+ (addr_hit[441] & (|(PINMUX_PERMIT[441] & ~reg_be))) |
+ (addr_hit[442] & (|(PINMUX_PERMIT[442] & ~reg_be))) |
+ (addr_hit[443] & (|(PINMUX_PERMIT[443] & ~reg_be))) |
+ (addr_hit[444] & (|(PINMUX_PERMIT[444] & ~reg_be))) |
+ (addr_hit[445] & (|(PINMUX_PERMIT[445] & ~reg_be))) |
+ (addr_hit[446] & (|(PINMUX_PERMIT[446] & ~reg_be))) |
+ (addr_hit[447] & (|(PINMUX_PERMIT[447] & ~reg_be))) |
+ (addr_hit[448] & (|(PINMUX_PERMIT[448] & ~reg_be))) |
+ (addr_hit[449] & (|(PINMUX_PERMIT[449] & ~reg_be))) |
+ (addr_hit[450] & (|(PINMUX_PERMIT[450] & ~reg_be))) |
+ (addr_hit[451] & (|(PINMUX_PERMIT[451] & ~reg_be))) |
+ (addr_hit[452] & (|(PINMUX_PERMIT[452] & ~reg_be))) |
+ (addr_hit[453] & (|(PINMUX_PERMIT[453] & ~reg_be))) |
+ (addr_hit[454] & (|(PINMUX_PERMIT[454] & ~reg_be))) |
+ (addr_hit[455] & (|(PINMUX_PERMIT[455] & ~reg_be))) |
+ (addr_hit[456] & (|(PINMUX_PERMIT[456] & ~reg_be))) |
+ (addr_hit[457] & (|(PINMUX_PERMIT[457] & ~reg_be))) |
+ (addr_hit[458] & (|(PINMUX_PERMIT[458] & ~reg_be))) |
+ (addr_hit[459] & (|(PINMUX_PERMIT[459] & ~reg_be))) |
+ (addr_hit[460] & (|(PINMUX_PERMIT[460] & ~reg_be))) |
+ (addr_hit[461] & (|(PINMUX_PERMIT[461] & ~reg_be))) |
+ (addr_hit[462] & (|(PINMUX_PERMIT[462] & ~reg_be))) |
+ (addr_hit[463] & (|(PINMUX_PERMIT[463] & ~reg_be))) |
+ (addr_hit[464] & (|(PINMUX_PERMIT[464] & ~reg_be))) |
+ (addr_hit[465] & (|(PINMUX_PERMIT[465] & ~reg_be))) |
+ (addr_hit[466] & (|(PINMUX_PERMIT[466] & ~reg_be))) |
+ (addr_hit[467] & (|(PINMUX_PERMIT[467] & ~reg_be))) |
+ (addr_hit[468] & (|(PINMUX_PERMIT[468] & ~reg_be))) |
+ (addr_hit[469] & (|(PINMUX_PERMIT[469] & ~reg_be))) |
+ (addr_hit[470] & (|(PINMUX_PERMIT[470] & ~reg_be))) |
+ (addr_hit[471] & (|(PINMUX_PERMIT[471] & ~reg_be))) |
+ (addr_hit[472] & (|(PINMUX_PERMIT[472] & ~reg_be))) |
+ (addr_hit[473] & (|(PINMUX_PERMIT[473] & ~reg_be))) |
+ (addr_hit[474] & (|(PINMUX_PERMIT[474] & ~reg_be))) |
+ (addr_hit[475] & (|(PINMUX_PERMIT[475] & ~reg_be))) |
+ (addr_hit[476] & (|(PINMUX_PERMIT[476] & ~reg_be))) |
+ (addr_hit[477] & (|(PINMUX_PERMIT[477] & ~reg_be))) |
+ (addr_hit[478] & (|(PINMUX_PERMIT[478] & ~reg_be))) |
+ (addr_hit[479] & (|(PINMUX_PERMIT[479] & ~reg_be))) |
+ (addr_hit[480] & (|(PINMUX_PERMIT[480] & ~reg_be))) |
+ (addr_hit[481] & (|(PINMUX_PERMIT[481] & ~reg_be))) |
+ (addr_hit[482] & (|(PINMUX_PERMIT[482] & ~reg_be))) |
+ (addr_hit[483] & (|(PINMUX_PERMIT[483] & ~reg_be))) |
+ (addr_hit[484] & (|(PINMUX_PERMIT[484] & ~reg_be))) |
+ (addr_hit[485] & (|(PINMUX_PERMIT[485] & ~reg_be))) |
+ (addr_hit[486] & (|(PINMUX_PERMIT[486] & ~reg_be))) |
+ (addr_hit[487] & (|(PINMUX_PERMIT[487] & ~reg_be))) |
+ (addr_hit[488] & (|(PINMUX_PERMIT[488] & ~reg_be))) |
+ (addr_hit[489] & (|(PINMUX_PERMIT[489] & ~reg_be))) |
+ (addr_hit[490] & (|(PINMUX_PERMIT[490] & ~reg_be))) |
+ (addr_hit[491] & (|(PINMUX_PERMIT[491] & ~reg_be))) |
+ (addr_hit[492] & (|(PINMUX_PERMIT[492] & ~reg_be))) |
+ (addr_hit[493] & (|(PINMUX_PERMIT[493] & ~reg_be))) |
+ (addr_hit[494] & (|(PINMUX_PERMIT[494] & ~reg_be))) |
+ (addr_hit[495] & (|(PINMUX_PERMIT[495] & ~reg_be))) |
+ (addr_hit[496] & (|(PINMUX_PERMIT[496] & ~reg_be))) |
+ (addr_hit[497] & (|(PINMUX_PERMIT[497] & ~reg_be))) |
+ (addr_hit[498] & (|(PINMUX_PERMIT[498] & ~reg_be))) |
+ (addr_hit[499] & (|(PINMUX_PERMIT[499] & ~reg_be))) |
+ (addr_hit[500] & (|(PINMUX_PERMIT[500] & ~reg_be))) |
+ (addr_hit[501] & (|(PINMUX_PERMIT[501] & ~reg_be))) |
+ (addr_hit[502] & (|(PINMUX_PERMIT[502] & ~reg_be))) |
+ (addr_hit[503] & (|(PINMUX_PERMIT[503] & ~reg_be))) |
+ (addr_hit[504] & (|(PINMUX_PERMIT[504] & ~reg_be))) |
+ (addr_hit[505] & (|(PINMUX_PERMIT[505] & ~reg_be))) |
+ (addr_hit[506] & (|(PINMUX_PERMIT[506] & ~reg_be))) |
+ (addr_hit[507] & (|(PINMUX_PERMIT[507] & ~reg_be))) |
+ (addr_hit[508] & (|(PINMUX_PERMIT[508] & ~reg_be))) |
+ (addr_hit[509] & (|(PINMUX_PERMIT[509] & ~reg_be))) |
+ (addr_hit[510] & (|(PINMUX_PERMIT[510] & ~reg_be))) |
+ (addr_hit[511] & (|(PINMUX_PERMIT[511] & ~reg_be))) |
+ (addr_hit[512] & (|(PINMUX_PERMIT[512] & ~reg_be))) |
+ (addr_hit[513] & (|(PINMUX_PERMIT[513] & ~reg_be))) |
+ (addr_hit[514] & (|(PINMUX_PERMIT[514] & ~reg_be))) |
+ (addr_hit[515] & (|(PINMUX_PERMIT[515] & ~reg_be))) |
+ (addr_hit[516] & (|(PINMUX_PERMIT[516] & ~reg_be))) |
+ (addr_hit[517] & (|(PINMUX_PERMIT[517] & ~reg_be))) |
+ (addr_hit[518] & (|(PINMUX_PERMIT[518] & ~reg_be))) |
+ (addr_hit[519] & (|(PINMUX_PERMIT[519] & ~reg_be))) |
+ (addr_hit[520] & (|(PINMUX_PERMIT[520] & ~reg_be))) |
+ (addr_hit[521] & (|(PINMUX_PERMIT[521] & ~reg_be))) |
+ (addr_hit[522] & (|(PINMUX_PERMIT[522] & ~reg_be))) |
+ (addr_hit[523] & (|(PINMUX_PERMIT[523] & ~reg_be))) |
+ (addr_hit[524] & (|(PINMUX_PERMIT[524] & ~reg_be))) |
+ (addr_hit[525] & (|(PINMUX_PERMIT[525] & ~reg_be))) |
+ (addr_hit[526] & (|(PINMUX_PERMIT[526] & ~reg_be))) |
+ (addr_hit[527] & (|(PINMUX_PERMIT[527] & ~reg_be))) |
+ (addr_hit[528] & (|(PINMUX_PERMIT[528] & ~reg_be))) |
+ (addr_hit[529] & (|(PINMUX_PERMIT[529] & ~reg_be))) |
+ (addr_hit[530] & (|(PINMUX_PERMIT[530] & ~reg_be))) |
+ (addr_hit[531] & (|(PINMUX_PERMIT[531] & ~reg_be))) |
+ (addr_hit[532] & (|(PINMUX_PERMIT[532] & ~reg_be))) |
+ (addr_hit[533] & (|(PINMUX_PERMIT[533] & ~reg_be))) |
+ (addr_hit[534] & (|(PINMUX_PERMIT[534] & ~reg_be))) |
+ (addr_hit[535] & (|(PINMUX_PERMIT[535] & ~reg_be))) |
+ (addr_hit[536] & (|(PINMUX_PERMIT[536] & ~reg_be))) |
+ (addr_hit[537] & (|(PINMUX_PERMIT[537] & ~reg_be))) |
+ (addr_hit[538] & (|(PINMUX_PERMIT[538] & ~reg_be))) |
+ (addr_hit[539] & (|(PINMUX_PERMIT[539] & ~reg_be))) |
+ (addr_hit[540] & (|(PINMUX_PERMIT[540] & ~reg_be))) |
+ (addr_hit[541] & (|(PINMUX_PERMIT[541] & ~reg_be))) |
+ (addr_hit[542] & (|(PINMUX_PERMIT[542] & ~reg_be))) |
+ (addr_hit[543] & (|(PINMUX_PERMIT[543] & ~reg_be))) |
+ (addr_hit[544] & (|(PINMUX_PERMIT[544] & ~reg_be))) |
+ (addr_hit[545] & (|(PINMUX_PERMIT[545] & ~reg_be))) |
+ (addr_hit[546] & (|(PINMUX_PERMIT[546] & ~reg_be))) |
+ (addr_hit[547] & (|(PINMUX_PERMIT[547] & ~reg_be))) |
+ (addr_hit[548] & (|(PINMUX_PERMIT[548] & ~reg_be))) |
+ (addr_hit[549] & (|(PINMUX_PERMIT[549] & ~reg_be))) |
+ (addr_hit[550] & (|(PINMUX_PERMIT[550] & ~reg_be))) |
+ (addr_hit[551] & (|(PINMUX_PERMIT[551] & ~reg_be))) |
+ (addr_hit[552] & (|(PINMUX_PERMIT[552] & ~reg_be))) |
+ (addr_hit[553] & (|(PINMUX_PERMIT[553] & ~reg_be))) |
+ (addr_hit[554] & (|(PINMUX_PERMIT[554] & ~reg_be))) |
+ (addr_hit[555] & (|(PINMUX_PERMIT[555] & ~reg_be))) |
+ (addr_hit[556] & (|(PINMUX_PERMIT[556] & ~reg_be))) |
+ (addr_hit[557] & (|(PINMUX_PERMIT[557] & ~reg_be))) |
+ (addr_hit[558] & (|(PINMUX_PERMIT[558] & ~reg_be))) |
+ (addr_hit[559] & (|(PINMUX_PERMIT[559] & ~reg_be))) |
+ (addr_hit[560] & (|(PINMUX_PERMIT[560] & ~reg_be))) |
+ (addr_hit[561] & (|(PINMUX_PERMIT[561] & ~reg_be))) |
+ (addr_hit[562] & (|(PINMUX_PERMIT[562] & ~reg_be))) |
+ (addr_hit[563] & (|(PINMUX_PERMIT[563] & ~reg_be))) |
+ (addr_hit[564] & (|(PINMUX_PERMIT[564] & ~reg_be))) |
+ (addr_hit[565] & (|(PINMUX_PERMIT[565] & ~reg_be))) |
+ (addr_hit[566] & (|(PINMUX_PERMIT[566] & ~reg_be))) |
+ (addr_hit[567] & (|(PINMUX_PERMIT[567] & ~reg_be))) |
+ (addr_hit[568] & (|(PINMUX_PERMIT[568] & ~reg_be))) |
+ (addr_hit[569] & (|(PINMUX_PERMIT[569] & ~reg_be))) |
+ (addr_hit[570] & (|(PINMUX_PERMIT[570] & ~reg_be))) |
+ (addr_hit[571] & (|(PINMUX_PERMIT[571] & ~reg_be))) |
+ (addr_hit[572] & (|(PINMUX_PERMIT[572] & ~reg_be))) |
+ (addr_hit[573] & (|(PINMUX_PERMIT[573] & ~reg_be))) |
+ (addr_hit[574] & (|(PINMUX_PERMIT[574] & ~reg_be))) |
+ (addr_hit[575] & (|(PINMUX_PERMIT[575] & ~reg_be))) |
+ (addr_hit[576] & (|(PINMUX_PERMIT[576] & ~reg_be))) |
+ (addr_hit[577] & (|(PINMUX_PERMIT[577] & ~reg_be))) |
+ (addr_hit[578] & (|(PINMUX_PERMIT[578] & ~reg_be))) |
+ (addr_hit[579] & (|(PINMUX_PERMIT[579] & ~reg_be))) |
+ (addr_hit[580] & (|(PINMUX_PERMIT[580] & ~reg_be))) |
+ (addr_hit[581] & (|(PINMUX_PERMIT[581] & ~reg_be))) |
+ (addr_hit[582] & (|(PINMUX_PERMIT[582] & ~reg_be))) |
+ (addr_hit[583] & (|(PINMUX_PERMIT[583] & ~reg_be))) |
+ (addr_hit[584] & (|(PINMUX_PERMIT[584] & ~reg_be))) |
+ (addr_hit[585] & (|(PINMUX_PERMIT[585] & ~reg_be))) |
+ (addr_hit[586] & (|(PINMUX_PERMIT[586] & ~reg_be))) |
+ (addr_hit[587] & (|(PINMUX_PERMIT[587] & ~reg_be))) |
+ (addr_hit[588] & (|(PINMUX_PERMIT[588] & ~reg_be))) |
+ (addr_hit[589] & (|(PINMUX_PERMIT[589] & ~reg_be))) |
+ (addr_hit[590] & (|(PINMUX_PERMIT[590] & ~reg_be))) |
+ (addr_hit[591] & (|(PINMUX_PERMIT[591] & ~reg_be))) |
+ (addr_hit[592] & (|(PINMUX_PERMIT[592] & ~reg_be))) |
+ (addr_hit[593] & (|(PINMUX_PERMIT[593] & ~reg_be))) |
+ (addr_hit[594] & (|(PINMUX_PERMIT[594] & ~reg_be))) |
+ (addr_hit[595] & (|(PINMUX_PERMIT[595] & ~reg_be))) |
+ (addr_hit[596] & (|(PINMUX_PERMIT[596] & ~reg_be))) |
+ (addr_hit[597] & (|(PINMUX_PERMIT[597] & ~reg_be))) |
+ (addr_hit[598] & (|(PINMUX_PERMIT[598] & ~reg_be))) |
+ (addr_hit[599] & (|(PINMUX_PERMIT[599] & ~reg_be))) |
+ (addr_hit[600] & (|(PINMUX_PERMIT[600] & ~reg_be))) |
+ (addr_hit[601] & (|(PINMUX_PERMIT[601] & ~reg_be))) |
+ (addr_hit[602] & (|(PINMUX_PERMIT[602] & ~reg_be))) |
+ (addr_hit[603] & (|(PINMUX_PERMIT[603] & ~reg_be))) |
+ (addr_hit[604] & (|(PINMUX_PERMIT[604] & ~reg_be))) |
+ (addr_hit[605] & (|(PINMUX_PERMIT[605] & ~reg_be))) |
+ (addr_hit[606] & (|(PINMUX_PERMIT[606] & ~reg_be))) |
+ (addr_hit[607] & (|(PINMUX_PERMIT[607] & ~reg_be))) |
+ (addr_hit[608] & (|(PINMUX_PERMIT[608] & ~reg_be))) |
+ (addr_hit[609] & (|(PINMUX_PERMIT[609] & ~reg_be))) |
+ (addr_hit[610] & (|(PINMUX_PERMIT[610] & ~reg_be))) |
+ (addr_hit[611] & (|(PINMUX_PERMIT[611] & ~reg_be))) |
+ (addr_hit[612] & (|(PINMUX_PERMIT[612] & ~reg_be))) |
+ (addr_hit[613] & (|(PINMUX_PERMIT[613] & ~reg_be))) |
+ (addr_hit[614] & (|(PINMUX_PERMIT[614] & ~reg_be))) |
+ (addr_hit[615] & (|(PINMUX_PERMIT[615] & ~reg_be))) |
+ (addr_hit[616] & (|(PINMUX_PERMIT[616] & ~reg_be))) |
+ (addr_hit[617] & (|(PINMUX_PERMIT[617] & ~reg_be))) |
+ (addr_hit[618] & (|(PINMUX_PERMIT[618] & ~reg_be))) |
+ (addr_hit[619] & (|(PINMUX_PERMIT[619] & ~reg_be))) |
+ (addr_hit[620] & (|(PINMUX_PERMIT[620] & ~reg_be))) |
+ (addr_hit[621] & (|(PINMUX_PERMIT[621] & ~reg_be))) |
+ (addr_hit[622] & (|(PINMUX_PERMIT[622] & ~reg_be))) |
+ (addr_hit[623] & (|(PINMUX_PERMIT[623] & ~reg_be))) |
+ (addr_hit[624] & (|(PINMUX_PERMIT[624] & ~reg_be))) |
+ (addr_hit[625] & (|(PINMUX_PERMIT[625] & ~reg_be))) |
+ (addr_hit[626] & (|(PINMUX_PERMIT[626] & ~reg_be))) |
+ (addr_hit[627] & (|(PINMUX_PERMIT[627] & ~reg_be))) |
+ (addr_hit[628] & (|(PINMUX_PERMIT[628] & ~reg_be))) |
+ (addr_hit[629] & (|(PINMUX_PERMIT[629] & ~reg_be))) |
+ (addr_hit[630] & (|(PINMUX_PERMIT[630] & ~reg_be))) |
+ (addr_hit[631] & (|(PINMUX_PERMIT[631] & ~reg_be))) |
+ (addr_hit[632] & (|(PINMUX_PERMIT[632] & ~reg_be))) |
+ (addr_hit[633] & (|(PINMUX_PERMIT[633] & ~reg_be))) |
+ (addr_hit[634] & (|(PINMUX_PERMIT[634] & ~reg_be))) |
+ (addr_hit[635] & (|(PINMUX_PERMIT[635] & ~reg_be))) |
+ (addr_hit[636] & (|(PINMUX_PERMIT[636] & ~reg_be))) |
+ (addr_hit[637] & (|(PINMUX_PERMIT[637] & ~reg_be))) |
+ (addr_hit[638] & (|(PINMUX_PERMIT[638] & ~reg_be))) |
+ (addr_hit[639] & (|(PINMUX_PERMIT[639] & ~reg_be))) |
+ (addr_hit[640] & (|(PINMUX_PERMIT[640] & ~reg_be))) |
+ (addr_hit[641] & (|(PINMUX_PERMIT[641] & ~reg_be))) |
+ (addr_hit[642] & (|(PINMUX_PERMIT[642] & ~reg_be))) |
+ (addr_hit[643] & (|(PINMUX_PERMIT[643] & ~reg_be))) |
+ (addr_hit[644] & (|(PINMUX_PERMIT[644] & ~reg_be))) |
+ (addr_hit[645] & (|(PINMUX_PERMIT[645] & ~reg_be))) |
+ (addr_hit[646] & (|(PINMUX_PERMIT[646] & ~reg_be))) |
+ (addr_hit[647] & (|(PINMUX_PERMIT[647] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_0_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_1_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_2_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_3_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_4_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_4_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_5_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_5_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_6_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_6_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_7_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_7_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_8_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_8_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_9_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_9_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_10_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_10_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_11_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_11_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_12_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_12_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_13_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_13_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_14_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_14_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_15_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_15_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_16_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_16_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_17_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_17_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_18_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_18_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_19_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_19_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_20_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_20_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_21_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_21_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_22_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_22_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_23_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_23_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_24_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_24_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_25_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_25_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_26_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_26_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_27_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_27_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_28_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_28_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_29_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_29_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_30_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_30_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_31_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_31_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_32_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_32_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_33_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_33_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_34_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_34_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_35_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_35_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_36_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_36_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_37_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_37_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_38_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_38_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_39_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_39_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_40_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_40_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_41_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_41_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_42_we = addr_hit[43] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_42_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_43_we = addr_hit[44] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_43_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_44_we = addr_hit[45] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_44_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_45_we = addr_hit[46] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_45_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_46_we = addr_hit[47] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_46_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_47_we = addr_hit[48] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_47_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_48_we = addr_hit[49] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_48_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_49_we = addr_hit[50] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_49_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_50_we = addr_hit[51] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_50_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_51_we = addr_hit[52] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_51_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_52_we = addr_hit[53] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_52_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_53_we = addr_hit[54] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_53_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_54_we = addr_hit[55] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_54_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_55_we = addr_hit[56] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_55_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_56_we = addr_hit[57] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_56_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_57_we = addr_hit[58] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_57_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_58_we = addr_hit[59] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_58_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_59_we = addr_hit[60] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_59_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_60_we = addr_hit[61] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_60_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_61_we = addr_hit[62] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_61_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_62_we = addr_hit[63] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_62_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_63_we = addr_hit[64] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_63_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_64_we = addr_hit[65] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_64_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_65_we = addr_hit[66] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_65_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_66_we = addr_hit[67] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_66_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_67_we = addr_hit[68] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_67_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_68_we = addr_hit[69] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_68_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_69_we = addr_hit[70] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_69_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_70_we = addr_hit[71] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_70_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_71_we = addr_hit[72] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_71_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_72_we = addr_hit[73] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_72_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_73_we = addr_hit[74] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_73_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_74_we = addr_hit[75] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_74_wd = reg_wdata[0];
+ assign mio_periph_insel_regwen_75_we = addr_hit[76] & reg_we & !reg_error;
+
+ assign mio_periph_insel_regwen_75_wd = reg_wdata[0];
+ assign mio_periph_insel_0_we = addr_hit[77] & reg_we & !reg_error;
+
+ assign mio_periph_insel_0_wd = reg_wdata[5:0];
+ assign mio_periph_insel_1_we = addr_hit[78] & reg_we & !reg_error;
+
+ assign mio_periph_insel_1_wd = reg_wdata[5:0];
+ assign mio_periph_insel_2_we = addr_hit[79] & reg_we & !reg_error;
+
+ assign mio_periph_insel_2_wd = reg_wdata[5:0];
+ assign mio_periph_insel_3_we = addr_hit[80] & reg_we & !reg_error;
+
+ assign mio_periph_insel_3_wd = reg_wdata[5:0];
+ assign mio_periph_insel_4_we = addr_hit[81] & reg_we & !reg_error;
+
+ assign mio_periph_insel_4_wd = reg_wdata[5:0];
+ assign mio_periph_insel_5_we = addr_hit[82] & reg_we & !reg_error;
+
+ assign mio_periph_insel_5_wd = reg_wdata[5:0];
+ assign mio_periph_insel_6_we = addr_hit[83] & reg_we & !reg_error;
+
+ assign mio_periph_insel_6_wd = reg_wdata[5:0];
+ assign mio_periph_insel_7_we = addr_hit[84] & reg_we & !reg_error;
+
+ assign mio_periph_insel_7_wd = reg_wdata[5:0];
+ assign mio_periph_insel_8_we = addr_hit[85] & reg_we & !reg_error;
+
+ assign mio_periph_insel_8_wd = reg_wdata[5:0];
+ assign mio_periph_insel_9_we = addr_hit[86] & reg_we & !reg_error;
+
+ assign mio_periph_insel_9_wd = reg_wdata[5:0];
+ assign mio_periph_insel_10_we = addr_hit[87] & reg_we & !reg_error;
+
+ assign mio_periph_insel_10_wd = reg_wdata[5:0];
+ assign mio_periph_insel_11_we = addr_hit[88] & reg_we & !reg_error;
+
+ assign mio_periph_insel_11_wd = reg_wdata[5:0];
+ assign mio_periph_insel_12_we = addr_hit[89] & reg_we & !reg_error;
+
+ assign mio_periph_insel_12_wd = reg_wdata[5:0];
+ assign mio_periph_insel_13_we = addr_hit[90] & reg_we & !reg_error;
+
+ assign mio_periph_insel_13_wd = reg_wdata[5:0];
+ assign mio_periph_insel_14_we = addr_hit[91] & reg_we & !reg_error;
+
+ assign mio_periph_insel_14_wd = reg_wdata[5:0];
+ assign mio_periph_insel_15_we = addr_hit[92] & reg_we & !reg_error;
+
+ assign mio_periph_insel_15_wd = reg_wdata[5:0];
+ assign mio_periph_insel_16_we = addr_hit[93] & reg_we & !reg_error;
+
+ assign mio_periph_insel_16_wd = reg_wdata[5:0];
+ assign mio_periph_insel_17_we = addr_hit[94] & reg_we & !reg_error;
+
+ assign mio_periph_insel_17_wd = reg_wdata[5:0];
+ assign mio_periph_insel_18_we = addr_hit[95] & reg_we & !reg_error;
+
+ assign mio_periph_insel_18_wd = reg_wdata[5:0];
+ assign mio_periph_insel_19_we = addr_hit[96] & reg_we & !reg_error;
+
+ assign mio_periph_insel_19_wd = reg_wdata[5:0];
+ assign mio_periph_insel_20_we = addr_hit[97] & reg_we & !reg_error;
+
+ assign mio_periph_insel_20_wd = reg_wdata[5:0];
+ assign mio_periph_insel_21_we = addr_hit[98] & reg_we & !reg_error;
+
+ assign mio_periph_insel_21_wd = reg_wdata[5:0];
+ assign mio_periph_insel_22_we = addr_hit[99] & reg_we & !reg_error;
+
+ assign mio_periph_insel_22_wd = reg_wdata[5:0];
+ assign mio_periph_insel_23_we = addr_hit[100] & reg_we & !reg_error;
+
+ assign mio_periph_insel_23_wd = reg_wdata[5:0];
+ assign mio_periph_insel_24_we = addr_hit[101] & reg_we & !reg_error;
+
+ assign mio_periph_insel_24_wd = reg_wdata[5:0];
+ assign mio_periph_insel_25_we = addr_hit[102] & reg_we & !reg_error;
+
+ assign mio_periph_insel_25_wd = reg_wdata[5:0];
+ assign mio_periph_insel_26_we = addr_hit[103] & reg_we & !reg_error;
+
+ assign mio_periph_insel_26_wd = reg_wdata[5:0];
+ assign mio_periph_insel_27_we = addr_hit[104] & reg_we & !reg_error;
+
+ assign mio_periph_insel_27_wd = reg_wdata[5:0];
+ assign mio_periph_insel_28_we = addr_hit[105] & reg_we & !reg_error;
+
+ assign mio_periph_insel_28_wd = reg_wdata[5:0];
+ assign mio_periph_insel_29_we = addr_hit[106] & reg_we & !reg_error;
+
+ assign mio_periph_insel_29_wd = reg_wdata[5:0];
+ assign mio_periph_insel_30_we = addr_hit[107] & reg_we & !reg_error;
+
+ assign mio_periph_insel_30_wd = reg_wdata[5:0];
+ assign mio_periph_insel_31_we = addr_hit[108] & reg_we & !reg_error;
+
+ assign mio_periph_insel_31_wd = reg_wdata[5:0];
+ assign mio_periph_insel_32_we = addr_hit[109] & reg_we & !reg_error;
+
+ assign mio_periph_insel_32_wd = reg_wdata[5:0];
+ assign mio_periph_insel_33_we = addr_hit[110] & reg_we & !reg_error;
+
+ assign mio_periph_insel_33_wd = reg_wdata[5:0];
+ assign mio_periph_insel_34_we = addr_hit[111] & reg_we & !reg_error;
+
+ assign mio_periph_insel_34_wd = reg_wdata[5:0];
+ assign mio_periph_insel_35_we = addr_hit[112] & reg_we & !reg_error;
+
+ assign mio_periph_insel_35_wd = reg_wdata[5:0];
+ assign mio_periph_insel_36_we = addr_hit[113] & reg_we & !reg_error;
+
+ assign mio_periph_insel_36_wd = reg_wdata[5:0];
+ assign mio_periph_insel_37_we = addr_hit[114] & reg_we & !reg_error;
+
+ assign mio_periph_insel_37_wd = reg_wdata[5:0];
+ assign mio_periph_insel_38_we = addr_hit[115] & reg_we & !reg_error;
+
+ assign mio_periph_insel_38_wd = reg_wdata[5:0];
+ assign mio_periph_insel_39_we = addr_hit[116] & reg_we & !reg_error;
+
+ assign mio_periph_insel_39_wd = reg_wdata[5:0];
+ assign mio_periph_insel_40_we = addr_hit[117] & reg_we & !reg_error;
+
+ assign mio_periph_insel_40_wd = reg_wdata[5:0];
+ assign mio_periph_insel_41_we = addr_hit[118] & reg_we & !reg_error;
+
+ assign mio_periph_insel_41_wd = reg_wdata[5:0];
+ assign mio_periph_insel_42_we = addr_hit[119] & reg_we & !reg_error;
+
+ assign mio_periph_insel_42_wd = reg_wdata[5:0];
+ assign mio_periph_insel_43_we = addr_hit[120] & reg_we & !reg_error;
+
+ assign mio_periph_insel_43_wd = reg_wdata[5:0];
+ assign mio_periph_insel_44_we = addr_hit[121] & reg_we & !reg_error;
+
+ assign mio_periph_insel_44_wd = reg_wdata[5:0];
+ assign mio_periph_insel_45_we = addr_hit[122] & reg_we & !reg_error;
+
+ assign mio_periph_insel_45_wd = reg_wdata[5:0];
+ assign mio_periph_insel_46_we = addr_hit[123] & reg_we & !reg_error;
+
+ assign mio_periph_insel_46_wd = reg_wdata[5:0];
+ assign mio_periph_insel_47_we = addr_hit[124] & reg_we & !reg_error;
+
+ assign mio_periph_insel_47_wd = reg_wdata[5:0];
+ assign mio_periph_insel_48_we = addr_hit[125] & reg_we & !reg_error;
+
+ assign mio_periph_insel_48_wd = reg_wdata[5:0];
+ assign mio_periph_insel_49_we = addr_hit[126] & reg_we & !reg_error;
+
+ assign mio_periph_insel_49_wd = reg_wdata[5:0];
+ assign mio_periph_insel_50_we = addr_hit[127] & reg_we & !reg_error;
+
+ assign mio_periph_insel_50_wd = reg_wdata[5:0];
+ assign mio_periph_insel_51_we = addr_hit[128] & reg_we & !reg_error;
+
+ assign mio_periph_insel_51_wd = reg_wdata[5:0];
+ assign mio_periph_insel_52_we = addr_hit[129] & reg_we & !reg_error;
+
+ assign mio_periph_insel_52_wd = reg_wdata[5:0];
+ assign mio_periph_insel_53_we = addr_hit[130] & reg_we & !reg_error;
+
+ assign mio_periph_insel_53_wd = reg_wdata[5:0];
+ assign mio_periph_insel_54_we = addr_hit[131] & reg_we & !reg_error;
+
+ assign mio_periph_insel_54_wd = reg_wdata[5:0];
+ assign mio_periph_insel_55_we = addr_hit[132] & reg_we & !reg_error;
+
+ assign mio_periph_insel_55_wd = reg_wdata[5:0];
+ assign mio_periph_insel_56_we = addr_hit[133] & reg_we & !reg_error;
+
+ assign mio_periph_insel_56_wd = reg_wdata[5:0];
+ assign mio_periph_insel_57_we = addr_hit[134] & reg_we & !reg_error;
+
+ assign mio_periph_insel_57_wd = reg_wdata[5:0];
+ assign mio_periph_insel_58_we = addr_hit[135] & reg_we & !reg_error;
+
+ assign mio_periph_insel_58_wd = reg_wdata[5:0];
+ assign mio_periph_insel_59_we = addr_hit[136] & reg_we & !reg_error;
+
+ assign mio_periph_insel_59_wd = reg_wdata[5:0];
+ assign mio_periph_insel_60_we = addr_hit[137] & reg_we & !reg_error;
+
+ assign mio_periph_insel_60_wd = reg_wdata[5:0];
+ assign mio_periph_insel_61_we = addr_hit[138] & reg_we & !reg_error;
+
+ assign mio_periph_insel_61_wd = reg_wdata[5:0];
+ assign mio_periph_insel_62_we = addr_hit[139] & reg_we & !reg_error;
+
+ assign mio_periph_insel_62_wd = reg_wdata[5:0];
+ assign mio_periph_insel_63_we = addr_hit[140] & reg_we & !reg_error;
+
+ assign mio_periph_insel_63_wd = reg_wdata[5:0];
+ assign mio_periph_insel_64_we = addr_hit[141] & reg_we & !reg_error;
+
+ assign mio_periph_insel_64_wd = reg_wdata[5:0];
+ assign mio_periph_insel_65_we = addr_hit[142] & reg_we & !reg_error;
+
+ assign mio_periph_insel_65_wd = reg_wdata[5:0];
+ assign mio_periph_insel_66_we = addr_hit[143] & reg_we & !reg_error;
+
+ assign mio_periph_insel_66_wd = reg_wdata[5:0];
+ assign mio_periph_insel_67_we = addr_hit[144] & reg_we & !reg_error;
+
+ assign mio_periph_insel_67_wd = reg_wdata[5:0];
+ assign mio_periph_insel_68_we = addr_hit[145] & reg_we & !reg_error;
+
+ assign mio_periph_insel_68_wd = reg_wdata[5:0];
+ assign mio_periph_insel_69_we = addr_hit[146] & reg_we & !reg_error;
+
+ assign mio_periph_insel_69_wd = reg_wdata[5:0];
+ assign mio_periph_insel_70_we = addr_hit[147] & reg_we & !reg_error;
+
+ assign mio_periph_insel_70_wd = reg_wdata[5:0];
+ assign mio_periph_insel_71_we = addr_hit[148] & reg_we & !reg_error;
+
+ assign mio_periph_insel_71_wd = reg_wdata[5:0];
+ assign mio_periph_insel_72_we = addr_hit[149] & reg_we & !reg_error;
+
+ assign mio_periph_insel_72_wd = reg_wdata[5:0];
+ assign mio_periph_insel_73_we = addr_hit[150] & reg_we & !reg_error;
+
+ assign mio_periph_insel_73_wd = reg_wdata[5:0];
+ assign mio_periph_insel_74_we = addr_hit[151] & reg_we & !reg_error;
+
+ assign mio_periph_insel_74_wd = reg_wdata[5:0];
+ assign mio_periph_insel_75_we = addr_hit[152] & reg_we & !reg_error;
+
+ assign mio_periph_insel_75_wd = reg_wdata[5:0];
+ assign mio_outsel_regwen_0_we = addr_hit[153] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_0_wd = reg_wdata[0];
+ assign mio_outsel_regwen_1_we = addr_hit[154] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_1_wd = reg_wdata[0];
+ assign mio_outsel_regwen_2_we = addr_hit[155] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_2_wd = reg_wdata[0];
+ assign mio_outsel_regwen_3_we = addr_hit[156] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_3_wd = reg_wdata[0];
+ assign mio_outsel_regwen_4_we = addr_hit[157] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_4_wd = reg_wdata[0];
+ assign mio_outsel_regwen_5_we = addr_hit[158] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_5_wd = reg_wdata[0];
+ assign mio_outsel_regwen_6_we = addr_hit[159] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_6_wd = reg_wdata[0];
+ assign mio_outsel_regwen_7_we = addr_hit[160] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_7_wd = reg_wdata[0];
+ assign mio_outsel_regwen_8_we = addr_hit[161] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_8_wd = reg_wdata[0];
+ assign mio_outsel_regwen_9_we = addr_hit[162] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_9_wd = reg_wdata[0];
+ assign mio_outsel_regwen_10_we = addr_hit[163] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_10_wd = reg_wdata[0];
+ assign mio_outsel_regwen_11_we = addr_hit[164] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_11_wd = reg_wdata[0];
+ assign mio_outsel_regwen_12_we = addr_hit[165] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_12_wd = reg_wdata[0];
+ assign mio_outsel_regwen_13_we = addr_hit[166] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_13_wd = reg_wdata[0];
+ assign mio_outsel_regwen_14_we = addr_hit[167] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_14_wd = reg_wdata[0];
+ assign mio_outsel_regwen_15_we = addr_hit[168] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_15_wd = reg_wdata[0];
+ assign mio_outsel_regwen_16_we = addr_hit[169] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_16_wd = reg_wdata[0];
+ assign mio_outsel_regwen_17_we = addr_hit[170] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_17_wd = reg_wdata[0];
+ assign mio_outsel_regwen_18_we = addr_hit[171] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_18_wd = reg_wdata[0];
+ assign mio_outsel_regwen_19_we = addr_hit[172] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_19_wd = reg_wdata[0];
+ assign mio_outsel_regwen_20_we = addr_hit[173] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_20_wd = reg_wdata[0];
+ assign mio_outsel_regwen_21_we = addr_hit[174] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_21_wd = reg_wdata[0];
+ assign mio_outsel_regwen_22_we = addr_hit[175] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_22_wd = reg_wdata[0];
+ assign mio_outsel_regwen_23_we = addr_hit[176] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_23_wd = reg_wdata[0];
+ assign mio_outsel_regwen_24_we = addr_hit[177] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_24_wd = reg_wdata[0];
+ assign mio_outsel_regwen_25_we = addr_hit[178] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_25_wd = reg_wdata[0];
+ assign mio_outsel_regwen_26_we = addr_hit[179] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_26_wd = reg_wdata[0];
+ assign mio_outsel_regwen_27_we = addr_hit[180] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_27_wd = reg_wdata[0];
+ assign mio_outsel_regwen_28_we = addr_hit[181] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_28_wd = reg_wdata[0];
+ assign mio_outsel_regwen_29_we = addr_hit[182] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_29_wd = reg_wdata[0];
+ assign mio_outsel_regwen_30_we = addr_hit[183] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_30_wd = reg_wdata[0];
+ assign mio_outsel_regwen_31_we = addr_hit[184] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_31_wd = reg_wdata[0];
+ assign mio_outsel_regwen_32_we = addr_hit[185] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_32_wd = reg_wdata[0];
+ assign mio_outsel_regwen_33_we = addr_hit[186] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_33_wd = reg_wdata[0];
+ assign mio_outsel_regwen_34_we = addr_hit[187] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_34_wd = reg_wdata[0];
+ assign mio_outsel_regwen_35_we = addr_hit[188] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_35_wd = reg_wdata[0];
+ assign mio_outsel_regwen_36_we = addr_hit[189] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_36_wd = reg_wdata[0];
+ assign mio_outsel_regwen_37_we = addr_hit[190] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_37_wd = reg_wdata[0];
+ assign mio_outsel_regwen_38_we = addr_hit[191] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_38_wd = reg_wdata[0];
+ assign mio_outsel_regwen_39_we = addr_hit[192] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_39_wd = reg_wdata[0];
+ assign mio_outsel_regwen_40_we = addr_hit[193] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_40_wd = reg_wdata[0];
+ assign mio_outsel_regwen_41_we = addr_hit[194] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_41_wd = reg_wdata[0];
+ assign mio_outsel_regwen_42_we = addr_hit[195] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_42_wd = reg_wdata[0];
+ assign mio_outsel_regwen_43_we = addr_hit[196] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_43_wd = reg_wdata[0];
+ assign mio_outsel_regwen_44_we = addr_hit[197] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_44_wd = reg_wdata[0];
+ assign mio_outsel_regwen_45_we = addr_hit[198] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_45_wd = reg_wdata[0];
+ assign mio_outsel_regwen_46_we = addr_hit[199] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_46_wd = reg_wdata[0];
+ assign mio_outsel_regwen_47_we = addr_hit[200] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_47_wd = reg_wdata[0];
+ assign mio_outsel_regwen_48_we = addr_hit[201] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_48_wd = reg_wdata[0];
+ assign mio_outsel_regwen_49_we = addr_hit[202] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_49_wd = reg_wdata[0];
+ assign mio_outsel_regwen_50_we = addr_hit[203] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_50_wd = reg_wdata[0];
+ assign mio_outsel_regwen_51_we = addr_hit[204] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_51_wd = reg_wdata[0];
+ assign mio_outsel_regwen_52_we = addr_hit[205] & reg_we & !reg_error;
+
+ assign mio_outsel_regwen_52_wd = reg_wdata[0];
+ assign mio_outsel_0_we = addr_hit[206] & reg_we & !reg_error;
+
+ assign mio_outsel_0_wd = reg_wdata[6:0];
+ assign mio_outsel_1_we = addr_hit[207] & reg_we & !reg_error;
+
+ assign mio_outsel_1_wd = reg_wdata[6:0];
+ assign mio_outsel_2_we = addr_hit[208] & reg_we & !reg_error;
+
+ assign mio_outsel_2_wd = reg_wdata[6:0];
+ assign mio_outsel_3_we = addr_hit[209] & reg_we & !reg_error;
+
+ assign mio_outsel_3_wd = reg_wdata[6:0];
+ assign mio_outsel_4_we = addr_hit[210] & reg_we & !reg_error;
+
+ assign mio_outsel_4_wd = reg_wdata[6:0];
+ assign mio_outsel_5_we = addr_hit[211] & reg_we & !reg_error;
+
+ assign mio_outsel_5_wd = reg_wdata[6:0];
+ assign mio_outsel_6_we = addr_hit[212] & reg_we & !reg_error;
+
+ assign mio_outsel_6_wd = reg_wdata[6:0];
+ assign mio_outsel_7_we = addr_hit[213] & reg_we & !reg_error;
+
+ assign mio_outsel_7_wd = reg_wdata[6:0];
+ assign mio_outsel_8_we = addr_hit[214] & reg_we & !reg_error;
+
+ assign mio_outsel_8_wd = reg_wdata[6:0];
+ assign mio_outsel_9_we = addr_hit[215] & reg_we & !reg_error;
+
+ assign mio_outsel_9_wd = reg_wdata[6:0];
+ assign mio_outsel_10_we = addr_hit[216] & reg_we & !reg_error;
+
+ assign mio_outsel_10_wd = reg_wdata[6:0];
+ assign mio_outsel_11_we = addr_hit[217] & reg_we & !reg_error;
+
+ assign mio_outsel_11_wd = reg_wdata[6:0];
+ assign mio_outsel_12_we = addr_hit[218] & reg_we & !reg_error;
+
+ assign mio_outsel_12_wd = reg_wdata[6:0];
+ assign mio_outsel_13_we = addr_hit[219] & reg_we & !reg_error;
+
+ assign mio_outsel_13_wd = reg_wdata[6:0];
+ assign mio_outsel_14_we = addr_hit[220] & reg_we & !reg_error;
+
+ assign mio_outsel_14_wd = reg_wdata[6:0];
+ assign mio_outsel_15_we = addr_hit[221] & reg_we & !reg_error;
+
+ assign mio_outsel_15_wd = reg_wdata[6:0];
+ assign mio_outsel_16_we = addr_hit[222] & reg_we & !reg_error;
+
+ assign mio_outsel_16_wd = reg_wdata[6:0];
+ assign mio_outsel_17_we = addr_hit[223] & reg_we & !reg_error;
+
+ assign mio_outsel_17_wd = reg_wdata[6:0];
+ assign mio_outsel_18_we = addr_hit[224] & reg_we & !reg_error;
+
+ assign mio_outsel_18_wd = reg_wdata[6:0];
+ assign mio_outsel_19_we = addr_hit[225] & reg_we & !reg_error;
+
+ assign mio_outsel_19_wd = reg_wdata[6:0];
+ assign mio_outsel_20_we = addr_hit[226] & reg_we & !reg_error;
+
+ assign mio_outsel_20_wd = reg_wdata[6:0];
+ assign mio_outsel_21_we = addr_hit[227] & reg_we & !reg_error;
+
+ assign mio_outsel_21_wd = reg_wdata[6:0];
+ assign mio_outsel_22_we = addr_hit[228] & reg_we & !reg_error;
+
+ assign mio_outsel_22_wd = reg_wdata[6:0];
+ assign mio_outsel_23_we = addr_hit[229] & reg_we & !reg_error;
+
+ assign mio_outsel_23_wd = reg_wdata[6:0];
+ assign mio_outsel_24_we = addr_hit[230] & reg_we & !reg_error;
+
+ assign mio_outsel_24_wd = reg_wdata[6:0];
+ assign mio_outsel_25_we = addr_hit[231] & reg_we & !reg_error;
+
+ assign mio_outsel_25_wd = reg_wdata[6:0];
+ assign mio_outsel_26_we = addr_hit[232] & reg_we & !reg_error;
+
+ assign mio_outsel_26_wd = reg_wdata[6:0];
+ assign mio_outsel_27_we = addr_hit[233] & reg_we & !reg_error;
+
+ assign mio_outsel_27_wd = reg_wdata[6:0];
+ assign mio_outsel_28_we = addr_hit[234] & reg_we & !reg_error;
+
+ assign mio_outsel_28_wd = reg_wdata[6:0];
+ assign mio_outsel_29_we = addr_hit[235] & reg_we & !reg_error;
+
+ assign mio_outsel_29_wd = reg_wdata[6:0];
+ assign mio_outsel_30_we = addr_hit[236] & reg_we & !reg_error;
+
+ assign mio_outsel_30_wd = reg_wdata[6:0];
+ assign mio_outsel_31_we = addr_hit[237] & reg_we & !reg_error;
+
+ assign mio_outsel_31_wd = reg_wdata[6:0];
+ assign mio_outsel_32_we = addr_hit[238] & reg_we & !reg_error;
+
+ assign mio_outsel_32_wd = reg_wdata[6:0];
+ assign mio_outsel_33_we = addr_hit[239] & reg_we & !reg_error;
+
+ assign mio_outsel_33_wd = reg_wdata[6:0];
+ assign mio_outsel_34_we = addr_hit[240] & reg_we & !reg_error;
+
+ assign mio_outsel_34_wd = reg_wdata[6:0];
+ assign mio_outsel_35_we = addr_hit[241] & reg_we & !reg_error;
+
+ assign mio_outsel_35_wd = reg_wdata[6:0];
+ assign mio_outsel_36_we = addr_hit[242] & reg_we & !reg_error;
+
+ assign mio_outsel_36_wd = reg_wdata[6:0];
+ assign mio_outsel_37_we = addr_hit[243] & reg_we & !reg_error;
+
+ assign mio_outsel_37_wd = reg_wdata[6:0];
+ assign mio_outsel_38_we = addr_hit[244] & reg_we & !reg_error;
+
+ assign mio_outsel_38_wd = reg_wdata[6:0];
+ assign mio_outsel_39_we = addr_hit[245] & reg_we & !reg_error;
+
+ assign mio_outsel_39_wd = reg_wdata[6:0];
+ assign mio_outsel_40_we = addr_hit[246] & reg_we & !reg_error;
+
+ assign mio_outsel_40_wd = reg_wdata[6:0];
+ assign mio_outsel_41_we = addr_hit[247] & reg_we & !reg_error;
+
+ assign mio_outsel_41_wd = reg_wdata[6:0];
+ assign mio_outsel_42_we = addr_hit[248] & reg_we & !reg_error;
+
+ assign mio_outsel_42_wd = reg_wdata[6:0];
+ assign mio_outsel_43_we = addr_hit[249] & reg_we & !reg_error;
+
+ assign mio_outsel_43_wd = reg_wdata[6:0];
+ assign mio_outsel_44_we = addr_hit[250] & reg_we & !reg_error;
+
+ assign mio_outsel_44_wd = reg_wdata[6:0];
+ assign mio_outsel_45_we = addr_hit[251] & reg_we & !reg_error;
+
+ assign mio_outsel_45_wd = reg_wdata[6:0];
+ assign mio_outsel_46_we = addr_hit[252] & reg_we & !reg_error;
+
+ assign mio_outsel_46_wd = reg_wdata[6:0];
+ assign mio_outsel_47_we = addr_hit[253] & reg_we & !reg_error;
+
+ assign mio_outsel_47_wd = reg_wdata[6:0];
+ assign mio_outsel_48_we = addr_hit[254] & reg_we & !reg_error;
+
+ assign mio_outsel_48_wd = reg_wdata[6:0];
+ assign mio_outsel_49_we = addr_hit[255] & reg_we & !reg_error;
+
+ assign mio_outsel_49_wd = reg_wdata[6:0];
+ assign mio_outsel_50_we = addr_hit[256] & reg_we & !reg_error;
+
+ assign mio_outsel_50_wd = reg_wdata[6:0];
+ assign mio_outsel_51_we = addr_hit[257] & reg_we & !reg_error;
+
+ assign mio_outsel_51_wd = reg_wdata[6:0];
+ assign mio_outsel_52_we = addr_hit[258] & reg_we & !reg_error;
+
+ assign mio_outsel_52_wd = reg_wdata[6:0];
+ assign mio_pad_attr_regwen_0_we = addr_hit[259] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_1_we = addr_hit[260] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_2_we = addr_hit[261] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_3_we = addr_hit[262] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_4_we = addr_hit[263] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_5_we = addr_hit[264] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_6_we = addr_hit[265] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_7_we = addr_hit[266] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_8_we = addr_hit[267] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_9_we = addr_hit[268] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_10_we = addr_hit[269] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_11_we = addr_hit[270] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_12_we = addr_hit[271] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_13_we = addr_hit[272] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_14_we = addr_hit[273] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_15_we = addr_hit[274] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_16_we = addr_hit[275] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_17_we = addr_hit[276] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_18_we = addr_hit[277] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_19_we = addr_hit[278] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_20_we = addr_hit[279] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_21_we = addr_hit[280] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_22_we = addr_hit[281] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_23_we = addr_hit[282] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_24_we = addr_hit[283] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_25_we = addr_hit[284] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_26_we = addr_hit[285] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_27_we = addr_hit[286] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_28_we = addr_hit[287] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_29_we = addr_hit[288] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_30_we = addr_hit[289] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_31_we = addr_hit[290] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_32_we = addr_hit[291] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_32_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_33_we = addr_hit[292] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_33_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_34_we = addr_hit[293] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_34_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_35_we = addr_hit[294] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_35_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_36_we = addr_hit[295] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_36_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_37_we = addr_hit[296] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_37_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_38_we = addr_hit[297] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_38_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_39_we = addr_hit[298] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_39_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_40_we = addr_hit[299] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_40_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_41_we = addr_hit[300] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_41_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_42_we = addr_hit[301] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_42_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_43_we = addr_hit[302] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_43_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_44_we = addr_hit[303] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_44_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_45_we = addr_hit[304] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_45_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_46_we = addr_hit[305] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_46_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_47_we = addr_hit[306] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_47_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_48_we = addr_hit[307] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_48_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_49_we = addr_hit[308] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_49_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_50_we = addr_hit[309] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_50_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_51_we = addr_hit[310] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_51_wd = reg_wdata[0];
+ assign mio_pad_attr_regwen_52_we = addr_hit[311] & reg_we & !reg_error;
+
+ assign mio_pad_attr_regwen_52_wd = reg_wdata[0];
+ assign mio_pad_attr_0_re = addr_hit[312] & reg_re & !reg_error;
+ assign mio_pad_attr_0_we = addr_hit[312] & reg_we & !reg_error;
+
+ assign mio_pad_attr_0_invert_0_wd = reg_wdata[0];
+
+ assign mio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1];
+
+ assign mio_pad_attr_0_pull_en_0_wd = reg_wdata[2];
+
+ assign mio_pad_attr_0_pull_select_0_wd = reg_wdata[3];
+
+ assign mio_pad_attr_0_keeper_en_0_wd = reg_wdata[4];
+
+ assign mio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5];
+
+ assign mio_pad_attr_0_od_en_0_wd = reg_wdata[6];
+
+ assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20];
+ assign mio_pad_attr_1_re = addr_hit[313] & reg_re & !reg_error;
+ assign mio_pad_attr_1_we = addr_hit[313] & reg_we & !reg_error;
+
+ assign mio_pad_attr_1_invert_1_wd = reg_wdata[0];
+
+ assign mio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1];
+
+ assign mio_pad_attr_1_pull_en_1_wd = reg_wdata[2];
+
+ assign mio_pad_attr_1_pull_select_1_wd = reg_wdata[3];
+
+ assign mio_pad_attr_1_keeper_en_1_wd = reg_wdata[4];
+
+ assign mio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5];
+
+ assign mio_pad_attr_1_od_en_1_wd = reg_wdata[6];
+
+ assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20];
+ assign mio_pad_attr_2_re = addr_hit[314] & reg_re & !reg_error;
+ assign mio_pad_attr_2_we = addr_hit[314] & reg_we & !reg_error;
+
+ assign mio_pad_attr_2_invert_2_wd = reg_wdata[0];
+
+ assign mio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1];
+
+ assign mio_pad_attr_2_pull_en_2_wd = reg_wdata[2];
+
+ assign mio_pad_attr_2_pull_select_2_wd = reg_wdata[3];
+
+ assign mio_pad_attr_2_keeper_en_2_wd = reg_wdata[4];
+
+ assign mio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5];
+
+ assign mio_pad_attr_2_od_en_2_wd = reg_wdata[6];
+
+ assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20];
+ assign mio_pad_attr_3_re = addr_hit[315] & reg_re & !reg_error;
+ assign mio_pad_attr_3_we = addr_hit[315] & reg_we & !reg_error;
+
+ assign mio_pad_attr_3_invert_3_wd = reg_wdata[0];
+
+ assign mio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1];
+
+ assign mio_pad_attr_3_pull_en_3_wd = reg_wdata[2];
+
+ assign mio_pad_attr_3_pull_select_3_wd = reg_wdata[3];
+
+ assign mio_pad_attr_3_keeper_en_3_wd = reg_wdata[4];
+
+ assign mio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5];
+
+ assign mio_pad_attr_3_od_en_3_wd = reg_wdata[6];
+
+ assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20];
+ assign mio_pad_attr_4_re = addr_hit[316] & reg_re & !reg_error;
+ assign mio_pad_attr_4_we = addr_hit[316] & reg_we & !reg_error;
+
+ assign mio_pad_attr_4_invert_4_wd = reg_wdata[0];
+
+ assign mio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1];
+
+ assign mio_pad_attr_4_pull_en_4_wd = reg_wdata[2];
+
+ assign mio_pad_attr_4_pull_select_4_wd = reg_wdata[3];
+
+ assign mio_pad_attr_4_keeper_en_4_wd = reg_wdata[4];
+
+ assign mio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5];
+
+ assign mio_pad_attr_4_od_en_4_wd = reg_wdata[6];
+
+ assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20];
+ assign mio_pad_attr_5_re = addr_hit[317] & reg_re & !reg_error;
+ assign mio_pad_attr_5_we = addr_hit[317] & reg_we & !reg_error;
+
+ assign mio_pad_attr_5_invert_5_wd = reg_wdata[0];
+
+ assign mio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1];
+
+ assign mio_pad_attr_5_pull_en_5_wd = reg_wdata[2];
+
+ assign mio_pad_attr_5_pull_select_5_wd = reg_wdata[3];
+
+ assign mio_pad_attr_5_keeper_en_5_wd = reg_wdata[4];
+
+ assign mio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5];
+
+ assign mio_pad_attr_5_od_en_5_wd = reg_wdata[6];
+
+ assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20];
+ assign mio_pad_attr_6_re = addr_hit[318] & reg_re & !reg_error;
+ assign mio_pad_attr_6_we = addr_hit[318] & reg_we & !reg_error;
+
+ assign mio_pad_attr_6_invert_6_wd = reg_wdata[0];
+
+ assign mio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1];
+
+ assign mio_pad_attr_6_pull_en_6_wd = reg_wdata[2];
+
+ assign mio_pad_attr_6_pull_select_6_wd = reg_wdata[3];
+
+ assign mio_pad_attr_6_keeper_en_6_wd = reg_wdata[4];
+
+ assign mio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5];
+
+ assign mio_pad_attr_6_od_en_6_wd = reg_wdata[6];
+
+ assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20];
+ assign mio_pad_attr_7_re = addr_hit[319] & reg_re & !reg_error;
+ assign mio_pad_attr_7_we = addr_hit[319] & reg_we & !reg_error;
+
+ assign mio_pad_attr_7_invert_7_wd = reg_wdata[0];
+
+ assign mio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1];
+
+ assign mio_pad_attr_7_pull_en_7_wd = reg_wdata[2];
+
+ assign mio_pad_attr_7_pull_select_7_wd = reg_wdata[3];
+
+ assign mio_pad_attr_7_keeper_en_7_wd = reg_wdata[4];
+
+ assign mio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5];
+
+ assign mio_pad_attr_7_od_en_7_wd = reg_wdata[6];
+
+ assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20];
+ assign mio_pad_attr_8_re = addr_hit[320] & reg_re & !reg_error;
+ assign mio_pad_attr_8_we = addr_hit[320] & reg_we & !reg_error;
+
+ assign mio_pad_attr_8_invert_8_wd = reg_wdata[0];
+
+ assign mio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1];
+
+ assign mio_pad_attr_8_pull_en_8_wd = reg_wdata[2];
+
+ assign mio_pad_attr_8_pull_select_8_wd = reg_wdata[3];
+
+ assign mio_pad_attr_8_keeper_en_8_wd = reg_wdata[4];
+
+ assign mio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5];
+
+ assign mio_pad_attr_8_od_en_8_wd = reg_wdata[6];
+
+ assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20];
+ assign mio_pad_attr_9_re = addr_hit[321] & reg_re & !reg_error;
+ assign mio_pad_attr_9_we = addr_hit[321] & reg_we & !reg_error;
+
+ assign mio_pad_attr_9_invert_9_wd = reg_wdata[0];
+
+ assign mio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1];
+
+ assign mio_pad_attr_9_pull_en_9_wd = reg_wdata[2];
+
+ assign mio_pad_attr_9_pull_select_9_wd = reg_wdata[3];
+
+ assign mio_pad_attr_9_keeper_en_9_wd = reg_wdata[4];
+
+ assign mio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5];
+
+ assign mio_pad_attr_9_od_en_9_wd = reg_wdata[6];
+
+ assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20];
+ assign mio_pad_attr_10_re = addr_hit[322] & reg_re & !reg_error;
+ assign mio_pad_attr_10_we = addr_hit[322] & reg_we & !reg_error;
+
+ assign mio_pad_attr_10_invert_10_wd = reg_wdata[0];
+
+ assign mio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1];
+
+ assign mio_pad_attr_10_pull_en_10_wd = reg_wdata[2];
+
+ assign mio_pad_attr_10_pull_select_10_wd = reg_wdata[3];
+
+ assign mio_pad_attr_10_keeper_en_10_wd = reg_wdata[4];
+
+ assign mio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5];
+
+ assign mio_pad_attr_10_od_en_10_wd = reg_wdata[6];
+
+ assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20];
+ assign mio_pad_attr_11_re = addr_hit[323] & reg_re & !reg_error;
+ assign mio_pad_attr_11_we = addr_hit[323] & reg_we & !reg_error;
+
+ assign mio_pad_attr_11_invert_11_wd = reg_wdata[0];
+
+ assign mio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1];
+
+ assign mio_pad_attr_11_pull_en_11_wd = reg_wdata[2];
+
+ assign mio_pad_attr_11_pull_select_11_wd = reg_wdata[3];
+
+ assign mio_pad_attr_11_keeper_en_11_wd = reg_wdata[4];
+
+ assign mio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5];
+
+ assign mio_pad_attr_11_od_en_11_wd = reg_wdata[6];
+
+ assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20];
+ assign mio_pad_attr_12_re = addr_hit[324] & reg_re & !reg_error;
+ assign mio_pad_attr_12_we = addr_hit[324] & reg_we & !reg_error;
+
+ assign mio_pad_attr_12_invert_12_wd = reg_wdata[0];
+
+ assign mio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1];
+
+ assign mio_pad_attr_12_pull_en_12_wd = reg_wdata[2];
+
+ assign mio_pad_attr_12_pull_select_12_wd = reg_wdata[3];
+
+ assign mio_pad_attr_12_keeper_en_12_wd = reg_wdata[4];
+
+ assign mio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5];
+
+ assign mio_pad_attr_12_od_en_12_wd = reg_wdata[6];
+
+ assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20];
+ assign mio_pad_attr_13_re = addr_hit[325] & reg_re & !reg_error;
+ assign mio_pad_attr_13_we = addr_hit[325] & reg_we & !reg_error;
+
+ assign mio_pad_attr_13_invert_13_wd = reg_wdata[0];
+
+ assign mio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1];
+
+ assign mio_pad_attr_13_pull_en_13_wd = reg_wdata[2];
+
+ assign mio_pad_attr_13_pull_select_13_wd = reg_wdata[3];
+
+ assign mio_pad_attr_13_keeper_en_13_wd = reg_wdata[4];
+
+ assign mio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5];
+
+ assign mio_pad_attr_13_od_en_13_wd = reg_wdata[6];
+
+ assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20];
+ assign mio_pad_attr_14_re = addr_hit[326] & reg_re & !reg_error;
+ assign mio_pad_attr_14_we = addr_hit[326] & reg_we & !reg_error;
+
+ assign mio_pad_attr_14_invert_14_wd = reg_wdata[0];
+
+ assign mio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1];
+
+ assign mio_pad_attr_14_pull_en_14_wd = reg_wdata[2];
+
+ assign mio_pad_attr_14_pull_select_14_wd = reg_wdata[3];
+
+ assign mio_pad_attr_14_keeper_en_14_wd = reg_wdata[4];
+
+ assign mio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5];
+
+ assign mio_pad_attr_14_od_en_14_wd = reg_wdata[6];
+
+ assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20];
+ assign mio_pad_attr_15_re = addr_hit[327] & reg_re & !reg_error;
+ assign mio_pad_attr_15_we = addr_hit[327] & reg_we & !reg_error;
+
+ assign mio_pad_attr_15_invert_15_wd = reg_wdata[0];
+
+ assign mio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1];
+
+ assign mio_pad_attr_15_pull_en_15_wd = reg_wdata[2];
+
+ assign mio_pad_attr_15_pull_select_15_wd = reg_wdata[3];
+
+ assign mio_pad_attr_15_keeper_en_15_wd = reg_wdata[4];
+
+ assign mio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5];
+
+ assign mio_pad_attr_15_od_en_15_wd = reg_wdata[6];
+
+ assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20];
+ assign mio_pad_attr_16_re = addr_hit[328] & reg_re & !reg_error;
+ assign mio_pad_attr_16_we = addr_hit[328] & reg_we & !reg_error;
+
+ assign mio_pad_attr_16_invert_16_wd = reg_wdata[0];
+
+ assign mio_pad_attr_16_virtual_od_en_16_wd = reg_wdata[1];
+
+ assign mio_pad_attr_16_pull_en_16_wd = reg_wdata[2];
+
+ assign mio_pad_attr_16_pull_select_16_wd = reg_wdata[3];
+
+ assign mio_pad_attr_16_keeper_en_16_wd = reg_wdata[4];
+
+ assign mio_pad_attr_16_schmitt_en_16_wd = reg_wdata[5];
+
+ assign mio_pad_attr_16_od_en_16_wd = reg_wdata[6];
+
+ assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20];
+ assign mio_pad_attr_17_re = addr_hit[329] & reg_re & !reg_error;
+ assign mio_pad_attr_17_we = addr_hit[329] & reg_we & !reg_error;
+
+ assign mio_pad_attr_17_invert_17_wd = reg_wdata[0];
+
+ assign mio_pad_attr_17_virtual_od_en_17_wd = reg_wdata[1];
+
+ assign mio_pad_attr_17_pull_en_17_wd = reg_wdata[2];
+
+ assign mio_pad_attr_17_pull_select_17_wd = reg_wdata[3];
+
+ assign mio_pad_attr_17_keeper_en_17_wd = reg_wdata[4];
+
+ assign mio_pad_attr_17_schmitt_en_17_wd = reg_wdata[5];
+
+ assign mio_pad_attr_17_od_en_17_wd = reg_wdata[6];
+
+ assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20];
+ assign mio_pad_attr_18_re = addr_hit[330] & reg_re & !reg_error;
+ assign mio_pad_attr_18_we = addr_hit[330] & reg_we & !reg_error;
+
+ assign mio_pad_attr_18_invert_18_wd = reg_wdata[0];
+
+ assign mio_pad_attr_18_virtual_od_en_18_wd = reg_wdata[1];
+
+ assign mio_pad_attr_18_pull_en_18_wd = reg_wdata[2];
+
+ assign mio_pad_attr_18_pull_select_18_wd = reg_wdata[3];
+
+ assign mio_pad_attr_18_keeper_en_18_wd = reg_wdata[4];
+
+ assign mio_pad_attr_18_schmitt_en_18_wd = reg_wdata[5];
+
+ assign mio_pad_attr_18_od_en_18_wd = reg_wdata[6];
+
+ assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20];
+ assign mio_pad_attr_19_re = addr_hit[331] & reg_re & !reg_error;
+ assign mio_pad_attr_19_we = addr_hit[331] & reg_we & !reg_error;
+
+ assign mio_pad_attr_19_invert_19_wd = reg_wdata[0];
+
+ assign mio_pad_attr_19_virtual_od_en_19_wd = reg_wdata[1];
+
+ assign mio_pad_attr_19_pull_en_19_wd = reg_wdata[2];
+
+ assign mio_pad_attr_19_pull_select_19_wd = reg_wdata[3];
+
+ assign mio_pad_attr_19_keeper_en_19_wd = reg_wdata[4];
+
+ assign mio_pad_attr_19_schmitt_en_19_wd = reg_wdata[5];
+
+ assign mio_pad_attr_19_od_en_19_wd = reg_wdata[6];
+
+ assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20];
+ assign mio_pad_attr_20_re = addr_hit[332] & reg_re & !reg_error;
+ assign mio_pad_attr_20_we = addr_hit[332] & reg_we & !reg_error;
+
+ assign mio_pad_attr_20_invert_20_wd = reg_wdata[0];
+
+ assign mio_pad_attr_20_virtual_od_en_20_wd = reg_wdata[1];
+
+ assign mio_pad_attr_20_pull_en_20_wd = reg_wdata[2];
+
+ assign mio_pad_attr_20_pull_select_20_wd = reg_wdata[3];
+
+ assign mio_pad_attr_20_keeper_en_20_wd = reg_wdata[4];
+
+ assign mio_pad_attr_20_schmitt_en_20_wd = reg_wdata[5];
+
+ assign mio_pad_attr_20_od_en_20_wd = reg_wdata[6];
+
+ assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20];
+ assign mio_pad_attr_21_re = addr_hit[333] & reg_re & !reg_error;
+ assign mio_pad_attr_21_we = addr_hit[333] & reg_we & !reg_error;
+
+ assign mio_pad_attr_21_invert_21_wd = reg_wdata[0];
+
+ assign mio_pad_attr_21_virtual_od_en_21_wd = reg_wdata[1];
+
+ assign mio_pad_attr_21_pull_en_21_wd = reg_wdata[2];
+
+ assign mio_pad_attr_21_pull_select_21_wd = reg_wdata[3];
+
+ assign mio_pad_attr_21_keeper_en_21_wd = reg_wdata[4];
+
+ assign mio_pad_attr_21_schmitt_en_21_wd = reg_wdata[5];
+
+ assign mio_pad_attr_21_od_en_21_wd = reg_wdata[6];
+
+ assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20];
+ assign mio_pad_attr_22_re = addr_hit[334] & reg_re & !reg_error;
+ assign mio_pad_attr_22_we = addr_hit[334] & reg_we & !reg_error;
+
+ assign mio_pad_attr_22_invert_22_wd = reg_wdata[0];
+
+ assign mio_pad_attr_22_virtual_od_en_22_wd = reg_wdata[1];
+
+ assign mio_pad_attr_22_pull_en_22_wd = reg_wdata[2];
+
+ assign mio_pad_attr_22_pull_select_22_wd = reg_wdata[3];
+
+ assign mio_pad_attr_22_keeper_en_22_wd = reg_wdata[4];
+
+ assign mio_pad_attr_22_schmitt_en_22_wd = reg_wdata[5];
+
+ assign mio_pad_attr_22_od_en_22_wd = reg_wdata[6];
+
+ assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20];
+ assign mio_pad_attr_23_re = addr_hit[335] & reg_re & !reg_error;
+ assign mio_pad_attr_23_we = addr_hit[335] & reg_we & !reg_error;
+
+ assign mio_pad_attr_23_invert_23_wd = reg_wdata[0];
+
+ assign mio_pad_attr_23_virtual_od_en_23_wd = reg_wdata[1];
+
+ assign mio_pad_attr_23_pull_en_23_wd = reg_wdata[2];
+
+ assign mio_pad_attr_23_pull_select_23_wd = reg_wdata[3];
+
+ assign mio_pad_attr_23_keeper_en_23_wd = reg_wdata[4];
+
+ assign mio_pad_attr_23_schmitt_en_23_wd = reg_wdata[5];
+
+ assign mio_pad_attr_23_od_en_23_wd = reg_wdata[6];
+
+ assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20];
+ assign mio_pad_attr_24_re = addr_hit[336] & reg_re & !reg_error;
+ assign mio_pad_attr_24_we = addr_hit[336] & reg_we & !reg_error;
+
+ assign mio_pad_attr_24_invert_24_wd = reg_wdata[0];
+
+ assign mio_pad_attr_24_virtual_od_en_24_wd = reg_wdata[1];
+
+ assign mio_pad_attr_24_pull_en_24_wd = reg_wdata[2];
+
+ assign mio_pad_attr_24_pull_select_24_wd = reg_wdata[3];
+
+ assign mio_pad_attr_24_keeper_en_24_wd = reg_wdata[4];
+
+ assign mio_pad_attr_24_schmitt_en_24_wd = reg_wdata[5];
+
+ assign mio_pad_attr_24_od_en_24_wd = reg_wdata[6];
+
+ assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20];
+ assign mio_pad_attr_25_re = addr_hit[337] & reg_re & !reg_error;
+ assign mio_pad_attr_25_we = addr_hit[337] & reg_we & !reg_error;
+
+ assign mio_pad_attr_25_invert_25_wd = reg_wdata[0];
+
+ assign mio_pad_attr_25_virtual_od_en_25_wd = reg_wdata[1];
+
+ assign mio_pad_attr_25_pull_en_25_wd = reg_wdata[2];
+
+ assign mio_pad_attr_25_pull_select_25_wd = reg_wdata[3];
+
+ assign mio_pad_attr_25_keeper_en_25_wd = reg_wdata[4];
+
+ assign mio_pad_attr_25_schmitt_en_25_wd = reg_wdata[5];
+
+ assign mio_pad_attr_25_od_en_25_wd = reg_wdata[6];
+
+ assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20];
+ assign mio_pad_attr_26_re = addr_hit[338] & reg_re & !reg_error;
+ assign mio_pad_attr_26_we = addr_hit[338] & reg_we & !reg_error;
+
+ assign mio_pad_attr_26_invert_26_wd = reg_wdata[0];
+
+ assign mio_pad_attr_26_virtual_od_en_26_wd = reg_wdata[1];
+
+ assign mio_pad_attr_26_pull_en_26_wd = reg_wdata[2];
+
+ assign mio_pad_attr_26_pull_select_26_wd = reg_wdata[3];
+
+ assign mio_pad_attr_26_keeper_en_26_wd = reg_wdata[4];
+
+ assign mio_pad_attr_26_schmitt_en_26_wd = reg_wdata[5];
+
+ assign mio_pad_attr_26_od_en_26_wd = reg_wdata[6];
+
+ assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20];
+ assign mio_pad_attr_27_re = addr_hit[339] & reg_re & !reg_error;
+ assign mio_pad_attr_27_we = addr_hit[339] & reg_we & !reg_error;
+
+ assign mio_pad_attr_27_invert_27_wd = reg_wdata[0];
+
+ assign mio_pad_attr_27_virtual_od_en_27_wd = reg_wdata[1];
+
+ assign mio_pad_attr_27_pull_en_27_wd = reg_wdata[2];
+
+ assign mio_pad_attr_27_pull_select_27_wd = reg_wdata[3];
+
+ assign mio_pad_attr_27_keeper_en_27_wd = reg_wdata[4];
+
+ assign mio_pad_attr_27_schmitt_en_27_wd = reg_wdata[5];
+
+ assign mio_pad_attr_27_od_en_27_wd = reg_wdata[6];
+
+ assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20];
+ assign mio_pad_attr_28_re = addr_hit[340] & reg_re & !reg_error;
+ assign mio_pad_attr_28_we = addr_hit[340] & reg_we & !reg_error;
+
+ assign mio_pad_attr_28_invert_28_wd = reg_wdata[0];
+
+ assign mio_pad_attr_28_virtual_od_en_28_wd = reg_wdata[1];
+
+ assign mio_pad_attr_28_pull_en_28_wd = reg_wdata[2];
+
+ assign mio_pad_attr_28_pull_select_28_wd = reg_wdata[3];
+
+ assign mio_pad_attr_28_keeper_en_28_wd = reg_wdata[4];
+
+ assign mio_pad_attr_28_schmitt_en_28_wd = reg_wdata[5];
+
+ assign mio_pad_attr_28_od_en_28_wd = reg_wdata[6];
+
+ assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20];
+ assign mio_pad_attr_29_re = addr_hit[341] & reg_re & !reg_error;
+ assign mio_pad_attr_29_we = addr_hit[341] & reg_we & !reg_error;
+
+ assign mio_pad_attr_29_invert_29_wd = reg_wdata[0];
+
+ assign mio_pad_attr_29_virtual_od_en_29_wd = reg_wdata[1];
+
+ assign mio_pad_attr_29_pull_en_29_wd = reg_wdata[2];
+
+ assign mio_pad_attr_29_pull_select_29_wd = reg_wdata[3];
+
+ assign mio_pad_attr_29_keeper_en_29_wd = reg_wdata[4];
+
+ assign mio_pad_attr_29_schmitt_en_29_wd = reg_wdata[5];
+
+ assign mio_pad_attr_29_od_en_29_wd = reg_wdata[6];
+
+ assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20];
+ assign mio_pad_attr_30_re = addr_hit[342] & reg_re & !reg_error;
+ assign mio_pad_attr_30_we = addr_hit[342] & reg_we & !reg_error;
+
+ assign mio_pad_attr_30_invert_30_wd = reg_wdata[0];
+
+ assign mio_pad_attr_30_virtual_od_en_30_wd = reg_wdata[1];
+
+ assign mio_pad_attr_30_pull_en_30_wd = reg_wdata[2];
+
+ assign mio_pad_attr_30_pull_select_30_wd = reg_wdata[3];
+
+ assign mio_pad_attr_30_keeper_en_30_wd = reg_wdata[4];
+
+ assign mio_pad_attr_30_schmitt_en_30_wd = reg_wdata[5];
+
+ assign mio_pad_attr_30_od_en_30_wd = reg_wdata[6];
+
+ assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20];
+ assign mio_pad_attr_31_re = addr_hit[343] & reg_re & !reg_error;
+ assign mio_pad_attr_31_we = addr_hit[343] & reg_we & !reg_error;
+
+ assign mio_pad_attr_31_invert_31_wd = reg_wdata[0];
+
+ assign mio_pad_attr_31_virtual_od_en_31_wd = reg_wdata[1];
+
+ assign mio_pad_attr_31_pull_en_31_wd = reg_wdata[2];
+
+ assign mio_pad_attr_31_pull_select_31_wd = reg_wdata[3];
+
+ assign mio_pad_attr_31_keeper_en_31_wd = reg_wdata[4];
+
+ assign mio_pad_attr_31_schmitt_en_31_wd = reg_wdata[5];
+
+ assign mio_pad_attr_31_od_en_31_wd = reg_wdata[6];
+
+ assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20];
+ assign mio_pad_attr_32_re = addr_hit[344] & reg_re & !reg_error;
+ assign mio_pad_attr_32_we = addr_hit[344] & reg_we & !reg_error;
+
+ assign mio_pad_attr_32_invert_32_wd = reg_wdata[0];
+
+ assign mio_pad_attr_32_virtual_od_en_32_wd = reg_wdata[1];
+
+ assign mio_pad_attr_32_pull_en_32_wd = reg_wdata[2];
+
+ assign mio_pad_attr_32_pull_select_32_wd = reg_wdata[3];
+
+ assign mio_pad_attr_32_keeper_en_32_wd = reg_wdata[4];
+
+ assign mio_pad_attr_32_schmitt_en_32_wd = reg_wdata[5];
+
+ assign mio_pad_attr_32_od_en_32_wd = reg_wdata[6];
+
+ assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20];
+ assign mio_pad_attr_33_re = addr_hit[345] & reg_re & !reg_error;
+ assign mio_pad_attr_33_we = addr_hit[345] & reg_we & !reg_error;
+
+ assign mio_pad_attr_33_invert_33_wd = reg_wdata[0];
+
+ assign mio_pad_attr_33_virtual_od_en_33_wd = reg_wdata[1];
+
+ assign mio_pad_attr_33_pull_en_33_wd = reg_wdata[2];
+
+ assign mio_pad_attr_33_pull_select_33_wd = reg_wdata[3];
+
+ assign mio_pad_attr_33_keeper_en_33_wd = reg_wdata[4];
+
+ assign mio_pad_attr_33_schmitt_en_33_wd = reg_wdata[5];
+
+ assign mio_pad_attr_33_od_en_33_wd = reg_wdata[6];
+
+ assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20];
+ assign mio_pad_attr_34_re = addr_hit[346] & reg_re & !reg_error;
+ assign mio_pad_attr_34_we = addr_hit[346] & reg_we & !reg_error;
+
+ assign mio_pad_attr_34_invert_34_wd = reg_wdata[0];
+
+ assign mio_pad_attr_34_virtual_od_en_34_wd = reg_wdata[1];
+
+ assign mio_pad_attr_34_pull_en_34_wd = reg_wdata[2];
+
+ assign mio_pad_attr_34_pull_select_34_wd = reg_wdata[3];
+
+ assign mio_pad_attr_34_keeper_en_34_wd = reg_wdata[4];
+
+ assign mio_pad_attr_34_schmitt_en_34_wd = reg_wdata[5];
+
+ assign mio_pad_attr_34_od_en_34_wd = reg_wdata[6];
+
+ assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20];
+ assign mio_pad_attr_35_re = addr_hit[347] & reg_re & !reg_error;
+ assign mio_pad_attr_35_we = addr_hit[347] & reg_we & !reg_error;
+
+ assign mio_pad_attr_35_invert_35_wd = reg_wdata[0];
+
+ assign mio_pad_attr_35_virtual_od_en_35_wd = reg_wdata[1];
+
+ assign mio_pad_attr_35_pull_en_35_wd = reg_wdata[2];
+
+ assign mio_pad_attr_35_pull_select_35_wd = reg_wdata[3];
+
+ assign mio_pad_attr_35_keeper_en_35_wd = reg_wdata[4];
+
+ assign mio_pad_attr_35_schmitt_en_35_wd = reg_wdata[5];
+
+ assign mio_pad_attr_35_od_en_35_wd = reg_wdata[6];
+
+ assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20];
+ assign mio_pad_attr_36_re = addr_hit[348] & reg_re & !reg_error;
+ assign mio_pad_attr_36_we = addr_hit[348] & reg_we & !reg_error;
+
+ assign mio_pad_attr_36_invert_36_wd = reg_wdata[0];
+
+ assign mio_pad_attr_36_virtual_od_en_36_wd = reg_wdata[1];
+
+ assign mio_pad_attr_36_pull_en_36_wd = reg_wdata[2];
+
+ assign mio_pad_attr_36_pull_select_36_wd = reg_wdata[3];
+
+ assign mio_pad_attr_36_keeper_en_36_wd = reg_wdata[4];
+
+ assign mio_pad_attr_36_schmitt_en_36_wd = reg_wdata[5];
+
+ assign mio_pad_attr_36_od_en_36_wd = reg_wdata[6];
+
+ assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20];
+ assign mio_pad_attr_37_re = addr_hit[349] & reg_re & !reg_error;
+ assign mio_pad_attr_37_we = addr_hit[349] & reg_we & !reg_error;
+
+ assign mio_pad_attr_37_invert_37_wd = reg_wdata[0];
+
+ assign mio_pad_attr_37_virtual_od_en_37_wd = reg_wdata[1];
+
+ assign mio_pad_attr_37_pull_en_37_wd = reg_wdata[2];
+
+ assign mio_pad_attr_37_pull_select_37_wd = reg_wdata[3];
+
+ assign mio_pad_attr_37_keeper_en_37_wd = reg_wdata[4];
+
+ assign mio_pad_attr_37_schmitt_en_37_wd = reg_wdata[5];
+
+ assign mio_pad_attr_37_od_en_37_wd = reg_wdata[6];
+
+ assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20];
+ assign mio_pad_attr_38_re = addr_hit[350] & reg_re & !reg_error;
+ assign mio_pad_attr_38_we = addr_hit[350] & reg_we & !reg_error;
+
+ assign mio_pad_attr_38_invert_38_wd = reg_wdata[0];
+
+ assign mio_pad_attr_38_virtual_od_en_38_wd = reg_wdata[1];
+
+ assign mio_pad_attr_38_pull_en_38_wd = reg_wdata[2];
+
+ assign mio_pad_attr_38_pull_select_38_wd = reg_wdata[3];
+
+ assign mio_pad_attr_38_keeper_en_38_wd = reg_wdata[4];
+
+ assign mio_pad_attr_38_schmitt_en_38_wd = reg_wdata[5];
+
+ assign mio_pad_attr_38_od_en_38_wd = reg_wdata[6];
+
+ assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20];
+ assign mio_pad_attr_39_re = addr_hit[351] & reg_re & !reg_error;
+ assign mio_pad_attr_39_we = addr_hit[351] & reg_we & !reg_error;
+
+ assign mio_pad_attr_39_invert_39_wd = reg_wdata[0];
+
+ assign mio_pad_attr_39_virtual_od_en_39_wd = reg_wdata[1];
+
+ assign mio_pad_attr_39_pull_en_39_wd = reg_wdata[2];
+
+ assign mio_pad_attr_39_pull_select_39_wd = reg_wdata[3];
+
+ assign mio_pad_attr_39_keeper_en_39_wd = reg_wdata[4];
+
+ assign mio_pad_attr_39_schmitt_en_39_wd = reg_wdata[5];
+
+ assign mio_pad_attr_39_od_en_39_wd = reg_wdata[6];
+
+ assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20];
+ assign mio_pad_attr_40_re = addr_hit[352] & reg_re & !reg_error;
+ assign mio_pad_attr_40_we = addr_hit[352] & reg_we & !reg_error;
+
+ assign mio_pad_attr_40_invert_40_wd = reg_wdata[0];
+
+ assign mio_pad_attr_40_virtual_od_en_40_wd = reg_wdata[1];
+
+ assign mio_pad_attr_40_pull_en_40_wd = reg_wdata[2];
+
+ assign mio_pad_attr_40_pull_select_40_wd = reg_wdata[3];
+
+ assign mio_pad_attr_40_keeper_en_40_wd = reg_wdata[4];
+
+ assign mio_pad_attr_40_schmitt_en_40_wd = reg_wdata[5];
+
+ assign mio_pad_attr_40_od_en_40_wd = reg_wdata[6];
+
+ assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20];
+ assign mio_pad_attr_41_re = addr_hit[353] & reg_re & !reg_error;
+ assign mio_pad_attr_41_we = addr_hit[353] & reg_we & !reg_error;
+
+ assign mio_pad_attr_41_invert_41_wd = reg_wdata[0];
+
+ assign mio_pad_attr_41_virtual_od_en_41_wd = reg_wdata[1];
+
+ assign mio_pad_attr_41_pull_en_41_wd = reg_wdata[2];
+
+ assign mio_pad_attr_41_pull_select_41_wd = reg_wdata[3];
+
+ assign mio_pad_attr_41_keeper_en_41_wd = reg_wdata[4];
+
+ assign mio_pad_attr_41_schmitt_en_41_wd = reg_wdata[5];
+
+ assign mio_pad_attr_41_od_en_41_wd = reg_wdata[6];
+
+ assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20];
+ assign mio_pad_attr_42_re = addr_hit[354] & reg_re & !reg_error;
+ assign mio_pad_attr_42_we = addr_hit[354] & reg_we & !reg_error;
+
+ assign mio_pad_attr_42_invert_42_wd = reg_wdata[0];
+
+ assign mio_pad_attr_42_virtual_od_en_42_wd = reg_wdata[1];
+
+ assign mio_pad_attr_42_pull_en_42_wd = reg_wdata[2];
+
+ assign mio_pad_attr_42_pull_select_42_wd = reg_wdata[3];
+
+ assign mio_pad_attr_42_keeper_en_42_wd = reg_wdata[4];
+
+ assign mio_pad_attr_42_schmitt_en_42_wd = reg_wdata[5];
+
+ assign mio_pad_attr_42_od_en_42_wd = reg_wdata[6];
+
+ assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20];
+ assign mio_pad_attr_43_re = addr_hit[355] & reg_re & !reg_error;
+ assign mio_pad_attr_43_we = addr_hit[355] & reg_we & !reg_error;
+
+ assign mio_pad_attr_43_invert_43_wd = reg_wdata[0];
+
+ assign mio_pad_attr_43_virtual_od_en_43_wd = reg_wdata[1];
+
+ assign mio_pad_attr_43_pull_en_43_wd = reg_wdata[2];
+
+ assign mio_pad_attr_43_pull_select_43_wd = reg_wdata[3];
+
+ assign mio_pad_attr_43_keeper_en_43_wd = reg_wdata[4];
+
+ assign mio_pad_attr_43_schmitt_en_43_wd = reg_wdata[5];
+
+ assign mio_pad_attr_43_od_en_43_wd = reg_wdata[6];
+
+ assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20];
+ assign mio_pad_attr_44_re = addr_hit[356] & reg_re & !reg_error;
+ assign mio_pad_attr_44_we = addr_hit[356] & reg_we & !reg_error;
+
+ assign mio_pad_attr_44_invert_44_wd = reg_wdata[0];
+
+ assign mio_pad_attr_44_virtual_od_en_44_wd = reg_wdata[1];
+
+ assign mio_pad_attr_44_pull_en_44_wd = reg_wdata[2];
+
+ assign mio_pad_attr_44_pull_select_44_wd = reg_wdata[3];
+
+ assign mio_pad_attr_44_keeper_en_44_wd = reg_wdata[4];
+
+ assign mio_pad_attr_44_schmitt_en_44_wd = reg_wdata[5];
+
+ assign mio_pad_attr_44_od_en_44_wd = reg_wdata[6];
+
+ assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20];
+ assign mio_pad_attr_45_re = addr_hit[357] & reg_re & !reg_error;
+ assign mio_pad_attr_45_we = addr_hit[357] & reg_we & !reg_error;
+
+ assign mio_pad_attr_45_invert_45_wd = reg_wdata[0];
+
+ assign mio_pad_attr_45_virtual_od_en_45_wd = reg_wdata[1];
+
+ assign mio_pad_attr_45_pull_en_45_wd = reg_wdata[2];
+
+ assign mio_pad_attr_45_pull_select_45_wd = reg_wdata[3];
+
+ assign mio_pad_attr_45_keeper_en_45_wd = reg_wdata[4];
+
+ assign mio_pad_attr_45_schmitt_en_45_wd = reg_wdata[5];
+
+ assign mio_pad_attr_45_od_en_45_wd = reg_wdata[6];
+
+ assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20];
+ assign mio_pad_attr_46_re = addr_hit[358] & reg_re & !reg_error;
+ assign mio_pad_attr_46_we = addr_hit[358] & reg_we & !reg_error;
+
+ assign mio_pad_attr_46_invert_46_wd = reg_wdata[0];
+
+ assign mio_pad_attr_46_virtual_od_en_46_wd = reg_wdata[1];
+
+ assign mio_pad_attr_46_pull_en_46_wd = reg_wdata[2];
+
+ assign mio_pad_attr_46_pull_select_46_wd = reg_wdata[3];
+
+ assign mio_pad_attr_46_keeper_en_46_wd = reg_wdata[4];
+
+ assign mio_pad_attr_46_schmitt_en_46_wd = reg_wdata[5];
+
+ assign mio_pad_attr_46_od_en_46_wd = reg_wdata[6];
+
+ assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20];
+ assign mio_pad_attr_47_re = addr_hit[359] & reg_re & !reg_error;
+ assign mio_pad_attr_47_we = addr_hit[359] & reg_we & !reg_error;
+
+ assign mio_pad_attr_47_invert_47_wd = reg_wdata[0];
+
+ assign mio_pad_attr_47_virtual_od_en_47_wd = reg_wdata[1];
+
+ assign mio_pad_attr_47_pull_en_47_wd = reg_wdata[2];
+
+ assign mio_pad_attr_47_pull_select_47_wd = reg_wdata[3];
+
+ assign mio_pad_attr_47_keeper_en_47_wd = reg_wdata[4];
+
+ assign mio_pad_attr_47_schmitt_en_47_wd = reg_wdata[5];
+
+ assign mio_pad_attr_47_od_en_47_wd = reg_wdata[6];
+
+ assign mio_pad_attr_47_slew_rate_47_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_47_drive_strength_47_wd = reg_wdata[23:20];
+ assign mio_pad_attr_48_re = addr_hit[360] & reg_re & !reg_error;
+ assign mio_pad_attr_48_we = addr_hit[360] & reg_we & !reg_error;
+
+ assign mio_pad_attr_48_invert_48_wd = reg_wdata[0];
+
+ assign mio_pad_attr_48_virtual_od_en_48_wd = reg_wdata[1];
+
+ assign mio_pad_attr_48_pull_en_48_wd = reg_wdata[2];
+
+ assign mio_pad_attr_48_pull_select_48_wd = reg_wdata[3];
+
+ assign mio_pad_attr_48_keeper_en_48_wd = reg_wdata[4];
+
+ assign mio_pad_attr_48_schmitt_en_48_wd = reg_wdata[5];
+
+ assign mio_pad_attr_48_od_en_48_wd = reg_wdata[6];
+
+ assign mio_pad_attr_48_slew_rate_48_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_48_drive_strength_48_wd = reg_wdata[23:20];
+ assign mio_pad_attr_49_re = addr_hit[361] & reg_re & !reg_error;
+ assign mio_pad_attr_49_we = addr_hit[361] & reg_we & !reg_error;
+
+ assign mio_pad_attr_49_invert_49_wd = reg_wdata[0];
+
+ assign mio_pad_attr_49_virtual_od_en_49_wd = reg_wdata[1];
+
+ assign mio_pad_attr_49_pull_en_49_wd = reg_wdata[2];
+
+ assign mio_pad_attr_49_pull_select_49_wd = reg_wdata[3];
+
+ assign mio_pad_attr_49_keeper_en_49_wd = reg_wdata[4];
+
+ assign mio_pad_attr_49_schmitt_en_49_wd = reg_wdata[5];
+
+ assign mio_pad_attr_49_od_en_49_wd = reg_wdata[6];
+
+ assign mio_pad_attr_49_slew_rate_49_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_49_drive_strength_49_wd = reg_wdata[23:20];
+ assign mio_pad_attr_50_re = addr_hit[362] & reg_re & !reg_error;
+ assign mio_pad_attr_50_we = addr_hit[362] & reg_we & !reg_error;
+
+ assign mio_pad_attr_50_invert_50_wd = reg_wdata[0];
+
+ assign mio_pad_attr_50_virtual_od_en_50_wd = reg_wdata[1];
+
+ assign mio_pad_attr_50_pull_en_50_wd = reg_wdata[2];
+
+ assign mio_pad_attr_50_pull_select_50_wd = reg_wdata[3];
+
+ assign mio_pad_attr_50_keeper_en_50_wd = reg_wdata[4];
+
+ assign mio_pad_attr_50_schmitt_en_50_wd = reg_wdata[5];
+
+ assign mio_pad_attr_50_od_en_50_wd = reg_wdata[6];
+
+ assign mio_pad_attr_50_slew_rate_50_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_50_drive_strength_50_wd = reg_wdata[23:20];
+ assign mio_pad_attr_51_re = addr_hit[363] & reg_re & !reg_error;
+ assign mio_pad_attr_51_we = addr_hit[363] & reg_we & !reg_error;
+
+ assign mio_pad_attr_51_invert_51_wd = reg_wdata[0];
+
+ assign mio_pad_attr_51_virtual_od_en_51_wd = reg_wdata[1];
+
+ assign mio_pad_attr_51_pull_en_51_wd = reg_wdata[2];
+
+ assign mio_pad_attr_51_pull_select_51_wd = reg_wdata[3];
+
+ assign mio_pad_attr_51_keeper_en_51_wd = reg_wdata[4];
+
+ assign mio_pad_attr_51_schmitt_en_51_wd = reg_wdata[5];
+
+ assign mio_pad_attr_51_od_en_51_wd = reg_wdata[6];
+
+ assign mio_pad_attr_51_slew_rate_51_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_51_drive_strength_51_wd = reg_wdata[23:20];
+ assign mio_pad_attr_52_re = addr_hit[364] & reg_re & !reg_error;
+ assign mio_pad_attr_52_we = addr_hit[364] & reg_we & !reg_error;
+
+ assign mio_pad_attr_52_invert_52_wd = reg_wdata[0];
+
+ assign mio_pad_attr_52_virtual_od_en_52_wd = reg_wdata[1];
+
+ assign mio_pad_attr_52_pull_en_52_wd = reg_wdata[2];
+
+ assign mio_pad_attr_52_pull_select_52_wd = reg_wdata[3];
+
+ assign mio_pad_attr_52_keeper_en_52_wd = reg_wdata[4];
+
+ assign mio_pad_attr_52_schmitt_en_52_wd = reg_wdata[5];
+
+ assign mio_pad_attr_52_od_en_52_wd = reg_wdata[6];
+
+ assign mio_pad_attr_52_slew_rate_52_wd = reg_wdata[17:16];
+
+ assign mio_pad_attr_52_drive_strength_52_wd = reg_wdata[23:20];
+ assign dio_pad_attr_regwen_0_we = addr_hit[365] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_1_we = addr_hit[366] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_2_we = addr_hit[367] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_3_we = addr_hit[368] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_4_we = addr_hit[369] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_5_we = addr_hit[370] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_6_we = addr_hit[371] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_7_we = addr_hit[372] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_8_we = addr_hit[373] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_9_we = addr_hit[374] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_10_we = addr_hit[375] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_11_we = addr_hit[376] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_12_we = addr_hit[377] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_13_we = addr_hit[378] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_14_we = addr_hit[379] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
+ assign dio_pad_attr_regwen_15_we = addr_hit[380] & reg_we & !reg_error;
+
+ assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
+ assign dio_pad_attr_0_re = addr_hit[381] & reg_re & !reg_error;
+ assign dio_pad_attr_0_we = addr_hit[381] & reg_we & !reg_error;
+
+ assign dio_pad_attr_0_invert_0_wd = reg_wdata[0];
+
+ assign dio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1];
+
+ assign dio_pad_attr_0_pull_en_0_wd = reg_wdata[2];
+
+ assign dio_pad_attr_0_pull_select_0_wd = reg_wdata[3];
+
+ assign dio_pad_attr_0_keeper_en_0_wd = reg_wdata[4];
+
+ assign dio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5];
+
+ assign dio_pad_attr_0_od_en_0_wd = reg_wdata[6];
+
+ assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20];
+ assign dio_pad_attr_1_re = addr_hit[382] & reg_re & !reg_error;
+ assign dio_pad_attr_1_we = addr_hit[382] & reg_we & !reg_error;
+
+ assign dio_pad_attr_1_invert_1_wd = reg_wdata[0];
+
+ assign dio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1];
+
+ assign dio_pad_attr_1_pull_en_1_wd = reg_wdata[2];
+
+ assign dio_pad_attr_1_pull_select_1_wd = reg_wdata[3];
+
+ assign dio_pad_attr_1_keeper_en_1_wd = reg_wdata[4];
+
+ assign dio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5];
+
+ assign dio_pad_attr_1_od_en_1_wd = reg_wdata[6];
+
+ assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20];
+ assign dio_pad_attr_2_re = addr_hit[383] & reg_re & !reg_error;
+ assign dio_pad_attr_2_we = addr_hit[383] & reg_we & !reg_error;
+
+ assign dio_pad_attr_2_invert_2_wd = reg_wdata[0];
+
+ assign dio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1];
+
+ assign dio_pad_attr_2_pull_en_2_wd = reg_wdata[2];
+
+ assign dio_pad_attr_2_pull_select_2_wd = reg_wdata[3];
+
+ assign dio_pad_attr_2_keeper_en_2_wd = reg_wdata[4];
+
+ assign dio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5];
+
+ assign dio_pad_attr_2_od_en_2_wd = reg_wdata[6];
+
+ assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20];
+ assign dio_pad_attr_3_re = addr_hit[384] & reg_re & !reg_error;
+ assign dio_pad_attr_3_we = addr_hit[384] & reg_we & !reg_error;
+
+ assign dio_pad_attr_3_invert_3_wd = reg_wdata[0];
+
+ assign dio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1];
+
+ assign dio_pad_attr_3_pull_en_3_wd = reg_wdata[2];
+
+ assign dio_pad_attr_3_pull_select_3_wd = reg_wdata[3];
+
+ assign dio_pad_attr_3_keeper_en_3_wd = reg_wdata[4];
+
+ assign dio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5];
+
+ assign dio_pad_attr_3_od_en_3_wd = reg_wdata[6];
+
+ assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20];
+ assign dio_pad_attr_4_re = addr_hit[385] & reg_re & !reg_error;
+ assign dio_pad_attr_4_we = addr_hit[385] & reg_we & !reg_error;
+
+ assign dio_pad_attr_4_invert_4_wd = reg_wdata[0];
+
+ assign dio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1];
+
+ assign dio_pad_attr_4_pull_en_4_wd = reg_wdata[2];
+
+ assign dio_pad_attr_4_pull_select_4_wd = reg_wdata[3];
+
+ assign dio_pad_attr_4_keeper_en_4_wd = reg_wdata[4];
+
+ assign dio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5];
+
+ assign dio_pad_attr_4_od_en_4_wd = reg_wdata[6];
+
+ assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20];
+ assign dio_pad_attr_5_re = addr_hit[386] & reg_re & !reg_error;
+ assign dio_pad_attr_5_we = addr_hit[386] & reg_we & !reg_error;
+
+ assign dio_pad_attr_5_invert_5_wd = reg_wdata[0];
+
+ assign dio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1];
+
+ assign dio_pad_attr_5_pull_en_5_wd = reg_wdata[2];
+
+ assign dio_pad_attr_5_pull_select_5_wd = reg_wdata[3];
+
+ assign dio_pad_attr_5_keeper_en_5_wd = reg_wdata[4];
+
+ assign dio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5];
+
+ assign dio_pad_attr_5_od_en_5_wd = reg_wdata[6];
+
+ assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20];
+ assign dio_pad_attr_6_re = addr_hit[387] & reg_re & !reg_error;
+ assign dio_pad_attr_6_we = addr_hit[387] & reg_we & !reg_error;
+
+ assign dio_pad_attr_6_invert_6_wd = reg_wdata[0];
+
+ assign dio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1];
+
+ assign dio_pad_attr_6_pull_en_6_wd = reg_wdata[2];
+
+ assign dio_pad_attr_6_pull_select_6_wd = reg_wdata[3];
+
+ assign dio_pad_attr_6_keeper_en_6_wd = reg_wdata[4];
+
+ assign dio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5];
+
+ assign dio_pad_attr_6_od_en_6_wd = reg_wdata[6];
+
+ assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20];
+ assign dio_pad_attr_7_re = addr_hit[388] & reg_re & !reg_error;
+ assign dio_pad_attr_7_we = addr_hit[388] & reg_we & !reg_error;
+
+ assign dio_pad_attr_7_invert_7_wd = reg_wdata[0];
+
+ assign dio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1];
+
+ assign dio_pad_attr_7_pull_en_7_wd = reg_wdata[2];
+
+ assign dio_pad_attr_7_pull_select_7_wd = reg_wdata[3];
+
+ assign dio_pad_attr_7_keeper_en_7_wd = reg_wdata[4];
+
+ assign dio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5];
+
+ assign dio_pad_attr_7_od_en_7_wd = reg_wdata[6];
+
+ assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20];
+ assign dio_pad_attr_8_re = addr_hit[389] & reg_re & !reg_error;
+ assign dio_pad_attr_8_we = addr_hit[389] & reg_we & !reg_error;
+
+ assign dio_pad_attr_8_invert_8_wd = reg_wdata[0];
+
+ assign dio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1];
+
+ assign dio_pad_attr_8_pull_en_8_wd = reg_wdata[2];
+
+ assign dio_pad_attr_8_pull_select_8_wd = reg_wdata[3];
+
+ assign dio_pad_attr_8_keeper_en_8_wd = reg_wdata[4];
+
+ assign dio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5];
+
+ assign dio_pad_attr_8_od_en_8_wd = reg_wdata[6];
+
+ assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20];
+ assign dio_pad_attr_9_re = addr_hit[390] & reg_re & !reg_error;
+ assign dio_pad_attr_9_we = addr_hit[390] & reg_we & !reg_error;
+
+ assign dio_pad_attr_9_invert_9_wd = reg_wdata[0];
+
+ assign dio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1];
+
+ assign dio_pad_attr_9_pull_en_9_wd = reg_wdata[2];
+
+ assign dio_pad_attr_9_pull_select_9_wd = reg_wdata[3];
+
+ assign dio_pad_attr_9_keeper_en_9_wd = reg_wdata[4];
+
+ assign dio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5];
+
+ assign dio_pad_attr_9_od_en_9_wd = reg_wdata[6];
+
+ assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20];
+ assign dio_pad_attr_10_re = addr_hit[391] & reg_re & !reg_error;
+ assign dio_pad_attr_10_we = addr_hit[391] & reg_we & !reg_error;
+
+ assign dio_pad_attr_10_invert_10_wd = reg_wdata[0];
+
+ assign dio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1];
+
+ assign dio_pad_attr_10_pull_en_10_wd = reg_wdata[2];
+
+ assign dio_pad_attr_10_pull_select_10_wd = reg_wdata[3];
+
+ assign dio_pad_attr_10_keeper_en_10_wd = reg_wdata[4];
+
+ assign dio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5];
+
+ assign dio_pad_attr_10_od_en_10_wd = reg_wdata[6];
+
+ assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20];
+ assign dio_pad_attr_11_re = addr_hit[392] & reg_re & !reg_error;
+ assign dio_pad_attr_11_we = addr_hit[392] & reg_we & !reg_error;
+
+ assign dio_pad_attr_11_invert_11_wd = reg_wdata[0];
+
+ assign dio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1];
+
+ assign dio_pad_attr_11_pull_en_11_wd = reg_wdata[2];
+
+ assign dio_pad_attr_11_pull_select_11_wd = reg_wdata[3];
+
+ assign dio_pad_attr_11_keeper_en_11_wd = reg_wdata[4];
+
+ assign dio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5];
+
+ assign dio_pad_attr_11_od_en_11_wd = reg_wdata[6];
+
+ assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20];
+ assign dio_pad_attr_12_re = addr_hit[393] & reg_re & !reg_error;
+ assign dio_pad_attr_12_we = addr_hit[393] & reg_we & !reg_error;
+
+ assign dio_pad_attr_12_invert_12_wd = reg_wdata[0];
+
+ assign dio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1];
+
+ assign dio_pad_attr_12_pull_en_12_wd = reg_wdata[2];
+
+ assign dio_pad_attr_12_pull_select_12_wd = reg_wdata[3];
+
+ assign dio_pad_attr_12_keeper_en_12_wd = reg_wdata[4];
+
+ assign dio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5];
+
+ assign dio_pad_attr_12_od_en_12_wd = reg_wdata[6];
+
+ assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20];
+ assign dio_pad_attr_13_re = addr_hit[394] & reg_re & !reg_error;
+ assign dio_pad_attr_13_we = addr_hit[394] & reg_we & !reg_error;
+
+ assign dio_pad_attr_13_invert_13_wd = reg_wdata[0];
+
+ assign dio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1];
+
+ assign dio_pad_attr_13_pull_en_13_wd = reg_wdata[2];
+
+ assign dio_pad_attr_13_pull_select_13_wd = reg_wdata[3];
+
+ assign dio_pad_attr_13_keeper_en_13_wd = reg_wdata[4];
+
+ assign dio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5];
+
+ assign dio_pad_attr_13_od_en_13_wd = reg_wdata[6];
+
+ assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20];
+ assign dio_pad_attr_14_re = addr_hit[395] & reg_re & !reg_error;
+ assign dio_pad_attr_14_we = addr_hit[395] & reg_we & !reg_error;
+
+ assign dio_pad_attr_14_invert_14_wd = reg_wdata[0];
+
+ assign dio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1];
+
+ assign dio_pad_attr_14_pull_en_14_wd = reg_wdata[2];
+
+ assign dio_pad_attr_14_pull_select_14_wd = reg_wdata[3];
+
+ assign dio_pad_attr_14_keeper_en_14_wd = reg_wdata[4];
+
+ assign dio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5];
+
+ assign dio_pad_attr_14_od_en_14_wd = reg_wdata[6];
+
+ assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20];
+ assign dio_pad_attr_15_re = addr_hit[396] & reg_re & !reg_error;
+ assign dio_pad_attr_15_we = addr_hit[396] & reg_we & !reg_error;
+
+ assign dio_pad_attr_15_invert_15_wd = reg_wdata[0];
+
+ assign dio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1];
+
+ assign dio_pad_attr_15_pull_en_15_wd = reg_wdata[2];
+
+ assign dio_pad_attr_15_pull_select_15_wd = reg_wdata[3];
+
+ assign dio_pad_attr_15_keeper_en_15_wd = reg_wdata[4];
+
+ assign dio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5];
+
+ assign dio_pad_attr_15_od_en_15_wd = reg_wdata[6];
+
+ assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16];
+
+ assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20];
+ assign mio_pad_sleep_status_0_we = addr_hit[397] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0];
+
+ assign mio_pad_sleep_status_0_en_1_wd = reg_wdata[1];
+
+ assign mio_pad_sleep_status_0_en_2_wd = reg_wdata[2];
+
+ assign mio_pad_sleep_status_0_en_3_wd = reg_wdata[3];
+
+ assign mio_pad_sleep_status_0_en_4_wd = reg_wdata[4];
+
+ assign mio_pad_sleep_status_0_en_5_wd = reg_wdata[5];
+
+ assign mio_pad_sleep_status_0_en_6_wd = reg_wdata[6];
+
+ assign mio_pad_sleep_status_0_en_7_wd = reg_wdata[7];
+
+ assign mio_pad_sleep_status_0_en_8_wd = reg_wdata[8];
+
+ assign mio_pad_sleep_status_0_en_9_wd = reg_wdata[9];
+
+ assign mio_pad_sleep_status_0_en_10_wd = reg_wdata[10];
+
+ assign mio_pad_sleep_status_0_en_11_wd = reg_wdata[11];
+
+ assign mio_pad_sleep_status_0_en_12_wd = reg_wdata[12];
+
+ assign mio_pad_sleep_status_0_en_13_wd = reg_wdata[13];
+
+ assign mio_pad_sleep_status_0_en_14_wd = reg_wdata[14];
+
+ assign mio_pad_sleep_status_0_en_15_wd = reg_wdata[15];
+
+ assign mio_pad_sleep_status_0_en_16_wd = reg_wdata[16];
+
+ assign mio_pad_sleep_status_0_en_17_wd = reg_wdata[17];
+
+ assign mio_pad_sleep_status_0_en_18_wd = reg_wdata[18];
+
+ assign mio_pad_sleep_status_0_en_19_wd = reg_wdata[19];
+
+ assign mio_pad_sleep_status_0_en_20_wd = reg_wdata[20];
+
+ assign mio_pad_sleep_status_0_en_21_wd = reg_wdata[21];
+
+ assign mio_pad_sleep_status_0_en_22_wd = reg_wdata[22];
+
+ assign mio_pad_sleep_status_0_en_23_wd = reg_wdata[23];
+
+ assign mio_pad_sleep_status_0_en_24_wd = reg_wdata[24];
+
+ assign mio_pad_sleep_status_0_en_25_wd = reg_wdata[25];
+
+ assign mio_pad_sleep_status_0_en_26_wd = reg_wdata[26];
+
+ assign mio_pad_sleep_status_0_en_27_wd = reg_wdata[27];
+
+ assign mio_pad_sleep_status_0_en_28_wd = reg_wdata[28];
+
+ assign mio_pad_sleep_status_0_en_29_wd = reg_wdata[29];
+
+ assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30];
+
+ assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31];
+ assign mio_pad_sleep_status_1_we = addr_hit[398] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0];
+
+ assign mio_pad_sleep_status_1_en_33_wd = reg_wdata[1];
+
+ assign mio_pad_sleep_status_1_en_34_wd = reg_wdata[2];
+
+ assign mio_pad_sleep_status_1_en_35_wd = reg_wdata[3];
+
+ assign mio_pad_sleep_status_1_en_36_wd = reg_wdata[4];
+
+ assign mio_pad_sleep_status_1_en_37_wd = reg_wdata[5];
+
+ assign mio_pad_sleep_status_1_en_38_wd = reg_wdata[6];
+
+ assign mio_pad_sleep_status_1_en_39_wd = reg_wdata[7];
+
+ assign mio_pad_sleep_status_1_en_40_wd = reg_wdata[8];
+
+ assign mio_pad_sleep_status_1_en_41_wd = reg_wdata[9];
+
+ assign mio_pad_sleep_status_1_en_42_wd = reg_wdata[10];
+
+ assign mio_pad_sleep_status_1_en_43_wd = reg_wdata[11];
+
+ assign mio_pad_sleep_status_1_en_44_wd = reg_wdata[12];
+
+ assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13];
+
+ assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14];
+
+ assign mio_pad_sleep_status_1_en_47_wd = reg_wdata[15];
+
+ assign mio_pad_sleep_status_1_en_48_wd = reg_wdata[16];
+
+ assign mio_pad_sleep_status_1_en_49_wd = reg_wdata[17];
+
+ assign mio_pad_sleep_status_1_en_50_wd = reg_wdata[18];
+
+ assign mio_pad_sleep_status_1_en_51_wd = reg_wdata[19];
+
+ assign mio_pad_sleep_status_1_en_52_wd = reg_wdata[20];
+ assign mio_pad_sleep_regwen_0_we = addr_hit[399] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_1_we = addr_hit[400] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_2_we = addr_hit[401] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_3_we = addr_hit[402] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_4_we = addr_hit[403] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_5_we = addr_hit[404] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_6_we = addr_hit[405] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_7_we = addr_hit[406] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_8_we = addr_hit[407] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_9_we = addr_hit[408] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_10_we = addr_hit[409] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_11_we = addr_hit[410] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_12_we = addr_hit[411] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_13_we = addr_hit[412] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_14_we = addr_hit[413] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_15_we = addr_hit[414] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_16_we = addr_hit[415] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_17_we = addr_hit[416] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_18_we = addr_hit[417] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_19_we = addr_hit[418] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_20_we = addr_hit[419] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_21_we = addr_hit[420] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_22_we = addr_hit[421] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_23_we = addr_hit[422] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_24_we = addr_hit[423] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_25_we = addr_hit[424] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_26_we = addr_hit[425] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_27_we = addr_hit[426] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_28_we = addr_hit[427] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_29_we = addr_hit[428] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_30_we = addr_hit[429] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_31_we = addr_hit[430] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_32_we = addr_hit[431] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_32_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_33_we = addr_hit[432] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_33_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_34_we = addr_hit[433] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_34_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_35_we = addr_hit[434] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_35_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_36_we = addr_hit[435] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_36_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_37_we = addr_hit[436] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_37_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_38_we = addr_hit[437] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_38_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_39_we = addr_hit[438] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_39_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_40_we = addr_hit[439] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_40_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_41_we = addr_hit[440] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_41_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_42_we = addr_hit[441] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_42_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_43_we = addr_hit[442] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_43_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_44_we = addr_hit[443] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_44_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_45_we = addr_hit[444] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_45_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_46_we = addr_hit[445] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_46_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_47_we = addr_hit[446] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_47_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_48_we = addr_hit[447] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_48_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_49_we = addr_hit[448] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_49_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_50_we = addr_hit[449] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_50_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_51_we = addr_hit[450] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_51_wd = reg_wdata[0];
+ assign mio_pad_sleep_regwen_52_we = addr_hit[451] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_regwen_52_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_0_we = addr_hit[452] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_0_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_1_we = addr_hit[453] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_1_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_2_we = addr_hit[454] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_2_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_3_we = addr_hit[455] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_3_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_4_we = addr_hit[456] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_4_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_5_we = addr_hit[457] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_5_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_6_we = addr_hit[458] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_6_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_7_we = addr_hit[459] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_7_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_8_we = addr_hit[460] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_8_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_9_we = addr_hit[461] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_9_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_10_we = addr_hit[462] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_10_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_11_we = addr_hit[463] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_11_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_12_we = addr_hit[464] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_12_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_13_we = addr_hit[465] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_13_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_14_we = addr_hit[466] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_14_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_15_we = addr_hit[467] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_15_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_16_we = addr_hit[468] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_16_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_17_we = addr_hit[469] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_17_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_18_we = addr_hit[470] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_18_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_19_we = addr_hit[471] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_19_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_20_we = addr_hit[472] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_20_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_21_we = addr_hit[473] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_21_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_22_we = addr_hit[474] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_22_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_23_we = addr_hit[475] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_23_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_24_we = addr_hit[476] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_24_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_25_we = addr_hit[477] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_25_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_26_we = addr_hit[478] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_26_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_27_we = addr_hit[479] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_27_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_28_we = addr_hit[480] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_28_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_29_we = addr_hit[481] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_29_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_30_we = addr_hit[482] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_30_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_31_we = addr_hit[483] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_31_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_32_we = addr_hit[484] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_32_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_33_we = addr_hit[485] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_33_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_34_we = addr_hit[486] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_34_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_35_we = addr_hit[487] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_35_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_36_we = addr_hit[488] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_36_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_37_we = addr_hit[489] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_37_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_38_we = addr_hit[490] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_38_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_39_we = addr_hit[491] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_39_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_40_we = addr_hit[492] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_40_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_41_we = addr_hit[493] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_41_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_42_we = addr_hit[494] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_42_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_43_we = addr_hit[495] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_43_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_44_we = addr_hit[496] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_44_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_45_we = addr_hit[497] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_45_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_46_we = addr_hit[498] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_46_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_47_we = addr_hit[499] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_47_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_48_we = addr_hit[500] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_48_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_49_we = addr_hit[501] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_49_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_50_we = addr_hit[502] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_50_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_51_we = addr_hit[503] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_51_wd = reg_wdata[0];
+ assign mio_pad_sleep_en_52_we = addr_hit[504] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_en_52_wd = reg_wdata[0];
+ assign mio_pad_sleep_mode_0_we = addr_hit[505] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_1_we = addr_hit[506] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_2_we = addr_hit[507] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_3_we = addr_hit[508] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_4_we = addr_hit[509] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_5_we = addr_hit[510] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_6_we = addr_hit[511] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_7_we = addr_hit[512] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_8_we = addr_hit[513] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_9_we = addr_hit[514] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_10_we = addr_hit[515] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_11_we = addr_hit[516] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_12_we = addr_hit[517] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_13_we = addr_hit[518] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_14_we = addr_hit[519] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_15_we = addr_hit[520] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_16_we = addr_hit[521] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_17_we = addr_hit[522] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_18_we = addr_hit[523] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_19_we = addr_hit[524] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_20_we = addr_hit[525] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_21_we = addr_hit[526] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_22_we = addr_hit[527] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_23_we = addr_hit[528] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_24_we = addr_hit[529] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_25_we = addr_hit[530] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_26_we = addr_hit[531] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_27_we = addr_hit[532] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_28_we = addr_hit[533] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_29_we = addr_hit[534] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_30_we = addr_hit[535] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_31_we = addr_hit[536] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_32_we = addr_hit[537] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_33_we = addr_hit[538] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_34_we = addr_hit[539] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_35_we = addr_hit[540] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_36_we = addr_hit[541] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_37_we = addr_hit[542] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_38_we = addr_hit[543] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_39_we = addr_hit[544] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_40_we = addr_hit[545] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_41_we = addr_hit[546] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_42_we = addr_hit[547] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_43_we = addr_hit[548] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_44_we = addr_hit[549] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_45_we = addr_hit[550] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_46_we = addr_hit[551] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_47_we = addr_hit[552] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_47_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_48_we = addr_hit[553] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_48_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_49_we = addr_hit[554] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_49_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_50_we = addr_hit[555] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_50_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_51_we = addr_hit[556] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_51_wd = reg_wdata[1:0];
+ assign mio_pad_sleep_mode_52_we = addr_hit[557] & reg_we & !reg_error;
+
+ assign mio_pad_sleep_mode_52_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_status_we = addr_hit[558] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
+
+ assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
+
+ assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
+
+ assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
+
+ assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
+
+ assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
+
+ assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
+
+ assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
+
+ assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
+
+ assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
+
+ assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
+
+ assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
+
+ assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
+
+ assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
+
+ assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
+
+ assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
+ assign dio_pad_sleep_regwen_0_we = addr_hit[559] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_1_we = addr_hit[560] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_2_we = addr_hit[561] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_3_we = addr_hit[562] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_4_we = addr_hit[563] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_5_we = addr_hit[564] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_6_we = addr_hit[565] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_7_we = addr_hit[566] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_8_we = addr_hit[567] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_9_we = addr_hit[568] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_10_we = addr_hit[569] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_11_we = addr_hit[570] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_12_we = addr_hit[571] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_13_we = addr_hit[572] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_14_we = addr_hit[573] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
+ assign dio_pad_sleep_regwen_15_we = addr_hit[574] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_0_we = addr_hit[575] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_0_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_1_we = addr_hit[576] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_1_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_2_we = addr_hit[577] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_2_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_3_we = addr_hit[578] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_3_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_4_we = addr_hit[579] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_4_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_5_we = addr_hit[580] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_5_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_6_we = addr_hit[581] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_6_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_7_we = addr_hit[582] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_7_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_8_we = addr_hit[583] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_8_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_9_we = addr_hit[584] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_9_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_10_we = addr_hit[585] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_10_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_11_we = addr_hit[586] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_11_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_12_we = addr_hit[587] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_12_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_13_we = addr_hit[588] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_13_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_14_we = addr_hit[589] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_14_wd = reg_wdata[0];
+ assign dio_pad_sleep_en_15_we = addr_hit[590] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_en_15_wd = reg_wdata[0];
+ assign dio_pad_sleep_mode_0_we = addr_hit[591] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_1_we = addr_hit[592] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_2_we = addr_hit[593] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_3_we = addr_hit[594] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_4_we = addr_hit[595] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_5_we = addr_hit[596] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_6_we = addr_hit[597] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_7_we = addr_hit[598] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_8_we = addr_hit[599] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_9_we = addr_hit[600] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_10_we = addr_hit[601] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_11_we = addr_hit[602] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_12_we = addr_hit[603] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_13_we = addr_hit[604] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_14_we = addr_hit[605] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
+ assign dio_pad_sleep_mode_15_we = addr_hit[606] & reg_we & !reg_error;
+
+ assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
+ assign wkup_detector_regwen_0_we = addr_hit[607] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_0_wd = reg_wdata[0];
+ assign wkup_detector_regwen_1_we = addr_hit[608] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_1_wd = reg_wdata[0];
+ assign wkup_detector_regwen_2_we = addr_hit[609] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_2_wd = reg_wdata[0];
+ assign wkup_detector_regwen_3_we = addr_hit[610] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_3_wd = reg_wdata[0];
+ assign wkup_detector_regwen_4_we = addr_hit[611] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_4_wd = reg_wdata[0];
+ assign wkup_detector_regwen_5_we = addr_hit[612] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_5_wd = reg_wdata[0];
+ assign wkup_detector_regwen_6_we = addr_hit[613] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_6_wd = reg_wdata[0];
+ assign wkup_detector_regwen_7_we = addr_hit[614] & reg_we & !reg_error;
+
+ assign wkup_detector_regwen_7_wd = reg_wdata[0];
+ assign wkup_detector_en_0_we = addr_hit[615] & reg_we & !reg_error;
+
+ assign wkup_detector_en_1_we = addr_hit[616] & reg_we & !reg_error;
+
+ assign wkup_detector_en_2_we = addr_hit[617] & reg_we & !reg_error;
+
+ assign wkup_detector_en_3_we = addr_hit[618] & reg_we & !reg_error;
+
+ assign wkup_detector_en_4_we = addr_hit[619] & reg_we & !reg_error;
+
+ assign wkup_detector_en_5_we = addr_hit[620] & reg_we & !reg_error;
+
+ assign wkup_detector_en_6_we = addr_hit[621] & reg_we & !reg_error;
+
+ assign wkup_detector_en_7_we = addr_hit[622] & reg_we & !reg_error;
+
+ assign wkup_detector_0_we = addr_hit[623] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_1_we = addr_hit[624] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_2_we = addr_hit[625] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_3_we = addr_hit[626] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_4_we = addr_hit[627] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_5_we = addr_hit[628] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_6_we = addr_hit[629] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_7_we = addr_hit[630] & reg_we & !reg_error;
+
+
+
+ assign wkup_detector_cnt_th_0_we = addr_hit[631] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_1_we = addr_hit[632] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_2_we = addr_hit[633] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_3_we = addr_hit[634] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_4_we = addr_hit[635] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_5_we = addr_hit[636] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_6_we = addr_hit[637] & reg_we & !reg_error;
+
+ assign wkup_detector_cnt_th_7_we = addr_hit[638] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_0_we = addr_hit[639] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_1_we = addr_hit[640] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_2_we = addr_hit[641] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_3_we = addr_hit[642] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_4_we = addr_hit[643] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_5_we = addr_hit[644] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_6_we = addr_hit[645] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
+ assign wkup_detector_padsel_7_we = addr_hit[646] & reg_we & !reg_error;
+
+ assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
+ assign wkup_cause_we = addr_hit[647] & reg_we & !reg_error;
+
+
+
+
+
+
+
+
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = alert_test_we;
+ reg_we_check[1] = mio_periph_insel_regwen_0_we;
+ reg_we_check[2] = mio_periph_insel_regwen_1_we;
+ reg_we_check[3] = mio_periph_insel_regwen_2_we;
+ reg_we_check[4] = mio_periph_insel_regwen_3_we;
+ reg_we_check[5] = mio_periph_insel_regwen_4_we;
+ reg_we_check[6] = mio_periph_insel_regwen_5_we;
+ reg_we_check[7] = mio_periph_insel_regwen_6_we;
+ reg_we_check[8] = mio_periph_insel_regwen_7_we;
+ reg_we_check[9] = mio_periph_insel_regwen_8_we;
+ reg_we_check[10] = mio_periph_insel_regwen_9_we;
+ reg_we_check[11] = mio_periph_insel_regwen_10_we;
+ reg_we_check[12] = mio_periph_insel_regwen_11_we;
+ reg_we_check[13] = mio_periph_insel_regwen_12_we;
+ reg_we_check[14] = mio_periph_insel_regwen_13_we;
+ reg_we_check[15] = mio_periph_insel_regwen_14_we;
+ reg_we_check[16] = mio_periph_insel_regwen_15_we;
+ reg_we_check[17] = mio_periph_insel_regwen_16_we;
+ reg_we_check[18] = mio_periph_insel_regwen_17_we;
+ reg_we_check[19] = mio_periph_insel_regwen_18_we;
+ reg_we_check[20] = mio_periph_insel_regwen_19_we;
+ reg_we_check[21] = mio_periph_insel_regwen_20_we;
+ reg_we_check[22] = mio_periph_insel_regwen_21_we;
+ reg_we_check[23] = mio_periph_insel_regwen_22_we;
+ reg_we_check[24] = mio_periph_insel_regwen_23_we;
+ reg_we_check[25] = mio_periph_insel_regwen_24_we;
+ reg_we_check[26] = mio_periph_insel_regwen_25_we;
+ reg_we_check[27] = mio_periph_insel_regwen_26_we;
+ reg_we_check[28] = mio_periph_insel_regwen_27_we;
+ reg_we_check[29] = mio_periph_insel_regwen_28_we;
+ reg_we_check[30] = mio_periph_insel_regwen_29_we;
+ reg_we_check[31] = mio_periph_insel_regwen_30_we;
+ reg_we_check[32] = mio_periph_insel_regwen_31_we;
+ reg_we_check[33] = mio_periph_insel_regwen_32_we;
+ reg_we_check[34] = mio_periph_insel_regwen_33_we;
+ reg_we_check[35] = mio_periph_insel_regwen_34_we;
+ reg_we_check[36] = mio_periph_insel_regwen_35_we;
+ reg_we_check[37] = mio_periph_insel_regwen_36_we;
+ reg_we_check[38] = mio_periph_insel_regwen_37_we;
+ reg_we_check[39] = mio_periph_insel_regwen_38_we;
+ reg_we_check[40] = mio_periph_insel_regwen_39_we;
+ reg_we_check[41] = mio_periph_insel_regwen_40_we;
+ reg_we_check[42] = mio_periph_insel_regwen_41_we;
+ reg_we_check[43] = mio_periph_insel_regwen_42_we;
+ reg_we_check[44] = mio_periph_insel_regwen_43_we;
+ reg_we_check[45] = mio_periph_insel_regwen_44_we;
+ reg_we_check[46] = mio_periph_insel_regwen_45_we;
+ reg_we_check[47] = mio_periph_insel_regwen_46_we;
+ reg_we_check[48] = mio_periph_insel_regwen_47_we;
+ reg_we_check[49] = mio_periph_insel_regwen_48_we;
+ reg_we_check[50] = mio_periph_insel_regwen_49_we;
+ reg_we_check[51] = mio_periph_insel_regwen_50_we;
+ reg_we_check[52] = mio_periph_insel_regwen_51_we;
+ reg_we_check[53] = mio_periph_insel_regwen_52_we;
+ reg_we_check[54] = mio_periph_insel_regwen_53_we;
+ reg_we_check[55] = mio_periph_insel_regwen_54_we;
+ reg_we_check[56] = mio_periph_insel_regwen_55_we;
+ reg_we_check[57] = mio_periph_insel_regwen_56_we;
+ reg_we_check[58] = mio_periph_insel_regwen_57_we;
+ reg_we_check[59] = mio_periph_insel_regwen_58_we;
+ reg_we_check[60] = mio_periph_insel_regwen_59_we;
+ reg_we_check[61] = mio_periph_insel_regwen_60_we;
+ reg_we_check[62] = mio_periph_insel_regwen_61_we;
+ reg_we_check[63] = mio_periph_insel_regwen_62_we;
+ reg_we_check[64] = mio_periph_insel_regwen_63_we;
+ reg_we_check[65] = mio_periph_insel_regwen_64_we;
+ reg_we_check[66] = mio_periph_insel_regwen_65_we;
+ reg_we_check[67] = mio_periph_insel_regwen_66_we;
+ reg_we_check[68] = mio_periph_insel_regwen_67_we;
+ reg_we_check[69] = mio_periph_insel_regwen_68_we;
+ reg_we_check[70] = mio_periph_insel_regwen_69_we;
+ reg_we_check[71] = mio_periph_insel_regwen_70_we;
+ reg_we_check[72] = mio_periph_insel_regwen_71_we;
+ reg_we_check[73] = mio_periph_insel_regwen_72_we;
+ reg_we_check[74] = mio_periph_insel_regwen_73_we;
+ reg_we_check[75] = mio_periph_insel_regwen_74_we;
+ reg_we_check[76] = mio_periph_insel_regwen_75_we;
+ reg_we_check[77] = mio_periph_insel_0_gated_we;
+ reg_we_check[78] = mio_periph_insel_1_gated_we;
+ reg_we_check[79] = mio_periph_insel_2_gated_we;
+ reg_we_check[80] = mio_periph_insel_3_gated_we;
+ reg_we_check[81] = mio_periph_insel_4_gated_we;
+ reg_we_check[82] = mio_periph_insel_5_gated_we;
+ reg_we_check[83] = mio_periph_insel_6_gated_we;
+ reg_we_check[84] = mio_periph_insel_7_gated_we;
+ reg_we_check[85] = mio_periph_insel_8_gated_we;
+ reg_we_check[86] = mio_periph_insel_9_gated_we;
+ reg_we_check[87] = mio_periph_insel_10_gated_we;
+ reg_we_check[88] = mio_periph_insel_11_gated_we;
+ reg_we_check[89] = mio_periph_insel_12_gated_we;
+ reg_we_check[90] = mio_periph_insel_13_gated_we;
+ reg_we_check[91] = mio_periph_insel_14_gated_we;
+ reg_we_check[92] = mio_periph_insel_15_gated_we;
+ reg_we_check[93] = mio_periph_insel_16_gated_we;
+ reg_we_check[94] = mio_periph_insel_17_gated_we;
+ reg_we_check[95] = mio_periph_insel_18_gated_we;
+ reg_we_check[96] = mio_periph_insel_19_gated_we;
+ reg_we_check[97] = mio_periph_insel_20_gated_we;
+ reg_we_check[98] = mio_periph_insel_21_gated_we;
+ reg_we_check[99] = mio_periph_insel_22_gated_we;
+ reg_we_check[100] = mio_periph_insel_23_gated_we;
+ reg_we_check[101] = mio_periph_insel_24_gated_we;
+ reg_we_check[102] = mio_periph_insel_25_gated_we;
+ reg_we_check[103] = mio_periph_insel_26_gated_we;
+ reg_we_check[104] = mio_periph_insel_27_gated_we;
+ reg_we_check[105] = mio_periph_insel_28_gated_we;
+ reg_we_check[106] = mio_periph_insel_29_gated_we;
+ reg_we_check[107] = mio_periph_insel_30_gated_we;
+ reg_we_check[108] = mio_periph_insel_31_gated_we;
+ reg_we_check[109] = mio_periph_insel_32_gated_we;
+ reg_we_check[110] = mio_periph_insel_33_gated_we;
+ reg_we_check[111] = mio_periph_insel_34_gated_we;
+ reg_we_check[112] = mio_periph_insel_35_gated_we;
+ reg_we_check[113] = mio_periph_insel_36_gated_we;
+ reg_we_check[114] = mio_periph_insel_37_gated_we;
+ reg_we_check[115] = mio_periph_insel_38_gated_we;
+ reg_we_check[116] = mio_periph_insel_39_gated_we;
+ reg_we_check[117] = mio_periph_insel_40_gated_we;
+ reg_we_check[118] = mio_periph_insel_41_gated_we;
+ reg_we_check[119] = mio_periph_insel_42_gated_we;
+ reg_we_check[120] = mio_periph_insel_43_gated_we;
+ reg_we_check[121] = mio_periph_insel_44_gated_we;
+ reg_we_check[122] = mio_periph_insel_45_gated_we;
+ reg_we_check[123] = mio_periph_insel_46_gated_we;
+ reg_we_check[124] = mio_periph_insel_47_gated_we;
+ reg_we_check[125] = mio_periph_insel_48_gated_we;
+ reg_we_check[126] = mio_periph_insel_49_gated_we;
+ reg_we_check[127] = mio_periph_insel_50_gated_we;
+ reg_we_check[128] = mio_periph_insel_51_gated_we;
+ reg_we_check[129] = mio_periph_insel_52_gated_we;
+ reg_we_check[130] = mio_periph_insel_53_gated_we;
+ reg_we_check[131] = mio_periph_insel_54_gated_we;
+ reg_we_check[132] = mio_periph_insel_55_gated_we;
+ reg_we_check[133] = mio_periph_insel_56_gated_we;
+ reg_we_check[134] = mio_periph_insel_57_gated_we;
+ reg_we_check[135] = mio_periph_insel_58_gated_we;
+ reg_we_check[136] = mio_periph_insel_59_gated_we;
+ reg_we_check[137] = mio_periph_insel_60_gated_we;
+ reg_we_check[138] = mio_periph_insel_61_gated_we;
+ reg_we_check[139] = mio_periph_insel_62_gated_we;
+ reg_we_check[140] = mio_periph_insel_63_gated_we;
+ reg_we_check[141] = mio_periph_insel_64_gated_we;
+ reg_we_check[142] = mio_periph_insel_65_gated_we;
+ reg_we_check[143] = mio_periph_insel_66_gated_we;
+ reg_we_check[144] = mio_periph_insel_67_gated_we;
+ reg_we_check[145] = mio_periph_insel_68_gated_we;
+ reg_we_check[146] = mio_periph_insel_69_gated_we;
+ reg_we_check[147] = mio_periph_insel_70_gated_we;
+ reg_we_check[148] = mio_periph_insel_71_gated_we;
+ reg_we_check[149] = mio_periph_insel_72_gated_we;
+ reg_we_check[150] = mio_periph_insel_73_gated_we;
+ reg_we_check[151] = mio_periph_insel_74_gated_we;
+ reg_we_check[152] = mio_periph_insel_75_gated_we;
+ reg_we_check[153] = mio_outsel_regwen_0_we;
+ reg_we_check[154] = mio_outsel_regwen_1_we;
+ reg_we_check[155] = mio_outsel_regwen_2_we;
+ reg_we_check[156] = mio_outsel_regwen_3_we;
+ reg_we_check[157] = mio_outsel_regwen_4_we;
+ reg_we_check[158] = mio_outsel_regwen_5_we;
+ reg_we_check[159] = mio_outsel_regwen_6_we;
+ reg_we_check[160] = mio_outsel_regwen_7_we;
+ reg_we_check[161] = mio_outsel_regwen_8_we;
+ reg_we_check[162] = mio_outsel_regwen_9_we;
+ reg_we_check[163] = mio_outsel_regwen_10_we;
+ reg_we_check[164] = mio_outsel_regwen_11_we;
+ reg_we_check[165] = mio_outsel_regwen_12_we;
+ reg_we_check[166] = mio_outsel_regwen_13_we;
+ reg_we_check[167] = mio_outsel_regwen_14_we;
+ reg_we_check[168] = mio_outsel_regwen_15_we;
+ reg_we_check[169] = mio_outsel_regwen_16_we;
+ reg_we_check[170] = mio_outsel_regwen_17_we;
+ reg_we_check[171] = mio_outsel_regwen_18_we;
+ reg_we_check[172] = mio_outsel_regwen_19_we;
+ reg_we_check[173] = mio_outsel_regwen_20_we;
+ reg_we_check[174] = mio_outsel_regwen_21_we;
+ reg_we_check[175] = mio_outsel_regwen_22_we;
+ reg_we_check[176] = mio_outsel_regwen_23_we;
+ reg_we_check[177] = mio_outsel_regwen_24_we;
+ reg_we_check[178] = mio_outsel_regwen_25_we;
+ reg_we_check[179] = mio_outsel_regwen_26_we;
+ reg_we_check[180] = mio_outsel_regwen_27_we;
+ reg_we_check[181] = mio_outsel_regwen_28_we;
+ reg_we_check[182] = mio_outsel_regwen_29_we;
+ reg_we_check[183] = mio_outsel_regwen_30_we;
+ reg_we_check[184] = mio_outsel_regwen_31_we;
+ reg_we_check[185] = mio_outsel_regwen_32_we;
+ reg_we_check[186] = mio_outsel_regwen_33_we;
+ reg_we_check[187] = mio_outsel_regwen_34_we;
+ reg_we_check[188] = mio_outsel_regwen_35_we;
+ reg_we_check[189] = mio_outsel_regwen_36_we;
+ reg_we_check[190] = mio_outsel_regwen_37_we;
+ reg_we_check[191] = mio_outsel_regwen_38_we;
+ reg_we_check[192] = mio_outsel_regwen_39_we;
+ reg_we_check[193] = mio_outsel_regwen_40_we;
+ reg_we_check[194] = mio_outsel_regwen_41_we;
+ reg_we_check[195] = mio_outsel_regwen_42_we;
+ reg_we_check[196] = mio_outsel_regwen_43_we;
+ reg_we_check[197] = mio_outsel_regwen_44_we;
+ reg_we_check[198] = mio_outsel_regwen_45_we;
+ reg_we_check[199] = mio_outsel_regwen_46_we;
+ reg_we_check[200] = mio_outsel_regwen_47_we;
+ reg_we_check[201] = mio_outsel_regwen_48_we;
+ reg_we_check[202] = mio_outsel_regwen_49_we;
+ reg_we_check[203] = mio_outsel_regwen_50_we;
+ reg_we_check[204] = mio_outsel_regwen_51_we;
+ reg_we_check[205] = mio_outsel_regwen_52_we;
+ reg_we_check[206] = mio_outsel_0_gated_we;
+ reg_we_check[207] = mio_outsel_1_gated_we;
+ reg_we_check[208] = mio_outsel_2_gated_we;
+ reg_we_check[209] = mio_outsel_3_gated_we;
+ reg_we_check[210] = mio_outsel_4_gated_we;
+ reg_we_check[211] = mio_outsel_5_gated_we;
+ reg_we_check[212] = mio_outsel_6_gated_we;
+ reg_we_check[213] = mio_outsel_7_gated_we;
+ reg_we_check[214] = mio_outsel_8_gated_we;
+ reg_we_check[215] = mio_outsel_9_gated_we;
+ reg_we_check[216] = mio_outsel_10_gated_we;
+ reg_we_check[217] = mio_outsel_11_gated_we;
+ reg_we_check[218] = mio_outsel_12_gated_we;
+ reg_we_check[219] = mio_outsel_13_gated_we;
+ reg_we_check[220] = mio_outsel_14_gated_we;
+ reg_we_check[221] = mio_outsel_15_gated_we;
+ reg_we_check[222] = mio_outsel_16_gated_we;
+ reg_we_check[223] = mio_outsel_17_gated_we;
+ reg_we_check[224] = mio_outsel_18_gated_we;
+ reg_we_check[225] = mio_outsel_19_gated_we;
+ reg_we_check[226] = mio_outsel_20_gated_we;
+ reg_we_check[227] = mio_outsel_21_gated_we;
+ reg_we_check[228] = mio_outsel_22_gated_we;
+ reg_we_check[229] = mio_outsel_23_gated_we;
+ reg_we_check[230] = mio_outsel_24_gated_we;
+ reg_we_check[231] = mio_outsel_25_gated_we;
+ reg_we_check[232] = mio_outsel_26_gated_we;
+ reg_we_check[233] = mio_outsel_27_gated_we;
+ reg_we_check[234] = mio_outsel_28_gated_we;
+ reg_we_check[235] = mio_outsel_29_gated_we;
+ reg_we_check[236] = mio_outsel_30_gated_we;
+ reg_we_check[237] = mio_outsel_31_gated_we;
+ reg_we_check[238] = mio_outsel_32_gated_we;
+ reg_we_check[239] = mio_outsel_33_gated_we;
+ reg_we_check[240] = mio_outsel_34_gated_we;
+ reg_we_check[241] = mio_outsel_35_gated_we;
+ reg_we_check[242] = mio_outsel_36_gated_we;
+ reg_we_check[243] = mio_outsel_37_gated_we;
+ reg_we_check[244] = mio_outsel_38_gated_we;
+ reg_we_check[245] = mio_outsel_39_gated_we;
+ reg_we_check[246] = mio_outsel_40_gated_we;
+ reg_we_check[247] = mio_outsel_41_gated_we;
+ reg_we_check[248] = mio_outsel_42_gated_we;
+ reg_we_check[249] = mio_outsel_43_gated_we;
+ reg_we_check[250] = mio_outsel_44_gated_we;
+ reg_we_check[251] = mio_outsel_45_gated_we;
+ reg_we_check[252] = mio_outsel_46_gated_we;
+ reg_we_check[253] = mio_outsel_47_gated_we;
+ reg_we_check[254] = mio_outsel_48_gated_we;
+ reg_we_check[255] = mio_outsel_49_gated_we;
+ reg_we_check[256] = mio_outsel_50_gated_we;
+ reg_we_check[257] = mio_outsel_51_gated_we;
+ reg_we_check[258] = mio_outsel_52_gated_we;
+ reg_we_check[259] = mio_pad_attr_regwen_0_we;
+ reg_we_check[260] = mio_pad_attr_regwen_1_we;
+ reg_we_check[261] = mio_pad_attr_regwen_2_we;
+ reg_we_check[262] = mio_pad_attr_regwen_3_we;
+ reg_we_check[263] = mio_pad_attr_regwen_4_we;
+ reg_we_check[264] = mio_pad_attr_regwen_5_we;
+ reg_we_check[265] = mio_pad_attr_regwen_6_we;
+ reg_we_check[266] = mio_pad_attr_regwen_7_we;
+ reg_we_check[267] = mio_pad_attr_regwen_8_we;
+ reg_we_check[268] = mio_pad_attr_regwen_9_we;
+ reg_we_check[269] = mio_pad_attr_regwen_10_we;
+ reg_we_check[270] = mio_pad_attr_regwen_11_we;
+ reg_we_check[271] = mio_pad_attr_regwen_12_we;
+ reg_we_check[272] = mio_pad_attr_regwen_13_we;
+ reg_we_check[273] = mio_pad_attr_regwen_14_we;
+ reg_we_check[274] = mio_pad_attr_regwen_15_we;
+ reg_we_check[275] = mio_pad_attr_regwen_16_we;
+ reg_we_check[276] = mio_pad_attr_regwen_17_we;
+ reg_we_check[277] = mio_pad_attr_regwen_18_we;
+ reg_we_check[278] = mio_pad_attr_regwen_19_we;
+ reg_we_check[279] = mio_pad_attr_regwen_20_we;
+ reg_we_check[280] = mio_pad_attr_regwen_21_we;
+ reg_we_check[281] = mio_pad_attr_regwen_22_we;
+ reg_we_check[282] = mio_pad_attr_regwen_23_we;
+ reg_we_check[283] = mio_pad_attr_regwen_24_we;
+ reg_we_check[284] = mio_pad_attr_regwen_25_we;
+ reg_we_check[285] = mio_pad_attr_regwen_26_we;
+ reg_we_check[286] = mio_pad_attr_regwen_27_we;
+ reg_we_check[287] = mio_pad_attr_regwen_28_we;
+ reg_we_check[288] = mio_pad_attr_regwen_29_we;
+ reg_we_check[289] = mio_pad_attr_regwen_30_we;
+ reg_we_check[290] = mio_pad_attr_regwen_31_we;
+ reg_we_check[291] = mio_pad_attr_regwen_32_we;
+ reg_we_check[292] = mio_pad_attr_regwen_33_we;
+ reg_we_check[293] = mio_pad_attr_regwen_34_we;
+ reg_we_check[294] = mio_pad_attr_regwen_35_we;
+ reg_we_check[295] = mio_pad_attr_regwen_36_we;
+ reg_we_check[296] = mio_pad_attr_regwen_37_we;
+ reg_we_check[297] = mio_pad_attr_regwen_38_we;
+ reg_we_check[298] = mio_pad_attr_regwen_39_we;
+ reg_we_check[299] = mio_pad_attr_regwen_40_we;
+ reg_we_check[300] = mio_pad_attr_regwen_41_we;
+ reg_we_check[301] = mio_pad_attr_regwen_42_we;
+ reg_we_check[302] = mio_pad_attr_regwen_43_we;
+ reg_we_check[303] = mio_pad_attr_regwen_44_we;
+ reg_we_check[304] = mio_pad_attr_regwen_45_we;
+ reg_we_check[305] = mio_pad_attr_regwen_46_we;
+ reg_we_check[306] = mio_pad_attr_regwen_47_we;
+ reg_we_check[307] = mio_pad_attr_regwen_48_we;
+ reg_we_check[308] = mio_pad_attr_regwen_49_we;
+ reg_we_check[309] = mio_pad_attr_regwen_50_we;
+ reg_we_check[310] = mio_pad_attr_regwen_51_we;
+ reg_we_check[311] = mio_pad_attr_regwen_52_we;
+ reg_we_check[312] = mio_pad_attr_0_gated_we;
+ reg_we_check[313] = mio_pad_attr_1_gated_we;
+ reg_we_check[314] = mio_pad_attr_2_gated_we;
+ reg_we_check[315] = mio_pad_attr_3_gated_we;
+ reg_we_check[316] = mio_pad_attr_4_gated_we;
+ reg_we_check[317] = mio_pad_attr_5_gated_we;
+ reg_we_check[318] = mio_pad_attr_6_gated_we;
+ reg_we_check[319] = mio_pad_attr_7_gated_we;
+ reg_we_check[320] = mio_pad_attr_8_gated_we;
+ reg_we_check[321] = mio_pad_attr_9_gated_we;
+ reg_we_check[322] = mio_pad_attr_10_gated_we;
+ reg_we_check[323] = mio_pad_attr_11_gated_we;
+ reg_we_check[324] = mio_pad_attr_12_gated_we;
+ reg_we_check[325] = mio_pad_attr_13_gated_we;
+ reg_we_check[326] = mio_pad_attr_14_gated_we;
+ reg_we_check[327] = mio_pad_attr_15_gated_we;
+ reg_we_check[328] = mio_pad_attr_16_gated_we;
+ reg_we_check[329] = mio_pad_attr_17_gated_we;
+ reg_we_check[330] = mio_pad_attr_18_gated_we;
+ reg_we_check[331] = mio_pad_attr_19_gated_we;
+ reg_we_check[332] = mio_pad_attr_20_gated_we;
+ reg_we_check[333] = mio_pad_attr_21_gated_we;
+ reg_we_check[334] = mio_pad_attr_22_gated_we;
+ reg_we_check[335] = mio_pad_attr_23_gated_we;
+ reg_we_check[336] = mio_pad_attr_24_gated_we;
+ reg_we_check[337] = mio_pad_attr_25_gated_we;
+ reg_we_check[338] = mio_pad_attr_26_gated_we;
+ reg_we_check[339] = mio_pad_attr_27_gated_we;
+ reg_we_check[340] = mio_pad_attr_28_gated_we;
+ reg_we_check[341] = mio_pad_attr_29_gated_we;
+ reg_we_check[342] = mio_pad_attr_30_gated_we;
+ reg_we_check[343] = mio_pad_attr_31_gated_we;
+ reg_we_check[344] = mio_pad_attr_32_gated_we;
+ reg_we_check[345] = mio_pad_attr_33_gated_we;
+ reg_we_check[346] = mio_pad_attr_34_gated_we;
+ reg_we_check[347] = mio_pad_attr_35_gated_we;
+ reg_we_check[348] = mio_pad_attr_36_gated_we;
+ reg_we_check[349] = mio_pad_attr_37_gated_we;
+ reg_we_check[350] = mio_pad_attr_38_gated_we;
+ reg_we_check[351] = mio_pad_attr_39_gated_we;
+ reg_we_check[352] = mio_pad_attr_40_gated_we;
+ reg_we_check[353] = mio_pad_attr_41_gated_we;
+ reg_we_check[354] = mio_pad_attr_42_gated_we;
+ reg_we_check[355] = mio_pad_attr_43_gated_we;
+ reg_we_check[356] = mio_pad_attr_44_gated_we;
+ reg_we_check[357] = mio_pad_attr_45_gated_we;
+ reg_we_check[358] = mio_pad_attr_46_gated_we;
+ reg_we_check[359] = mio_pad_attr_47_gated_we;
+ reg_we_check[360] = mio_pad_attr_48_gated_we;
+ reg_we_check[361] = mio_pad_attr_49_gated_we;
+ reg_we_check[362] = mio_pad_attr_50_gated_we;
+ reg_we_check[363] = mio_pad_attr_51_gated_we;
+ reg_we_check[364] = mio_pad_attr_52_gated_we;
+ reg_we_check[365] = dio_pad_attr_regwen_0_we;
+ reg_we_check[366] = dio_pad_attr_regwen_1_we;
+ reg_we_check[367] = dio_pad_attr_regwen_2_we;
+ reg_we_check[368] = dio_pad_attr_regwen_3_we;
+ reg_we_check[369] = dio_pad_attr_regwen_4_we;
+ reg_we_check[370] = dio_pad_attr_regwen_5_we;
+ reg_we_check[371] = dio_pad_attr_regwen_6_we;
+ reg_we_check[372] = dio_pad_attr_regwen_7_we;
+ reg_we_check[373] = dio_pad_attr_regwen_8_we;
+ reg_we_check[374] = dio_pad_attr_regwen_9_we;
+ reg_we_check[375] = dio_pad_attr_regwen_10_we;
+ reg_we_check[376] = dio_pad_attr_regwen_11_we;
+ reg_we_check[377] = dio_pad_attr_regwen_12_we;
+ reg_we_check[378] = dio_pad_attr_regwen_13_we;
+ reg_we_check[379] = dio_pad_attr_regwen_14_we;
+ reg_we_check[380] = dio_pad_attr_regwen_15_we;
+ reg_we_check[381] = dio_pad_attr_0_gated_we;
+ reg_we_check[382] = dio_pad_attr_1_gated_we;
+ reg_we_check[383] = dio_pad_attr_2_gated_we;
+ reg_we_check[384] = dio_pad_attr_3_gated_we;
+ reg_we_check[385] = dio_pad_attr_4_gated_we;
+ reg_we_check[386] = dio_pad_attr_5_gated_we;
+ reg_we_check[387] = dio_pad_attr_6_gated_we;
+ reg_we_check[388] = dio_pad_attr_7_gated_we;
+ reg_we_check[389] = dio_pad_attr_8_gated_we;
+ reg_we_check[390] = dio_pad_attr_9_gated_we;
+ reg_we_check[391] = dio_pad_attr_10_gated_we;
+ reg_we_check[392] = dio_pad_attr_11_gated_we;
+ reg_we_check[393] = dio_pad_attr_12_gated_we;
+ reg_we_check[394] = dio_pad_attr_13_gated_we;
+ reg_we_check[395] = dio_pad_attr_14_gated_we;
+ reg_we_check[396] = dio_pad_attr_15_gated_we;
+ reg_we_check[397] = mio_pad_sleep_status_0_we;
+ reg_we_check[398] = mio_pad_sleep_status_1_we;
+ reg_we_check[399] = mio_pad_sleep_regwen_0_we;
+ reg_we_check[400] = mio_pad_sleep_regwen_1_we;
+ reg_we_check[401] = mio_pad_sleep_regwen_2_we;
+ reg_we_check[402] = mio_pad_sleep_regwen_3_we;
+ reg_we_check[403] = mio_pad_sleep_regwen_4_we;
+ reg_we_check[404] = mio_pad_sleep_regwen_5_we;
+ reg_we_check[405] = mio_pad_sleep_regwen_6_we;
+ reg_we_check[406] = mio_pad_sleep_regwen_7_we;
+ reg_we_check[407] = mio_pad_sleep_regwen_8_we;
+ reg_we_check[408] = mio_pad_sleep_regwen_9_we;
+ reg_we_check[409] = mio_pad_sleep_regwen_10_we;
+ reg_we_check[410] = mio_pad_sleep_regwen_11_we;
+ reg_we_check[411] = mio_pad_sleep_regwen_12_we;
+ reg_we_check[412] = mio_pad_sleep_regwen_13_we;
+ reg_we_check[413] = mio_pad_sleep_regwen_14_we;
+ reg_we_check[414] = mio_pad_sleep_regwen_15_we;
+ reg_we_check[415] = mio_pad_sleep_regwen_16_we;
+ reg_we_check[416] = mio_pad_sleep_regwen_17_we;
+ reg_we_check[417] = mio_pad_sleep_regwen_18_we;
+ reg_we_check[418] = mio_pad_sleep_regwen_19_we;
+ reg_we_check[419] = mio_pad_sleep_regwen_20_we;
+ reg_we_check[420] = mio_pad_sleep_regwen_21_we;
+ reg_we_check[421] = mio_pad_sleep_regwen_22_we;
+ reg_we_check[422] = mio_pad_sleep_regwen_23_we;
+ reg_we_check[423] = mio_pad_sleep_regwen_24_we;
+ reg_we_check[424] = mio_pad_sleep_regwen_25_we;
+ reg_we_check[425] = mio_pad_sleep_regwen_26_we;
+ reg_we_check[426] = mio_pad_sleep_regwen_27_we;
+ reg_we_check[427] = mio_pad_sleep_regwen_28_we;
+ reg_we_check[428] = mio_pad_sleep_regwen_29_we;
+ reg_we_check[429] = mio_pad_sleep_regwen_30_we;
+ reg_we_check[430] = mio_pad_sleep_regwen_31_we;
+ reg_we_check[431] = mio_pad_sleep_regwen_32_we;
+ reg_we_check[432] = mio_pad_sleep_regwen_33_we;
+ reg_we_check[433] = mio_pad_sleep_regwen_34_we;
+ reg_we_check[434] = mio_pad_sleep_regwen_35_we;
+ reg_we_check[435] = mio_pad_sleep_regwen_36_we;
+ reg_we_check[436] = mio_pad_sleep_regwen_37_we;
+ reg_we_check[437] = mio_pad_sleep_regwen_38_we;
+ reg_we_check[438] = mio_pad_sleep_regwen_39_we;
+ reg_we_check[439] = mio_pad_sleep_regwen_40_we;
+ reg_we_check[440] = mio_pad_sleep_regwen_41_we;
+ reg_we_check[441] = mio_pad_sleep_regwen_42_we;
+ reg_we_check[442] = mio_pad_sleep_regwen_43_we;
+ reg_we_check[443] = mio_pad_sleep_regwen_44_we;
+ reg_we_check[444] = mio_pad_sleep_regwen_45_we;
+ reg_we_check[445] = mio_pad_sleep_regwen_46_we;
+ reg_we_check[446] = mio_pad_sleep_regwen_47_we;
+ reg_we_check[447] = mio_pad_sleep_regwen_48_we;
+ reg_we_check[448] = mio_pad_sleep_regwen_49_we;
+ reg_we_check[449] = mio_pad_sleep_regwen_50_we;
+ reg_we_check[450] = mio_pad_sleep_regwen_51_we;
+ reg_we_check[451] = mio_pad_sleep_regwen_52_we;
+ reg_we_check[452] = mio_pad_sleep_en_0_gated_we;
+ reg_we_check[453] = mio_pad_sleep_en_1_gated_we;
+ reg_we_check[454] = mio_pad_sleep_en_2_gated_we;
+ reg_we_check[455] = mio_pad_sleep_en_3_gated_we;
+ reg_we_check[456] = mio_pad_sleep_en_4_gated_we;
+ reg_we_check[457] = mio_pad_sleep_en_5_gated_we;
+ reg_we_check[458] = mio_pad_sleep_en_6_gated_we;
+ reg_we_check[459] = mio_pad_sleep_en_7_gated_we;
+ reg_we_check[460] = mio_pad_sleep_en_8_gated_we;
+ reg_we_check[461] = mio_pad_sleep_en_9_gated_we;
+ reg_we_check[462] = mio_pad_sleep_en_10_gated_we;
+ reg_we_check[463] = mio_pad_sleep_en_11_gated_we;
+ reg_we_check[464] = mio_pad_sleep_en_12_gated_we;
+ reg_we_check[465] = mio_pad_sleep_en_13_gated_we;
+ reg_we_check[466] = mio_pad_sleep_en_14_gated_we;
+ reg_we_check[467] = mio_pad_sleep_en_15_gated_we;
+ reg_we_check[468] = mio_pad_sleep_en_16_gated_we;
+ reg_we_check[469] = mio_pad_sleep_en_17_gated_we;
+ reg_we_check[470] = mio_pad_sleep_en_18_gated_we;
+ reg_we_check[471] = mio_pad_sleep_en_19_gated_we;
+ reg_we_check[472] = mio_pad_sleep_en_20_gated_we;
+ reg_we_check[473] = mio_pad_sleep_en_21_gated_we;
+ reg_we_check[474] = mio_pad_sleep_en_22_gated_we;
+ reg_we_check[475] = mio_pad_sleep_en_23_gated_we;
+ reg_we_check[476] = mio_pad_sleep_en_24_gated_we;
+ reg_we_check[477] = mio_pad_sleep_en_25_gated_we;
+ reg_we_check[478] = mio_pad_sleep_en_26_gated_we;
+ reg_we_check[479] = mio_pad_sleep_en_27_gated_we;
+ reg_we_check[480] = mio_pad_sleep_en_28_gated_we;
+ reg_we_check[481] = mio_pad_sleep_en_29_gated_we;
+ reg_we_check[482] = mio_pad_sleep_en_30_gated_we;
+ reg_we_check[483] = mio_pad_sleep_en_31_gated_we;
+ reg_we_check[484] = mio_pad_sleep_en_32_gated_we;
+ reg_we_check[485] = mio_pad_sleep_en_33_gated_we;
+ reg_we_check[486] = mio_pad_sleep_en_34_gated_we;
+ reg_we_check[487] = mio_pad_sleep_en_35_gated_we;
+ reg_we_check[488] = mio_pad_sleep_en_36_gated_we;
+ reg_we_check[489] = mio_pad_sleep_en_37_gated_we;
+ reg_we_check[490] = mio_pad_sleep_en_38_gated_we;
+ reg_we_check[491] = mio_pad_sleep_en_39_gated_we;
+ reg_we_check[492] = mio_pad_sleep_en_40_gated_we;
+ reg_we_check[493] = mio_pad_sleep_en_41_gated_we;
+ reg_we_check[494] = mio_pad_sleep_en_42_gated_we;
+ reg_we_check[495] = mio_pad_sleep_en_43_gated_we;
+ reg_we_check[496] = mio_pad_sleep_en_44_gated_we;
+ reg_we_check[497] = mio_pad_sleep_en_45_gated_we;
+ reg_we_check[498] = mio_pad_sleep_en_46_gated_we;
+ reg_we_check[499] = mio_pad_sleep_en_47_gated_we;
+ reg_we_check[500] = mio_pad_sleep_en_48_gated_we;
+ reg_we_check[501] = mio_pad_sleep_en_49_gated_we;
+ reg_we_check[502] = mio_pad_sleep_en_50_gated_we;
+ reg_we_check[503] = mio_pad_sleep_en_51_gated_we;
+ reg_we_check[504] = mio_pad_sleep_en_52_gated_we;
+ reg_we_check[505] = mio_pad_sleep_mode_0_gated_we;
+ reg_we_check[506] = mio_pad_sleep_mode_1_gated_we;
+ reg_we_check[507] = mio_pad_sleep_mode_2_gated_we;
+ reg_we_check[508] = mio_pad_sleep_mode_3_gated_we;
+ reg_we_check[509] = mio_pad_sleep_mode_4_gated_we;
+ reg_we_check[510] = mio_pad_sleep_mode_5_gated_we;
+ reg_we_check[511] = mio_pad_sleep_mode_6_gated_we;
+ reg_we_check[512] = mio_pad_sleep_mode_7_gated_we;
+ reg_we_check[513] = mio_pad_sleep_mode_8_gated_we;
+ reg_we_check[514] = mio_pad_sleep_mode_9_gated_we;
+ reg_we_check[515] = mio_pad_sleep_mode_10_gated_we;
+ reg_we_check[516] = mio_pad_sleep_mode_11_gated_we;
+ reg_we_check[517] = mio_pad_sleep_mode_12_gated_we;
+ reg_we_check[518] = mio_pad_sleep_mode_13_gated_we;
+ reg_we_check[519] = mio_pad_sleep_mode_14_gated_we;
+ reg_we_check[520] = mio_pad_sleep_mode_15_gated_we;
+ reg_we_check[521] = mio_pad_sleep_mode_16_gated_we;
+ reg_we_check[522] = mio_pad_sleep_mode_17_gated_we;
+ reg_we_check[523] = mio_pad_sleep_mode_18_gated_we;
+ reg_we_check[524] = mio_pad_sleep_mode_19_gated_we;
+ reg_we_check[525] = mio_pad_sleep_mode_20_gated_we;
+ reg_we_check[526] = mio_pad_sleep_mode_21_gated_we;
+ reg_we_check[527] = mio_pad_sleep_mode_22_gated_we;
+ reg_we_check[528] = mio_pad_sleep_mode_23_gated_we;
+ reg_we_check[529] = mio_pad_sleep_mode_24_gated_we;
+ reg_we_check[530] = mio_pad_sleep_mode_25_gated_we;
+ reg_we_check[531] = mio_pad_sleep_mode_26_gated_we;
+ reg_we_check[532] = mio_pad_sleep_mode_27_gated_we;
+ reg_we_check[533] = mio_pad_sleep_mode_28_gated_we;
+ reg_we_check[534] = mio_pad_sleep_mode_29_gated_we;
+ reg_we_check[535] = mio_pad_sleep_mode_30_gated_we;
+ reg_we_check[536] = mio_pad_sleep_mode_31_gated_we;
+ reg_we_check[537] = mio_pad_sleep_mode_32_gated_we;
+ reg_we_check[538] = mio_pad_sleep_mode_33_gated_we;
+ reg_we_check[539] = mio_pad_sleep_mode_34_gated_we;
+ reg_we_check[540] = mio_pad_sleep_mode_35_gated_we;
+ reg_we_check[541] = mio_pad_sleep_mode_36_gated_we;
+ reg_we_check[542] = mio_pad_sleep_mode_37_gated_we;
+ reg_we_check[543] = mio_pad_sleep_mode_38_gated_we;
+ reg_we_check[544] = mio_pad_sleep_mode_39_gated_we;
+ reg_we_check[545] = mio_pad_sleep_mode_40_gated_we;
+ reg_we_check[546] = mio_pad_sleep_mode_41_gated_we;
+ reg_we_check[547] = mio_pad_sleep_mode_42_gated_we;
+ reg_we_check[548] = mio_pad_sleep_mode_43_gated_we;
+ reg_we_check[549] = mio_pad_sleep_mode_44_gated_we;
+ reg_we_check[550] = mio_pad_sleep_mode_45_gated_we;
+ reg_we_check[551] = mio_pad_sleep_mode_46_gated_we;
+ reg_we_check[552] = mio_pad_sleep_mode_47_gated_we;
+ reg_we_check[553] = mio_pad_sleep_mode_48_gated_we;
+ reg_we_check[554] = mio_pad_sleep_mode_49_gated_we;
+ reg_we_check[555] = mio_pad_sleep_mode_50_gated_we;
+ reg_we_check[556] = mio_pad_sleep_mode_51_gated_we;
+ reg_we_check[557] = mio_pad_sleep_mode_52_gated_we;
+ reg_we_check[558] = dio_pad_sleep_status_we;
+ reg_we_check[559] = dio_pad_sleep_regwen_0_we;
+ reg_we_check[560] = dio_pad_sleep_regwen_1_we;
+ reg_we_check[561] = dio_pad_sleep_regwen_2_we;
+ reg_we_check[562] = dio_pad_sleep_regwen_3_we;
+ reg_we_check[563] = dio_pad_sleep_regwen_4_we;
+ reg_we_check[564] = dio_pad_sleep_regwen_5_we;
+ reg_we_check[565] = dio_pad_sleep_regwen_6_we;
+ reg_we_check[566] = dio_pad_sleep_regwen_7_we;
+ reg_we_check[567] = dio_pad_sleep_regwen_8_we;
+ reg_we_check[568] = dio_pad_sleep_regwen_9_we;
+ reg_we_check[569] = dio_pad_sleep_regwen_10_we;
+ reg_we_check[570] = dio_pad_sleep_regwen_11_we;
+ reg_we_check[571] = dio_pad_sleep_regwen_12_we;
+ reg_we_check[572] = dio_pad_sleep_regwen_13_we;
+ reg_we_check[573] = dio_pad_sleep_regwen_14_we;
+ reg_we_check[574] = dio_pad_sleep_regwen_15_we;
+ reg_we_check[575] = dio_pad_sleep_en_0_gated_we;
+ reg_we_check[576] = dio_pad_sleep_en_1_gated_we;
+ reg_we_check[577] = dio_pad_sleep_en_2_gated_we;
+ reg_we_check[578] = dio_pad_sleep_en_3_gated_we;
+ reg_we_check[579] = dio_pad_sleep_en_4_gated_we;
+ reg_we_check[580] = dio_pad_sleep_en_5_gated_we;
+ reg_we_check[581] = dio_pad_sleep_en_6_gated_we;
+ reg_we_check[582] = dio_pad_sleep_en_7_gated_we;
+ reg_we_check[583] = dio_pad_sleep_en_8_gated_we;
+ reg_we_check[584] = dio_pad_sleep_en_9_gated_we;
+ reg_we_check[585] = dio_pad_sleep_en_10_gated_we;
+ reg_we_check[586] = dio_pad_sleep_en_11_gated_we;
+ reg_we_check[587] = dio_pad_sleep_en_12_gated_we;
+ reg_we_check[588] = dio_pad_sleep_en_13_gated_we;
+ reg_we_check[589] = dio_pad_sleep_en_14_gated_we;
+ reg_we_check[590] = dio_pad_sleep_en_15_gated_we;
+ reg_we_check[591] = dio_pad_sleep_mode_0_gated_we;
+ reg_we_check[592] = dio_pad_sleep_mode_1_gated_we;
+ reg_we_check[593] = dio_pad_sleep_mode_2_gated_we;
+ reg_we_check[594] = dio_pad_sleep_mode_3_gated_we;
+ reg_we_check[595] = dio_pad_sleep_mode_4_gated_we;
+ reg_we_check[596] = dio_pad_sleep_mode_5_gated_we;
+ reg_we_check[597] = dio_pad_sleep_mode_6_gated_we;
+ reg_we_check[598] = dio_pad_sleep_mode_7_gated_we;
+ reg_we_check[599] = dio_pad_sleep_mode_8_gated_we;
+ reg_we_check[600] = dio_pad_sleep_mode_9_gated_we;
+ reg_we_check[601] = dio_pad_sleep_mode_10_gated_we;
+ reg_we_check[602] = dio_pad_sleep_mode_11_gated_we;
+ reg_we_check[603] = dio_pad_sleep_mode_12_gated_we;
+ reg_we_check[604] = dio_pad_sleep_mode_13_gated_we;
+ reg_we_check[605] = dio_pad_sleep_mode_14_gated_we;
+ reg_we_check[606] = dio_pad_sleep_mode_15_gated_we;
+ reg_we_check[607] = wkup_detector_regwen_0_we;
+ reg_we_check[608] = wkup_detector_regwen_1_we;
+ reg_we_check[609] = wkup_detector_regwen_2_we;
+ reg_we_check[610] = wkup_detector_regwen_3_we;
+ reg_we_check[611] = wkup_detector_regwen_4_we;
+ reg_we_check[612] = wkup_detector_regwen_5_we;
+ reg_we_check[613] = wkup_detector_regwen_6_we;
+ reg_we_check[614] = wkup_detector_regwen_7_we;
+ reg_we_check[615] = wkup_detector_en_0_we;
+ reg_we_check[616] = wkup_detector_en_1_we;
+ reg_we_check[617] = wkup_detector_en_2_we;
+ reg_we_check[618] = wkup_detector_en_3_we;
+ reg_we_check[619] = wkup_detector_en_4_we;
+ reg_we_check[620] = wkup_detector_en_5_we;
+ reg_we_check[621] = wkup_detector_en_6_we;
+ reg_we_check[622] = wkup_detector_en_7_we;
+ reg_we_check[623] = wkup_detector_0_we;
+ reg_we_check[624] = wkup_detector_1_we;
+ reg_we_check[625] = wkup_detector_2_we;
+ reg_we_check[626] = wkup_detector_3_we;
+ reg_we_check[627] = wkup_detector_4_we;
+ reg_we_check[628] = wkup_detector_5_we;
+ reg_we_check[629] = wkup_detector_6_we;
+ reg_we_check[630] = wkup_detector_7_we;
+ reg_we_check[631] = wkup_detector_cnt_th_0_we;
+ reg_we_check[632] = wkup_detector_cnt_th_1_we;
+ reg_we_check[633] = wkup_detector_cnt_th_2_we;
+ reg_we_check[634] = wkup_detector_cnt_th_3_we;
+ reg_we_check[635] = wkup_detector_cnt_th_4_we;
+ reg_we_check[636] = wkup_detector_cnt_th_5_we;
+ reg_we_check[637] = wkup_detector_cnt_th_6_we;
+ reg_we_check[638] = wkup_detector_cnt_th_7_we;
+ reg_we_check[639] = wkup_detector_padsel_0_gated_we;
+ reg_we_check[640] = wkup_detector_padsel_1_gated_we;
+ reg_we_check[641] = wkup_detector_padsel_2_gated_we;
+ reg_we_check[642] = wkup_detector_padsel_3_gated_we;
+ reg_we_check[643] = wkup_detector_padsel_4_gated_we;
+ reg_we_check[644] = wkup_detector_padsel_5_gated_we;
+ reg_we_check[645] = wkup_detector_padsel_6_gated_we;
+ reg_we_check[646] = wkup_detector_padsel_7_gated_we;
+ reg_we_check[647] = wkup_cause_we;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_33_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_34_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_35_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_36_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_37_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_38_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_39_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_40_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_41_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_42_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_43_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_44_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_45_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_46_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_47_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_48_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_49_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_50_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_51_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_52_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_53_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_54_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_55_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_56_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_57_qs;
+ end
+
+ addr_hit[59]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_58_qs;
+ end
+
+ addr_hit[60]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_59_qs;
+ end
+
+ addr_hit[61]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_60_qs;
+ end
+
+ addr_hit[62]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_61_qs;
+ end
+
+ addr_hit[63]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_62_qs;
+ end
+
+ addr_hit[64]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_63_qs;
+ end
+
+ addr_hit[65]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_64_qs;
+ end
+
+ addr_hit[66]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_65_qs;
+ end
+
+ addr_hit[67]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_66_qs;
+ end
+
+ addr_hit[68]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_67_qs;
+ end
+
+ addr_hit[69]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_68_qs;
+ end
+
+ addr_hit[70]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_69_qs;
+ end
+
+ addr_hit[71]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_70_qs;
+ end
+
+ addr_hit[72]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_71_qs;
+ end
+
+ addr_hit[73]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_72_qs;
+ end
+
+ addr_hit[74]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_73_qs;
+ end
+
+ addr_hit[75]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_74_qs;
+ end
+
+ addr_hit[76]: begin
+ reg_rdata_next[0] = mio_periph_insel_regwen_75_qs;
+ end
+
+ addr_hit[77]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_0_qs;
+ end
+
+ addr_hit[78]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_1_qs;
+ end
+
+ addr_hit[79]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_2_qs;
+ end
+
+ addr_hit[80]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_3_qs;
+ end
+
+ addr_hit[81]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_4_qs;
+ end
+
+ addr_hit[82]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_5_qs;
+ end
+
+ addr_hit[83]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_6_qs;
+ end
+
+ addr_hit[84]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_7_qs;
+ end
+
+ addr_hit[85]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_8_qs;
+ end
+
+ addr_hit[86]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_9_qs;
+ end
+
+ addr_hit[87]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_10_qs;
+ end
+
+ addr_hit[88]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_11_qs;
+ end
+
+ addr_hit[89]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_12_qs;
+ end
+
+ addr_hit[90]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_13_qs;
+ end
+
+ addr_hit[91]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_14_qs;
+ end
+
+ addr_hit[92]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_15_qs;
+ end
+
+ addr_hit[93]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_16_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_17_qs;
+ end
+
+ addr_hit[95]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_18_qs;
+ end
+
+ addr_hit[96]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_19_qs;
+ end
+
+ addr_hit[97]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_20_qs;
+ end
+
+ addr_hit[98]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_21_qs;
+ end
+
+ addr_hit[99]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_22_qs;
+ end
+
+ addr_hit[100]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_23_qs;
+ end
+
+ addr_hit[101]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_24_qs;
+ end
+
+ addr_hit[102]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_25_qs;
+ end
+
+ addr_hit[103]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_26_qs;
+ end
+
+ addr_hit[104]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_27_qs;
+ end
+
+ addr_hit[105]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_28_qs;
+ end
+
+ addr_hit[106]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_29_qs;
+ end
+
+ addr_hit[107]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_30_qs;
+ end
+
+ addr_hit[108]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_31_qs;
+ end
+
+ addr_hit[109]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_32_qs;
+ end
+
+ addr_hit[110]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_33_qs;
+ end
+
+ addr_hit[111]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_34_qs;
+ end
+
+ addr_hit[112]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_35_qs;
+ end
+
+ addr_hit[113]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_36_qs;
+ end
+
+ addr_hit[114]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_37_qs;
+ end
+
+ addr_hit[115]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_38_qs;
+ end
+
+ addr_hit[116]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_39_qs;
+ end
+
+ addr_hit[117]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_40_qs;
+ end
+
+ addr_hit[118]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_41_qs;
+ end
+
+ addr_hit[119]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_42_qs;
+ end
+
+ addr_hit[120]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_43_qs;
+ end
+
+ addr_hit[121]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_44_qs;
+ end
+
+ addr_hit[122]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_45_qs;
+ end
+
+ addr_hit[123]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_46_qs;
+ end
+
+ addr_hit[124]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_47_qs;
+ end
+
+ addr_hit[125]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_48_qs;
+ end
+
+ addr_hit[126]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_49_qs;
+ end
+
+ addr_hit[127]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_50_qs;
+ end
+
+ addr_hit[128]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_51_qs;
+ end
+
+ addr_hit[129]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_52_qs;
+ end
+
+ addr_hit[130]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_53_qs;
+ end
+
+ addr_hit[131]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_54_qs;
+ end
+
+ addr_hit[132]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_55_qs;
+ end
+
+ addr_hit[133]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_56_qs;
+ end
+
+ addr_hit[134]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_57_qs;
+ end
+
+ addr_hit[135]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_58_qs;
+ end
+
+ addr_hit[136]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_59_qs;
+ end
+
+ addr_hit[137]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_60_qs;
+ end
+
+ addr_hit[138]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_61_qs;
+ end
+
+ addr_hit[139]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_62_qs;
+ end
+
+ addr_hit[140]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_63_qs;
+ end
+
+ addr_hit[141]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_64_qs;
+ end
+
+ addr_hit[142]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_65_qs;
+ end
+
+ addr_hit[143]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_66_qs;
+ end
+
+ addr_hit[144]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_67_qs;
+ end
+
+ addr_hit[145]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_68_qs;
+ end
+
+ addr_hit[146]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_69_qs;
+ end
+
+ addr_hit[147]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_70_qs;
+ end
+
+ addr_hit[148]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_71_qs;
+ end
+
+ addr_hit[149]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_72_qs;
+ end
+
+ addr_hit[150]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_73_qs;
+ end
+
+ addr_hit[151]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_74_qs;
+ end
+
+ addr_hit[152]: begin
+ reg_rdata_next[5:0] = mio_periph_insel_75_qs;
+ end
+
+ addr_hit[153]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_0_qs;
+ end
+
+ addr_hit[154]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_1_qs;
+ end
+
+ addr_hit[155]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_2_qs;
+ end
+
+ addr_hit[156]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_3_qs;
+ end
+
+ addr_hit[157]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_4_qs;
+ end
+
+ addr_hit[158]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_5_qs;
+ end
+
+ addr_hit[159]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_6_qs;
+ end
+
+ addr_hit[160]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_7_qs;
+ end
+
+ addr_hit[161]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_8_qs;
+ end
+
+ addr_hit[162]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_9_qs;
+ end
+
+ addr_hit[163]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_10_qs;
+ end
+
+ addr_hit[164]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_11_qs;
+ end
+
+ addr_hit[165]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_12_qs;
+ end
+
+ addr_hit[166]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_13_qs;
+ end
+
+ addr_hit[167]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_14_qs;
+ end
+
+ addr_hit[168]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_15_qs;
+ end
+
+ addr_hit[169]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_16_qs;
+ end
+
+ addr_hit[170]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_17_qs;
+ end
+
+ addr_hit[171]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_18_qs;
+ end
+
+ addr_hit[172]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_19_qs;
+ end
+
+ addr_hit[173]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_20_qs;
+ end
+
+ addr_hit[174]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_21_qs;
+ end
+
+ addr_hit[175]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_22_qs;
+ end
+
+ addr_hit[176]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_23_qs;
+ end
+
+ addr_hit[177]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_24_qs;
+ end
+
+ addr_hit[178]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_25_qs;
+ end
+
+ addr_hit[179]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_26_qs;
+ end
+
+ addr_hit[180]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_27_qs;
+ end
+
+ addr_hit[181]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_28_qs;
+ end
+
+ addr_hit[182]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_29_qs;
+ end
+
+ addr_hit[183]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_30_qs;
+ end
+
+ addr_hit[184]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_31_qs;
+ end
+
+ addr_hit[185]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_32_qs;
+ end
+
+ addr_hit[186]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_33_qs;
+ end
+
+ addr_hit[187]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_34_qs;
+ end
+
+ addr_hit[188]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_35_qs;
+ end
+
+ addr_hit[189]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_36_qs;
+ end
+
+ addr_hit[190]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_37_qs;
+ end
+
+ addr_hit[191]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_38_qs;
+ end
+
+ addr_hit[192]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_39_qs;
+ end
+
+ addr_hit[193]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_40_qs;
+ end
+
+ addr_hit[194]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_41_qs;
+ end
+
+ addr_hit[195]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_42_qs;
+ end
+
+ addr_hit[196]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_43_qs;
+ end
+
+ addr_hit[197]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_44_qs;
+ end
+
+ addr_hit[198]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_45_qs;
+ end
+
+ addr_hit[199]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_46_qs;
+ end
+
+ addr_hit[200]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_47_qs;
+ end
+
+ addr_hit[201]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_48_qs;
+ end
+
+ addr_hit[202]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_49_qs;
+ end
+
+ addr_hit[203]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_50_qs;
+ end
+
+ addr_hit[204]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_51_qs;
+ end
+
+ addr_hit[205]: begin
+ reg_rdata_next[0] = mio_outsel_regwen_52_qs;
+ end
+
+ addr_hit[206]: begin
+ reg_rdata_next[6:0] = mio_outsel_0_qs;
+ end
+
+ addr_hit[207]: begin
+ reg_rdata_next[6:0] = mio_outsel_1_qs;
+ end
+
+ addr_hit[208]: begin
+ reg_rdata_next[6:0] = mio_outsel_2_qs;
+ end
+
+ addr_hit[209]: begin
+ reg_rdata_next[6:0] = mio_outsel_3_qs;
+ end
+
+ addr_hit[210]: begin
+ reg_rdata_next[6:0] = mio_outsel_4_qs;
+ end
+
+ addr_hit[211]: begin
+ reg_rdata_next[6:0] = mio_outsel_5_qs;
+ end
+
+ addr_hit[212]: begin
+ reg_rdata_next[6:0] = mio_outsel_6_qs;
+ end
+
+ addr_hit[213]: begin
+ reg_rdata_next[6:0] = mio_outsel_7_qs;
+ end
+
+ addr_hit[214]: begin
+ reg_rdata_next[6:0] = mio_outsel_8_qs;
+ end
+
+ addr_hit[215]: begin
+ reg_rdata_next[6:0] = mio_outsel_9_qs;
+ end
+
+ addr_hit[216]: begin
+ reg_rdata_next[6:0] = mio_outsel_10_qs;
+ end
+
+ addr_hit[217]: begin
+ reg_rdata_next[6:0] = mio_outsel_11_qs;
+ end
+
+ addr_hit[218]: begin
+ reg_rdata_next[6:0] = mio_outsel_12_qs;
+ end
+
+ addr_hit[219]: begin
+ reg_rdata_next[6:0] = mio_outsel_13_qs;
+ end
+
+ addr_hit[220]: begin
+ reg_rdata_next[6:0] = mio_outsel_14_qs;
+ end
+
+ addr_hit[221]: begin
+ reg_rdata_next[6:0] = mio_outsel_15_qs;
+ end
+
+ addr_hit[222]: begin
+ reg_rdata_next[6:0] = mio_outsel_16_qs;
+ end
+
+ addr_hit[223]: begin
+ reg_rdata_next[6:0] = mio_outsel_17_qs;
+ end
+
+ addr_hit[224]: begin
+ reg_rdata_next[6:0] = mio_outsel_18_qs;
+ end
+
+ addr_hit[225]: begin
+ reg_rdata_next[6:0] = mio_outsel_19_qs;
+ end
+
+ addr_hit[226]: begin
+ reg_rdata_next[6:0] = mio_outsel_20_qs;
+ end
+
+ addr_hit[227]: begin
+ reg_rdata_next[6:0] = mio_outsel_21_qs;
+ end
+
+ addr_hit[228]: begin
+ reg_rdata_next[6:0] = mio_outsel_22_qs;
+ end
+
+ addr_hit[229]: begin
+ reg_rdata_next[6:0] = mio_outsel_23_qs;
+ end
+
+ addr_hit[230]: begin
+ reg_rdata_next[6:0] = mio_outsel_24_qs;
+ end
+
+ addr_hit[231]: begin
+ reg_rdata_next[6:0] = mio_outsel_25_qs;
+ end
+
+ addr_hit[232]: begin
+ reg_rdata_next[6:0] = mio_outsel_26_qs;
+ end
+
+ addr_hit[233]: begin
+ reg_rdata_next[6:0] = mio_outsel_27_qs;
+ end
+
+ addr_hit[234]: begin
+ reg_rdata_next[6:0] = mio_outsel_28_qs;
+ end
+
+ addr_hit[235]: begin
+ reg_rdata_next[6:0] = mio_outsel_29_qs;
+ end
+
+ addr_hit[236]: begin
+ reg_rdata_next[6:0] = mio_outsel_30_qs;
+ end
+
+ addr_hit[237]: begin
+ reg_rdata_next[6:0] = mio_outsel_31_qs;
+ end
+
+ addr_hit[238]: begin
+ reg_rdata_next[6:0] = mio_outsel_32_qs;
+ end
+
+ addr_hit[239]: begin
+ reg_rdata_next[6:0] = mio_outsel_33_qs;
+ end
+
+ addr_hit[240]: begin
+ reg_rdata_next[6:0] = mio_outsel_34_qs;
+ end
+
+ addr_hit[241]: begin
+ reg_rdata_next[6:0] = mio_outsel_35_qs;
+ end
+
+ addr_hit[242]: begin
+ reg_rdata_next[6:0] = mio_outsel_36_qs;
+ end
+
+ addr_hit[243]: begin
+ reg_rdata_next[6:0] = mio_outsel_37_qs;
+ end
+
+ addr_hit[244]: begin
+ reg_rdata_next[6:0] = mio_outsel_38_qs;
+ end
+
+ addr_hit[245]: begin
+ reg_rdata_next[6:0] = mio_outsel_39_qs;
+ end
+
+ addr_hit[246]: begin
+ reg_rdata_next[6:0] = mio_outsel_40_qs;
+ end
+
+ addr_hit[247]: begin
+ reg_rdata_next[6:0] = mio_outsel_41_qs;
+ end
+
+ addr_hit[248]: begin
+ reg_rdata_next[6:0] = mio_outsel_42_qs;
+ end
+
+ addr_hit[249]: begin
+ reg_rdata_next[6:0] = mio_outsel_43_qs;
+ end
+
+ addr_hit[250]: begin
+ reg_rdata_next[6:0] = mio_outsel_44_qs;
+ end
+
+ addr_hit[251]: begin
+ reg_rdata_next[6:0] = mio_outsel_45_qs;
+ end
+
+ addr_hit[252]: begin
+ reg_rdata_next[6:0] = mio_outsel_46_qs;
+ end
+
+ addr_hit[253]: begin
+ reg_rdata_next[6:0] = mio_outsel_47_qs;
+ end
+
+ addr_hit[254]: begin
+ reg_rdata_next[6:0] = mio_outsel_48_qs;
+ end
+
+ addr_hit[255]: begin
+ reg_rdata_next[6:0] = mio_outsel_49_qs;
+ end
+
+ addr_hit[256]: begin
+ reg_rdata_next[6:0] = mio_outsel_50_qs;
+ end
+
+ addr_hit[257]: begin
+ reg_rdata_next[6:0] = mio_outsel_51_qs;
+ end
+
+ addr_hit[258]: begin
+ reg_rdata_next[6:0] = mio_outsel_52_qs;
+ end
+
+ addr_hit[259]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
+ end
+
+ addr_hit[260]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
+ end
+
+ addr_hit[261]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
+ end
+
+ addr_hit[262]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
+ end
+
+ addr_hit[263]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
+ end
+
+ addr_hit[264]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
+ end
+
+ addr_hit[265]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
+ end
+
+ addr_hit[266]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
+ end
+
+ addr_hit[267]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
+ end
+
+ addr_hit[268]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
+ end
+
+ addr_hit[269]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
+ end
+
+ addr_hit[270]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
+ end
+
+ addr_hit[271]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
+ end
+
+ addr_hit[272]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
+ end
+
+ addr_hit[273]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
+ end
+
+ addr_hit[274]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
+ end
+
+ addr_hit[275]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
+ end
+
+ addr_hit[276]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
+ end
+
+ addr_hit[277]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
+ end
+
+ addr_hit[278]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
+ end
+
+ addr_hit[279]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
+ end
+
+ addr_hit[280]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
+ end
+
+ addr_hit[281]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
+ end
+
+ addr_hit[282]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
+ end
+
+ addr_hit[283]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
+ end
+
+ addr_hit[284]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
+ end
+
+ addr_hit[285]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
+ end
+
+ addr_hit[286]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
+ end
+
+ addr_hit[287]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
+ end
+
+ addr_hit[288]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
+ end
+
+ addr_hit[289]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
+ end
+
+ addr_hit[290]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
+ end
+
+ addr_hit[291]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
+ end
+
+ addr_hit[292]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
+ end
+
+ addr_hit[293]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
+ end
+
+ addr_hit[294]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
+ end
+
+ addr_hit[295]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
+ end
+
+ addr_hit[296]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
+ end
+
+ addr_hit[297]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
+ end
+
+ addr_hit[298]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
+ end
+
+ addr_hit[299]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
+ end
+
+ addr_hit[300]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
+ end
+
+ addr_hit[301]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
+ end
+
+ addr_hit[302]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_43_qs;
+ end
+
+ addr_hit[303]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_44_qs;
+ end
+
+ addr_hit[304]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_45_qs;
+ end
+
+ addr_hit[305]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_46_qs;
+ end
+
+ addr_hit[306]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_47_qs;
+ end
+
+ addr_hit[307]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_48_qs;
+ end
+
+ addr_hit[308]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_49_qs;
+ end
+
+ addr_hit[309]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_50_qs;
+ end
+
+ addr_hit[310]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_51_qs;
+ end
+
+ addr_hit[311]: begin
+ reg_rdata_next[0] = mio_pad_attr_regwen_52_qs;
+ end
+
+ addr_hit[312]: begin
+ reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs;
+ reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs;
+ reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs;
+ reg_rdata_next[3] = mio_pad_attr_0_pull_select_0_qs;
+ reg_rdata_next[4] = mio_pad_attr_0_keeper_en_0_qs;
+ reg_rdata_next[5] = mio_pad_attr_0_schmitt_en_0_qs;
+ reg_rdata_next[6] = mio_pad_attr_0_od_en_0_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_0_slew_rate_0_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs;
+ end
+
+ addr_hit[313]: begin
+ reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs;
+ reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs;
+ reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs;
+ reg_rdata_next[3] = mio_pad_attr_1_pull_select_1_qs;
+ reg_rdata_next[4] = mio_pad_attr_1_keeper_en_1_qs;
+ reg_rdata_next[5] = mio_pad_attr_1_schmitt_en_1_qs;
+ reg_rdata_next[6] = mio_pad_attr_1_od_en_1_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_1_slew_rate_1_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs;
+ end
+
+ addr_hit[314]: begin
+ reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs;
+ reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs;
+ reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs;
+ reg_rdata_next[3] = mio_pad_attr_2_pull_select_2_qs;
+ reg_rdata_next[4] = mio_pad_attr_2_keeper_en_2_qs;
+ reg_rdata_next[5] = mio_pad_attr_2_schmitt_en_2_qs;
+ reg_rdata_next[6] = mio_pad_attr_2_od_en_2_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_2_slew_rate_2_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs;
+ end
+
+ addr_hit[315]: begin
+ reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs;
+ reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs;
+ reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs;
+ reg_rdata_next[3] = mio_pad_attr_3_pull_select_3_qs;
+ reg_rdata_next[4] = mio_pad_attr_3_keeper_en_3_qs;
+ reg_rdata_next[5] = mio_pad_attr_3_schmitt_en_3_qs;
+ reg_rdata_next[6] = mio_pad_attr_3_od_en_3_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_3_slew_rate_3_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs;
+ end
+
+ addr_hit[316]: begin
+ reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs;
+ reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs;
+ reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs;
+ reg_rdata_next[3] = mio_pad_attr_4_pull_select_4_qs;
+ reg_rdata_next[4] = mio_pad_attr_4_keeper_en_4_qs;
+ reg_rdata_next[5] = mio_pad_attr_4_schmitt_en_4_qs;
+ reg_rdata_next[6] = mio_pad_attr_4_od_en_4_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_4_slew_rate_4_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs;
+ end
+
+ addr_hit[317]: begin
+ reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs;
+ reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs;
+ reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs;
+ reg_rdata_next[3] = mio_pad_attr_5_pull_select_5_qs;
+ reg_rdata_next[4] = mio_pad_attr_5_keeper_en_5_qs;
+ reg_rdata_next[5] = mio_pad_attr_5_schmitt_en_5_qs;
+ reg_rdata_next[6] = mio_pad_attr_5_od_en_5_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_5_slew_rate_5_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs;
+ end
+
+ addr_hit[318]: begin
+ reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs;
+ reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs;
+ reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs;
+ reg_rdata_next[3] = mio_pad_attr_6_pull_select_6_qs;
+ reg_rdata_next[4] = mio_pad_attr_6_keeper_en_6_qs;
+ reg_rdata_next[5] = mio_pad_attr_6_schmitt_en_6_qs;
+ reg_rdata_next[6] = mio_pad_attr_6_od_en_6_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_6_slew_rate_6_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs;
+ end
+
+ addr_hit[319]: begin
+ reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs;
+ reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs;
+ reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs;
+ reg_rdata_next[3] = mio_pad_attr_7_pull_select_7_qs;
+ reg_rdata_next[4] = mio_pad_attr_7_keeper_en_7_qs;
+ reg_rdata_next[5] = mio_pad_attr_7_schmitt_en_7_qs;
+ reg_rdata_next[6] = mio_pad_attr_7_od_en_7_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_7_slew_rate_7_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs;
+ end
+
+ addr_hit[320]: begin
+ reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs;
+ reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs;
+ reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs;
+ reg_rdata_next[3] = mio_pad_attr_8_pull_select_8_qs;
+ reg_rdata_next[4] = mio_pad_attr_8_keeper_en_8_qs;
+ reg_rdata_next[5] = mio_pad_attr_8_schmitt_en_8_qs;
+ reg_rdata_next[6] = mio_pad_attr_8_od_en_8_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_8_slew_rate_8_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs;
+ end
+
+ addr_hit[321]: begin
+ reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs;
+ reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs;
+ reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs;
+ reg_rdata_next[3] = mio_pad_attr_9_pull_select_9_qs;
+ reg_rdata_next[4] = mio_pad_attr_9_keeper_en_9_qs;
+ reg_rdata_next[5] = mio_pad_attr_9_schmitt_en_9_qs;
+ reg_rdata_next[6] = mio_pad_attr_9_od_en_9_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_9_slew_rate_9_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs;
+ end
+
+ addr_hit[322]: begin
+ reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs;
+ reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs;
+ reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs;
+ reg_rdata_next[3] = mio_pad_attr_10_pull_select_10_qs;
+ reg_rdata_next[4] = mio_pad_attr_10_keeper_en_10_qs;
+ reg_rdata_next[5] = mio_pad_attr_10_schmitt_en_10_qs;
+ reg_rdata_next[6] = mio_pad_attr_10_od_en_10_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_10_slew_rate_10_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs;
+ end
+
+ addr_hit[323]: begin
+ reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs;
+ reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs;
+ reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs;
+ reg_rdata_next[3] = mio_pad_attr_11_pull_select_11_qs;
+ reg_rdata_next[4] = mio_pad_attr_11_keeper_en_11_qs;
+ reg_rdata_next[5] = mio_pad_attr_11_schmitt_en_11_qs;
+ reg_rdata_next[6] = mio_pad_attr_11_od_en_11_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_11_slew_rate_11_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs;
+ end
+
+ addr_hit[324]: begin
+ reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs;
+ reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs;
+ reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs;
+ reg_rdata_next[3] = mio_pad_attr_12_pull_select_12_qs;
+ reg_rdata_next[4] = mio_pad_attr_12_keeper_en_12_qs;
+ reg_rdata_next[5] = mio_pad_attr_12_schmitt_en_12_qs;
+ reg_rdata_next[6] = mio_pad_attr_12_od_en_12_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_12_slew_rate_12_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs;
+ end
+
+ addr_hit[325]: begin
+ reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs;
+ reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs;
+ reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs;
+ reg_rdata_next[3] = mio_pad_attr_13_pull_select_13_qs;
+ reg_rdata_next[4] = mio_pad_attr_13_keeper_en_13_qs;
+ reg_rdata_next[5] = mio_pad_attr_13_schmitt_en_13_qs;
+ reg_rdata_next[6] = mio_pad_attr_13_od_en_13_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_13_slew_rate_13_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs;
+ end
+
+ addr_hit[326]: begin
+ reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs;
+ reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs;
+ reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs;
+ reg_rdata_next[3] = mio_pad_attr_14_pull_select_14_qs;
+ reg_rdata_next[4] = mio_pad_attr_14_keeper_en_14_qs;
+ reg_rdata_next[5] = mio_pad_attr_14_schmitt_en_14_qs;
+ reg_rdata_next[6] = mio_pad_attr_14_od_en_14_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_14_slew_rate_14_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs;
+ end
+
+ addr_hit[327]: begin
+ reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs;
+ reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs;
+ reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs;
+ reg_rdata_next[3] = mio_pad_attr_15_pull_select_15_qs;
+ reg_rdata_next[4] = mio_pad_attr_15_keeper_en_15_qs;
+ reg_rdata_next[5] = mio_pad_attr_15_schmitt_en_15_qs;
+ reg_rdata_next[6] = mio_pad_attr_15_od_en_15_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_15_slew_rate_15_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs;
+ end
+
+ addr_hit[328]: begin
+ reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs;
+ reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs;
+ reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs;
+ reg_rdata_next[3] = mio_pad_attr_16_pull_select_16_qs;
+ reg_rdata_next[4] = mio_pad_attr_16_keeper_en_16_qs;
+ reg_rdata_next[5] = mio_pad_attr_16_schmitt_en_16_qs;
+ reg_rdata_next[6] = mio_pad_attr_16_od_en_16_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_16_slew_rate_16_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs;
+ end
+
+ addr_hit[329]: begin
+ reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs;
+ reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs;
+ reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs;
+ reg_rdata_next[3] = mio_pad_attr_17_pull_select_17_qs;
+ reg_rdata_next[4] = mio_pad_attr_17_keeper_en_17_qs;
+ reg_rdata_next[5] = mio_pad_attr_17_schmitt_en_17_qs;
+ reg_rdata_next[6] = mio_pad_attr_17_od_en_17_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_17_slew_rate_17_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs;
+ end
+
+ addr_hit[330]: begin
+ reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs;
+ reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs;
+ reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs;
+ reg_rdata_next[3] = mio_pad_attr_18_pull_select_18_qs;
+ reg_rdata_next[4] = mio_pad_attr_18_keeper_en_18_qs;
+ reg_rdata_next[5] = mio_pad_attr_18_schmitt_en_18_qs;
+ reg_rdata_next[6] = mio_pad_attr_18_od_en_18_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_18_slew_rate_18_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs;
+ end
+
+ addr_hit[331]: begin
+ reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs;
+ reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs;
+ reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs;
+ reg_rdata_next[3] = mio_pad_attr_19_pull_select_19_qs;
+ reg_rdata_next[4] = mio_pad_attr_19_keeper_en_19_qs;
+ reg_rdata_next[5] = mio_pad_attr_19_schmitt_en_19_qs;
+ reg_rdata_next[6] = mio_pad_attr_19_od_en_19_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_19_slew_rate_19_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs;
+ end
+
+ addr_hit[332]: begin
+ reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs;
+ reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs;
+ reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs;
+ reg_rdata_next[3] = mio_pad_attr_20_pull_select_20_qs;
+ reg_rdata_next[4] = mio_pad_attr_20_keeper_en_20_qs;
+ reg_rdata_next[5] = mio_pad_attr_20_schmitt_en_20_qs;
+ reg_rdata_next[6] = mio_pad_attr_20_od_en_20_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_20_slew_rate_20_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs;
+ end
+
+ addr_hit[333]: begin
+ reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs;
+ reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs;
+ reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs;
+ reg_rdata_next[3] = mio_pad_attr_21_pull_select_21_qs;
+ reg_rdata_next[4] = mio_pad_attr_21_keeper_en_21_qs;
+ reg_rdata_next[5] = mio_pad_attr_21_schmitt_en_21_qs;
+ reg_rdata_next[6] = mio_pad_attr_21_od_en_21_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_21_slew_rate_21_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs;
+ end
+
+ addr_hit[334]: begin
+ reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs;
+ reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs;
+ reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs;
+ reg_rdata_next[3] = mio_pad_attr_22_pull_select_22_qs;
+ reg_rdata_next[4] = mio_pad_attr_22_keeper_en_22_qs;
+ reg_rdata_next[5] = mio_pad_attr_22_schmitt_en_22_qs;
+ reg_rdata_next[6] = mio_pad_attr_22_od_en_22_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_22_slew_rate_22_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs;
+ end
+
+ addr_hit[335]: begin
+ reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs;
+ reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs;
+ reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs;
+ reg_rdata_next[3] = mio_pad_attr_23_pull_select_23_qs;
+ reg_rdata_next[4] = mio_pad_attr_23_keeper_en_23_qs;
+ reg_rdata_next[5] = mio_pad_attr_23_schmitt_en_23_qs;
+ reg_rdata_next[6] = mio_pad_attr_23_od_en_23_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_23_slew_rate_23_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs;
+ end
+
+ addr_hit[336]: begin
+ reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs;
+ reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs;
+ reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs;
+ reg_rdata_next[3] = mio_pad_attr_24_pull_select_24_qs;
+ reg_rdata_next[4] = mio_pad_attr_24_keeper_en_24_qs;
+ reg_rdata_next[5] = mio_pad_attr_24_schmitt_en_24_qs;
+ reg_rdata_next[6] = mio_pad_attr_24_od_en_24_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_24_slew_rate_24_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs;
+ end
+
+ addr_hit[337]: begin
+ reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs;
+ reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs;
+ reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs;
+ reg_rdata_next[3] = mio_pad_attr_25_pull_select_25_qs;
+ reg_rdata_next[4] = mio_pad_attr_25_keeper_en_25_qs;
+ reg_rdata_next[5] = mio_pad_attr_25_schmitt_en_25_qs;
+ reg_rdata_next[6] = mio_pad_attr_25_od_en_25_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_25_slew_rate_25_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs;
+ end
+
+ addr_hit[338]: begin
+ reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs;
+ reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs;
+ reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs;
+ reg_rdata_next[3] = mio_pad_attr_26_pull_select_26_qs;
+ reg_rdata_next[4] = mio_pad_attr_26_keeper_en_26_qs;
+ reg_rdata_next[5] = mio_pad_attr_26_schmitt_en_26_qs;
+ reg_rdata_next[6] = mio_pad_attr_26_od_en_26_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_26_slew_rate_26_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs;
+ end
+
+ addr_hit[339]: begin
+ reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs;
+ reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs;
+ reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs;
+ reg_rdata_next[3] = mio_pad_attr_27_pull_select_27_qs;
+ reg_rdata_next[4] = mio_pad_attr_27_keeper_en_27_qs;
+ reg_rdata_next[5] = mio_pad_attr_27_schmitt_en_27_qs;
+ reg_rdata_next[6] = mio_pad_attr_27_od_en_27_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_27_slew_rate_27_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs;
+ end
+
+ addr_hit[340]: begin
+ reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs;
+ reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs;
+ reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs;
+ reg_rdata_next[3] = mio_pad_attr_28_pull_select_28_qs;
+ reg_rdata_next[4] = mio_pad_attr_28_keeper_en_28_qs;
+ reg_rdata_next[5] = mio_pad_attr_28_schmitt_en_28_qs;
+ reg_rdata_next[6] = mio_pad_attr_28_od_en_28_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_28_slew_rate_28_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs;
+ end
+
+ addr_hit[341]: begin
+ reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs;
+ reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs;
+ reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs;
+ reg_rdata_next[3] = mio_pad_attr_29_pull_select_29_qs;
+ reg_rdata_next[4] = mio_pad_attr_29_keeper_en_29_qs;
+ reg_rdata_next[5] = mio_pad_attr_29_schmitt_en_29_qs;
+ reg_rdata_next[6] = mio_pad_attr_29_od_en_29_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_29_slew_rate_29_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs;
+ end
+
+ addr_hit[342]: begin
+ reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs;
+ reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs;
+ reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs;
+ reg_rdata_next[3] = mio_pad_attr_30_pull_select_30_qs;
+ reg_rdata_next[4] = mio_pad_attr_30_keeper_en_30_qs;
+ reg_rdata_next[5] = mio_pad_attr_30_schmitt_en_30_qs;
+ reg_rdata_next[6] = mio_pad_attr_30_od_en_30_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_30_slew_rate_30_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs;
+ end
+
+ addr_hit[343]: begin
+ reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs;
+ reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs;
+ reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs;
+ reg_rdata_next[3] = mio_pad_attr_31_pull_select_31_qs;
+ reg_rdata_next[4] = mio_pad_attr_31_keeper_en_31_qs;
+ reg_rdata_next[5] = mio_pad_attr_31_schmitt_en_31_qs;
+ reg_rdata_next[6] = mio_pad_attr_31_od_en_31_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_31_slew_rate_31_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs;
+ end
+
+ addr_hit[344]: begin
+ reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs;
+ reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs;
+ reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs;
+ reg_rdata_next[3] = mio_pad_attr_32_pull_select_32_qs;
+ reg_rdata_next[4] = mio_pad_attr_32_keeper_en_32_qs;
+ reg_rdata_next[5] = mio_pad_attr_32_schmitt_en_32_qs;
+ reg_rdata_next[6] = mio_pad_attr_32_od_en_32_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_32_slew_rate_32_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs;
+ end
+
+ addr_hit[345]: begin
+ reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs;
+ reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs;
+ reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs;
+ reg_rdata_next[3] = mio_pad_attr_33_pull_select_33_qs;
+ reg_rdata_next[4] = mio_pad_attr_33_keeper_en_33_qs;
+ reg_rdata_next[5] = mio_pad_attr_33_schmitt_en_33_qs;
+ reg_rdata_next[6] = mio_pad_attr_33_od_en_33_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_33_slew_rate_33_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs;
+ end
+
+ addr_hit[346]: begin
+ reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs;
+ reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs;
+ reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs;
+ reg_rdata_next[3] = mio_pad_attr_34_pull_select_34_qs;
+ reg_rdata_next[4] = mio_pad_attr_34_keeper_en_34_qs;
+ reg_rdata_next[5] = mio_pad_attr_34_schmitt_en_34_qs;
+ reg_rdata_next[6] = mio_pad_attr_34_od_en_34_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_34_slew_rate_34_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs;
+ end
+
+ addr_hit[347]: begin
+ reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs;
+ reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs;
+ reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs;
+ reg_rdata_next[3] = mio_pad_attr_35_pull_select_35_qs;
+ reg_rdata_next[4] = mio_pad_attr_35_keeper_en_35_qs;
+ reg_rdata_next[5] = mio_pad_attr_35_schmitt_en_35_qs;
+ reg_rdata_next[6] = mio_pad_attr_35_od_en_35_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_35_slew_rate_35_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs;
+ end
+
+ addr_hit[348]: begin
+ reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs;
+ reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs;
+ reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs;
+ reg_rdata_next[3] = mio_pad_attr_36_pull_select_36_qs;
+ reg_rdata_next[4] = mio_pad_attr_36_keeper_en_36_qs;
+ reg_rdata_next[5] = mio_pad_attr_36_schmitt_en_36_qs;
+ reg_rdata_next[6] = mio_pad_attr_36_od_en_36_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_36_slew_rate_36_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs;
+ end
+
+ addr_hit[349]: begin
+ reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs;
+ reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs;
+ reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs;
+ reg_rdata_next[3] = mio_pad_attr_37_pull_select_37_qs;
+ reg_rdata_next[4] = mio_pad_attr_37_keeper_en_37_qs;
+ reg_rdata_next[5] = mio_pad_attr_37_schmitt_en_37_qs;
+ reg_rdata_next[6] = mio_pad_attr_37_od_en_37_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_37_slew_rate_37_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs;
+ end
+
+ addr_hit[350]: begin
+ reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs;
+ reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs;
+ reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs;
+ reg_rdata_next[3] = mio_pad_attr_38_pull_select_38_qs;
+ reg_rdata_next[4] = mio_pad_attr_38_keeper_en_38_qs;
+ reg_rdata_next[5] = mio_pad_attr_38_schmitt_en_38_qs;
+ reg_rdata_next[6] = mio_pad_attr_38_od_en_38_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_38_slew_rate_38_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs;
+ end
+
+ addr_hit[351]: begin
+ reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs;
+ reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs;
+ reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs;
+ reg_rdata_next[3] = mio_pad_attr_39_pull_select_39_qs;
+ reg_rdata_next[4] = mio_pad_attr_39_keeper_en_39_qs;
+ reg_rdata_next[5] = mio_pad_attr_39_schmitt_en_39_qs;
+ reg_rdata_next[6] = mio_pad_attr_39_od_en_39_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_39_slew_rate_39_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs;
+ end
+
+ addr_hit[352]: begin
+ reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs;
+ reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs;
+ reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs;
+ reg_rdata_next[3] = mio_pad_attr_40_pull_select_40_qs;
+ reg_rdata_next[4] = mio_pad_attr_40_keeper_en_40_qs;
+ reg_rdata_next[5] = mio_pad_attr_40_schmitt_en_40_qs;
+ reg_rdata_next[6] = mio_pad_attr_40_od_en_40_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_40_slew_rate_40_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs;
+ end
+
+ addr_hit[353]: begin
+ reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs;
+ reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs;
+ reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs;
+ reg_rdata_next[3] = mio_pad_attr_41_pull_select_41_qs;
+ reg_rdata_next[4] = mio_pad_attr_41_keeper_en_41_qs;
+ reg_rdata_next[5] = mio_pad_attr_41_schmitt_en_41_qs;
+ reg_rdata_next[6] = mio_pad_attr_41_od_en_41_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_41_slew_rate_41_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs;
+ end
+
+ addr_hit[354]: begin
+ reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs;
+ reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs;
+ reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs;
+ reg_rdata_next[3] = mio_pad_attr_42_pull_select_42_qs;
+ reg_rdata_next[4] = mio_pad_attr_42_keeper_en_42_qs;
+ reg_rdata_next[5] = mio_pad_attr_42_schmitt_en_42_qs;
+ reg_rdata_next[6] = mio_pad_attr_42_od_en_42_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_42_slew_rate_42_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs;
+ end
+
+ addr_hit[355]: begin
+ reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs;
+ reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs;
+ reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs;
+ reg_rdata_next[3] = mio_pad_attr_43_pull_select_43_qs;
+ reg_rdata_next[4] = mio_pad_attr_43_keeper_en_43_qs;
+ reg_rdata_next[5] = mio_pad_attr_43_schmitt_en_43_qs;
+ reg_rdata_next[6] = mio_pad_attr_43_od_en_43_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_43_slew_rate_43_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs;
+ end
+
+ addr_hit[356]: begin
+ reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs;
+ reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs;
+ reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs;
+ reg_rdata_next[3] = mio_pad_attr_44_pull_select_44_qs;
+ reg_rdata_next[4] = mio_pad_attr_44_keeper_en_44_qs;
+ reg_rdata_next[5] = mio_pad_attr_44_schmitt_en_44_qs;
+ reg_rdata_next[6] = mio_pad_attr_44_od_en_44_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_44_slew_rate_44_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs;
+ end
+
+ addr_hit[357]: begin
+ reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs;
+ reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs;
+ reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs;
+ reg_rdata_next[3] = mio_pad_attr_45_pull_select_45_qs;
+ reg_rdata_next[4] = mio_pad_attr_45_keeper_en_45_qs;
+ reg_rdata_next[5] = mio_pad_attr_45_schmitt_en_45_qs;
+ reg_rdata_next[6] = mio_pad_attr_45_od_en_45_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_45_slew_rate_45_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs;
+ end
+
+ addr_hit[358]: begin
+ reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs;
+ reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs;
+ reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs;
+ reg_rdata_next[3] = mio_pad_attr_46_pull_select_46_qs;
+ reg_rdata_next[4] = mio_pad_attr_46_keeper_en_46_qs;
+ reg_rdata_next[5] = mio_pad_attr_46_schmitt_en_46_qs;
+ reg_rdata_next[6] = mio_pad_attr_46_od_en_46_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_46_slew_rate_46_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs;
+ end
+
+ addr_hit[359]: begin
+ reg_rdata_next[0] = mio_pad_attr_47_invert_47_qs;
+ reg_rdata_next[1] = mio_pad_attr_47_virtual_od_en_47_qs;
+ reg_rdata_next[2] = mio_pad_attr_47_pull_en_47_qs;
+ reg_rdata_next[3] = mio_pad_attr_47_pull_select_47_qs;
+ reg_rdata_next[4] = mio_pad_attr_47_keeper_en_47_qs;
+ reg_rdata_next[5] = mio_pad_attr_47_schmitt_en_47_qs;
+ reg_rdata_next[6] = mio_pad_attr_47_od_en_47_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_47_slew_rate_47_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_47_drive_strength_47_qs;
+ end
+
+ addr_hit[360]: begin
+ reg_rdata_next[0] = mio_pad_attr_48_invert_48_qs;
+ reg_rdata_next[1] = mio_pad_attr_48_virtual_od_en_48_qs;
+ reg_rdata_next[2] = mio_pad_attr_48_pull_en_48_qs;
+ reg_rdata_next[3] = mio_pad_attr_48_pull_select_48_qs;
+ reg_rdata_next[4] = mio_pad_attr_48_keeper_en_48_qs;
+ reg_rdata_next[5] = mio_pad_attr_48_schmitt_en_48_qs;
+ reg_rdata_next[6] = mio_pad_attr_48_od_en_48_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_48_slew_rate_48_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_48_drive_strength_48_qs;
+ end
+
+ addr_hit[361]: begin
+ reg_rdata_next[0] = mio_pad_attr_49_invert_49_qs;
+ reg_rdata_next[1] = mio_pad_attr_49_virtual_od_en_49_qs;
+ reg_rdata_next[2] = mio_pad_attr_49_pull_en_49_qs;
+ reg_rdata_next[3] = mio_pad_attr_49_pull_select_49_qs;
+ reg_rdata_next[4] = mio_pad_attr_49_keeper_en_49_qs;
+ reg_rdata_next[5] = mio_pad_attr_49_schmitt_en_49_qs;
+ reg_rdata_next[6] = mio_pad_attr_49_od_en_49_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_49_slew_rate_49_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_49_drive_strength_49_qs;
+ end
+
+ addr_hit[362]: begin
+ reg_rdata_next[0] = mio_pad_attr_50_invert_50_qs;
+ reg_rdata_next[1] = mio_pad_attr_50_virtual_od_en_50_qs;
+ reg_rdata_next[2] = mio_pad_attr_50_pull_en_50_qs;
+ reg_rdata_next[3] = mio_pad_attr_50_pull_select_50_qs;
+ reg_rdata_next[4] = mio_pad_attr_50_keeper_en_50_qs;
+ reg_rdata_next[5] = mio_pad_attr_50_schmitt_en_50_qs;
+ reg_rdata_next[6] = mio_pad_attr_50_od_en_50_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_50_slew_rate_50_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_50_drive_strength_50_qs;
+ end
+
+ addr_hit[363]: begin
+ reg_rdata_next[0] = mio_pad_attr_51_invert_51_qs;
+ reg_rdata_next[1] = mio_pad_attr_51_virtual_od_en_51_qs;
+ reg_rdata_next[2] = mio_pad_attr_51_pull_en_51_qs;
+ reg_rdata_next[3] = mio_pad_attr_51_pull_select_51_qs;
+ reg_rdata_next[4] = mio_pad_attr_51_keeper_en_51_qs;
+ reg_rdata_next[5] = mio_pad_attr_51_schmitt_en_51_qs;
+ reg_rdata_next[6] = mio_pad_attr_51_od_en_51_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_51_slew_rate_51_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_51_drive_strength_51_qs;
+ end
+
+ addr_hit[364]: begin
+ reg_rdata_next[0] = mio_pad_attr_52_invert_52_qs;
+ reg_rdata_next[1] = mio_pad_attr_52_virtual_od_en_52_qs;
+ reg_rdata_next[2] = mio_pad_attr_52_pull_en_52_qs;
+ reg_rdata_next[3] = mio_pad_attr_52_pull_select_52_qs;
+ reg_rdata_next[4] = mio_pad_attr_52_keeper_en_52_qs;
+ reg_rdata_next[5] = mio_pad_attr_52_schmitt_en_52_qs;
+ reg_rdata_next[6] = mio_pad_attr_52_od_en_52_qs;
+ reg_rdata_next[17:16] = mio_pad_attr_52_slew_rate_52_qs;
+ reg_rdata_next[23:20] = mio_pad_attr_52_drive_strength_52_qs;
+ end
+
+ addr_hit[365]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
+ end
+
+ addr_hit[366]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
+ end
+
+ addr_hit[367]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
+ end
+
+ addr_hit[368]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
+ end
+
+ addr_hit[369]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
+ end
+
+ addr_hit[370]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
+ end
+
+ addr_hit[371]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
+ end
+
+ addr_hit[372]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
+ end
+
+ addr_hit[373]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
+ end
+
+ addr_hit[374]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
+ end
+
+ addr_hit[375]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
+ end
+
+ addr_hit[376]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
+ end
+
+ addr_hit[377]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
+ end
+
+ addr_hit[378]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
+ end
+
+ addr_hit[379]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
+ end
+
+ addr_hit[380]: begin
+ reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
+ end
+
+ addr_hit[381]: begin
+ reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs;
+ reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs;
+ reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs;
+ reg_rdata_next[3] = dio_pad_attr_0_pull_select_0_qs;
+ reg_rdata_next[4] = dio_pad_attr_0_keeper_en_0_qs;
+ reg_rdata_next[5] = dio_pad_attr_0_schmitt_en_0_qs;
+ reg_rdata_next[6] = dio_pad_attr_0_od_en_0_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_0_slew_rate_0_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs;
+ end
+
+ addr_hit[382]: begin
+ reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs;
+ reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs;
+ reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs;
+ reg_rdata_next[3] = dio_pad_attr_1_pull_select_1_qs;
+ reg_rdata_next[4] = dio_pad_attr_1_keeper_en_1_qs;
+ reg_rdata_next[5] = dio_pad_attr_1_schmitt_en_1_qs;
+ reg_rdata_next[6] = dio_pad_attr_1_od_en_1_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_1_slew_rate_1_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs;
+ end
+
+ addr_hit[383]: begin
+ reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs;
+ reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs;
+ reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs;
+ reg_rdata_next[3] = dio_pad_attr_2_pull_select_2_qs;
+ reg_rdata_next[4] = dio_pad_attr_2_keeper_en_2_qs;
+ reg_rdata_next[5] = dio_pad_attr_2_schmitt_en_2_qs;
+ reg_rdata_next[6] = dio_pad_attr_2_od_en_2_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_2_slew_rate_2_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs;
+ end
+
+ addr_hit[384]: begin
+ reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs;
+ reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs;
+ reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs;
+ reg_rdata_next[3] = dio_pad_attr_3_pull_select_3_qs;
+ reg_rdata_next[4] = dio_pad_attr_3_keeper_en_3_qs;
+ reg_rdata_next[5] = dio_pad_attr_3_schmitt_en_3_qs;
+ reg_rdata_next[6] = dio_pad_attr_3_od_en_3_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_3_slew_rate_3_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs;
+ end
+
+ addr_hit[385]: begin
+ reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs;
+ reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs;
+ reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs;
+ reg_rdata_next[3] = dio_pad_attr_4_pull_select_4_qs;
+ reg_rdata_next[4] = dio_pad_attr_4_keeper_en_4_qs;
+ reg_rdata_next[5] = dio_pad_attr_4_schmitt_en_4_qs;
+ reg_rdata_next[6] = dio_pad_attr_4_od_en_4_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_4_slew_rate_4_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs;
+ end
+
+ addr_hit[386]: begin
+ reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs;
+ reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs;
+ reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs;
+ reg_rdata_next[3] = dio_pad_attr_5_pull_select_5_qs;
+ reg_rdata_next[4] = dio_pad_attr_5_keeper_en_5_qs;
+ reg_rdata_next[5] = dio_pad_attr_5_schmitt_en_5_qs;
+ reg_rdata_next[6] = dio_pad_attr_5_od_en_5_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_5_slew_rate_5_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs;
+ end
+
+ addr_hit[387]: begin
+ reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs;
+ reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs;
+ reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs;
+ reg_rdata_next[3] = dio_pad_attr_6_pull_select_6_qs;
+ reg_rdata_next[4] = dio_pad_attr_6_keeper_en_6_qs;
+ reg_rdata_next[5] = dio_pad_attr_6_schmitt_en_6_qs;
+ reg_rdata_next[6] = dio_pad_attr_6_od_en_6_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_6_slew_rate_6_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs;
+ end
+
+ addr_hit[388]: begin
+ reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs;
+ reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs;
+ reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs;
+ reg_rdata_next[3] = dio_pad_attr_7_pull_select_7_qs;
+ reg_rdata_next[4] = dio_pad_attr_7_keeper_en_7_qs;
+ reg_rdata_next[5] = dio_pad_attr_7_schmitt_en_7_qs;
+ reg_rdata_next[6] = dio_pad_attr_7_od_en_7_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_7_slew_rate_7_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs;
+ end
+
+ addr_hit[389]: begin
+ reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs;
+ reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs;
+ reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs;
+ reg_rdata_next[3] = dio_pad_attr_8_pull_select_8_qs;
+ reg_rdata_next[4] = dio_pad_attr_8_keeper_en_8_qs;
+ reg_rdata_next[5] = dio_pad_attr_8_schmitt_en_8_qs;
+ reg_rdata_next[6] = dio_pad_attr_8_od_en_8_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_8_slew_rate_8_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs;
+ end
+
+ addr_hit[390]: begin
+ reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs;
+ reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs;
+ reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs;
+ reg_rdata_next[3] = dio_pad_attr_9_pull_select_9_qs;
+ reg_rdata_next[4] = dio_pad_attr_9_keeper_en_9_qs;
+ reg_rdata_next[5] = dio_pad_attr_9_schmitt_en_9_qs;
+ reg_rdata_next[6] = dio_pad_attr_9_od_en_9_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_9_slew_rate_9_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs;
+ end
+
+ addr_hit[391]: begin
+ reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs;
+ reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs;
+ reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs;
+ reg_rdata_next[3] = dio_pad_attr_10_pull_select_10_qs;
+ reg_rdata_next[4] = dio_pad_attr_10_keeper_en_10_qs;
+ reg_rdata_next[5] = dio_pad_attr_10_schmitt_en_10_qs;
+ reg_rdata_next[6] = dio_pad_attr_10_od_en_10_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_10_slew_rate_10_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs;
+ end
+
+ addr_hit[392]: begin
+ reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs;
+ reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs;
+ reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs;
+ reg_rdata_next[3] = dio_pad_attr_11_pull_select_11_qs;
+ reg_rdata_next[4] = dio_pad_attr_11_keeper_en_11_qs;
+ reg_rdata_next[5] = dio_pad_attr_11_schmitt_en_11_qs;
+ reg_rdata_next[6] = dio_pad_attr_11_od_en_11_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_11_slew_rate_11_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs;
+ end
+
+ addr_hit[393]: begin
+ reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs;
+ reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs;
+ reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs;
+ reg_rdata_next[3] = dio_pad_attr_12_pull_select_12_qs;
+ reg_rdata_next[4] = dio_pad_attr_12_keeper_en_12_qs;
+ reg_rdata_next[5] = dio_pad_attr_12_schmitt_en_12_qs;
+ reg_rdata_next[6] = dio_pad_attr_12_od_en_12_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_12_slew_rate_12_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs;
+ end
+
+ addr_hit[394]: begin
+ reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs;
+ reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs;
+ reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs;
+ reg_rdata_next[3] = dio_pad_attr_13_pull_select_13_qs;
+ reg_rdata_next[4] = dio_pad_attr_13_keeper_en_13_qs;
+ reg_rdata_next[5] = dio_pad_attr_13_schmitt_en_13_qs;
+ reg_rdata_next[6] = dio_pad_attr_13_od_en_13_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_13_slew_rate_13_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs;
+ end
+
+ addr_hit[395]: begin
+ reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs;
+ reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs;
+ reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs;
+ reg_rdata_next[3] = dio_pad_attr_14_pull_select_14_qs;
+ reg_rdata_next[4] = dio_pad_attr_14_keeper_en_14_qs;
+ reg_rdata_next[5] = dio_pad_attr_14_schmitt_en_14_qs;
+ reg_rdata_next[6] = dio_pad_attr_14_od_en_14_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_14_slew_rate_14_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs;
+ end
+
+ addr_hit[396]: begin
+ reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs;
+ reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs;
+ reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs;
+ reg_rdata_next[3] = dio_pad_attr_15_pull_select_15_qs;
+ reg_rdata_next[4] = dio_pad_attr_15_keeper_en_15_qs;
+ reg_rdata_next[5] = dio_pad_attr_15_schmitt_en_15_qs;
+ reg_rdata_next[6] = dio_pad_attr_15_od_en_15_qs;
+ reg_rdata_next[17:16] = dio_pad_attr_15_slew_rate_15_qs;
+ reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs;
+ end
+
+ addr_hit[397]: begin
+ reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs;
+ reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs;
+ reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs;
+ reg_rdata_next[3] = mio_pad_sleep_status_0_en_3_qs;
+ reg_rdata_next[4] = mio_pad_sleep_status_0_en_4_qs;
+ reg_rdata_next[5] = mio_pad_sleep_status_0_en_5_qs;
+ reg_rdata_next[6] = mio_pad_sleep_status_0_en_6_qs;
+ reg_rdata_next[7] = mio_pad_sleep_status_0_en_7_qs;
+ reg_rdata_next[8] = mio_pad_sleep_status_0_en_8_qs;
+ reg_rdata_next[9] = mio_pad_sleep_status_0_en_9_qs;
+ reg_rdata_next[10] = mio_pad_sleep_status_0_en_10_qs;
+ reg_rdata_next[11] = mio_pad_sleep_status_0_en_11_qs;
+ reg_rdata_next[12] = mio_pad_sleep_status_0_en_12_qs;
+ reg_rdata_next[13] = mio_pad_sleep_status_0_en_13_qs;
+ reg_rdata_next[14] = mio_pad_sleep_status_0_en_14_qs;
+ reg_rdata_next[15] = mio_pad_sleep_status_0_en_15_qs;
+ reg_rdata_next[16] = mio_pad_sleep_status_0_en_16_qs;
+ reg_rdata_next[17] = mio_pad_sleep_status_0_en_17_qs;
+ reg_rdata_next[18] = mio_pad_sleep_status_0_en_18_qs;
+ reg_rdata_next[19] = mio_pad_sleep_status_0_en_19_qs;
+ reg_rdata_next[20] = mio_pad_sleep_status_0_en_20_qs;
+ reg_rdata_next[21] = mio_pad_sleep_status_0_en_21_qs;
+ reg_rdata_next[22] = mio_pad_sleep_status_0_en_22_qs;
+ reg_rdata_next[23] = mio_pad_sleep_status_0_en_23_qs;
+ reg_rdata_next[24] = mio_pad_sleep_status_0_en_24_qs;
+ reg_rdata_next[25] = mio_pad_sleep_status_0_en_25_qs;
+ reg_rdata_next[26] = mio_pad_sleep_status_0_en_26_qs;
+ reg_rdata_next[27] = mio_pad_sleep_status_0_en_27_qs;
+ reg_rdata_next[28] = mio_pad_sleep_status_0_en_28_qs;
+ reg_rdata_next[29] = mio_pad_sleep_status_0_en_29_qs;
+ reg_rdata_next[30] = mio_pad_sleep_status_0_en_30_qs;
+ reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs;
+ end
+
+ addr_hit[398]: begin
+ reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs;
+ reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs;
+ reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs;
+ reg_rdata_next[3] = mio_pad_sleep_status_1_en_35_qs;
+ reg_rdata_next[4] = mio_pad_sleep_status_1_en_36_qs;
+ reg_rdata_next[5] = mio_pad_sleep_status_1_en_37_qs;
+ reg_rdata_next[6] = mio_pad_sleep_status_1_en_38_qs;
+ reg_rdata_next[7] = mio_pad_sleep_status_1_en_39_qs;
+ reg_rdata_next[8] = mio_pad_sleep_status_1_en_40_qs;
+ reg_rdata_next[9] = mio_pad_sleep_status_1_en_41_qs;
+ reg_rdata_next[10] = mio_pad_sleep_status_1_en_42_qs;
+ reg_rdata_next[11] = mio_pad_sleep_status_1_en_43_qs;
+ reg_rdata_next[12] = mio_pad_sleep_status_1_en_44_qs;
+ reg_rdata_next[13] = mio_pad_sleep_status_1_en_45_qs;
+ reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs;
+ reg_rdata_next[15] = mio_pad_sleep_status_1_en_47_qs;
+ reg_rdata_next[16] = mio_pad_sleep_status_1_en_48_qs;
+ reg_rdata_next[17] = mio_pad_sleep_status_1_en_49_qs;
+ reg_rdata_next[18] = mio_pad_sleep_status_1_en_50_qs;
+ reg_rdata_next[19] = mio_pad_sleep_status_1_en_51_qs;
+ reg_rdata_next[20] = mio_pad_sleep_status_1_en_52_qs;
+ end
+
+ addr_hit[399]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
+ end
+
+ addr_hit[400]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
+ end
+
+ addr_hit[401]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
+ end
+
+ addr_hit[402]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
+ end
+
+ addr_hit[403]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
+ end
+
+ addr_hit[404]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
+ end
+
+ addr_hit[405]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
+ end
+
+ addr_hit[406]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
+ end
+
+ addr_hit[407]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
+ end
+
+ addr_hit[408]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
+ end
+
+ addr_hit[409]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
+ end
+
+ addr_hit[410]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
+ end
+
+ addr_hit[411]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
+ end
+
+ addr_hit[412]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
+ end
+
+ addr_hit[413]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
+ end
+
+ addr_hit[414]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
+ end
+
+ addr_hit[415]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
+ end
+
+ addr_hit[416]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
+ end
+
+ addr_hit[417]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
+ end
+
+ addr_hit[418]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
+ end
+
+ addr_hit[419]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
+ end
+
+ addr_hit[420]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
+ end
+
+ addr_hit[421]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
+ end
+
+ addr_hit[422]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
+ end
+
+ addr_hit[423]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
+ end
+
+ addr_hit[424]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
+ end
+
+ addr_hit[425]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
+ end
+
+ addr_hit[426]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
+ end
+
+ addr_hit[427]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
+ end
+
+ addr_hit[428]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
+ end
+
+ addr_hit[429]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
+ end
+
+ addr_hit[430]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
+ end
+
+ addr_hit[431]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs;
+ end
+
+ addr_hit[432]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs;
+ end
+
+ addr_hit[433]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs;
+ end
+
+ addr_hit[434]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs;
+ end
+
+ addr_hit[435]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs;
+ end
+
+ addr_hit[436]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs;
+ end
+
+ addr_hit[437]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs;
+ end
+
+ addr_hit[438]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs;
+ end
+
+ addr_hit[439]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs;
+ end
+
+ addr_hit[440]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs;
+ end
+
+ addr_hit[441]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs;
+ end
+
+ addr_hit[442]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs;
+ end
+
+ addr_hit[443]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs;
+ end
+
+ addr_hit[444]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs;
+ end
+
+ addr_hit[445]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs;
+ end
+
+ addr_hit[446]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_47_qs;
+ end
+
+ addr_hit[447]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_48_qs;
+ end
+
+ addr_hit[448]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_49_qs;
+ end
+
+ addr_hit[449]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_50_qs;
+ end
+
+ addr_hit[450]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_51_qs;
+ end
+
+ addr_hit[451]: begin
+ reg_rdata_next[0] = mio_pad_sleep_regwen_52_qs;
+ end
+
+ addr_hit[452]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
+ end
+
+ addr_hit[453]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
+ end
+
+ addr_hit[454]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
+ end
+
+ addr_hit[455]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
+ end
+
+ addr_hit[456]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
+ end
+
+ addr_hit[457]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
+ end
+
+ addr_hit[458]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
+ end
+
+ addr_hit[459]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
+ end
+
+ addr_hit[460]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
+ end
+
+ addr_hit[461]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
+ end
+
+ addr_hit[462]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
+ end
+
+ addr_hit[463]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
+ end
+
+ addr_hit[464]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
+ end
+
+ addr_hit[465]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
+ end
+
+ addr_hit[466]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
+ end
+
+ addr_hit[467]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
+ end
+
+ addr_hit[468]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
+ end
+
+ addr_hit[469]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
+ end
+
+ addr_hit[470]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
+ end
+
+ addr_hit[471]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
+ end
+
+ addr_hit[472]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
+ end
+
+ addr_hit[473]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
+ end
+
+ addr_hit[474]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
+ end
+
+ addr_hit[475]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
+ end
+
+ addr_hit[476]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
+ end
+
+ addr_hit[477]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
+ end
+
+ addr_hit[478]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
+ end
+
+ addr_hit[479]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
+ end
+
+ addr_hit[480]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
+ end
+
+ addr_hit[481]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
+ end
+
+ addr_hit[482]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
+ end
+
+ addr_hit[483]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
+ end
+
+ addr_hit[484]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_32_qs;
+ end
+
+ addr_hit[485]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_33_qs;
+ end
+
+ addr_hit[486]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_34_qs;
+ end
+
+ addr_hit[487]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_35_qs;
+ end
+
+ addr_hit[488]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_36_qs;
+ end
+
+ addr_hit[489]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_37_qs;
+ end
+
+ addr_hit[490]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_38_qs;
+ end
+
+ addr_hit[491]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_39_qs;
+ end
+
+ addr_hit[492]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_40_qs;
+ end
+
+ addr_hit[493]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_41_qs;
+ end
+
+ addr_hit[494]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_42_qs;
+ end
+
+ addr_hit[495]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_43_qs;
+ end
+
+ addr_hit[496]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_44_qs;
+ end
+
+ addr_hit[497]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_45_qs;
+ end
+
+ addr_hit[498]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_46_qs;
+ end
+
+ addr_hit[499]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_47_qs;
+ end
+
+ addr_hit[500]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_48_qs;
+ end
+
+ addr_hit[501]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_49_qs;
+ end
+
+ addr_hit[502]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_50_qs;
+ end
+
+ addr_hit[503]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_51_qs;
+ end
+
+ addr_hit[504]: begin
+ reg_rdata_next[0] = mio_pad_sleep_en_52_qs;
+ end
+
+ addr_hit[505]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
+ end
+
+ addr_hit[506]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
+ end
+
+ addr_hit[507]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
+ end
+
+ addr_hit[508]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
+ end
+
+ addr_hit[509]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
+ end
+
+ addr_hit[510]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
+ end
+
+ addr_hit[511]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
+ end
+
+ addr_hit[512]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
+ end
+
+ addr_hit[513]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
+ end
+
+ addr_hit[514]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
+ end
+
+ addr_hit[515]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
+ end
+
+ addr_hit[516]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
+ end
+
+ addr_hit[517]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
+ end
+
+ addr_hit[518]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
+ end
+
+ addr_hit[519]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
+ end
+
+ addr_hit[520]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
+ end
+
+ addr_hit[521]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
+ end
+
+ addr_hit[522]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
+ end
+
+ addr_hit[523]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
+ end
+
+ addr_hit[524]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
+ end
+
+ addr_hit[525]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
+ end
+
+ addr_hit[526]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
+ end
+
+ addr_hit[527]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
+ end
+
+ addr_hit[528]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
+ end
+
+ addr_hit[529]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
+ end
+
+ addr_hit[530]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
+ end
+
+ addr_hit[531]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
+ end
+
+ addr_hit[532]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
+ end
+
+ addr_hit[533]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
+ end
+
+ addr_hit[534]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
+ end
+
+ addr_hit[535]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
+ end
+
+ addr_hit[536]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
+ end
+
+ addr_hit[537]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs;
+ end
+
+ addr_hit[538]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs;
+ end
+
+ addr_hit[539]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs;
+ end
+
+ addr_hit[540]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs;
+ end
+
+ addr_hit[541]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs;
+ end
+
+ addr_hit[542]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs;
+ end
+
+ addr_hit[543]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs;
+ end
+
+ addr_hit[544]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs;
+ end
+
+ addr_hit[545]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs;
+ end
+
+ addr_hit[546]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs;
+ end
+
+ addr_hit[547]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs;
+ end
+
+ addr_hit[548]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs;
+ end
+
+ addr_hit[549]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs;
+ end
+
+ addr_hit[550]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs;
+ end
+
+ addr_hit[551]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs;
+ end
+
+ addr_hit[552]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_47_qs;
+ end
+
+ addr_hit[553]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_48_qs;
+ end
+
+ addr_hit[554]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_49_qs;
+ end
+
+ addr_hit[555]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_50_qs;
+ end
+
+ addr_hit[556]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_51_qs;
+ end
+
+ addr_hit[557]: begin
+ reg_rdata_next[1:0] = mio_pad_sleep_mode_52_qs;
+ end
+
+ addr_hit[558]: begin
+ reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
+ reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
+ reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
+ reg_rdata_next[3] = dio_pad_sleep_status_en_3_qs;
+ reg_rdata_next[4] = dio_pad_sleep_status_en_4_qs;
+ reg_rdata_next[5] = dio_pad_sleep_status_en_5_qs;
+ reg_rdata_next[6] = dio_pad_sleep_status_en_6_qs;
+ reg_rdata_next[7] = dio_pad_sleep_status_en_7_qs;
+ reg_rdata_next[8] = dio_pad_sleep_status_en_8_qs;
+ reg_rdata_next[9] = dio_pad_sleep_status_en_9_qs;
+ reg_rdata_next[10] = dio_pad_sleep_status_en_10_qs;
+ reg_rdata_next[11] = dio_pad_sleep_status_en_11_qs;
+ reg_rdata_next[12] = dio_pad_sleep_status_en_12_qs;
+ reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs;
+ reg_rdata_next[14] = dio_pad_sleep_status_en_14_qs;
+ reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs;
+ end
+
+ addr_hit[559]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
+ end
+
+ addr_hit[560]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
+ end
+
+ addr_hit[561]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
+ end
+
+ addr_hit[562]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
+ end
+
+ addr_hit[563]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
+ end
+
+ addr_hit[564]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
+ end
+
+ addr_hit[565]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
+ end
+
+ addr_hit[566]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
+ end
+
+ addr_hit[567]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
+ end
+
+ addr_hit[568]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
+ end
+
+ addr_hit[569]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
+ end
+
+ addr_hit[570]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
+ end
+
+ addr_hit[571]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
+ end
+
+ addr_hit[572]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
+ end
+
+ addr_hit[573]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
+ end
+
+ addr_hit[574]: begin
+ reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
+ end
+
+ addr_hit[575]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
+ end
+
+ addr_hit[576]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
+ end
+
+ addr_hit[577]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
+ end
+
+ addr_hit[578]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
+ end
+
+ addr_hit[579]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
+ end
+
+ addr_hit[580]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
+ end
+
+ addr_hit[581]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
+ end
+
+ addr_hit[582]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
+ end
+
+ addr_hit[583]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
+ end
+
+ addr_hit[584]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
+ end
+
+ addr_hit[585]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
+ end
+
+ addr_hit[586]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
+ end
+
+ addr_hit[587]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
+ end
+
+ addr_hit[588]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
+ end
+
+ addr_hit[589]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
+ end
+
+ addr_hit[590]: begin
+ reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
+ end
+
+ addr_hit[591]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
+ end
+
+ addr_hit[592]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
+ end
+
+ addr_hit[593]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
+ end
+
+ addr_hit[594]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
+ end
+
+ addr_hit[595]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
+ end
+
+ addr_hit[596]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
+ end
+
+ addr_hit[597]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
+ end
+
+ addr_hit[598]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
+ end
+
+ addr_hit[599]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
+ end
+
+ addr_hit[600]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
+ end
+
+ addr_hit[601]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
+ end
+
+ addr_hit[602]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
+ end
+
+ addr_hit[603]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
+ end
+
+ addr_hit[604]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
+ end
+
+ addr_hit[605]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
+ end
+
+ addr_hit[606]: begin
+ reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
+ end
+
+ addr_hit[607]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_0_qs;
+ end
+
+ addr_hit[608]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_1_qs;
+ end
+
+ addr_hit[609]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_2_qs;
+ end
+
+ addr_hit[610]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_3_qs;
+ end
+
+ addr_hit[611]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_4_qs;
+ end
+
+ addr_hit[612]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_5_qs;
+ end
+
+ addr_hit[613]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_6_qs;
+ end
+
+ addr_hit[614]: begin
+ reg_rdata_next[0] = wkup_detector_regwen_7_qs;
+ end
+
+ addr_hit[615]: begin
+ reg_rdata_next = DW'(wkup_detector_en_0_qs);
+ end
+ addr_hit[616]: begin
+ reg_rdata_next = DW'(wkup_detector_en_1_qs);
+ end
+ addr_hit[617]: begin
+ reg_rdata_next = DW'(wkup_detector_en_2_qs);
+ end
+ addr_hit[618]: begin
+ reg_rdata_next = DW'(wkup_detector_en_3_qs);
+ end
+ addr_hit[619]: begin
+ reg_rdata_next = DW'(wkup_detector_en_4_qs);
+ end
+ addr_hit[620]: begin
+ reg_rdata_next = DW'(wkup_detector_en_5_qs);
+ end
+ addr_hit[621]: begin
+ reg_rdata_next = DW'(wkup_detector_en_6_qs);
+ end
+ addr_hit[622]: begin
+ reg_rdata_next = DW'(wkup_detector_en_7_qs);
+ end
+ addr_hit[623]: begin
+ reg_rdata_next = DW'(wkup_detector_0_qs);
+ end
+ addr_hit[624]: begin
+ reg_rdata_next = DW'(wkup_detector_1_qs);
+ end
+ addr_hit[625]: begin
+ reg_rdata_next = DW'(wkup_detector_2_qs);
+ end
+ addr_hit[626]: begin
+ reg_rdata_next = DW'(wkup_detector_3_qs);
+ end
+ addr_hit[627]: begin
+ reg_rdata_next = DW'(wkup_detector_4_qs);
+ end
+ addr_hit[628]: begin
+ reg_rdata_next = DW'(wkup_detector_5_qs);
+ end
+ addr_hit[629]: begin
+ reg_rdata_next = DW'(wkup_detector_6_qs);
+ end
+ addr_hit[630]: begin
+ reg_rdata_next = DW'(wkup_detector_7_qs);
+ end
+ addr_hit[631]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs);
+ end
+ addr_hit[632]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs);
+ end
+ addr_hit[633]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs);
+ end
+ addr_hit[634]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs);
+ end
+ addr_hit[635]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs);
+ end
+ addr_hit[636]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs);
+ end
+ addr_hit[637]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs);
+ end
+ addr_hit[638]: begin
+ reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs);
+ end
+ addr_hit[639]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
+ end
+
+ addr_hit[640]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
+ end
+
+ addr_hit[641]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
+ end
+
+ addr_hit[642]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
+ end
+
+ addr_hit[643]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
+ end
+
+ addr_hit[644]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
+ end
+
+ addr_hit[645]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
+ end
+
+ addr_hit[646]: begin
+ reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
+ end
+
+ addr_hit[647]: begin
+ reg_rdata_next = DW'(wkup_cause_qs);
+ end
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ logic reg_busy_sel;
+ assign reg_busy = reg_busy_sel | shadow_busy;
+ always_comb begin
+ reg_busy_sel = '0;
+ unique case (1'b1)
+ addr_hit[615]: begin
+ reg_busy_sel = wkup_detector_en_0_busy;
+ end
+ addr_hit[616]: begin
+ reg_busy_sel = wkup_detector_en_1_busy;
+ end
+ addr_hit[617]: begin
+ reg_busy_sel = wkup_detector_en_2_busy;
+ end
+ addr_hit[618]: begin
+ reg_busy_sel = wkup_detector_en_3_busy;
+ end
+ addr_hit[619]: begin
+ reg_busy_sel = wkup_detector_en_4_busy;
+ end
+ addr_hit[620]: begin
+ reg_busy_sel = wkup_detector_en_5_busy;
+ end
+ addr_hit[621]: begin
+ reg_busy_sel = wkup_detector_en_6_busy;
+ end
+ addr_hit[622]: begin
+ reg_busy_sel = wkup_detector_en_7_busy;
+ end
+ addr_hit[623]: begin
+ reg_busy_sel = wkup_detector_0_busy;
+ end
+ addr_hit[624]: begin
+ reg_busy_sel = wkup_detector_1_busy;
+ end
+ addr_hit[625]: begin
+ reg_busy_sel = wkup_detector_2_busy;
+ end
+ addr_hit[626]: begin
+ reg_busy_sel = wkup_detector_3_busy;
+ end
+ addr_hit[627]: begin
+ reg_busy_sel = wkup_detector_4_busy;
+ end
+ addr_hit[628]: begin
+ reg_busy_sel = wkup_detector_5_busy;
+ end
+ addr_hit[629]: begin
+ reg_busy_sel = wkup_detector_6_busy;
+ end
+ addr_hit[630]: begin
+ reg_busy_sel = wkup_detector_7_busy;
+ end
+ addr_hit[631]: begin
+ reg_busy_sel = wkup_detector_cnt_th_0_busy;
+ end
+ addr_hit[632]: begin
+ reg_busy_sel = wkup_detector_cnt_th_1_busy;
+ end
+ addr_hit[633]: begin
+ reg_busy_sel = wkup_detector_cnt_th_2_busy;
+ end
+ addr_hit[634]: begin
+ reg_busy_sel = wkup_detector_cnt_th_3_busy;
+ end
+ addr_hit[635]: begin
+ reg_busy_sel = wkup_detector_cnt_th_4_busy;
+ end
+ addr_hit[636]: begin
+ reg_busy_sel = wkup_detector_cnt_th_5_busy;
+ end
+ addr_hit[637]: begin
+ reg_busy_sel = wkup_detector_cnt_th_6_busy;
+ end
+ addr_hit[638]: begin
+ reg_busy_sel = wkup_detector_cnt_th_7_busy;
+ end
+ addr_hit[647]: begin
+ reg_busy_sel = wkup_cause_busy;
+ end
+ default: begin
+ reg_busy_sel = '0;
+ end
+ endcase
+ end
+
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson
new file mode 100644
index 0000000..a79f330
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr.hjson
@@ -0,0 +1,778 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "pwrmgr",
+ human_name: "Power Manager",
+ one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states",
+ one_paragraph_desc: '''
+ Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets.
+ To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager.
+ During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute.
+ It features several countermeasures to deter fault injection (FI) attacks.
+ '''
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_pwrmgr",
+ revisions: [
+ {
+ version: "0.1",
+ life_stage: "L1",
+ design_stage: "D1",
+ verification_stage: "V0", // this module is not verified at the block level
+ dif_stage: "S0",
+ commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb"
+ }
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D2S",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ }
+ ]
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {reset: "rst_main_ni"},
+ {clock: "clk_slow_i", reset: "rst_slow_ni"},
+ {clock: "clk_lc_i", reset: "rst_lc_ni"},
+ {clock: "clk_esc_i", reset: "rst_esc_ni"}
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+ interrupt_list: [
+ { name: "wakeup", desc: "Wake from low power state. See wake info for more details" },
+ ],
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+
+ inter_signal_list: [
+ { struct: "pwr_ast",
+ type: "req_rsp",
+ name: "pwr_ast",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_rst",
+ type: "req_rsp",
+ name: "pwr_rst",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_clk",
+ type: "req_rsp",
+ name: "pwr_clk",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_otp",
+ type: "req_rsp",
+ name: "pwr_otp",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_lc",
+ type: "req_rsp",
+ name: "pwr_lc",
+ act: "req",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "pwr_flash",
+ type: "uni",
+ name: "pwr_flash",
+ act: "rcv",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "esc_tx",
+ type: "uni",
+ name: "esc_rst_tx",
+ act: "rcv",
+ package: "prim_esc_pkg",
+ },
+
+ { struct: "esc_rx",
+ type: "uni",
+ name: "esc_rst_rx",
+ act: "req",
+ package: "prim_esc_pkg",
+ },
+
+ { struct: "pwr_cpu",
+ type: "uni",
+ name: "pwr_cpu",
+ act: "rcv",
+ package: "pwrmgr_pkg",
+ },
+
+ { struct: "logic",
+ width: 6,
+ type: "uni",
+ name: "wakeups",
+ act: "rcv",
+ package: "",
+ },
+
+ { struct: "logic",
+ width: 2,
+ type: "uni",
+ name: "rstreqs",
+ act: "rcv",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "ndmreset_req",
+ act: "rcv",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "strap",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "low_power",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "pwrmgr_data",
+ type: "uni",
+ name: "rom_ctrl",
+ act: "rcv",
+ package: "rom_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "fetch_en",
+ act: "req",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_dft_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_hw_debug_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg",
+ },
+
+ { struct: "mubi4",
+ type: "uni",
+ name: "sw_rst_req",
+ act: "rcv",
+ package: "prim_mubi_pkg",
+ },
+ ],
+
+ param_list: [
+ { name: "NumWkups",
+ desc: "Number of wakeups",
+ type: "int",
+ default: "6",
+ local: "true"
+ },
+
+ { name: "SYSRST_CTRL_AON_WKUP_REQ_IDX",
+ desc: "Vector index for sysrst_ctrl_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "0",
+ local: "true"
+ },
+
+ { name: "ADC_CTRL_AON_WKUP_REQ_IDX",
+ desc: "Vector index for adc_ctrl_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "1",
+ local: "true"
+ },
+
+ { name: "PINMUX_AON_PIN_WKUP_REQ_IDX",
+ desc: "Vector index for pinmux_aon pin_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "PINMUX_AON_USB_WKUP_REQ_IDX",
+ desc: "Vector index for pinmux_aon usb_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "3",
+ local: "true"
+ },
+
+ { name: "AON_TIMER_AON_WKUP_REQ_IDX",
+ desc: "Vector index for aon_timer_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+
+ { name: "SENSOR_CTRL_WKUP_REQ_IDX",
+ desc: "Vector index for sensor_ctrl wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ type: "int",
+ default: "5",
+ local: "true"
+ },
+
+
+ { name: "NumRstReqs",
+ desc: "Number of peripheral reset requets",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "NumIntRstReqs",
+ desc: "Number of pwrmgr internal reset requets",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+
+ { name: "NumDebugRstReqs",
+ desc: "Number of debug reset requets",
+ type: "int",
+ default: "1",
+ local: "true"
+ },
+
+ { name: "ResetMainPwrIdx",
+ desc: "Reset req idx for MainPwr",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+ { name: "ResetEscIdx",
+ desc: "Reset req idx for Esc",
+ type: "int",
+ default: "3",
+ local: "true"
+ },
+ { name: "ResetNdmIdx",
+ desc: "Reset req idx for Ndm",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+
+ ],
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ { name: "LC_CTRL.INTERSIG.MUBI",
+ desc: "life cycle control / debug signals are multibit."
+ }
+ { name: "ROM_CTRL.INTERSIG.MUBI",
+ desc: "rom control done/good signals are multibit."
+ }
+ { name: "RSTMGR.INTERSIG.MUBI",
+ desc: "reset manager software request is multibit."
+ }
+ { name: "ESC_RX.CLK.BKGN_CHK",
+ desc: "Escalation receiver has a background timeout check"
+ }
+ { name: "ESC_RX.CLK.LOCAL_ESC",
+ desc: "Escalation receiver clock timeout has a local reset escalation"
+ }
+ { name: "FSM.SPARSE",
+ desc: "Sparse encoding for slow and fast state machines."
+ }
+ { name: "FSM.TERMINAL",
+ desc: '''
+ When FSMs reach a bad state, go into a terminate state that does not
+ recover without user or external host intervention.
+ '''
+ }
+ { name: "CTRL_FLOW.GLOBAL_ESC",
+ desc: "When global escalation is received, proceed directly to reset."
+ }
+ { name: "MAIN_PD.RST.LOCAL_ESC",
+ desc: "When main power domain reset glitches, proceed directly to reset."
+ }
+ { name: "CTRL.CONFIG.REGWEN",
+ desc: "Main control protected by regwen."
+ }
+ { name: "WAKEUP.CONFIG.REGWEN",
+ desc: "Wakeup configuration protected by regwen."
+ }
+ { name: "RESET.CONFIG.REGWEN",
+ desc: "Reset configuration protected by regwen."
+ }
+
+ ]
+
+ regwidth: "32",
+ registers: [
+
+ { name: "CTRL_CFG_REGWEN",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ desc: '''
+ Controls the configurability of the !!CONTROL register.
+
+ This register ensures the contents do not change once a low power hint and
+ WFI has occurred.
+
+ It unlocks whenever a low power transition has completed (transition back to the
+ ACTIVE state) for any reason.
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Configuration enable.
+
+ This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated.
+ When the device transitions back from low power state to active state, this bit is set
+ back to 1 to allow software configuration of !!CONTROL
+ ''',
+ resval: "1",
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+
+ { name: "CONTROL",
+ desc: "Control register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CTRL_CFG_REGWEN",
+ tags: [// Turning off USB clock in active state impacts other CSRs
+ // at the chip level (in other blocks, such as clkmgr),
+ // so we exclude writing from this register.
+ "excl:CsrAllTests:CsrExclWrite"]
+ fields: [
+ { bits: "0",
+ hwaccess: "hrw",
+ name: "LOW_POWER_HINT",
+ desc: '''
+ The low power hint to power manager.
+ The hint is an indication for how the manager should treat the next WFI.
+ Once the power manager begins a low power transition, or if a valid reset request is registered,
+ this bit is automatically cleared by HW.
+ '''
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "None",
+ desc: '''
+ No low power intent
+ '''
+ },
+ { value: "1",
+ name: "Low Power",
+ desc: '''
+ Next WFI should trigger low power entry
+ '''
+ },
+ ]
+ tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg
+ "excl:CsrAllTests:CsrExclAll"]
+ },
+
+ { bits: "4",
+ name: "CORE_CLK_EN",
+ desc: "core clock enable during low power state",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ Core clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ Core clock enabled during low power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "5",
+ name: "IO_CLK_EN",
+ desc: "IO clock enable during low power state",
+ resval: "0"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ IO clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ IO clock enabled during low power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "6",
+ name: "USB_CLK_EN_LP",
+ desc: "USB clock enable during low power state",
+ resval: "0",
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ USB clock disabled during low power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ USB clock enabled during low power state.
+
+ However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled
+ during low power state.
+ '''
+ },
+ ]
+ },
+
+ { bits: "7",
+ name: "USB_CLK_EN_ACTIVE",
+ desc: "USB clock enable during active power state",
+ resval: "1"
+ enum: [
+ { value: "0",
+ name: "Disabled",
+ desc: '''
+ USB clock disabled during active power state
+ '''
+ },
+ { value: "1",
+ name: "Enabled",
+ desc: '''
+ USB clock enabled during active power state
+ '''
+ },
+ ]
+ },
+
+ { bits: "8",
+ name: "MAIN_PD_N",
+ desc: "Active low, main power domain power down",
+ resval: "1"
+ enum: [
+ { value: "0",
+ name: "Power down",
+ desc: '''
+ Main power domain is powered down during low power state.
+ '''
+ },
+ { value: "1",
+ name: "Power up",
+ desc: '''
+ Main power domain is kept powered during low power state
+ '''
+ },
+ ]
+ },
+
+
+ ],
+ },
+
+ { name: "CFG_CDC_SYNC",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwqe: "true",
+ desc: '''
+ The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the
+ fast clock domain but used in the slow clock domain.
+
+ The configuration are not propagated across the clock boundary until this
+ register is triggered and read. See fields below for more details
+ ''',
+
+ fields: [
+ { bits: "0",
+ name: "SYNC",
+ desc: '''
+ Configuration sync. When this bit is written to 1, a sync pulse is generated. When
+ the sync completes, this bit then self clears.
+
+ Software should write this bit to 1, wait for it to clear, before assuming the slow clock
+ domain has accepted the programmed values.
+ ''',
+ resval: "0",
+ },
+ ]
+ tags: [// This bit triggers a payload synchronization and self clears when complete.
+ // Do not write this bit as there will be side effects and the value will not persist
+ "excl:CsrNonInitTests:CsrExclWrite"]
+ },
+
+ { name: "WAKEUP_EN_REGWEN",
+ desc: "Configuration enable for wakeup_en register",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ resval: "1"
+ name: "EN",
+ desc: '''
+ When 1, WAKEUP_EN register can be configured.
+ When 0, WAKEUP_EN register cannot be configured.
+ ''',
+ },
+ ]
+ },
+
+ { multireg:
+ { name: "WAKEUP_EN",
+ desc: "Bit mask for enabled wakeups",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WAKEUP_EN_REGWEN",
+ resval: "0"
+ cname: "wakeup_en",
+ count: "NumWkups"
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Whenever a particular bit is set to 1, that wakeup is also enabled.
+ Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
+ ''',
+ },
+ ]
+ },
+ },
+
+ { multireg:
+ { name: "WAKE_STATUS",
+ desc: "A read only register of all current wake requests post enable mask",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ cname: "wake_status",
+ count: "NumWkups",
+ tags: [// Cannot auto-predict current wake request status
+ "excl:CsrNonInitTests:CsrExclWriteCheck"],
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Current value of wake requests
+ ''',
+ },
+ ]
+ },
+ },
+
+ { name: "RESET_EN_REGWEN",
+ desc: "Configuration enable for reset_en register",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ resval: "1"
+ name: "EN",
+ desc: '''
+ When 1, RESET_EN register can be configured.
+ When 0, RESET_EN register cannot be configured.
+ ''',
+ },
+ ]
+ },
+
+ { multireg:
+ { name: "RESET_EN",
+ desc: "Bit mask for enabled reset requests",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "RESET_EN_REGWEN",
+ resval: "0"
+ cname: "rstreq_en",
+ count: "NumRstReqs"
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Whenever a particular bit is set to 1, that reset request is enabled.
+ Whenever a particular bit is set to 0, that reset request cannot reset the device.
+ ''',
+ },
+ ]
+ tags: [// Self resets should never be triggered by automated tests
+ "excl:CsrAllTests:CsrExclWrite"]
+ },
+ },
+
+ { multireg:
+ { name: "RESET_STATUS",
+ desc: "A read only register of all current reset requests post enable mask",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ cname: "reset_status",
+ count: "NumRstReqs",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Current value of reset request
+ ''',
+ },
+ ]
+ },
+ },
+
+ { name: "ESCALATE_RESET_STATUS",
+ desc: "A read only register of escalation reset request",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ When 1, an escalation reset has been seen.
+ When 0, there is no escalation reset.
+ ''',
+ },
+ ]
+ },
+
+ { name: "WAKE_INFO_CAPTURE_DIS",
+ desc: "Indicates which functions caused the chip to wakeup",
+ swaccess: "rw",
+ hwaccess: "hro",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ When written to 1, this actively suppresses the wakeup info capture.
+ When written to 0, wakeup info capture timing is controlled by HW.
+ ''',
+ },
+ ]
+ },
+
+ { name: "WAKE_INFO",
+ desc: '''
+ Indicates which functions caused the chip to wakeup.
+ The wake info recording begins whenever the device begins a valid low power entry.
+
+ This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS.
+ This means it is possible to capture multiple wakeup reasons.
+ ''',
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ resval: "0"
+ fields: [
+ { bits: "5:0",
+ name: "REASONS",
+ desc: "Various peripheral wake reasons"
+ },
+ { bits: "6",
+ name: "FALL_THROUGH",
+ desc: '''
+ The fall through wakeup reason indicates that despite setting a WFI and providing a low power
+ hint, an interrupt arrived at just the right time to break the executing core out of WFI.
+
+ The power manager detects this condition, halts low power entry and reports as a wakeup reason
+ ''',
+ },
+ { bits: "7",
+ name: "ABORT",
+ desc: '''
+ The abort wakeup reason indicates that despite setting a WFI and providing a low power
+ hint, an active flash / lifecycle / otp transaction was ongoing when the power controller
+ attempted to initiate low power entry.
+
+ The power manager detects this condition, halts low power entry and reports as a wakeup reason
+ ''',
+ },
+ ]
+ tags: [// This regwen is completely under HW management and thus cannot be manipulated
+ // by software.
+ "excl:CsrNonInitTests:CsrExclCheck"]
+ },
+
+ { name: "FAULT_STATUS",
+ desc: "A read only register that shows the existing faults",
+ swaccess: "ro",
+ hwaccess: "hrw",
+ sync: "clk_lc_i",
+ resval: "0"
+ fields: [
+ { bits: "0",
+ name: "REG_INTG_ERR",
+ desc: '''
+ When 1, an integrity error has occurred.
+ ''',
+ },
+
+ { bits: "1",
+ name: "ESC_TIMEOUT",
+ desc: '''
+ When 1, an escalation clock / reset timeout has occurred.
+ ''',
+ },
+
+ { bits: "2",
+ name: "MAIN_PD_GLITCH",
+ desc: '''
+ When 1, unexpected power glitch was observed on main PD.
+ ''',
+ },
+ ]
+ },
+ ]
+}
diff --git a/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson b/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson
new file mode 100644
index 0000000..40db006
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/data/autogen/pwrmgr_sec_cm_testplan.hjson
@@ -0,0 +1,105 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../pwrmgr/data/pwrmgr.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../pwrmgr/data/pwrmgr_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_lc_ctrl_intersig_mubi
+ desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_rom_ctrl_intersig_mubi
+ desc: "Verify the countermeasure(s) ROM_CTRL.INTERSIG.MUBI."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_rstmgr_intersig_mubi
+ desc: "Verify the countermeasure(s) RSTMGR.INTERSIG.MUBI."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_esc_rx_clk_bkgn_chk
+ desc: "Verify the countermeasure(s) ESC_RX.CLK.BKGN_CHK."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_esc_rx_clk_local_esc
+ desc: "Verify the countermeasure(s) ESC_RX.CLK.LOCAL_ESC."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_fsm_sparse
+ desc: "Verify the countermeasure(s) FSM.SPARSE."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_fsm_terminal
+ desc: "Verify the countermeasure(s) FSM.TERMINAL."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_ctrl_flow_global_esc
+ desc: "Verify the countermeasure(s) CTRL_FLOW.GLOBAL_ESC."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_main_pd_rst_local_esc
+ desc: "Verify the countermeasure(s) MAIN_PD.RST.LOCAL_ESC."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_ctrl_config_regwen
+ desc: "Verify the countermeasure(s) CTRL.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_wakeup_config_regwen
+ desc: "Verify the countermeasure(s) WAKEUP.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_reset_config_regwen
+ desc: "Verify the countermeasure(s) RESET.CONFIG.REGWEN."
+ stage: V2S
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv b/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
new file mode 100644
index 0000000..bd0e1b3
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
@@ -0,0 +1,279 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pwrmgr_reg_pkg;
+
+ // Param list
+ parameter int NumWkups = 6;
+ parameter int SYSRST_CTRL_AON_WKUP_REQ_IDX = 0;
+ parameter int ADC_CTRL_AON_WKUP_REQ_IDX = 1;
+ parameter int PINMUX_AON_PIN_WKUP_REQ_IDX = 2;
+ parameter int PINMUX_AON_USB_WKUP_REQ_IDX = 3;
+ parameter int AON_TIMER_AON_WKUP_REQ_IDX = 4;
+ parameter int SENSOR_CTRL_WKUP_REQ_IDX = 5;
+ parameter int NumRstReqs = 2;
+ parameter int NumIntRstReqs = 2;
+ parameter int NumDebugRstReqs = 1;
+ parameter int ResetMainPwrIdx = 2;
+ parameter int ResetEscIdx = 3;
+ parameter int ResetNdmIdx = 4;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 7;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } low_power_hint;
+ struct packed {
+ logic q;
+ } core_clk_en;
+ struct packed {
+ logic q;
+ } io_clk_en;
+ struct packed {
+ logic q;
+ } usb_clk_en_lp;
+ struct packed {
+ logic q;
+ } usb_clk_en_active;
+ struct packed {
+ logic q;
+ } main_pd_n;
+ } pwrmgr_reg2hw_control_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } pwrmgr_reg2hw_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wakeup_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_reset_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } pwrmgr_reg2hw_wake_info_capture_dis_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [5:0] q;
+ logic qe;
+ } reasons;
+ struct packed {
+ logic q;
+ logic qe;
+ } fall_through;
+ struct packed {
+ logic q;
+ logic qe;
+ } abort;
+ } pwrmgr_reg2hw_wake_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } esc_timeout;
+ struct packed {
+ logic q;
+ } main_pd_glitch;
+ } pwrmgr_reg2hw_fault_status_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } low_power_hint;
+ } pwrmgr_hw2reg_control_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_cfg_cdc_sync_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_wake_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_reset_status_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } pwrmgr_hw2reg_escalate_reset_status_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [5:0] d;
+ } reasons;
+ struct packed {
+ logic d;
+ } fall_through;
+ struct packed {
+ logic d;
+ } abort;
+ } pwrmgr_hw2reg_wake_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } esc_timeout;
+ struct packed {
+ logic d;
+ logic de;
+ } main_pd_glitch;
+ } pwrmgr_hw2reg_fault_status_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ pwrmgr_reg2hw_intr_state_reg_t intr_state; // [36:36]
+ pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [35:35]
+ pwrmgr_reg2hw_intr_test_reg_t intr_test; // [34:33]
+ pwrmgr_reg2hw_alert_test_reg_t alert_test; // [32:31]
+ pwrmgr_reg2hw_control_reg_t control; // [30:25]
+ pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [24:23]
+ pwrmgr_reg2hw_wakeup_en_mreg_t [5:0] wakeup_en; // [22:17]
+ pwrmgr_reg2hw_reset_en_mreg_t [1:0] reset_en; // [16:15]
+ pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [14:14]
+ pwrmgr_reg2hw_wake_info_reg_t wake_info; // [13:3]
+ pwrmgr_reg2hw_fault_status_reg_t fault_status; // [2:0]
+ } pwrmgr_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ pwrmgr_hw2reg_intr_state_reg_t intr_state; // [38:37]
+ pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [36:36]
+ pwrmgr_hw2reg_control_reg_t control; // [35:34]
+ pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [33:32]
+ pwrmgr_hw2reg_wake_status_mreg_t [5:0] wake_status; // [31:20]
+ pwrmgr_hw2reg_reset_status_mreg_t [1:0] reset_status; // [19:16]
+ pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [15:14]
+ pwrmgr_hw2reg_wake_info_reg_t wake_info; // [13:6]
+ pwrmgr_hw2reg_fault_status_reg_t fault_status; // [5:0]
+ } pwrmgr_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 7'h 0;
+ parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 7'h 4;
+ parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 7'h 8;
+ parameter logic [BlockAw-1:0] PWRMGR_ALERT_TEST_OFFSET = 7'h c;
+ parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 7'h 10;
+ parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 7'h 14;
+ parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 7'h 18;
+ parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 7'h 1c;
+ parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 7'h 20;
+ parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 7'h 24;
+ parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 7'h 28;
+ parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 7'h 2c;
+ parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 7'h 30;
+ parameter logic [BlockAw-1:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 7'h 34;
+ parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 7'h 38;
+ parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 7'h 3c;
+ parameter logic [BlockAw-1:0] PWRMGR_FAULT_STATUS_OFFSET = 7'h 40;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0;
+ parameter logic [0:0] PWRMGR_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PWRMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1;
+ parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1;
+ parameter logic [7:0] PWRMGR_WAKE_INFO_RESVAL = 8'h 0;
+ parameter logic [5:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 6'h 0;
+ parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0;
+ parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0;
+
+ // Register index
+ typedef enum int {
+ PWRMGR_INTR_STATE,
+ PWRMGR_INTR_ENABLE,
+ PWRMGR_INTR_TEST,
+ PWRMGR_ALERT_TEST,
+ PWRMGR_CTRL_CFG_REGWEN,
+ PWRMGR_CONTROL,
+ PWRMGR_CFG_CDC_SYNC,
+ PWRMGR_WAKEUP_EN_REGWEN,
+ PWRMGR_WAKEUP_EN,
+ PWRMGR_WAKE_STATUS,
+ PWRMGR_RESET_EN_REGWEN,
+ PWRMGR_RESET_EN,
+ PWRMGR_RESET_STATUS,
+ PWRMGR_ESCALATE_RESET_STATUS,
+ PWRMGR_WAKE_INFO_CAPTURE_DIS,
+ PWRMGR_WAKE_INFO,
+ PWRMGR_FAULT_STATUS
+ } pwrmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] PWRMGR_PERMIT [17] = '{
+ 4'b 0001, // index[ 0] PWRMGR_INTR_STATE
+ 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE
+ 4'b 0001, // index[ 2] PWRMGR_INTR_TEST
+ 4'b 0001, // index[ 3] PWRMGR_ALERT_TEST
+ 4'b 0001, // index[ 4] PWRMGR_CTRL_CFG_REGWEN
+ 4'b 0011, // index[ 5] PWRMGR_CONTROL
+ 4'b 0001, // index[ 6] PWRMGR_CFG_CDC_SYNC
+ 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN_REGWEN
+ 4'b 0001, // index[ 8] PWRMGR_WAKEUP_EN
+ 4'b 0001, // index[ 9] PWRMGR_WAKE_STATUS
+ 4'b 0001, // index[10] PWRMGR_RESET_EN_REGWEN
+ 4'b 0001, // index[11] PWRMGR_RESET_EN
+ 4'b 0001, // index[12] PWRMGR_RESET_STATUS
+ 4'b 0001, // index[13] PWRMGR_ESCALATE_RESET_STATUS
+ 4'b 0001, // index[14] PWRMGR_WAKE_INFO_CAPTURE_DIS
+ 4'b 0001, // index[15] PWRMGR_WAKE_INFO
+ 4'b 0001 // index[16] PWRMGR_FAULT_STATUS
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv b/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
new file mode 100644
index 0000000..84b238c
--- /dev/null
+++ b/hw/top_sencha/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
@@ -0,0 +1,1458 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module pwrmgr_reg_top (
+ input clk_i,
+ input rst_ni,
+ input clk_lc_i,
+ input rst_lc_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write
+ input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import pwrmgr_reg_pkg::* ;
+
+ localparam int AW = 7;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [16:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(17)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_lc_i or negedge rst_lc_ni) begin
+ if (!rst_lc_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_qs;
+ logic intr_state_wd;
+ logic intr_enable_we;
+ logic intr_enable_qs;
+ logic intr_enable_wd;
+ logic intr_test_we;
+ logic intr_test_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+ logic ctrl_cfg_regwen_re;
+ logic ctrl_cfg_regwen_qs;
+ logic control_we;
+ logic control_low_power_hint_qs;
+ logic control_low_power_hint_wd;
+ logic control_core_clk_en_qs;
+ logic control_core_clk_en_wd;
+ logic control_io_clk_en_qs;
+ logic control_io_clk_en_wd;
+ logic control_usb_clk_en_lp_qs;
+ logic control_usb_clk_en_lp_wd;
+ logic control_usb_clk_en_active_qs;
+ logic control_usb_clk_en_active_wd;
+ logic control_main_pd_n_qs;
+ logic control_main_pd_n_wd;
+ logic cfg_cdc_sync_we;
+ logic cfg_cdc_sync_qs;
+ logic cfg_cdc_sync_wd;
+ logic wakeup_en_regwen_we;
+ logic wakeup_en_regwen_qs;
+ logic wakeup_en_regwen_wd;
+ logic wakeup_en_we;
+ logic wakeup_en_en_0_qs;
+ logic wakeup_en_en_0_wd;
+ logic wakeup_en_en_1_qs;
+ logic wakeup_en_en_1_wd;
+ logic wakeup_en_en_2_qs;
+ logic wakeup_en_en_2_wd;
+ logic wakeup_en_en_3_qs;
+ logic wakeup_en_en_3_wd;
+ logic wakeup_en_en_4_qs;
+ logic wakeup_en_en_4_wd;
+ logic wakeup_en_en_5_qs;
+ logic wakeup_en_en_5_wd;
+ logic wake_status_val_0_qs;
+ logic wake_status_val_1_qs;
+ logic wake_status_val_2_qs;
+ logic wake_status_val_3_qs;
+ logic wake_status_val_4_qs;
+ logic wake_status_val_5_qs;
+ logic reset_en_regwen_we;
+ logic reset_en_regwen_qs;
+ logic reset_en_regwen_wd;
+ logic reset_en_we;
+ logic reset_en_en_0_qs;
+ logic reset_en_en_0_wd;
+ logic reset_en_en_1_qs;
+ logic reset_en_en_1_wd;
+ logic reset_status_val_0_qs;
+ logic reset_status_val_1_qs;
+ logic escalate_reset_status_qs;
+ logic wake_info_capture_dis_we;
+ logic wake_info_capture_dis_qs;
+ logic wake_info_capture_dis_wd;
+ logic wake_info_re;
+ logic wake_info_we;
+ logic [5:0] wake_info_reasons_qs;
+ logic [5:0] wake_info_reasons_wd;
+ logic wake_info_fall_through_qs;
+ logic wake_info_fall_through_wd;
+ logic wake_info_abort_qs;
+ logic wake_info_abort_wd;
+ logic fault_status_reg_intg_err_qs;
+ logic fault_status_esc_timeout_qs;
+ logic fault_status_main_pd_glitch_qs;
+ // Define register CDC handling.
+ // CDC handling is done on a per-reg instead of per-field boundary.
+
+ // Register instances
+ // R[intr_state]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.de),
+ .d (hw2reg.intr_state.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ logic intr_test_qe;
+ logic [0:0] intr_test_flds_we;
+ assign intr_test_qe = &intr_test_flds_we;
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[0]),
+ .q (reg2hw.intr_test.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.qe = intr_test_qe;
+
+
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [0:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.qe = alert_test_qe;
+
+
+ // R[ctrl_cfg_regwen]: V(True)
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_ctrl_cfg_regwen (
+ .re (ctrl_cfg_regwen_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.ctrl_cfg_regwen.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (ctrl_cfg_regwen_qs)
+ );
+
+
+ // R[control]: V(False)
+ // Create REGWEN-gated WE signal
+ logic control_gated_we;
+ assign control_gated_we = control_we & ctrl_cfg_regwen_qs;
+ // F[low_power_hint]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_low_power_hint (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_low_power_hint_wd),
+
+ // from internal hardware
+ .de (hw2reg.control.low_power_hint.de),
+ .d (hw2reg.control.low_power_hint.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.low_power_hint.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_low_power_hint_qs)
+ );
+
+ // F[core_clk_en]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_core_clk_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_core_clk_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.core_clk_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_core_clk_en_qs)
+ );
+
+ // F[io_clk_en]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_io_clk_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_io_clk_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.io_clk_en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_io_clk_en_qs)
+ );
+
+ // F[usb_clk_en_lp]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_control_usb_clk_en_lp (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_usb_clk_en_lp_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.usb_clk_en_lp.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_usb_clk_en_lp_qs)
+ );
+
+ // F[usb_clk_en_active]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_control_usb_clk_en_active (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_usb_clk_en_active_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.usb_clk_en_active.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_usb_clk_en_active_qs)
+ );
+
+ // F[main_pd_n]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_control_main_pd_n (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (control_gated_we),
+ .wd (control_main_pd_n_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.control.main_pd_n.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (control_main_pd_n_qs)
+ );
+
+
+ // R[cfg_cdc_sync]: V(False)
+ logic cfg_cdc_sync_qe;
+ logic [0:0] cfg_cdc_sync_flds_we;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_cfg_cdc_sync0_qe (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .d_i(&cfg_cdc_sync_flds_we),
+ .q_o(cfg_cdc_sync_qe)
+ );
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_cfg_cdc_sync (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (cfg_cdc_sync_we),
+ .wd (cfg_cdc_sync_wd),
+
+ // from internal hardware
+ .de (hw2reg.cfg_cdc_sync.de),
+ .d (hw2reg.cfg_cdc_sync.d),
+
+ // to internal hardware
+ .qe (cfg_cdc_sync_flds_we[0]),
+ .q (reg2hw.cfg_cdc_sync.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (cfg_cdc_sync_qs)
+ );
+ assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe;
+
+
+ // R[wakeup_en_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_wakeup_en_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_regwen_we),
+ .wd (wakeup_en_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg wakeup_en
+ // R[wakeup_en]: V(False)
+ // Create REGWEN-gated WE signal
+ logic wakeup_en_gated_we;
+ assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs;
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_0_qs)
+ );
+
+ // F[en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_1_qs)
+ );
+
+ // F[en_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_2_qs)
+ );
+
+ // F[en_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_3_qs)
+ );
+
+ // F[en_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_4_qs)
+ );
+
+ // F[en_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wakeup_en_gated_we),
+ .wd (wakeup_en_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wakeup_en_en_5_qs)
+ );
+
+
+ // Subregister 0 of Multireg wake_status
+ // R[wake_status]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[0].de),
+ .d (hw2reg.wake_status[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[1].de),
+ .d (hw2reg.wake_status[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[2].de),
+ .d (hw2reg.wake_status[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[3].de),
+ .d (hw2reg.wake_status[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[4].de),
+ .d (hw2reg.wake_status[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_wake_status_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.wake_status[5].de),
+ .d (hw2reg.wake_status[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_status_val_5_qs)
+ );
+
+
+ // R[reset_en_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_reset_en_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (reset_en_regwen_we),
+ .wd (reset_en_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_en_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg reset_en
+ // R[reset_en]: V(False)
+ // Create REGWEN-gated WE signal
+ logic reset_en_gated_we;
+ assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs;
+ // F[en_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_reset_en_en_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (reset_en_gated_we),
+ .wd (reset_en_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.reset_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_en_en_0_qs)
+ );
+
+ // F[en_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_reset_en_en_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (reset_en_gated_we),
+ .wd (reset_en_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.reset_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_en_en_1_qs)
+ );
+
+
+ // Subregister 0 of Multireg reset_status
+ // R[reset_status]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_reset_status_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.reset_status[0].de),
+ .d (hw2reg.reset_status[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_status_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_reset_status_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.reset_status[1].de),
+ .d (hw2reg.reset_status[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_status_val_1_qs)
+ );
+
+
+ // R[escalate_reset_status]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_escalate_reset_status (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.escalate_reset_status.de),
+ .d (hw2reg.escalate_reset_status.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (escalate_reset_status_qs)
+ );
+
+
+ // R[wake_info_capture_dis]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_wake_info_capture_dis (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (wake_info_capture_dis_we),
+ .wd (wake_info_capture_dis_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wake_info_capture_dis.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (wake_info_capture_dis_qs)
+ );
+
+
+ // R[wake_info]: V(True)
+ logic wake_info_qe;
+ logic [2:0] wake_info_flds_we;
+ assign wake_info_qe = &wake_info_flds_we;
+ // F[reasons]: 5:0
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_wake_info_reasons (
+ .re (wake_info_re),
+ .we (wake_info_we),
+ .wd (wake_info_reasons_wd),
+ .d (hw2reg.wake_info.reasons.d),
+ .qre (),
+ .qe (wake_info_flds_we[0]),
+ .q (reg2hw.wake_info.reasons.q),
+ .ds (),
+ .qs (wake_info_reasons_qs)
+ );
+ assign reg2hw.wake_info.reasons.qe = wake_info_qe;
+
+ // F[fall_through]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_wake_info_fall_through (
+ .re (wake_info_re),
+ .we (wake_info_we),
+ .wd (wake_info_fall_through_wd),
+ .d (hw2reg.wake_info.fall_through.d),
+ .qre (),
+ .qe (wake_info_flds_we[1]),
+ .q (reg2hw.wake_info.fall_through.q),
+ .ds (),
+ .qs (wake_info_fall_through_qs)
+ );
+ assign reg2hw.wake_info.fall_through.qe = wake_info_qe;
+
+ // F[abort]: 7:7
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_wake_info_abort (
+ .re (wake_info_re),
+ .we (wake_info_we),
+ .wd (wake_info_abort_wd),
+ .d (hw2reg.wake_info.abort.d),
+ .qre (),
+ .qe (wake_info_flds_we[2]),
+ .q (reg2hw.wake_info.abort.q),
+ .ds (),
+ .qs (wake_info_abort_qs)
+ );
+ assign reg2hw.wake_info.abort.qe = wake_info_qe;
+
+
+ // R[fault_status]: V(False)
+ // F[reg_intg_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_reg_intg_err (
+ // sync clock and reset required for this register
+ .clk_i (clk_lc_i),
+ .rst_ni (rst_lc_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.reg_intg_err.de),
+ .d (hw2reg.fault_status.reg_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.reg_intg_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_reg_intg_err_qs)
+ );
+
+ // F[esc_timeout]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_esc_timeout (
+ // sync clock and reset required for this register
+ .clk_i (clk_lc_i),
+ .rst_ni (rst_lc_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.esc_timeout.de),
+ .d (hw2reg.fault_status.esc_timeout.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.esc_timeout.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_esc_timeout_qs)
+ );
+
+ // F[main_pd_glitch]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fault_status_main_pd_glitch (
+ // sync clock and reset required for this register
+ .clk_i (clk_lc_i),
+ .rst_ni (rst_lc_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fault_status.main_pd_glitch.de),
+ .d (hw2reg.fault_status.main_pd_glitch.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fault_status.main_pd_glitch.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fault_status_main_pd_glitch_qs)
+ );
+
+
+
+ logic [16:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == PWRMGR_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET);
+ addr_hit[ 5] = (reg_addr == PWRMGR_CONTROL_OFFSET);
+ addr_hit[ 6] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET);
+ addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET);
+ addr_hit[ 8] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET);
+ addr_hit[ 9] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET);
+ addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET);
+ addr_hit[11] = (reg_addr == PWRMGR_RESET_EN_OFFSET);
+ addr_hit[12] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET);
+ addr_hit[13] = (reg_addr == PWRMGR_ESCALATE_RESET_STATUS_OFFSET);
+ addr_hit[14] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET);
+ addr_hit[15] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET);
+ addr_hit[16] = (reg_addr == PWRMGR_FAULT_STATUS_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(PWRMGR_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(PWRMGR_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(PWRMGR_PERMIT[16] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_wd = reg_wdata[0];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_wd = reg_wdata[0];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_wd = reg_wdata[0];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+ assign ctrl_cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
+ assign control_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign control_low_power_hint_wd = reg_wdata[0];
+
+ assign control_core_clk_en_wd = reg_wdata[4];
+
+ assign control_io_clk_en_wd = reg_wdata[5];
+
+ assign control_usb_clk_en_lp_wd = reg_wdata[6];
+
+ assign control_usb_clk_en_active_wd = reg_wdata[7];
+
+ assign control_main_pd_n_wd = reg_wdata[8];
+ assign cfg_cdc_sync_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign cfg_cdc_sync_wd = reg_wdata[0];
+ assign wakeup_en_regwen_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign wakeup_en_regwen_wd = reg_wdata[0];
+ assign wakeup_en_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign wakeup_en_en_0_wd = reg_wdata[0];
+
+ assign wakeup_en_en_1_wd = reg_wdata[1];
+
+ assign wakeup_en_en_2_wd = reg_wdata[2];
+
+ assign wakeup_en_en_3_wd = reg_wdata[3];
+
+ assign wakeup_en_en_4_wd = reg_wdata[4];
+
+ assign wakeup_en_en_5_wd = reg_wdata[5];
+ assign reset_en_regwen_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign reset_en_regwen_wd = reg_wdata[0];
+ assign reset_en_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign reset_en_en_0_wd = reg_wdata[0];
+
+ assign reset_en_en_1_wd = reg_wdata[1];
+ assign wake_info_capture_dis_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign wake_info_capture_dis_wd = reg_wdata[0];
+ assign wake_info_re = addr_hit[15] & reg_re & !reg_error;
+ assign wake_info_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign wake_info_reasons_wd = reg_wdata[5:0];
+
+ assign wake_info_fall_through_wd = reg_wdata[6];
+
+ assign wake_info_abort_wd = reg_wdata[7];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = intr_state_we;
+ reg_we_check[1] = intr_enable_we;
+ reg_we_check[2] = intr_test_we;
+ reg_we_check[3] = alert_test_we;
+ reg_we_check[4] = 1'b0;
+ reg_we_check[5] = control_gated_we;
+ reg_we_check[6] = cfg_cdc_sync_we;
+ reg_we_check[7] = wakeup_en_regwen_we;
+ reg_we_check[8] = wakeup_en_gated_we;
+ reg_we_check[9] = 1'b0;
+ reg_we_check[10] = reset_en_regwen_we;
+ reg_we_check[11] = reset_en_gated_we;
+ reg_we_check[12] = 1'b0;
+ reg_we_check[13] = 1'b0;
+ reg_we_check[14] = wake_info_capture_dis_we;
+ reg_we_check[15] = wake_info_we;
+ reg_we_check[16] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = ctrl_cfg_regwen_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = control_low_power_hint_qs;
+ reg_rdata_next[4] = control_core_clk_en_qs;
+ reg_rdata_next[5] = control_io_clk_en_qs;
+ reg_rdata_next[6] = control_usb_clk_en_lp_qs;
+ reg_rdata_next[7] = control_usb_clk_en_active_qs;
+ reg_rdata_next[8] = control_main_pd_n_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = cfg_cdc_sync_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = wakeup_en_regwen_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = wakeup_en_en_0_qs;
+ reg_rdata_next[1] = wakeup_en_en_1_qs;
+ reg_rdata_next[2] = wakeup_en_en_2_qs;
+ reg_rdata_next[3] = wakeup_en_en_3_qs;
+ reg_rdata_next[4] = wakeup_en_en_4_qs;
+ reg_rdata_next[5] = wakeup_en_en_5_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = wake_status_val_0_qs;
+ reg_rdata_next[1] = wake_status_val_1_qs;
+ reg_rdata_next[2] = wake_status_val_2_qs;
+ reg_rdata_next[3] = wake_status_val_3_qs;
+ reg_rdata_next[4] = wake_status_val_4_qs;
+ reg_rdata_next[5] = wake_status_val_5_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = reset_en_regwen_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = reset_en_en_0_qs;
+ reg_rdata_next[1] = reset_en_en_1_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = reset_status_val_0_qs;
+ reg_rdata_next[1] = reset_status_val_1_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = escalate_reset_status_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = wake_info_capture_dis_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[5:0] = wake_info_reasons_qs;
+ reg_rdata_next[6] = wake_info_fall_through_qs;
+ reg_rdata_next[7] = wake_info_abort_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = fault_status_reg_intg_err_qs;
+ reg_rdata_next[1] = fault_status_esc_timeout_qs;
+ reg_rdata_next[2] = fault_status_main_pd_glitch_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr.sv
new file mode 100644
index 0000000..2f356ee
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -0,0 +1,1780 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module is the overall reset manager wrapper
+
+`include "prim_assert.sv"
+
+
+// This top level controller is fairly hardcoded right now, but will be switched to a template
+module rstmgr
+ import rstmgr_pkg::*;
+ import rstmgr_reg_pkg::*;
+ import prim_mubi_pkg::mubi4_t;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+ parameter bit SecCheck = 1,
+ parameter int SecMaxSyncDelay = 2
+) (
+ // Primary module clocks
+ input clk_i,
+ input rst_ni,
+ input clk_aon_i,
+ input clk_io_div4_i,
+ input clk_main_i,
+ input clk_io_i,
+ input clk_io_div2_i,
+ input clk_usb_i,
+ input clk_smc_i,
+ input clk_ml_i,
+ input clk_video_i,
+ input clk_audio_i,
+ input clk_por_i,
+ input rst_por_ni,
+
+ // POR input
+ input [PowerDomains-1:0] por_n_i,
+
+ // Bus Interface
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // pwrmgr interface
+ input pwrmgr_pkg::pwr_rst_req_t pwr_i,
+ output pwrmgr_pkg::pwr_rst_rsp_t pwr_o,
+
+ // software initiated reset request
+ output mubi4_t sw_rst_req_o,
+
+ // Interface to alert handler
+ input alert_pkg::alert_crashdump_t alert_dump_i,
+
+ // Interface to cpu crash dump
+ input rv_core_ibex_pkg::cpu_crash_dump_t cpu_dump_i,
+
+ // dft bypass
+ input scan_rst_ni,
+ // SEC_CM: SCAN.INTERSIG.MUBI
+ input prim_mubi_pkg::mubi4_t scanmode_i,
+
+ // Reset asserted indications going to alert handler
+ output rstmgr_rst_en_t rst_en_o,
+
+ // reset outputs
+ output rstmgr_out_t resets_o
+
+);
+
+ import prim_mubi_pkg::MuBi4False;
+ import prim_mubi_pkg::MuBi4True;
+
+ // receive POR and stretch
+ // The por is at first stretched and synced on clk_aon
+ // The rst_ni and pok_i input will be changed once AST is integrated
+ logic [PowerDomains-1:0] rst_por_aon_n;
+
+ for (genvar i = 0; i < PowerDomains; i++) begin : gen_rst_por_aon
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] por_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_por_scanmode_sync (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(scanmode_i),
+ .mubi_o(por_scanmode)
+ );
+
+ if (i == DomainAonSel) begin : gen_rst_por_aon_normal
+ rstmgr_por u_rst_por_aon (
+ .clk_i(clk_aon_i),
+ .rst_ni(por_n_i[i]),
+ .scan_rst_ni,
+ .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])),
+ .rst_no(rst_por_aon_n[i])
+ );
+
+ // reset asserted indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_por_aon_n[i]),
+ .mubi_i(MuBi4False),
+ .mubi_o(rst_en_o.por_aon[i])
+ );
+ end else begin : gen_rst_por_domain
+ logic rst_por_aon_premux;
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_por_domain_sync (
+ .clk_i(clk_aon_i),
+ // do not release from reset if aon has not
+ .rst_ni(rst_por_aon_n[DomainAonSel] & por_n_i[i]),
+ .d_i(1'b1),
+ .q_o(rst_por_aon_premux)
+ );
+
+ prim_clock_mux2 #(
+ .NoFpgaBufG(1'b1)
+ ) u_por_domain_mux (
+ .clk0_i(rst_por_aon_premux),
+ .clk1_i(scan_rst_ni),
+ .sel_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])),
+ .clk_o(rst_por_aon_n[i])
+ );
+
+ // reset asserted indication for alert handler
+ prim_mubi4_sender #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sender (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_por_aon_n[i]),
+ .mubi_i(MuBi4False),
+ .mubi_o(rst_en_o.por_aon[i])
+ );
+ end
+ end
+ assign resets_o.rst_por_aon_n = rst_por_aon_n;
+
+ logic clk_por;
+ logic rst_por_n;
+ prim_clock_buf #(
+ .NoFpgaBuf(1'b1)
+ ) u_por_clk_buf (
+ .clk_i(clk_por_i),
+ .clk_o(clk_por)
+ );
+
+ prim_clock_buf #(
+ .NoFpgaBuf(1'b1)
+ ) u_por_rst_buf (
+ .clk_i(rst_por_ni),
+ .clk_o(rst_por_n)
+ );
+
+ ////////////////////////////////////////////////////
+ // Register Interface //
+ ////////////////////////////////////////////////////
+
+ rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw;
+ rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg;
+
+ logic reg_intg_err;
+ // SEC_CM: BUS.INTEGRITY
+ // SEC_CM: SW_RST.CONFIG.REGWEN, DUMP_CTRL.CONFIG.REGWEN
+ rstmgr_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .clk_por_i (clk_por),
+ .rst_por_ni (rst_por_n),
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .intg_err_o(reg_intg_err),
+ .devmode_i(1'b1)
+ );
+
+
+ ////////////////////////////////////////////////////
+ // Errors //
+ ////////////////////////////////////////////////////
+
+ // consistency check errors
+ logic [34:0][PowerDomains-1:0] cnsty_chk_errs;
+ logic [34:0][PowerDomains-1:0] shadow_cnsty_chk_errs;
+
+ // consistency sparse fsm errors
+ logic [34:0][PowerDomains-1:0] fsm_errs;
+ logic [34:0][PowerDomains-1:0] shadow_fsm_errs;
+
+ assign hw2reg.err_code.reg_intg_err.d = 1'b1;
+ assign hw2reg.err_code.reg_intg_err.de = reg_intg_err;
+ assign hw2reg.err_code.reset_consistency_err.d = 1'b1;
+ assign hw2reg.err_code.reset_consistency_err.de = |cnsty_chk_errs ||
+ |shadow_cnsty_chk_errs;
+ assign hw2reg.err_code.fsm_err.d = 1'b1;
+ assign hw2reg.err_code.fsm_err.de = |fsm_errs || |shadow_fsm_errs;
+ ////////////////////////////////////////////////////
+ // Alerts //
+ ////////////////////////////////////////////////////
+ logic [NumAlerts-1:0] alert_test, alerts;
+
+ // All of these are fatal alerts
+ assign alerts[0] = reg2hw.err_code.reg_intg_err.q |
+ (|reg2hw.err_code.fsm_err.q);
+
+ assign alerts[1] = reg2hw.err_code.reset_consistency_err.q;
+
+ assign alert_test = {
+ reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe,
+ reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ ////////////////////////////////////////////////////
+ // Source resets in the system //
+ // These are hardcoded and not directly used. //
+ // Instead they act as async reset roots. //
+ ////////////////////////////////////////////////////
+
+ // The two source reset modules are chained together. The output of one is fed into the
+ // the second. This ensures that if upstream resets for any reason, the associated downstream
+ // reset will also reset.
+
+ logic [PowerDomains-1:0] rst_lc_src_n;
+ logic [PowerDomains-1:0] rst_sys_src_n;
+
+ // Declared as size 1 packed array to avoid FPV warning.
+ prim_mubi_pkg::mubi4_t [0:0] rst_ctrl_scanmode;
+ prim_mubi4_sync #(
+ .NumCopies(1),
+ .AsyncOn(0)
+ ) u_ctrl_scanmode_sync (
+ .clk_i (clk_por),
+ .rst_ni (rst_por_n),
+ .mubi_i(scanmode_i),
+ .mubi_o(rst_ctrl_scanmode)
+ );
+
+ // lc reset sources
+ rstmgr_ctrl u_lc_src (
+ .clk_i (clk_por),
+ .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])),
+ .scan_rst_ni,
+ .rst_req_i(pwr_i.rst_lc_req),
+ .rst_parent_ni(rst_por_aon_n),
+ .rst_no(rst_lc_src_n)
+ );
+
+ // sys reset sources
+ rstmgr_ctrl u_sys_src (
+ .clk_i (clk_por),
+ .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])),
+ .scan_rst_ni,
+ .rst_req_i(pwr_i.rst_sys_req),
+ .rst_parent_ni(rst_por_aon_n),
+ .rst_no(rst_sys_src_n)
+ );
+
+ assign pwr_o.rst_lc_src_n = rst_lc_src_n;
+ assign pwr_o.rst_sys_src_n = rst_sys_src_n;
+
+
+ ////////////////////////////////////////////////////
+ // leaf reset in the system //
+ // These should all be generated //
+ ////////////////////////////////////////////////////
+ // To simplify generation, each reset generates all associated power domain outputs.
+ // If a reset does not support a particular power domain, that reset is always hard-wired to 0.
+
+ // Generating resets for por
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[0][DomainAonSel]),
+ .fsm_err_o(fsm_errs[0][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorFsmCheck_A,
+ u_daon_por.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[0][Domain0Sel] = '0;
+ assign fsm_errs[0][Domain0Sel] = '0;
+ assign rst_en_o.por[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[0] = '0;
+ assign shadow_fsm_errs[0] = '0;
+
+ // Generating resets for por_io
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_io (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_io[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_io_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[1][DomainAonSel]),
+ .fsm_err_o(fsm_errs[1][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_io_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorIoFsmCheck_A,
+ u_daon_por_io.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_io_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[1][Domain0Sel] = '0;
+ assign fsm_errs[1][Domain0Sel] = '0;
+ assign rst_en_o.por_io[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[1] = '0;
+ assign shadow_fsm_errs[1] = '0;
+
+ // Generating resets for por_io_div2
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_io_div2 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div2_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_io_div2[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_io_div2_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[2][DomainAonSel]),
+ .fsm_err_o(fsm_errs[2][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_io_div2_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorIoDiv2FsmCheck_A,
+ u_daon_por_io_div2.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_io_div2_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[2][Domain0Sel] = '0;
+ assign fsm_errs[2][Domain0Sel] = '0;
+ assign rst_en_o.por_io_div2[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[2] = '0;
+ assign shadow_fsm_errs[2] = '0;
+
+ // Generating resets for por_io_div4
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_io_div4 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_io_div4[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_io_div4_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[3][DomainAonSel]),
+ .fsm_err_o(fsm_errs[3][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_io_div4_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorIoDiv4FsmCheck_A,
+ u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[3][Domain0Sel] = '0;
+ assign fsm_errs[3][Domain0Sel] = '0;
+ assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[3] = '0;
+ assign shadow_fsm_errs[3] = '0;
+
+ // Generating resets for por_usb
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_usb (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_usb_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_usb[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_usb_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[4][DomainAonSel]),
+ .fsm_err_o(fsm_errs[4][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_usb_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorUsbFsmCheck_A,
+ u_daon_por_usb.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_usb_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[4][Domain0Sel] = '0;
+ assign fsm_errs[4][Domain0Sel] = '0;
+ assign rst_en_o.por_usb[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[4] = '0;
+ assign shadow_fsm_errs[4] = '0;
+
+ // Generating resets for por_smc
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_smc (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_smc_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_smc[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_smc_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[5][DomainAonSel]),
+ .fsm_err_o(fsm_errs[5][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_smc_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorSmcFsmCheck_A,
+ u_daon_por_smc.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_smc_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[5][Domain0Sel] = '0;
+ assign fsm_errs[5][Domain0Sel] = '0;
+ assign rst_en_o.por_smc[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[5] = '0;
+ assign shadow_fsm_errs[5] = '0;
+
+ // Generating resets for por_ml
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_ml (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_ml_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_ml[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_ml_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[6][DomainAonSel]),
+ .fsm_err_o(fsm_errs[6][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_ml_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorMlFsmCheck_A,
+ u_daon_por_ml.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_ml_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[6][Domain0Sel] = '0;
+ assign fsm_errs[6][Domain0Sel] = '0;
+ assign rst_en_o.por_ml[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[6] = '0;
+ assign shadow_fsm_errs[6] = '0;
+
+ // Generating resets for por_video
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_video (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_video_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_video[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_video_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[7][DomainAonSel]),
+ .fsm_err_o(fsm_errs[7][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_video_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorVideoFsmCheck_A,
+ u_daon_por_video.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_video_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[7][Domain0Sel] = '0;
+ assign fsm_errs[7][Domain0Sel] = '0;
+ assign rst_en_o.por_video[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[7] = '0;
+ assign shadow_fsm_errs[7] = '0;
+
+ // Generating resets for por_audio
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_por_audio (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_audio_i),
+ .parent_rst_ni(rst_por_aon_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.por_audio[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_por_audio_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[8][DomainAonSel]),
+ .fsm_err_o(fsm_errs[8][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_por_audio_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonPorAudioFsmCheck_A,
+ u_daon_por_audio.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_por_audio_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[8][Domain0Sel] = '0;
+ assign fsm_errs[8][Domain0Sel] = '0;
+ assign rst_en_o.por_audio[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[8] = '0;
+ assign shadow_fsm_errs[8] = '0;
+
+ // Generating resets for lc
+ // Power Domains: ['0', 'Aon']
+ // Shadowed: True
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[9][DomainAonSel]),
+ .fsm_err_o(fsm_errs[9][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcFsmCheck_A,
+ u_daon_lc.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[9][Domain0Sel]),
+ .fsm_err_o(fsm_errs[9][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_lc_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0LcFsmCheck_A,
+ u_d0_lc.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_shadowed (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_shadowed[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_shadowed_n[DomainAonSel]),
+ .err_o(shadow_cnsty_chk_errs[9][DomainAonSel]),
+ .fsm_err_o(shadow_fsm_errs[9][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_shadowed_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcShadowedFsmCheck_A,
+ u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc_shadowed (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_shadowed[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_shadowed_n[Domain0Sel]),
+ .err_o(shadow_cnsty_chk_errs[9][Domain0Sel]),
+ .fsm_err_o(shadow_fsm_errs[9][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_lc_shadowed_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0LcShadowedFsmCheck_A,
+ u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+
+ // Generating resets for lc_aon
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_aon (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_aon_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_aon[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_aon_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[10][DomainAonSel]),
+ .fsm_err_o(fsm_errs[10][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_aon_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcAonFsmCheck_A,
+ u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_aon_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[10][Domain0Sel] = '0;
+ assign fsm_errs[10][Domain0Sel] = '0;
+ assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[10] = '0;
+ assign shadow_fsm_errs[10] = '0;
+
+ // Generating resets for lc_io
+ // Power Domains: ['Aon', '0']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_io (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_io_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[11][DomainAonSel]),
+ .fsm_err_o(fsm_errs[11][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_io_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcIoFsmCheck_A,
+ u_daon_lc_io.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc_io (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_io_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[11][Domain0Sel]),
+ .fsm_err_o(fsm_errs[11][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_lc_io_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0LcIoFsmCheck_A,
+ u_d0_lc_io.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[11] = '0;
+ assign shadow_fsm_errs[11] = '0;
+
+ // Generating resets for lc_io_div2
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_io_div2 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div2_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io_div2[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_io_div2_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[12][DomainAonSel]),
+ .fsm_err_o(fsm_errs[12][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_io_div2_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcIoDiv2FsmCheck_A,
+ u_daon_lc_io_div2.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_io_div2_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[12][Domain0Sel] = '0;
+ assign fsm_errs[12][Domain0Sel] = '0;
+ assign rst_en_o.lc_io_div2[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[12] = '0;
+ assign shadow_fsm_errs[12] = '0;
+
+ // Generating resets for lc_io_div4
+ // Power Domains: ['0', 'Aon']
+ // Shadowed: True
+ rstmgr_leaf_rst #(
+ .SecCheck(0),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_io_div4 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io_div4[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_io_div4_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[13][DomainAonSel]),
+ .fsm_err_o(fsm_errs[13][DomainAonSel])
+ );
+
+ rstmgr_leaf_rst #(
+ .SecCheck(0),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc_io_div4 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io_div4[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_io_div4_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[13][Domain0Sel]),
+ .fsm_err_o(fsm_errs[13][Domain0Sel])
+ );
+
+ rstmgr_leaf_rst #(
+ .SecCheck(0),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_io_div4_shadowed (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io_div4_shadowed[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[DomainAonSel]),
+ .err_o(shadow_cnsty_chk_errs[13][DomainAonSel]),
+ .fsm_err_o(shadow_fsm_errs[13][DomainAonSel])
+ );
+
+ rstmgr_leaf_rst #(
+ .SecCheck(0),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc_io_div4_shadowed (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_io_div4_shadowed[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[Domain0Sel]),
+ .err_o(shadow_cnsty_chk_errs[13][Domain0Sel]),
+ .fsm_err_o(shadow_fsm_errs[13][Domain0Sel])
+ );
+
+
+ // Generating resets for lc_usb
+ // Power Domains: ['Aon', '0']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_usb (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_usb_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_usb[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_usb_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[14][DomainAonSel]),
+ .fsm_err_o(fsm_errs[14][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_usb_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcUsbFsmCheck_A,
+ u_daon_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_lc_usb (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_usb_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_usb[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_lc_usb_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[14][Domain0Sel]),
+ .fsm_err_o(fsm_errs[14][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_lc_usb_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0LcUsbFsmCheck_A,
+ u_d0_lc_usb.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[14] = '0;
+ assign shadow_fsm_errs[14] = '0;
+
+ // Generating resets for lc_smc
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_smc (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_smc_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_smc[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_smc_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[15][DomainAonSel]),
+ .fsm_err_o(fsm_errs[15][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_smc_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcSmcFsmCheck_A,
+ u_daon_lc_smc.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_smc_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[15][Domain0Sel] = '0;
+ assign fsm_errs[15][Domain0Sel] = '0;
+ assign rst_en_o.lc_smc[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[15] = '0;
+ assign shadow_fsm_errs[15] = '0;
+
+ // Generating resets for lc_ml
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_ml (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_ml_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_ml[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_ml_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[16][DomainAonSel]),
+ .fsm_err_o(fsm_errs[16][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_ml_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcMlFsmCheck_A,
+ u_daon_lc_ml.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_ml_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[16][Domain0Sel] = '0;
+ assign fsm_errs[16][Domain0Sel] = '0;
+ assign rst_en_o.lc_ml[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[16] = '0;
+ assign shadow_fsm_errs[16] = '0;
+
+ // Generating resets for lc_video
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_video (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_video_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_video[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_video_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[17][DomainAonSel]),
+ .fsm_err_o(fsm_errs[17][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_video_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcVideoFsmCheck_A,
+ u_daon_lc_video.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_video_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[17][Domain0Sel] = '0;
+ assign fsm_errs[17][Domain0Sel] = '0;
+ assign rst_en_o.lc_video[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[17] = '0;
+ assign shadow_fsm_errs[17] = '0;
+
+ // Generating resets for lc_audio
+ // Power Domains: ['Aon']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_lc_audio (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_audio_i),
+ .parent_rst_ni(rst_lc_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.lc_audio[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_lc_audio_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[18][DomainAonSel]),
+ .fsm_err_o(fsm_errs[18][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_lc_audio_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonLcAudioFsmCheck_A,
+ u_daon_lc_audio.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign resets_o.rst_lc_audio_n[Domain0Sel] = '0;
+ assign cnsty_chk_errs[18][Domain0Sel] = '0;
+ assign fsm_errs[18][Domain0Sel] = '0;
+ assign rst_en_o.lc_audio[Domain0Sel] = MuBi4True;
+ assign shadow_cnsty_chk_errs[18] = '0;
+ assign shadow_fsm_errs[18] = '0;
+
+ // Generating resets for sys
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_sys_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[19][DomainAonSel] = '0;
+ assign fsm_errs[19][DomainAonSel] = '0;
+ assign rst_en_o.sys[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_sys (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_main_i),
+ .parent_rst_ni(rst_sys_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.sys[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_sys_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[19][Domain0Sel]),
+ .fsm_err_o(fsm_errs[19][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_sys_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SysFsmCheck_A,
+ u_d0_sys.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[19] = '0;
+ assign shadow_fsm_errs[19] = '0;
+
+ // Generating resets for sys_io_div4
+ // Power Domains: ['Aon', '0']
+ // Shadowed: False
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_daon_sys_io_div4 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_sys_src_n[DomainAonSel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.sys_io_div4[DomainAonSel]),
+ .leaf_rst_o(resets_o.rst_sys_io_div4_n[DomainAonSel]),
+ .err_o(cnsty_chk_errs[20][DomainAonSel]),
+ .fsm_err_o(fsm_errs[20][DomainAonSel])
+ );
+
+ if (SecCheck) begin : gen_daon_sys_io_div4_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ DAonSysIoDiv4FsmCheck_A,
+ u_daon_sys_io_div4.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b0)
+ ) u_d0_sys_io_div4 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_sys_src_n[Domain0Sel]),
+ .sw_rst_req_ni(1'b1),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.sys_io_div4[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_sys_io_div4_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[20][Domain0Sel]),
+ .fsm_err_o(fsm_errs[20][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_sys_io_div4_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SysIoDiv4FsmCheck_A,
+ u_d0_sys_io_div4.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[20] = '0;
+ assign shadow_fsm_errs[20] = '0;
+
+ // Generating resets for spi_device
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_spi_device_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[21][DomainAonSel] = '0;
+ assign fsm_errs[21][DomainAonSel] = '0;
+ assign rst_en_o.spi_device[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_spi_device (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_DEVICE].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.spi_device[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_spi_device_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[21][Domain0Sel]),
+ .fsm_err_o(fsm_errs[21][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_spi_device_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SpiDeviceFsmCheck_A,
+ u_d0_spi_device.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[21] = '0;
+ assign shadow_fsm_errs[21] = '0;
+
+ // Generating resets for spi_host0
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_spi_host0_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[22][DomainAonSel] = '0;
+ assign fsm_errs[22][DomainAonSel] = '0;
+ assign rst_en_o.spi_host0[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_spi_host0 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST0].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.spi_host0[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_spi_host0_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[22][Domain0Sel]),
+ .fsm_err_o(fsm_errs[22][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_spi_host0_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SpiHost0FsmCheck_A,
+ u_d0_spi_host0.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[22] = '0;
+ assign shadow_fsm_errs[22] = '0;
+
+ // Generating resets for spi_host1
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_spi_host1_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[23][DomainAonSel] = '0;
+ assign fsm_errs[23][DomainAonSel] = '0;
+ assign rst_en_o.spi_host1[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_spi_host1 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST1].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.spi_host1[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_spi_host1_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[23][Domain0Sel]),
+ .fsm_err_o(fsm_errs[23][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_spi_host1_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SpiHost1FsmCheck_A,
+ u_d0_spi_host1.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[23] = '0;
+ assign shadow_fsm_errs[23] = '0;
+
+ // Generating resets for spi_host2
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_spi_host2_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[24][DomainAonSel] = '0;
+ assign fsm_errs[24][DomainAonSel] = '0;
+ assign rst_en_o.spi_host2[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_spi_host2 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST2].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.spi_host2[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_spi_host2_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[24][Domain0Sel]),
+ .fsm_err_o(fsm_errs[24][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_spi_host2_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SpiHost2FsmCheck_A,
+ u_d0_spi_host2.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[24] = '0;
+ assign shadow_fsm_errs[24] = '0;
+
+ // Generating resets for usb
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_usb_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[25][DomainAonSel] = '0;
+ assign fsm_errs[25][DomainAonSel] = '0;
+ assign rst_en_o.usb[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_usb (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_usb_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[USB].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.usb[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_usb_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[25][Domain0Sel]),
+ .fsm_err_o(fsm_errs[25][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_usb_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0UsbFsmCheck_A,
+ u_d0_usb.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[25] = '0;
+ assign shadow_fsm_errs[25] = '0;
+
+ // Generating resets for usb_aon
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_usb_aon_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[26][DomainAonSel] = '0;
+ assign fsm_errs[26][DomainAonSel] = '0;
+ assign rst_en_o.usb_aon[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_usb_aon (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_aon_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[USB_AON].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.usb_aon[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_usb_aon_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[26][Domain0Sel]),
+ .fsm_err_o(fsm_errs[26][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_usb_aon_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0UsbAonFsmCheck_A,
+ u_d0_usb_aon.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[26] = '0;
+ assign shadow_fsm_errs[26] = '0;
+
+ // Generating resets for i2c0
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_i2c0_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[27][DomainAonSel] = '0;
+ assign fsm_errs[27][DomainAonSel] = '0;
+ assign rst_en_o.i2c0[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_i2c0 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C0].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.i2c0[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_i2c0_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[27][Domain0Sel]),
+ .fsm_err_o(fsm_errs[27][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_i2c0_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0I2c0FsmCheck_A,
+ u_d0_i2c0.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[27] = '0;
+ assign shadow_fsm_errs[27] = '0;
+
+ // Generating resets for i2c1
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_i2c1_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[28][DomainAonSel] = '0;
+ assign fsm_errs[28][DomainAonSel] = '0;
+ assign rst_en_o.i2c1[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_i2c1 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C1].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.i2c1[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_i2c1_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[28][Domain0Sel]),
+ .fsm_err_o(fsm_errs[28][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_i2c1_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0I2c1FsmCheck_A,
+ u_d0_i2c1.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[28] = '0;
+ assign shadow_fsm_errs[28] = '0;
+
+ // Generating resets for i2c2
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_i2c2_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[29][DomainAonSel] = '0;
+ assign fsm_errs[29][DomainAonSel] = '0;
+ assign rst_en_o.i2c2[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_i2c2 (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C2].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.i2c2[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_i2c2_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[29][Domain0Sel]),
+ .fsm_err_o(fsm_errs[29][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_i2c2_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0I2c2FsmCheck_A,
+ u_d0_i2c2.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[29] = '0;
+ assign shadow_fsm_errs[29] = '0;
+
+ // Generating resets for smc
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_smc_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[30][DomainAonSel] = '0;
+ assign fsm_errs[30][DomainAonSel] = '0;
+ assign rst_en_o.smc[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_smc (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_smc_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SMC].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.smc[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_smc_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[30][Domain0Sel]),
+ .fsm_err_o(fsm_errs[30][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_smc_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0SmcFsmCheck_A,
+ u_d0_smc.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[30] = '0;
+ assign shadow_fsm_errs[30] = '0;
+
+ // Generating resets for ml
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_ml_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[31][DomainAonSel] = '0;
+ assign fsm_errs[31][DomainAonSel] = '0;
+ assign rst_en_o.ml[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_ml (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_ml_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[ML].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.ml[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_ml_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[31][Domain0Sel]),
+ .fsm_err_o(fsm_errs[31][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_ml_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0MlFsmCheck_A,
+ u_d0_ml.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[31] = '0;
+ assign shadow_fsm_errs[31] = '0;
+
+ // Generating resets for cam_i2c
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_cam_i2c_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[32][DomainAonSel] = '0;
+ assign fsm_errs[32][DomainAonSel] = '0;
+ assign rst_en_o.cam_i2c[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_cam_i2c (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_io_div4_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[CAM_I2C].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.cam_i2c[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_cam_i2c_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[32][Domain0Sel]),
+ .fsm_err_o(fsm_errs[32][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_cam_i2c_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0CamI2cFsmCheck_A,
+ u_d0_cam_i2c.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[32] = '0;
+ assign shadow_fsm_errs[32] = '0;
+
+ // Generating resets for video
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_video_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[33][DomainAonSel] = '0;
+ assign fsm_errs[33][DomainAonSel] = '0;
+ assign rst_en_o.video[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_video (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_video_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[VIDEO].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.video[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_video_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[33][Domain0Sel]),
+ .fsm_err_o(fsm_errs[33][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_video_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0VideoFsmCheck_A,
+ u_d0_video.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[33] = '0;
+ assign shadow_fsm_errs[33] = '0;
+
+ // Generating resets for audio
+ // Power Domains: ['0']
+ // Shadowed: False
+ assign resets_o.rst_audio_n[DomainAonSel] = '0;
+ assign cnsty_chk_errs[34][DomainAonSel] = '0;
+ assign fsm_errs[34][DomainAonSel] = '0;
+ assign rst_en_o.audio[DomainAonSel] = MuBi4True;
+ rstmgr_leaf_rst #(
+ .SecCheck(SecCheck),
+ .SecMaxSyncDelay(SecMaxSyncDelay),
+ .SwRstReq(1'b1)
+ ) u_d0_audio (
+ .clk_i,
+ .rst_ni,
+ .leaf_clk_i(clk_audio_i),
+ .parent_rst_ni(rst_lc_src_n[Domain0Sel]),
+ .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[AUDIO].q),
+ .scan_rst_ni,
+ .scanmode_i,
+ .rst_en_o(rst_en_o.audio[Domain0Sel]),
+ .leaf_rst_o(resets_o.rst_audio_n[Domain0Sel]),
+ .err_o(cnsty_chk_errs[34][Domain0Sel]),
+ .fsm_err_o(fsm_errs[34][Domain0Sel])
+ );
+
+ if (SecCheck) begin : gen_d0_audio_assert
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(
+ D0AudioFsmCheck_A,
+ u_d0_audio.gen_rst_chk.u_rst_chk.u_state_regs,
+ alert_tx_o[0])
+ end
+ assign shadow_cnsty_chk_errs[34] = '0;
+ assign shadow_fsm_errs[34] = '0;
+
+
+ ////////////////////////////////////////////////////
+ // Reset info construction //
+ ////////////////////////////////////////////////////
+
+ logic rst_hw_req;
+ logic rst_low_power;
+ logic pwrmgr_rst_req;
+
+ // there is a valid reset request from pwrmgr
+ assign pwrmgr_rst_req = |pwr_i.rst_lc_req || |pwr_i.rst_sys_req;
+
+ // a reset reason is only valid if the related processing element is also reset.
+ // In the future, if ever there are multiple processing elements, this code here
+ // must be updated to account for each individual core.
+ assign rst_hw_req = pwrmgr_rst_req &
+ (pwr_i.reset_cause == pwrmgr_pkg::HwReq);
+ assign rst_low_power = pwrmgr_rst_req &
+ (pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry);
+
+ // software initiated reset request
+ assign sw_rst_req_o = prim_mubi_pkg::mubi4_t'(reg2hw.reset_req.q);
+
+ // when pwrmgr reset request is received (reset is imminent), clear software
+ // request so we are not in an infinite reset loop.
+ assign hw2reg.reset_req.de = pwrmgr_rst_req;
+ assign hw2reg.reset_req.d = prim_mubi_pkg::MuBi4False;
+
+ // Only sw is allowed to clear a reset reason, hw is only allowed to set it.
+ assign hw2reg.reset_info.low_power_exit.d = 1'b1;
+ assign hw2reg.reset_info.low_power_exit.de = rst_low_power;
+
+ // software issued request triggers the same response as hardware, although it is
+ // accounted for differently.
+ assign hw2reg.reset_info.sw_reset.d = prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_o) |
+ reg2hw.reset_info.sw_reset.q;
+ assign hw2reg.reset_info.sw_reset.de = rst_hw_req;
+
+ // HW reset requests most likely will be multi-bit, so OR in whatever reasons
+ // that are already set.
+ assign hw2reg.reset_info.hw_req.d = pwr_i.rstreqs |
+ reg2hw.reset_info.hw_req.q;
+ assign hw2reg.reset_info.hw_req.de = rst_hw_req;
+
+ ////////////////////////////////////////////////////
+ // Crash info capture //
+ ////////////////////////////////////////////////////
+
+ logic dump_capture;
+ assign dump_capture = rst_hw_req | rst_low_power;
+
+ // halt dump capture once we hit particular conditions
+ logic dump_capture_halt;
+ assign dump_capture_halt = rst_hw_req;
+
+ rstmgr_crash_info #(
+ .CrashDumpWidth($bits(alert_pkg::alert_crashdump_t))
+ ) u_alert_info (
+ .clk_i(clk_por_i),
+ .rst_ni(rst_por_ni),
+ .dump_i(alert_dump_i),
+ .dump_capture_i(dump_capture & reg2hw.alert_info_ctrl.en.q),
+ .slot_sel_i(reg2hw.alert_info_ctrl.index.q),
+ .slots_cnt_o(hw2reg.alert_info_attr.d),
+ .slot_o(hw2reg.alert_info.d)
+ );
+
+ rstmgr_crash_info #(
+ .CrashDumpWidth($bits(rv_core_ibex_pkg::cpu_crash_dump_t))
+ ) u_cpu_info (
+ .clk_i(clk_por_i),
+ .rst_ni(rst_por_ni),
+ .dump_i(cpu_dump_i),
+ .dump_capture_i(dump_capture & reg2hw.cpu_info_ctrl.en.q),
+ .slot_sel_i(reg2hw.cpu_info_ctrl.index.q),
+ .slots_cnt_o(hw2reg.cpu_info_attr.d),
+ .slot_o(hw2reg.cpu_info.d)
+ );
+
+ // once dump is captured, no more information is captured until
+ // re-eanbled by software.
+ assign hw2reg.alert_info_ctrl.en.d = 1'b0;
+ assign hw2reg.alert_info_ctrl.en.de = dump_capture_halt;
+ assign hw2reg.cpu_info_ctrl.en.d = 1'b0;
+ assign hw2reg.cpu_info_ctrl.en.de = dump_capture_halt;
+
+ ////////////////////////////////////////////////////
+ // Exported resets //
+ ////////////////////////////////////////////////////
+
+
+
+
+ ////////////////////////////////////////////////////
+ // Assertions //
+ ////////////////////////////////////////////////////
+
+ `ASSERT_INIT(ParameterMatch_A, NumHwResets == pwrmgr_pkg::HwResetWidth)
+
+ // when upstream resets, downstream must also reset
+
+ // output known asserts
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid )
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready )
+ `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o )
+ `ASSERT_KNOWN(PwrKnownO_A, pwr_o )
+ `ASSERT_KNOWN(ResetsKnownO_A, resets_o )
+ `ASSERT_KNOWN(RstEnKnownO_A, rst_en_o )
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
+endmodule // rstmgr
diff --git a/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
new file mode 100644
index 0000000..4bf0874
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -0,0 +1,168 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package rstmgr_pkg;
+
+ // Power domain parameters
+ parameter int PowerDomains = 2;
+ parameter int DomainAonSel = 0;
+ parameter int Domain0Sel = 1;
+
+ // Number of non-always-on domains
+ parameter int OffDomains = PowerDomains-1;
+
+ // positions of software controllable reset bits
+ parameter int SPI_DEVICE = 0;
+ parameter int SPI_HOST0 = 1;
+ parameter int SPI_HOST1 = 2;
+ parameter int SPI_HOST2 = 3;
+ parameter int USB = 4;
+ parameter int USB_AON = 5;
+ parameter int I2C0 = 6;
+ parameter int I2C1 = 7;
+ parameter int I2C2 = 8;
+ parameter int SMC = 9;
+ parameter int ML = 10;
+ parameter int CAM_I2C = 11;
+ parameter int VIDEO = 12;
+ parameter int AUDIO = 13;
+
+ // resets generated and broadcast
+ // SEC_CM: LEAF.RST.SHADOW
+ typedef struct packed {
+ logic [PowerDomains-1:0] rst_por_aon_n;
+ logic [PowerDomains-1:0] rst_por_n;
+ logic [PowerDomains-1:0] rst_por_io_n;
+ logic [PowerDomains-1:0] rst_por_io_div2_n;
+ logic [PowerDomains-1:0] rst_por_io_div4_n;
+ logic [PowerDomains-1:0] rst_por_usb_n;
+ logic [PowerDomains-1:0] rst_por_smc_n;
+ logic [PowerDomains-1:0] rst_por_ml_n;
+ logic [PowerDomains-1:0] rst_por_video_n;
+ logic [PowerDomains-1:0] rst_por_audio_n;
+ logic [PowerDomains-1:0] rst_lc_shadowed_n;
+ logic [PowerDomains-1:0] rst_lc_n;
+ logic [PowerDomains-1:0] rst_lc_aon_n;
+ logic [PowerDomains-1:0] rst_lc_io_n;
+ logic [PowerDomains-1:0] rst_lc_io_div2_n;
+ logic [PowerDomains-1:0] rst_lc_io_div4_shadowed_n;
+ logic [PowerDomains-1:0] rst_lc_io_div4_n;
+ logic [PowerDomains-1:0] rst_lc_usb_n;
+ logic [PowerDomains-1:0] rst_lc_smc_n;
+ logic [PowerDomains-1:0] rst_lc_ml_n;
+ logic [PowerDomains-1:0] rst_lc_video_n;
+ logic [PowerDomains-1:0] rst_lc_audio_n;
+ logic [PowerDomains-1:0] rst_sys_n;
+ logic [PowerDomains-1:0] rst_sys_io_div4_n;
+ logic [PowerDomains-1:0] rst_spi_device_n;
+ logic [PowerDomains-1:0] rst_spi_host0_n;
+ logic [PowerDomains-1:0] rst_spi_host1_n;
+ logic [PowerDomains-1:0] rst_spi_host2_n;
+ logic [PowerDomains-1:0] rst_usb_n;
+ logic [PowerDomains-1:0] rst_usb_aon_n;
+ logic [PowerDomains-1:0] rst_i2c0_n;
+ logic [PowerDomains-1:0] rst_i2c1_n;
+ logic [PowerDomains-1:0] rst_i2c2_n;
+ logic [PowerDomains-1:0] rst_smc_n;
+ logic [PowerDomains-1:0] rst_ml_n;
+ logic [PowerDomains-1:0] rst_cam_i2c_n;
+ logic [PowerDomains-1:0] rst_video_n;
+ logic [PowerDomains-1:0] rst_audio_n;
+ } rstmgr_out_t;
+
+ // reset indication for alert handler
+ typedef struct packed {
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_aon;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div2;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div4;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_usb;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_smc;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_ml;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_video;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_audio;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_shadowed;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_aon;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div2;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4_shadowed;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_usb;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_smc;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_ml;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_video;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_audio;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys_io_div4;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_device;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_host0;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_host1;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_host2;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] usb;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] usb_aon;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c0;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c1;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c2;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] smc;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] ml;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] cam_i2c;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] video;
+ prim_mubi_pkg::mubi4_t [PowerDomains-1:0] audio;
+ } rstmgr_rst_en_t;
+
+ parameter int NumOutputRst = 38 * PowerDomains;
+
+ // cpu reset requests and status
+ typedef struct packed {
+ logic ndmreset_req;
+ } rstmgr_cpu_t;
+
+ // exported resets
+
+ // default value for rstmgr_ast_rsp_t (for dangling ports)
+ parameter rstmgr_cpu_t RSTMGR_CPU_DEFAULT = '{
+ ndmreset_req: '0
+ };
+
+ // Enumeration for pwrmgr hw reset inputs
+ localparam int ResetWidths = $clog2(rstmgr_reg_pkg::NumTotalResets);
+ typedef enum logic [ResetWidths-1:0] {
+ ReqPeriResetIdx[0:1],
+ ReqMainPwrResetIdx,
+ ReqEscResetIdx,
+ ReqNdmResetIdx
+ } reset_req_idx_e;
+
+ // Enumeration for reset info bit idx
+ typedef enum logic [ResetWidths-1:0] {
+ InfoPorIdx,
+ InfoLowPowerExitIdx,
+ InfoSwResetIdx,
+ InfoPeriResetIdx[0:1],
+ InfoMainPwrResetIdx,
+ InfoEscResetIdx,
+ InfoNdmResetIdx
+ } reset_info_idx_e;
+
+
+endpackage // rstmgr_pkg
diff --git a/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
new file mode 100644
index 0000000..f1a8c8e
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
@@ -0,0 +1,314 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package rstmgr_reg_pkg;
+
+ // Param list
+ parameter int RdWidth = 32;
+ parameter int IdxWidth = 4;
+ parameter int NumHwResets = 5;
+ parameter int NumSwResets = 14;
+ parameter int NumTotalResets = 8;
+ parameter int NumAlerts = 2;
+
+ // Address widths within the block
+ parameter int BlockAw = 8;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_fault;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_cnsty_fault;
+ } rstmgr_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic [3:0] q;
+ } rstmgr_reg2hw_reset_req_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } sw_reset;
+ struct packed {
+ logic [4:0] q;
+ } hw_req;
+ } rstmgr_reg2hw_reset_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } index;
+ } rstmgr_reg2hw_alert_info_ctrl_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic [3:0] q;
+ } index;
+ } rstmgr_reg2hw_cpu_info_ctrl_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } reg_intg_err;
+ struct packed {
+ logic q;
+ } reset_consistency_err;
+ struct packed {
+ logic q;
+ } fsm_err;
+ } rstmgr_reg2hw_err_code_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ logic de;
+ } rstmgr_hw2reg_reset_req_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } low_power_exit;
+ struct packed {
+ logic d;
+ logic de;
+ } sw_reset;
+ struct packed {
+ logic [4:0] d;
+ logic de;
+ } hw_req;
+ } rstmgr_hw2reg_reset_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } en;
+ } rstmgr_hw2reg_alert_info_ctrl_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ } rstmgr_hw2reg_alert_info_attr_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } rstmgr_hw2reg_alert_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } en;
+ } rstmgr_hw2reg_cpu_info_ctrl_reg_t;
+
+ typedef struct packed {
+ logic [3:0] d;
+ } rstmgr_hw2reg_cpu_info_attr_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } rstmgr_hw2reg_cpu_info_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } reg_intg_err;
+ struct packed {
+ logic d;
+ logic de;
+ } reset_consistency_err;
+ struct packed {
+ logic d;
+ logic de;
+ } fsm_err;
+ } rstmgr_hw2reg_err_code_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ rstmgr_reg2hw_alert_test_reg_t alert_test; // [40:37]
+ rstmgr_reg2hw_reset_req_reg_t reset_req; // [36:33]
+ rstmgr_reg2hw_reset_info_reg_t reset_info; // [32:27]
+ rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [26:22]
+ rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [21:17]
+ rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [13:0] sw_rst_ctrl_n; // [16:3]
+ rstmgr_reg2hw_err_code_reg_t err_code; // [2:0]
+ } rstmgr_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ rstmgr_hw2reg_reset_req_reg_t reset_req; // [96:92]
+ rstmgr_hw2reg_reset_info_reg_t reset_info; // [91:82]
+ rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [81:80]
+ rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [79:76]
+ rstmgr_hw2reg_alert_info_reg_t alert_info; // [75:44]
+ rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [43:42]
+ rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [41:38]
+ rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [37:6]
+ rstmgr_hw2reg_err_code_reg_t err_code; // [5:0]
+ } rstmgr_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] RSTMGR_ALERT_TEST_OFFSET = 8'h 0;
+ parameter logic [BlockAw-1:0] RSTMGR_RESET_REQ_OFFSET = 8'h 4;
+ parameter logic [BlockAw-1:0] RSTMGR_RESET_INFO_OFFSET = 8'h 8;
+ parameter logic [BlockAw-1:0] RSTMGR_ALERT_REGWEN_OFFSET = 8'h c;
+ parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 8'h 10;
+ parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 8'h 14;
+ parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_OFFSET = 8'h 18;
+ parameter logic [BlockAw-1:0] RSTMGR_CPU_REGWEN_OFFSET = 8'h 1c;
+ parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 8'h 20;
+ parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 8'h 24;
+ parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_OFFSET = 8'h 28;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_0_OFFSET = 8'h 2c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_1_OFFSET = 8'h 30;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_2_OFFSET = 8'h 34;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_3_OFFSET = 8'h 38;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_4_OFFSET = 8'h 3c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_5_OFFSET = 8'h 40;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_6_OFFSET = 8'h 44;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_7_OFFSET = 8'h 48;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_8_OFFSET = 8'h 4c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_9_OFFSET = 8'h 50;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_10_OFFSET = 8'h 54;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_11_OFFSET = 8'h 58;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_12_OFFSET = 8'h 5c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_13_OFFSET = 8'h 60;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 8'h 64;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 8'h 68;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 8'h 6c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_3_OFFSET = 8'h 70;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_4_OFFSET = 8'h 74;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_5_OFFSET = 8'h 78;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_6_OFFSET = 8'h 7c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_7_OFFSET = 8'h 80;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_8_OFFSET = 8'h 84;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_9_OFFSET = 8'h 88;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_10_OFFSET = 8'h 8c;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_11_OFFSET = 8'h 90;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_12_OFFSET = 8'h 94;
+ parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_13_OFFSET = 8'h 98;
+ parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 8'h 9c;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [1:0] RSTMGR_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_RESVAL = 1'h 0;
+ parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_RESVAL = 4'h 0;
+ parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0;
+ parameter logic [31:0] RSTMGR_ALERT_INFO_RESVAL = 32'h 0;
+ parameter logic [31:0] RSTMGR_ALERT_INFO_VALUE_RESVAL = 32'h 0;
+ parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_RESVAL = 4'h 0;
+ parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0;
+ parameter logic [31:0] RSTMGR_CPU_INFO_RESVAL = 32'h 0;
+ parameter logic [31:0] RSTMGR_CPU_INFO_VALUE_RESVAL = 32'h 0;
+
+ // Register index
+ typedef enum int {
+ RSTMGR_ALERT_TEST,
+ RSTMGR_RESET_REQ,
+ RSTMGR_RESET_INFO,
+ RSTMGR_ALERT_REGWEN,
+ RSTMGR_ALERT_INFO_CTRL,
+ RSTMGR_ALERT_INFO_ATTR,
+ RSTMGR_ALERT_INFO,
+ RSTMGR_CPU_REGWEN,
+ RSTMGR_CPU_INFO_CTRL,
+ RSTMGR_CPU_INFO_ATTR,
+ RSTMGR_CPU_INFO,
+ RSTMGR_SW_RST_REGWEN_0,
+ RSTMGR_SW_RST_REGWEN_1,
+ RSTMGR_SW_RST_REGWEN_2,
+ RSTMGR_SW_RST_REGWEN_3,
+ RSTMGR_SW_RST_REGWEN_4,
+ RSTMGR_SW_RST_REGWEN_5,
+ RSTMGR_SW_RST_REGWEN_6,
+ RSTMGR_SW_RST_REGWEN_7,
+ RSTMGR_SW_RST_REGWEN_8,
+ RSTMGR_SW_RST_REGWEN_9,
+ RSTMGR_SW_RST_REGWEN_10,
+ RSTMGR_SW_RST_REGWEN_11,
+ RSTMGR_SW_RST_REGWEN_12,
+ RSTMGR_SW_RST_REGWEN_13,
+ RSTMGR_SW_RST_CTRL_N_0,
+ RSTMGR_SW_RST_CTRL_N_1,
+ RSTMGR_SW_RST_CTRL_N_2,
+ RSTMGR_SW_RST_CTRL_N_3,
+ RSTMGR_SW_RST_CTRL_N_4,
+ RSTMGR_SW_RST_CTRL_N_5,
+ RSTMGR_SW_RST_CTRL_N_6,
+ RSTMGR_SW_RST_CTRL_N_7,
+ RSTMGR_SW_RST_CTRL_N_8,
+ RSTMGR_SW_RST_CTRL_N_9,
+ RSTMGR_SW_RST_CTRL_N_10,
+ RSTMGR_SW_RST_CTRL_N_11,
+ RSTMGR_SW_RST_CTRL_N_12,
+ RSTMGR_SW_RST_CTRL_N_13,
+ RSTMGR_ERR_CODE
+ } rstmgr_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] RSTMGR_PERMIT [40] = '{
+ 4'b 0001, // index[ 0] RSTMGR_ALERT_TEST
+ 4'b 0001, // index[ 1] RSTMGR_RESET_REQ
+ 4'b 0001, // index[ 2] RSTMGR_RESET_INFO
+ 4'b 0001, // index[ 3] RSTMGR_ALERT_REGWEN
+ 4'b 0001, // index[ 4] RSTMGR_ALERT_INFO_CTRL
+ 4'b 0001, // index[ 5] RSTMGR_ALERT_INFO_ATTR
+ 4'b 1111, // index[ 6] RSTMGR_ALERT_INFO
+ 4'b 0001, // index[ 7] RSTMGR_CPU_REGWEN
+ 4'b 0001, // index[ 8] RSTMGR_CPU_INFO_CTRL
+ 4'b 0001, // index[ 9] RSTMGR_CPU_INFO_ATTR
+ 4'b 1111, // index[10] RSTMGR_CPU_INFO
+ 4'b 0001, // index[11] RSTMGR_SW_RST_REGWEN_0
+ 4'b 0001, // index[12] RSTMGR_SW_RST_REGWEN_1
+ 4'b 0001, // index[13] RSTMGR_SW_RST_REGWEN_2
+ 4'b 0001, // index[14] RSTMGR_SW_RST_REGWEN_3
+ 4'b 0001, // index[15] RSTMGR_SW_RST_REGWEN_4
+ 4'b 0001, // index[16] RSTMGR_SW_RST_REGWEN_5
+ 4'b 0001, // index[17] RSTMGR_SW_RST_REGWEN_6
+ 4'b 0001, // index[18] RSTMGR_SW_RST_REGWEN_7
+ 4'b 0001, // index[19] RSTMGR_SW_RST_REGWEN_8
+ 4'b 0001, // index[20] RSTMGR_SW_RST_REGWEN_9
+ 4'b 0001, // index[21] RSTMGR_SW_RST_REGWEN_10
+ 4'b 0001, // index[22] RSTMGR_SW_RST_REGWEN_11
+ 4'b 0001, // index[23] RSTMGR_SW_RST_REGWEN_12
+ 4'b 0001, // index[24] RSTMGR_SW_RST_REGWEN_13
+ 4'b 0001, // index[25] RSTMGR_SW_RST_CTRL_N_0
+ 4'b 0001, // index[26] RSTMGR_SW_RST_CTRL_N_1
+ 4'b 0001, // index[27] RSTMGR_SW_RST_CTRL_N_2
+ 4'b 0001, // index[28] RSTMGR_SW_RST_CTRL_N_3
+ 4'b 0001, // index[29] RSTMGR_SW_RST_CTRL_N_4
+ 4'b 0001, // index[30] RSTMGR_SW_RST_CTRL_N_5
+ 4'b 0001, // index[31] RSTMGR_SW_RST_CTRL_N_6
+ 4'b 0001, // index[32] RSTMGR_SW_RST_CTRL_N_7
+ 4'b 0001, // index[33] RSTMGR_SW_RST_CTRL_N_8
+ 4'b 0001, // index[34] RSTMGR_SW_RST_CTRL_N_9
+ 4'b 0001, // index[35] RSTMGR_SW_RST_CTRL_N_10
+ 4'b 0001, // index[36] RSTMGR_SW_RST_CTRL_N_11
+ 4'b 0001, // index[37] RSTMGR_SW_RST_CTRL_N_12
+ 4'b 0001, // index[38] RSTMGR_SW_RST_CTRL_N_13
+ 4'b 0001 // index[39] RSTMGR_ERR_CODE
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
new file mode 100644
index 0000000..98acb40
--- /dev/null
+++ b/hw/top_sencha/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -0,0 +1,2042 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module rstmgr_reg_top (
+ input clk_i,
+ input rst_ni,
+ input clk_por_i,
+ input rst_por_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write
+ input rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import rstmgr_reg_pkg::* ;
+
+ localparam int AW = 8;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [39:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(40)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic alert_test_we;
+ logic alert_test_fatal_fault_wd;
+ logic alert_test_fatal_cnsty_fault_wd;
+ logic reset_req_we;
+ logic [3:0] reset_req_qs;
+ logic [3:0] reset_req_wd;
+ logic reset_info_we;
+ logic reset_info_por_qs;
+ logic reset_info_por_wd;
+ logic reset_info_low_power_exit_qs;
+ logic reset_info_low_power_exit_wd;
+ logic reset_info_sw_reset_qs;
+ logic reset_info_sw_reset_wd;
+ logic [4:0] reset_info_hw_req_qs;
+ logic [4:0] reset_info_hw_req_wd;
+ logic alert_regwen_we;
+ logic alert_regwen_qs;
+ logic alert_regwen_wd;
+ logic alert_info_ctrl_we;
+ logic alert_info_ctrl_en_qs;
+ logic alert_info_ctrl_en_wd;
+ logic [3:0] alert_info_ctrl_index_qs;
+ logic [3:0] alert_info_ctrl_index_wd;
+ logic alert_info_attr_re;
+ logic [3:0] alert_info_attr_qs;
+ logic alert_info_re;
+ logic [31:0] alert_info_qs;
+ logic cpu_regwen_we;
+ logic cpu_regwen_qs;
+ logic cpu_regwen_wd;
+ logic cpu_info_ctrl_we;
+ logic cpu_info_ctrl_en_qs;
+ logic cpu_info_ctrl_en_wd;
+ logic [3:0] cpu_info_ctrl_index_qs;
+ logic [3:0] cpu_info_ctrl_index_wd;
+ logic cpu_info_attr_re;
+ logic [3:0] cpu_info_attr_qs;
+ logic cpu_info_re;
+ logic [31:0] cpu_info_qs;
+ logic sw_rst_regwen_0_we;
+ logic sw_rst_regwen_0_qs;
+ logic sw_rst_regwen_0_wd;
+ logic sw_rst_regwen_1_we;
+ logic sw_rst_regwen_1_qs;
+ logic sw_rst_regwen_1_wd;
+ logic sw_rst_regwen_2_we;
+ logic sw_rst_regwen_2_qs;
+ logic sw_rst_regwen_2_wd;
+ logic sw_rst_regwen_3_we;
+ logic sw_rst_regwen_3_qs;
+ logic sw_rst_regwen_3_wd;
+ logic sw_rst_regwen_4_we;
+ logic sw_rst_regwen_4_qs;
+ logic sw_rst_regwen_4_wd;
+ logic sw_rst_regwen_5_we;
+ logic sw_rst_regwen_5_qs;
+ logic sw_rst_regwen_5_wd;
+ logic sw_rst_regwen_6_we;
+ logic sw_rst_regwen_6_qs;
+ logic sw_rst_regwen_6_wd;
+ logic sw_rst_regwen_7_we;
+ logic sw_rst_regwen_7_qs;
+ logic sw_rst_regwen_7_wd;
+ logic sw_rst_regwen_8_we;
+ logic sw_rst_regwen_8_qs;
+ logic sw_rst_regwen_8_wd;
+ logic sw_rst_regwen_9_we;
+ logic sw_rst_regwen_9_qs;
+ logic sw_rst_regwen_9_wd;
+ logic sw_rst_regwen_10_we;
+ logic sw_rst_regwen_10_qs;
+ logic sw_rst_regwen_10_wd;
+ logic sw_rst_regwen_11_we;
+ logic sw_rst_regwen_11_qs;
+ logic sw_rst_regwen_11_wd;
+ logic sw_rst_regwen_12_we;
+ logic sw_rst_regwen_12_qs;
+ logic sw_rst_regwen_12_wd;
+ logic sw_rst_regwen_13_we;
+ logic sw_rst_regwen_13_qs;
+ logic sw_rst_regwen_13_wd;
+ logic sw_rst_ctrl_n_0_we;
+ logic sw_rst_ctrl_n_0_qs;
+ logic sw_rst_ctrl_n_0_wd;
+ logic sw_rst_ctrl_n_1_we;
+ logic sw_rst_ctrl_n_1_qs;
+ logic sw_rst_ctrl_n_1_wd;
+ logic sw_rst_ctrl_n_2_we;
+ logic sw_rst_ctrl_n_2_qs;
+ logic sw_rst_ctrl_n_2_wd;
+ logic sw_rst_ctrl_n_3_we;
+ logic sw_rst_ctrl_n_3_qs;
+ logic sw_rst_ctrl_n_3_wd;
+ logic sw_rst_ctrl_n_4_we;
+ logic sw_rst_ctrl_n_4_qs;
+ logic sw_rst_ctrl_n_4_wd;
+ logic sw_rst_ctrl_n_5_we;
+ logic sw_rst_ctrl_n_5_qs;
+ logic sw_rst_ctrl_n_5_wd;
+ logic sw_rst_ctrl_n_6_we;
+ logic sw_rst_ctrl_n_6_qs;
+ logic sw_rst_ctrl_n_6_wd;
+ logic sw_rst_ctrl_n_7_we;
+ logic sw_rst_ctrl_n_7_qs;
+ logic sw_rst_ctrl_n_7_wd;
+ logic sw_rst_ctrl_n_8_we;
+ logic sw_rst_ctrl_n_8_qs;
+ logic sw_rst_ctrl_n_8_wd;
+ logic sw_rst_ctrl_n_9_we;
+ logic sw_rst_ctrl_n_9_qs;
+ logic sw_rst_ctrl_n_9_wd;
+ logic sw_rst_ctrl_n_10_we;
+ logic sw_rst_ctrl_n_10_qs;
+ logic sw_rst_ctrl_n_10_wd;
+ logic sw_rst_ctrl_n_11_we;
+ logic sw_rst_ctrl_n_11_qs;
+ logic sw_rst_ctrl_n_11_wd;
+ logic sw_rst_ctrl_n_12_we;
+ logic sw_rst_ctrl_n_12_qs;
+ logic sw_rst_ctrl_n_12_wd;
+ logic sw_rst_ctrl_n_13_we;
+ logic sw_rst_ctrl_n_13_qs;
+ logic sw_rst_ctrl_n_13_wd;
+ logic err_code_reg_intg_err_qs;
+ logic err_code_reset_consistency_err_qs;
+ logic err_code_fsm_err_qs;
+ // Define register CDC handling.
+ // CDC handling is done on a per-reg instead of per-field boundary.
+
+ // Register instances
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [1:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ // F[fatal_fault]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_fault (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_fault_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.fatal_fault.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;
+
+ // F[fatal_cnsty_fault]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_cnsty_fault (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_cnsty_fault_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_cnsty_fault.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe;
+
+
+ // R[reset_req]: V(False)
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h9)
+ ) u_reset_req (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (reset_req_we),
+ .wd (reset_req_wd),
+
+ // from internal hardware
+ .de (hw2reg.reset_req.de),
+ .d (hw2reg.reset_req.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.reset_req.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_req_qs)
+ );
+
+
+ // R[reset_info]: V(False)
+ // F[por]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h1)
+ ) u_reset_info_por (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (reset_info_we),
+ .wd (reset_info_por_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_info_por_qs)
+ );
+
+ // F[low_power_exit]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_reset_info_low_power_exit (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (reset_info_we),
+ .wd (reset_info_low_power_exit_wd),
+
+ // from internal hardware
+ .de (hw2reg.reset_info.low_power_exit.de),
+ .d (hw2reg.reset_info.low_power_exit.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_info_low_power_exit_qs)
+ );
+
+ // F[sw_reset]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_reset_info_sw_reset (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (reset_info_we),
+ .wd (reset_info_sw_reset_wd),
+
+ // from internal hardware
+ .de (hw2reg.reset_info.sw_reset.de),
+ .d (hw2reg.reset_info.sw_reset.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.reset_info.sw_reset.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_info_sw_reset_qs)
+ );
+
+ // F[hw_req]: 7:3
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (5'h0)
+ ) u_reset_info_hw_req (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (reset_info_we),
+ .wd (reset_info_hw_req_wd),
+
+ // from internal hardware
+ .de (hw2reg.reset_info.hw_req.de),
+ .d (hw2reg.reset_info.hw_req.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.reset_info.hw_req.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (reset_info_hw_req_qs)
+ );
+
+
+ // R[alert_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_we),
+ .wd (alert_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_qs)
+ );
+
+
+ // R[alert_info_ctrl]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_info_ctrl_gated_we;
+ assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_info_ctrl_en (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (alert_info_ctrl_gated_we),
+ .wd (alert_info_ctrl_en_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_info_ctrl.en.de),
+ .d (hw2reg.alert_info_ctrl.en.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_info_ctrl.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_info_ctrl_en_qs)
+ );
+
+ // F[index]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h0)
+ ) u_alert_info_ctrl_index (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (alert_info_ctrl_gated_we),
+ .wd (alert_info_ctrl_index_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_info_ctrl.index.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_info_ctrl_index_qs)
+ );
+
+
+ // R[alert_info_attr]: V(True)
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_info_attr (
+ .re (alert_info_attr_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_info_attr.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (alert_info_attr_qs)
+ );
+
+
+ // R[alert_info]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_alert_info (
+ .re (alert_info_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_info.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (alert_info_qs)
+ );
+
+
+ // R[cpu_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_cpu_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (cpu_regwen_we),
+ .wd (cpu_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (cpu_regwen_qs)
+ );
+
+
+ // R[cpu_info_ctrl]: V(False)
+ // Create REGWEN-gated WE signal
+ logic cpu_info_ctrl_gated_we;
+ assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_cpu_info_ctrl_en (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (cpu_info_ctrl_gated_we),
+ .wd (cpu_info_ctrl_en_wd),
+
+ // from internal hardware
+ .de (hw2reg.cpu_info_ctrl.en.de),
+ .d (hw2reg.cpu_info_ctrl.en.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.cpu_info_ctrl.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (cpu_info_ctrl_en_qs)
+ );
+
+ // F[index]: 7:4
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h0)
+ ) u_cpu_info_ctrl_index (
+ // sync clock and reset required for this register
+ .clk_i (clk_por_i),
+ .rst_ni (rst_por_ni),
+
+ // from register interface
+ .we (cpu_info_ctrl_gated_we),
+ .wd (cpu_info_ctrl_index_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.cpu_info_ctrl.index.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (cpu_info_ctrl_index_qs)
+ );
+
+
+ // R[cpu_info_attr]: V(True)
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_cpu_info_attr (
+ .re (cpu_info_attr_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.cpu_info_attr.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (cpu_info_attr_qs)
+ );
+
+
+ // R[cpu_info]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_cpu_info (
+ .re (cpu_info_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.cpu_info.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (cpu_info_qs)
+ );
+
+
+ // Subregister 0 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_0_we),
+ .wd (sw_rst_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_1_we),
+ .wd (sw_rst_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_2_we),
+ .wd (sw_rst_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_3_we),
+ .wd (sw_rst_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_4_we),
+ .wd (sw_rst_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_5_we),
+ .wd (sw_rst_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_6_we),
+ .wd (sw_rst_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_7_we),
+ .wd (sw_rst_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_8_we),
+ .wd (sw_rst_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_9_we),
+ .wd (sw_rst_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_10_we),
+ .wd (sw_rst_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_11_we),
+ .wd (sw_rst_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_12_we),
+ .wd (sw_rst_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg sw_rst_regwen
+ // R[sw_rst_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_sw_rst_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_regwen_13_we),
+ .wd (sw_rst_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_regwen_13_qs)
+ );
+
+
+ // Subregister 0 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_0_gated_we;
+ assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_0_gated_we),
+ .wd (sw_rst_ctrl_n_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_1_gated_we;
+ assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_1_gated_we),
+ .wd (sw_rst_ctrl_n_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_2_gated_we;
+ assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_2_gated_we),
+ .wd (sw_rst_ctrl_n_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_3_gated_we;
+ assign sw_rst_ctrl_n_3_gated_we = sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_3_gated_we),
+ .wd (sw_rst_ctrl_n_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_4_gated_we;
+ assign sw_rst_ctrl_n_4_gated_we = sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_4_gated_we),
+ .wd (sw_rst_ctrl_n_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_5_gated_we;
+ assign sw_rst_ctrl_n_5_gated_we = sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_5_gated_we),
+ .wd (sw_rst_ctrl_n_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_6_gated_we;
+ assign sw_rst_ctrl_n_6_gated_we = sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_6_gated_we),
+ .wd (sw_rst_ctrl_n_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_7_gated_we;
+ assign sw_rst_ctrl_n_7_gated_we = sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_7_gated_we),
+ .wd (sw_rst_ctrl_n_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_8_gated_we;
+ assign sw_rst_ctrl_n_8_gated_we = sw_rst_ctrl_n_8_we & sw_rst_regwen_8_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_8_gated_we),
+ .wd (sw_rst_ctrl_n_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_9_gated_we;
+ assign sw_rst_ctrl_n_9_gated_we = sw_rst_ctrl_n_9_we & sw_rst_regwen_9_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_9_gated_we),
+ .wd (sw_rst_ctrl_n_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_10_gated_we;
+ assign sw_rst_ctrl_n_10_gated_we = sw_rst_ctrl_n_10_we & sw_rst_regwen_10_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_10_gated_we),
+ .wd (sw_rst_ctrl_n_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_11_gated_we;
+ assign sw_rst_ctrl_n_11_gated_we = sw_rst_ctrl_n_11_we & sw_rst_regwen_11_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_11_gated_we),
+ .wd (sw_rst_ctrl_n_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_12_gated_we;
+ assign sw_rst_ctrl_n_12_gated_we = sw_rst_ctrl_n_12_we & sw_rst_regwen_12_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_12_gated_we),
+ .wd (sw_rst_ctrl_n_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg sw_rst_ctrl_n
+ // R[sw_rst_ctrl_n_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic sw_rst_ctrl_n_13_gated_we;
+ assign sw_rst_ctrl_n_13_gated_we = sw_rst_ctrl_n_13_we & sw_rst_regwen_13_qs;
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_sw_rst_ctrl_n_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (sw_rst_ctrl_n_13_gated_we),
+ .wd (sw_rst_ctrl_n_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.sw_rst_ctrl_n[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (sw_rst_ctrl_n_13_qs)
+ );
+
+
+ // R[err_code]: V(False)
+ // F[reg_intg_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_err_code_reg_intg_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.reg_intg_err.de),
+ .d (hw2reg.err_code.reg_intg_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.err_code.reg_intg_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_reg_intg_err_qs)
+ );
+
+ // F[reset_consistency_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_err_code_reset_consistency_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.reset_consistency_err.de),
+ .d (hw2reg.err_code.reset_consistency_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.err_code.reset_consistency_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_reset_consistency_err_qs)
+ );
+
+ // F[fsm_err]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_err_code_fsm_err (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.err_code.fsm_err.de),
+ .d (hw2reg.err_code.fsm_err.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.err_code.fsm_err.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (err_code_fsm_err_qs)
+ );
+
+
+
+ logic [39:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET);
+ addr_hit[ 1] = (reg_addr == RSTMGR_RESET_REQ_OFFSET);
+ addr_hit[ 2] = (reg_addr == RSTMGR_RESET_INFO_OFFSET);
+ addr_hit[ 3] = (reg_addr == RSTMGR_ALERT_REGWEN_OFFSET);
+ addr_hit[ 4] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET);
+ addr_hit[ 5] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET);
+ addr_hit[ 6] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET);
+ addr_hit[ 7] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET);
+ addr_hit[ 8] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET);
+ addr_hit[ 9] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET);
+ addr_hit[10] = (reg_addr == RSTMGR_CPU_INFO_OFFSET);
+ addr_hit[11] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET);
+ addr_hit[12] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET);
+ addr_hit[13] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET);
+ addr_hit[14] = (reg_addr == RSTMGR_SW_RST_REGWEN_3_OFFSET);
+ addr_hit[15] = (reg_addr == RSTMGR_SW_RST_REGWEN_4_OFFSET);
+ addr_hit[16] = (reg_addr == RSTMGR_SW_RST_REGWEN_5_OFFSET);
+ addr_hit[17] = (reg_addr == RSTMGR_SW_RST_REGWEN_6_OFFSET);
+ addr_hit[18] = (reg_addr == RSTMGR_SW_RST_REGWEN_7_OFFSET);
+ addr_hit[19] = (reg_addr == RSTMGR_SW_RST_REGWEN_8_OFFSET);
+ addr_hit[20] = (reg_addr == RSTMGR_SW_RST_REGWEN_9_OFFSET);
+ addr_hit[21] = (reg_addr == RSTMGR_SW_RST_REGWEN_10_OFFSET);
+ addr_hit[22] = (reg_addr == RSTMGR_SW_RST_REGWEN_11_OFFSET);
+ addr_hit[23] = (reg_addr == RSTMGR_SW_RST_REGWEN_12_OFFSET);
+ addr_hit[24] = (reg_addr == RSTMGR_SW_RST_REGWEN_13_OFFSET);
+ addr_hit[25] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET);
+ addr_hit[26] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET);
+ addr_hit[27] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET);
+ addr_hit[28] = (reg_addr == RSTMGR_SW_RST_CTRL_N_3_OFFSET);
+ addr_hit[29] = (reg_addr == RSTMGR_SW_RST_CTRL_N_4_OFFSET);
+ addr_hit[30] = (reg_addr == RSTMGR_SW_RST_CTRL_N_5_OFFSET);
+ addr_hit[31] = (reg_addr == RSTMGR_SW_RST_CTRL_N_6_OFFSET);
+ addr_hit[32] = (reg_addr == RSTMGR_SW_RST_CTRL_N_7_OFFSET);
+ addr_hit[33] = (reg_addr == RSTMGR_SW_RST_CTRL_N_8_OFFSET);
+ addr_hit[34] = (reg_addr == RSTMGR_SW_RST_CTRL_N_9_OFFSET);
+ addr_hit[35] = (reg_addr == RSTMGR_SW_RST_CTRL_N_10_OFFSET);
+ addr_hit[36] = (reg_addr == RSTMGR_SW_RST_CTRL_N_11_OFFSET);
+ addr_hit[37] = (reg_addr == RSTMGR_SW_RST_CTRL_N_12_OFFSET);
+ addr_hit[38] = (reg_addr == RSTMGR_SW_RST_CTRL_N_13_OFFSET);
+ addr_hit[39] = (reg_addr == RSTMGR_ERR_CODE_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(RSTMGR_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(RSTMGR_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(RSTMGR_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(RSTMGR_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(RSTMGR_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(RSTMGR_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(RSTMGR_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(RSTMGR_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(RSTMGR_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(RSTMGR_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(RSTMGR_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(RSTMGR_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(RSTMGR_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(RSTMGR_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(RSTMGR_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(RSTMGR_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(RSTMGR_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(RSTMGR_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(RSTMGR_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(RSTMGR_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(RSTMGR_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(RSTMGR_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(RSTMGR_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(RSTMGR_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(RSTMGR_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(RSTMGR_PERMIT[26] & ~reg_be))) |
+ (addr_hit[27] & (|(RSTMGR_PERMIT[27] & ~reg_be))) |
+ (addr_hit[28] & (|(RSTMGR_PERMIT[28] & ~reg_be))) |
+ (addr_hit[29] & (|(RSTMGR_PERMIT[29] & ~reg_be))) |
+ (addr_hit[30] & (|(RSTMGR_PERMIT[30] & ~reg_be))) |
+ (addr_hit[31] & (|(RSTMGR_PERMIT[31] & ~reg_be))) |
+ (addr_hit[32] & (|(RSTMGR_PERMIT[32] & ~reg_be))) |
+ (addr_hit[33] & (|(RSTMGR_PERMIT[33] & ~reg_be))) |
+ (addr_hit[34] & (|(RSTMGR_PERMIT[34] & ~reg_be))) |
+ (addr_hit[35] & (|(RSTMGR_PERMIT[35] & ~reg_be))) |
+ (addr_hit[36] & (|(RSTMGR_PERMIT[36] & ~reg_be))) |
+ (addr_hit[37] & (|(RSTMGR_PERMIT[37] & ~reg_be))) |
+ (addr_hit[38] & (|(RSTMGR_PERMIT[38] & ~reg_be))) |
+ (addr_hit[39] & (|(RSTMGR_PERMIT[39] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign alert_test_fatal_fault_wd = reg_wdata[0];
+
+ assign alert_test_fatal_cnsty_fault_wd = reg_wdata[1];
+ assign reset_req_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign reset_req_wd = reg_wdata[3:0];
+ assign reset_info_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign reset_info_por_wd = reg_wdata[0];
+
+ assign reset_info_low_power_exit_wd = reg_wdata[1];
+
+ assign reset_info_sw_reset_wd = reg_wdata[2];
+
+ assign reset_info_hw_req_wd = reg_wdata[7:3];
+ assign alert_regwen_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_regwen_wd = reg_wdata[0];
+ assign alert_info_ctrl_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign alert_info_ctrl_en_wd = reg_wdata[0];
+
+ assign alert_info_ctrl_index_wd = reg_wdata[7:4];
+ assign alert_info_attr_re = addr_hit[5] & reg_re & !reg_error;
+ assign alert_info_re = addr_hit[6] & reg_re & !reg_error;
+ assign cpu_regwen_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign cpu_regwen_wd = reg_wdata[0];
+ assign cpu_info_ctrl_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign cpu_info_ctrl_en_wd = reg_wdata[0];
+
+ assign cpu_info_ctrl_index_wd = reg_wdata[7:4];
+ assign cpu_info_attr_re = addr_hit[9] & reg_re & !reg_error;
+ assign cpu_info_re = addr_hit[10] & reg_re & !reg_error;
+ assign sw_rst_regwen_0_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_0_wd = reg_wdata[0];
+ assign sw_rst_regwen_1_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_1_wd = reg_wdata[0];
+ assign sw_rst_regwen_2_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_2_wd = reg_wdata[0];
+ assign sw_rst_regwen_3_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_3_wd = reg_wdata[0];
+ assign sw_rst_regwen_4_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_4_wd = reg_wdata[0];
+ assign sw_rst_regwen_5_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_5_wd = reg_wdata[0];
+ assign sw_rst_regwen_6_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_6_wd = reg_wdata[0];
+ assign sw_rst_regwen_7_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_7_wd = reg_wdata[0];
+ assign sw_rst_regwen_8_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_8_wd = reg_wdata[0];
+ assign sw_rst_regwen_9_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_9_wd = reg_wdata[0];
+ assign sw_rst_regwen_10_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_10_wd = reg_wdata[0];
+ assign sw_rst_regwen_11_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_11_wd = reg_wdata[0];
+ assign sw_rst_regwen_12_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_12_wd = reg_wdata[0];
+ assign sw_rst_regwen_13_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign sw_rst_regwen_13_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_0_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_0_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_1_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_1_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_2_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_2_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_3_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_3_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_4_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_4_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_5_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_5_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_6_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_6_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_7_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_7_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_8_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_8_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_9_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_9_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_10_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_10_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_11_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_11_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_12_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_12_wd = reg_wdata[0];
+ assign sw_rst_ctrl_n_13_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign sw_rst_ctrl_n_13_wd = reg_wdata[0];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = alert_test_we;
+ reg_we_check[1] = reset_req_we;
+ reg_we_check[2] = reset_info_we;
+ reg_we_check[3] = alert_regwen_we;
+ reg_we_check[4] = alert_info_ctrl_gated_we;
+ reg_we_check[5] = 1'b0;
+ reg_we_check[6] = 1'b0;
+ reg_we_check[7] = cpu_regwen_we;
+ reg_we_check[8] = cpu_info_ctrl_gated_we;
+ reg_we_check[9] = 1'b0;
+ reg_we_check[10] = 1'b0;
+ reg_we_check[11] = sw_rst_regwen_0_we;
+ reg_we_check[12] = sw_rst_regwen_1_we;
+ reg_we_check[13] = sw_rst_regwen_2_we;
+ reg_we_check[14] = sw_rst_regwen_3_we;
+ reg_we_check[15] = sw_rst_regwen_4_we;
+ reg_we_check[16] = sw_rst_regwen_5_we;
+ reg_we_check[17] = sw_rst_regwen_6_we;
+ reg_we_check[18] = sw_rst_regwen_7_we;
+ reg_we_check[19] = sw_rst_regwen_8_we;
+ reg_we_check[20] = sw_rst_regwen_9_we;
+ reg_we_check[21] = sw_rst_regwen_10_we;
+ reg_we_check[22] = sw_rst_regwen_11_we;
+ reg_we_check[23] = sw_rst_regwen_12_we;
+ reg_we_check[24] = sw_rst_regwen_13_we;
+ reg_we_check[25] = sw_rst_ctrl_n_0_gated_we;
+ reg_we_check[26] = sw_rst_ctrl_n_1_gated_we;
+ reg_we_check[27] = sw_rst_ctrl_n_2_gated_we;
+ reg_we_check[28] = sw_rst_ctrl_n_3_gated_we;
+ reg_we_check[29] = sw_rst_ctrl_n_4_gated_we;
+ reg_we_check[30] = sw_rst_ctrl_n_5_gated_we;
+ reg_we_check[31] = sw_rst_ctrl_n_6_gated_we;
+ reg_we_check[32] = sw_rst_ctrl_n_7_gated_we;
+ reg_we_check[33] = sw_rst_ctrl_n_8_gated_we;
+ reg_we_check[34] = sw_rst_ctrl_n_9_gated_we;
+ reg_we_check[35] = sw_rst_ctrl_n_10_gated_we;
+ reg_we_check[36] = sw_rst_ctrl_n_11_gated_we;
+ reg_we_check[37] = sw_rst_ctrl_n_12_gated_we;
+ reg_we_check[38] = sw_rst_ctrl_n_13_gated_we;
+ reg_we_check[39] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[3:0] = reset_req_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = reset_info_por_qs;
+ reg_rdata_next[1] = reset_info_low_power_exit_qs;
+ reg_rdata_next[2] = reset_info_sw_reset_qs;
+ reg_rdata_next[7:3] = reset_info_hw_req_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = alert_regwen_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = alert_info_ctrl_en_qs;
+ reg_rdata_next[7:4] = alert_info_ctrl_index_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[3:0] = alert_info_attr_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[31:0] = alert_info_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = cpu_regwen_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = cpu_info_ctrl_en_qs;
+ reg_rdata_next[7:4] = cpu_info_ctrl_index_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[3:0] = cpu_info_attr_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[31:0] = cpu_info_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = sw_rst_regwen_0_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = sw_rst_regwen_1_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = sw_rst_regwen_2_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = sw_rst_regwen_3_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[0] = sw_rst_regwen_4_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = sw_rst_regwen_5_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[0] = sw_rst_regwen_6_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = sw_rst_regwen_7_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = sw_rst_regwen_8_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[0] = sw_rst_regwen_9_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[0] = sw_rst_regwen_10_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[0] = sw_rst_regwen_11_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[0] = sw_rst_regwen_12_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[0] = sw_rst_regwen_13_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_0_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_1_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_2_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_3_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_4_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_5_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_6_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_7_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_8_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_9_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_10_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_11_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_12_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[0] = sw_rst_ctrl_n_13_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[0] = err_code_reg_intg_err_qs;
+ reg_rdata_next[1] = err_code_reset_consistency_err_qs;
+ reg_rdata_next[2] = err_code_fsm_err_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
new file mode 100644
index 0000000..90d9f97
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
@@ -0,0 +1,178 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package sensor_ctrl_reg_pkg;
+
+ // Param list
+ parameter int NumAlertEvents = 11;
+ parameter int NumLocalEvents = 1;
+ parameter int NumAlerts = 2;
+ parameter int NumIoRails = 2;
+
+ // Address widths within the block
+ parameter int BlockAw = 6;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } io_status_change;
+ struct packed {
+ logic q;
+ } init_status_change;
+ } sensor_ctrl_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } io_status_change;
+ struct packed {
+ logic q;
+ } init_status_change;
+ } sensor_ctrl_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } io_status_change;
+ struct packed {
+ logic q;
+ logic qe;
+ } init_status_change;
+ } sensor_ctrl_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_alert;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_alert;
+ } sensor_ctrl_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_alert_trig_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_fatal_alert_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_recov_alert_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_fatal_alert_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } io_status_change;
+ struct packed {
+ logic d;
+ logic de;
+ } init_status_change;
+ } sensor_ctrl_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } sensor_ctrl_hw2reg_recov_alert_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } sensor_ctrl_hw2reg_fatal_alert_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } ast_init_done;
+ struct packed {
+ logic [1:0] d;
+ logic de;
+ } io_pok;
+ } sensor_ctrl_hw2reg_status_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ sensor_ctrl_reg2hw_intr_state_reg_t intr_state; // [56:55]
+ sensor_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [54:53]
+ sensor_ctrl_reg2hw_intr_test_reg_t intr_test; // [52:49]
+ sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [48:45]
+ sensor_ctrl_reg2hw_alert_trig_mreg_t [10:0] alert_trig; // [44:34]
+ sensor_ctrl_reg2hw_fatal_alert_en_mreg_t [10:0] fatal_alert_en; // [33:23]
+ sensor_ctrl_reg2hw_recov_alert_mreg_t [10:0] recov_alert; // [22:12]
+ sensor_ctrl_reg2hw_fatal_alert_mreg_t [11:0] fatal_alert; // [11:0]
+ } sensor_ctrl_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ sensor_ctrl_hw2reg_intr_state_reg_t intr_state; // [54:51]
+ sensor_ctrl_hw2reg_recov_alert_mreg_t [10:0] recov_alert; // [50:29]
+ sensor_ctrl_hw2reg_fatal_alert_mreg_t [11:0] fatal_alert; // [28:5]
+ sensor_ctrl_hw2reg_status_reg_t status; // [4:0]
+ } sensor_ctrl_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_INTR_STATE_OFFSET = 6'h 0;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_INTR_ENABLE_OFFSET = 6'h 4;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_INTR_TEST_OFFSET = 6'h 8;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_TEST_OFFSET = 6'h c;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_CFG_REGWEN_OFFSET = 6'h 10;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_TRIG_OFFSET = 6'h 14;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_FATAL_ALERT_EN_OFFSET = 6'h 18;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_RECOV_ALERT_OFFSET = 6'h 1c;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_FATAL_ALERT_OFFSET = 6'h 20;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_STATUS_OFFSET = 6'h 24;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [1:0] SENSOR_CTRL_INTR_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] SENSOR_CTRL_INTR_TEST_IO_STATUS_CHANGE_RESVAL = 1'h 0;
+ parameter logic [0:0] SENSOR_CTRL_INTR_TEST_INIT_STATUS_CHANGE_RESVAL = 1'h 0;
+ parameter logic [1:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_ALERT_RESVAL = 1'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_FATAL_ALERT_RESVAL = 1'h 0;
+
+ // Register index
+ typedef enum int {
+ SENSOR_CTRL_INTR_STATE,
+ SENSOR_CTRL_INTR_ENABLE,
+ SENSOR_CTRL_INTR_TEST,
+ SENSOR_CTRL_ALERT_TEST,
+ SENSOR_CTRL_CFG_REGWEN,
+ SENSOR_CTRL_ALERT_TRIG,
+ SENSOR_CTRL_FATAL_ALERT_EN,
+ SENSOR_CTRL_RECOV_ALERT,
+ SENSOR_CTRL_FATAL_ALERT,
+ SENSOR_CTRL_STATUS
+ } sensor_ctrl_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] SENSOR_CTRL_PERMIT [10] = '{
+ 4'b 0001, // index[0] SENSOR_CTRL_INTR_STATE
+ 4'b 0001, // index[1] SENSOR_CTRL_INTR_ENABLE
+ 4'b 0001, // index[2] SENSOR_CTRL_INTR_TEST
+ 4'b 0001, // index[3] SENSOR_CTRL_ALERT_TEST
+ 4'b 0001, // index[4] SENSOR_CTRL_CFG_REGWEN
+ 4'b 0011, // index[5] SENSOR_CTRL_ALERT_TRIG
+ 4'b 0011, // index[6] SENSOR_CTRL_FATAL_ALERT_EN
+ 4'b 0011, // index[7] SENSOR_CTRL_RECOV_ALERT
+ 4'b 0011, // index[8] SENSOR_CTRL_FATAL_ALERT
+ 4'b 0001 // index[9] SENSOR_CTRL_STATUS
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
new file mode 100644
index 0000000..d273352
--- /dev/null
+++ b/hw/top_sencha/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -0,0 +1,1945 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module sensor_ctrl_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output sensor_ctrl_reg_pkg::sensor_ctrl_reg2hw_t reg2hw, // Write
+ input sensor_ctrl_reg_pkg::sensor_ctrl_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import sensor_ctrl_reg_pkg::* ;
+
+ localparam int AW = 6;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [9:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(10)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_io_status_change_qs;
+ logic intr_state_io_status_change_wd;
+ logic intr_state_init_status_change_qs;
+ logic intr_state_init_status_change_wd;
+ logic intr_enable_we;
+ logic intr_enable_io_status_change_qs;
+ logic intr_enable_io_status_change_wd;
+ logic intr_enable_init_status_change_qs;
+ logic intr_enable_init_status_change_wd;
+ logic intr_test_we;
+ logic intr_test_io_status_change_wd;
+ logic intr_test_init_status_change_wd;
+ logic alert_test_we;
+ logic alert_test_recov_alert_wd;
+ logic alert_test_fatal_alert_wd;
+ logic cfg_regwen_we;
+ logic cfg_regwen_qs;
+ logic cfg_regwen_wd;
+ logic alert_trig_we;
+ logic alert_trig_val_0_qs;
+ logic alert_trig_val_0_wd;
+ logic alert_trig_val_1_qs;
+ logic alert_trig_val_1_wd;
+ logic alert_trig_val_2_qs;
+ logic alert_trig_val_2_wd;
+ logic alert_trig_val_3_qs;
+ logic alert_trig_val_3_wd;
+ logic alert_trig_val_4_qs;
+ logic alert_trig_val_4_wd;
+ logic alert_trig_val_5_qs;
+ logic alert_trig_val_5_wd;
+ logic alert_trig_val_6_qs;
+ logic alert_trig_val_6_wd;
+ logic alert_trig_val_7_qs;
+ logic alert_trig_val_7_wd;
+ logic alert_trig_val_8_qs;
+ logic alert_trig_val_8_wd;
+ logic alert_trig_val_9_qs;
+ logic alert_trig_val_9_wd;
+ logic alert_trig_val_10_qs;
+ logic alert_trig_val_10_wd;
+ logic fatal_alert_en_we;
+ logic fatal_alert_en_val_0_qs;
+ logic fatal_alert_en_val_0_wd;
+ logic fatal_alert_en_val_1_qs;
+ logic fatal_alert_en_val_1_wd;
+ logic fatal_alert_en_val_2_qs;
+ logic fatal_alert_en_val_2_wd;
+ logic fatal_alert_en_val_3_qs;
+ logic fatal_alert_en_val_3_wd;
+ logic fatal_alert_en_val_4_qs;
+ logic fatal_alert_en_val_4_wd;
+ logic fatal_alert_en_val_5_qs;
+ logic fatal_alert_en_val_5_wd;
+ logic fatal_alert_en_val_6_qs;
+ logic fatal_alert_en_val_6_wd;
+ logic fatal_alert_en_val_7_qs;
+ logic fatal_alert_en_val_7_wd;
+ logic fatal_alert_en_val_8_qs;
+ logic fatal_alert_en_val_8_wd;
+ logic fatal_alert_en_val_9_qs;
+ logic fatal_alert_en_val_9_wd;
+ logic fatal_alert_en_val_10_qs;
+ logic fatal_alert_en_val_10_wd;
+ logic recov_alert_we;
+ logic recov_alert_val_0_qs;
+ logic recov_alert_val_0_wd;
+ logic recov_alert_val_1_qs;
+ logic recov_alert_val_1_wd;
+ logic recov_alert_val_2_qs;
+ logic recov_alert_val_2_wd;
+ logic recov_alert_val_3_qs;
+ logic recov_alert_val_3_wd;
+ logic recov_alert_val_4_qs;
+ logic recov_alert_val_4_wd;
+ logic recov_alert_val_5_qs;
+ logic recov_alert_val_5_wd;
+ logic recov_alert_val_6_qs;
+ logic recov_alert_val_6_wd;
+ logic recov_alert_val_7_qs;
+ logic recov_alert_val_7_wd;
+ logic recov_alert_val_8_qs;
+ logic recov_alert_val_8_wd;
+ logic recov_alert_val_9_qs;
+ logic recov_alert_val_9_wd;
+ logic recov_alert_val_10_qs;
+ logic recov_alert_val_10_wd;
+ logic fatal_alert_val_0_qs;
+ logic fatal_alert_val_1_qs;
+ logic fatal_alert_val_2_qs;
+ logic fatal_alert_val_3_qs;
+ logic fatal_alert_val_4_qs;
+ logic fatal_alert_val_5_qs;
+ logic fatal_alert_val_6_qs;
+ logic fatal_alert_val_7_qs;
+ logic fatal_alert_val_8_qs;
+ logic fatal_alert_val_9_qs;
+ logic fatal_alert_val_10_qs;
+ logic fatal_alert_val_11_qs;
+ logic status_ast_init_done_qs;
+ logic [1:0] status_io_pok_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[io_status_change]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_io_status_change (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_io_status_change_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.io_status_change.de),
+ .d (hw2reg.intr_state.io_status_change.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.io_status_change.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_io_status_change_qs)
+ );
+
+ // F[init_status_change]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_init_status_change (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_init_status_change_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.init_status_change.de),
+ .d (hw2reg.intr_state.init_status_change.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.init_status_change.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_init_status_change_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[io_status_change]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_io_status_change (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_io_status_change_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.io_status_change.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_io_status_change_qs)
+ );
+
+ // F[init_status_change]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_init_status_change (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_init_status_change_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.init_status_change.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_init_status_change_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ logic intr_test_qe;
+ logic [1:0] intr_test_flds_we;
+ assign intr_test_qe = &intr_test_flds_we;
+ // F[io_status_change]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_io_status_change (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_io_status_change_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[0]),
+ .q (reg2hw.intr_test.io_status_change.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.io_status_change.qe = intr_test_qe;
+
+ // F[init_status_change]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_init_status_change (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_init_status_change_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[1]),
+ .q (reg2hw.intr_test.init_status_change.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.init_status_change.qe = intr_test_qe;
+
+
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [1:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ // F[recov_alert]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_alert (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_recov_alert_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.recov_alert.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.recov_alert.qe = alert_test_qe;
+
+ // F[fatal_alert]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_alert (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_fatal_alert_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[1]),
+ .q (reg2hw.alert_test.fatal_alert.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.fatal_alert.qe = alert_test_qe;
+
+
+ // R[cfg_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_cfg_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (cfg_regwen_we),
+ .wd (cfg_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (cfg_regwen_qs)
+ );
+
+
+ // Subregister 0 of Multireg alert_trig
+ // R[alert_trig]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_trig_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_trig_we),
+ .wd (alert_trig_val_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_trig[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_trig_val_10_qs)
+ );
+
+
+ // Subregister 0 of Multireg fatal_alert_en
+ // R[fatal_alert_en]: V(False)
+ // Create REGWEN-gated WE signal
+ logic fatal_alert_en_gated_we;
+ assign fatal_alert_en_gated_we = fatal_alert_en_we & cfg_regwen_qs;
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_gated_we),
+ .wd (fatal_alert_en_val_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_10_qs)
+ );
+
+
+ // Subregister 0 of Multireg recov_alert
+ // R[recov_alert]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[0].de),
+ .d (hw2reg.recov_alert[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[1].de),
+ .d (hw2reg.recov_alert[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_2_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[2].de),
+ .d (hw2reg.recov_alert[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_3_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[3].de),
+ .d (hw2reg.recov_alert[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_4_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[4].de),
+ .d (hw2reg.recov_alert[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_5_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[5].de),
+ .d (hw2reg.recov_alert[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_6_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[6].de),
+ .d (hw2reg.recov_alert[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_7_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[7].de),
+ .d (hw2reg.recov_alert[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_8_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[8].de),
+ .d (hw2reg.recov_alert[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_9_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[9].de),
+ .d (hw2reg.recov_alert[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_recov_alert_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (recov_alert_we),
+ .wd (recov_alert_val_10_wd),
+
+ // from internal hardware
+ .de (hw2reg.recov_alert[10].de),
+ .d (hw2reg.recov_alert[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.recov_alert[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (recov_alert_val_10_qs)
+ );
+
+
+ // Subregister 0 of Multireg fatal_alert
+ // R[fatal_alert]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[0].de),
+ .d (hw2reg.fatal_alert[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[1].de),
+ .d (hw2reg.fatal_alert[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[2].de),
+ .d (hw2reg.fatal_alert[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[3].de),
+ .d (hw2reg.fatal_alert[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[4].de),
+ .d (hw2reg.fatal_alert[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[5].de),
+ .d (hw2reg.fatal_alert[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[6].de),
+ .d (hw2reg.fatal_alert[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[7].de),
+ .d (hw2reg.fatal_alert[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[8].de),
+ .d (hw2reg.fatal_alert[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[9].de),
+ .d (hw2reg.fatal_alert[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[10].de),
+ .d (hw2reg.fatal_alert[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_10_qs)
+ );
+
+ // F[val_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[11].de),
+ .d (hw2reg.fatal_alert[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_11_qs)
+ );
+
+
+ // R[status]: V(False)
+ // F[ast_init_done]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_status_ast_init_done (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.ast_init_done.de),
+ .d (hw2reg.status.ast_init_done.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_ast_init_done_qs)
+ );
+
+ // F[io_pok]: 2:1
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (2'h0)
+ ) u_status_io_pok (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.status.io_pok.de),
+ .d (hw2reg.status.io_pok.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (status_io_pok_qs)
+ );
+
+
+
+ logic [9:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[0] = (reg_addr == SENSOR_CTRL_INTR_STATE_OFFSET);
+ addr_hit[1] = (reg_addr == SENSOR_CTRL_INTR_ENABLE_OFFSET);
+ addr_hit[2] = (reg_addr == SENSOR_CTRL_INTR_TEST_OFFSET);
+ addr_hit[3] = (reg_addr == SENSOR_CTRL_ALERT_TEST_OFFSET);
+ addr_hit[4] = (reg_addr == SENSOR_CTRL_CFG_REGWEN_OFFSET);
+ addr_hit[5] = (reg_addr == SENSOR_CTRL_ALERT_TRIG_OFFSET);
+ addr_hit[6] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_EN_OFFSET);
+ addr_hit[7] = (reg_addr == SENSOR_CTRL_RECOV_ALERT_OFFSET);
+ addr_hit[8] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_OFFSET);
+ addr_hit[9] = (reg_addr == SENSOR_CTRL_STATUS_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[0] & (|(SENSOR_CTRL_PERMIT[0] & ~reg_be))) |
+ (addr_hit[1] & (|(SENSOR_CTRL_PERMIT[1] & ~reg_be))) |
+ (addr_hit[2] & (|(SENSOR_CTRL_PERMIT[2] & ~reg_be))) |
+ (addr_hit[3] & (|(SENSOR_CTRL_PERMIT[3] & ~reg_be))) |
+ (addr_hit[4] & (|(SENSOR_CTRL_PERMIT[4] & ~reg_be))) |
+ (addr_hit[5] & (|(SENSOR_CTRL_PERMIT[5] & ~reg_be))) |
+ (addr_hit[6] & (|(SENSOR_CTRL_PERMIT[6] & ~reg_be))) |
+ (addr_hit[7] & (|(SENSOR_CTRL_PERMIT[7] & ~reg_be))) |
+ (addr_hit[8] & (|(SENSOR_CTRL_PERMIT[8] & ~reg_be))) |
+ (addr_hit[9] & (|(SENSOR_CTRL_PERMIT[9] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_io_status_change_wd = reg_wdata[0];
+
+ assign intr_state_init_status_change_wd = reg_wdata[1];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_io_status_change_wd = reg_wdata[0];
+
+ assign intr_enable_init_status_change_wd = reg_wdata[1];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_io_status_change_wd = reg_wdata[0];
+
+ assign intr_test_init_status_change_wd = reg_wdata[1];
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign alert_test_recov_alert_wd = reg_wdata[0];
+
+ assign alert_test_fatal_alert_wd = reg_wdata[1];
+ assign cfg_regwen_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign cfg_regwen_wd = reg_wdata[0];
+ assign alert_trig_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign alert_trig_val_0_wd = reg_wdata[0];
+
+ assign alert_trig_val_1_wd = reg_wdata[1];
+
+ assign alert_trig_val_2_wd = reg_wdata[2];
+
+ assign alert_trig_val_3_wd = reg_wdata[3];
+
+ assign alert_trig_val_4_wd = reg_wdata[4];
+
+ assign alert_trig_val_5_wd = reg_wdata[5];
+
+ assign alert_trig_val_6_wd = reg_wdata[6];
+
+ assign alert_trig_val_7_wd = reg_wdata[7];
+
+ assign alert_trig_val_8_wd = reg_wdata[8];
+
+ assign alert_trig_val_9_wd = reg_wdata[9];
+
+ assign alert_trig_val_10_wd = reg_wdata[10];
+ assign fatal_alert_en_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign fatal_alert_en_val_0_wd = reg_wdata[0];
+
+ assign fatal_alert_en_val_1_wd = reg_wdata[1];
+
+ assign fatal_alert_en_val_2_wd = reg_wdata[2];
+
+ assign fatal_alert_en_val_3_wd = reg_wdata[3];
+
+ assign fatal_alert_en_val_4_wd = reg_wdata[4];
+
+ assign fatal_alert_en_val_5_wd = reg_wdata[5];
+
+ assign fatal_alert_en_val_6_wd = reg_wdata[6];
+
+ assign fatal_alert_en_val_7_wd = reg_wdata[7];
+
+ assign fatal_alert_en_val_8_wd = reg_wdata[8];
+
+ assign fatal_alert_en_val_9_wd = reg_wdata[9];
+
+ assign fatal_alert_en_val_10_wd = reg_wdata[10];
+ assign recov_alert_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign recov_alert_val_0_wd = reg_wdata[0];
+
+ assign recov_alert_val_1_wd = reg_wdata[1];
+
+ assign recov_alert_val_2_wd = reg_wdata[2];
+
+ assign recov_alert_val_3_wd = reg_wdata[3];
+
+ assign recov_alert_val_4_wd = reg_wdata[4];
+
+ assign recov_alert_val_5_wd = reg_wdata[5];
+
+ assign recov_alert_val_6_wd = reg_wdata[6];
+
+ assign recov_alert_val_7_wd = reg_wdata[7];
+
+ assign recov_alert_val_8_wd = reg_wdata[8];
+
+ assign recov_alert_val_9_wd = reg_wdata[9];
+
+ assign recov_alert_val_10_wd = reg_wdata[10];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = intr_state_we;
+ reg_we_check[1] = intr_enable_we;
+ reg_we_check[2] = intr_test_we;
+ reg_we_check[3] = alert_test_we;
+ reg_we_check[4] = cfg_regwen_we;
+ reg_we_check[5] = alert_trig_we;
+ reg_we_check[6] = fatal_alert_en_gated_we;
+ reg_we_check[7] = recov_alert_we;
+ reg_we_check[8] = 1'b0;
+ reg_we_check[9] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_io_status_change_qs;
+ reg_rdata_next[1] = intr_state_init_status_change_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_io_status_change_qs;
+ reg_rdata_next[1] = intr_enable_init_status_change_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[0] = cfg_regwen_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = alert_trig_val_0_qs;
+ reg_rdata_next[1] = alert_trig_val_1_qs;
+ reg_rdata_next[2] = alert_trig_val_2_qs;
+ reg_rdata_next[3] = alert_trig_val_3_qs;
+ reg_rdata_next[4] = alert_trig_val_4_qs;
+ reg_rdata_next[5] = alert_trig_val_5_qs;
+ reg_rdata_next[6] = alert_trig_val_6_qs;
+ reg_rdata_next[7] = alert_trig_val_7_qs;
+ reg_rdata_next[8] = alert_trig_val_8_qs;
+ reg_rdata_next[9] = alert_trig_val_9_qs;
+ reg_rdata_next[10] = alert_trig_val_10_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = fatal_alert_en_val_0_qs;
+ reg_rdata_next[1] = fatal_alert_en_val_1_qs;
+ reg_rdata_next[2] = fatal_alert_en_val_2_qs;
+ reg_rdata_next[3] = fatal_alert_en_val_3_qs;
+ reg_rdata_next[4] = fatal_alert_en_val_4_qs;
+ reg_rdata_next[5] = fatal_alert_en_val_5_qs;
+ reg_rdata_next[6] = fatal_alert_en_val_6_qs;
+ reg_rdata_next[7] = fatal_alert_en_val_7_qs;
+ reg_rdata_next[8] = fatal_alert_en_val_8_qs;
+ reg_rdata_next[9] = fatal_alert_en_val_9_qs;
+ reg_rdata_next[10] = fatal_alert_en_val_10_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = recov_alert_val_0_qs;
+ reg_rdata_next[1] = recov_alert_val_1_qs;
+ reg_rdata_next[2] = recov_alert_val_2_qs;
+ reg_rdata_next[3] = recov_alert_val_3_qs;
+ reg_rdata_next[4] = recov_alert_val_4_qs;
+ reg_rdata_next[5] = recov_alert_val_5_qs;
+ reg_rdata_next[6] = recov_alert_val_6_qs;
+ reg_rdata_next[7] = recov_alert_val_7_qs;
+ reg_rdata_next[8] = recov_alert_val_8_qs;
+ reg_rdata_next[9] = recov_alert_val_9_qs;
+ reg_rdata_next[10] = recov_alert_val_10_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = fatal_alert_val_0_qs;
+ reg_rdata_next[1] = fatal_alert_val_1_qs;
+ reg_rdata_next[2] = fatal_alert_val_2_qs;
+ reg_rdata_next[3] = fatal_alert_val_3_qs;
+ reg_rdata_next[4] = fatal_alert_val_4_qs;
+ reg_rdata_next[5] = fatal_alert_val_5_qs;
+ reg_rdata_next[6] = fatal_alert_val_6_qs;
+ reg_rdata_next[7] = fatal_alert_val_7_qs;
+ reg_rdata_next[8] = fatal_alert_val_8_qs;
+ reg_rdata_next[9] = fatal_alert_val_9_qs;
+ reg_rdata_next[10] = fatal_alert_val_10_qs;
+ reg_rdata_next[11] = fatal_alert_val_11_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = status_ast_init_done_qs;
+ reg_rdata_next[2:1] = status_io_pok_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson b/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson
new file mode 100644
index 0000000..9c03e8d
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson
@@ -0,0 +1,123 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+{
+ name: dbg
+ clock_srcs:
+ {
+ clk_main_i: main
+ }
+ clock_group: infra
+ reset: rst_main_ni
+ reset_connections:
+ {
+ rst_main_ni:
+ {
+ name: lc
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_main_i: clkmgr_aon_clocks.clk_main_infra
+ }
+ domain:
+ [
+ "0"
+ ]
+ connections:
+ {
+ main:
+ [
+ rv_dm.regs
+ rv_dm.mem
+ ]
+ smc:
+ [
+ rv_dm.regs
+ rv_dm.mem
+ ]
+ }
+ nodes:
+ [
+ {
+ name: main
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ xbar: true
+ pipeline: true
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: smc
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ xbar: true
+ pipeline: true
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_dm.regs
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ addr_range:
+ [
+ {
+ base_addr: 0x6000
+ size_byte: 0x4
+ }
+ ]
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rv_dm
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rv_dm.mem
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ addr_range:
+ [
+ {
+ base_addr: 0x4000
+ size_byte: 0x1000
+ }
+ ]
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rv_dm
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ ]
+ clock: clk_main_i
+ type: xbar
+}
diff --git a/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.hjson b/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.hjson
new file mode 100644
index 0000000..bc69b41
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/data/autogen/xbar_dbg.hjson
@@ -0,0 +1,41 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_dbg comportable IP spec generated by `tlgen.py` tool
+{ name: "xbar_dbg"
+ clock_primary: ""
+ other_clock_list: []
+ reset_primary: ""
+ other_reset_list: []
+ //available_input_list: []
+
+ inter_signal_list: [
+ // host
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_main"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_smc"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ // device
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_dm__regs"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_dm__mem"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv b/hw/top_sencha/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv
new file mode 100644
index 0000000..0c0d3a7
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__xbar_connect generated by `tlgen.py` tool
+
+xbar_dbg dut();
+
+`DRIVE_CLK(clk_main_i)
+
+initial force dut.clk_main_i = clk_main_i;
+
+// TODO, all resets tie together
+initial force dut.rst_main_ni = rst_n;
+
+// Host TileLink interface connections
+`CONNECT_TL_HOST_IF(main, dut, clk_main_i, rst_n)
+`CONNECT_TL_HOST_IF(smc, dut, clk_main_i, rst_n)
+
+// Device TileLink interface connections
+`CONNECT_TL_DEVICE_IF(rv_dm__regs, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_dm__mem, dut, clk_main_i, rst_n)
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el
new file mode 100644
index 0000000..15d0dad
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el
@@ -0,0 +1,24 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cov_excl.el generated by `tlgen.py` tool
+
+ANNOTATION: "[NON_RTL]"
+MODULE: uvm_pkg
+Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion"
+Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion"
+
+ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim"
+MODULE: xbar_dbg
+Block 1 "0" "assign unused_scanmode = scanmode_i;"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_fifo_sync
+Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cover.cfg
new file mode 100644
index 0000000..f2aa91d
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_cover.cfg
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cover.cfg generated by `tlgen.py` tool
+
++tree tb.dut
+-module pins_if // DV construct.
+-module clk_rst_if // DV construct.
+
+-assert legalAOpcodeErr_A
+-assert sizeGTEMaskErr_A
+-assert sizeMatchesMaskErr_A
+-assert addrSizeAlignedErr_A
+
+// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after.
+-node tb.dut tl_*.a_param
+-node tb.dut tl_*.d_param
+-node tb.dut tl_*.d_opcode[2:1]
+
+// [UNR] these device address bits are always 0
+-node tb.dut tl_rv_dm__regs_o.a_address[12:2]
+-node tb.dut tl_rv_dm__regs_o.a_address[31:15]
+-node tb.dut tl_rv_dm__mem_o.a_address[13:12]
+-node tb.dut tl_rv_dm__mem_o.a_address[31:15]
+
+-node tb.dut tl_*.a_source[7:7]
+-node tb.dut tl_*.d_source[7:7]
+begin tgl
+ -tree tb
+ +tree tb.dut 1
+ -node tb.dut.scanmode_i
+end
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core
new file mode 100644
index 0000000..4ad7ace
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_dbg_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_dbg_bind:0.1"
+description: "XBAR dbg assertion bind"
+filesets:
+ files_dv:
+ files:
+ - xbar_dbg_bind.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv
new file mode 100644
index 0000000..761d4cc
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv
@@ -0,0 +1,36 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_dbg_bind module generated by `tlgen.py` tool for assertions
+module xbar_dbg_bind;
+
+ // Host interfaces
+ bind xbar_dbg tlul_assert #(.EndpointType("Device")) tlul_assert_host_main (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_main_i),
+ .d2h (tl_main_o)
+ );
+ bind xbar_dbg tlul_assert #(.EndpointType("Device")) tlul_assert_host_smc (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_smc_i),
+ .d2h (tl_smc_o)
+ );
+
+ // Device interfaces
+ bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__regs (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_dm__regs_o),
+ .d2h (tl_rv_dm__regs_i)
+ );
+ bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__mem (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_dm__mem_o),
+ .d2h (tl_rv_dm__mem_i)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core
new file mode 100644
index 0000000..8ea870b
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core
@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_dbg_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_dbg_sim:0.1"
+description: "XBAR DV sim target"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:top_sencha:xbar_dbg
+ - lowrisc:dv:dv_utils
+ - lowrisc:dv:xbar_tb
+ - lowrisc:dv:top_sencha_xbar_dbg_bind
+ files:
+ - tb__xbar_connect.sv: {is_include_file: true}
+ - xbar_env_pkg__params.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+
+targets:
+ sim: &sim_target
+ toplevel: xbar_tb_top
+ filesets:
+ - files_dv
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson
new file mode 100644
index 0000000..bc99cdc
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_dbg_sim_cfg.hjson file generated by `tlgen.py` tool
+{
+ name: xbar_dbg
+
+ // Top level dut name (sv module).
+ dut: xbar_dbg
+
+ // The name of the chip this XBAR configuration is made for.
+ top_chip: top_sencha
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson"
+
+ // Add xbar_main specific exclusion files.
+ vcs_cov_excl_files: ["{proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cov_excl.el"]
+
+ // replace common cover.cfg with a generated one, which includes xbar toggle exclusions
+ overrides: [
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cover.cfg"
+ }
+ ]
+ // Import additional common sim cfg files.
+ import_cfgs: [// xbar common sim cfg file
+ "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"]
+}
diff --git a/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv
new file mode 100644
index 0000000..f877f98
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `tlgen.py` tool
+
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+ '{"rv_dm__regs", '{
+ '{32'h00006000, 32'h00006003}
+ }},
+ '{"rv_dm__mem", '{
+ '{32'h00004000, 32'h00004fff}
+}}};
+
+ // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+ '{"main", 0, '{
+ "rv_dm__regs",
+ "rv_dm__mem"}}
+ ,
+ '{"smc", 1, '{
+ "rv_dm__regs",
+ "rv_dm__mem"}}
+};
diff --git a/hw/top_sencha/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv b/hw/top_sencha/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv
new file mode 100644
index 0000000..4769c56
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tl_dbg package generated by `tlgen.py` tool
+
+package tl_dbg_pkg;
+
+ localparam logic [31:0] ADDR_SPACE_RV_DM__REGS = 32'h 00006000;
+ localparam logic [31:0] ADDR_SPACE_RV_DM__MEM = 32'h 00004000;
+
+ localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 00000003;
+ localparam logic [31:0] ADDR_MASK_RV_DM__MEM = 32'h 00000fff;
+
+ localparam int N_HOST = 2;
+ localparam int N_DEVICE = 2;
+
+ typedef enum int {
+ TlRvDmRegs = 0,
+ TlRvDmMem = 1
+ } tl_device_e;
+
+ typedef enum int {
+ TlMain = 0,
+ TlSmc = 1
+ } tl_host_e;
+
+endpackage
diff --git a/hw/top_sencha/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv b/hw/top_sencha/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv
new file mode 100644
index 0000000..af04e8e
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv
@@ -0,0 +1,192 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_dbg module generated by `tlgen.py` tool
+// all reset signals should be generated from one reset signal to not make any deadlock
+//
+// Interconnect
+// main
+// -> s1n_4
+// -> sm1_5
+// -> rv_dm.regs
+// -> sm1_6
+// -> rv_dm.mem
+// smc
+// -> s1n_7
+// -> sm1_5
+// -> rv_dm.regs
+// -> sm1_6
+// -> rv_dm.mem
+
+module xbar_dbg (
+ input clk_main_i,
+ input rst_main_ni,
+
+ // Host interfaces
+ input tlul_pkg::tl_h2d_t tl_main_i,
+ output tlul_pkg::tl_d2h_t tl_main_o,
+ input tlul_pkg::tl_h2d_t tl_smc_i,
+ output tlul_pkg::tl_d2h_t tl_smc_o,
+
+ // Device interfaces
+ output tlul_pkg::tl_h2d_t tl_rv_dm__regs_o,
+ input tlul_pkg::tl_d2h_t tl_rv_dm__regs_i,
+ output tlul_pkg::tl_h2d_t tl_rv_dm__mem_o,
+ input tlul_pkg::tl_d2h_t tl_rv_dm__mem_i,
+
+ input prim_mubi_pkg::mubi4_t scanmode_i
+);
+
+ import tlul_pkg::*;
+ import tl_dbg_pkg::*;
+
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = ^scanmode_i;
+
+ tl_h2d_t tl_s1n_4_us_h2d ;
+ tl_d2h_t tl_s1n_4_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_4_ds_h2d [2];
+ tl_d2h_t tl_s1n_4_ds_d2h [2];
+
+ // Create steering signal
+ logic [1:0] dev_sel_s1n_4;
+
+
+ tl_h2d_t tl_sm1_5_us_h2d [2];
+ tl_d2h_t tl_sm1_5_us_d2h [2];
+
+ tl_h2d_t tl_sm1_5_ds_h2d ;
+ tl_d2h_t tl_sm1_5_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_6_us_h2d [2];
+ tl_d2h_t tl_sm1_6_us_d2h [2];
+
+ tl_h2d_t tl_sm1_6_ds_h2d ;
+ tl_d2h_t tl_sm1_6_ds_d2h ;
+
+ tl_h2d_t tl_s1n_7_us_h2d ;
+ tl_d2h_t tl_s1n_7_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_7_ds_h2d [2];
+ tl_d2h_t tl_s1n_7_ds_d2h [2];
+
+ // Create steering signal
+ logic [1:0] dev_sel_s1n_7;
+
+
+
+ assign tl_sm1_5_us_h2d[0] = tl_s1n_4_ds_h2d[0];
+ assign tl_s1n_4_ds_d2h[0] = tl_sm1_5_us_d2h[0];
+
+ assign tl_sm1_6_us_h2d[0] = tl_s1n_4_ds_h2d[1];
+ assign tl_s1n_4_ds_d2h[1] = tl_sm1_6_us_d2h[0];
+
+ assign tl_sm1_5_us_h2d[1] = tl_s1n_7_ds_h2d[0];
+ assign tl_s1n_7_ds_d2h[0] = tl_sm1_5_us_d2h[1];
+
+ assign tl_sm1_6_us_h2d[1] = tl_s1n_7_ds_h2d[1];
+ assign tl_s1n_7_ds_d2h[1] = tl_sm1_6_us_d2h[1];
+
+ assign tl_s1n_4_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_4_us_d2h;
+
+ assign tl_rv_dm__regs_o = tl_sm1_5_ds_h2d;
+ assign tl_sm1_5_ds_d2h = tl_rv_dm__regs_i;
+
+ assign tl_rv_dm__mem_o = tl_sm1_6_ds_h2d;
+ assign tl_sm1_6_ds_d2h = tl_rv_dm__mem_i;
+
+ assign tl_s1n_7_us_h2d = tl_smc_i;
+ assign tl_smc_o = tl_s1n_7_us_d2h;
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_4 = 2'd2;
+ if ((tl_s1n_4_us_h2d.a_address &
+ ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin
+ dev_sel_s1n_4 = 2'd0;
+
+ end else if ((tl_s1n_4_us_h2d.a_address &
+ ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin
+ dev_sel_s1n_4 = 2'd1;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_7 = 2'd2;
+ if ((tl_s1n_7_us_h2d.a_address &
+ ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin
+ dev_sel_s1n_7 = 2'd0;
+
+ end else if ((tl_s1n_7_us_h2d.a_address &
+ ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin
+ dev_sel_s1n_7 = 2'd1;
+end
+ end
+
+
+ // Instantiation phase
+ tlul_socket_1n #(
+ .DReqDepth (8'h0),
+ .DRspDepth (8'h0),
+ .N (2)
+ ) u_s1n_4 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_4_us_h2d),
+ .tl_h_o (tl_s1n_4_us_d2h),
+ .tl_d_o (tl_s1n_4_ds_h2d),
+ .tl_d_i (tl_s1n_4_ds_d2h),
+ .dev_select_i (dev_sel_s1n_4)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_5 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_5_us_h2d),
+ .tl_h_o (tl_sm1_5_us_d2h),
+ .tl_d_o (tl_sm1_5_ds_h2d),
+ .tl_d_i (tl_sm1_5_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_6 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_6_us_h2d),
+ .tl_h_o (tl_sm1_6_us_d2h),
+ .tl_d_o (tl_sm1_6_ds_h2d),
+ .tl_d_i (tl_sm1_6_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .DReqDepth (8'h0),
+ .DRspDepth (8'h0),
+ .N (2)
+ ) u_s1n_7 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_7_us_h2d),
+ .tl_h_o (tl_s1n_7_us_d2h),
+ .tl_d_o (tl_s1n_7_ds_h2d),
+ .tl_d_i (tl_s1n_7_ds_d2h),
+ .dev_select_i (dev_sel_s1n_7)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.gen.hjson
new file mode 100644
index 0000000..9aaddbd
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -0,0 +1,718 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+{
+ name: main
+ clock_srcs:
+ {
+ clk_main_i: main
+ clk_fixed_i: io_div4
+ clk_usb_i: usb
+ clk_spi_host0_i: io
+ clk_spi_host1_i: io
+ clk_smc_i: smc
+ }
+ clock_group: infra
+ reset: rst_main_ni
+ reset_connections:
+ {
+ rst_main_ni:
+ {
+ name: lc
+ domain: "0"
+ }
+ rst_fixed_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ rst_usb_ni:
+ {
+ name: lc_usb
+ domain: "0"
+ }
+ rst_spi_host0_ni:
+ {
+ name: lc_io
+ domain: "0"
+ }
+ rst_spi_host1_ni:
+ {
+ name: lc_io
+ domain: "0"
+ }
+ rst_smc_ni:
+ {
+ name: smc
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_main_i: clkmgr_aon_clocks.clk_main_infra
+ clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
+ clk_usb_i: clkmgr_aon_clocks.clk_usb_infra
+ clk_spi_host0_i: clkmgr_aon_clocks.clk_io_infra
+ clk_spi_host1_i: clkmgr_aon_clocks.clk_io_infra
+ clk_smc_i: clkmgr_aon_clocks.clk_smc_infra
+ }
+ domain:
+ [
+ "0"
+ ]
+ connections:
+ {
+ rv_core_ibex_sec.corei:
+ [
+ rom_ctrl.rom
+ dbg
+ sram_ctrl_main.ram
+ flash_ctrl.mem
+ ]
+ rv_core_ibex_sec.cored:
+ [
+ rom_ctrl.rom
+ rom_ctrl.regs
+ dbg
+ sram_ctrl_main.ram
+ peri
+ spi_host0
+ spi_host1
+ usbdev
+ flash_ctrl.core
+ flash_ctrl.prim
+ flash_ctrl.mem
+ aes
+ entropy_src
+ csrng
+ edn0
+ edn1
+ hmac
+ rv_plic
+ otbn
+ keymgr
+ kmac
+ sram_ctrl_main.regs
+ rv_core_ibex_sec.cfg
+ smc
+ tlul_mailbox_sec
+ dma0
+ ]
+ rv_dm.sba:
+ [
+ dbg
+ rom_ctrl.rom
+ rom_ctrl.regs
+ peri
+ spi_host0
+ spi_host1
+ usbdev
+ flash_ctrl.core
+ flash_ctrl.prim
+ flash_ctrl.mem
+ hmac
+ kmac
+ aes
+ entropy_src
+ csrng
+ edn0
+ edn1
+ rv_plic
+ otbn
+ keymgr
+ rv_core_ibex_sec.cfg
+ sram_ctrl_main.regs
+ sram_ctrl_main.ram
+ smc
+ tlul_mailbox_sec
+ ]
+ dma0.reader:
+ [
+ rom_ctrl.rom
+ sram_ctrl_main.ram
+ flash_ctrl.mem
+ smc
+ ]
+ dma0.writer:
+ [
+ rom_ctrl.rom
+ sram_ctrl_main.ram
+ flash_ctrl.mem
+ smc
+ ]
+ }
+ nodes:
+ [
+ {
+ name: rv_core_ibex_sec.corei
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline: false
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_core_ibex_sec.cored
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline: false
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_dm.sba
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ xbar: false
+ stub: false
+ inst_type: ""
+ pipeline: true
+ }
+ {
+ name: dma0.reader
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline: false
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: dma0.writer
+ type: host
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline: false
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: dma0
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: dma
+ addr_range:
+ [
+ {
+ base_addr: 0x40200000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rom_ctrl.rom
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: true
+ rsp_fifo_pass: false
+ inst_type: rom_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x8000
+ size_byte: 0x8000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rom_ctrl.regs
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rom_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x411e0000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: peri
+ type: device
+ clock: clk_fixed_i
+ reset: rst_fixed_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ xbar: true
+ stub: false
+ pipeline: true
+ addr_range:
+ [
+ {
+ base_addr: 0x40000000
+ size_byte: 0x200000
+ }
+ {
+ base_addr: 0x40400000
+ size_byte: 0x400000
+ }
+ ]
+ }
+ {
+ name: spi_host0
+ type: device
+ clock: clk_spi_host0_i
+ reset: rst_spi_host0_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40300000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: spi_host1
+ type: device
+ clock: clk_spi_host1_i
+ reset: rst_spi_host1_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x40310000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: usbdev
+ type: device
+ clock: clk_usb_i
+ reset: rst_usb_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: usbdev
+ addr_range:
+ [
+ {
+ base_addr: 0x40320000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: flash_ctrl.core
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: flash_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x41000000
+ size_byte: 0x200
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: flash_ctrl.prim
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: flash_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x41008000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: flash_ctrl.mem
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: flash_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x20000000
+ size_byte: 0x100000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: hmac
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: hmac
+ addr_range:
+ [
+ {
+ base_addr: 0x41110000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: kmac
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: kmac
+ addr_range:
+ [
+ {
+ base_addr: 0x41120000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: aes
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: aes
+ addr_range:
+ [
+ {
+ base_addr: 0x41100000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: entropy_src
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: entropy_src
+ addr_range:
+ [
+ {
+ base_addr: 0x41160000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: csrng
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: csrng
+ addr_range:
+ [
+ {
+ base_addr: 0x41150000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: edn0
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: edn
+ addr_range:
+ [
+ {
+ base_addr: 0x41170000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: edn1
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: edn
+ addr_range:
+ [
+ {
+ base_addr: 0x41180000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rv_plic
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ inst_type: rv_plic
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ addr_range:
+ [
+ {
+ base_addr: 0x48000000
+ size_byte: 0x8000000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: otbn
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: otbn
+ addr_range:
+ [
+ {
+ base_addr: 0x41130000
+ size_byte: 0x10000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: keymgr
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: keymgr
+ addr_range:
+ [
+ {
+ base_addr: 0x41140000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rv_core_ibex_sec.cfg
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rv_core_ibex
+ addr_range:
+ [
+ {
+ base_addr: 0x411f0000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: sram_ctrl_main.regs
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: sram_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x411c0000
+ size_byte: 0x20
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: sram_ctrl_main.ram
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline: false
+ inst_type: sram_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x10000000
+ size_byte: 0x20000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: tlul_mailbox_sec
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline_byp: false
+ inst_type: tlul_mailbox
+ addr_range:
+ [
+ {
+ base_addr: 0x40800000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ req_fifo_pass: true
+ }
+ {
+ name: smc
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline_byp: false
+ xbar: true
+ stub: false
+ pipeline: true
+ req_fifo_pass: true
+ addr_range:
+ [
+ {
+ base_addr: 0x50000000
+ size_byte: 0x10000000
+ }
+ ]
+ }
+ {
+ name: dbg
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline_byp: false
+ xbar: true
+ stub: false
+ pipeline: true
+ req_fifo_pass: true
+ addr_range:
+ [
+ {
+ base_addr: 0x4000
+ size_byte: 0x4000
+ }
+ ]
+ }
+ ]
+ clock: clk_main_i
+ type: xbar
+}
diff --git a/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.hjson
new file mode 100644
index 0000000..92a0021
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -0,0 +1,203 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_main comportable IP spec generated by `tlgen.py` tool
+{ name: "xbar_main"
+ clock_primary: ""
+ other_clock_list: []
+ reset_primary: ""
+ other_reset_list: []
+ //available_input_list: []
+
+ inter_signal_list: [
+ // host
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_sec__corei"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_sec__cored"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_dm__sba"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma0__reader"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma0__writer"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ // device
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rom_ctrl__rom"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rom_ctrl__regs"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_peri"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_spi_host0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_spi_host1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_usbdev"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_flash_ctrl__core"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_flash_ctrl__prim"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_flash_ctrl__mem"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_hmac"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_kmac"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_aes"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_entropy_src"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_csrng"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_edn0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_edn1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_plic"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_otbn"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_keymgr"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_sec__cfg"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sram_ctrl_main__regs"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sram_ctrl_main__ram"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_tlul_mailbox_sec"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dbg"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_sencha/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
new file mode 100644
index 0000000..1b1f4c4
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__xbar_connect generated by `tlgen.py` tool
+
+xbar_main dut();
+
+`DRIVE_CLK(clk_main_i)
+`DRIVE_CLK(clk_fixed_i)
+`DRIVE_CLK(clk_usb_i)
+`DRIVE_CLK(clk_spi_host0_i)
+`DRIVE_CLK(clk_spi_host1_i)
+`DRIVE_CLK(clk_smc_i)
+
+initial force dut.clk_main_i = clk_main_i;
+initial force dut.clk_fixed_i = clk_fixed_i;
+initial force dut.clk_usb_i = clk_usb_i;
+initial force dut.clk_spi_host0_i = clk_spi_host0_i;
+initial force dut.clk_spi_host1_i = clk_spi_host1_i;
+initial force dut.clk_smc_i = clk_smc_i;
+
+// TODO, all resets tie together
+initial force dut.rst_main_ni = rst_n;
+initial force dut.rst_fixed_ni = rst_n;
+initial force dut.rst_usb_ni = rst_n;
+initial force dut.rst_spi_host0_ni = rst_n;
+initial force dut.rst_spi_host1_ni = rst_n;
+initial force dut.rst_smc_ni = rst_n;
+
+// Host TileLink interface connections
+`CONNECT_TL_HOST_IF(rv_core_ibex_sec__corei, dut, clk_main_i, rst_n)
+`CONNECT_TL_HOST_IF(rv_core_ibex_sec__cored, dut, clk_main_i, rst_n)
+`CONNECT_TL_HOST_IF(rv_dm__sba, dut, clk_main_i, rst_n)
+`CONNECT_TL_HOST_IF(dma0__reader, dut, clk_main_i, rst_n)
+`CONNECT_TL_HOST_IF(dma0__writer, dut, clk_main_i, rst_n)
+
+// Device TileLink interface connections
+`CONNECT_TL_DEVICE_IF(dma0, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rom_ctrl__rom, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rom_ctrl__regs, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_spi_host0_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_spi_host1_i, rst_n)
+`CONNECT_TL_DEVICE_IF(usbdev, dut, clk_usb_i, rst_n)
+`CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(entropy_src, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(csrng, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(keymgr, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_core_ibex_sec__cfg, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sram_ctrl_main__ram, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(tlul_mailbox_sec, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(smc, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(dbg, dut, clk_main_i, rst_n)
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cov_excl.el b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cov_excl.el
new file mode 100644
index 0000000..585ef7c
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cov_excl.el
@@ -0,0 +1,36 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cov_excl.el generated by `tlgen.py` tool
+
+ANNOTATION: "[NON_RTL]"
+MODULE: uvm_pkg
+Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion"
+Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion"
+
+ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim"
+MODULE: xbar_main
+Block 1 "0" "assign unused_scanmode = scanmode_i;"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_fifo_sync
+Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=3,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=4,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=5,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cover.cfg
new file mode 100644
index 0000000..d70a0ae
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -0,0 +1,120 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cover.cfg generated by `tlgen.py` tool
+
++tree tb.dut
+-module pins_if // DV construct.
+-module clk_rst_if // DV construct.
+
+-assert legalAOpcodeErr_A
+-assert sizeGTEMaskErr_A
+-assert sizeMatchesMaskErr_A
+-assert addrSizeAlignedErr_A
+
+// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after.
+-node tb.dut tl_*.a_param
+-node tb.dut tl_*.d_param
+-node tb.dut tl_*.d_opcode[2:1]
+
+// [UNR] these device address bits are always 0
+-node tb.dut tl_dma0_o.a_address[20:6]
+-node tb.dut tl_dma0_o.a_address[29:22]
+-node tb.dut tl_dma0_o.a_address[31:31]
+-node tb.dut tl_rom_ctrl__rom_o.a_address[31:16]
+-node tb.dut tl_rom_ctrl__regs_o.a_address[16:7]
+-node tb.dut tl_rom_ctrl__regs_o.a_address[23:21]
+-node tb.dut tl_rom_ctrl__regs_o.a_address[29:25]
+-node tb.dut tl_rom_ctrl__regs_o.a_address[31:31]
+-node tb.dut tl_peri_o.a_address[29:23]
+-node tb.dut tl_peri_o.a_address[31:31]
+-node tb.dut tl_spi_host0_o.a_address[19:6]
+-node tb.dut tl_spi_host0_o.a_address[29:22]
+-node tb.dut tl_spi_host0_o.a_address[31:31]
+-node tb.dut tl_spi_host1_o.a_address[15:6]
+-node tb.dut tl_spi_host1_o.a_address[19:17]
+-node tb.dut tl_spi_host1_o.a_address[29:22]
+-node tb.dut tl_spi_host1_o.a_address[31:31]
+-node tb.dut tl_usbdev_o.a_address[16:12]
+-node tb.dut tl_usbdev_o.a_address[19:18]
+-node tb.dut tl_usbdev_o.a_address[29:22]
+-node tb.dut tl_usbdev_o.a_address[31:31]
+-node tb.dut tl_flash_ctrl__core_o.a_address[23:9]
+-node tb.dut tl_flash_ctrl__core_o.a_address[29:25]
+-node tb.dut tl_flash_ctrl__core_o.a_address[31:31]
+-node tb.dut tl_flash_ctrl__prim_o.a_address[14:7]
+-node tb.dut tl_flash_ctrl__prim_o.a_address[23:16]
+-node tb.dut tl_flash_ctrl__prim_o.a_address[29:25]
+-node tb.dut tl_flash_ctrl__prim_o.a_address[31:31]
+-node tb.dut tl_flash_ctrl__mem_o.a_address[28:20]
+-node tb.dut tl_flash_ctrl__mem_o.a_address[31:30]
+-node tb.dut tl_hmac_o.a_address[15:12]
+-node tb.dut tl_hmac_o.a_address[19:17]
+-node tb.dut tl_hmac_o.a_address[23:21]
+-node tb.dut tl_hmac_o.a_address[29:25]
+-node tb.dut tl_hmac_o.a_address[31:31]
+-node tb.dut tl_kmac_o.a_address[16:12]
+-node tb.dut tl_kmac_o.a_address[19:18]
+-node tb.dut tl_kmac_o.a_address[23:21]
+-node tb.dut tl_kmac_o.a_address[29:25]
+-node tb.dut tl_kmac_o.a_address[31:31]
+-node tb.dut tl_aes_o.a_address[19:8]
+-node tb.dut tl_aes_o.a_address[23:21]
+-node tb.dut tl_aes_o.a_address[29:25]
+-node tb.dut tl_aes_o.a_address[31:31]
+-node tb.dut tl_entropy_src_o.a_address[16:8]
+-node tb.dut tl_entropy_src_o.a_address[19:19]
+-node tb.dut tl_entropy_src_o.a_address[23:21]
+-node tb.dut tl_entropy_src_o.a_address[29:25]
+-node tb.dut tl_entropy_src_o.a_address[31:31]
+-node tb.dut tl_csrng_o.a_address[15:7]
+-node tb.dut tl_csrng_o.a_address[17:17]
+-node tb.dut tl_csrng_o.a_address[19:19]
+-node tb.dut tl_csrng_o.a_address[23:21]
+-node tb.dut tl_csrng_o.a_address[29:25]
+-node tb.dut tl_csrng_o.a_address[31:31]
+-node tb.dut tl_edn0_o.a_address[15:7]
+-node tb.dut tl_edn0_o.a_address[19:19]
+-node tb.dut tl_edn0_o.a_address[23:21]
+-node tb.dut tl_edn0_o.a_address[29:25]
+-node tb.dut tl_edn0_o.a_address[31:31]
+-node tb.dut tl_edn1_o.a_address[18:7]
+-node tb.dut tl_edn1_o.a_address[23:21]
+-node tb.dut tl_edn1_o.a_address[29:25]
+-node tb.dut tl_edn1_o.a_address[31:31]
+-node tb.dut tl_rv_plic_o.a_address[29:28]
+-node tb.dut tl_rv_plic_o.a_address[31:31]
+-node tb.dut tl_otbn_o.a_address[19:18]
+-node tb.dut tl_otbn_o.a_address[23:21]
+-node tb.dut tl_otbn_o.a_address[29:25]
+-node tb.dut tl_otbn_o.a_address[31:31]
+-node tb.dut tl_keymgr_o.a_address[17:8]
+-node tb.dut tl_keymgr_o.a_address[19:19]
+-node tb.dut tl_keymgr_o.a_address[23:21]
+-node tb.dut tl_keymgr_o.a_address[29:25]
+-node tb.dut tl_keymgr_o.a_address[31:31]
+-node tb.dut tl_rv_core_ibex_sec__cfg_o.a_address[15:8]
+-node tb.dut tl_rv_core_ibex_sec__cfg_o.a_address[23:21]
+-node tb.dut tl_rv_core_ibex_sec__cfg_o.a_address[29:25]
+-node tb.dut tl_rv_core_ibex_sec__cfg_o.a_address[31:31]
+-node tb.dut tl_sram_ctrl_main__regs_o.a_address[17:5]
+-node tb.dut tl_sram_ctrl_main__regs_o.a_address[23:21]
+-node tb.dut tl_sram_ctrl_main__regs_o.a_address[29:25]
+-node tb.dut tl_sram_ctrl_main__regs_o.a_address[31:31]
+-node tb.dut tl_sram_ctrl_main__ram_o.a_address[27:17]
+-node tb.dut tl_sram_ctrl_main__ram_o.a_address[31:29]
+-node tb.dut tl_tlul_mailbox_sec_o.a_address[22:6]
+-node tb.dut tl_tlul_mailbox_sec_o.a_address[29:24]
+-node tb.dut tl_tlul_mailbox_sec_o.a_address[31:31]
+-node tb.dut tl_smc_o.a_address[29:29]
+-node tb.dut tl_smc_o.a_address[31:31]
+-node tb.dut tl_dbg_o.a_address[31:15]
+
+-node tb.dut tl_*.a_source[7:5]
+-node tb.dut tl_*.d_source[7:5]
+begin tgl
+ -tree tb
+ +tree tb.dut 1
+ -node tb.dut.scanmode_i
+end
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
new file mode 100644
index 0000000..3e8eb12
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -0,0 +1,164 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `tlgen.py` tool
+
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+ '{"dma0", '{
+ '{32'h40200000, 32'h4020003f}
+ }},
+ '{"rom_ctrl__rom", '{
+ '{32'h00008000, 32'h0000ffff}
+ }},
+ '{"rom_ctrl__regs", '{
+ '{32'h411e0000, 32'h411e007f}
+ }},
+ '{"peri", '{
+ '{32'h40000000, 32'h401fffff},
+ '{32'h40400000, 32'h407fffff}
+ }},
+ '{"spi_host0", '{
+ '{32'h40300000, 32'h4030003f}
+ }},
+ '{"spi_host1", '{
+ '{32'h40310000, 32'h4031003f}
+ }},
+ '{"usbdev", '{
+ '{32'h40320000, 32'h40320fff}
+ }},
+ '{"flash_ctrl__core", '{
+ '{32'h41000000, 32'h410001ff}
+ }},
+ '{"flash_ctrl__prim", '{
+ '{32'h41008000, 32'h4100807f}
+ }},
+ '{"flash_ctrl__mem", '{
+ '{32'h20000000, 32'h200fffff}
+ }},
+ '{"hmac", '{
+ '{32'h41110000, 32'h41110fff}
+ }},
+ '{"kmac", '{
+ '{32'h41120000, 32'h41120fff}
+ }},
+ '{"aes", '{
+ '{32'h41100000, 32'h411000ff}
+ }},
+ '{"entropy_src", '{
+ '{32'h41160000, 32'h411600ff}
+ }},
+ '{"csrng", '{
+ '{32'h41150000, 32'h4115007f}
+ }},
+ '{"edn0", '{
+ '{32'h41170000, 32'h4117007f}
+ }},
+ '{"edn1", '{
+ '{32'h41180000, 32'h4118007f}
+ }},
+ '{"rv_plic", '{
+ '{32'h48000000, 32'h4fffffff}
+ }},
+ '{"otbn", '{
+ '{32'h41130000, 32'h4113ffff}
+ }},
+ '{"keymgr", '{
+ '{32'h41140000, 32'h411400ff}
+ }},
+ '{"rv_core_ibex_sec__cfg", '{
+ '{32'h411f0000, 32'h411f00ff}
+ }},
+ '{"sram_ctrl_main__regs", '{
+ '{32'h411c0000, 32'h411c001f}
+ }},
+ '{"sram_ctrl_main__ram", '{
+ '{32'h10000000, 32'h1001ffff}
+ }},
+ '{"tlul_mailbox_sec", '{
+ '{32'h40800000, 32'h4080003f}
+ }},
+ '{"smc", '{
+ '{32'h50000000, 32'h5fffffff}
+ }},
+ '{"dbg", '{
+ '{32'h00004000, 32'h00007fff}
+}}};
+
+ // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+ '{"rv_core_ibex_sec__corei", 0, '{
+ "rom_ctrl__rom",
+ "dbg",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem"}}
+ ,
+ '{"rv_core_ibex_sec__cored", 1, '{
+ "rom_ctrl__rom",
+ "rom_ctrl__regs",
+ "dbg",
+ "sram_ctrl_main__ram",
+ "peri",
+ "spi_host0",
+ "spi_host1",
+ "usbdev",
+ "flash_ctrl__core",
+ "flash_ctrl__prim",
+ "flash_ctrl__mem",
+ "aes",
+ "entropy_src",
+ "csrng",
+ "edn0",
+ "edn1",
+ "hmac",
+ "rv_plic",
+ "otbn",
+ "keymgr",
+ "kmac",
+ "sram_ctrl_main__regs",
+ "rv_core_ibex_sec__cfg",
+ "smc",
+ "tlul_mailbox_sec",
+ "dma0"}}
+ ,
+ '{"rv_dm__sba", 2, '{
+ "dbg",
+ "rom_ctrl__rom",
+ "rom_ctrl__regs",
+ "peri",
+ "spi_host0",
+ "spi_host1",
+ "usbdev",
+ "flash_ctrl__core",
+ "flash_ctrl__prim",
+ "flash_ctrl__mem",
+ "hmac",
+ "kmac",
+ "aes",
+ "entropy_src",
+ "csrng",
+ "edn0",
+ "edn1",
+ "rv_plic",
+ "otbn",
+ "keymgr",
+ "rv_core_ibex_sec__cfg",
+ "sram_ctrl_main__regs",
+ "sram_ctrl_main__ram",
+ "smc",
+ "tlul_mailbox_sec"}}
+ ,
+ '{"dma0__reader", 3, '{
+ "rom_ctrl__rom",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem",
+ "smc"}}
+ ,
+ '{"dma0__writer", 4, '{
+ "rom_ctrl__rom",
+ "sram_ctrl_main__ram",
+ "flash_ctrl__mem",
+ "smc"}}
+};
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.core b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.core
new file mode 100644
index 0000000..59e3d90
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_main_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_main_bind:0.1"
+description: "XBAR main assertion bind"
+filesets:
+ files_dv:
+ files:
+ - xbar_main_bind.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.sv
new file mode 100644
index 0000000..73b6102
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -0,0 +1,198 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_main_bind module generated by `tlgen.py` tool for assertions
+module xbar_main_bind;
+
+ // Host interfaces
+ bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex_sec__corei (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_core_ibex_sec__corei_i),
+ .d2h (tl_rv_core_ibex_sec__corei_o)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex_sec__cored (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_core_ibex_sec__cored_i),
+ .d2h (tl_rv_core_ibex_sec__cored_o)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_dm__sba (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_dm__sba_i),
+ .d2h (tl_rv_dm__sba_o)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma0__reader (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_dma0__reader_i),
+ .d2h (tl_dma0__reader_o)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma0__writer (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_dma0__writer_i),
+ .d2h (tl_dma0__writer_o)
+ );
+
+ // Device interfaces
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_dma0 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_dma0_o),
+ .d2h (tl_dma0_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl__rom (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rom_ctrl__rom_o),
+ .d2h (tl_rom_ctrl__rom_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl__regs (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rom_ctrl__regs_o),
+ .d2h (tl_rom_ctrl__regs_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_peri (
+ .clk_i (clk_fixed_i),
+ .rst_ni (rst_fixed_ni),
+ .h2d (tl_peri_o),
+ .d2h (tl_peri_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 (
+ .clk_i (clk_spi_host0_i),
+ .rst_ni (rst_spi_host0_ni),
+ .h2d (tl_spi_host0_o),
+ .d2h (tl_spi_host0_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host1 (
+ .clk_i (clk_spi_host1_i),
+ .rst_ni (rst_spi_host1_ni),
+ .h2d (tl_spi_host1_o),
+ .d2h (tl_spi_host1_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_usbdev (
+ .clk_i (clk_usb_i),
+ .rst_ni (rst_usb_ni),
+ .h2d (tl_usbdev_o),
+ .d2h (tl_usbdev_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__core (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_flash_ctrl__core_o),
+ .d2h (tl_flash_ctrl__core_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__prim (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_flash_ctrl__prim_o),
+ .d2h (tl_flash_ctrl__prim_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__mem (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_flash_ctrl__mem_o),
+ .d2h (tl_flash_ctrl__mem_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_hmac_o),
+ .d2h (tl_hmac_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_kmac (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_kmac_o),
+ .d2h (tl_kmac_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_aes (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_aes_o),
+ .d2h (tl_aes_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_entropy_src (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_entropy_src_o),
+ .d2h (tl_entropy_src_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_csrng (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_csrng_o),
+ .d2h (tl_csrng_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn0 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_edn0_o),
+ .d2h (tl_edn0_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn1 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_edn1_o),
+ .d2h (tl_edn1_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_plic (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_plic_o),
+ .d2h (tl_rv_plic_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_otbn_o),
+ .d2h (tl_otbn_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_keymgr_o),
+ .d2h (tl_keymgr_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_core_ibex_sec__cfg (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_rv_core_ibex_sec__cfg_o),
+ .d2h (tl_rv_core_ibex_sec__cfg_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__regs (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_sram_ctrl_main__regs_o),
+ .d2h (tl_sram_ctrl_main__regs_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__ram (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_sram_ctrl_main__ram_o),
+ .d2h (tl_sram_ctrl_main__ram_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_tlul_mailbox_sec (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_tlul_mailbox_sec_o),
+ .d2h (tl_tlul_mailbox_sec_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_smc (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_smc_o),
+ .d2h (tl_smc_i)
+ );
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_dbg (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_dbg_o),
+ .d2h (tl_dbg_i)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim.core b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim.core
new file mode 100644
index 0000000..93a0d48
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim.core
@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_main_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_main_sim:0.1"
+description: "XBAR DV sim target"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:top_sencha:xbar_main
+ - lowrisc:dv:dv_utils
+ - lowrisc:dv:xbar_tb
+ - lowrisc:dv:top_sencha_xbar_main_bind
+ files:
+ - tb__xbar_connect.sv: {is_include_file: true}
+ - xbar_env_pkg__params.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+
+targets:
+ sim: &sim_target
+ toplevel: xbar_tb_top
+ filesets:
+ - files_dv
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson
new file mode 100644
index 0000000..41e42f0
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_main_sim_cfg.hjson file generated by `tlgen.py` tool
+{
+ name: xbar_main
+
+ // Top level dut name (sv module).
+ dut: xbar_main
+
+ // The name of the chip this XBAR configuration is made for.
+ top_chip: top_sencha
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson"
+
+ // Add xbar_main specific exclusion files.
+ vcs_cov_excl_files: ["{proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cov_excl.el"]
+
+ // replace common cover.cfg with a generated one, which includes xbar toggle exclusions
+ overrides: [
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cover.cfg"
+ }
+ ]
+ // Import additional common sim cfg files.
+ import_cfgs: [// xbar common sim cfg file
+ "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"]
+}
diff --git a/hw/top_sencha/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_sencha/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
new file mode 100644
index 0000000..a812466
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -0,0 +1,117 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tl_main package generated by `tlgen.py` tool
+
+package tl_main_pkg;
+
+ localparam logic [31:0] ADDR_SPACE_DMA0 = 32'h 40200000;
+ localparam logic [31:0] ADDR_SPACE_ROM_CTRL__ROM = 32'h 00008000;
+ localparam logic [31:0] ADDR_SPACE_ROM_CTRL__REGS = 32'h 411e0000;
+ localparam logic [1:0][31:0] ADDR_SPACE_PERI = {
+ 32'h 40400000,
+ 32'h 40000000
+ };
+ localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 40300000;
+ localparam logic [31:0] ADDR_SPACE_SPI_HOST1 = 32'h 40310000;
+ localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40320000;
+ localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000;
+ localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000;
+ localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000;
+ localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 41110000;
+ localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 41120000;
+ localparam logic [31:0] ADDR_SPACE_AES = 32'h 41100000;
+ localparam logic [31:0] ADDR_SPACE_ENTROPY_SRC = 32'h 41160000;
+ localparam logic [31:0] ADDR_SPACE_CSRNG = 32'h 41150000;
+ localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 41170000;
+ localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 41180000;
+ localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 48000000;
+ localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 41130000;
+ localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 41140000;
+ localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX_SEC__CFG = 32'h 411f0000;
+ localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 411c0000;
+ localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__RAM = 32'h 10000000;
+ localparam logic [31:0] ADDR_SPACE_TLUL_MAILBOX_SEC = 32'h 40800000;
+ localparam logic [0:0][31:0] ADDR_SPACE_SMC = {
+ 32'h 50000000
+ };
+ localparam logic [0:0][31:0] ADDR_SPACE_DBG = {
+ 32'h 00004000
+ };
+
+ localparam logic [31:0] ADDR_MASK_DMA0 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_ROM_CTRL__ROM = 32'h 00007fff;
+ localparam logic [31:0] ADDR_MASK_ROM_CTRL__REGS = 32'h 0000007f;
+ localparam logic [1:0][31:0] ADDR_MASK_PERI = {
+ 32'h 003fffff,
+ 32'h 001fffff
+ };
+ localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_SPI_HOST1 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 000001ff;
+ localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 000fffff;
+ localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_ENTROPY_SRC = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_CSRNG = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff;
+ localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff;
+ localparam logic [31:0] ADDR_MASK_KEYMGR = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX_SEC__CFG = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000001f;
+ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0001ffff;
+ localparam logic [31:0] ADDR_MASK_TLUL_MAILBOX_SEC = 32'h 0000003f;
+ localparam logic [0:0][31:0] ADDR_MASK_SMC = {
+ 32'h 0fffffff
+ };
+ localparam logic [0:0][31:0] ADDR_MASK_DBG = {
+ 32'h 00003fff
+ };
+
+ localparam int N_HOST = 5;
+ localparam int N_DEVICE = 26;
+
+ typedef enum int {
+ TlDma0 = 0,
+ TlRomCtrlRom = 1,
+ TlRomCtrlRegs = 2,
+ TlPeri = 3,
+ TlSpiHost0 = 4,
+ TlSpiHost1 = 5,
+ TlUsbdev = 6,
+ TlFlashCtrlCore = 7,
+ TlFlashCtrlPrim = 8,
+ TlFlashCtrlMem = 9,
+ TlHmac = 10,
+ TlKmac = 11,
+ TlAes = 12,
+ TlEntropySrc = 13,
+ TlCsrng = 14,
+ TlEdn0 = 15,
+ TlEdn1 = 16,
+ TlRvPlic = 17,
+ TlOtbn = 18,
+ TlKeymgr = 19,
+ TlRvCoreIbexSecCfg = 20,
+ TlSramCtrlMainRegs = 21,
+ TlSramCtrlMainRam = 22,
+ TlTlulMailboxSec = 23,
+ TlSmc = 24,
+ TlDbg = 25
+ } tl_device_e;
+
+ typedef enum int {
+ TlRvCoreIbexSecCorei = 0,
+ TlRvCoreIbexSecCored = 1,
+ TlRvDmSba = 2,
+ TlDma0Reader = 3,
+ TlDma0Writer = 4
+ } tl_host_e;
+
+endpackage
diff --git a/hw/top_sencha/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_sencha/ip/xbar_main/rtl/autogen/xbar_main.sv
new file mode 100644
index 0000000..3347f11
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -0,0 +1,1567 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_main module generated by `tlgen.py` tool
+// all reset signals should be generated from one reset signal to not make any deadlock
+//
+// Interconnect
+// rv_core_ibex_sec.corei
+// -> s1n_31
+// -> sm1_32
+// -> rom_ctrl.rom
+// -> sm1_33
+// -> dbg
+// -> sm1_34
+// -> sram_ctrl_main.ram
+// -> sm1_35
+// -> flash_ctrl.mem
+// rv_core_ibex_sec.cored
+// -> s1n_36
+// -> sm1_32
+// -> rom_ctrl.rom
+// -> sm1_37
+// -> rom_ctrl.regs
+// -> sm1_33
+// -> dbg
+// -> sm1_34
+// -> sram_ctrl_main.ram
+// -> sm1_39
+// -> asf_38
+// -> peri
+// -> sm1_41
+// -> asf_40
+// -> spi_host0
+// -> sm1_43
+// -> asf_42
+// -> spi_host1
+// -> sm1_45
+// -> asf_44
+// -> usbdev
+// -> sm1_46
+// -> flash_ctrl.core
+// -> sm1_47
+// -> flash_ctrl.prim
+// -> sm1_35
+// -> flash_ctrl.mem
+// -> sm1_48
+// -> aes
+// -> sm1_49
+// -> entropy_src
+// -> sm1_50
+// -> csrng
+// -> sm1_51
+// -> edn0
+// -> sm1_52
+// -> edn1
+// -> sm1_53
+// -> hmac
+// -> sm1_54
+// -> rv_plic
+// -> sm1_55
+// -> otbn
+// -> sm1_56
+// -> keymgr
+// -> sm1_57
+// -> kmac
+// -> sm1_58
+// -> sram_ctrl_main.regs
+// -> sm1_59
+// -> rv_core_ibex_sec.cfg
+// -> sm1_61
+// -> asf_60
+// -> smc
+// -> sm1_62
+// -> tlul_mailbox_sec
+// -> dma0
+// rv_dm.sba
+// -> s1n_63
+// -> sm1_33
+// -> dbg
+// -> sm1_32
+// -> rom_ctrl.rom
+// -> sm1_37
+// -> rom_ctrl.regs
+// -> sm1_39
+// -> asf_38
+// -> peri
+// -> sm1_41
+// -> asf_40
+// -> spi_host0
+// -> sm1_43
+// -> asf_42
+// -> spi_host1
+// -> sm1_45
+// -> asf_44
+// -> usbdev
+// -> sm1_46
+// -> flash_ctrl.core
+// -> sm1_47
+// -> flash_ctrl.prim
+// -> sm1_35
+// -> flash_ctrl.mem
+// -> sm1_53
+// -> hmac
+// -> sm1_57
+// -> kmac
+// -> sm1_48
+// -> aes
+// -> sm1_49
+// -> entropy_src
+// -> sm1_50
+// -> csrng
+// -> sm1_51
+// -> edn0
+// -> sm1_52
+// -> edn1
+// -> sm1_54
+// -> rv_plic
+// -> sm1_55
+// -> otbn
+// -> sm1_56
+// -> keymgr
+// -> sm1_59
+// -> rv_core_ibex_sec.cfg
+// -> sm1_58
+// -> sram_ctrl_main.regs
+// -> sm1_34
+// -> sram_ctrl_main.ram
+// -> sm1_61
+// -> asf_60
+// -> smc
+// -> sm1_62
+// -> tlul_mailbox_sec
+// dma0.reader
+// -> s1n_64
+// -> sm1_32
+// -> rom_ctrl.rom
+// -> sm1_34
+// -> sram_ctrl_main.ram
+// -> sm1_35
+// -> flash_ctrl.mem
+// -> sm1_61
+// -> asf_60
+// -> smc
+// dma0.writer
+// -> s1n_65
+// -> sm1_32
+// -> rom_ctrl.rom
+// -> sm1_34
+// -> sram_ctrl_main.ram
+// -> sm1_35
+// -> flash_ctrl.mem
+// -> sm1_61
+// -> asf_60
+// -> smc
+
+module xbar_main (
+ input clk_main_i,
+ input clk_fixed_i,
+ input clk_usb_i,
+ input clk_spi_host0_i,
+ input clk_spi_host1_i,
+ input clk_smc_i,
+ input rst_main_ni,
+ input rst_fixed_ni,
+ input rst_usb_ni,
+ input rst_spi_host0_ni,
+ input rst_spi_host1_ni,
+ input rst_smc_ni,
+
+ // Host interfaces
+ input tlul_pkg::tl_h2d_t tl_rv_core_ibex_sec__corei_i,
+ output tlul_pkg::tl_d2h_t tl_rv_core_ibex_sec__corei_o,
+ input tlul_pkg::tl_h2d_t tl_rv_core_ibex_sec__cored_i,
+ output tlul_pkg::tl_d2h_t tl_rv_core_ibex_sec__cored_o,
+ input tlul_pkg::tl_h2d_t tl_rv_dm__sba_i,
+ output tlul_pkg::tl_d2h_t tl_rv_dm__sba_o,
+ input tlul_pkg::tl_h2d_t tl_dma0__reader_i,
+ output tlul_pkg::tl_d2h_t tl_dma0__reader_o,
+ input tlul_pkg::tl_h2d_t tl_dma0__writer_i,
+ output tlul_pkg::tl_d2h_t tl_dma0__writer_o,
+
+ // Device interfaces
+ output tlul_pkg::tl_h2d_t tl_dma0_o,
+ input tlul_pkg::tl_d2h_t tl_dma0_i,
+ output tlul_pkg::tl_h2d_t tl_rom_ctrl__rom_o,
+ input tlul_pkg::tl_d2h_t tl_rom_ctrl__rom_i,
+ output tlul_pkg::tl_h2d_t tl_rom_ctrl__regs_o,
+ input tlul_pkg::tl_d2h_t tl_rom_ctrl__regs_i,
+ output tlul_pkg::tl_h2d_t tl_peri_o,
+ input tlul_pkg::tl_d2h_t tl_peri_i,
+ output tlul_pkg::tl_h2d_t tl_spi_host0_o,
+ input tlul_pkg::tl_d2h_t tl_spi_host0_i,
+ output tlul_pkg::tl_h2d_t tl_spi_host1_o,
+ input tlul_pkg::tl_d2h_t tl_spi_host1_i,
+ output tlul_pkg::tl_h2d_t tl_usbdev_o,
+ input tlul_pkg::tl_d2h_t tl_usbdev_i,
+ output tlul_pkg::tl_h2d_t tl_flash_ctrl__core_o,
+ input tlul_pkg::tl_d2h_t tl_flash_ctrl__core_i,
+ output tlul_pkg::tl_h2d_t tl_flash_ctrl__prim_o,
+ input tlul_pkg::tl_d2h_t tl_flash_ctrl__prim_i,
+ output tlul_pkg::tl_h2d_t tl_flash_ctrl__mem_o,
+ input tlul_pkg::tl_d2h_t tl_flash_ctrl__mem_i,
+ output tlul_pkg::tl_h2d_t tl_hmac_o,
+ input tlul_pkg::tl_d2h_t tl_hmac_i,
+ output tlul_pkg::tl_h2d_t tl_kmac_o,
+ input tlul_pkg::tl_d2h_t tl_kmac_i,
+ output tlul_pkg::tl_h2d_t tl_aes_o,
+ input tlul_pkg::tl_d2h_t tl_aes_i,
+ output tlul_pkg::tl_h2d_t tl_entropy_src_o,
+ input tlul_pkg::tl_d2h_t tl_entropy_src_i,
+ output tlul_pkg::tl_h2d_t tl_csrng_o,
+ input tlul_pkg::tl_d2h_t tl_csrng_i,
+ output tlul_pkg::tl_h2d_t tl_edn0_o,
+ input tlul_pkg::tl_d2h_t tl_edn0_i,
+ output tlul_pkg::tl_h2d_t tl_edn1_o,
+ input tlul_pkg::tl_d2h_t tl_edn1_i,
+ output tlul_pkg::tl_h2d_t tl_rv_plic_o,
+ input tlul_pkg::tl_d2h_t tl_rv_plic_i,
+ output tlul_pkg::tl_h2d_t tl_otbn_o,
+ input tlul_pkg::tl_d2h_t tl_otbn_i,
+ output tlul_pkg::tl_h2d_t tl_keymgr_o,
+ input tlul_pkg::tl_d2h_t tl_keymgr_i,
+ output tlul_pkg::tl_h2d_t tl_rv_core_ibex_sec__cfg_o,
+ input tlul_pkg::tl_d2h_t tl_rv_core_ibex_sec__cfg_i,
+ output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__regs_o,
+ input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__regs_i,
+ output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__ram_o,
+ input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__ram_i,
+ output tlul_pkg::tl_h2d_t tl_tlul_mailbox_sec_o,
+ input tlul_pkg::tl_d2h_t tl_tlul_mailbox_sec_i,
+ output tlul_pkg::tl_h2d_t tl_smc_o,
+ input tlul_pkg::tl_d2h_t tl_smc_i,
+ output tlul_pkg::tl_h2d_t tl_dbg_o,
+ input tlul_pkg::tl_d2h_t tl_dbg_i,
+
+ input prim_mubi_pkg::mubi4_t scanmode_i
+);
+
+ import tlul_pkg::*;
+ import tl_main_pkg::*;
+
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = ^scanmode_i;
+
+ tl_h2d_t tl_s1n_31_us_h2d ;
+ tl_d2h_t tl_s1n_31_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_31_ds_h2d [4];
+ tl_d2h_t tl_s1n_31_ds_d2h [4];
+
+ // Create steering signal
+ logic [2:0] dev_sel_s1n_31;
+
+
+ tl_h2d_t tl_sm1_32_us_h2d [5];
+ tl_d2h_t tl_sm1_32_us_d2h [5];
+
+ tl_h2d_t tl_sm1_32_ds_h2d ;
+ tl_d2h_t tl_sm1_32_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_33_us_h2d [3];
+ tl_d2h_t tl_sm1_33_us_d2h [3];
+
+ tl_h2d_t tl_sm1_33_ds_h2d ;
+ tl_d2h_t tl_sm1_33_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_34_us_h2d [5];
+ tl_d2h_t tl_sm1_34_us_d2h [5];
+
+ tl_h2d_t tl_sm1_34_ds_h2d ;
+ tl_d2h_t tl_sm1_34_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_35_us_h2d [5];
+ tl_d2h_t tl_sm1_35_us_d2h [5];
+
+ tl_h2d_t tl_sm1_35_ds_h2d ;
+ tl_d2h_t tl_sm1_35_ds_d2h ;
+
+ tl_h2d_t tl_s1n_36_us_h2d ;
+ tl_d2h_t tl_s1n_36_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_36_ds_h2d [26];
+ tl_d2h_t tl_s1n_36_ds_d2h [26];
+
+ // Create steering signal
+ logic [4:0] dev_sel_s1n_36;
+
+
+ tl_h2d_t tl_sm1_37_us_h2d [2];
+ tl_d2h_t tl_sm1_37_us_d2h [2];
+
+ tl_h2d_t tl_sm1_37_ds_h2d ;
+ tl_d2h_t tl_sm1_37_ds_d2h ;
+
+ tl_h2d_t tl_asf_38_us_h2d ;
+ tl_d2h_t tl_asf_38_us_d2h ;
+ tl_h2d_t tl_asf_38_ds_h2d ;
+ tl_d2h_t tl_asf_38_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_39_us_h2d [2];
+ tl_d2h_t tl_sm1_39_us_d2h [2];
+
+ tl_h2d_t tl_sm1_39_ds_h2d ;
+ tl_d2h_t tl_sm1_39_ds_d2h ;
+
+ tl_h2d_t tl_asf_40_us_h2d ;
+ tl_d2h_t tl_asf_40_us_d2h ;
+ tl_h2d_t tl_asf_40_ds_h2d ;
+ tl_d2h_t tl_asf_40_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_41_us_h2d [2];
+ tl_d2h_t tl_sm1_41_us_d2h [2];
+
+ tl_h2d_t tl_sm1_41_ds_h2d ;
+ tl_d2h_t tl_sm1_41_ds_d2h ;
+
+ tl_h2d_t tl_asf_42_us_h2d ;
+ tl_d2h_t tl_asf_42_us_d2h ;
+ tl_h2d_t tl_asf_42_ds_h2d ;
+ tl_d2h_t tl_asf_42_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_43_us_h2d [2];
+ tl_d2h_t tl_sm1_43_us_d2h [2];
+
+ tl_h2d_t tl_sm1_43_ds_h2d ;
+ tl_d2h_t tl_sm1_43_ds_d2h ;
+
+ tl_h2d_t tl_asf_44_us_h2d ;
+ tl_d2h_t tl_asf_44_us_d2h ;
+ tl_h2d_t tl_asf_44_ds_h2d ;
+ tl_d2h_t tl_asf_44_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_45_us_h2d [2];
+ tl_d2h_t tl_sm1_45_us_d2h [2];
+
+ tl_h2d_t tl_sm1_45_ds_h2d ;
+ tl_d2h_t tl_sm1_45_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_46_us_h2d [2];
+ tl_d2h_t tl_sm1_46_us_d2h [2];
+
+ tl_h2d_t tl_sm1_46_ds_h2d ;
+ tl_d2h_t tl_sm1_46_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_47_us_h2d [2];
+ tl_d2h_t tl_sm1_47_us_d2h [2];
+
+ tl_h2d_t tl_sm1_47_ds_h2d ;
+ tl_d2h_t tl_sm1_47_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_48_us_h2d [2];
+ tl_d2h_t tl_sm1_48_us_d2h [2];
+
+ tl_h2d_t tl_sm1_48_ds_h2d ;
+ tl_d2h_t tl_sm1_48_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_49_us_h2d [2];
+ tl_d2h_t tl_sm1_49_us_d2h [2];
+
+ tl_h2d_t tl_sm1_49_ds_h2d ;
+ tl_d2h_t tl_sm1_49_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_50_us_h2d [2];
+ tl_d2h_t tl_sm1_50_us_d2h [2];
+
+ tl_h2d_t tl_sm1_50_ds_h2d ;
+ tl_d2h_t tl_sm1_50_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_51_us_h2d [2];
+ tl_d2h_t tl_sm1_51_us_d2h [2];
+
+ tl_h2d_t tl_sm1_51_ds_h2d ;
+ tl_d2h_t tl_sm1_51_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_52_us_h2d [2];
+ tl_d2h_t tl_sm1_52_us_d2h [2];
+
+ tl_h2d_t tl_sm1_52_ds_h2d ;
+ tl_d2h_t tl_sm1_52_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_53_us_h2d [2];
+ tl_d2h_t tl_sm1_53_us_d2h [2];
+
+ tl_h2d_t tl_sm1_53_ds_h2d ;
+ tl_d2h_t tl_sm1_53_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_54_us_h2d [2];
+ tl_d2h_t tl_sm1_54_us_d2h [2];
+
+ tl_h2d_t tl_sm1_54_ds_h2d ;
+ tl_d2h_t tl_sm1_54_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_55_us_h2d [2];
+ tl_d2h_t tl_sm1_55_us_d2h [2];
+
+ tl_h2d_t tl_sm1_55_ds_h2d ;
+ tl_d2h_t tl_sm1_55_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_56_us_h2d [2];
+ tl_d2h_t tl_sm1_56_us_d2h [2];
+
+ tl_h2d_t tl_sm1_56_ds_h2d ;
+ tl_d2h_t tl_sm1_56_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_57_us_h2d [2];
+ tl_d2h_t tl_sm1_57_us_d2h [2];
+
+ tl_h2d_t tl_sm1_57_ds_h2d ;
+ tl_d2h_t tl_sm1_57_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_58_us_h2d [2];
+ tl_d2h_t tl_sm1_58_us_d2h [2];
+
+ tl_h2d_t tl_sm1_58_ds_h2d ;
+ tl_d2h_t tl_sm1_58_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_59_us_h2d [2];
+ tl_d2h_t tl_sm1_59_us_d2h [2];
+
+ tl_h2d_t tl_sm1_59_ds_h2d ;
+ tl_d2h_t tl_sm1_59_ds_d2h ;
+
+ tl_h2d_t tl_asf_60_us_h2d ;
+ tl_d2h_t tl_asf_60_us_d2h ;
+ tl_h2d_t tl_asf_60_ds_h2d ;
+ tl_d2h_t tl_asf_60_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_61_us_h2d [4];
+ tl_d2h_t tl_sm1_61_us_d2h [4];
+
+ tl_h2d_t tl_sm1_61_ds_h2d ;
+ tl_d2h_t tl_sm1_61_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_62_us_h2d [2];
+ tl_d2h_t tl_sm1_62_us_d2h [2];
+
+ tl_h2d_t tl_sm1_62_ds_h2d ;
+ tl_d2h_t tl_sm1_62_ds_d2h ;
+
+ tl_h2d_t tl_s1n_63_us_h2d ;
+ tl_d2h_t tl_s1n_63_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_63_ds_h2d [25];
+ tl_d2h_t tl_s1n_63_ds_d2h [25];
+
+ // Create steering signal
+ logic [4:0] dev_sel_s1n_63;
+
+ tl_h2d_t tl_s1n_64_us_h2d ;
+ tl_d2h_t tl_s1n_64_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_64_ds_h2d [4];
+ tl_d2h_t tl_s1n_64_ds_d2h [4];
+
+ // Create steering signal
+ logic [2:0] dev_sel_s1n_64;
+
+ tl_h2d_t tl_s1n_65_us_h2d ;
+ tl_d2h_t tl_s1n_65_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_65_ds_h2d [4];
+ tl_d2h_t tl_s1n_65_ds_d2h [4];
+
+ // Create steering signal
+ logic [2:0] dev_sel_s1n_65;
+
+
+
+ assign tl_sm1_32_us_h2d[0] = tl_s1n_31_ds_h2d[0];
+ assign tl_s1n_31_ds_d2h[0] = tl_sm1_32_us_d2h[0];
+
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_31_ds_h2d[1];
+ assign tl_s1n_31_ds_d2h[1] = tl_sm1_33_us_d2h[0];
+
+ assign tl_sm1_34_us_h2d[0] = tl_s1n_31_ds_h2d[2];
+ assign tl_s1n_31_ds_d2h[2] = tl_sm1_34_us_d2h[0];
+
+ assign tl_sm1_35_us_h2d[0] = tl_s1n_31_ds_h2d[3];
+ assign tl_s1n_31_ds_d2h[3] = tl_sm1_35_us_d2h[0];
+
+ assign tl_sm1_32_us_h2d[1] = tl_s1n_36_ds_h2d[0];
+ assign tl_s1n_36_ds_d2h[0] = tl_sm1_32_us_d2h[1];
+
+ assign tl_sm1_37_us_h2d[0] = tl_s1n_36_ds_h2d[1];
+ assign tl_s1n_36_ds_d2h[1] = tl_sm1_37_us_d2h[0];
+
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_36_ds_h2d[2];
+ assign tl_s1n_36_ds_d2h[2] = tl_sm1_33_us_d2h[1];
+
+ assign tl_sm1_34_us_h2d[1] = tl_s1n_36_ds_h2d[3];
+ assign tl_s1n_36_ds_d2h[3] = tl_sm1_34_us_d2h[1];
+
+ assign tl_sm1_39_us_h2d[0] = tl_s1n_36_ds_h2d[4];
+ assign tl_s1n_36_ds_d2h[4] = tl_sm1_39_us_d2h[0];
+
+ assign tl_sm1_41_us_h2d[0] = tl_s1n_36_ds_h2d[5];
+ assign tl_s1n_36_ds_d2h[5] = tl_sm1_41_us_d2h[0];
+
+ assign tl_sm1_43_us_h2d[0] = tl_s1n_36_ds_h2d[6];
+ assign tl_s1n_36_ds_d2h[6] = tl_sm1_43_us_d2h[0];
+
+ assign tl_sm1_45_us_h2d[0] = tl_s1n_36_ds_h2d[7];
+ assign tl_s1n_36_ds_d2h[7] = tl_sm1_45_us_d2h[0];
+
+ assign tl_sm1_46_us_h2d[0] = tl_s1n_36_ds_h2d[8];
+ assign tl_s1n_36_ds_d2h[8] = tl_sm1_46_us_d2h[0];
+
+ assign tl_sm1_47_us_h2d[0] = tl_s1n_36_ds_h2d[9];
+ assign tl_s1n_36_ds_d2h[9] = tl_sm1_47_us_d2h[0];
+
+ assign tl_sm1_35_us_h2d[1] = tl_s1n_36_ds_h2d[10];
+ assign tl_s1n_36_ds_d2h[10] = tl_sm1_35_us_d2h[1];
+
+ assign tl_sm1_48_us_h2d[0] = tl_s1n_36_ds_h2d[11];
+ assign tl_s1n_36_ds_d2h[11] = tl_sm1_48_us_d2h[0];
+
+ assign tl_sm1_49_us_h2d[0] = tl_s1n_36_ds_h2d[12];
+ assign tl_s1n_36_ds_d2h[12] = tl_sm1_49_us_d2h[0];
+
+ assign tl_sm1_50_us_h2d[0] = tl_s1n_36_ds_h2d[13];
+ assign tl_s1n_36_ds_d2h[13] = tl_sm1_50_us_d2h[0];
+
+ assign tl_sm1_51_us_h2d[0] = tl_s1n_36_ds_h2d[14];
+ assign tl_s1n_36_ds_d2h[14] = tl_sm1_51_us_d2h[0];
+
+ assign tl_sm1_52_us_h2d[0] = tl_s1n_36_ds_h2d[15];
+ assign tl_s1n_36_ds_d2h[15] = tl_sm1_52_us_d2h[0];
+
+ assign tl_sm1_53_us_h2d[0] = tl_s1n_36_ds_h2d[16];
+ assign tl_s1n_36_ds_d2h[16] = tl_sm1_53_us_d2h[0];
+
+ assign tl_sm1_54_us_h2d[0] = tl_s1n_36_ds_h2d[17];
+ assign tl_s1n_36_ds_d2h[17] = tl_sm1_54_us_d2h[0];
+
+ assign tl_sm1_55_us_h2d[0] = tl_s1n_36_ds_h2d[18];
+ assign tl_s1n_36_ds_d2h[18] = tl_sm1_55_us_d2h[0];
+
+ assign tl_sm1_56_us_h2d[0] = tl_s1n_36_ds_h2d[19];
+ assign tl_s1n_36_ds_d2h[19] = tl_sm1_56_us_d2h[0];
+
+ assign tl_sm1_57_us_h2d[0] = tl_s1n_36_ds_h2d[20];
+ assign tl_s1n_36_ds_d2h[20] = tl_sm1_57_us_d2h[0];
+
+ assign tl_sm1_58_us_h2d[0] = tl_s1n_36_ds_h2d[21];
+ assign tl_s1n_36_ds_d2h[21] = tl_sm1_58_us_d2h[0];
+
+ assign tl_sm1_59_us_h2d[0] = tl_s1n_36_ds_h2d[22];
+ assign tl_s1n_36_ds_d2h[22] = tl_sm1_59_us_d2h[0];
+
+ assign tl_sm1_61_us_h2d[0] = tl_s1n_36_ds_h2d[23];
+ assign tl_s1n_36_ds_d2h[23] = tl_sm1_61_us_d2h[0];
+
+ assign tl_sm1_62_us_h2d[0] = tl_s1n_36_ds_h2d[24];
+ assign tl_s1n_36_ds_d2h[24] = tl_sm1_62_us_d2h[0];
+
+ assign tl_dma0_o = tl_s1n_36_ds_h2d[25];
+ assign tl_s1n_36_ds_d2h[25] = tl_dma0_i;
+
+ assign tl_sm1_33_us_h2d[2] = tl_s1n_63_ds_h2d[0];
+ assign tl_s1n_63_ds_d2h[0] = tl_sm1_33_us_d2h[2];
+
+ assign tl_sm1_32_us_h2d[2] = tl_s1n_63_ds_h2d[1];
+ assign tl_s1n_63_ds_d2h[1] = tl_sm1_32_us_d2h[2];
+
+ assign tl_sm1_37_us_h2d[1] = tl_s1n_63_ds_h2d[2];
+ assign tl_s1n_63_ds_d2h[2] = tl_sm1_37_us_d2h[1];
+
+ assign tl_sm1_39_us_h2d[1] = tl_s1n_63_ds_h2d[3];
+ assign tl_s1n_63_ds_d2h[3] = tl_sm1_39_us_d2h[1];
+
+ assign tl_sm1_41_us_h2d[1] = tl_s1n_63_ds_h2d[4];
+ assign tl_s1n_63_ds_d2h[4] = tl_sm1_41_us_d2h[1];
+
+ assign tl_sm1_43_us_h2d[1] = tl_s1n_63_ds_h2d[5];
+ assign tl_s1n_63_ds_d2h[5] = tl_sm1_43_us_d2h[1];
+
+ assign tl_sm1_45_us_h2d[1] = tl_s1n_63_ds_h2d[6];
+ assign tl_s1n_63_ds_d2h[6] = tl_sm1_45_us_d2h[1];
+
+ assign tl_sm1_46_us_h2d[1] = tl_s1n_63_ds_h2d[7];
+ assign tl_s1n_63_ds_d2h[7] = tl_sm1_46_us_d2h[1];
+
+ assign tl_sm1_47_us_h2d[1] = tl_s1n_63_ds_h2d[8];
+ assign tl_s1n_63_ds_d2h[8] = tl_sm1_47_us_d2h[1];
+
+ assign tl_sm1_35_us_h2d[2] = tl_s1n_63_ds_h2d[9];
+ assign tl_s1n_63_ds_d2h[9] = tl_sm1_35_us_d2h[2];
+
+ assign tl_sm1_53_us_h2d[1] = tl_s1n_63_ds_h2d[10];
+ assign tl_s1n_63_ds_d2h[10] = tl_sm1_53_us_d2h[1];
+
+ assign tl_sm1_57_us_h2d[1] = tl_s1n_63_ds_h2d[11];
+ assign tl_s1n_63_ds_d2h[11] = tl_sm1_57_us_d2h[1];
+
+ assign tl_sm1_48_us_h2d[1] = tl_s1n_63_ds_h2d[12];
+ assign tl_s1n_63_ds_d2h[12] = tl_sm1_48_us_d2h[1];
+
+ assign tl_sm1_49_us_h2d[1] = tl_s1n_63_ds_h2d[13];
+ assign tl_s1n_63_ds_d2h[13] = tl_sm1_49_us_d2h[1];
+
+ assign tl_sm1_50_us_h2d[1] = tl_s1n_63_ds_h2d[14];
+ assign tl_s1n_63_ds_d2h[14] = tl_sm1_50_us_d2h[1];
+
+ assign tl_sm1_51_us_h2d[1] = tl_s1n_63_ds_h2d[15];
+ assign tl_s1n_63_ds_d2h[15] = tl_sm1_51_us_d2h[1];
+
+ assign tl_sm1_52_us_h2d[1] = tl_s1n_63_ds_h2d[16];
+ assign tl_s1n_63_ds_d2h[16] = tl_sm1_52_us_d2h[1];
+
+ assign tl_sm1_54_us_h2d[1] = tl_s1n_63_ds_h2d[17];
+ assign tl_s1n_63_ds_d2h[17] = tl_sm1_54_us_d2h[1];
+
+ assign tl_sm1_55_us_h2d[1] = tl_s1n_63_ds_h2d[18];
+ assign tl_s1n_63_ds_d2h[18] = tl_sm1_55_us_d2h[1];
+
+ assign tl_sm1_56_us_h2d[1] = tl_s1n_63_ds_h2d[19];
+ assign tl_s1n_63_ds_d2h[19] = tl_sm1_56_us_d2h[1];
+
+ assign tl_sm1_59_us_h2d[1] = tl_s1n_63_ds_h2d[20];
+ assign tl_s1n_63_ds_d2h[20] = tl_sm1_59_us_d2h[1];
+
+ assign tl_sm1_58_us_h2d[1] = tl_s1n_63_ds_h2d[21];
+ assign tl_s1n_63_ds_d2h[21] = tl_sm1_58_us_d2h[1];
+
+ assign tl_sm1_34_us_h2d[2] = tl_s1n_63_ds_h2d[22];
+ assign tl_s1n_63_ds_d2h[22] = tl_sm1_34_us_d2h[2];
+
+ assign tl_sm1_61_us_h2d[1] = tl_s1n_63_ds_h2d[23];
+ assign tl_s1n_63_ds_d2h[23] = tl_sm1_61_us_d2h[1];
+
+ assign tl_sm1_62_us_h2d[1] = tl_s1n_63_ds_h2d[24];
+ assign tl_s1n_63_ds_d2h[24] = tl_sm1_62_us_d2h[1];
+
+ assign tl_sm1_32_us_h2d[3] = tl_s1n_64_ds_h2d[0];
+ assign tl_s1n_64_ds_d2h[0] = tl_sm1_32_us_d2h[3];
+
+ assign tl_sm1_34_us_h2d[3] = tl_s1n_64_ds_h2d[1];
+ assign tl_s1n_64_ds_d2h[1] = tl_sm1_34_us_d2h[3];
+
+ assign tl_sm1_35_us_h2d[3] = tl_s1n_64_ds_h2d[2];
+ assign tl_s1n_64_ds_d2h[2] = tl_sm1_35_us_d2h[3];
+
+ assign tl_sm1_61_us_h2d[2] = tl_s1n_64_ds_h2d[3];
+ assign tl_s1n_64_ds_d2h[3] = tl_sm1_61_us_d2h[2];
+
+ assign tl_sm1_32_us_h2d[4] = tl_s1n_65_ds_h2d[0];
+ assign tl_s1n_65_ds_d2h[0] = tl_sm1_32_us_d2h[4];
+
+ assign tl_sm1_34_us_h2d[4] = tl_s1n_65_ds_h2d[1];
+ assign tl_s1n_65_ds_d2h[1] = tl_sm1_34_us_d2h[4];
+
+ assign tl_sm1_35_us_h2d[4] = tl_s1n_65_ds_h2d[2];
+ assign tl_s1n_65_ds_d2h[2] = tl_sm1_35_us_d2h[4];
+
+ assign tl_sm1_61_us_h2d[3] = tl_s1n_65_ds_h2d[3];
+ assign tl_s1n_65_ds_d2h[3] = tl_sm1_61_us_d2h[3];
+
+ assign tl_s1n_31_us_h2d = tl_rv_core_ibex_sec__corei_i;
+ assign tl_rv_core_ibex_sec__corei_o = tl_s1n_31_us_d2h;
+
+ assign tl_rom_ctrl__rom_o = tl_sm1_32_ds_h2d;
+ assign tl_sm1_32_ds_d2h = tl_rom_ctrl__rom_i;
+
+ assign tl_dbg_o = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_dbg_i;
+
+ assign tl_sram_ctrl_main__ram_o = tl_sm1_34_ds_h2d;
+ assign tl_sm1_34_ds_d2h = tl_sram_ctrl_main__ram_i;
+
+ assign tl_flash_ctrl__mem_o = tl_sm1_35_ds_h2d;
+ assign tl_sm1_35_ds_d2h = tl_flash_ctrl__mem_i;
+
+ assign tl_s1n_36_us_h2d = tl_rv_core_ibex_sec__cored_i;
+ assign tl_rv_core_ibex_sec__cored_o = tl_s1n_36_us_d2h;
+
+ assign tl_rom_ctrl__regs_o = tl_sm1_37_ds_h2d;
+ assign tl_sm1_37_ds_d2h = tl_rom_ctrl__regs_i;
+
+ assign tl_peri_o = tl_asf_38_ds_h2d;
+ assign tl_asf_38_ds_d2h = tl_peri_i;
+
+ assign tl_asf_38_us_h2d = tl_sm1_39_ds_h2d;
+ assign tl_sm1_39_ds_d2h = tl_asf_38_us_d2h;
+
+ assign tl_spi_host0_o = tl_asf_40_ds_h2d;
+ assign tl_asf_40_ds_d2h = tl_spi_host0_i;
+
+ assign tl_asf_40_us_h2d = tl_sm1_41_ds_h2d;
+ assign tl_sm1_41_ds_d2h = tl_asf_40_us_d2h;
+
+ assign tl_spi_host1_o = tl_asf_42_ds_h2d;
+ assign tl_asf_42_ds_d2h = tl_spi_host1_i;
+
+ assign tl_asf_42_us_h2d = tl_sm1_43_ds_h2d;
+ assign tl_sm1_43_ds_d2h = tl_asf_42_us_d2h;
+
+ assign tl_usbdev_o = tl_asf_44_ds_h2d;
+ assign tl_asf_44_ds_d2h = tl_usbdev_i;
+
+ assign tl_asf_44_us_h2d = tl_sm1_45_ds_h2d;
+ assign tl_sm1_45_ds_d2h = tl_asf_44_us_d2h;
+
+ assign tl_flash_ctrl__core_o = tl_sm1_46_ds_h2d;
+ assign tl_sm1_46_ds_d2h = tl_flash_ctrl__core_i;
+
+ assign tl_flash_ctrl__prim_o = tl_sm1_47_ds_h2d;
+ assign tl_sm1_47_ds_d2h = tl_flash_ctrl__prim_i;
+
+ assign tl_aes_o = tl_sm1_48_ds_h2d;
+ assign tl_sm1_48_ds_d2h = tl_aes_i;
+
+ assign tl_entropy_src_o = tl_sm1_49_ds_h2d;
+ assign tl_sm1_49_ds_d2h = tl_entropy_src_i;
+
+ assign tl_csrng_o = tl_sm1_50_ds_h2d;
+ assign tl_sm1_50_ds_d2h = tl_csrng_i;
+
+ assign tl_edn0_o = tl_sm1_51_ds_h2d;
+ assign tl_sm1_51_ds_d2h = tl_edn0_i;
+
+ assign tl_edn1_o = tl_sm1_52_ds_h2d;
+ assign tl_sm1_52_ds_d2h = tl_edn1_i;
+
+ assign tl_hmac_o = tl_sm1_53_ds_h2d;
+ assign tl_sm1_53_ds_d2h = tl_hmac_i;
+
+ assign tl_rv_plic_o = tl_sm1_54_ds_h2d;
+ assign tl_sm1_54_ds_d2h = tl_rv_plic_i;
+
+ assign tl_otbn_o = tl_sm1_55_ds_h2d;
+ assign tl_sm1_55_ds_d2h = tl_otbn_i;
+
+ assign tl_keymgr_o = tl_sm1_56_ds_h2d;
+ assign tl_sm1_56_ds_d2h = tl_keymgr_i;
+
+ assign tl_kmac_o = tl_sm1_57_ds_h2d;
+ assign tl_sm1_57_ds_d2h = tl_kmac_i;
+
+ assign tl_sram_ctrl_main__regs_o = tl_sm1_58_ds_h2d;
+ assign tl_sm1_58_ds_d2h = tl_sram_ctrl_main__regs_i;
+
+ assign tl_rv_core_ibex_sec__cfg_o = tl_sm1_59_ds_h2d;
+ assign tl_sm1_59_ds_d2h = tl_rv_core_ibex_sec__cfg_i;
+
+ assign tl_smc_o = tl_asf_60_ds_h2d;
+ assign tl_asf_60_ds_d2h = tl_smc_i;
+
+ assign tl_asf_60_us_h2d = tl_sm1_61_ds_h2d;
+ assign tl_sm1_61_ds_d2h = tl_asf_60_us_d2h;
+
+ assign tl_tlul_mailbox_sec_o = tl_sm1_62_ds_h2d;
+ assign tl_sm1_62_ds_d2h = tl_tlul_mailbox_sec_i;
+
+ assign tl_s1n_63_us_h2d = tl_rv_dm__sba_i;
+ assign tl_rv_dm__sba_o = tl_s1n_63_us_d2h;
+
+ assign tl_s1n_64_us_h2d = tl_dma0__reader_i;
+ assign tl_dma0__reader_o = tl_s1n_64_us_d2h;
+
+ assign tl_s1n_65_us_h2d = tl_dma0__writer_i;
+ assign tl_dma0__writer_o = tl_s1n_65_us_d2h;
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_31 = 3'd4;
+ if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
+ dev_sel_s1n_31 = 3'd0;
+
+ end else if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_DBG)) == ADDR_SPACE_DBG) begin
+ dev_sel_s1n_31 = 3'd1;
+
+ end else if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
+ dev_sel_s1n_31 = 3'd2;
+
+ end else if ((tl_s1n_31_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
+ dev_sel_s1n_31 = 3'd3;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_36 = 5'd26;
+ if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
+ dev_sel_s1n_36 = 5'd0;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin
+ dev_sel_s1n_36 = 5'd1;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_DBG)) == ADDR_SPACE_DBG) begin
+ dev_sel_s1n_36 = 5'd2;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
+ dev_sel_s1n_36 = 5'd3;
+
+ end else if (
+ ((tl_s1n_36_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_36_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1])
+ ) begin
+ dev_sel_s1n_36 = 5'd4;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin
+ dev_sel_s1n_36 = 5'd5;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin
+ dev_sel_s1n_36 = 5'd6;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_36 = 5'd7;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin
+ dev_sel_s1n_36 = 5'd8;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin
+ dev_sel_s1n_36 = 5'd9;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
+ dev_sel_s1n_36 = 5'd10;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_36 = 5'd11;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
+ dev_sel_s1n_36 = 5'd12;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
+ dev_sel_s1n_36 = 5'd13;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
+ dev_sel_s1n_36 = 5'd14;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
+ dev_sel_s1n_36 = 5'd15;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_36 = 5'd16;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_36 = 5'd17;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_36 = 5'd18;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
+ dev_sel_s1n_36 = 5'd19;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
+ dev_sel_s1n_36 = 5'd20;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin
+ dev_sel_s1n_36 = 5'd21;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_RV_CORE_IBEX_SEC__CFG)) == ADDR_SPACE_RV_CORE_IBEX_SEC__CFG) begin
+ dev_sel_s1n_36 = 5'd22;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_SMC)) == ADDR_SPACE_SMC) begin
+ dev_sel_s1n_36 = 5'd23;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_TLUL_MAILBOX_SEC)) == ADDR_SPACE_TLUL_MAILBOX_SEC) begin
+ dev_sel_s1n_36 = 5'd24;
+
+ end else if ((tl_s1n_36_us_h2d.a_address &
+ ~(ADDR_MASK_DMA0)) == ADDR_SPACE_DMA0) begin
+ dev_sel_s1n_36 = 5'd25;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_63 = 5'd25;
+ if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_DBG)) == ADDR_SPACE_DBG) begin
+ dev_sel_s1n_63 = 5'd0;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
+ dev_sel_s1n_63 = 5'd1;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin
+ dev_sel_s1n_63 = 5'd2;
+
+ end else if (
+ ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_63_us_h2d.a_address & ~(ADDR_MASK_PERI[1])) == ADDR_SPACE_PERI[1])
+ ) begin
+ dev_sel_s1n_63 = 5'd3;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin
+ dev_sel_s1n_63 = 5'd4;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin
+ dev_sel_s1n_63 = 5'd5;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_63 = 5'd6;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin
+ dev_sel_s1n_63 = 5'd7;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin
+ dev_sel_s1n_63 = 5'd8;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
+ dev_sel_s1n_63 = 5'd9;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_63 = 5'd10;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
+ dev_sel_s1n_63 = 5'd11;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_63 = 5'd12;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
+ dev_sel_s1n_63 = 5'd13;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
+ dev_sel_s1n_63 = 5'd14;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
+ dev_sel_s1n_63 = 5'd15;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
+ dev_sel_s1n_63 = 5'd16;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_63 = 5'd17;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_63 = 5'd18;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
+ dev_sel_s1n_63 = 5'd19;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_RV_CORE_IBEX_SEC__CFG)) == ADDR_SPACE_RV_CORE_IBEX_SEC__CFG) begin
+ dev_sel_s1n_63 = 5'd20;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin
+ dev_sel_s1n_63 = 5'd21;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
+ dev_sel_s1n_63 = 5'd22;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_SMC)) == ADDR_SPACE_SMC) begin
+ dev_sel_s1n_63 = 5'd23;
+
+ end else if ((tl_s1n_63_us_h2d.a_address &
+ ~(ADDR_MASK_TLUL_MAILBOX_SEC)) == ADDR_SPACE_TLUL_MAILBOX_SEC) begin
+ dev_sel_s1n_63 = 5'd24;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_64 = 3'd4;
+ if ((tl_s1n_64_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
+ dev_sel_s1n_64 = 3'd0;
+
+ end else if ((tl_s1n_64_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
+ dev_sel_s1n_64 = 3'd1;
+
+ end else if ((tl_s1n_64_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
+ dev_sel_s1n_64 = 3'd2;
+
+ end else if ((tl_s1n_64_us_h2d.a_address &
+ ~(ADDR_MASK_SMC)) == ADDR_SPACE_SMC) begin
+ dev_sel_s1n_64 = 3'd3;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_65 = 3'd4;
+ if ((tl_s1n_65_us_h2d.a_address &
+ ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin
+ dev_sel_s1n_65 = 3'd0;
+
+ end else if ((tl_s1n_65_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
+ dev_sel_s1n_65 = 3'd1;
+
+ end else if ((tl_s1n_65_us_h2d.a_address &
+ ~(ADDR_MASK_FLASH_CTRL__MEM)) == ADDR_SPACE_FLASH_CTRL__MEM) begin
+ dev_sel_s1n_65 = 3'd2;
+
+ end else if ((tl_s1n_65_us_h2d.a_address &
+ ~(ADDR_MASK_SMC)) == ADDR_SPACE_SMC) begin
+ dev_sel_s1n_65 = 3'd3;
+end
+ end
+
+
+ // Instantiation phase
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth (16'h0),
+ .DRspDepth (16'h0),
+ .N (4)
+ ) u_s1n_31 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_31_us_h2d),
+ .tl_h_o (tl_s1n_31_us_d2h),
+ .tl_d_o (tl_s1n_31_ds_h2d),
+ .tl_d_i (tl_s1n_31_ds_d2h),
+ .dev_select_i (dev_sel_s1n_31)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (20'h0),
+ .HRspDepth (20'h0),
+ .DRspPass (1'b0),
+ .M (5)
+ ) u_sm1_32 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_32_us_h2d),
+ .tl_h_o (tl_sm1_32_us_d2h),
+ .tl_d_o (tl_sm1_32_ds_h2d),
+ .tl_d_i (tl_sm1_32_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
+ .DRspPass (1'b0),
+ .M (3)
+ ) u_sm1_33 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_33_us_h2d),
+ .tl_h_o (tl_sm1_33_us_d2h),
+ .tl_d_o (tl_sm1_33_ds_h2d),
+ .tl_d_i (tl_sm1_33_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (20'h0),
+ .HRspDepth (20'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (5)
+ ) u_sm1_34 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_34_us_h2d),
+ .tl_h_o (tl_sm1_34_us_d2h),
+ .tl_d_o (tl_sm1_34_ds_h2d),
+ .tl_d_i (tl_sm1_34_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (20'h0),
+ .HRspDepth (20'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (5)
+ ) u_sm1_35 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_35_us_h2d),
+ .tl_h_o (tl_sm1_35_us_d2h),
+ .tl_d_o (tl_sm1_35_ds_h2d),
+ .tl_d_i (tl_sm1_35_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqPass (26'h1ffffff),
+ .DRspPass (26'h1ffffff),
+ .DReqDepth (104'h10000000000000000000000000),
+ .DRspDepth (104'h10000000000000000000000000),
+ .N (26)
+ ) u_s1n_36 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_36_us_h2d),
+ .tl_h_o (tl_s1n_36_us_d2h),
+ .tl_d_o (tl_s1n_36_ds_h2d),
+ .tl_d_i (tl_s1n_36_ds_d2h),
+ .dev_select_i (dev_sel_s1n_36)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_37 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_37_us_h2d),
+ .tl_h_o (tl_sm1_37_us_d2h),
+ .tl_d_o (tl_sm1_37_ds_h2d),
+ .tl_d_i (tl_sm1_37_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_38 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_fixed_i),
+ .rst_d_ni (rst_fixed_ni),
+ .tl_h_i (tl_asf_38_us_h2d),
+ .tl_h_o (tl_asf_38_us_d2h),
+ .tl_d_o (tl_asf_38_ds_h2d),
+ .tl_d_i (tl_asf_38_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_39 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_39_us_h2d),
+ .tl_h_o (tl_sm1_39_us_d2h),
+ .tl_d_o (tl_sm1_39_ds_h2d),
+ .tl_d_i (tl_sm1_39_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_40 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_spi_host0_i),
+ .rst_d_ni (rst_spi_host0_ni),
+ .tl_h_i (tl_asf_40_us_h2d),
+ .tl_h_o (tl_asf_40_us_d2h),
+ .tl_d_o (tl_asf_40_ds_h2d),
+ .tl_d_i (tl_asf_40_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_41 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_41_us_h2d),
+ .tl_h_o (tl_sm1_41_us_d2h),
+ .tl_d_o (tl_sm1_41_ds_h2d),
+ .tl_d_i (tl_sm1_41_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_42 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_spi_host1_i),
+ .rst_d_ni (rst_spi_host1_ni),
+ .tl_h_i (tl_asf_42_us_h2d),
+ .tl_h_o (tl_asf_42_us_d2h),
+ .tl_d_o (tl_asf_42_ds_h2d),
+ .tl_d_i (tl_asf_42_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_43 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_43_us_h2d),
+ .tl_h_o (tl_sm1_43_us_d2h),
+ .tl_d_o (tl_sm1_43_ds_h2d),
+ .tl_d_i (tl_sm1_43_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_44 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_usb_i),
+ .rst_d_ni (rst_usb_ni),
+ .tl_h_i (tl_asf_44_us_h2d),
+ .tl_h_o (tl_asf_44_us_d2h),
+ .tl_d_o (tl_asf_44_ds_h2d),
+ .tl_d_i (tl_asf_44_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_45 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_45_us_h2d),
+ .tl_h_o (tl_sm1_45_us_d2h),
+ .tl_d_o (tl_sm1_45_ds_h2d),
+ .tl_d_i (tl_sm1_45_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_46 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_46_us_h2d),
+ .tl_h_o (tl_sm1_46_us_d2h),
+ .tl_d_o (tl_sm1_46_ds_h2d),
+ .tl_d_i (tl_sm1_46_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_47 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_47_us_h2d),
+ .tl_h_o (tl_sm1_47_us_d2h),
+ .tl_d_o (tl_sm1_47_ds_h2d),
+ .tl_d_i (tl_sm1_47_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_48 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_48_us_h2d),
+ .tl_h_o (tl_sm1_48_us_d2h),
+ .tl_d_o (tl_sm1_48_ds_h2d),
+ .tl_d_i (tl_sm1_48_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_49 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_49_us_h2d),
+ .tl_h_o (tl_sm1_49_us_d2h),
+ .tl_d_o (tl_sm1_49_ds_h2d),
+ .tl_d_i (tl_sm1_49_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_50 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_50_us_h2d),
+ .tl_h_o (tl_sm1_50_us_d2h),
+ .tl_d_o (tl_sm1_50_ds_h2d),
+ .tl_d_i (tl_sm1_50_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_51 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_51_us_h2d),
+ .tl_h_o (tl_sm1_51_us_d2h),
+ .tl_d_o (tl_sm1_51_ds_h2d),
+ .tl_d_i (tl_sm1_51_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_52 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_52_us_h2d),
+ .tl_h_o (tl_sm1_52_us_d2h),
+ .tl_d_o (tl_sm1_52_ds_h2d),
+ .tl_d_i (tl_sm1_52_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_53 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_53_us_h2d),
+ .tl_h_o (tl_sm1_53_us_d2h),
+ .tl_d_o (tl_sm1_53_ds_h2d),
+ .tl_d_i (tl_sm1_53_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_54 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_54_us_h2d),
+ .tl_h_o (tl_sm1_54_us_d2h),
+ .tl_d_o (tl_sm1_54_ds_h2d),
+ .tl_d_i (tl_sm1_54_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_55 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_55_us_h2d),
+ .tl_h_o (tl_sm1_55_us_d2h),
+ .tl_d_o (tl_sm1_55_ds_h2d),
+ .tl_d_i (tl_sm1_55_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_56 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_56_us_h2d),
+ .tl_h_o (tl_sm1_56_us_d2h),
+ .tl_d_o (tl_sm1_56_ds_h2d),
+ .tl_d_i (tl_sm1_56_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_57 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_57_us_h2d),
+ .tl_h_o (tl_sm1_57_us_d2h),
+ .tl_d_o (tl_sm1_57_ds_h2d),
+ .tl_d_i (tl_sm1_57_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_58 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_58_us_h2d),
+ .tl_h_o (tl_sm1_58_us_d2h),
+ .tl_d_o (tl_sm1_58_ds_h2d),
+ .tl_d_i (tl_sm1_58_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_59 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_59_us_h2d),
+ .tl_h_o (tl_sm1_59_us_d2h),
+ .tl_d_o (tl_sm1_59_ds_h2d),
+ .tl_d_i (tl_sm1_59_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_60 (
+ .clk_h_i (clk_main_i),
+ .rst_h_ni (rst_main_ni),
+ .clk_d_i (clk_smc_i),
+ .rst_d_ni (rst_smc_ni),
+ .tl_h_i (tl_asf_60_us_h2d),
+ .tl_h_o (tl_asf_60_us_d2h),
+ .tl_d_o (tl_asf_60_ds_h2d),
+ .tl_d_i (tl_asf_60_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (16'h0),
+ .HRspDepth (16'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (4)
+ ) u_sm1_61 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_61_us_h2d),
+ .tl_h_o (tl_sm1_61_us_d2h),
+ .tl_d_o (tl_sm1_61_ds_h2d),
+ .tl_d_i (tl_sm1_61_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_62 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_62_us_h2d),
+ .tl_h_o (tl_sm1_62_us_d2h),
+ .tl_d_o (tl_sm1_62_ds_h2d),
+ .tl_d_i (tl_sm1_62_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .HReqPass (1'b0),
+ .HRspPass (1'b0),
+ .DReqDepth (100'h0),
+ .DRspDepth (100'h0),
+ .N (25)
+ ) u_s1n_63 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_63_us_h2d),
+ .tl_h_o (tl_s1n_63_us_d2h),
+ .tl_d_o (tl_s1n_63_ds_h2d),
+ .tl_d_i (tl_s1n_63_ds_d2h),
+ .dev_select_i (dev_sel_s1n_63)
+ );
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth (16'h0),
+ .DRspDepth (16'h0),
+ .N (4)
+ ) u_s1n_64 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_64_us_h2d),
+ .tl_h_o (tl_s1n_64_us_d2h),
+ .tl_d_o (tl_s1n_64_ds_h2d),
+ .tl_d_i (tl_s1n_64_ds_d2h),
+ .dev_select_i (dev_sel_s1n_64)
+ );
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth (16'h0),
+ .DRspDepth (16'h0),
+ .N (4)
+ ) u_s1n_65 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_s1n_65_us_h2d),
+ .tl_h_o (tl_s1n_65_us_d2h),
+ .tl_d_o (tl_s1n_65_ds_h2d),
+ .tl_d_i (tl_s1n_65_ds_d2h),
+ .dev_select_i (dev_sel_s1n_65)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
new file mode 100644
index 0000000..5a26486
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -0,0 +1,579 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+{
+ name: peri
+ clock_srcs:
+ {
+ clk_peri_i: io_div4
+ }
+ clock_group: infra
+ reset: rst_peri_ni
+ reset_connections:
+ {
+ rst_peri_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
+ }
+ domain:
+ [
+ "0"
+ ]
+ connections:
+ {
+ main:
+ [
+ uart0
+ uart1
+ uart2
+ uart3
+ i2c0
+ i2c1
+ i2c2
+ pattgen
+ gpio
+ spi_device
+ rv_timer
+ pwrmgr_aon
+ rstmgr_aon
+ clkmgr_aon
+ pinmux_aon
+ otp_ctrl.core
+ otp_ctrl.prim
+ lc_ctrl
+ sensor_ctrl
+ alert_handler
+ ast
+ sram_ctrl_ret_aon.ram
+ sram_ctrl_ret_aon.regs
+ aon_timer_aon
+ adc_ctrl_aon
+ sysrst_ctrl_aon
+ pwm_aon
+ ]
+ }
+ nodes:
+ [
+ {
+ name: main
+ type: host
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ xbar: true
+ pipeline: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: uart0
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40000000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: uart1
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40010000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: uart2
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40020000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: uart3
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x40030000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: i2c0
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: i2c
+ addr_range:
+ [
+ {
+ base_addr: 0x40080000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: i2c1
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: i2c
+ addr_range:
+ [
+ {
+ base_addr: 0x40090000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: i2c2
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: i2c
+ addr_range:
+ [
+ {
+ base_addr: 0x400a0000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: pattgen
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: pattgen
+ addr_range:
+ [
+ {
+ base_addr: 0x400e0000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: pwm_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: pwm
+ addr_range:
+ [
+ {
+ base_addr: 0x40450000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: gpio
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: gpio
+ addr_range:
+ [
+ {
+ base_addr: 0x40040000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: spi_device
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: spi_device
+ addr_range:
+ [
+ {
+ base_addr: 0x40050000
+ size_byte: 0x2000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: rv_timer
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: rv_timer
+ addr_range:
+ [
+ {
+ base_addr: 0x40100000
+ size_byte: 0x200
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: pwrmgr_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: pwrmgr
+ addr_range:
+ [
+ {
+ base_addr: 0x40400000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: rstmgr_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: rstmgr
+ addr_range:
+ [
+ {
+ base_addr: 0x40410000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: clkmgr_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: clkmgr
+ addr_range:
+ [
+ {
+ base_addr: 0x40420000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: pinmux_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: pinmux
+ addr_range:
+ [
+ {
+ base_addr: 0x40460000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: otp_ctrl.core
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: otp_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40130000
+ size_byte: 0x2000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: otp_ctrl.prim
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: otp_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40132000
+ size_byte: 0x20
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: lc_ctrl
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: lc_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40140000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: sensor_ctrl
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: sensor_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40490000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: alert_handler
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: alert_handler
+ addr_range:
+ [
+ {
+ base_addr: 0x40150000
+ size_byte: 0x800
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: sram_ctrl_ret_aon.regs
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: sram_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40500000
+ size_byte: 0x20
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: sram_ctrl_ret_aon.ram
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: sram_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40600000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: aon_timer_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: aon_timer
+ addr_range:
+ [
+ {
+ base_addr: 0x40470000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: sysrst_ctrl_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: sysrst_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40430000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: adc_ctrl_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: adc_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40440000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: ast
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: false
+ inst_type: ast
+ addr_range:
+ [
+ {
+ base_addr: 0x40480000
+ size_byte: 0x400
+ }
+ ]
+ xbar: false
+ stub: true
+ req_fifo_pass: true
+ }
+ ]
+ clock: clk_peri_i
+ type: xbar
+}
diff --git a/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.hjson
new file mode 100644
index 0000000..a7403da
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -0,0 +1,185 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_peri comportable IP spec generated by `tlgen.py` tool
+{ name: "xbar_peri"
+ clock_primary: ""
+ other_clock_list: []
+ reset_primary: ""
+ other_reset_list: []
+ //available_input_list: []
+
+ inter_signal_list: [
+ // host
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_main"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ // device
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart2"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_uart3"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_i2c0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_i2c1"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_i2c2"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_pattgen"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_pwm_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_gpio"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_spi_device"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_timer"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_pwrmgr_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rstmgr_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_clkmgr_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_pinmux_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_otp_ctrl__core"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_otp_ctrl__prim"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_lc_ctrl"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sensor_ctrl"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_alert_handler"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sram_ctrl_ret_aon__regs"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sram_ctrl_ret_aon__ram"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_aon_timer_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_sysrst_ctrl_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_adc_ctrl_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_ast"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_sencha/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
new file mode 100644
index 0000000..0c3ec7d
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__xbar_connect generated by `tlgen.py` tool
+
+xbar_peri dut();
+
+`DRIVE_CLK(clk_peri_i)
+
+initial force dut.clk_peri_i = clk_peri_i;
+
+// TODO, all resets tie together
+initial force dut.rst_peri_ni = rst_n;
+
+// Host TileLink interface connections
+`CONNECT_TL_HOST_IF(main, dut, clk_peri_i, rst_n)
+
+// Device TileLink interface connections
+`CONNECT_TL_DEVICE_IF(uart0, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart1, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart2, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(uart3, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(i2c1, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(i2c2, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pattgen, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pwm_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(otp_ctrl__core, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(otp_ctrl__prim, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(lc_ctrl, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sensor_ctrl, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(aon_timer_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sysrst_ctrl_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(adc_ctrl_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ast, dut, clk_peri_i, rst_n)
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cov_excl.el b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cov_excl.el
new file mode 100644
index 0000000..f7a31e0
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cov_excl.el
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cov_excl.el generated by `tlgen.py` tool
+
+ANNOTATION: "[NON_RTL]"
+MODULE: uvm_pkg
+Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion"
+Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion"
+
+ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim"
+MODULE: xbar_peri
+Block 1 "0" "assign unused_scanmode = scanmode_i;"
+
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cover.cfg
new file mode 100644
index 0000000..ba4c746
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -0,0 +1,128 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cover.cfg generated by `tlgen.py` tool
+
++tree tb.dut
+-module pins_if // DV construct.
+-module clk_rst_if // DV construct.
+
+-assert legalAOpcodeErr_A
+-assert sizeGTEMaskErr_A
+-assert sizeMatchesMaskErr_A
+-assert addrSizeAlignedErr_A
+
+// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after.
+-node tb.dut tl_*.a_param
+-node tb.dut tl_*.d_param
+-node tb.dut tl_*.d_opcode[2:1]
+
+// [UNR] these device address bits are always 0
+-node tb.dut tl_uart0_o.a_address[29:6]
+-node tb.dut tl_uart0_o.a_address[31:31]
+-node tb.dut tl_uart1_o.a_address[15:6]
+-node tb.dut tl_uart1_o.a_address[29:17]
+-node tb.dut tl_uart1_o.a_address[31:31]
+-node tb.dut tl_uart2_o.a_address[16:6]
+-node tb.dut tl_uart2_o.a_address[29:18]
+-node tb.dut tl_uart2_o.a_address[31:31]
+-node tb.dut tl_uart3_o.a_address[15:6]
+-node tb.dut tl_uart3_o.a_address[29:18]
+-node tb.dut tl_uart3_o.a_address[31:31]
+-node tb.dut tl_i2c0_o.a_address[18:7]
+-node tb.dut tl_i2c0_o.a_address[29:20]
+-node tb.dut tl_i2c0_o.a_address[31:31]
+-node tb.dut tl_i2c1_o.a_address[15:7]
+-node tb.dut tl_i2c1_o.a_address[18:17]
+-node tb.dut tl_i2c1_o.a_address[29:20]
+-node tb.dut tl_i2c1_o.a_address[31:31]
+-node tb.dut tl_i2c2_o.a_address[16:7]
+-node tb.dut tl_i2c2_o.a_address[18:18]
+-node tb.dut tl_i2c2_o.a_address[29:20]
+-node tb.dut tl_i2c2_o.a_address[31:31]
+-node tb.dut tl_pattgen_o.a_address[16:6]
+-node tb.dut tl_pattgen_o.a_address[29:20]
+-node tb.dut tl_pattgen_o.a_address[31:31]
+-node tb.dut tl_pwm_aon_o.a_address[15:7]
+-node tb.dut tl_pwm_aon_o.a_address[17:17]
+-node tb.dut tl_pwm_aon_o.a_address[21:19]
+-node tb.dut tl_pwm_aon_o.a_address[29:23]
+-node tb.dut tl_pwm_aon_o.a_address[31:31]
+-node tb.dut tl_gpio_o.a_address[17:6]
+-node tb.dut tl_gpio_o.a_address[29:19]
+-node tb.dut tl_gpio_o.a_address[31:31]
+-node tb.dut tl_spi_device_o.a_address[15:13]
+-node tb.dut tl_spi_device_o.a_address[17:17]
+-node tb.dut tl_spi_device_o.a_address[29:19]
+-node tb.dut tl_spi_device_o.a_address[31:31]
+-node tb.dut tl_rv_timer_o.a_address[19:9]
+-node tb.dut tl_rv_timer_o.a_address[29:21]
+-node tb.dut tl_rv_timer_o.a_address[31:31]
+-node tb.dut tl_pwrmgr_aon_o.a_address[21:7]
+-node tb.dut tl_pwrmgr_aon_o.a_address[29:23]
+-node tb.dut tl_pwrmgr_aon_o.a_address[31:31]
+-node tb.dut tl_rstmgr_aon_o.a_address[15:8]
+-node tb.dut tl_rstmgr_aon_o.a_address[21:17]
+-node tb.dut tl_rstmgr_aon_o.a_address[29:23]
+-node tb.dut tl_rstmgr_aon_o.a_address[31:31]
+-node tb.dut tl_clkmgr_aon_o.a_address[16:7]
+-node tb.dut tl_clkmgr_aon_o.a_address[21:18]
+-node tb.dut tl_clkmgr_aon_o.a_address[29:23]
+-node tb.dut tl_clkmgr_aon_o.a_address[31:31]
+-node tb.dut tl_pinmux_aon_o.a_address[16:12]
+-node tb.dut tl_pinmux_aon_o.a_address[21:19]
+-node tb.dut tl_pinmux_aon_o.a_address[29:23]
+-node tb.dut tl_pinmux_aon_o.a_address[31:31]
+-node tb.dut tl_otp_ctrl__core_o.a_address[15:13]
+-node tb.dut tl_otp_ctrl__core_o.a_address[19:18]
+-node tb.dut tl_otp_ctrl__core_o.a_address[29:21]
+-node tb.dut tl_otp_ctrl__core_o.a_address[31:31]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[12:5]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[15:14]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[19:18]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[29:21]
+-node tb.dut tl_otp_ctrl__prim_o.a_address[31:31]
+-node tb.dut tl_lc_ctrl_o.a_address[17:8]
+-node tb.dut tl_lc_ctrl_o.a_address[19:19]
+-node tb.dut tl_lc_ctrl_o.a_address[29:21]
+-node tb.dut tl_lc_ctrl_o.a_address[31:31]
+-node tb.dut tl_sensor_ctrl_o.a_address[15:6]
+-node tb.dut tl_sensor_ctrl_o.a_address[18:17]
+-node tb.dut tl_sensor_ctrl_o.a_address[21:20]
+-node tb.dut tl_sensor_ctrl_o.a_address[29:23]
+-node tb.dut tl_sensor_ctrl_o.a_address[31:31]
+-node tb.dut tl_alert_handler_o.a_address[15:11]
+-node tb.dut tl_alert_handler_o.a_address[17:17]
+-node tb.dut tl_alert_handler_o.a_address[19:19]
+-node tb.dut tl_alert_handler_o.a_address[29:21]
+-node tb.dut tl_alert_handler_o.a_address[31:31]
+-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[19:5]
+-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[21:21]
+-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[29:23]
+-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[31:31]
+-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[20:12]
+-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[29:23]
+-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[31:31]
+-node tb.dut tl_aon_timer_aon_o.a_address[15:6]
+-node tb.dut tl_aon_timer_aon_o.a_address[21:19]
+-node tb.dut tl_aon_timer_aon_o.a_address[29:23]
+-node tb.dut tl_aon_timer_aon_o.a_address[31:31]
+-node tb.dut tl_sysrst_ctrl_aon_o.a_address[15:8]
+-node tb.dut tl_sysrst_ctrl_aon_o.a_address[21:18]
+-node tb.dut tl_sysrst_ctrl_aon_o.a_address[29:23]
+-node tb.dut tl_sysrst_ctrl_aon_o.a_address[31:31]
+-node tb.dut tl_adc_ctrl_aon_o.a_address[17:7]
+-node tb.dut tl_adc_ctrl_aon_o.a_address[21:19]
+-node tb.dut tl_adc_ctrl_aon_o.a_address[29:23]
+-node tb.dut tl_adc_ctrl_aon_o.a_address[31:31]
+-node tb.dut tl_ast_o.a_address[18:10]
+-node tb.dut tl_ast_o.a_address[21:20]
+-node tb.dut tl_ast_o.a_address[29:23]
+-node tb.dut tl_ast_o.a_address[31:31]
+
+begin tgl
+ -tree tb
+ +tree tb.dut 1
+ -node tb.dut.scanmode_i
+end
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
new file mode 100644
index 0000000..451edf4
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -0,0 +1,122 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `tlgen.py` tool
+
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+ '{"uart0", '{
+ '{32'h40000000, 32'h4000003f}
+ }},
+ '{"uart1", '{
+ '{32'h40010000, 32'h4001003f}
+ }},
+ '{"uart2", '{
+ '{32'h40020000, 32'h4002003f}
+ }},
+ '{"uart3", '{
+ '{32'h40030000, 32'h4003003f}
+ }},
+ '{"i2c0", '{
+ '{32'h40080000, 32'h4008007f}
+ }},
+ '{"i2c1", '{
+ '{32'h40090000, 32'h4009007f}
+ }},
+ '{"i2c2", '{
+ '{32'h400a0000, 32'h400a007f}
+ }},
+ '{"pattgen", '{
+ '{32'h400e0000, 32'h400e003f}
+ }},
+ '{"pwm_aon", '{
+ '{32'h40450000, 32'h4045007f}
+ }},
+ '{"gpio", '{
+ '{32'h40040000, 32'h4004003f}
+ }},
+ '{"spi_device", '{
+ '{32'h40050000, 32'h40051fff}
+ }},
+ '{"rv_timer", '{
+ '{32'h40100000, 32'h401001ff}
+ }},
+ '{"pwrmgr_aon", '{
+ '{32'h40400000, 32'h4040007f}
+ }},
+ '{"rstmgr_aon", '{
+ '{32'h40410000, 32'h404100ff}
+ }},
+ '{"clkmgr_aon", '{
+ '{32'h40420000, 32'h4042007f}
+ }},
+ '{"pinmux_aon", '{
+ '{32'h40460000, 32'h40460fff}
+ }},
+ '{"otp_ctrl__core", '{
+ '{32'h40130000, 32'h40131fff}
+ }},
+ '{"otp_ctrl__prim", '{
+ '{32'h40132000, 32'h4013201f}
+ }},
+ '{"lc_ctrl", '{
+ '{32'h40140000, 32'h401400ff}
+ }},
+ '{"sensor_ctrl", '{
+ '{32'h40490000, 32'h4049003f}
+ }},
+ '{"alert_handler", '{
+ '{32'h40150000, 32'h401507ff}
+ }},
+ '{"sram_ctrl_ret_aon__regs", '{
+ '{32'h40500000, 32'h4050001f}
+ }},
+ '{"sram_ctrl_ret_aon__ram", '{
+ '{32'h40600000, 32'h40600fff}
+ }},
+ '{"aon_timer_aon", '{
+ '{32'h40470000, 32'h4047003f}
+ }},
+ '{"sysrst_ctrl_aon", '{
+ '{32'h40430000, 32'h404300ff}
+ }},
+ '{"adc_ctrl_aon", '{
+ '{32'h40440000, 32'h4044007f}
+ }},
+ '{"ast", '{
+ '{32'h40480000, 32'h404803ff}
+}}};
+
+ // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+ '{"main", 0, '{
+ "uart0",
+ "uart1",
+ "uart2",
+ "uart3",
+ "i2c0",
+ "i2c1",
+ "i2c2",
+ "pattgen",
+ "gpio",
+ "spi_device",
+ "rv_timer",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "otp_ctrl__core",
+ "otp_ctrl__prim",
+ "lc_ctrl",
+ "sensor_ctrl",
+ "alert_handler",
+ "ast",
+ "sram_ctrl_ret_aon__ram",
+ "sram_ctrl_ret_aon__regs",
+ "aon_timer_aon",
+ "adc_ctrl_aon",
+ "sysrst_ctrl_aon",
+ "pwm_aon"}}
+};
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.core b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.core
new file mode 100644
index 0000000..c1b087e
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_peri_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_peri_bind:0.1"
+description: "XBAR peri assertion bind"
+filesets:
+ files_dv:
+ files:
+ - xbar_peri_bind.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
new file mode 100644
index 0000000..75398d4
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -0,0 +1,180 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_peri_bind module generated by `tlgen.py` tool for assertions
+module xbar_peri_bind;
+
+ // Host interfaces
+ bind xbar_peri tlul_assert #(.EndpointType("Device")) tlul_assert_host_main (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_main_i),
+ .d2h (tl_main_o)
+ );
+
+ // Device interfaces
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart0 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart0_o),
+ .d2h (tl_uart0_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart1 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart1_o),
+ .d2h (tl_uart1_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart2 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart2_o),
+ .d2h (tl_uart2_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart3 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_uart3_o),
+ .d2h (tl_uart3_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c0 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_i2c0_o),
+ .d2h (tl_i2c0_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c1 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_i2c1_o),
+ .d2h (tl_i2c1_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c2 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_i2c2_o),
+ .d2h (tl_i2c2_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pattgen (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_pattgen_o),
+ .d2h (tl_pattgen_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwm_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_pwm_aon_o),
+ .d2h (tl_pwm_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_gpio_o),
+ .d2h (tl_gpio_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_spi_device_o),
+ .d2h (tl_spi_device_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_rv_timer_o),
+ .d2h (tl_rv_timer_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_pwrmgr_aon_o),
+ .d2h (tl_pwrmgr_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_rstmgr_aon_o),
+ .d2h (tl_rstmgr_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_clkmgr_aon_o),
+ .d2h (tl_clkmgr_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_pinmux_aon_o),
+ .d2h (tl_pinmux_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__core (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_otp_ctrl__core_o),
+ .d2h (tl_otp_ctrl__core_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__prim (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_otp_ctrl__prim_o),
+ .d2h (tl_otp_ctrl__prim_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_lc_ctrl_o),
+ .d2h (tl_lc_ctrl_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sensor_ctrl (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_sensor_ctrl_o),
+ .d2h (tl_sensor_ctrl_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_alert_handler (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_alert_handler_o),
+ .d2h (tl_alert_handler_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__regs (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_sram_ctrl_ret_aon__regs_o),
+ .d2h (tl_sram_ctrl_ret_aon__regs_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__ram (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_sram_ctrl_ret_aon__ram_o),
+ .d2h (tl_sram_ctrl_ret_aon__ram_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_aon_timer_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_aon_timer_aon_o),
+ .d2h (tl_aon_timer_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sysrst_ctrl_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_sysrst_ctrl_aon_o),
+ .d2h (tl_sysrst_ctrl_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_adc_ctrl_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_adc_ctrl_aon_o),
+ .d2h (tl_adc_ctrl_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_ast_o),
+ .d2h (tl_ast_i)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim.core b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
new file mode 100644
index 0000000..e43425d
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_peri_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_peri_sim:0.1"
+description: "XBAR DV sim target"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:top_sencha:xbar_peri
+ - lowrisc:dv:dv_utils
+ - lowrisc:dv:xbar_tb
+ - lowrisc:dv:top_sencha_xbar_peri_bind
+ files:
+ - tb__xbar_connect.sv: {is_include_file: true}
+ - xbar_env_pkg__params.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+
+targets:
+ sim: &sim_target
+ toplevel: xbar_tb_top
+ filesets:
+ - files_dv
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson
new file mode 100644
index 0000000..0dab6d1
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_peri_sim_cfg.hjson file generated by `tlgen.py` tool
+{
+ name: xbar_peri
+
+ // Top level dut name (sv module).
+ dut: xbar_peri
+
+ // The name of the chip this XBAR configuration is made for.
+ top_chip: top_sencha
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson"
+
+ // Add xbar_main specific exclusion files.
+ vcs_cov_excl_files: ["{proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cov_excl.el"]
+
+ // replace common cover.cfg with a generated one, which includes xbar toggle exclusions
+ overrides: [
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cover.cfg"
+ }
+ ]
+ // Import additional common sim cfg files.
+ import_cfgs: [// xbar common sim cfg file
+ "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"]
+}
diff --git a/hw/top_sencha/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_sencha/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
new file mode 100644
index 0000000..c34b64c
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -0,0 +1,102 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tl_peri package generated by `tlgen.py` tool
+
+package tl_peri_pkg;
+
+ localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 40000000;
+ localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 40010000;
+ localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 40020000;
+ localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 40030000;
+ localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 40080000;
+ localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 40090000;
+ localparam logic [31:0] ADDR_SPACE_I2C2 = 32'h 400a0000;
+ localparam logic [31:0] ADDR_SPACE_PATTGEN = 32'h 400e0000;
+ localparam logic [31:0] ADDR_SPACE_PWM_AON = 32'h 40450000;
+ localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
+ localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
+ localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
+ localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 40400000;
+ localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 40410000;
+ localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 40420000;
+ localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 40460000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL__CORE = 32'h 40130000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL__PRIM = 32'h 40132000;
+ localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000;
+ localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40490000;
+ localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40150000;
+ localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__REGS = 32'h 40500000;
+ localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__RAM = 32'h 40600000;
+ localparam logic [31:0] ADDR_SPACE_AON_TIMER_AON = 32'h 40470000;
+ localparam logic [31:0] ADDR_SPACE_SYSRST_CTRL_AON = 32'h 40430000;
+ localparam logic [31:0] ADDR_SPACE_ADC_CTRL_AON = 32'h 40440000;
+ localparam logic [31:0] ADDR_SPACE_AST = 32'h 40480000;
+
+ localparam logic [31:0] ADDR_MASK_UART0 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_UART1 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_UART2 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_UART3 = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_I2C2 = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_PATTGEN = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_PWM_AON = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_GPIO = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00001fff;
+ localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 000001ff;
+ localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00001fff;
+ localparam logic [31:0] ADDR_MASK_OTP_CTRL__PRIM = 32'h 0000001f;
+ localparam logic [31:0] ADDR_MASK_LC_CTRL = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_SENSOR_CTRL = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 000007ff;
+ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__REGS = 32'h 0000001f;
+ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__RAM = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_AON_TIMER_AON = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_SYSRST_CTRL_AON = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_ADC_CTRL_AON = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff;
+
+ localparam int N_HOST = 1;
+ localparam int N_DEVICE = 27;
+
+ typedef enum int {
+ TlUart0 = 0,
+ TlUart1 = 1,
+ TlUart2 = 2,
+ TlUart3 = 3,
+ TlI2C0 = 4,
+ TlI2C1 = 5,
+ TlI2C2 = 6,
+ TlPattgen = 7,
+ TlPwmAon = 8,
+ TlGpio = 9,
+ TlSpiDevice = 10,
+ TlRvTimer = 11,
+ TlPwrmgrAon = 12,
+ TlRstmgrAon = 13,
+ TlClkmgrAon = 14,
+ TlPinmuxAon = 15,
+ TlOtpCtrlCore = 16,
+ TlOtpCtrlPrim = 17,
+ TlLcCtrl = 18,
+ TlSensorCtrl = 19,
+ TlAlertHandler = 20,
+ TlSramCtrlRetAonRegs = 21,
+ TlSramCtrlRetAonRam = 22,
+ TlAonTimerAon = 23,
+ TlSysrstCtrlAon = 24,
+ TlAdcCtrlAon = 25,
+ TlAst = 26
+ } tl_device_e;
+
+ typedef enum int {
+ TlMain = 0
+ } tl_host_e;
+
+endpackage
diff --git a/hw/top_sencha/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_sencha/ip/xbar_peri/rtl/autogen/xbar_peri.sv
new file mode 100644
index 0000000..5c52114
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -0,0 +1,341 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_peri module generated by `tlgen.py` tool
+// all reset signals should be generated from one reset signal to not make any deadlock
+//
+// Interconnect
+// main
+// -> s1n_28
+// -> uart0
+// -> uart1
+// -> uart2
+// -> uart3
+// -> i2c0
+// -> i2c1
+// -> i2c2
+// -> pattgen
+// -> gpio
+// -> spi_device
+// -> rv_timer
+// -> pwrmgr_aon
+// -> rstmgr_aon
+// -> clkmgr_aon
+// -> pinmux_aon
+// -> otp_ctrl.core
+// -> otp_ctrl.prim
+// -> lc_ctrl
+// -> sensor_ctrl
+// -> alert_handler
+// -> ast
+// -> sram_ctrl_ret_aon.ram
+// -> sram_ctrl_ret_aon.regs
+// -> aon_timer_aon
+// -> adc_ctrl_aon
+// -> sysrst_ctrl_aon
+// -> pwm_aon
+
+module xbar_peri (
+ input clk_peri_i,
+ input rst_peri_ni,
+
+ // Host interfaces
+ input tlul_pkg::tl_h2d_t tl_main_i,
+ output tlul_pkg::tl_d2h_t tl_main_o,
+
+ // Device interfaces
+ output tlul_pkg::tl_h2d_t tl_uart0_o,
+ input tlul_pkg::tl_d2h_t tl_uart0_i,
+ output tlul_pkg::tl_h2d_t tl_uart1_o,
+ input tlul_pkg::tl_d2h_t tl_uart1_i,
+ output tlul_pkg::tl_h2d_t tl_uart2_o,
+ input tlul_pkg::tl_d2h_t tl_uart2_i,
+ output tlul_pkg::tl_h2d_t tl_uart3_o,
+ input tlul_pkg::tl_d2h_t tl_uart3_i,
+ output tlul_pkg::tl_h2d_t tl_i2c0_o,
+ input tlul_pkg::tl_d2h_t tl_i2c0_i,
+ output tlul_pkg::tl_h2d_t tl_i2c1_o,
+ input tlul_pkg::tl_d2h_t tl_i2c1_i,
+ output tlul_pkg::tl_h2d_t tl_i2c2_o,
+ input tlul_pkg::tl_d2h_t tl_i2c2_i,
+ output tlul_pkg::tl_h2d_t tl_pattgen_o,
+ input tlul_pkg::tl_d2h_t tl_pattgen_i,
+ output tlul_pkg::tl_h2d_t tl_pwm_aon_o,
+ input tlul_pkg::tl_d2h_t tl_pwm_aon_i,
+ output tlul_pkg::tl_h2d_t tl_gpio_o,
+ input tlul_pkg::tl_d2h_t tl_gpio_i,
+ output tlul_pkg::tl_h2d_t tl_spi_device_o,
+ input tlul_pkg::tl_d2h_t tl_spi_device_i,
+ output tlul_pkg::tl_h2d_t tl_rv_timer_o,
+ input tlul_pkg::tl_d2h_t tl_rv_timer_i,
+ output tlul_pkg::tl_h2d_t tl_pwrmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_pwrmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_rstmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_rstmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_clkmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_pinmux_aon_o,
+ input tlul_pkg::tl_d2h_t tl_pinmux_aon_i,
+ output tlul_pkg::tl_h2d_t tl_otp_ctrl__core_o,
+ input tlul_pkg::tl_d2h_t tl_otp_ctrl__core_i,
+ output tlul_pkg::tl_h2d_t tl_otp_ctrl__prim_o,
+ input tlul_pkg::tl_d2h_t tl_otp_ctrl__prim_i,
+ output tlul_pkg::tl_h2d_t tl_lc_ctrl_o,
+ input tlul_pkg::tl_d2h_t tl_lc_ctrl_i,
+ output tlul_pkg::tl_h2d_t tl_sensor_ctrl_o,
+ input tlul_pkg::tl_d2h_t tl_sensor_ctrl_i,
+ output tlul_pkg::tl_h2d_t tl_alert_handler_o,
+ input tlul_pkg::tl_d2h_t tl_alert_handler_i,
+ output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__regs_o,
+ input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__regs_i,
+ output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__ram_o,
+ input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__ram_i,
+ output tlul_pkg::tl_h2d_t tl_aon_timer_aon_o,
+ input tlul_pkg::tl_d2h_t tl_aon_timer_aon_i,
+ output tlul_pkg::tl_h2d_t tl_sysrst_ctrl_aon_o,
+ input tlul_pkg::tl_d2h_t tl_sysrst_ctrl_aon_i,
+ output tlul_pkg::tl_h2d_t tl_adc_ctrl_aon_o,
+ input tlul_pkg::tl_d2h_t tl_adc_ctrl_aon_i,
+ output tlul_pkg::tl_h2d_t tl_ast_o,
+ input tlul_pkg::tl_d2h_t tl_ast_i,
+
+ input prim_mubi_pkg::mubi4_t scanmode_i
+);
+
+ import tlul_pkg::*;
+ import tl_peri_pkg::*;
+
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = ^scanmode_i;
+
+ tl_h2d_t tl_s1n_28_us_h2d ;
+ tl_d2h_t tl_s1n_28_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_28_ds_h2d [27];
+ tl_d2h_t tl_s1n_28_ds_d2h [27];
+
+ // Create steering signal
+ logic [4:0] dev_sel_s1n_28;
+
+
+
+ assign tl_uart0_o = tl_s1n_28_ds_h2d[0];
+ assign tl_s1n_28_ds_d2h[0] = tl_uart0_i;
+
+ assign tl_uart1_o = tl_s1n_28_ds_h2d[1];
+ assign tl_s1n_28_ds_d2h[1] = tl_uart1_i;
+
+ assign tl_uart2_o = tl_s1n_28_ds_h2d[2];
+ assign tl_s1n_28_ds_d2h[2] = tl_uart2_i;
+
+ assign tl_uart3_o = tl_s1n_28_ds_h2d[3];
+ assign tl_s1n_28_ds_d2h[3] = tl_uart3_i;
+
+ assign tl_i2c0_o = tl_s1n_28_ds_h2d[4];
+ assign tl_s1n_28_ds_d2h[4] = tl_i2c0_i;
+
+ assign tl_i2c1_o = tl_s1n_28_ds_h2d[5];
+ assign tl_s1n_28_ds_d2h[5] = tl_i2c1_i;
+
+ assign tl_i2c2_o = tl_s1n_28_ds_h2d[6];
+ assign tl_s1n_28_ds_d2h[6] = tl_i2c2_i;
+
+ assign tl_pattgen_o = tl_s1n_28_ds_h2d[7];
+ assign tl_s1n_28_ds_d2h[7] = tl_pattgen_i;
+
+ assign tl_gpio_o = tl_s1n_28_ds_h2d[8];
+ assign tl_s1n_28_ds_d2h[8] = tl_gpio_i;
+
+ assign tl_spi_device_o = tl_s1n_28_ds_h2d[9];
+ assign tl_s1n_28_ds_d2h[9] = tl_spi_device_i;
+
+ assign tl_rv_timer_o = tl_s1n_28_ds_h2d[10];
+ assign tl_s1n_28_ds_d2h[10] = tl_rv_timer_i;
+
+ assign tl_pwrmgr_aon_o = tl_s1n_28_ds_h2d[11];
+ assign tl_s1n_28_ds_d2h[11] = tl_pwrmgr_aon_i;
+
+ assign tl_rstmgr_aon_o = tl_s1n_28_ds_h2d[12];
+ assign tl_s1n_28_ds_d2h[12] = tl_rstmgr_aon_i;
+
+ assign tl_clkmgr_aon_o = tl_s1n_28_ds_h2d[13];
+ assign tl_s1n_28_ds_d2h[13] = tl_clkmgr_aon_i;
+
+ assign tl_pinmux_aon_o = tl_s1n_28_ds_h2d[14];
+ assign tl_s1n_28_ds_d2h[14] = tl_pinmux_aon_i;
+
+ assign tl_otp_ctrl__core_o = tl_s1n_28_ds_h2d[15];
+ assign tl_s1n_28_ds_d2h[15] = tl_otp_ctrl__core_i;
+
+ assign tl_otp_ctrl__prim_o = tl_s1n_28_ds_h2d[16];
+ assign tl_s1n_28_ds_d2h[16] = tl_otp_ctrl__prim_i;
+
+ assign tl_lc_ctrl_o = tl_s1n_28_ds_h2d[17];
+ assign tl_s1n_28_ds_d2h[17] = tl_lc_ctrl_i;
+
+ assign tl_sensor_ctrl_o = tl_s1n_28_ds_h2d[18];
+ assign tl_s1n_28_ds_d2h[18] = tl_sensor_ctrl_i;
+
+ assign tl_alert_handler_o = tl_s1n_28_ds_h2d[19];
+ assign tl_s1n_28_ds_d2h[19] = tl_alert_handler_i;
+
+ assign tl_ast_o = tl_s1n_28_ds_h2d[20];
+ assign tl_s1n_28_ds_d2h[20] = tl_ast_i;
+
+ assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_28_ds_h2d[21];
+ assign tl_s1n_28_ds_d2h[21] = tl_sram_ctrl_ret_aon__ram_i;
+
+ assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_28_ds_h2d[22];
+ assign tl_s1n_28_ds_d2h[22] = tl_sram_ctrl_ret_aon__regs_i;
+
+ assign tl_aon_timer_aon_o = tl_s1n_28_ds_h2d[23];
+ assign tl_s1n_28_ds_d2h[23] = tl_aon_timer_aon_i;
+
+ assign tl_adc_ctrl_aon_o = tl_s1n_28_ds_h2d[24];
+ assign tl_s1n_28_ds_d2h[24] = tl_adc_ctrl_aon_i;
+
+ assign tl_sysrst_ctrl_aon_o = tl_s1n_28_ds_h2d[25];
+ assign tl_s1n_28_ds_d2h[25] = tl_sysrst_ctrl_aon_i;
+
+ assign tl_pwm_aon_o = tl_s1n_28_ds_h2d[26];
+ assign tl_s1n_28_ds_d2h[26] = tl_pwm_aon_i;
+
+ assign tl_s1n_28_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_28_us_d2h;
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_28 = 5'd27;
+ if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
+ dev_sel_s1n_28 = 5'd0;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
+ dev_sel_s1n_28 = 5'd1;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
+ dev_sel_s1n_28 = 5'd2;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
+ dev_sel_s1n_28 = 5'd3;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
+ dev_sel_s1n_28 = 5'd4;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
+ dev_sel_s1n_28 = 5'd5;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
+ dev_sel_s1n_28 = 5'd6;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
+ dev_sel_s1n_28 = 5'd7;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_28 = 5'd8;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_28 = 5'd9;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_28 = 5'd10;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin
+ dev_sel_s1n_28 = 5'd11;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin
+ dev_sel_s1n_28 = 5'd12;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin
+ dev_sel_s1n_28 = 5'd13;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin
+ dev_sel_s1n_28 = 5'd14;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin
+ dev_sel_s1n_28 = 5'd15;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin
+ dev_sel_s1n_28 = 5'd16;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
+ dev_sel_s1n_28 = 5'd17;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
+ dev_sel_s1n_28 = 5'd18;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_28 = 5'd19;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin
+ dev_sel_s1n_28 = 5'd20;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin
+ dev_sel_s1n_28 = 5'd21;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin
+ dev_sel_s1n_28 = 5'd22;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin
+ dev_sel_s1n_28 = 5'd23;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_ADC_CTRL_AON)) == ADDR_SPACE_ADC_CTRL_AON) begin
+ dev_sel_s1n_28 = 5'd24;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_SYSRST_CTRL_AON)) == ADDR_SPACE_SYSRST_CTRL_AON) begin
+ dev_sel_s1n_28 = 5'd25;
+
+ end else if ((tl_s1n_28_us_h2d.a_address &
+ ~(ADDR_MASK_PWM_AON)) == ADDR_SPACE_PWM_AON) begin
+ dev_sel_s1n_28 = 5'd26;
+end
+ end
+
+
+ // Instantiation phase
+ tlul_socket_1n #(
+ .HReqDepth (4'h0),
+ .HRspDepth (4'h0),
+ .DReqDepth (108'h0),
+ .DRspDepth (108'h0),
+ .N (27)
+ ) u_s1n_28 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .tl_h_i (tl_s1n_28_us_h2d),
+ .tl_h_o (tl_s1n_28_us_d2h),
+ .tl_d_o (tl_s1n_28_ds_h2d),
+ .tl_d_i (tl_s1n_28_ds_d2h),
+ .dev_select_i (dev_sel_s1n_28)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
new file mode 100644
index 0000000..c214c1b
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.gen.hjson
@@ -0,0 +1,519 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson -o hw/top_sencha/
+
+{
+ name: smc
+ clock_srcs:
+ {
+ clk_smc_i: smc
+ clk_peri_i: io_div4
+ clk_spi_host2_i: io
+ clk_ml_i: ml
+ clk_video_i: video
+ clk_audio_i: audio
+ clk_main_i: main
+ }
+ clock_group: infra
+ reset: rst_smc_ni
+ reset_connections:
+ {
+ rst_smc_ni:
+ {
+ name: smc
+ domain: "0"
+ }
+ rst_peri_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ rst_spi_host2_ni:
+ {
+ name: lc_io
+ domain: "0"
+ }
+ rst_ml_ni:
+ {
+ name: ml
+ domain: "0"
+ }
+ rst_video_ni:
+ {
+ name: video
+ domain: "0"
+ }
+ rst_audio_ni:
+ {
+ name: audio
+ domain: "0"
+ }
+ rst_main_ni:
+ {
+ name: lc
+ domain: "0"
+ }
+ }
+ clock_connections:
+ {
+ clk_smc_i: clkmgr_aon_clocks.clk_smc_infra
+ clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
+ clk_spi_host2_i: clkmgr_aon_clocks.clk_io_infra
+ clk_ml_i: clkmgr_aon_clocks.clk_ml_infra
+ clk_video_i: clkmgr_aon_clocks.clk_video_infra
+ clk_audio_i: clkmgr_aon_clocks.clk_audio_infra
+ clk_main_i: clkmgr_aon_clocks.clk_main_infra
+ }
+ domain:
+ [
+ "0"
+ ]
+ connections:
+ {
+ main:
+ [
+ ram_smc
+ smc_ctrl
+ smc_uart
+ rv_timer_smc
+ cam_i2c
+ cam_ctrl
+ ml_top.dmem
+ ml_top.core
+ isp_wrapper
+ dma_smc
+ spi_host2
+ rv_timer_smc2
+ i2s0
+ ]
+ rv_core_ibex_smc.corei:
+ [
+ ram_smc
+ dbg
+ ]
+ rv_core_ibex_smc.cored:
+ [
+ ram_smc
+ rv_core_ibex_smc.cfg
+ smc_uart
+ rv_timer_smc
+ rv_plic_smc
+ tlul_mailbox_smc
+ cam_i2c
+ cam_ctrl
+ ml_top.dmem
+ ml_top.core
+ isp_wrapper
+ dma_smc
+ spi_host2
+ dbg
+ rv_timer_smc2
+ i2s0
+ ]
+ dma_smc.reader:
+ [
+ ram_smc
+ ml_top.dmem
+ ]
+ dma_smc.writer:
+ [
+ ram_smc
+ ml_top.dmem
+ ]
+ }
+ nodes:
+ [
+ {
+ name: main
+ type: host
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ xbar: true
+ pipeline: "false"
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_core_ibex_smc.corei
+ type: host
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_core_ibex_smc.cored
+ type: host
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: dma_smc.reader
+ type: host
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: dma_smc.writer
+ type: host
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ xbar: false
+ stub: false
+ inst_type: ""
+ req_fifo_pass: true
+ rsp_fifo_pass: true
+ }
+ {
+ name: rv_plic_smc
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ inst_type: rv_plic_smc
+ pipeline_byp: "false"
+ addr_range:
+ [
+ {
+ base_addr: 0x60000000
+ size_byte: 0x8000000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ req_fifo_pass: true
+ }
+ {
+ name: rv_core_ibex_smc.cfg
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline_byp: "false"
+ inst_type: rv_core_smc
+ addr_range:
+ [
+ {
+ base_addr: 0x54030000
+ size_byte: 0x100
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ req_fifo_pass: true
+ }
+ {
+ name: ram_smc
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ inst_type: ram_1p
+ addr_range:
+ [
+ {
+ base_addr: 0x50000000
+ size_byte: 0x400000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: smc_uart
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: uart
+ addr_range:
+ [
+ {
+ base_addr: 0x54000000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: rv_timer_smc
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rv_timer
+ addr_range:
+ [
+ {
+ base_addr: 0x54010000
+ size_byte: 0x200
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: tlul_mailbox_smc
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: tlul_mailbox
+ addr_range:
+ [
+ {
+ base_addr: 0x540f1000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: smc_ctrl
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: smc_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x54020000
+ size_byte: 0x8
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: cam_i2c
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: i2c
+ addr_range:
+ [
+ {
+ base_addr: 0x54040000
+ size_byte: 0x80
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: cam_ctrl
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: cam_ctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x54050000
+ size_byte: 0x10
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: ml_top.dmem
+ type: device
+ clock: clk_ml_i
+ reset: rst_ml_ni
+ pipeline: "false"
+ inst_type: ml_top
+ addr_range:
+ [
+ {
+ base_addr: 0x5a000000
+ size_byte: 0x400000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: ml_top.core
+ type: device
+ clock: clk_ml_i
+ reset: rst_ml_ni
+ pipeline: "false"
+ inst_type: ml_top
+ addr_range:
+ [
+ {
+ base_addr: 0x5c000000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: isp_wrapper
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ inst_type: isp_wrapper
+ addr_range:
+ [
+ {
+ base_addr: 0x54060000
+ size_byte: 0x2000
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: dma_smc
+ type: device
+ clock: clk_smc_i
+ reset: rst_smc_ni
+ pipeline: "false"
+ inst_type: dma
+ addr_range:
+ [
+ {
+ base_addr: 0x54070000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ req_fifo_pass: true
+ }
+ {
+ name: spi_host2
+ type: device
+ clock: clk_spi_host2_i
+ reset: rst_spi_host2_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: spi_host
+ addr_range:
+ [
+ {
+ base_addr: 0x54090000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: dbg
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ xbar: true
+ pipeline: "false"
+ stub: false
+ req_fifo_pass: true
+ addr_range:
+ [
+ {
+ base_addr: 0x4000
+ size_byte: 0x4000
+ }
+ ]
+ }
+ {
+ name: rv_timer_smc2
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: rv_timer
+ addr_range:
+ [
+ {
+ base_addr: 0x54011000
+ size_byte: 0x200
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ {
+ name: i2s0
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ req_fifo_pass: false
+ rsp_fifo_pass: false
+ inst_type: i2s
+ addr_range:
+ [
+ {
+ base_addr: 0x54100000
+ size_byte: 0x40
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: true
+ }
+ ]
+ clock: clk_smc_i
+ type: xbar
+}
diff --git a/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.hjson b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.hjson
new file mode 100644
index 0000000..bf66d84
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/data/autogen/xbar_smc.hjson
@@ -0,0 +1,149 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_smc comportable IP spec generated by `tlgen.py` tool
+{ name: "xbar_smc"
+ clock_primary: ""
+ other_clock_list: []
+ reset_primary: ""
+ other_reset_list: []
+ //available_input_list: []
+
+ inter_signal_list: [
+ // host
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_main"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_smc__corei"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_smc__cored"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma_smc__reader"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma_smc__writer"
+ act: "rsp"
+ package: "tlul_pkg"
+ }
+ // device
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_plic_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_core_ibex_smc__cfg"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_ram_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_smc_uart"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_timer_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_tlul_mailbox_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_smc_ctrl"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_cam_i2c"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_cam_ctrl"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_ml_top__dmem"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_ml_top__core"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_isp_wrapper"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dma_smc"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_spi_host2"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_dbg"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_rv_timer_smc2"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_i2s0"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/tb__xbar_connect.sv b/hw/top_sencha/ip/xbar_smc/dv/autogen/tb__xbar_connect.sv
new file mode 100644
index 0000000..e2435e6
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/tb__xbar_connect.sv
@@ -0,0 +1,58 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tb__xbar_connect generated by `tlgen.py` tool
+
+xbar_smc dut();
+
+`DRIVE_CLK(clk_smc_i)
+`DRIVE_CLK(clk_peri_i)
+`DRIVE_CLK(clk_spi_host2_i)
+`DRIVE_CLK(clk_ml_i)
+`DRIVE_CLK(clk_video_i)
+`DRIVE_CLK(clk_audio_i)
+`DRIVE_CLK(clk_main_i)
+
+initial force dut.clk_smc_i = clk_smc_i;
+initial force dut.clk_peri_i = clk_peri_i;
+initial force dut.clk_spi_host2_i = clk_spi_host2_i;
+initial force dut.clk_ml_i = clk_ml_i;
+initial force dut.clk_video_i = clk_video_i;
+initial force dut.clk_audio_i = clk_audio_i;
+initial force dut.clk_main_i = clk_main_i;
+
+// TODO, all resets tie together
+initial force dut.rst_smc_ni = rst_n;
+initial force dut.rst_peri_ni = rst_n;
+initial force dut.rst_spi_host2_ni = rst_n;
+initial force dut.rst_ml_ni = rst_n;
+initial force dut.rst_video_ni = rst_n;
+initial force dut.rst_audio_ni = rst_n;
+initial force dut.rst_main_ni = rst_n;
+
+// Host TileLink interface connections
+`CONNECT_TL_HOST_IF(main, dut, clk_smc_i, rst_n)
+`CONNECT_TL_HOST_IF(rv_core_ibex_smc__corei, dut, clk_smc_i, rst_n)
+`CONNECT_TL_HOST_IF(rv_core_ibex_smc__cored, dut, clk_smc_i, rst_n)
+`CONNECT_TL_HOST_IF(dma_smc__reader, dut, clk_smc_i, rst_n)
+`CONNECT_TL_HOST_IF(dma_smc__writer, dut, clk_smc_i, rst_n)
+
+// Device TileLink interface connections
+`CONNECT_TL_DEVICE_IF(rv_plic_smc, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_core_ibex_smc__cfg, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ram_smc, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(smc_uart, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_timer_smc, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(tlul_mailbox_smc, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(smc_ctrl, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(cam_i2c, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(cam_ctrl, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ml_top__dmem, dut, clk_ml_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ml_top__core, dut, clk_ml_i, rst_n)
+`CONNECT_TL_DEVICE_IF(isp_wrapper, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(dma_smc, dut, clk_smc_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host2, dut, clk_spi_host2_i, rst_n)
+`CONNECT_TL_DEVICE_IF(dbg, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rv_timer_smc2, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(i2s0, dut, clk_peri_i, rst_n)
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cov_excl.el b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cov_excl.el
new file mode 100644
index 0000000..c2dcefe
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cov_excl.el
@@ -0,0 +1,36 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cov_excl.el generated by `tlgen.py` tool
+
+ANNOTATION: "[NON_RTL]"
+MODULE: uvm_pkg
+Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion"
+Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion"
+
+ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim"
+MODULE: xbar_smc
+Block 1 "0" "assign unused_scanmode = scanmode_i;"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_fifo_sync
+Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=3,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=4,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
+ANNOTATION: "[UNR]"
+MODULE: prim_arbiter_ppc ( parameter N=5,DW=102,EnDataPort=1,EnReqStabA=0 )
+Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10")
+
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
new file mode 100644
index 0000000..d636d14
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_cover.cfg
@@ -0,0 +1,105 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_cover.cfg generated by `tlgen.py` tool
+
++tree tb.dut
+-module pins_if // DV construct.
+-module clk_rst_if // DV construct.
+
+-assert legalAOpcodeErr_A
+-assert sizeGTEMaskErr_A
+-assert sizeMatchesMaskErr_A
+-assert addrSizeAlignedErr_A
+
+// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after.
+-node tb.dut tl_*.a_param
+-node tb.dut tl_*.d_param
+-node tb.dut tl_*.d_opcode[2:1]
+
+// [UNR] these device address bits are always 0
+-node tb.dut tl_rv_plic_smc_o.a_address[28:27]
+-node tb.dut tl_rv_plic_smc_o.a_address[31:31]
+-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[15:8]
+-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[25:18]
+-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[27:27]
+-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[29:29]
+-node tb.dut tl_rv_core_ibex_smc__cfg_o.a_address[31:31]
+-node tb.dut tl_ram_smc_o.a_address[27:22]
+-node tb.dut tl_ram_smc_o.a_address[29:29]
+-node tb.dut tl_ram_smc_o.a_address[31:31]
+-node tb.dut tl_smc_uart_o.a_address[25:6]
+-node tb.dut tl_smc_uart_o.a_address[27:27]
+-node tb.dut tl_smc_uart_o.a_address[29:29]
+-node tb.dut tl_smc_uart_o.a_address[31:31]
+-node tb.dut tl_rv_timer_smc_o.a_address[15:9]
+-node tb.dut tl_rv_timer_smc_o.a_address[25:17]
+-node tb.dut tl_rv_timer_smc_o.a_address[27:27]
+-node tb.dut tl_rv_timer_smc_o.a_address[29:29]
+-node tb.dut tl_rv_timer_smc_o.a_address[31:31]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[11:6]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[15:13]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[25:20]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[27:27]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[29:29]
+-node tb.dut tl_tlul_mailbox_smc_o.a_address[31:31]
+-node tb.dut tl_smc_ctrl_o.a_address[16:3]
+-node tb.dut tl_smc_ctrl_o.a_address[25:18]
+-node tb.dut tl_smc_ctrl_o.a_address[27:27]
+-node tb.dut tl_smc_ctrl_o.a_address[29:29]
+-node tb.dut tl_smc_ctrl_o.a_address[31:31]
+-node tb.dut tl_cam_i2c_o.a_address[17:7]
+-node tb.dut tl_cam_i2c_o.a_address[25:19]
+-node tb.dut tl_cam_i2c_o.a_address[27:27]
+-node tb.dut tl_cam_i2c_o.a_address[29:29]
+-node tb.dut tl_cam_i2c_o.a_address[31:31]
+-node tb.dut tl_cam_ctrl_o.a_address[15:4]
+-node tb.dut tl_cam_ctrl_o.a_address[17:17]
+-node tb.dut tl_cam_ctrl_o.a_address[25:19]
+-node tb.dut tl_cam_ctrl_o.a_address[27:27]
+-node tb.dut tl_cam_ctrl_o.a_address[29:29]
+-node tb.dut tl_cam_ctrl_o.a_address[31:31]
+-node tb.dut tl_ml_top__dmem_o.a_address[24:22]
+-node tb.dut tl_ml_top__dmem_o.a_address[26:26]
+-node tb.dut tl_ml_top__dmem_o.a_address[29:29]
+-node tb.dut tl_ml_top__dmem_o.a_address[31:31]
+-node tb.dut tl_ml_top__core_o.a_address[25:6]
+-node tb.dut tl_ml_top__core_o.a_address[29:29]
+-node tb.dut tl_ml_top__core_o.a_address[31:31]
+-node tb.dut tl_isp_wrapper_o.a_address[16:13]
+-node tb.dut tl_isp_wrapper_o.a_address[25:19]
+-node tb.dut tl_isp_wrapper_o.a_address[27:27]
+-node tb.dut tl_isp_wrapper_o.a_address[29:29]
+-node tb.dut tl_isp_wrapper_o.a_address[31:31]
+-node tb.dut tl_dma_smc_o.a_address[15:6]
+-node tb.dut tl_dma_smc_o.a_address[25:19]
+-node tb.dut tl_dma_smc_o.a_address[27:27]
+-node tb.dut tl_dma_smc_o.a_address[29:29]
+-node tb.dut tl_dma_smc_o.a_address[31:31]
+-node tb.dut tl_spi_host2_o.a_address[15:6]
+-node tb.dut tl_spi_host2_o.a_address[18:17]
+-node tb.dut tl_spi_host2_o.a_address[25:20]
+-node tb.dut tl_spi_host2_o.a_address[27:27]
+-node tb.dut tl_spi_host2_o.a_address[29:29]
+-node tb.dut tl_spi_host2_o.a_address[31:31]
+-node tb.dut tl_dbg_o.a_address[31:15]
+-node tb.dut tl_rv_timer_smc2_o.a_address[11:9]
+-node tb.dut tl_rv_timer_smc2_o.a_address[15:13]
+-node tb.dut tl_rv_timer_smc2_o.a_address[25:17]
+-node tb.dut tl_rv_timer_smc2_o.a_address[27:27]
+-node tb.dut tl_rv_timer_smc2_o.a_address[29:29]
+-node tb.dut tl_rv_timer_smc2_o.a_address[31:31]
+-node tb.dut tl_i2s0_o.a_address[19:6]
+-node tb.dut tl_i2s0_o.a_address[25:21]
+-node tb.dut tl_i2s0_o.a_address[27:27]
+-node tb.dut tl_i2s0_o.a_address[29:29]
+-node tb.dut tl_i2s0_o.a_address[31:31]
+
+-node tb.dut tl_*.a_source[7:5]
+-node tb.dut tl_*.d_source[7:5]
+begin tgl
+ -tree tb
+ +tree tb.dut 1
+ -node tb.dut.scanmode_i
+end
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
new file mode 100644
index 0000000..b557ab1
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_env_pkg__params.sv
@@ -0,0 +1,108 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_env_pkg__params generated by `tlgen.py` tool
+
+
+// List of Xbar device memory map
+tl_device_t xbar_devices[$] = '{
+ '{"rv_plic_smc", '{
+ '{32'h60000000, 32'h67ffffff}
+ }},
+ '{"rv_core_ibex_smc__cfg", '{
+ '{32'h54030000, 32'h540300ff}
+ }},
+ '{"ram_smc", '{
+ '{32'h50000000, 32'h503fffff}
+ }},
+ '{"smc_uart", '{
+ '{32'h54000000, 32'h5400003f}
+ }},
+ '{"rv_timer_smc", '{
+ '{32'h54010000, 32'h540101ff}
+ }},
+ '{"tlul_mailbox_smc", '{
+ '{32'h540f1000, 32'h540f103f}
+ }},
+ '{"smc_ctrl", '{
+ '{32'h54020000, 32'h54020007}
+ }},
+ '{"cam_i2c", '{
+ '{32'h54040000, 32'h5404007f}
+ }},
+ '{"cam_ctrl", '{
+ '{32'h54050000, 32'h5405000f}
+ }},
+ '{"ml_top__dmem", '{
+ '{32'h5a000000, 32'h5a3fffff}
+ }},
+ '{"ml_top__core", '{
+ '{32'h5c000000, 32'h5c00003f}
+ }},
+ '{"isp_wrapper", '{
+ '{32'h54060000, 32'h54061fff}
+ }},
+ '{"dma_smc", '{
+ '{32'h54070000, 32'h5407003f}
+ }},
+ '{"spi_host2", '{
+ '{32'h54090000, 32'h5409003f}
+ }},
+ '{"dbg", '{
+ '{32'h00004000, 32'h00007fff}
+ }},
+ '{"rv_timer_smc2", '{
+ '{32'h54011000, 32'h540111ff}
+ }},
+ '{"i2s0", '{
+ '{32'h54100000, 32'h5410003f}
+}}};
+
+ // List of Xbar hosts
+tl_host_t xbar_hosts[$] = '{
+ '{"main", 0, '{
+ "ram_smc",
+ "smc_ctrl",
+ "smc_uart",
+ "rv_timer_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "rv_timer_smc2",
+ "i2s0"}}
+ ,
+ '{"rv_core_ibex_smc__corei", 1, '{
+ "ram_smc",
+ "dbg"}}
+ ,
+ '{"rv_core_ibex_smc__cored", 2, '{
+ "ram_smc",
+ "rv_core_ibex_smc__cfg",
+ "smc_uart",
+ "rv_timer_smc",
+ "rv_plic_smc",
+ "tlul_mailbox_smc",
+ "cam_i2c",
+ "cam_ctrl",
+ "ml_top__dmem",
+ "ml_top__core",
+ "isp_wrapper",
+ "dma_smc",
+ "spi_host2",
+ "dbg",
+ "rv_timer_smc2",
+ "i2s0"}}
+ ,
+ '{"dma_smc__reader", 3, '{
+ "ram_smc",
+ "ml_top__dmem"}}
+ ,
+ '{"dma_smc__writer", 4, '{
+ "ram_smc",
+ "ml_top__dmem"}}
+};
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.core b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.core
new file mode 100644
index 0000000..4c0dae8
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_smc_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_smc_bind:0.1"
+description: "XBAR smc assertion bind"
+filesets:
+ files_dv:
+ files:
+ - xbar_smc_bind.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.sv b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.sv
new file mode 100644
index 0000000..2804a7e
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_bind.sv
@@ -0,0 +1,144 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_smc_bind module generated by `tlgen.py` tool for assertions
+module xbar_smc_bind;
+
+ // Host interfaces
+ bind xbar_smc tlul_assert #(.EndpointType("Device")) tlul_assert_host_main (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_main_i),
+ .d2h (tl_main_o)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex_smc__corei (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_rv_core_ibex_smc__corei_i),
+ .d2h (tl_rv_core_ibex_smc__corei_o)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_core_ibex_smc__cored (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_rv_core_ibex_smc__cored_i),
+ .d2h (tl_rv_core_ibex_smc__cored_o)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma_smc__reader (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_dma_smc__reader_i),
+ .d2h (tl_dma_smc__reader_o)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma_smc__writer (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_dma_smc__writer_i),
+ .d2h (tl_dma_smc__writer_o)
+ );
+
+ // Device interfaces
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_plic_smc (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_rv_plic_smc_o),
+ .d2h (tl_rv_plic_smc_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_core_ibex_smc__cfg (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_rv_core_ibex_smc__cfg_o),
+ .d2h (tl_rv_core_ibex_smc__cfg_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_ram_smc (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_ram_smc_o),
+ .d2h (tl_ram_smc_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_smc_uart (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_smc_uart_o),
+ .d2h (tl_smc_uart_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer_smc (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_rv_timer_smc_o),
+ .d2h (tl_rv_timer_smc_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_tlul_mailbox_smc (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_tlul_mailbox_smc_o),
+ .d2h (tl_tlul_mailbox_smc_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_smc_ctrl (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_smc_ctrl_o),
+ .d2h (tl_smc_ctrl_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_cam_i2c (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_cam_i2c_o),
+ .d2h (tl_cam_i2c_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_cam_ctrl (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_cam_ctrl_o),
+ .d2h (tl_cam_ctrl_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_ml_top__dmem (
+ .clk_i (clk_ml_i),
+ .rst_ni (rst_ml_ni),
+ .h2d (tl_ml_top__dmem_o),
+ .d2h (tl_ml_top__dmem_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_ml_top__core (
+ .clk_i (clk_ml_i),
+ .rst_ni (rst_ml_ni),
+ .h2d (tl_ml_top__core_o),
+ .d2h (tl_ml_top__core_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_isp_wrapper (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_isp_wrapper_o),
+ .d2h (tl_isp_wrapper_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_dma_smc (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .h2d (tl_dma_smc_o),
+ .d2h (tl_dma_smc_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host2 (
+ .clk_i (clk_spi_host2_i),
+ .rst_ni (rst_spi_host2_ni),
+ .h2d (tl_spi_host2_o),
+ .d2h (tl_spi_host2_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_dbg (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_dbg_o),
+ .d2h (tl_dbg_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer_smc2 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_rv_timer_smc2_o),
+ .d2h (tl_rv_timer_smc2_i)
+ );
+ bind xbar_smc tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2s0 (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_i2s0_o),
+ .d2h (tl_i2s0_i)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim.core b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim.core
new file mode 100644
index 0000000..420cb16
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim.core
@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# xbar_smc_sim core file generated by `tlgen.py` tool
+name: "lowrisc:dv:top_sencha_xbar_smc_sim:0.1"
+description: "XBAR DV sim target"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:top_sencha:xbar_smc
+ - lowrisc:dv:dv_utils
+ - lowrisc:dv:xbar_tb
+ - lowrisc:dv:top_sencha_xbar_smc_bind
+ files:
+ - tb__xbar_connect.sv: {is_include_file: true}
+ - xbar_env_pkg__params.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+
+targets:
+ sim: &sim_target
+ toplevel: xbar_tb_top
+ filesets:
+ - files_dv
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim_cfg.hjson b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim_cfg.hjson
new file mode 100644
index 0000000..0175f39
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/dv/autogen/xbar_smc_sim_cfg.hjson
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_smc_sim_cfg.hjson file generated by `tlgen.py` tool
+{
+ name: xbar_smc
+
+ // Top level dut name (sv module).
+ dut: xbar_smc
+
+ // The name of the chip this XBAR configuration is made for.
+ top_chip: top_sencha
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson"
+
+ // Add xbar_main specific exclusion files.
+ vcs_cov_excl_files: ["{proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cov_excl.el"]
+
+ // replace common cover.cfg with a generated one, which includes xbar toggle exclusions
+ overrides: [
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/top_sencha/ip/{dut}/dv/autogen/xbar_cover.cfg"
+ }
+ ]
+ // Import additional common sim cfg files.
+ import_cfgs: [// xbar common sim cfg file
+ "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"]
+}
diff --git a/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
new file mode 100644
index 0000000..c9661f8
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/rtl/autogen/tl_smc_pkg.sv
@@ -0,0 +1,80 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// tl_smc package generated by `tlgen.py` tool
+
+package tl_smc_pkg;
+
+ localparam logic [31:0] ADDR_SPACE_RV_PLIC_SMC = 32'h 60000000;
+ localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX_SMC__CFG = 32'h 54030000;
+ localparam logic [31:0] ADDR_SPACE_RAM_SMC = 32'h 50000000;
+ localparam logic [31:0] ADDR_SPACE_SMC_UART = 32'h 54000000;
+ localparam logic [31:0] ADDR_SPACE_RV_TIMER_SMC = 32'h 54010000;
+ localparam logic [31:0] ADDR_SPACE_TLUL_MAILBOX_SMC = 32'h 540f1000;
+ localparam logic [31:0] ADDR_SPACE_SMC_CTRL = 32'h 54020000;
+ localparam logic [31:0] ADDR_SPACE_CAM_I2C = 32'h 54040000;
+ localparam logic [31:0] ADDR_SPACE_CAM_CTRL = 32'h 54050000;
+ localparam logic [31:0] ADDR_SPACE_ML_TOP__DMEM = 32'h 5a000000;
+ localparam logic [31:0] ADDR_SPACE_ML_TOP__CORE = 32'h 5c000000;
+ localparam logic [31:0] ADDR_SPACE_ISP_WRAPPER = 32'h 54060000;
+ localparam logic [31:0] ADDR_SPACE_DMA_SMC = 32'h 54070000;
+ localparam logic [31:0] ADDR_SPACE_SPI_HOST2 = 32'h 54090000;
+ localparam logic [0:0][31:0] ADDR_SPACE_DBG = {
+ 32'h 00004000
+ };
+ localparam logic [31:0] ADDR_SPACE_RV_TIMER_SMC2 = 32'h 54011000;
+ localparam logic [31:0] ADDR_SPACE_I2S0 = 32'h 54100000;
+
+ localparam logic [31:0] ADDR_MASK_RV_PLIC_SMC = 32'h 07ffffff;
+ localparam logic [31:0] ADDR_MASK_RV_CORE_IBEX_SMC__CFG = 32'h 000000ff;
+ localparam logic [31:0] ADDR_MASK_RAM_SMC = 32'h 003fffff;
+ localparam logic [31:0] ADDR_MASK_SMC_UART = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_RV_TIMER_SMC = 32'h 000001ff;
+ localparam logic [31:0] ADDR_MASK_TLUL_MAILBOX_SMC = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_SMC_CTRL = 32'h 00000007;
+ localparam logic [31:0] ADDR_MASK_CAM_I2C = 32'h 0000007f;
+ localparam logic [31:0] ADDR_MASK_CAM_CTRL = 32'h 0000000f;
+ localparam logic [31:0] ADDR_MASK_ML_TOP__DMEM = 32'h 003fffff;
+ localparam logic [31:0] ADDR_MASK_ML_TOP__CORE = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_ISP_WRAPPER = 32'h 00001fff;
+ localparam logic [31:0] ADDR_MASK_DMA_SMC = 32'h 0000003f;
+ localparam logic [31:0] ADDR_MASK_SPI_HOST2 = 32'h 0000003f;
+ localparam logic [0:0][31:0] ADDR_MASK_DBG = {
+ 32'h 00003fff
+ };
+ localparam logic [31:0] ADDR_MASK_RV_TIMER_SMC2 = 32'h 000001ff;
+ localparam logic [31:0] ADDR_MASK_I2S0 = 32'h 0000003f;
+
+ localparam int N_HOST = 5;
+ localparam int N_DEVICE = 17;
+
+ typedef enum int {
+ TlRvPlicSmc = 0,
+ TlRvCoreIbexSmcCfg = 1,
+ TlRamSmc = 2,
+ TlSmcUart = 3,
+ TlRvTimerSmc = 4,
+ TlTlulMailboxSmc = 5,
+ TlSmcCtrl = 6,
+ TlCamI2C = 7,
+ TlCamCtrl = 8,
+ TlMlTopDmem = 9,
+ TlMlTopCore = 10,
+ TlIspWrapper = 11,
+ TlDmaSmc = 12,
+ TlSpiHost2 = 13,
+ TlDbg = 14,
+ TlRvTimerSmc2 = 15,
+ TlI2S0 = 16
+ } tl_device_e;
+
+ typedef enum int {
+ TlMain = 0,
+ TlRvCoreIbexSmcCorei = 1,
+ TlRvCoreIbexSmcCored = 2,
+ TlDmaSmcReader = 3,
+ TlDmaSmcWriter = 4
+ } tl_host_e;
+
+endpackage
diff --git a/hw/top_sencha/ip/xbar_smc/rtl/autogen/xbar_smc.sv b/hw/top_sencha/ip/xbar_smc/rtl/autogen/xbar_smc.sv
new file mode 100644
index 0000000..9d9aed5
--- /dev/null
+++ b/hw/top_sencha/ip/xbar_smc/rtl/autogen/xbar_smc.sv
@@ -0,0 +1,1132 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// xbar_smc module generated by `tlgen.py` tool
+// all reset signals should be generated from one reset signal to not make any deadlock
+//
+// Interconnect
+// main
+// -> s1n_22
+// -> sm1_23
+// -> ram_smc
+// -> smc_ctrl
+// -> sm1_25
+// -> asf_24
+// -> smc_uart
+// -> sm1_27
+// -> asf_26
+// -> rv_timer_smc
+// -> sm1_29
+// -> asf_28
+// -> cam_i2c
+// -> sm1_31
+// -> asf_30
+// -> cam_ctrl
+// -> sm1_33
+// -> asf_32
+// -> ml_top.dmem
+// -> sm1_35
+// -> asf_34
+// -> ml_top.core
+// -> sm1_36
+// -> isp_wrapper
+// -> sm1_37
+// -> dma_smc
+// -> sm1_39
+// -> asf_38
+// -> spi_host2
+// -> sm1_41
+// -> asf_40
+// -> rv_timer_smc2
+// -> sm1_43
+// -> asf_42
+// -> i2s0
+// rv_core_ibex_smc.corei
+// -> s1n_44
+// -> sm1_23
+// -> ram_smc
+// -> sm1_46
+// -> asf_45
+// -> dbg
+// rv_core_ibex_smc.cored
+// -> s1n_47
+// -> sm1_23
+// -> ram_smc
+// -> rv_core_ibex_smc.cfg
+// -> sm1_25
+// -> asf_24
+// -> smc_uart
+// -> sm1_27
+// -> asf_26
+// -> rv_timer_smc
+// -> rv_plic_smc
+// -> asf_48
+// -> tlul_mailbox_smc
+// -> sm1_29
+// -> asf_28
+// -> cam_i2c
+// -> sm1_31
+// -> asf_30
+// -> cam_ctrl
+// -> sm1_33
+// -> asf_32
+// -> ml_top.dmem
+// -> sm1_35
+// -> asf_34
+// -> ml_top.core
+// -> sm1_36
+// -> isp_wrapper
+// -> sm1_37
+// -> dma_smc
+// -> sm1_39
+// -> asf_38
+// -> spi_host2
+// -> sm1_46
+// -> asf_45
+// -> dbg
+// -> sm1_41
+// -> asf_40
+// -> rv_timer_smc2
+// -> sm1_43
+// -> asf_42
+// -> i2s0
+// dma_smc.reader
+// -> s1n_49
+// -> sm1_23
+// -> ram_smc
+// -> sm1_33
+// -> asf_32
+// -> ml_top.dmem
+// dma_smc.writer
+// -> s1n_50
+// -> sm1_23
+// -> ram_smc
+// -> sm1_33
+// -> asf_32
+// -> ml_top.dmem
+
+module xbar_smc (
+ input clk_smc_i,
+ input clk_peri_i,
+ input clk_spi_host2_i,
+ input clk_ml_i,
+ input clk_video_i,
+ input clk_audio_i,
+ input clk_main_i,
+ input rst_smc_ni,
+ input rst_peri_ni,
+ input rst_spi_host2_ni,
+ input rst_ml_ni,
+ input rst_video_ni,
+ input rst_audio_ni,
+ input rst_main_ni,
+
+ // Host interfaces
+ input tlul_pkg::tl_h2d_t tl_main_i,
+ output tlul_pkg::tl_d2h_t tl_main_o,
+ input tlul_pkg::tl_h2d_t tl_rv_core_ibex_smc__corei_i,
+ output tlul_pkg::tl_d2h_t tl_rv_core_ibex_smc__corei_o,
+ input tlul_pkg::tl_h2d_t tl_rv_core_ibex_smc__cored_i,
+ output tlul_pkg::tl_d2h_t tl_rv_core_ibex_smc__cored_o,
+ input tlul_pkg::tl_h2d_t tl_dma_smc__reader_i,
+ output tlul_pkg::tl_d2h_t tl_dma_smc__reader_o,
+ input tlul_pkg::tl_h2d_t tl_dma_smc__writer_i,
+ output tlul_pkg::tl_d2h_t tl_dma_smc__writer_o,
+
+ // Device interfaces
+ output tlul_pkg::tl_h2d_t tl_rv_plic_smc_o,
+ input tlul_pkg::tl_d2h_t tl_rv_plic_smc_i,
+ output tlul_pkg::tl_h2d_t tl_rv_core_ibex_smc__cfg_o,
+ input tlul_pkg::tl_d2h_t tl_rv_core_ibex_smc__cfg_i,
+ output tlul_pkg::tl_h2d_t tl_ram_smc_o,
+ input tlul_pkg::tl_d2h_t tl_ram_smc_i,
+ output tlul_pkg::tl_h2d_t tl_smc_uart_o,
+ input tlul_pkg::tl_d2h_t tl_smc_uart_i,
+ output tlul_pkg::tl_h2d_t tl_rv_timer_smc_o,
+ input tlul_pkg::tl_d2h_t tl_rv_timer_smc_i,
+ output tlul_pkg::tl_h2d_t tl_tlul_mailbox_smc_o,
+ input tlul_pkg::tl_d2h_t tl_tlul_mailbox_smc_i,
+ output tlul_pkg::tl_h2d_t tl_smc_ctrl_o,
+ input tlul_pkg::tl_d2h_t tl_smc_ctrl_i,
+ output tlul_pkg::tl_h2d_t tl_cam_i2c_o,
+ input tlul_pkg::tl_d2h_t tl_cam_i2c_i,
+ output tlul_pkg::tl_h2d_t tl_cam_ctrl_o,
+ input tlul_pkg::tl_d2h_t tl_cam_ctrl_i,
+ output tlul_pkg::tl_h2d_t tl_ml_top__dmem_o,
+ input tlul_pkg::tl_d2h_t tl_ml_top__dmem_i,
+ output tlul_pkg::tl_h2d_t tl_ml_top__core_o,
+ input tlul_pkg::tl_d2h_t tl_ml_top__core_i,
+ output tlul_pkg::tl_h2d_t tl_isp_wrapper_o,
+ input tlul_pkg::tl_d2h_t tl_isp_wrapper_i,
+ output tlul_pkg::tl_h2d_t tl_dma_smc_o,
+ input tlul_pkg::tl_d2h_t tl_dma_smc_i,
+ output tlul_pkg::tl_h2d_t tl_spi_host2_o,
+ input tlul_pkg::tl_d2h_t tl_spi_host2_i,
+ output tlul_pkg::tl_h2d_t tl_dbg_o,
+ input tlul_pkg::tl_d2h_t tl_dbg_i,
+ output tlul_pkg::tl_h2d_t tl_rv_timer_smc2_o,
+ input tlul_pkg::tl_d2h_t tl_rv_timer_smc2_i,
+ output tlul_pkg::tl_h2d_t tl_i2s0_o,
+ input tlul_pkg::tl_d2h_t tl_i2s0_i,
+
+ input prim_mubi_pkg::mubi4_t scanmode_i
+);
+
+ import tlul_pkg::*;
+ import tl_smc_pkg::*;
+
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = ^scanmode_i;
+
+ tl_h2d_t tl_s1n_22_us_h2d ;
+ tl_d2h_t tl_s1n_22_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_22_ds_h2d [13];
+ tl_d2h_t tl_s1n_22_ds_d2h [13];
+
+ // Create steering signal
+ logic [3:0] dev_sel_s1n_22;
+
+
+ tl_h2d_t tl_sm1_23_us_h2d [5];
+ tl_d2h_t tl_sm1_23_us_d2h [5];
+
+ tl_h2d_t tl_sm1_23_ds_h2d ;
+ tl_d2h_t tl_sm1_23_ds_d2h ;
+
+ tl_h2d_t tl_asf_24_us_h2d ;
+ tl_d2h_t tl_asf_24_us_d2h ;
+ tl_h2d_t tl_asf_24_ds_h2d ;
+ tl_d2h_t tl_asf_24_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_25_us_h2d [2];
+ tl_d2h_t tl_sm1_25_us_d2h [2];
+
+ tl_h2d_t tl_sm1_25_ds_h2d ;
+ tl_d2h_t tl_sm1_25_ds_d2h ;
+
+ tl_h2d_t tl_asf_26_us_h2d ;
+ tl_d2h_t tl_asf_26_us_d2h ;
+ tl_h2d_t tl_asf_26_ds_h2d ;
+ tl_d2h_t tl_asf_26_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_27_us_h2d [2];
+ tl_d2h_t tl_sm1_27_us_d2h [2];
+
+ tl_h2d_t tl_sm1_27_ds_h2d ;
+ tl_d2h_t tl_sm1_27_ds_d2h ;
+
+ tl_h2d_t tl_asf_28_us_h2d ;
+ tl_d2h_t tl_asf_28_us_d2h ;
+ tl_h2d_t tl_asf_28_ds_h2d ;
+ tl_d2h_t tl_asf_28_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_29_us_h2d [2];
+ tl_d2h_t tl_sm1_29_us_d2h [2];
+
+ tl_h2d_t tl_sm1_29_ds_h2d ;
+ tl_d2h_t tl_sm1_29_ds_d2h ;
+
+ tl_h2d_t tl_asf_30_us_h2d ;
+ tl_d2h_t tl_asf_30_us_d2h ;
+ tl_h2d_t tl_asf_30_ds_h2d ;
+ tl_d2h_t tl_asf_30_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_31_us_h2d [2];
+ tl_d2h_t tl_sm1_31_us_d2h [2];
+
+ tl_h2d_t tl_sm1_31_ds_h2d ;
+ tl_d2h_t tl_sm1_31_ds_d2h ;
+
+ tl_h2d_t tl_asf_32_us_h2d ;
+ tl_d2h_t tl_asf_32_us_d2h ;
+ tl_h2d_t tl_asf_32_ds_h2d ;
+ tl_d2h_t tl_asf_32_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_33_us_h2d [4];
+ tl_d2h_t tl_sm1_33_us_d2h [4];
+
+ tl_h2d_t tl_sm1_33_ds_h2d ;
+ tl_d2h_t tl_sm1_33_ds_d2h ;
+
+ tl_h2d_t tl_asf_34_us_h2d ;
+ tl_d2h_t tl_asf_34_us_d2h ;
+ tl_h2d_t tl_asf_34_ds_h2d ;
+ tl_d2h_t tl_asf_34_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_35_us_h2d [2];
+ tl_d2h_t tl_sm1_35_us_d2h [2];
+
+ tl_h2d_t tl_sm1_35_ds_h2d ;
+ tl_d2h_t tl_sm1_35_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_36_us_h2d [2];
+ tl_d2h_t tl_sm1_36_us_d2h [2];
+
+ tl_h2d_t tl_sm1_36_ds_h2d ;
+ tl_d2h_t tl_sm1_36_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_37_us_h2d [2];
+ tl_d2h_t tl_sm1_37_us_d2h [2];
+
+ tl_h2d_t tl_sm1_37_ds_h2d ;
+ tl_d2h_t tl_sm1_37_ds_d2h ;
+
+ tl_h2d_t tl_asf_38_us_h2d ;
+ tl_d2h_t tl_asf_38_us_d2h ;
+ tl_h2d_t tl_asf_38_ds_h2d ;
+ tl_d2h_t tl_asf_38_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_39_us_h2d [2];
+ tl_d2h_t tl_sm1_39_us_d2h [2];
+
+ tl_h2d_t tl_sm1_39_ds_h2d ;
+ tl_d2h_t tl_sm1_39_ds_d2h ;
+
+ tl_h2d_t tl_asf_40_us_h2d ;
+ tl_d2h_t tl_asf_40_us_d2h ;
+ tl_h2d_t tl_asf_40_ds_h2d ;
+ tl_d2h_t tl_asf_40_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_41_us_h2d [2];
+ tl_d2h_t tl_sm1_41_us_d2h [2];
+
+ tl_h2d_t tl_sm1_41_ds_h2d ;
+ tl_d2h_t tl_sm1_41_ds_d2h ;
+
+ tl_h2d_t tl_asf_42_us_h2d ;
+ tl_d2h_t tl_asf_42_us_d2h ;
+ tl_h2d_t tl_asf_42_ds_h2d ;
+ tl_d2h_t tl_asf_42_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_43_us_h2d [2];
+ tl_d2h_t tl_sm1_43_us_d2h [2];
+
+ tl_h2d_t tl_sm1_43_ds_h2d ;
+ tl_d2h_t tl_sm1_43_ds_d2h ;
+
+ tl_h2d_t tl_s1n_44_us_h2d ;
+ tl_d2h_t tl_s1n_44_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_44_ds_h2d [2];
+ tl_d2h_t tl_s1n_44_ds_d2h [2];
+
+ // Create steering signal
+ logic [1:0] dev_sel_s1n_44;
+
+ tl_h2d_t tl_asf_45_us_h2d ;
+ tl_d2h_t tl_asf_45_us_d2h ;
+ tl_h2d_t tl_asf_45_ds_h2d ;
+ tl_d2h_t tl_asf_45_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_46_us_h2d [2];
+ tl_d2h_t tl_sm1_46_us_d2h [2];
+
+ tl_h2d_t tl_sm1_46_ds_h2d ;
+ tl_d2h_t tl_sm1_46_ds_d2h ;
+
+ tl_h2d_t tl_s1n_47_us_h2d ;
+ tl_d2h_t tl_s1n_47_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_47_ds_h2d [16];
+ tl_d2h_t tl_s1n_47_ds_d2h [16];
+
+ // Create steering signal
+ logic [4:0] dev_sel_s1n_47;
+
+ tl_h2d_t tl_asf_48_us_h2d ;
+ tl_d2h_t tl_asf_48_us_d2h ;
+ tl_h2d_t tl_asf_48_ds_h2d ;
+ tl_d2h_t tl_asf_48_ds_d2h ;
+
+ tl_h2d_t tl_s1n_49_us_h2d ;
+ tl_d2h_t tl_s1n_49_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_49_ds_h2d [2];
+ tl_d2h_t tl_s1n_49_ds_d2h [2];
+
+ // Create steering signal
+ logic [1:0] dev_sel_s1n_49;
+
+ tl_h2d_t tl_s1n_50_us_h2d ;
+ tl_d2h_t tl_s1n_50_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_50_ds_h2d [2];
+ tl_d2h_t tl_s1n_50_ds_d2h [2];
+
+ // Create steering signal
+ logic [1:0] dev_sel_s1n_50;
+
+
+
+ assign tl_sm1_23_us_h2d[0] = tl_s1n_22_ds_h2d[0];
+ assign tl_s1n_22_ds_d2h[0] = tl_sm1_23_us_d2h[0];
+
+ assign tl_smc_ctrl_o = tl_s1n_22_ds_h2d[1];
+ assign tl_s1n_22_ds_d2h[1] = tl_smc_ctrl_i;
+
+ assign tl_sm1_25_us_h2d[0] = tl_s1n_22_ds_h2d[2];
+ assign tl_s1n_22_ds_d2h[2] = tl_sm1_25_us_d2h[0];
+
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_22_ds_h2d[3];
+ assign tl_s1n_22_ds_d2h[3] = tl_sm1_27_us_d2h[0];
+
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_22_ds_h2d[4];
+ assign tl_s1n_22_ds_d2h[4] = tl_sm1_29_us_d2h[0];
+
+ assign tl_sm1_31_us_h2d[0] = tl_s1n_22_ds_h2d[5];
+ assign tl_s1n_22_ds_d2h[5] = tl_sm1_31_us_d2h[0];
+
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_22_ds_h2d[6];
+ assign tl_s1n_22_ds_d2h[6] = tl_sm1_33_us_d2h[0];
+
+ assign tl_sm1_35_us_h2d[0] = tl_s1n_22_ds_h2d[7];
+ assign tl_s1n_22_ds_d2h[7] = tl_sm1_35_us_d2h[0];
+
+ assign tl_sm1_36_us_h2d[0] = tl_s1n_22_ds_h2d[8];
+ assign tl_s1n_22_ds_d2h[8] = tl_sm1_36_us_d2h[0];
+
+ assign tl_sm1_37_us_h2d[0] = tl_s1n_22_ds_h2d[9];
+ assign tl_s1n_22_ds_d2h[9] = tl_sm1_37_us_d2h[0];
+
+ assign tl_sm1_39_us_h2d[0] = tl_s1n_22_ds_h2d[10];
+ assign tl_s1n_22_ds_d2h[10] = tl_sm1_39_us_d2h[0];
+
+ assign tl_sm1_41_us_h2d[0] = tl_s1n_22_ds_h2d[11];
+ assign tl_s1n_22_ds_d2h[11] = tl_sm1_41_us_d2h[0];
+
+ assign tl_sm1_43_us_h2d[0] = tl_s1n_22_ds_h2d[12];
+ assign tl_s1n_22_ds_d2h[12] = tl_sm1_43_us_d2h[0];
+
+ assign tl_sm1_23_us_h2d[1] = tl_s1n_44_ds_h2d[0];
+ assign tl_s1n_44_ds_d2h[0] = tl_sm1_23_us_d2h[1];
+
+ assign tl_sm1_46_us_h2d[0] = tl_s1n_44_ds_h2d[1];
+ assign tl_s1n_44_ds_d2h[1] = tl_sm1_46_us_d2h[0];
+
+ assign tl_sm1_23_us_h2d[2] = tl_s1n_47_ds_h2d[0];
+ assign tl_s1n_47_ds_d2h[0] = tl_sm1_23_us_d2h[2];
+
+ assign tl_rv_core_ibex_smc__cfg_o = tl_s1n_47_ds_h2d[1];
+ assign tl_s1n_47_ds_d2h[1] = tl_rv_core_ibex_smc__cfg_i;
+
+ assign tl_sm1_25_us_h2d[1] = tl_s1n_47_ds_h2d[2];
+ assign tl_s1n_47_ds_d2h[2] = tl_sm1_25_us_d2h[1];
+
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_47_ds_h2d[3];
+ assign tl_s1n_47_ds_d2h[3] = tl_sm1_27_us_d2h[1];
+
+ assign tl_rv_plic_smc_o = tl_s1n_47_ds_h2d[4];
+ assign tl_s1n_47_ds_d2h[4] = tl_rv_plic_smc_i;
+
+ assign tl_asf_48_us_h2d = tl_s1n_47_ds_h2d[5];
+ assign tl_s1n_47_ds_d2h[5] = tl_asf_48_us_d2h;
+
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_47_ds_h2d[6];
+ assign tl_s1n_47_ds_d2h[6] = tl_sm1_29_us_d2h[1];
+
+ assign tl_sm1_31_us_h2d[1] = tl_s1n_47_ds_h2d[7];
+ assign tl_s1n_47_ds_d2h[7] = tl_sm1_31_us_d2h[1];
+
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_47_ds_h2d[8];
+ assign tl_s1n_47_ds_d2h[8] = tl_sm1_33_us_d2h[1];
+
+ assign tl_sm1_35_us_h2d[1] = tl_s1n_47_ds_h2d[9];
+ assign tl_s1n_47_ds_d2h[9] = tl_sm1_35_us_d2h[1];
+
+ assign tl_sm1_36_us_h2d[1] = tl_s1n_47_ds_h2d[10];
+ assign tl_s1n_47_ds_d2h[10] = tl_sm1_36_us_d2h[1];
+
+ assign tl_sm1_37_us_h2d[1] = tl_s1n_47_ds_h2d[11];
+ assign tl_s1n_47_ds_d2h[11] = tl_sm1_37_us_d2h[1];
+
+ assign tl_sm1_39_us_h2d[1] = tl_s1n_47_ds_h2d[12];
+ assign tl_s1n_47_ds_d2h[12] = tl_sm1_39_us_d2h[1];
+
+ assign tl_sm1_46_us_h2d[1] = tl_s1n_47_ds_h2d[13];
+ assign tl_s1n_47_ds_d2h[13] = tl_sm1_46_us_d2h[1];
+
+ assign tl_sm1_41_us_h2d[1] = tl_s1n_47_ds_h2d[14];
+ assign tl_s1n_47_ds_d2h[14] = tl_sm1_41_us_d2h[1];
+
+ assign tl_sm1_43_us_h2d[1] = tl_s1n_47_ds_h2d[15];
+ assign tl_s1n_47_ds_d2h[15] = tl_sm1_43_us_d2h[1];
+
+ assign tl_sm1_23_us_h2d[3] = tl_s1n_49_ds_h2d[0];
+ assign tl_s1n_49_ds_d2h[0] = tl_sm1_23_us_d2h[3];
+
+ assign tl_sm1_33_us_h2d[2] = tl_s1n_49_ds_h2d[1];
+ assign tl_s1n_49_ds_d2h[1] = tl_sm1_33_us_d2h[2];
+
+ assign tl_sm1_23_us_h2d[4] = tl_s1n_50_ds_h2d[0];
+ assign tl_s1n_50_ds_d2h[0] = tl_sm1_23_us_d2h[4];
+
+ assign tl_sm1_33_us_h2d[3] = tl_s1n_50_ds_h2d[1];
+ assign tl_s1n_50_ds_d2h[1] = tl_sm1_33_us_d2h[3];
+
+ assign tl_s1n_22_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_22_us_d2h;
+
+ assign tl_ram_smc_o = tl_sm1_23_ds_h2d;
+ assign tl_sm1_23_ds_d2h = tl_ram_smc_i;
+
+ assign tl_smc_uart_o = tl_asf_24_ds_h2d;
+ assign tl_asf_24_ds_d2h = tl_smc_uart_i;
+
+ assign tl_asf_24_us_h2d = tl_sm1_25_ds_h2d;
+ assign tl_sm1_25_ds_d2h = tl_asf_24_us_d2h;
+
+ assign tl_rv_timer_smc_o = tl_asf_26_ds_h2d;
+ assign tl_asf_26_ds_d2h = tl_rv_timer_smc_i;
+
+ assign tl_asf_26_us_h2d = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_asf_26_us_d2h;
+
+ assign tl_cam_i2c_o = tl_asf_28_ds_h2d;
+ assign tl_asf_28_ds_d2h = tl_cam_i2c_i;
+
+ assign tl_asf_28_us_h2d = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_asf_28_us_d2h;
+
+ assign tl_cam_ctrl_o = tl_asf_30_ds_h2d;
+ assign tl_asf_30_ds_d2h = tl_cam_ctrl_i;
+
+ assign tl_asf_30_us_h2d = tl_sm1_31_ds_h2d;
+ assign tl_sm1_31_ds_d2h = tl_asf_30_us_d2h;
+
+ assign tl_ml_top__dmem_o = tl_asf_32_ds_h2d;
+ assign tl_asf_32_ds_d2h = tl_ml_top__dmem_i;
+
+ assign tl_asf_32_us_h2d = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_asf_32_us_d2h;
+
+ assign tl_ml_top__core_o = tl_asf_34_ds_h2d;
+ assign tl_asf_34_ds_d2h = tl_ml_top__core_i;
+
+ assign tl_asf_34_us_h2d = tl_sm1_35_ds_h2d;
+ assign tl_sm1_35_ds_d2h = tl_asf_34_us_d2h;
+
+ assign tl_isp_wrapper_o = tl_sm1_36_ds_h2d;
+ assign tl_sm1_36_ds_d2h = tl_isp_wrapper_i;
+
+ assign tl_dma_smc_o = tl_sm1_37_ds_h2d;
+ assign tl_sm1_37_ds_d2h = tl_dma_smc_i;
+
+ assign tl_spi_host2_o = tl_asf_38_ds_h2d;
+ assign tl_asf_38_ds_d2h = tl_spi_host2_i;
+
+ assign tl_asf_38_us_h2d = tl_sm1_39_ds_h2d;
+ assign tl_sm1_39_ds_d2h = tl_asf_38_us_d2h;
+
+ assign tl_rv_timer_smc2_o = tl_asf_40_ds_h2d;
+ assign tl_asf_40_ds_d2h = tl_rv_timer_smc2_i;
+
+ assign tl_asf_40_us_h2d = tl_sm1_41_ds_h2d;
+ assign tl_sm1_41_ds_d2h = tl_asf_40_us_d2h;
+
+ assign tl_i2s0_o = tl_asf_42_ds_h2d;
+ assign tl_asf_42_ds_d2h = tl_i2s0_i;
+
+ assign tl_asf_42_us_h2d = tl_sm1_43_ds_h2d;
+ assign tl_sm1_43_ds_d2h = tl_asf_42_us_d2h;
+
+ assign tl_s1n_44_us_h2d = tl_rv_core_ibex_smc__corei_i;
+ assign tl_rv_core_ibex_smc__corei_o = tl_s1n_44_us_d2h;
+
+ assign tl_dbg_o = tl_asf_45_ds_h2d;
+ assign tl_asf_45_ds_d2h = tl_dbg_i;
+
+ assign tl_asf_45_us_h2d = tl_sm1_46_ds_h2d;
+ assign tl_sm1_46_ds_d2h = tl_asf_45_us_d2h;
+
+ assign tl_s1n_47_us_h2d = tl_rv_core_ibex_smc__cored_i;
+ assign tl_rv_core_ibex_smc__cored_o = tl_s1n_47_us_d2h;
+
+ assign tl_tlul_mailbox_smc_o = tl_asf_48_ds_h2d;
+ assign tl_asf_48_ds_d2h = tl_tlul_mailbox_smc_i;
+
+ assign tl_s1n_49_us_h2d = tl_dma_smc__reader_i;
+ assign tl_dma_smc__reader_o = tl_s1n_49_us_d2h;
+
+ assign tl_s1n_50_us_h2d = tl_dma_smc__writer_i;
+ assign tl_dma_smc__writer_o = tl_s1n_50_us_d2h;
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_22 = 4'd13;
+ if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_RAM_SMC)) == ADDR_SPACE_RAM_SMC) begin
+ dev_sel_s1n_22 = 4'd0;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_SMC_CTRL)) == ADDR_SPACE_SMC_CTRL) begin
+ dev_sel_s1n_22 = 4'd1;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_SMC_UART)) == ADDR_SPACE_SMC_UART) begin
+ dev_sel_s1n_22 = 4'd2;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_RV_TIMER_SMC)) == ADDR_SPACE_RV_TIMER_SMC) begin
+ dev_sel_s1n_22 = 4'd3;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_CAM_I2C)) == ADDR_SPACE_CAM_I2C) begin
+ dev_sel_s1n_22 = 4'd4;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_CAM_CTRL)) == ADDR_SPACE_CAM_CTRL) begin
+ dev_sel_s1n_22 = 4'd5;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__DMEM)) == ADDR_SPACE_ML_TOP__DMEM) begin
+ dev_sel_s1n_22 = 4'd6;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__CORE)) == ADDR_SPACE_ML_TOP__CORE) begin
+ dev_sel_s1n_22 = 4'd7;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_ISP_WRAPPER)) == ADDR_SPACE_ISP_WRAPPER) begin
+ dev_sel_s1n_22 = 4'd8;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_DMA_SMC)) == ADDR_SPACE_DMA_SMC) begin
+ dev_sel_s1n_22 = 4'd9;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST2)) == ADDR_SPACE_SPI_HOST2) begin
+ dev_sel_s1n_22 = 4'd10;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_RV_TIMER_SMC2)) == ADDR_SPACE_RV_TIMER_SMC2) begin
+ dev_sel_s1n_22 = 4'd11;
+
+ end else if ((tl_s1n_22_us_h2d.a_address &
+ ~(ADDR_MASK_I2S0)) == ADDR_SPACE_I2S0) begin
+ dev_sel_s1n_22 = 4'd12;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_44 = 2'd2;
+ if ((tl_s1n_44_us_h2d.a_address &
+ ~(ADDR_MASK_RAM_SMC)) == ADDR_SPACE_RAM_SMC) begin
+ dev_sel_s1n_44 = 2'd0;
+
+ end else if ((tl_s1n_44_us_h2d.a_address &
+ ~(ADDR_MASK_DBG)) == ADDR_SPACE_DBG) begin
+ dev_sel_s1n_44 = 2'd1;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_47 = 5'd16;
+ if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_RAM_SMC)) == ADDR_SPACE_RAM_SMC) begin
+ dev_sel_s1n_47 = 5'd0;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_RV_CORE_IBEX_SMC__CFG)) == ADDR_SPACE_RV_CORE_IBEX_SMC__CFG) begin
+ dev_sel_s1n_47 = 5'd1;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_SMC_UART)) == ADDR_SPACE_SMC_UART) begin
+ dev_sel_s1n_47 = 5'd2;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_RV_TIMER_SMC)) == ADDR_SPACE_RV_TIMER_SMC) begin
+ dev_sel_s1n_47 = 5'd3;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_RV_PLIC_SMC)) == ADDR_SPACE_RV_PLIC_SMC) begin
+ dev_sel_s1n_47 = 5'd4;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_TLUL_MAILBOX_SMC)) == ADDR_SPACE_TLUL_MAILBOX_SMC) begin
+ dev_sel_s1n_47 = 5'd5;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_CAM_I2C)) == ADDR_SPACE_CAM_I2C) begin
+ dev_sel_s1n_47 = 5'd6;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_CAM_CTRL)) == ADDR_SPACE_CAM_CTRL) begin
+ dev_sel_s1n_47 = 5'd7;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__DMEM)) == ADDR_SPACE_ML_TOP__DMEM) begin
+ dev_sel_s1n_47 = 5'd8;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__CORE)) == ADDR_SPACE_ML_TOP__CORE) begin
+ dev_sel_s1n_47 = 5'd9;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_ISP_WRAPPER)) == ADDR_SPACE_ISP_WRAPPER) begin
+ dev_sel_s1n_47 = 5'd10;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_DMA_SMC)) == ADDR_SPACE_DMA_SMC) begin
+ dev_sel_s1n_47 = 5'd11;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_SPI_HOST2)) == ADDR_SPACE_SPI_HOST2) begin
+ dev_sel_s1n_47 = 5'd12;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_DBG)) == ADDR_SPACE_DBG) begin
+ dev_sel_s1n_47 = 5'd13;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_RV_TIMER_SMC2)) == ADDR_SPACE_RV_TIMER_SMC2) begin
+ dev_sel_s1n_47 = 5'd14;
+
+ end else if ((tl_s1n_47_us_h2d.a_address &
+ ~(ADDR_MASK_I2S0)) == ADDR_SPACE_I2S0) begin
+ dev_sel_s1n_47 = 5'd15;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_49 = 2'd2;
+ if ((tl_s1n_49_us_h2d.a_address &
+ ~(ADDR_MASK_RAM_SMC)) == ADDR_SPACE_RAM_SMC) begin
+ dev_sel_s1n_49 = 2'd0;
+
+ end else if ((tl_s1n_49_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__DMEM)) == ADDR_SPACE_ML_TOP__DMEM) begin
+ dev_sel_s1n_49 = 2'd1;
+end
+ end
+
+ always_comb begin
+ // default steering to generate error response if address is not within the range
+ dev_sel_s1n_50 = 2'd2;
+ if ((tl_s1n_50_us_h2d.a_address &
+ ~(ADDR_MASK_RAM_SMC)) == ADDR_SPACE_RAM_SMC) begin
+ dev_sel_s1n_50 = 2'd0;
+
+ end else if ((tl_s1n_50_us_h2d.a_address &
+ ~(ADDR_MASK_ML_TOP__DMEM)) == ADDR_SPACE_ML_TOP__DMEM) begin
+ dev_sel_s1n_50 = 2'd1;
+end
+ end
+
+
+ // Instantiation phase
+ tlul_socket_1n #(
+ .DReqPass (13'h1ffd),
+ .DRspPass (13'h1ffd),
+ .DReqDepth (52'h10),
+ .DRspDepth (52'h10),
+ .N (13)
+ ) u_s1n_22 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_s1n_22_us_h2d),
+ .tl_h_o (tl_s1n_22_us_d2h),
+ .tl_d_o (tl_s1n_22_ds_h2d),
+ .tl_d_i (tl_s1n_22_ds_d2h),
+ .dev_select_i (dev_sel_s1n_22)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (20'h0),
+ .HRspDepth (20'h0),
+ .DRspPass (1'b0),
+ .M (5)
+ ) u_sm1_23 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_23_us_h2d),
+ .tl_h_o (tl_sm1_23_us_d2h),
+ .tl_d_o (tl_sm1_23_ds_h2d),
+ .tl_d_i (tl_sm1_23_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_24 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_24_us_h2d),
+ .tl_h_o (tl_asf_24_us_d2h),
+ .tl_d_o (tl_asf_24_ds_h2d),
+ .tl_d_i (tl_asf_24_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_25 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_25_us_h2d),
+ .tl_h_o (tl_sm1_25_us_d2h),
+ .tl_d_o (tl_sm1_25_ds_h2d),
+ .tl_d_i (tl_sm1_25_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_26 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_26_us_h2d),
+ .tl_h_o (tl_asf_26_us_d2h),
+ .tl_d_o (tl_asf_26_ds_h2d),
+ .tl_d_i (tl_asf_26_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_27 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_27_us_h2d),
+ .tl_h_o (tl_sm1_27_us_d2h),
+ .tl_d_o (tl_sm1_27_ds_h2d),
+ .tl_d_i (tl_sm1_27_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_28 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_28_us_h2d),
+ .tl_h_o (tl_asf_28_us_d2h),
+ .tl_d_o (tl_asf_28_ds_h2d),
+ .tl_d_i (tl_asf_28_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_29 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_29_us_h2d),
+ .tl_h_o (tl_sm1_29_us_d2h),
+ .tl_d_o (tl_sm1_29_ds_h2d),
+ .tl_d_i (tl_sm1_29_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_30 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_30_us_h2d),
+ .tl_h_o (tl_asf_30_us_d2h),
+ .tl_d_o (tl_asf_30_ds_h2d),
+ .tl_d_i (tl_asf_30_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_31 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_31_us_h2d),
+ .tl_h_o (tl_sm1_31_us_d2h),
+ .tl_d_o (tl_sm1_31_ds_h2d),
+ .tl_d_i (tl_sm1_31_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_32 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_ml_i),
+ .rst_d_ni (rst_ml_ni),
+ .tl_h_i (tl_asf_32_us_h2d),
+ .tl_h_o (tl_asf_32_us_d2h),
+ .tl_d_o (tl_asf_32_ds_h2d),
+ .tl_d_i (tl_asf_32_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (16'h0),
+ .HRspDepth (16'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (4)
+ ) u_sm1_33 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_33_us_h2d),
+ .tl_h_o (tl_sm1_33_us_d2h),
+ .tl_d_o (tl_sm1_33_ds_h2d),
+ .tl_d_i (tl_sm1_33_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_34 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_ml_i),
+ .rst_d_ni (rst_ml_ni),
+ .tl_h_i (tl_asf_34_us_h2d),
+ .tl_h_o (tl_asf_34_us_d2h),
+ .tl_d_o (tl_asf_34_ds_h2d),
+ .tl_d_i (tl_asf_34_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_35 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_35_us_h2d),
+ .tl_h_o (tl_sm1_35_us_d2h),
+ .tl_d_o (tl_sm1_35_ds_h2d),
+ .tl_d_i (tl_sm1_35_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_36 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_36_us_h2d),
+ .tl_h_o (tl_sm1_36_us_d2h),
+ .tl_d_o (tl_sm1_36_ds_h2d),
+ .tl_d_i (tl_sm1_36_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_37 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_37_us_h2d),
+ .tl_h_o (tl_sm1_37_us_d2h),
+ .tl_d_o (tl_sm1_37_ds_h2d),
+ .tl_d_i (tl_sm1_37_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_38 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_spi_host2_i),
+ .rst_d_ni (rst_spi_host2_ni),
+ .tl_h_i (tl_asf_38_us_h2d),
+ .tl_h_o (tl_asf_38_us_d2h),
+ .tl_d_o (tl_asf_38_ds_h2d),
+ .tl_d_i (tl_asf_38_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_39 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_39_us_h2d),
+ .tl_h_o (tl_sm1_39_us_d2h),
+ .tl_d_o (tl_sm1_39_ds_h2d),
+ .tl_d_i (tl_sm1_39_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_40 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_40_us_h2d),
+ .tl_h_o (tl_asf_40_us_d2h),
+ .tl_d_o (tl_asf_40_ds_h2d),
+ .tl_d_i (tl_asf_40_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_41 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_41_us_h2d),
+ .tl_h_o (tl_sm1_41_us_d2h),
+ .tl_d_o (tl_sm1_41_ds_h2d),
+ .tl_d_i (tl_sm1_41_ds_d2h)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_42 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_peri_i),
+ .rst_d_ni (rst_peri_ni),
+ .tl_h_i (tl_asf_42_us_h2d),
+ .tl_h_o (tl_asf_42_us_d2h),
+ .tl_d_o (tl_asf_42_ds_h2d),
+ .tl_d_i (tl_asf_42_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_43 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_43_us_h2d),
+ .tl_h_o (tl_sm1_43_us_d2h),
+ .tl_d_o (tl_sm1_43_ds_h2d),
+ .tl_d_i (tl_sm1_43_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .DReqDepth (8'h0),
+ .DRspDepth (8'h0),
+ .N (2)
+ ) u_s1n_44 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_s1n_44_us_h2d),
+ .tl_h_o (tl_s1n_44_us_d2h),
+ .tl_d_o (tl_s1n_44_ds_h2d),
+ .tl_d_i (tl_s1n_44_ds_d2h),
+ .dev_select_i (dev_sel_s1n_44)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_45 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_main_i),
+ .rst_d_ni (rst_main_ni),
+ .tl_h_i (tl_asf_45_us_h2d),
+ .tl_h_o (tl_asf_45_us_d2h),
+ .tl_d_o (tl_asf_45_ds_h2d),
+ .tl_d_i (tl_asf_45_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (2)
+ ) u_sm1_46 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_sm1_46_us_h2d),
+ .tl_h_o (tl_sm1_46_us_d2h),
+ .tl_d_o (tl_sm1_46_ds_h2d),
+ .tl_d_i (tl_sm1_46_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .DRspPass (16'hffed),
+ .DReqDepth (64'h10010),
+ .DRspDepth (64'h10010),
+ .N (16)
+ ) u_s1n_47 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_s1n_47_us_h2d),
+ .tl_h_o (tl_s1n_47_us_d2h),
+ .tl_d_o (tl_s1n_47_ds_h2d),
+ .tl_d_i (tl_s1n_47_ds_d2h),
+ .dev_select_i (dev_sel_s1n_47)
+ );
+ tlul_fifo_async #(
+ .ReqDepth (1),
+ .RspDepth (1)
+ ) u_asf_48 (
+ .clk_h_i (clk_smc_i),
+ .rst_h_ni (rst_smc_ni),
+ .clk_d_i (clk_main_i),
+ .rst_d_ni (rst_main_ni),
+ .tl_h_i (tl_asf_48_us_h2d),
+ .tl_h_o (tl_asf_48_us_d2h),
+ .tl_d_o (tl_asf_48_ds_h2d),
+ .tl_d_i (tl_asf_48_ds_d2h)
+ );
+ tlul_socket_1n #(
+ .DReqDepth (8'h0),
+ .DRspDepth (8'h0),
+ .N (2)
+ ) u_s1n_49 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_s1n_49_us_h2d),
+ .tl_h_o (tl_s1n_49_us_d2h),
+ .tl_d_o (tl_s1n_49_ds_h2d),
+ .tl_d_i (tl_s1n_49_ds_d2h),
+ .dev_select_i (dev_sel_s1n_49)
+ );
+ tlul_socket_1n #(
+ .DReqDepth (8'h0),
+ .DRspDepth (8'h0),
+ .N (2)
+ ) u_s1n_50 (
+ .clk_i (clk_smc_i),
+ .rst_ni (rst_smc_ni),
+ .tl_h_i (tl_s1n_50_us_h2d),
+ .tl_h_o (tl_s1n_50_us_d2h),
+ .tl_d_o (tl_s1n_50_ds_h2d),
+ .tl_d_i (tl_s1n_50_ds_d2h),
+ .dev_select_i (dev_sel_s1n_50)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/alert_handler/README.md b/hw/top_sencha/ip_autogen/alert_handler/README.md
new file mode 100644
index 0000000..574804e
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/README.md
@@ -0,0 +1,978 @@
+# Alert Handler Technical Specification
+
+
+# Overview
+
+This document specifies the functionality of the alert handler mechanism.
+The alert handler is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../doc/contributing/hw/comportability/README.md).
+It gathers alerts - defined as interrupt-type signals from other peripherals that are designated as potential security threats - throughout the design, and converts them to interrupts that the processor can handle.
+If the processor does not handle them, the alert handler mechanism provides hardware responses to handle the threat.
+
+
+## Features
+
+- Differentially-signaled, asynchronous alert inputs from `NAlerts` peripheral sources, where `NAlerts` is a function of the requirements of the peripherals.
+
+- Ping testing of alert sources:
+ - responder module requests periodic alert response from each source to ensure proper wiring.
+ - reset-asserted and clock-gated information is used to temporarily pause the ping mechanism on alert channels that are in a low-power state.
+
+- Register locking on all configuration registers.
+ - Once locked, can not be modified by software until next system reset.
+
+- Register-based assignment of alert to alert-class.
+ - Four classes, can be individually disabled.
+ - Each class generates one interrupt.
+ - Disambiguation history for software to determine which alert caused the class interrupt.
+ - Each class has configurable response time for escalation.
+ - Disable allows for ignoring alerts, should only be used in cases when alerts are faulty.
+ Undesirable access is enforced by locking the register state after initial configuration.
+
+- Register-based escalation controls.
+ - Number of alerts in class before escalation.
+ - Timeout for unhandled alert IRQs can also trigger escalation.
+ - Configurable escalation enables for 4 escalation signals.
+ - Could map to NMI, wipe secrets signal, lower privilege, chip reset, etc.
+ - Escalation signals differentially-signaled with heartbeat, will trigger response if differential or heartbeat failure at destination.
+ - Configurable time in cycles between each escalation level.
+
+- Two locally sourced hardware alerts.
+ - Differential signaling from a source has failed.
+ - Ping response from a source has failed.
+
+
+## Description
+
+The alert handler module manages incoming alerts from throughout the system, classifies them, sends interrupts, and escalates interrupts to hardware responses if the processor does not respond to any interrupts.
+The intention is for this module to be a stand-in for security responses in the case where the processor can not handle the security alerts.
+
+It is first notable that all security alerts are rare events.
+Module and top level designers should only designate events as alerts if they are expected to never happen, and if they have potential security consequences.
+Examples are parity errors (which might indicate an attack), illegal actions on cryptography or security modules, physical sensors of environmental modification (e.g. voltage, temperature), etc.
+Alerts will be routed through this module and initially converted to interrupts for the processor to handle.
+The expectation is that the secure operating system has a protocol for handling any such alert interrupt in software.
+The operating system should respond, then clear the interrupt.
+Since these are possible security attacks, the response is not always obvious, but the response is beyond the scope of this document.
+
+This module is designed to help the full chip respond to security threats in the case where the processor is not trusted: either it has been attacked, or is not responding.
+It does this by escalating alerts beyond a processor interrupt.
+It provides four such escalation signals that can be routed to chip functions for attack responses.
+This could include such functions as wiping secret chip material, power down, reset, etc.
+It is beyond the scope of this document to specify what those escalation responses are at the chip level.
+
+To ease software management of alerts, classification is provided whereby each alert can be classified into one of four classes.
+How the classification is done by software is beyond the scope of this document, but it is suggested that alerts of a similar profile (risk of occurring, level of security concern, frequency of false trigger, etc) are classed together.
+For each class a counter of alerts is kept, clearable by software.
+If that counter exceeds a programmable maximum value, then the escalation protocol for that class begins.
+
+The details for alert signaling, classification, and escalation are all given in the Theory of Operations section.
+
+
+# Theory of Operations
+
+## Block Diagram
+
+The figure below shows a block diagram of the alert handler module, as well as a few examples of alert senders in other peripheral modules.
+In this diagram, there are seven sources of alerts: three sources from external modules (two from `periph0` and one from `periph1`), and four local sources (`alert_ping_fail`, `alert_sig_int`, `esc_ping_fail`, `esc_sig_int`).
+The local sources represent alerts that are created by this module itself. See the later section on special local alerts.
+
+
+
+Also shown are internal modules for classification, interrupt generation, accumulation, escalation, ping generation and alert-channel low-power control.
+These are described later in the document.
+Note that the differential alert sender and receiver blocks used for alert signaling support both _asynchronous_ and _synchronous_ clocking schemes, and hence peripherals able to raise alerts may be placed in clock domains different from that of the alert handler (Jittered clock domains are also supported in the asynchronous clocking scheme).
+Proper care must however be taken when formulating the timing constraints for the diff pairs, and when determining clock-dependent parameters (such as the ping timeout) of the design.
+On the escalation sender / receiver side, the differential signaling blocks employ a fully synchronous clocking scheme throughout.
+
+## Hardware Interfaces
+
+### Parameters
+
+The following table lists the main parameters used throughout the alert handler design.
+Note that the alert handler is generated based on the system configuration, and hence these parameters are placed into a package as "localparams".
+The parameterization rules are explained in more detail in the architectural description.
+
+Localparam | Default (Max) | Top Earlgrey | Description
+---------------|-----------------------|--------------|---------------
+`NAlerts` | 8 (248) | see RTL | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing.
+`NLpg` | 1 | see RTL | Number of unique low-power groups as determined by topgen.
+`LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen.
+`EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit.
+`AccuCntWidth` | 16 (32) | 16 | Width of the alert accumulation counters in bit.
+`AsyncOn` | '0 (2^`NAlerts`-1) | see RTL | This is a bit array specifying whether a certain alert sender / receiver pair goes across an asynchronous boundary or not.
+
+The next table lists free parameters in the `prim_alert_sender` and
+`prim_alert receiver` submodules.
+
+Parameter | Default (Max) | Description
+---------------|------------------|---------------
+`AsyncOn` | `1'b0` (`1'b1`) | 0: Synchronous, 1: Asynchronous, determines whether additional synchronizer flops and logic need to be instantiated.
+
+
+### Signals
+
+* [Interface Tables](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#interfaces)
+
+The table below lists other alert handler module signals.
+The number of alert instances is parametric and hence alert and ping diff pairs are grouped together in packed arrays.
+The diff pair signals are indexed with the corresponding alert instance `<number>`.
+
+Signal | Direction | Type | Description
+-------------------------|------------------|---------------- |---------------
+`edn_o` | `output` | `otp_edn_req_t` | Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation.
+`edn_i` | `input` | `otp_edn_rsp_t` | Entropy acknowledgment to the entropy distribution network for LFSR reseeding and ephemeral key derivation.
+`alert_tx_i[<number>]` | `input` | packed `alert_tx_t` array | Incoming alert or ping response(s), differentially encoded. Index range: `[NAlerts-1:0]`
+`alert_rx_o[<number>]` | `output` | packed `alert_rx_t` array | Outgoing alert acknowledgment and ping requests, differentially encoded. Index range: `[NAlerts-1:0]`
+`esc_tx_o[<sev>]` | `output` | packed `esc_tx_t` array | Escalation or ping request, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3.
+`esc_rx_i[<sev>]` | `input` | packed `esc_rx_t` array | Escalation ping response, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3.
+`lpg_cg_en_i[<lpg>]` | `input` | packed `mubi4_t` array | Incoming clock gated indication from clock manager. Index range: `[NLpg-1:0]`
+`lpg_rst_en_i[<lpg>]` | `input` | packed `mubi4_t` array | Incoming reset asserted indication from reset manager. Index range: `[NLpg-1:0]`
+`crashdump_o` | `output` | packed `struct` | This is a collection of alert handler state registers that can be latched by hardware debugging circuitry, if needed.
+
+#### Entropy Network Connections
+
+The LFSR ping timer needs to be periodically reseeded.
+Therefore, the alert handler is connected to the entropy distribution network via the `edn_i/o` signals.
+
+#### Alert Channels
+
+For each alert, there is a pair of input and two pairs of output signals.
+These signals are connected to a differential sender module within the source, and a differential receiver module within the alert handler.
+Both of these modules are described in more detail in the following section.
+These signal pairs carry differentially encoded messages that enable two types of signaling: a native alert and a ping/response test of the alert mechanism.
+The latter is to ensure that all alert senders are always active and have not been the target of an attack.
+
+#### Escalation Channels
+
+For each escalation action in the system, there is a pair of input and a pair of output signals, encapsulated in the `esc_rx_t` and `esc_tx_t` types.
+These signals are connected to a differential sender module within the alert handler, and a differential receiver module within the module that performs a particular escalation action (for example the reset manager or life cycle controllers).
+The signal pairs carry differentially encoded messages that enable two types of signaling: a native escalation and a ping/response test of the escalation mechanism.
+The latter is to ensure that all escalation receivers are always active and have not been the target of an attack.
+
+#### Low-power Indication Signals
+
+The `lpg_cg_en_i` and `lpg_rst_en_i` are two arrays with multibit indication signals from the [clock](../../ip/clkmgr/README.md) and [reset managers](../../ip/rstmgr/README.md).
+These indication signals convey whether a specific group of alert senders are either clock gated or in reset.
+As explained in [more detail below](#low-power-management-of-alert-channels), this information is used to temporarily halt the ping timer mechanism on channels that are in a low-power state in order to prevent false positives.
+
+#### Crashdump Output
+
+The `crashdump_o` struct outputs a snapshot of CSRs and alert handler state bits that can be read by hardware debugging circuitry:
+
+```systemverilog
+ typedef struct packed {
+ // alerts
+ logic [NAlerts-1:0] alert_cause; // alert cause bits
+ logic [6:0] loc_alert_cause; // local alert cause bits
+ // class state
+ logic [3:0][15:0] class_accum_cnt; // current accumulator value
+ logic [3:0][31:0] class_esc_cnt; // current escalation counter value
+ cstate_e [3:0] class_esc_state; // current escalation protocol state
+ } alert_crashdump_t;
+```
+
+This can be useful for extracting more information about possible failures or bugs without having to use the tile-link bus interface (which may become unresponsive under certain circumstances).
+It is recommended for the top level to store this information in an always-on location.
+
+Note that the crashdump state is continuously output via `crashdump_o` until the latching trigger condition is true for the first time (see [`CLASSA_CRASHDUMP_TRIGGER_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_crashdump_trigger_shadowed)).
+After that, the `crashdump_o` is held constant until all classes that have escalated are cleared.
+This is done so that it is possible to capture the true alert cause before spurious alert events start to pop up due to escalation countermeasures with excessive side effects (like life cycle scrapping for example).
+If classes that have escalated are not configured as clearable, then it is not possible to re-arm the crashdump latching mechanism at runtime and the alert handler has to be reset.
+
+## Design Details
+
+This section gives the full design details of the alert handler module and its submodules.
+
+
+### Alert Definition
+
+Alerts are defined as events that have security implications, and should be handled by the main processor, or escalated to other hardware modules to take action.
+Each peripheral has the option to define one or more alert signals.
+Those peripherals should instantiate one module (`prim_alert_sender`) to convert the event associated with that alert into a signal to the alert handler module.
+The alert handler instantiates one receiver module (`prim_alert_receiver`) per alert, then handles the classification, accumulation, and escalation of the received signal.
+The differential signaling submodules may either use a synchronous or asynchronous clocking scheme, since the message type to be transferred is a single discrete event.
+
+
+### Differential Alert Signaling
+
+Each alert sender is connected to the corresponding alert receiver via the 3 differential pairs `alert_tx_i/o.alert_p/n`, `alert_rx_i/o.ack_p/n` and `alert_rx_i/o.ping_p/n`, as illustrated below:
+
+
+
+Alerts are encoded differentially and signaled using a full handshake on the `alert_tx_i/o.alert_p/n` and `alert_rx_i/o.ack_p/n` wires.
+The use of a full handshake protocol allows this mechanism to be used with an asynchronous clocking strategy, where peripherals may reside in a different clock domain than the alert handler.
+The full handshake guarantees that alert messages are correctly back-pressured and no alert is "lost" at the asynchronous boundary due to (possibly variable) clock ratios greater or less than 1.0.
+The "native alert message" will be repeated on the output wires as long as the alert event is still true within the peripheral.
+
+The wave pattern below illustrates differential full handshake mechanism.
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p...............' },
+ { name: 'alert_req_i', wave: '01.|..|..|...|..' },
+ { name: 'alert_ack_o', wave: '0..|..|..|10.|..' },
+ { name: 'alert_tx_o/i.alert_p', wave: '01.|..|0.|..1|..' , node: '.a.....c....e'},
+ { name: 'alert_tx_o/i.alert_n', wave: '10.|..|1.|..0|..' },
+ { name: 'alert_rx_i/o.ack_p', wave: '0..|1.|..|0..|1.' , node: '....b.....d..'},
+ { name: 'alert_rx_i/o.ack_n', wave: '1..|0.|..|1..|0.' },
+ { name: 'alert_o', wave: '0..|10|..|...|10' },
+ ],
+ edge: [
+ 'a~>b Phase 0/1',
+ 'b~>c Phase 1/2',
+ 'c~>d Phase 2/3',
+ 'd~>e 2 Pause Cycles',
+ ],
+ head: {
+ text: 'Alert signaling and repeat pattern',
+ },
+ foot: {
+ text: 'Native alert at time 1 with 4-phase handshake; repeated alert at time 12;',
+ tick: 0,
+ }
+}
+```
+
+The handshake pattern is repeated as long as the alert is true.
+The sender will wait for 2 cycles between handshakes.
+
+Note that the alert is immediately propagated to `alert_o` once the initial level change on `alert_tx_i.alert_p/n` has been received and synchronized to the local clock on the receiver side.
+This ensures that the first occurrence of an alert is always propagated - even if the handshake lines have been manipulated to emulate backpressure.
+(In such a scenario, all subsequent alerts would be back-pressured and eventually the ping testing mechanism described in the next subsection would detect that the wires have been tampered with.)
+
+The alert sender and receiver modules can either be used synchronously or asynchronously.
+The signaling protocol remains the same in both cases, but the additional synchronizer flops at the diff pair inputs may be omitted, which results in lower signaling latency.
+
+### Ping Testing
+
+In order to ensure that the event sending modules have not been compromised, the alert receiver module `prim_alert_receiver` will "ping" or line-test the senders periodically every few microseconds.
+Pings timing is randomized so their appearance can not be predicted.
+
+
+The ping timing is generated by a central LFSR-based timer within the alert handler that randomly asserts the `ping_req_i` signal of a particular `prim_alert_receiver` module.
+Once `ping_req_i` is asserted, the receiver module encodes the ping message as a level change on the differential `alert_rx_o.ping_p/n` output, and waits until the sender responds with a full handshake on the `alert_tx_i.alert_p/n` and `alert_rx_o.ack_p/n` lines.
+Once that handshake is complete, the `ping_ok_o` signal is asserted.
+The LFSR timer has a programmable ping timeout, after which it will automatically assert a "pingfail" alert.
+That timeout is a function of the clock ratios present in the system, and has to be programmed accordingly at system startup (as explained later in the LFSR timer subsection).
+
+The following wave diagram illustrates a correct ping sequence, viewed from the receiver side:
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p..............' },
+ { name: 'ping_req_i', wave: '01.|..|..|..|.0' },
+ { name: 'ping_ok_o', wave: '0..|..|..|..|10' , node: '.............e'},
+ { name: 'alert_rx_o.ping_p', wave: '01.|..|..|..|..' , node: '.a'},
+ { name: 'alert_rx_o.ping_n', wave: '10.|..|..|..|..' , node: '.b'},
+ { name: 'alert_tx_i.alert_p', wave: '0..|1.|..|0.|..' , node: '....c'},
+ { name: 'alert_tx_i.alert_n', wave: '1..|0.|..|1.|..' },
+ { name: 'alert_rx_o.ack_p', wave: '0..|..|1.|..|0.' , node: '.............d'},
+ { name: 'alert_rx_o.ack_n', wave: '1..|..|0.|..|1.' },
+ ],
+ edge: [
+ 'a-b',
+ 'b~>c ping response',
+ 'd->e response complete',
+ ],
+ head: {
+ text: 'Ping testing',
+ },
+ foot: {
+ text: 'Level change at time 1 triggers a full handshake (ping response) at time 4',
+ tick: 0,
+ }
+}
+```
+
+In the unlikely case that a ping request collides with a native alert at the sender side, the native alert is held back until the ping handshake has been completed.
+This slightly delays the transmission of a native alert, but the alert will eventually be signaled.
+Further, if an alert is sent out right before a ping requests comes in at the sender side, the receiver will treat the alert as a ping response.
+However, the "true" ping response will be returned right after the alert handshake completed, and thus the alert will eventually be signaled with a slight delay.
+
+Note that in both collision cases mentioned, the delay will be in the order of the handshake length, plus the constant amount of pause cycles between handshakes (2 sender cycles).
+
+
+### Monitoring of Signal Integrity Issues
+
+All differential pairs are monitored for signal integrity issues, and if an encoding failure is detected, the receiver module asserts a signal integrity alert via `integ_fail_o`. In particular, this covers the following failure cases:
+
+1. The `alert_tx_i.alert_p/n` pair is not correctly encoded on the receiver side.
+This can be directly flagged as an integrity failure on the receiver side.
+
+2. The `alert_rx_i.ping_p/n` or the `alert_rx_i.ack_p/n` pairs are not correctly encoded on the sender side.
+This is signaled to the receiver by setting the `alert_tx_o.alert_p/n` wires to the same value, and that value will be continuously toggled.
+This implicitly triggers a signal integrity alert on the receiver side.
+
+Some of these failure patterns are illustrated in the wave diagram below:
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p..............' },
+ { name: 'alert_tx_o.alert_p', wave: '0.1...|0..10101' , node: '..a.......d'},
+ { name: 'alert_tx_o.alert_n', wave: '1.....|....0101' },
+ { name: 'alert_rx_i.ack_p', wave: '0.....|.1......' , node: '........c'},
+ { name: 'alert_rx_i.ack_n', wave: '1.....|........' },
+ { name: 'integ_fail_o', wave: '0...1.|0....1..' , node: '....b.......e'},
+ ],
+ edge: [
+ 'a~>b sigint issue detected',
+ 'c~>d',
+ 'd~>e indirect sigint issue detected',
+ ],
+ head: {
+ text: 'Detection of Signal Integrity Issues',
+ },
+ foot: {
+ text: 'signal integrity issues occur at times 2 and 8; synchronizer latency is 2 cycles.',
+ tick: 0,
+ }
+}
+```
+
+Note that if signal integrity failures occur during ping or alert handshaking, it is possible that the protocol state-machines lock up and the alert sender and receiver modules become unresponsive. However, the above mechanisms ensure that this will always trigger either a signal integrity alert or eventually a "pingfail" alert.
+
+### Skew on Asynchronous Differential Pairs
+
+Note that there is likely a (small) skew present within each differential pair of the signaling mechanism above. Since these pairs cross clock domain boundaries, it may thus happen that a level change appears in staggered manner after resynchronization, as illustrated below:
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p...........' },
+ { name: 'diff_p', wave: '0.1.|.0.|..1' , node: '......a....d' },
+ { name: 'diff_n', wave: '1.0.|..1|.0.' , node: '.......b..c.' },
+ ],
+ edge: [
+ 'a-~>b skew',
+ 'c-~>d skew'
+ ],
+ head: {
+ text: 'Skewed diff pair',
+ },
+ foot: {
+ text: 'Correctly sampled diff pair at time 2; staggered samples at time 6-7 and 10-11',
+ tick: 0,
+ }
+}
+```
+
+This behavior is permissible, but needs to be accounted for in the protocol logic.
+Further, the skew within the differential pair should be constrained to be smaller than the shortest clock period in the system.
+This ensures that the staggered level changes appear at most 1 cycle apart from each other.
+
+
+### LFSR Timer
+
+The `ping_req_i` inputs of all signaling modules (`prim_alert_receiver`, `prim_esc_sender`) instantiated within the alert handler are connected to a central ping timer that alternatingly pings either an alert line or an escalation line after waiting for a pseudo-random amount of clock cycles.
+Further, this ping timer also randomly selects a particular alert line to be pinged (escalation senders are always pinged in-order due to the [ping monitoring mechanism](#monitoring-of-pings-at-the-escalation-receiver-side) on the escalation side).
+That should make it more difficult to predict the next ping occurrence based on past observations.
+
+The ping timer is implemented using an [LFSR-based PRNG of Galois type](../../ip/prim/doc/prim_lfsr.md).
+This ping timer is reseeded with fresh entropy from EDN roughly every 500k cycles which corresponds to around 16 ping operations on average.
+The LFSR is 32bits wide, but only 24bits of its state are actually being used to generate the random timer count and select the alert line to be pinged.
+I.e., the 32bits first go through a fixed permutation function, and then bits `[23:16]` are used to determine which alert line to ping.
+The random cycle count is created by OR'ing bits `[15:0]` with the constant `3'b100` as follows:
+
+```
+cycle_cnt = permuted[15:0] | 3'b100;
+```
+
+This constant DC offset introduces a minimum ping spacing of 4 cycles (1 cycle + margin) to ensure that the handshake protocols of the sender/receiver pairs work.
+
+After selecting one of the peripherals to ping, the LFSR timer waits until either the corresponding `*_ping_ok[<number>]` signal is asserted, or until the programmable ping timeout value is reached.
+In both cases, the LFSR timer proceeds with the next ping, but in the second case it will additionally raise a "pingfail" alert.
+The ping enable signal remains asserted during the time where the LFSR counter waits.
+
+The timeout value is a function of the ratios between the alert handler clock and peripheral clocks present in the system, and can be programmed at startup time via the register [`PING_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timeout_cyc_shadowed).
+
+Note that the ping timer directly flags a "pingfail" alert if a spurious "ping ok" message comes in that has not been requested.
+
+
+As described in the programmers guide below, the ping timer has to be enabled explicitly.
+Only alerts that have been *enabled and locked* will be pinged in order to avoid spurious alerts.
+Escalation channels are always enabled, and hence will always be pinged once this mechanism has been turned on.
+
+In addition to the ping timer mechanism described above, the escalation receivers contain monitoring counters that monitor the liveness of the alert handler (described in more detail in [this section](#monitoring-of-pings-at-the-escalation-receiver-side).
+This mechanism requires that the maximum wait time between escalation receiver pings is bounded.
+To that end, escalation senders are pinged in-order every second ping operation (i.e., the wait time is randomized, but the selection of the escalation line is not).
+
+### Alert Receiving
+
+The alert handler module contains one alert receiver module (`prim_alert_receiver`) per sending module.
+This receiver module has three outputs based upon the signaling of the input alert.
+Primary is the signal of a received native alert, shown in the top-level diagram as `alert_triggered[<number>]`.
+Also generated are two other outputs, one that signals a differential encoding error (`alert_integ_fail[<number>]`), and one that signals the receipt of a ping response (`alert_ping_ok[<number>]`).
+Each "triggered" alert received is sent into the classification block for individual configuration.
+All of the `integ_fail` signals are OR'ed together to create one alert for classification.
+The ping responses are fed to the LFSR timer, which determines whether a ping has correctly completed within the timeout window or not.
+
+
+### Alert Classification and Interrupts
+
+Each of the incoming and local alert signals can be classified generically to one of four classes, or disabled for no classification at all.
+These are the classes A, B, C, and D.
+There is no pre-determined definition of a class, that is left to software.
+But for guidance, software can consider that some alert types are similar to others; some alert types are more "noisy" than others (i.e. when triggered they stay on for long periods of time); some are more critical than others, etc.
+
+For each alert class (A-D), an interrupt is generally sent.
+Like all other peripheral interrupts, there is a triad of registers: enable, status, test.
+Thus like all other interrupts, software should handle the source of the interrupt (in this case, the original alert), then clear the state.
+Since the interrupt class is disassociated with the original alert (due to the classification process), software can access cause registers to determine which alerts have fired since the last clearing.
+Since alerts are expected to be rare (if ever) events, the complexity of dealing with multiple interrupts per class firing during the same time period should not be of concern. See the programming section on interrupt clearing.
+
+Each of the four interrupts can optionally trigger a timeout counter that triggers escalation if the interrupt is not handled and cleared within a certain time frame.
+This feature is explained in more detail in the next subsection about escalation mechanisms.
+
+Note that an interrupt always fires once an alert has been registered in the corresponding class.
+Interrupts are not dependent on escalation mechanisms like alert accumulation or timeout as described in the next subsection.
+
+
+### Escalation Mechanisms
+
+There are two mechanisms per class that can trigger the corresponding escalation
+protocol:
+
+1. The first consists of an accumulation counter that counts the amount of alert occurrences within a particular class.
+ An alert classified to class A indicates that on every received alert trigger, the accumulation counter for class A is incremented.
+ Note: since alerts are expected to be rare or never occur, the module does not attempt to count every alert per cycle, but rather all triggers per class are ORd before sending to the accumulation counter as an increment signal.
+ Once the threshold has been reached, the next occurrence triggers the escalation escalation protocol for this particular class.
+ The counter is a saturation counter, meaning that it will not wrap around once it hits the maximum representable count.
+ This mechanism has two associated CSRs:
+
+ - Accumulation max value.
+ This is the total number (sum of all alerts classified in this group) of alerts required to enter escalation phase (see below).
+ Example register is [`CLASSA_ACCUM_THRESH_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_thresh_shadowed).
+ - Current accumulation register.
+ This clearable register indicates how many alerts have been accumulated to date.
+ Software should clear before it reaches the accumulation setting to avoid escalation.
+ Example register is [`CLASSA_ACCUM_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_cnt).
+
+2. The second way is an interrupt timeout counter which triggers escalation if an alert interrupt is not handled within the programmable timeout window.
+ Once the counter hits the timeout threshold, the escalation protocol is triggered.
+ The corresponding CSRs are:
+
+ - Interrupt timeout value in cycles [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed).
+ The interrupt timeout is disabled if this is set to 0 (default).
+ - The current interrupt timeout value can be read via [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt) if [`CLASSA_STATE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_state) is in the `Timeout` state.
+ Software should clear the corresponding interrupt state bit [`INTR_STATE.CLASSA`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#intr_state) before the timeout expires to avoid escalation.
+
+Technically, the interrupt timeout feature (2. above) is implemented using the same counter used to time the escalation phases.
+This is possible since escalation phases or interrupt timeout periods are non-overlapping (escalation always takes precedence should it be triggered).
+
+
+### Programmable Escalation Protocol
+
+There are four output escalation signals, 0, 1, 2, and 3.
+There is no predetermined definition of an escalation signal, that is left to the top-level integration.
+Examples could be processor Non Maskable Interrupt (NMI), privilege lowering, secret wiping, chip reset, etc.
+Typically the assumption is that escalation level 0 is the first to trigger, followed by 1, 2, and then 3, emulating a "fuse" that is lit that can't be stopped once the first triggers (this is however not a requirement).
+See register section for discussion of counter clearing and register locking to determine the finality of accumulation
+triggers.
+
+Each class can be programmed with its own escalation protocol.
+If one of the two mechanisms described above fires, a timer for that particular class is started.
+The timer can be programmed with up to 4 delays (e.g., [`CLASSA_PHASE0_CYC`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_phase0_cyc)), each representing a distinct escalation phase (0 - 3).
+Each of the four escalation severity outputs (0 - 3) are by default configured to be asserted during the corresponding phase, e.g., severity 0 in phase 0, severity 1 in phase 1, etc.
+However, this mapping can be freely reassigned by modifying the corresponding enable/phase mappings (e.g., [`CLASSA_CTRL_SHADOWED.E0_MAP`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) for enable bit 0 of class A).
+This mapping will be locked in together with the alert enable configuration after initial configuration.
+
+SW can stop a triggered escalation protocol by clearing the corresponding escalation counter (e.g., [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt)).
+Protection of this clearing is up to software, see the register control section that follows for [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed).
+
+It should be noted that each of the escalation phases have a duration of at least 1 clock cycle, even if the cycle count of a particular phase has been
+set to 0.
+
+The next waveform shows the gathering of alerts of one class until eventually the escalation protocol is engaged.
+In this diagram, two different alerts are shown for class A, and the gathering and escalation configuration values are shown.
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p...................' },
+ { name: 'CLASSA_ACCUM_THRESH_SHADOWED', wave: '2...................', data: ['15'] },
+ { name: 'CLASSA_PHASE0_CYC_SHADOWED', wave: '2...................', data: ['1e3 cycles'] },
+ { name: 'CLASSA_PHASE1_CYC_SHADOWED', wave: '2...................', data: ['1e4 cycles'] },
+ { name: 'CLASSA_PHASE2_CYC_SHADOWED', wave: '2...................', data: ['1e5 cycles'] },
+ { name: 'CLASSA_PHASE3_CYC_SHADOWED', wave: '2...................', data: ['1e6 cycles'] },
+ { name: 'alert_triggered[0]', wave: '010|.10.............' },
+ { name: 'alert_triggered[1]', wave: '0..|10..............' },
+ { name: 'CLASSA_ACCUM_CNT', wave: '33.|33..............', data: ['0', '1','15','16'] },
+ { name: 'irq_o[0]', wave: '01.|................' },
+ { name: 'CLASSA_STATE', wave: '3..|.3|3.|3..|3..|3.', data: ['Idle', ' Phase0','Phase1','Phase2','Phase3','Terminal'] },
+ { name: 'CLASSA_ESC_CNT', wave: '3..|.3|33|333|333|3.', data: ['0','1','1','2','1','2','3','1','2','3','0'] },
+ { name: 'esc_tx_o.esc_p[0]', wave: '0..|.1|.0...........', node: '.....a..b' },
+ { name: 'esc_tx_o.esc_n[0]', wave: '1..|.0|.1...........' },
+ { name: 'esc_tx_o.esc_p[1]', wave: '0..|..|1.|.0........', node: '.......c...d' },
+ { name: 'esc_tx_o.esc_n[1]', wave: '1..|..|0.|.1........' },
+ { name: 'esc_tx_o.esc_p[2]', wave: '0..|.....|1..|.0....', node: '..........e....f' },
+ { name: 'esc_tx_o.esc_n[2]', wave: '1..|.....|0..|.1....' },
+ { name: 'esc_tx_o.esc_p[3]', wave: '0..|.........|1..|.0', node: '..............g....h' },
+ { name: 'esc_tx_o.esc_n[3]', wave: '1..|.........|0..|.1' },
+ ],
+ edge: [
+ 'a->b 1e3 + 1 cycles',
+ 'c->d 1e4 + 1 cycles',
+ 'e->f 1e5 + 1 cycles',
+ 'g->h 1e6 + 1 cycles',
+ ],
+ head: {
+ text: 'Alert class gathering and escalation triggers (fully synchronous case)',
+ },
+ foot: {
+ text: 'alert class A gathers 16 alerts, triggers first escalation, followed by three more',
+ tick: 0,
+ }
+}
+```
+
+In this diagram, the first alert triggers an interrupt to class A.
+The assumption is that the processor is wedged or taken over, in which case it does not handle the interrupt.
+Once enough interrupts gather (16 in this case), the first escalation phase is entered, followed by three more (each phase has its own programmable length).
+Note that the accumulator threshold is set to 15 in order to trigger on the 16th occurrence.
+If escalation shall be triggered on the first occurrence within an alert class, the accumulation threshold shall be set to 0.
+Also note that it takes one cycle to activate escalation and enter phase 0.
+
+The next wave shows a case where an interrupt remains unhandled and hence the interrupt timeout counter triggers escalation.
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p.....................' },
+ { name: 'CLASSA_TIMEOUT_CYC_SHADOWED', wave: '2.....................', data: ['1e4 cycles'] },
+ { name: 'alert_triggered[0]', wave: '010.|.................' },
+ { name: 'irq_o[0]', wave: '01..|.................', node: '.a..|.b' },
+ { name: 'CLASSA_ESC_STATE', wave: '33..|.3|3.|3..|3...|3.', data: ['Idle', 'Timeout',' Phase0','Phase1','Phase2','Phase3','Terminal'] },
+ { name: 'CLASSA_ESC_CNT', wave: '3333|33|33|333|3333|3.', data: ['0', '1','2','3','1e4','1','1','2','1','2','3','1','2','3','4','0'] },
+ { name: 'esc_tx_o.esc_p[0]', wave: '0...|.1|.0............' },
+ { name: 'esc_tx_o.esc_n[0]', wave: '1...|.0|.1............' },
+ { name: 'esc_tx_o.esc_p[1]', wave: '0...|..|1.|.0.........' },
+ { name: 'esc_tx_o.esc_n[1]', wave: '1...|..|0.|.1.........' },
+ { name: 'esc_tx_o.esc_p[2]', wave: '0...|.....|1..|.0.....' },
+ { name: 'esc_tx_o.esc_n[2]', wave: '1...|.....|0..|.1.....' },
+ { name: 'esc_tx_o.esc_p[3]', wave: '0...|.........|1...|.0' },
+ { name: 'esc_tx_o.esc_n[3]', wave: '1...|.........|0...|.1' },
+ ],
+ edge: [
+ 'a->b 1e4 cycles',
+ ],
+ head: {
+ text: 'Escalation due to an interrupt timeout (fully synchronous case)',
+ },
+ foot: {
+ text: 'alert class A triggers an interrupt and the timeout counter, which eventually triggers escalation after 1e4 cycles.',
+ tick: 0,
+ }
+}
+```
+
+It should be noted here that the differential escalation signaling protocol distinguishes 'true' escalation conditions from mere pings by encoding them as pulses that are N + 1 cycles long.
+This is reflected in the two wave diagrams above.
+Refer to the subsequent section on escalation signaling for more details.
+
+### Escalation Signaling
+
+For each of the four escalation severities, the alert handler instantiates a `prim_esc_sender` module and each of the four escalation countermeasures instantiates an `prim_esc_receiver` module.
+The signaling mechanism has similarities with the alert signaling mechanism - but it is a fully synchronous protocol.
+Hence, it must be ensured at the top-level that all escalation sender and receiver modules are using the same clock and reset
+signals.
+
+As illustrated in the following block diagram, a sender-receiver pair is connected with two differential lines, one going from sender to receiver and the other going from receiver to sender.
+
+
+
+Upon receiving an escalation enable pulse of width N > 0 at the `esc_req_i` input, the escalation sender encodes that signal as a differential pulse of width N+1 on `esc_tx.esc_p/n`.
+The receiver decodes that message and asserts the `esc_req_o` output after one cycle of delay.
+Further, it acknowledges the receipt of that message by continuously toggling the `esc_rx.resp_p/n` signals as long as the escalation signal is asserted.
+Any failure to respond correctly will trigger a `integ_fail_o` alert, as illustrated below:
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p..................' },
+ { name: 'ping_req_i', wave: '0........|.........' },
+ { name: 'ping_ok_o', wave: '0........|.........' },
+ { name: 'integ_fail_o', wave: '0........|..1010...' , node: '............b.d' },
+ { name: 'ping_fail_o', wave: '0........|.........' },
+ { name: 'esc_req_i', wave: '01....0..|.1....0..' },
+ { name: 'esc_rx_i/o.resp_p', wave: '0.101010.|.........', node: '............a.c' },
+ { name: 'esc_rx_i/o.resp_n', wave: '1.010101.|.........' },
+ { name: 'esc_tx_o/i.esc_p', wave: '01.....0.|.1.....0.' },
+ { name: 'esc_tx_o/i.esc_n', wave: '10.....1.|.0.....1.' },
+ { name: 'esc_req_o', wave: '0.1....0.|..?....0.'},
+ ],
+ edge: [
+ 'a~>b missing response',
+ 'c~>d',
+ ],
+ head: {
+ text: 'Escalation signaling and response',
+ },
+ foot: {
+ text: 'escalation enable pulse shown at input sender at time 1 and 11; missing response and repeated integfail at time 12 and 14',
+ tick: 0,
+ }
+}
+```
+
+Further, any differential signal mismatch on both the `esc_tx_i.esc_p/n` and `esc_rx_i.resp_p/n` lines will trigger an `integ_fail_o` alert.
+Mismatches on `esc_rx_i.resp_p/n` can be directly detected at the sender.
+Mismatches on the `esc_tx_i.esc_p/n` line will be signaled back to the sender by setting both the positive and negative response wires to the same value - and that value is being toggled each cycle.
+This implicitly triggers a signal integrity alert on the sender side.
+In addition to that, a signal integrity error on the `esc_tx_i.esc_p/n` lines will lead to assertion of the `esc_req_o` output, since it cannot be guaranteed that the back signalling mechanism always works when the sender / receiver pair is being tampered with.
+
+This back-signaling mechanism can be leveraged to fast-track escalation and use another countermeasure in case it is detected that a particular escalation signaling path has been tampered with.
+
+Some signal integrity failure cases are illustrated in the wave diagram below:
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p...........' },
+ { name: 'ping_req_i', wave: '0....|......' },
+ { name: 'ping_ok_o', wave: '0....|......' },
+ { name: 'integ_fail_o', wave: '0.1.0|.1....' , node: '..b....e' },
+ { name: 'esc_req_i', wave: '0....|......' },
+ { name: 'esc_rx_i.resp_p', wave: '0.1.0|..1010', node: '..a..' },
+ { name: 'esc_rx_i.resp_n', wave: '1....|.01010', node: '.......d' },
+ { name: 'esc_tx_i.esc_p', wave: '0....|1.....', node: '......c..' },
+ { name: 'esc_tx_i.esc_n', wave: '1....|......' },
+ { name: 'esc_req_o', wave: '0....|1.....'},
+ ],
+ edge: [
+ 'a~>b',
+ 'c->d',
+ 'd->e',
+ ],
+ head: {
+ text: 'possible signal integrity failure cases',
+ },
+ foot: {
+ text: 'direct signal integrity failure at time 2; indirect failure at time 6',
+ tick: 0,
+ }
+}
+```
+
+
+### Ping Testing of the Escalation Signals
+
+
+Similarly to the alert signaling scheme, the escalation signaling lines can be pinged / line tested in order to test whether the escalation receiver has been tampered with.
+This is achieved by asserting `ping_req_i` at the escalation sender module.
+A ping request is encoded as a single cycle pulse on the `esc_tx_o.esc_p/n` outputs.
+Hence, the receiver module will not decode this single cycle pulse as an escalation enable message, but it will respond to it with a "1010" pattern on the `esc_rx_i.resp_p/n` lines.
+The escalation sender module will assert `ping_ok_o` if that pattern is received correctly after one cycle of latency.
+Otherwise, the escalation sender will first assert `integ_fail_o` later, after the programmable ping timeout is reached, the LFSR timer will raise a "pingfail" alert.
+The `integ_fail_o` triggers in this case since "no ping response" and "wrong ping response" are ambiguous in this setting, and it has been decided to not suppress integrity failures when expecting a ping response.
+
+This mechanism is illustrated below from the viewpoint of the sender module.
+
+```wavejson
+{
+ signal: [
+ { name: 'clk_i', wave: 'p..............' },
+ { name: 'ping_req_i', wave: '01....0|.1.....' , node: '.a'},
+ { name: 'ping_ok_o', wave: '0....10|.......' , node: '.....e....g'},
+ { name: 'integ_fail_o', wave: '0......|..10101' },
+ { name: 'esc_req_i', wave: '0......|.......' },
+ { name: 'esc_rx_i.resp_p', wave: '0.1010.|.......' , node: '..c..d....f'},
+ { name: 'esc_rx_i.resp_n', wave: '1.0101.|.......' },
+ { name: 'esc_tx_o.esc_p', wave: '010....|.10....' , node: '.b'},
+ { name: 'esc_tx_o.esc_n', wave: '101....|.01....' },
+ ],
+ edge: [
+ 'a->b',
+ 'b->c',
+ 'd->e correct response',
+ 'f->g missing response',
+ ],
+ head: {
+ text: 'ping testing of escalation lines',
+ },
+ foot: {
+ text: 'ping trig at sender input at time 1 and 9; correct response at time 5; missing response at time 10',
+ tick: 0,
+ }
+}
+```
+
+Note that the escalation signal always takes precedence, and the `ping_req_i` will just be acknowledged with `ping_ok_o` in case `esc_req_i` is already asserted.
+An ongoing ping sequence will be aborted immediately.
+
+Another thing to note is that the ping and escalation response sequences have to start _exactly_ one cycle after either a ping or escalation event has been signaled.
+Otherwise the escalation sender will assert `integ_fail_o` immediately.
+
+### Monitoring of Pings at the Escalation Receiver Side
+
+Escalation receivers contain a mechanism to monitor the liveness of the alert handler itself.
+In particular, the receivers passively monitor the ping requests sent out by the alert handler using a timeout counter.
+If ping requests are absent for too long, the corresponding escalation action will be automatically asserted until reset.
+
+The monitoring mechanism builds on top of the following properties of the alert handler system:
+1. the ping mechanism can only be enabled, but not disabled.
+This allows us to start the timeout counter once the first ping request arrives at a particular escalation receiver.
+
+2. the escalation receivers are in the same clock/reset domain as the alert handler.
+This ensures that we are seeing the same clock frequency, and the mechanism is properly reset together with the alert handler logic.
+
+3. the maximum cycle count between subsequent pings on the same escalation line is bounded, even though the wait counts are randomized.
+This allows us to compute a safe and fixed timeout threshold based on design constants.
+
+
+### Low-power Management of Alert Channels
+
+Due to the various clock and reset domains in the OpenTitan system, the alert handler ping mechanism needs to have additional logic to deal with alert senders that are either held in reset, or that are clock gated.
+This is needed to ensure that no false alarms are produced by the ping mechanism when an alert channel (sender / receiver pair) does not respond due to the sender being either in reset or clock gated.
+
+Since the FSMs associated with an alert channel may end up in an inconsistent state when the sender is reset or gated while an asynchronous event handshake is in progress, this logic also needs to be able to re-initialize affected alert channels whenever the channels comes back from reset / clock gated state.
+
+#### Assumptions
+
+The following diagram shows a typical arrangement of alert sender (TX) and receiver (RX) pairs.
+
+
+
+It is assumed that:
+
+1. The alert handler clock domain cannot be gated by SW.
+ This means that this clock domain is only ever disabled as part of the power-down sequence of the corresponding power domain.
+2. The alert senders are in general located within different clock and reset domains than the alert receivers within the alert handler, and thus use the asynchronous event handshake mode.
+3. Some alert senders may be located in an always-on (AON) power domain, within different clock and reset groups than the alert handler.
+4. The alert handler may be located in an non-AON power domain, and may thus undergo a reset cycle where it cannot be guaranteed that all alert senders are reset as well (i.e., some alert senders may retain their state).
+
+Further, we assume that we can get the following side-band information from the clock and reset managers in the system:
+
+- All relevant reset signals pertaining to alert sender domains
+- All relevant clock enable signals pertaining to alert sender domains
+
+#### Scenarios
+
+With the assumptions above, the following two problematic scenarios can occur.
+
+##### Alert Handler in Reset
+
+It may happen that the alert handler is reset while some alert senders (e.g. those located in the AON domain) are not.
+In general, if the associated alert channels are idle during an alert handler reset cycle, no problems arise.
+
+However, if an alert channel is reset while it is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state upon deassertion of the alert handler reset.
+This can either lead to spurious alert or ping events, or a completely locked up alert channel which will be flagged eventually by the ping mechanism.
+
+##### Alert Sender in Reset or Clock-gated
+
+If any of the alert senders is either put into reset or its clock is disabled while the alert handler is operational, the ping mechanism inside the alert handler will eventually report a ping failure because of missing ping responses from the affected alert channel(s).
+
+Further, if the alert sender is reset while the corresponding alert channel is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state after reset deassertion.
+
+#### Employed Solution
+
+As elaborated before, the side effects of resetting / clock gating either the alert handler or any of the alert senders are inconsistent FSM states, leading to locked up alert channels, or spurious alert or ping events.
+To address these issues, we have to:
+
+1. make sure spurious events (alert and ping_ok outputs of the alert receivers) are suppressed if an alert channel is clock gated or in reset,
+2. provide a mechanism for resetting an alert channel to an operational state once the associated clock is re-enabled, or the associated reset is released,
+3. trigger this reset mechanism on all alert channels whenever the alert handler itself has been reset.
+
+To attain this, the idea is to make use of side-band information available from the clock and reset managers to detect whether an alert channel (or a group of alert channels with the same clock and reset on the sender side) has to be put into a low-power state.
+In the following we will refer to such a clock / reset domain grouping as a low-power group (LPG).
+
+The mechanism is illustrated below for a single LPG (in practice, this logic is replicated for each LPG that is identified in the system):
+
+
+
+The clock gating enable (`lpg_cg_en`) and reset enable (`lpg_rst_en`) indications are routed as multibit signals to the alert handler, where they are synchronized to the alert handler clock and logically combined using an OR function to form a combined low-power indication signal that is multibit encoded.
+
+This multibit indication signal is then routed to all alert receivers, where it is used to trigger re-initialization of each alert channel, and bypass the ping requests from the ping mechanism.
+
+To that end, two extra *init states* are added to the alert receiver FSMs to perform this in-band reset, as indicated in the state diagram below:
+
+
+
+Whenever the `init_trig` multibit signal of an LPG is asserted, all corresponding sender FSMs are moved into the `InitReq` state.
+In that state, the alert receivers immediately acknowledge ping requests from the ping mechanism, and ignore alert events from the sender side.
+In addition to that, the receivers intentionally place a signal integrity error onto the `ping_p` / `ping_n`, `ack_p` / `ack_n` lines going from receivers to the senders.
+This causes the senders to 1) move into the signal integrity error state, and 2) respond by placing a signal integrity error onto the `alert_p` / `alert_n` lines, which serves as an initialization "acknowledge" signal in this case.
+Since the sender FSMs fall back into the `Idle` state once the signal integrity error disappears, this procedure essentially implements an in-band reset mechanism with an acknowledgement handshake that can be used to determine whether the reset has been successful.
+
+#### Implementation Aspects
+
+##### Ping Mechanism Bypass
+
+Note that the ping bypass mechanism is to be implemented in a way that pings are only ack'ed immediately if 1) the FSM is in the `InitReq` state, and 2) the `init_trig` signal is still asserted.
+
+This allows to subject the initialization process of each alert channel to the ping mechanism for channels that are recovering from a reset or clock gated cycle on the sender side.
+I.e., alert channels that get stuck during the initialization process can be detected by the ping mechanism since ping requests are not immediately ack'ed anymore once `init_trig` is deasserted.
+
+##### FSM Encoding
+
+Since there are many alert channels in the design, the receiver and sender FSMs themselves are not sparsely encoded.
+Instead, we rely on the ping mechanism to detect alert channels that are in a bad state.
+The specific implementation of the ping bypass mentioned in the previous subsection ensures that the ping mechanism can also be used to monitor the initialization sequence of alert channels.
+
+##### Latency / Skew Considerations
+
+Due to asynchronous transitions and different path latencies in the system, a change in reset or clock gating state will experience a different latency through the alert channels than through the indication signals (`rst_n` and `clk_en`) that are connected to the low-power control logic.
+
+It is consequently possible for a group of alert senders to already be in reset or clock gated state, while the corresponding LPG logic does not yet know about this state change - and vice versa.
+
+In practice, this means that ping requests may be pending for several cycles until the LPG logic detects a reset or clock-gated condition and disables the corresponding alert channel(s).
+Fortunately, such delay can be tolerated by setting the ping timeout to a sufficiently large value (see [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed)).
+
+As for alert events, this latency difference should not pose a problem.
+Alert events may get stuck in the alert sender due to a reset or clock-gated condition - but this is to be expected.
+
+##### Integration Considerations
+
+Note that due to the aforementioned latency tolerance built into the ping timer, it is permissible to connect **any** reset or clock enable indication signal from the relevant clock group to the LPG logic.
+I.e., the only requirement is that the indication signals are logically related to the resets and clocks routed to the alert senders, and that the skew between reset / clock state changes and the indication signals is bounded.
+
+The topgen script is extended so that it can identify all LPGs and the associated alert channels.
+This information is then used to parameterize the alert handler design, and make the necessary top-level connections from the reset and clock management controllers to the alert handler.
+
+### Hardening Against Glitch Attacks
+
+In addition to the differential alert and escalation signalling scheme, the internal state machines and counters are hardened against glitch attacks as described bellow:
+
+1. Ping Timer:
+ - The FSM is sparsely encoded.
+ - The LFSR and the counter are duplicated.
+ - If the FSM or counter are glitched into an invalid state, all internal ping fail alerts will be permanently asserted.
+
+2. Escalation Timers:
+ - The escalation timer FSMs are sparsely encoded.
+ - The escalation timer counters are duplicated.
+ - The escalation accumulators are duplicated.
+ - If one of these FSMs, counters or accumulators are glitched into an invalid state, all escalation actions will be triggered and the affected FSM goes into a terminal `FsmError` state.
+
+3. CSRs:
+ - Critical configuration CSRs are shadowed.
+ - The shadow CSRs can trigger additional internal alerts for CSR storage and update failures.
+ These internal alerts are fed back into the alert classifier in the same manner as the ping and integrity failure alerts.
+
+4. LPGs:
+ - Clock-gated and reset-asserted indication signals that are routed from clock and reset managers to the alert handler are encoded with multibit signals.
+
+# Programmers Guide
+
+
+## Power-up and Reset Considerations
+
+False alerts during power-up and reset are not possible since the alerts are disabled by default, and need to be configured and locked in by the firmware.
+The ping timer won't start until initial configuration is over and the registers are locked in.
+
+The low-power state management of alert channels is handled entirely by hardware and hence this is transparent to software.
+Note however that the LPGs inherit the security properties of the associated clock groups and resets.
+This means that the low-power state of certain alerts can be controlled by SW by means of clock gating or block reset.
+For example, certain crypto blocks are located in a transactional clock group which can be clock gated by SW - and this also affects the associated alerts of these crypto blocks.
+See [clock](../../ip/clkmgr/README.md) and [reset managers](../../ip/rstmgr/README.md) for more detail.
+
+
+## Initialization
+
+To initialize the block, software running at a high privilege levels (early in the security settings process) should do the following:
+
+1. For each alert and each local alert:
+
+ - Determine if alert is enabled (should only be false if alert is known to be faulty).
+ Set [`ALERT_EN_SHADOWED_0.EN_A_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_en_shadowed_0) and [`LOC_ALERT_EN_SHADOWED_0.EN_LA_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_en_shadowed_0) accordingly.
+
+ - Determine which class (A..D) the alert is associated with.
+ Set [`ALERT_CLASS_SHADOWED_0.CLASS_A_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_class_shadowed_0) and [`LOC_ALERT_CLASS_SHADOWED_0.CLASS_LA_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_class_shadowed_0) accordingly.
+
+ - Optionally lock each alert configuration by writing 0 to [`ALERT_REGWEN_0.EN_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_regwen_0) or [`LOC_ALERT_REGWEN_0.EN_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_regwen_0).
+ Note however that only **locked and enabled** alerts are going to be pinged using the ping mechanism.
+ This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking).
+
+
+2. Set the ping timeout value [`PING_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timeout_cyc_shadowed).
+ This value is dependent on the clock ratios present in the system.
+
+3. For each class (A..D):
+
+ - Determine whether to enable escalation mechanisms (accumulation / interrupt timeout) for this particular class. Set [`CLASSA_CTRL_SHADOWED.EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) accordingly.
+
+ - Determine if this class of alerts allows clearing of escalation once it has begun.
+ Set [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) to true if clearing should be disabled.
+ If true, once escalation protocol begins, it can not be stopped, the assumption being that it ends in a chip reset else it will be rendered useless thenceforth.
+
+ - Determine the number of alerts required to be accumulated before escalation protocol kicks in. Set [`CLASSA_ACCUM_THRESH`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_thresh) accordingly.
+
+ - Determine whether the interrupt associated with that class needs a timeout.
+ If yes, set [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed) to an appropriate value greater than zero (zero corresponds to an infinite timeout and disables the mechanism).
+
+ - For each escalation phase (0..3):
+ - Determine length of each escalation phase by setting [`CLASSA_PHASE0_CYC`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_phase0_cyc) accordingly
+
+ - For each escalation signal (0..3):
+ - Determine whether to enable the escalation signal, and set the [`CLASSA_CTRL_SHADOWED.E0_EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) bit accordingly (default is enabled).
+ Note that setting all of the `E*_EN` bits to 0 within a class has the same effect of disabling the entire class by setting [`CLASSA_CTRL_SHADOWED.EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) to zero.
+ - Determine the phase -> escalation mapping of this class and program it via the [`CLASSA_CTRL_SHADOWED.E0_MAP`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) values if it needs to be changed from the default mapping (0->0, 1->1, 2->2, 3->3).
+
+ - Optionally lock the class configuration by writing 0 to [`CLASSA_CTRL_SHADOWED.REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed).
+
+4. After initial configuration at startup, enable the ping timer mechanism by writing 1 to [`PING_TIMER_EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timer_en).
+It is also recommended to lock the ping timer configuration by clearing [`PING_TIMER_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timer_regwen).
+Note that only **locked and enabled** alerts are going to be pinged using the ping mechanism.
+This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking).
+
+## Interrupt Handling
+
+For every alert that is enabled, an interrupt will be triggered on class A, B, C, or D.
+To handle an interrupt of a particular class, software should execute the following steps:
+
+1. If needed, check the escalation state of this class by reading [`CLASSA_STATE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_state).
+ This reveals whether escalation protocol has been triggered and in which escalation phase the class is.
+ In case interrupt timeouts are enabled the class will be in timeout state unless escalation has already been triggered.
+ The current interrupt or escalation cycle counter can be read via [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt).
+
+2. Since the interrupt does not indicate which alert triggered, SW must read the cause registers [`LOC_ALERT_CAUSE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_cause) and [`ALERT_CAUSE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_cause) etc.
+ The cause bits of all alerts are concatenated and chunked into 32bit words.
+ Hence the register file contains as many cause words as needed to cover all alerts present in the system.
+ Each cause register contains a sticky bit that is set by the incoming alert, and is clearable with a write by software.
+ This should only be cleared after software has cleared the event trigger, if applicable.
+ It is possible that the event requires no clearing (e.g. a parity error), or can't be cleared (a breach in the metal mesh protecting the chip).
+
+ Note that in the rare case when multiple events are triggered at or about the same time, all events should be cleared before proceeding.
+
+3. After the event is cleared (if needed or possible), software should handle the interrupt as follows:
+
+ - Resetting the accumulation register for the class by writing [`CLASSA_CLR`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr).
+ This also aborts the escalation protocol if it has been triggered.
+ If for some reason it is desired to never allow the accumulator or escalation to be cleared, software can initialize the [`CLASSA_CLR_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr_regwen) register to zero.
+ If [`CLASSA_CLR_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr_regwen) is already false when an alert interrupt is detected (either due to software control or hardware trigger via [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed)), then the accumulation counter can not be cleared and this step has no effect.
+
+ - After the accumulation counter is reset (if applicable), software should clear the class A interrupt state bit [`INTR_STATE.CLASSA`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#intr_state).
+ Clearing the class A interrupt state bit also clears and stops the interrupt timeout counter (if enabled).
+
+Note that testing interrupts by writing to the interrupt test registers does also trigger the internal interrupt timeout (if enabled), since the interrupt state is used as enable signal for the timer.
+However, alert accumulation will not be triggered by this testing mechanism.
+
+## Device Interface Functions (DIFs)
+
+- [Device Interface Functions](../../../sw/device/lib/dif/dif_alert_handler.h)
+
+## Register Table
+
+* [Register Table](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#registers)
+
+
+# Additional Notes
+
+## Timing Constraints
+
+The skew within all differential signal pairs must be constrained to be smaller than the period of the fastest clock operating the alert handler receivers.
+The maximum propagation delay of differential pair should also be constrained (although it may be longer than the clock periods involved).
+
+
+## Fast-track Alerts
+
+Note that it is possible to program a certain class to provide a fast-track response for critical alerts by setting its accumulation trigger value to 1, and configuring the escalation protocol such that the appropriate escalation measure is triggered within escalation phase 0.
+This results in a minimal escalation latency of 4 clock cycles from alert sender input to escalation receiver output in the case where all involved signaling modules are completely synchronous with the alert handler.
+In case the alert sender is asynchronous w.r.t. to the alert handler, the actual latency depends on the clock periods involved.
+Assuming both clocks have the same frequency alert propagation takes at least 6-8 clock alert handler clock cycles.
+
+For alerts that mandate an asynchronous response (i.e. without requiring a clock to be active), it is highly recommended to build a separate network at the top-level.
+That network should OR' the critical sources together and route the asynchronous alert signal directly to the highest severity countermeasure device.
+Examples for alert conditions of this sort would be attacks on the secure clock.
diff --git a/hw/top_sencha/ip_autogen/alert_handler/alert_handler.core b/hw/top_sencha/ip_autogen/alert_handler/alert_handler.core
new file mode 100644
index 0000000..44f10d9
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/alert_handler.core
@@ -0,0 +1,38 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler:0.1
+description: "Alert Handler"
+virtual:
+ - lowrisc:ip_interfaces:alert_handler
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:alert_handler_component
+ - lowrisc:opentitan:top_sencha_alert_handler_reg:0.1
+ file_type: systemVerilogSource
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: alert_handler
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip_autogen/alert_handler/alert_handler_component.core b/hw/top_sencha/ip_autogen/alert_handler/alert_handler_component.core
new file mode 100644
index 0000000..97cb604
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/alert_handler_component.core
@@ -0,0 +1,63 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:alert_handler_component:0.1"
+description: "Alert Handler component without the CSRs"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:prim:esc
+ - lowrisc:prim:double_lfsr
+ - lowrisc:prim:count
+ - lowrisc:prim:edn_req
+ - lowrisc:prim:buf
+ - lowrisc:prim:mubi
+ - lowrisc:prim:sparse_fsm
+ - lowrisc:ip_interfaces:alert_handler_reg
+ files:
+ - rtl/alert_pkg.sv
+ - rtl/alert_handler_reg_wrap.sv
+ - rtl/alert_handler_lpg_ctrl.sv
+ - rtl/alert_handler_class.sv
+ - rtl/alert_handler_ping_timer.sv
+ - rtl/alert_handler_esc_timer.sv
+ - rtl/alert_handler_accu.sv
+ - rtl/alert_handler.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/alert_handler.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/alert_handler.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+
+targets:
+ default: &default_target
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/ip_autogen/alert_handler/alert_handler_reg.core b/hw/top_sencha/ip_autogen/alert_handler/alert_handler_reg.core
new file mode 100644
index 0000000..b262afc
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/alert_handler_reg.core
@@ -0,0 +1,27 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler_reg:0.1
+description: "Auto-generated alert handler register sources"
+virtual:
+ # TODO: Check if the generated files actually maintain a stable public API.
+ - "lowrisc:ip_interfaces:alert_handler_reg"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:tlul:headers
+ - lowrisc:prim:subreg
+ - lowrisc:ip:tlul
+ - lowrisc:prim:subreg
+ files:
+ - rtl/alert_handler_reg_pkg.sv
+ - rtl/alert_handler_reg_top.sv
+ file_type: systemVerilogSource
+
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
diff --git a/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler.hjson
new file mode 100644
index 0000000..295a377
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -0,0 +1,1933 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# ALERT_HANDLER register template
+
+{
+ name: "alert_handler",
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_alert_handler"
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D3",
+ verification_stage: "V2S",
+ dif_stage: "S2",
+ notes: "Use both FPV and DV to perform block level verification.",
+ clocking: [
+ {clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_edn_i", reset: "rst_edn_ni"}
+ ]
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device", hier_path: "u_reg_wrap.u_reg" }
+ ],
+ regwidth: "32",
+ param_list: [
+ // Random netlist constants
+ { name: "RndCnstLfsrSeed",
+ desc: "Compile-time random bits for initial LFSR seed",
+ type: "alert_pkg::lfsr_seed_t"
+ randcount: "32",
+ randtype: "data", // randomize randcount databits
+ }
+ { name: "RndCnstLfsrPerm",
+ desc: "Compile-time random permutation for LFSR output",
+ type: "alert_pkg::lfsr_perm_t"
+ randcount: "32",
+ randtype: "perm", // random permutation for randcount elements
+ }
+ // Normal parameters
+ { name: "NAlerts",
+ desc: "Number of alert channels.",
+ type: "int",
+ default: "75",
+ local: "true"
+ },
+ { name: "NLpg",
+ desc: "Number of LPGs.",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+ { name: "NLpgWidth",
+ desc: "Width of LPG ID.",
+ type: "int",
+ default: "6",
+ local: "true"
+ },
+ { name: "LpgMap",
+ desc: '''
+ Defines a mapping from alerts to LPGs.
+ '''
+ type: "logic [NAlerts-1:0][NLpgWidth-1:0]",
+ default: '''
+ {
+ 6'd26,
+ 6'd26,
+ 6'd26,
+ 6'd26,
+ 6'd30,
+ 6'd29,
+ 6'd27,
+ 6'd25,
+ 6'd5,
+ 6'd0,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd23,
+ 6'd23,
+ 6'd22,
+ 6'd22,
+ 6'd21,
+ 6'd20,
+ 6'd20,
+ 6'd19,
+ 6'd18,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd16,
+ 6'd12,
+ 6'd12,
+ 6'd14,
+ 6'd11,
+ 6'd13,
+ 6'd13,
+ 6'd12,
+ 6'd11,
+ 6'd11,
+ 6'd11,
+ 6'd11,
+ 6'd10,
+ 6'd9,
+ 6'd8,
+ 6'd7,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd5,
+ 6'd0,
+ 6'd4,
+ 6'd3,
+ 6'd2,
+ 6'd1,
+ 6'd0,
+ 6'd0,
+ 6'd0,
+ 6'd0,
+ 6'd0
+ }
+ ''',
+ local: "true"
+ },
+ { name: "EscCntDw",
+ desc: "Width of the escalation timer.",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+ { name: "AccuCntDw",
+ desc: "Width of the accumulation counter.",
+ type: "int",
+ default: "16",
+ local: "true"
+ },
+ { name: "AsyncOn",
+ desc: '''
+ Each bit of this parameter corresponds to an escalation channel and
+ defines whether the protocol is synchronous (0) or asynchronous (1).
+ '''
+ type: "logic [NAlerts-1:0]",
+ default: '''
+ {
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1
+ }
+ '''
+ local: "true"
+ },
+ { name: "N_CLASSES",
+ desc: "Number of classes",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ { name: "N_ESC_SEV",
+ desc: "Number of escalation severities",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ { name: "N_PHASES",
+ desc: "Number of escalation phases",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ { name: "N_LOC_ALERT",
+ desc: "Number of local alerts",
+ type: "int",
+ default: "7",
+ local: "true"
+ },
+ { name: "PING_CNT_DW",
+ desc: "Width of ping counter",
+ type: "int",
+ default: "16",
+ local: "true"
+ },
+ { name: "PHASE_DW",
+ desc: "Width of phase ID",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+ { name: "CLASS_DW",
+ desc: "Width of class ID",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_ALERT_PINGFAIL",
+ desc: "Local alert ID for alert ping failure.",
+ type: "int",
+ default: "0",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_ESC_PINGFAIL",
+ desc: "Local alert ID for escalation ping failure.",
+ type: "int",
+ default: "1",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_ALERT_INTEGFAIL",
+ desc: "Local alert ID for alert integrity failure.",
+ type: "int",
+ default: "2",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_ESC_INTEGFAIL",
+ desc: "Local alert ID for escalation integrity failure.",
+ type: "int",
+ default: "3",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_BUS_INTEGFAIL",
+ desc: "Local alert ID for bus integrity failure.",
+ type: "int",
+ default: "4",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR",
+ desc: "Local alert ID for shadow register update error.",
+ type: "int",
+ default: "5",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR",
+ desc: "Local alert ID for shadow register storage error.",
+ type: "int",
+ default: "6",
+ local: "true"
+ },
+ { name: "LOCAL_ALERT_ID_LAST",
+ desc: "Last local alert ID.",
+ type: "int",
+ default: "6",
+ local: "true"
+ },
+ ],
+
+ inter_signal_list: [
+ { struct: "alert_crashdump",
+ type: "uni",
+ name: "crashdump",
+ act: "req",
+ package: "alert_pkg"
+ },
+ { struct: "edn"
+ type: "req_rsp"
+ name: "edn"
+ act: "req"
+ width: "1"
+ package: "edn_pkg"
+ },
+ { struct: "esc_rx"
+ type: "uni"
+ name: "esc_rx"
+ act: "rcv"
+ width: "4", // N_ESC_SEV
+ package: "prim_esc_pkg"
+ },
+ { struct: "esc_tx"
+ type: "uni"
+ name: "esc_tx"
+ act: "req"
+ width: "4", // N_ESC_SEV
+ package: "prim_esc_pkg"
+ },
+ ]
+
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ { name: "CONFIG.SHADOW",
+ desc: "Important CSRs are shadowed."
+ }
+ { name: "PING_TIMER.CONFIG.REGWEN",
+ desc: "The ping timer configuration registers are REGWEN protected."
+ }
+ { name: "ALERT.CONFIG.REGWEN",
+ desc: "The individual alert enables are REGWEN protected."
+ }
+ { name: "ALERT_LOC.CONFIG.REGWEN",
+ desc: "The individual local alert enables are REGWEN protected."
+ }
+ { name: "CLASS.CONFIG.REGWEN",
+ desc: "The class configuration registers are REGWEN protected."
+ }
+ { name: "ALERT.INTERSIG.DIFF",
+ desc: "Differentially encoded alert channels."
+ }
+ { name: "LPG.INTERSIG.MUBI",
+ desc: "LPG signals are encoded with MUBI types."
+ }
+ { name: "ESC.INTERSIG.DIFF",
+ desc: "Differentially encoded escalation channels."
+ }
+ { name: "ALERT_RX.INTERSIG.BKGN_CHK",
+ desc: "Periodic background checks on alert channels (ping mechanism)."
+ }
+ { name: "ESC_TX.INTERSIG.BKGN_CHK",
+ desc: "Periodic background checks on escalation channels (ping mechanism)."
+ }
+ { name: "ESC_RX.INTERSIG.BKGN_CHK",
+ desc: "Escalation receivers can detect absence of periodic ping requests."
+ }
+ { name: "ESC_TIMER.FSM.SPARSE",
+ desc: "Escalation timer FSMs are sparsely encoded."
+ }
+ { name: "PING_TIMER.FSM.SPARSE",
+ desc: "Ping timer FSM is sparsely encoded."
+ }
+ { name: "ESC_TIMER.FSM.LOCAL_ESC",
+ desc: "Escalation timer FSMs move into an invalid state upon local escalation."
+ }
+ { name: "PING_TIMER.FSM.LOCAL_ESC",
+ desc: "Ping timer FSM moves into an invalid state upon local escalation."
+ }
+ { name: "ESC_TIMER.FSM.GLOBAL_ESC",
+ desc: '''
+ The escalation timer FSMs are the root of global escalation,
+ hence if any of them moves into an invalid state by virtue of
+ ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions
+ and thereby global escalation as well.
+ '''
+ }
+ { name: "ACCU.CTR.REDUN",
+ desc: "Accumulator counters employ a cross-counter implementation."
+ }
+ { name: "ESC_TIMER.CTR.REDUN",
+ desc: "Escalation timer counters employ a duplicated counter implementation."
+ }
+ { name: "PING_TIMER.CTR.REDUN",
+ desc: "Ping timer counters employ a duplicated counter implementation."
+ }
+ { name: "PING_TIMER.LFSR.REDUN",
+ desc: "Ping timer LFSR is redundant."
+ }
+ ]
+
+# interrupt registers for the classes
+ interrupt_list: [
+ { name: "classa",
+ desc: '''
+ Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "classb",
+ desc: '''
+ Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "classc",
+ desc: '''
+ Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "classd",
+ desc: '''
+ Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ ],
+
+ registers: [
+# register lock for ping timeout counter
+ { name: "PING_TIMER_REGWEN",
+ desc: '''
+ Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED.
+ ''',
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ {
+ bits: "0",
+ desc: '''
+ When true, the !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED registers can be modified.
+ When false, they become read-only. Defaults true, write one to clear.
+ This should be cleared once the alert handler has been configured and the ping
+ timer mechanism has been kicked off.
+ '''
+ resval: 1,
+ },
+ ]
+ },
+ { name: "PING_TIMEOUT_CYC_SHADOWED",
+ desc: '''
+ Ping timeout cycle count.
+ '''
+ shadowed: "true",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "PING_TIMER_REGWEN",
+ fields: [
+ {
+ bits: "PING_CNT_DW-1:0",
+ resval: 256,
+ desc: '''
+ Timeout value in cycles.
+ If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised.
+ It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater).
+ '''
+ }
+ ]
+ }
+ { name: "PING_TIMER_EN_SHADOWED",
+ desc: '''
+ Ping timer enable.
+ '''
+ shadowed: "true",
+ swaccess: "rw1s",
+ hwaccess: "hro",
+ regwen: "PING_TIMER_REGWEN",
+ fields: [
+ {
+ bits: "0",
+ resval: 0,
+ desc: '''
+ Setting this to 1 enables the ping timer mechanism.
+ This bit cannot be cleared to 0 once it has been set to 1.
+
+ Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.
+ '''
+ }
+ ]
+ }
+# all alerts
+ { multireg: { name: "ALERT_REGWEN",
+ desc: "Register write enable for alert enable bits.",
+ count: "NAlerts",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "hro",
+ hwqe: "false",
+ cname: "alert",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Alert configuration write enable bit.
+ If this is cleared to 0, the corresponding !!ALERT_EN_SHADOWED
+ and !!ALERT_CLASS_SHADOWED bits are not writable anymore.
+
+ Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "ALERT_EN_SHADOWED",
+ desc: '''Enable register for alerts.
+ ''',
+ count: "NAlerts",
+ shadowed: "true",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "ALERT_REGWEN",
+ regwen_multi: "true",
+ cname: "alert",
+ tags: [// Enable `alert_en` might cause top-level escalators to trigger
+ // unexpected reset
+ "excl:CsrAllTests:CsrExclWrite"]
+ fields: [
+ { bits: "0",
+ name: "EN_A",
+ resval: 0
+ desc: '''
+ Alert enable bit.
+
+ Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.
+ '''
+ }
+ ]
+ }
+ },
+ { multireg: { name: "ALERT_CLASS_SHADOWED",
+ desc: '''Class assignment of alerts.
+ ''',
+ count: "NAlerts",
+ shadowed: "true",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "ALERT_REGWEN",
+ regwen_multi: "true",
+ cname: "alert",
+ fields: [
+ {
+ bits: "CLASS_DW-1:0",
+ name: "CLASS_A",
+ resval: 0
+ desc: "Classification ",
+ enum: [
+ { value: "0", name: "ClassA", desc: "" },
+ { value: "1", name: "ClassB", desc: "" },
+ { value: "2", name: "ClassC", desc: "" },
+ { value: "3", name: "ClassD", desc: "" },
+ ]
+ }
+ ]
+ }
+ },
+ { multireg: {
+ name: "ALERT_CAUSE",
+ desc: "Alert Cause Register",
+ count: "NAlerts",
+ compact: "false",
+ cname: "ALERT",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0", name: "A", desc: "Cause bit ", resval: 0}
+ ],
+ }
+ },
+# local alerts
+ { multireg: { name: "LOC_ALERT_REGWEN",
+ desc: "Register write enable for alert enable bits.",
+ count: "N_LOC_ALERT",
+ compact: "false",
+ swaccess: "rw0c",
+ hwaccess: "none",
+ cname: "LOC_ALERT",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Alert configuration write enable bit.
+ If this is cleared to 0, the corresponding !!LOC_ALERT_EN_SHADOWED
+ and !!LOC_ALERT_CLASS_SHADOWED bits are not writable anymore.
+
+ Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.
+ ''',
+ resval: "1",
+ }
+ ]
+ }
+ },
+ { multireg: { name: "LOC_ALERT_EN_SHADOWED",
+ desc:
+ '''
+ Enable register for the local alerts
+ "alert pingfail" (0), "escalation pingfail" (1),
+ "alert integfail" (2), "escalation integfail" (3),
+ "bus integrity failure" (4), "shadow reg update error" (5)
+ and "shadow reg storage error" (6).
+ ''',
+ count: "N_LOC_ALERT",
+ shadowed: "true",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "LOC_ALERT_REGWEN",
+ regwen_multi: "true",
+ cname: "LOC_ALERT",
+ fields: [
+ { bits: "0",
+ name: "EN_LA",
+ resval: 0
+ desc: '''
+ Alert enable bit.
+
+ Note that the alert pinging mechanism will only ping alerts that have been enabled and locked.
+ '''
+ }
+ ]
+ }
+ },
+ { multireg: { name: "LOC_ALERT_CLASS_SHADOWED",
+ desc: '''
+ Class assignment of the local alerts
+ "alert pingfail" (0), "escalation pingfail" (1),
+ "alert integfail" (2), "escalation integfail" (3),
+ "bus integrity failure" (4), "shadow reg update error" (5)
+ and "shadow reg storage error" (6).
+ ''',
+ count: "N_LOC_ALERT",
+ shadowed: "true",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "LOC_ALERT_REGWEN",
+ regwen_multi: "true",
+ cname: "LOC_ALERT",
+ fields: [
+ {
+ bits: "CLASS_DW-1:0",
+ name: "CLASS_LA",
+ resval: 0
+ desc: "Classification ",
+ enum: [
+ { value: "0", name: "ClassA", desc: "" },
+ { value: "1", name: "ClassB", desc: "" },
+ { value: "2", name: "ClassC", desc: "" },
+ { value: "3", name: "ClassD", desc: "" },
+ ]
+ }
+ ]
+ }
+ },
+ { multireg: {
+ name: "LOC_ALERT_CAUSE",
+ desc: '''Alert Cause Register for the local alerts
+ "alert pingfail" (0), "escalation pingfail" (1),
+ "alert integfail" (2), "escalation integfail" (3),
+ "bus integrity failure" (4), "shadow reg update error" (5)
+ and "shadow reg storage error" (6).
+ ''',
+ count: "N_LOC_ALERT",
+ compact: "false",
+ cname: "LOC_ALERT",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ tags: [// Top level CSR automation test, CPU clock is disabled, so escalation response will
+ // not send back to alert handler. This will set loc_alert_cause and could not predict
+ // automatically.
+ // TODO: remove the exclusion after set up top-level esc_receiver_driver
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ fields: [
+ { bits: "0", name: "LA", desc: "Cause bit ", resval: 0}
+ ]
+ }
+ },
+# classes
+
+ { name: "CLASSA_REGWEN",
+ desc: '''
+ Lock bit for Class A configuration.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ desc: '''
+ Class configuration enable bit.
+ If this is cleared to 0, the corresponding class configuration
+ registers cannot be written anymore.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSA_CTRL_SHADOWED",
+ desc: "Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CLASSA_REGWEN",
+ shadowed: "true",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class A. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class A.
+ If true, there is no way to stop the escalation protocol for class A
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for Class A",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for Class A",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for Class A",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for Class A",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determines in which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSA_CLR_REGWEN",
+ desc: '''
+ Clear enable for escalation protocol of Class A alerts.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSA_CTRL_SHADOWED.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ],
+ tags: [// The value of this register is set to false only by hardware, under the condition
+ // that escalation is triggered and the corresponding lock bit is true
+ // Cannot not be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSA_CLR_SHADOWED",
+ desc: '''
+ Clear for escalation protocol of Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ hwqe: "true",
+ shadowed: "true",
+ regwen: "CLASSA_CLR_REGWEN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing 1 to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSA_CLR_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class A. Software can clear this register
+ with a write to !!CLASSA_CLR_SHADOWED register unless !!CLASSA_CLR_REGWEN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "AccuCntDw-1:0" }
+ ],
+ tags: [// The value of this register is determined by how many alerts have been triggered
+ // Cannot be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSA_ACCUM_THRESH_SHADOWED",
+ desc: '''
+ Accumulation threshold value for alert Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "AccuCntDw-1:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class A begins. Note that this
+ register can not be modified if !!CLASSA_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_TIMEOUT_CYC_SHADOWED",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!CLASSA_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_CRASHDUMP_TRIGGER_SHADOWED",
+ desc: '''
+ Crashdump trigger configuration for Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ resval: "0",
+ fields: [
+ { bits: "PHASE_DW-1:0",
+ desc: '''
+ Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation
+ timer states. It is recommended to capture the crashdump upon entering the first escalation phase
+ that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order
+ to prevent spurious alert events from masking the original alert causes.
+ Note that this register can not be modified if !!CLASSA_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_PHASE0_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 0 for Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSA_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE1_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 1 for Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSA_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE2_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 2 for Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSA_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE3_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 3 for Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSA_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSA_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for Class A.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSA_CLR_SHADOWED. Note however that has no effect if !!CLASSA_REGWEN
+ is set to false (either by SW or by HW via the !!CLASSA_CTRL_SHADOWED.LOCK feature).
+ '''
+ }
+ ],
+ tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted
+ // Cannot be auto-predicted so excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSA_STATE",
+ desc: '''
+ Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ],
+ tags: [// The current escalation state cannot be auto-predicted
+ // so this register is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+
+ { name: "CLASSB_REGWEN",
+ desc: '''
+ Lock bit for Class B configuration.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ desc: '''
+ Class configuration enable bit.
+ If this is cleared to 0, the corresponding class configuration
+ registers cannot be written anymore.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSB_CTRL_SHADOWED",
+ desc: "Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CLASSB_REGWEN",
+ shadowed: "true",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class B. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class B.
+ If true, there is no way to stop the escalation protocol for class B
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for Class B",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for Class B",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for Class B",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for Class B",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determines in which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSB_CLR_REGWEN",
+ desc: '''
+ Clear enable for escalation protocol of Class B alerts.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSB_CTRL_SHADOWED.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ],
+ tags: [// The value of this register is set to false only by hardware, under the condition
+ // that escalation is triggered and the corresponding lock bit is true
+ // Cannot not be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSB_CLR_SHADOWED",
+ desc: '''
+ Clear for escalation protocol of Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ hwqe: "true",
+ shadowed: "true",
+ regwen: "CLASSB_CLR_REGWEN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing 1 to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSB_CLR_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class B. Software can clear this register
+ with a write to !!CLASSB_CLR_SHADOWED register unless !!CLASSB_CLR_REGWEN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "AccuCntDw-1:0" }
+ ],
+ tags: [// The value of this register is determined by how many alerts have been triggered
+ // Cannot be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSB_ACCUM_THRESH_SHADOWED",
+ desc: '''
+ Accumulation threshold value for alert Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "AccuCntDw-1:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class B begins. Note that this
+ register can not be modified if !!CLASSB_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_TIMEOUT_CYC_SHADOWED",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!CLASSB_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_CRASHDUMP_TRIGGER_SHADOWED",
+ desc: '''
+ Crashdump trigger configuration for Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ resval: "0",
+ fields: [
+ { bits: "PHASE_DW-1:0",
+ desc: '''
+ Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation
+ timer states. It is recommended to capture the crashdump upon entering the first escalation phase
+ that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order
+ to prevent spurious alert events from masking the original alert causes.
+ Note that this register can not be modified if !!CLASSB_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_PHASE0_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 0 for Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSB_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE1_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 1 for Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSB_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE2_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 2 for Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSB_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE3_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 3 for Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSB_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSB_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for Class B.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSB_CLR_SHADOWED. Note however that has no effect if !!CLASSB_REGWEN
+ is set to false (either by SW or by HW via the !!CLASSB_CTRL_SHADOWED.LOCK feature).
+ '''
+ }
+ ],
+ tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted
+ // Cannot be auto-predicted so excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSB_STATE",
+ desc: '''
+ Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ],
+ tags: [// The current escalation state cannot be auto-predicted
+ // so this register is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+
+ { name: "CLASSC_REGWEN",
+ desc: '''
+ Lock bit for Class C configuration.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ desc: '''
+ Class configuration enable bit.
+ If this is cleared to 0, the corresponding class configuration
+ registers cannot be written anymore.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSC_CTRL_SHADOWED",
+ desc: "Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CLASSC_REGWEN",
+ shadowed: "true",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class C. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class C.
+ If true, there is no way to stop the escalation protocol for class C
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for Class C",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for Class C",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for Class C",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for Class C",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determines in which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSC_CLR_REGWEN",
+ desc: '''
+ Clear enable for escalation protocol of Class C alerts.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSC_CTRL_SHADOWED.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ],
+ tags: [// The value of this register is set to false only by hardware, under the condition
+ // that escalation is triggered and the corresponding lock bit is true
+ // Cannot not be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSC_CLR_SHADOWED",
+ desc: '''
+ Clear for escalation protocol of Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ hwqe: "true",
+ shadowed: "true",
+ regwen: "CLASSC_CLR_REGWEN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing 1 to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSC_CLR_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class C. Software can clear this register
+ with a write to !!CLASSC_CLR_SHADOWED register unless !!CLASSC_CLR_REGWEN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "AccuCntDw-1:0" }
+ ],
+ tags: [// The value of this register is determined by how many alerts have been triggered
+ // Cannot be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSC_ACCUM_THRESH_SHADOWED",
+ desc: '''
+ Accumulation threshold value for alert Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "AccuCntDw-1:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class C begins. Note that this
+ register can not be modified if !!CLASSC_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_TIMEOUT_CYC_SHADOWED",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!CLASSC_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_CRASHDUMP_TRIGGER_SHADOWED",
+ desc: '''
+ Crashdump trigger configuration for Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ resval: "0",
+ fields: [
+ { bits: "PHASE_DW-1:0",
+ desc: '''
+ Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation
+ timer states. It is recommended to capture the crashdump upon entering the first escalation phase
+ that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order
+ to prevent spurious alert events from masking the original alert causes.
+ Note that this register can not be modified if !!CLASSC_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_PHASE0_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 0 for Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSC_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE1_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 1 for Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSC_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE2_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 2 for Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSC_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE3_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 3 for Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSC_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSC_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for Class C.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSC_CLR_SHADOWED. Note however that has no effect if !!CLASSC_REGWEN
+ is set to false (either by SW or by HW via the !!CLASSC_CTRL_SHADOWED.LOCK feature).
+ '''
+ }
+ ],
+ tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted
+ // Cannot be auto-predicted so excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSC_STATE",
+ desc: '''
+ Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ],
+ tags: [// The current escalation state cannot be auto-predicted
+ // so this register is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+
+ { name: "CLASSD_REGWEN",
+ desc: '''
+ Lock bit for Class D configuration.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ desc: '''
+ Class configuration enable bit.
+ If this is cleared to 0, the corresponding class configuration
+ registers cannot be written anymore.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSD_CTRL_SHADOWED",
+ desc: "Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "CLASSD_REGWEN",
+ shadowed: "true",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class D. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class D.
+ If true, there is no way to stop the escalation protocol for class D
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for Class D",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for Class D",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for Class D",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for Class D",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determines in which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSD_CLR_REGWEN",
+ desc: '''
+ Clear enable for escalation protocol of Class D alerts.
+ '''
+ swaccess: "rw0c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSD_CTRL_SHADOWED.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ],
+ tags: [// The value of this register is set to false only by hardware, under the condition
+ // that escalation is triggered and the corresponding lock bit is true
+ // Cannot not be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSD_CLR_SHADOWED",
+ desc: '''
+ Clear for escalation protocol of Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ hwqe: "true",
+ shadowed: "true",
+ regwen: "CLASSD_CLR_REGWEN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing 1 to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSD_CLR_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class D. Software can clear this register
+ with a write to !!CLASSD_CLR_SHADOWED register unless !!CLASSD_CLR_REGWEN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "AccuCntDw-1:0" }
+ ],
+ tags: [// The value of this register is determined by how many alerts have been triggered
+ // Cannot be auto-predicted so it is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSD_ACCUM_THRESH_SHADOWED",
+ desc: '''
+ Accumulation threshold value for alert Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "AccuCntDw-1:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class D begins. Note that this
+ register can not be modified if !!CLASSD_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_TIMEOUT_CYC_SHADOWED",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!CLASSD_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_CRASHDUMP_TRIGGER_SHADOWED",
+ desc: '''
+ Crashdump trigger configuration for Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ resval: "0",
+ fields: [
+ { bits: "PHASE_DW-1:0",
+ desc: '''
+ Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation
+ timer states. It is recommended to capture the crashdump upon entering the first escalation phase
+ that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order
+ to prevent spurious alert events from masking the original alert causes.
+ Note that this register can not be modified if !!CLASSD_REGWEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_PHASE0_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 0 for Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSD_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE1_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 1 for Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSD_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE2_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 2 for Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSD_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE3_CYC_SHADOWED",
+ desc: '''
+ Duration of escalation phase 3 for Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ shadowed: "true",
+ regwen: "CLASSD_REGWEN",
+ fields: [
+ { bits: "EscCntDw-1:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!CLASSD_REGWEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for Class D.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "EscCntDw-1:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSD_CLR_SHADOWED. Note however that has no effect if !!CLASSD_REGWEN
+ is set to false (either by SW or by HW via the !!CLASSD_CTRL_SHADOWED.LOCK feature).
+ '''
+ }
+ ],
+ tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted
+ // Cannot be auto-predicted so excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ { name: "CLASSD_STATE",
+ desc: '''
+ Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ],
+ tags: [// The current escalation state cannot be auto-predicted
+ // so this register is excluded from read check
+ "excl:CsrNonInitTests:CsrExclWriteCheck"]
+ },
+ ],
+}
diff --git a/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson
new file mode 100644
index 0000000..86dcdc7
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson
@@ -0,0 +1,156 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../alert_handler/data/alert_handler.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../alert_handler/data/alert_handler_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ stage: V2S
+ tests: ["alert_handler_tl_intg_err"]
+ }
+ {
+ name: sec_cm_config_shadow
+ desc: "Verify the countermeasure(s) CONFIG.SHADOW."
+ stage: V2S
+ tests: ["alert_handler_shadow_reg_errors"]
+ }
+ {
+ name: sec_cm_ping_timer_config_regwen
+ desc: "Verify the countermeasure(s) PING_TIMER.CONFIG.REGWEN."
+ stage: V2S
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: sec_cm_alert_config_regwen
+ desc: "Verify the countermeasure(s) ALERT.CONFIG.REGWEN."
+ stage: V2S
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: sec_cm_alert_loc_config_regwen
+ desc: "Verify the countermeasure(s) ALERT_LOC.CONFIG.REGWEN."
+ stage: V2S
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: sec_cm_class_config_regwen
+ desc: "Verify the countermeasure(s) CLASS.CONFIG.REGWEN."
+ stage: V2S
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: sec_cm_alert_intersig_diff
+ desc: "Verify the countermeasure(s) ALERT.INTERSIG.DIFF."
+ stage: V2S
+ tests: ["alert_handler_sig_int_fail"]
+ }
+ {
+ name: sec_cm_lpg_intersig_mubi
+ desc: "Verify the countermeasure(s) LPG.INTERSIG.MUBI."
+ stage: V2S
+ tests: ["alert_handler_lpg"]
+ }
+ {
+ name: sec_cm_esc_intersig_diff
+ desc: "Verify the countermeasure(s) ESC.INTERSIG.DIFF."
+ stage: V2S
+ tests: ["alert_handler_sig_int_fail"]
+ }
+ {
+ name: sec_cm_alert_rx_intersig_bkgn_chk
+ desc: "Verify the countermeasure(s) ALERT_RX.INTERSIG.BKGN_CHK."
+ stage: V2S
+ tests: ["alert_handler_entropy"]
+ }
+ {
+ name: sec_cm_esc_tx_intersig_bkgn_chk
+ desc: "Verify the countermeasure(s) ESC_TX.INTERSIG.BKGN_CHK."
+ stage: V2S
+ tests: ["alert_handler_entropy"]
+ }
+ {
+ name: sec_cm_esc_rx_intersig_bkgn_chk
+ desc: "Verify the countermeasure(s) ESC_RX.INTERSIG.BKGN_CHK."
+ stage: V2S
+ // This test entry is only valid with prim_esc_receiver module, which is not included in the
+ // alert_handler testbench. Thus this test point will be checked in `prim_esc` testbench and
+ // top-level testbench.
+ tests: ["N/A"]
+ }
+ {
+ name: sec_cm_esc_timer_fsm_sparse
+ desc: "Verify the countermeasure(s) ESC_TIMER.FSM.SPARSE."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_ping_timer_fsm_sparse
+ desc: "Verify the countermeasure(s) PING_TIMER.FSM.SPARSE."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_esc_timer_fsm_local_esc
+ desc: "Verify the countermeasure(s) ESC_TIMER.FSM.LOCAL_ESC."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_ping_timer_fsm_local_esc
+ desc: "Verify the countermeasure(s) PING_TIMER.FSM.LOCAL_ESC."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_esc_timer_fsm_global_esc
+ desc: "Verify the countermeasure(s) ESC_TIMER.FSM.GLOBAL_ESC."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_accu_ctr_redun
+ desc: "Verify the countermeasure(s) ACCU.CTR.REDUN."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_esc_timer_ctr_redun
+ desc: "Verify the countermeasure(s) ESC_TIMER.CTR.REDUN."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_ping_timer_ctr_redun
+ desc: "Verify the countermeasure(s) PING_TIMER.CTR.REDUN."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ {
+ name: sec_cm_ping_timer_lfsr_redun
+ desc: "Verify the countermeasure(s) PING_TIMER.LFSR.REDUN."
+ stage: V2S
+ tests: ["alert_handler_sec_cm"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_testplan.hjson b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_testplan.hjson
new file mode 100644
index 0000000..48ab857
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/data/alert_handler_testplan.hjson
@@ -0,0 +1,285 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "alert_handler"
+ import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ "hw/dv/sv/alert_esc_agent/data/alert_agent_basic_testplan.hjson",
+ "hw/dv/sv/alert_esc_agent/data/alert_agent_additional_testplan.hjson",
+ "hw/dv/sv/alert_esc_agent/data/esc_agent_basic_testplan.hjson",
+ "hw/dv/sv/alert_esc_agent/data/esc_agent_additional_testplan.hjson",
+ // Generated in IP gen area (hw/{top}/ip_autogen).
+ "alert_handler_sec_cm_testplan.hjson"]
+ testpoints: [
+ {
+ name: smoke
+ desc: '''
+ - Alert_handler smoke test with one class configured that escalates through all
+ phases after one alert has been triggered
+ - Check interrupt pins, alert cause CSR values, escalation pings, and crashdump_o
+ output values
+ - Support both synchronous and asynchronous settings
+ '''
+ stage: V1
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: esc_accum
+ desc: '''
+ Based on the smoke test, this test will focus on testing the escalation accumulation
+ feature. So all the escalations in the test will be triggered by alert accumulation.
+ '''
+ stage: V2
+ tests: ["alert_handler_esc_alert_accum"]
+ }
+ {
+ name: esc_timeout
+ desc: '''
+ Based on the smoke test, this test will focus on testing the escalation timeout
+ feature. So all the escalations in the test will be triggered by interrupt timeout.
+ '''
+ stage: V2
+ tests: ["alert_handler_esc_intr_timeout"]
+ }
+ {
+ name: entropy
+ desc: '''
+ Based on the smoke test, this test enables ping testing, and check if the ping feature
+ correctly pings all devices within certain period of time.
+ '''
+ stage: V2
+ tests: ["alert_handler_entropy"]
+ }
+ {
+ name: sig_int_fail
+ desc: '''
+ This test will randomly inject differential pair failures on alert tx/rx pairs and the
+ escalator tx/rx pairs. Then check if integrity failure alert is triggered and
+ escalated.
+ '''
+ stage: V2
+ tests: ["alert_handler_sig_int_fail"]
+ }
+ {
+ name: clk_skew
+ desc: '''
+ This test will randomly inject clock skew within the differential pairs. Then check no
+ alert is raised.
+ '''
+ stage: V2
+ tests: ["alert_handler_smoke"]
+ }
+ {
+ name: random_alerts
+ desc: "Input random alerts and randomly write phase cycles."
+ stage: V2
+ tests: ["alert_handler_random_alerts"]
+ }
+ {
+ name: random_classes
+ desc: "Based on random_alerts test, this test will also randomly enable interrupt classes."
+ stage: V2
+ tests: ["alert_handler_random_classes"]
+ }
+ {
+ name: ping_timeout
+ desc: '''
+ Based on entropy test, this test request alert_sender and esc_receiver drivers to
+ randomly create ping requests timeout stimulus.
+
+ Checks:
+ - Verify interrupt pin and states.
+ - Verify alert and local alert causes.
+ - Verify escalation states and counts.
+ '''
+ stage: V2
+ tests: ["alert_handler_ping_timeout"]
+ }
+ {
+ name: lpg
+ desc: '''
+ Test alert_handler low_power_group(lpg) request.
+
+ Stimulus:
+ - Randomly enabled alert_receivers' `alert_en` but disable their ping response.
+ - Turn on their low-power control by either set `lpg_cg_en_i` or `lpg_rst_en_i`.
+ Or pause the alert_handler's clk input for a random period of time.
+ - Enable alert ping timeout local alert.
+ - Run alert_handler_entropy_vseq.
+
+ Checks:
+ - Expect no ping timeout error because the alert_receivers are disabled via low-power
+ group, or because alert_handler's clk input is paused due to sleep mode.
+ '''
+ stage: V2
+ tests: ["alert_handler_lpg", "alert_handler_lpg_stub_clk"]
+ }
+ {
+ name: stress_all
+ desc: '''
+ Combine above sequences in one test to run sequentially with the following exclusions:
+ - CSR sequences: scoreboard disabled
+ - Ping_corner_cases sequence: included reset in the sequence
+ '''
+ stage: V2
+ tests: ["alert_handler_stress_all"]
+ }
+ {
+ name: alert_handler_entropy_stress_test
+ desc: '''
+ Stress the alert_handler's entropy request and make sure there is no spurious alert.
+
+ Stimulus:
+ - Randomly force the `wait_cyc_mask_i` to a legal value to stress the ping requests.
+ - Wait for all alerts at least being pinged for a few times.
+ Checks:
+ - Check alert_cause and loc_alert_cause registers to make sure there is no spurious
+ alert being fired.
+ '''
+ stage: V2
+ tests: ["alert_handler_entropy_stress"]
+ }
+
+ {
+ name: alert_handler_alert_accum_saturation
+ desc: '''
+ This sequence forces all four alert classes' accumulate counters to a large value that
+ is close to the max saturation value.
+ Then the sequence triggers alerts until the count saturates.
+
+ Checks:
+ - Check `accum_cnt` register does not overflow, but stays at the max value.
+ - Check the correct interrupt fires if even the count saturates.
+ '''
+ stage: V2
+ tests: ["alert_handler_alert_accum_saturation"]
+ }
+ ]
+
+ covergroups: [
+ {
+ name: accum_cnt_cg
+ desc: '''Covers escalation due to accumulated alerts.
+
+ - Collect the threshold of accumulated alerts.
+ - Collect which alert_class exceeds the accumulated count.
+ - Cross the above coverpoints.
+ '''
+ }
+ {
+ name: intr_timeout_cnt_cg
+ desc: '''Covers escalation due to interrupt timeout.
+
+ - Collect the threshold of interrupt timeout cycles.
+ - Collect which alert_class exceeds the timeout threshold.
+ - Cross the above coverpoints.
+ '''
+ }
+ {
+ name: esc_sig_length_cg
+ desc: '''Covers escalation signal length for each escalation signal.'''
+ }
+ {
+ name: clear_intr_cnt_cg
+ desc: '''Covers interrupt counter being cleared by class_clr_shadowed register.'''
+ }
+ {
+ name: clear_esc_cnt_cg
+ desc: '''Covers escalation counter being cleared by class_clr_shadowed register.'''
+ }
+ {
+ name: alert_cause_cg
+ desc: '''Covers alert_cause register and related items.
+
+ - Collect which alert causes the alert_cause register to set.
+ - Collect the alert_class that this alert belongs to.
+ - Cross the above coverpoints.
+ '''
+ }
+ {
+ name: alert_loc_alert_cause_cg
+ desc: '''Covers loc_alert_cause register regarding alert.
+
+ - Collect two loc_alert causes: alert_ping_fail and alert_integrity_fail.
+ - Collect which alert triggers this loc_alert.
+ - Collect the alert_class that this local alert belongs to.
+ - Cross the first coverpoint with the rest of the coverpoints.
+ '''
+ }
+ {
+ name: esc_loc_alert_cause_cg
+ desc: '''Covers loc_alert_cause register regarding escalation.
+
+ - Collect two loc_alert causes: esc_ping_fail and esc_integrity_fail.
+ - Collect which escalation triggers this loc_alert.
+ - Collect the alert_class that this local alert belongs to.
+ - Cross the first coverpoint with the rest of the coverpoints.
+ '''
+ }
+ {
+ name: crashdump_trigger_cg
+ desc: '''Covers which phase triggers crashdump.'''
+ }
+ {
+ name: alert_en_regwen_cg
+ desc: '''Covers if regwen is locked for alert_en registers.'''
+ }
+ {
+ name: alert_class_regwen_cg
+ desc: '''Covers if regwen is locked for alert_class registers.'''
+ }
+ {
+ name: loc_alert_en_regwen_cg
+ desc: '''Covers if regwen is locked for loc_alert_en registers.'''
+ }
+ {
+ name: loc_alert_class_regwen_cg
+ desc: '''Covers if regwen is locked for loc_alert_class registers.'''
+ }
+ {
+ name: class_ctrl_regwen_cg
+ desc: '''Covers if regwen is locked for class_ctrl registers.'''
+ }
+ {
+ name: class_clr_regwen_cg
+ desc: '''Covers if regwen is locked for class_clr registers.'''
+ }
+ {
+ name: class_accum_thresh_regwen_cg
+ desc: '''Covers if regwen is locked for class_accum_thresh registers.'''
+ }
+ {
+ name: class_timeout_cyc_regwen_cg
+ desc: '''Covers if regwen is locked for class_timeout_cyc registers.'''
+ }
+ {
+ name: class_crashdump_trigger_regwen_cg
+ desc: '''Covers if regwen is locked for class_crashdump_trigger registers.'''
+ }
+ {
+ name: class_phase_cyc_regwen_cg
+ desc: '''Covers if regwen is locked for class_phase_cyc registers.'''
+ }
+ {
+ name: num_edn_reqs_cg
+ desc: '''Covers if simulation runs long enough to capture more than five EDN requests.'''
+ }
+ {
+ name: num_checked_pings_cg
+ desc: '''Covers if simulation runs long enough to capture more than twenty ping requests.'''
+ }
+ {
+ name: cycles_bwtween_pings_cg
+ desc: '''Covers how many cycles are there between two ping requests.'''
+ }
+ {
+ name: alert_ping_with_lpg_wrap_cg
+ desc: '''Covers ping requests are initiated with LPG enabled or disabled.'''
+ }
+
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/alert_handler/data/top_sencha_alert_handler.ipconfig.hjson b/hw/top_sencha/ip_autogen/alert_handler/data/top_sencha_alert_handler.ipconfig.hjson
new file mode 100644
index 0000000..b0de2cc
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/data/top_sencha_alert_handler.ipconfig.hjson
@@ -0,0 +1,170 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ instance_name: top_sencha_alert_handler
+ param_values:
+ {
+ n_alerts: 75
+ esc_cnt_dw: 32
+ accu_cnt_dw: 16
+ async_on:
+ [
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ 1'b1
+ ]
+ n_classes: 4
+ n_lpg: 32
+ lpg_map:
+ [
+ 6'd0
+ 6'd0
+ 6'd0
+ 6'd0
+ 6'd0
+ 6'd1
+ 6'd2
+ 6'd3
+ 6'd4
+ 6'd0
+ 6'd5
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd6
+ 6'd7
+ 6'd8
+ 6'd9
+ 6'd10
+ 6'd11
+ 6'd11
+ 6'd11
+ 6'd11
+ 6'd12
+ 6'd13
+ 6'd13
+ 6'd11
+ 6'd14
+ 6'd12
+ 6'd12
+ 6'd16
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd18
+ 6'd19
+ 6'd20
+ 6'd20
+ 6'd21
+ 6'd22
+ 6'd22
+ 6'd23
+ 6'd23
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd19
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd17
+ 6'd0
+ 6'd5
+ 6'd25
+ 6'd27
+ 6'd29
+ 6'd30
+ 6'd26
+ 6'd26
+ 6'd26
+ 6'd26
+ ]
+ }
+}
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/README.md b/hw/top_sencha/ip_autogen/alert_handler/dv/README.md
new file mode 100644
index 0000000..2016a09
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/README.md
@@ -0,0 +1,120 @@
+# ALERT_HANDLER DV document
+
+## Goals
+* **DV**
+ * Verify all ALERT_HANDLER IP features by running dynamic simulations with a SV/UVM based testbench
+ * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules
+ * Verify transmitter and receiver pairs for alert (/hw/ip/prim/dv/prim_alert) and escalation (/hw/ip/prim/dv/prim_esc) via direct stimulus.
+* **FPV**
+ * Verify TileLink device protocol compliance with an SVA based testbench
+ * Verify transmitter and receiver pairs for alert and escalator
+ * Verify alert_handler_esc_timer and alert_handler_ping_timer
+
+## Current status
+* [Design & verification stage](../../../README.md)
+ * [HW development stages](../../../../doc/project_governance/development_stages.md)
+* [Simulation results](https://reports.opentitan.org/hw/top_earlgrey/ip_autogen/alert_handler/dv/latest/report.html)
+
+## Design features
+For detailed information on ALERT_HANDLER design features, please see the [ALERT_HANDLER HWIP technical specification](../README.md).
+
+## Testbench architecture
+ALERT_HANDLER testbench has been constructed based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md).
+
+### Block diagram
+
+
+### Top level testbench
+Top level testbench is located at `hw/ip/alert_handler/dv/tb/tb.sv`. It instantiates the ALERT_HANDLER DUT module `hw/ip/alert_handler/rtl/alert_handler.sv`.
+In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
+* [Clock and reset interface](../../../dv/sv/common_ifs/README.md)
+* [TileLink host interface](../../../dv/sv/tl_agent/README.md)
+* ALERT_HANDLER IOs
+* Alerts and escalations([`alert_esc_if`](../../../dv/sv/alert_esc_agent/README.md))
+* Interrupts ([`pins_if`](../../../dv/sv/common_ifs/README.md))
+* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md))
+
+The alert_handler testbench environment can be reused in chip level testing.
+
+### Common DV utility components
+The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
+* [dv_utils_pkg](../../../dv/sv/dv_utils/README.md)
+* [csr_utils_pkg](../../../dv/sv/csr_utils/README.md)
+
+### Global types & methods
+All common types and methods defined at the package level can be found in
+`alert_handler_env_pkg`. Some of them in use are:
+```systemverilog
+ parameter uint NUM_MAX_ESC_SEV = 8;
+```
+
+### TL_agent
+ALERT_HANDLER testbench instantiates (already handled in CIP base env) [tl_agent](../../../dv/sv/tl_agent/README.md)
+which provides the ability to drive and independently monitor random traffic via
+TL host interface into ALERT_HANDLER device.
+
+### ALERT_ESC Agent
+[ALERT_ESC agent](../../../dv/sv/alert_esc_agent/README.md) is used to drive and monitor transmitter and receiver pairs for the alerts and escalators.
+Alert_handler DUT includes alert_receivers and esc_senders, so the alert_esc agent will drive output signals of the alert_senders and esc_receivers.
+
+### UVM RAL Model
+The ALERT_HANDLER RAL model is created with the [`ralgen`](../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage.
+
+It can be created manually by invoking [`regtool`](../../../../util/reggen/doc/setup_and_use.md).
+
+### Stimulus strategy
+#### Test sequences
+All test sequences reside in `hw/ip/alert_handler/dv/env/seq_lib`.
+The `alert_handler_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
+All test sequences are extended from `alert_handler_base_vseq`.
+It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
+Some of the most commonly used tasks / functions are as follows:
+* alert_handler_init: Configure alert_handler DUT by writing to `intr_en`, `alert_en_shadowed_*`, `alert_class_shadowed_*`, `loc_alert_en_shadowed_*`, `loc_alert_class_shadowed_*` registers.
+* drive_alert: Drive alert_tx signal pairs through `alert_sender_driver`.
+* drive_esc_rsp: Drive esc_rx signal pairs through `esc_receiver_driver`.
+* read_ecs_status: Readout registers that reflect escalation status, including `classa/b/c/d_accum_cnt`, `classa/b/c/d_esc_cnt`, and `classa/b/c/d_state`.
+* wait_alert_handshake_done: Wait for alert_rx/tx handshake to finish. If the alert's low-power-group(LPG) is enabled, immediately return.
+* wait_esc_handshake_done: Wait for esc_rx/tx handshake to finish by reading `class*_state` registers and check esc_rx/tx signals.
+* set_alert_lpg: Given alert index, find the linked LPG group and enabled the LPG group by driving `lpg_cg_en` or `lpg_rst_en` to Mubi4True.
+* run_esc_rsp_seq_nonblocking: A non-blocking sequence to drive `esc_tx` when received escalation or escalation-ping requests.
+* run_alert_ping_rsp_seq_nonblocking: A non-blocking sequence to drive `alert_rx` when received alert-ping requests.
+
+#### Functional coverage
+To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
+The detailed covergroups are documented under alert_handler [testplan](#testplan).
+
+### Self-checking strategy
+#### Scoreboard
+The `alert_handler_scoreboard` is primarily used for end to end checking.
+It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
+* tl_a_chan_fifo: tl address channel
+* tl_d_chan_fifo: tl data channel
+* alert_fifo: An array of `alert_fifo` that connects to corresponding alert_monitors
+* esc_fifo: An array of `esc_fifo` that connects to corresponding esc_monitors
+
+Alert_handler scoreboard monitors all valid CSR registers, alert handshakes, and escalation handshakes.
+To ensure certain alert, interrupt, or escalation signals are triggered at the expected time, the alert_handler scoreboard implemented a few counters:
+* intr_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of clock cycles that the interrupt bit stays high.
+ If the stored number is larger than the `timeout_cyc` registers, the corresponding escalation is expected to be triggered
+* accum_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of alerts triggered under the same class.
+ If the stored number is larger than the `accum_threshold` registers, the corresponding escalation is expected to be triggered
+* esc_cnter_per_signal[NUM_ESC_SIGNALS]: Count number of clock cycles that each escalation signal stays high.
+ Compare the counter against `phase_cyc` registers
+
+The alert_handler scoreboard is parameterized to support different number of classes, alert pairs, and escalation pairs.
+
+#### Assertions
+* TLUL assertions: The `tb/alert_handler_bind.sv` binds the `tlul_assert` [assertions](../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
+* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
+
+## Building and running tests
+We are using our in-house developed [regression tool](../../../../util/dvsim/README.md) for building and running our tests and regressions.
+Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
+Here's how to run a smoke test:
+```console
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke
+```
+In this run command, $CHIP can be top_earlgrey, etc.
+
+## Testplan
+[Testplan](../data/alert_handler_testplan.hjson)
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim.core
new file mode 100644
index 0000000..8201c15
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim.core
@@ -0,0 +1,39 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler_sim:0.1
+description: "ALERT_HANDLER DV sim target"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:opentitan:top_sencha_alert_handler:0.1
+ file_type: systemVerilogSource
+
+ files_dv:
+ depend:
+ - lowrisc:dv:ralgen
+ - lowrisc:dv:alert_handler_tb
+ - lowrisc:dv:alert_handler_cov
+ - lowrisc:opentitan:top_sencha_alert_handler_sva:0.1
+ file_type: systemVerilogSource
+
+generate:
+ ral:
+ generator: ralgen
+ parameters:
+ name: alert_handler
+ ip_hjson: ../data/alert_handler.hjson
+
+targets:
+ sim: &sim_target
+ toplevel: tb
+ filesets:
+ - files_rtl
+ - files_dv
+ generate:
+ - ral
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson b/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson
new file mode 100644
index 0000000..218cb69
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson
@@ -0,0 +1,153 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: alert_handler
+
+ // Top level dut name (sv module).
+ dut: alert_handler
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Simulator used to sign off this block
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:opentitan:top_sencha_alert_handler_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{self_dir}/../data/alert_handler_testplan.hjson"
+
+ // Import additional common sim cfg files.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+ // Common CIP test lists
+ "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
+
+ // Add additional tops for simulation.
+ sim_tops: ["alert_handler_bind",
+ "alert_handler_cov_bind",
+ "sec_cm_prim_sparse_fsm_flop_bind",
+ "sec_cm_prim_count_bind",
+ "sec_cm_prim_double_lfsr_bind",
+ "sec_cm_prim_onehot_check_bind"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ overrides: [
+ {
+ name: cover_reg_top_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/top_earlgrey/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg"
+ }
+ ]
+
+ // Add ALERT_HANDLER specific exclusion files.
+ vcs_cov_excl_files: ["{self_dir}/cov/alert_handler_cov_excl.el",
+ "{self_dir}/cov/alert_handler_cov_unr.el"]
+
+ // Default UVM test and seq class name.
+ uvm_test: alert_handler_base_test
+ uvm_test_seq: alert_handler_base_vseq
+
+ // List of test specifications.
+ tests: [
+ {
+ name: alert_handler_smoke
+ uvm_test_seq: alert_handler_smoke_vseq
+ }
+
+ {
+ name: alert_handler_random_alerts
+ uvm_test_seq: alert_handler_random_alerts_vseq
+ }
+
+ {
+ name: alert_handler_random_classes
+ uvm_test_seq: alert_handler_random_classes_vseq
+ }
+
+ {
+ name: alert_handler_esc_intr_timeout
+ uvm_test_seq: alert_handler_esc_intr_timeout_vseq
+ }
+
+ {
+ name: alert_handler_esc_alert_accum
+ uvm_test_seq: alert_handler_esc_alert_accum_vseq
+ }
+
+ {
+ name: alert_handler_sig_int_fail
+ uvm_test_seq: alert_handler_sig_int_fail_vseq
+ }
+
+ {
+ name: alert_handler_entropy
+ uvm_test_seq: alert_handler_entropy_vseq
+ run_opts: ["+test_timeout_ns=1_000_000_000"]
+ }
+
+ {
+ name: alert_handler_ping_timeout
+ uvm_test_seq: alert_handler_ping_timeout_vseq
+ run_opts: ["+test_timeout_ns=1_000_000_000"]
+ }
+
+ {
+ name: alert_handler_lpg
+ uvm_test_seq: alert_handler_lpg_vseq
+ run_opts: ["+test_timeout_ns=1_000_000_000"]
+ }
+
+ {
+ name: alert_handler_lpg_stub_clk
+ uvm_test_seq: alert_handler_lpg_stub_clk_vseq
+ run_opts: ["+test_timeout_ns=1_000_000_000"]
+ }
+
+ {
+ name: alert_handler_entropy_stress
+ uvm_test_seq: alert_handler_entropy_stress_vseq
+ // This sequence forces signal `wait_cyc_mask_i` to a much smaller value.
+ // So all the timings are not accurate and we need to disable the scb.
+ run_opts: ["+en_scb=0"]
+ reseed: 20
+ }
+
+ {
+ name: alert_handler_stress_all
+ run_opts: ["+test_timeout_ns=15_000_000_000"]
+ }
+
+ {
+ name: alert_handler_shadow_reg_errors_with_csr_rw
+ run_opts: ["+test_timeout_ns=500_000_000"]
+ run_timeout_mins: 120
+ }
+
+ {
+ name: alert_handler_alert_accum_saturation
+ uvm_test_seq: alert_handler_alert_accum_saturation_vseq
+ // This is a direct sequence that forces the accum_cnt to a large number, so does not support
+ // scb checkings.
+ run_opts: ["+en_scb=0"]
+ reseed: 20
+ }
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ name: smoke
+ tests: ["alert_handler_smoke"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core
new file mode 100644
index 0000000..53ecb54
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:alert_handler_cov"
+description: "ALERT_HANDLER cov bind files"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:ip:alert_handler_component # import alert_pkg
+ - lowrisc:dv:dv_utils
+ files:
+ - alert_handler_cov_bind.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv
new file mode 100644
index 0000000..dd9e5c7
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv
@@ -0,0 +1,19 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Binds ALERT_HANDLER functional coverage interafaces to the top level ALERT_HANDLER module.
+
+module alert_handler_cov_bind;
+ import alert_pkg::*;
+
+ bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_cg_en_cov_if (
+ .rst_ni (rst_ni),
+ .mubis (lpg_cg_en_i)
+ );
+
+ bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_rst_en_cov_if (
+ .rst_ni (rst_ni),
+ .mubis (lpg_rst_en_i)
+ );
+endmodule : alert_handler_cov_bind
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el
new file mode 100644
index 0000000..ec22f6a
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el
@@ -0,0 +1,163 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: chencindy
+// Format Version: 2
+// Date: Wed Nov 30 12:30:55 2022
+// ExclMode: default
+//==================================================
+CHECKSUM: "951561765 3328643058"
+INSTANCE: tb.dut.u_ping_timer
+Fsm state_q "2842986776"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition AlertPingSt->FsmErrorSt "369->366"
+Fsm state_q "2842986776"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition EscWaitSt->FsmErrorSt "182->366"
+Fsm state_q "2842986776"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition EscPingSt->FsmErrorSt "29->366"
+Fsm state_q "2842986776"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition InitSt->FsmErrorSt "203->366"
+CHECKSUM: "3358687906 2811042798"
+INSTANCE: tb.dut.gen_classes[0].u_esc_timer
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase1St->FsmErrorSt "340->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase2St->FsmErrorSt "25->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase3St->FsmErrorSt "609->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TerminalSt->FsmErrorSt "895->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TimeoutSt->FsmErrorSt "38->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase0St->FsmErrorSt "901->488"
+CHECKSUM: "3358687906 2811042798"
+INSTANCE: tb.dut.gen_classes[1].u_esc_timer
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase0St->FsmErrorSt "901->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TerminalSt->FsmErrorSt "895->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TimeoutSt->FsmErrorSt "38->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase3St->FsmErrorSt "609->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase2St->FsmErrorSt "25->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase1St->FsmErrorSt "340->488"
+CHECKSUM: "3358687906 2811042798"
+INSTANCE: tb.dut.gen_classes[2].u_esc_timer
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase0St->FsmErrorSt "901->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TimeoutSt->FsmErrorSt "38->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TerminalSt->FsmErrorSt "895->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase3St->FsmErrorSt "609->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase2St->FsmErrorSt "25->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase1St->FsmErrorSt "340->488"
+CHECKSUM: "3358687906 2811042798"
+INSTANCE: tb.dut.gen_classes[3].u_esc_timer
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase1St->FsmErrorSt "340->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase2St->FsmErrorSt "25->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase3St->FsmErrorSt "609->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TerminalSt->FsmErrorSt "895->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition TimeoutSt->FsmErrorSt "38->488"
+Fsm state_q "3850519017"
+ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV."
+Transition Phase0St->FsmErrorSt "901->488"
+CHECKSUM: "1268953672 3214085926"
+INSTANCE: tb.dut
+ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000."
+Toggle crashdump_o.class_esc_cnt [1][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt"
+ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000."
+Toggle crashdump_o.class_esc_cnt [2][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt"
+ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000."
+Toggle crashdump_o.class_esc_cnt [3][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt"
+ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000."
+Toggle crashdump_o.class_esc_cnt [0][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.u_ping_timer.u_prim_count_esc_cnt
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.u_ping_timer.u_prim_count_cnt
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.gen_classes[0].u_accu.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.gen_classes[1].u_accu.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.gen_classes[2].u_accu.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 1403235006"
+INSTANCE: tb.dut.gen_classes[3].u_accu.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[15:0]"
+CHECKSUM: "2301929872 277894862"
+INSTANCE: tb.dut.gen_classes[0].u_esc_timer.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle set_cnt_i "net set_cnt_i[31:0]"
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[31:0]"
+CHECKSUM: "2301929872 277894862"
+INSTANCE: tb.dut.gen_classes[1].u_esc_timer.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle set_cnt_i "net set_cnt_i[31:0]"
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[31:0]"
+CHECKSUM: "2301929872 277894862"
+INSTANCE: tb.dut.gen_classes[2].u_esc_timer.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle set_cnt_i "net set_cnt_i[31:0]"
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[31:0]"
+CHECKSUM: "2301929872 277894862"
+INSTANCE: tb.dut.gen_classes[3].u_esc_timer.u_prim_count
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle step_i "net step_i[31:0]"
+ANNOTATION: "[UNR]: Tied off to 1."
+Toggle set_cnt_i "net set_cnt_i[31:0]"
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el
new file mode 100644
index 0000000..a30f31f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el
@@ -0,0 +1,934 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This is auto-generated from the UNR tool.
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: chencindy
+// Format Version: 2
+// Date: Fri Jan 20 02:18:45 2023
+// ExclMode: default
+//==================================================
+CHECKSUM: "1549052440 1514362506"
+INSTANCE: tb.dut.u_alert_handler_lpg_ctrl
+ANNOTATION: "VC_COV_UNR"
+Block 30 "3894967986" "unused_lpg_init_trig ^= (^lpg_init_trig[k]);"
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_44
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_45
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_46
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_47
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_48
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_49
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_50
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_51
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_52
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_53
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_54
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_55
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_56
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_57
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_58
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_59
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_60
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_61
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_62
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_63
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_64
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_4
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_5
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_6
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_7
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_8
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_9
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_10
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_11
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_12
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_13
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_14
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_15
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_16
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_17
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_18
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_19
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_20
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_21
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_22
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_23
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_24
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_25
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_26
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_27
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_28
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_29
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_30
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_31
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_32
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_33
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_34
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_35
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_36
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_37
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_38
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_39
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_40
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_41
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_42
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_43
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_44
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_45
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_46
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_47
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_48
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_49
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_50
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_51
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_52
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_53
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_54
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_55
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_56
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_57
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_58
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_59
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_60
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_61
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_62
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_63
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_class_shadowed_64
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_4
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_5
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "1430476793 1594399761"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
+ANNOTATION: "VC_COV_UNR"
+Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110")
+CHECKSUM: "74367784 3785313510"
+INSTANCE: tb.dut.u_reg_wrap.u_reg.u_reg_if
+ANNOTATION: "VC_COV_UNR"
+Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000")
+CHECKSUM: "4013022403 2890184979"
+INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo
+ANNOTATION: "VC_COV_UNR"
+Condition 9 "398812176" "(gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q) 1 -1" (2 "1")
+ANNOTATION: "VC_COV_UNR"
+Condition 11 "855985636" "(gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q) 1 -1" (2 "1")
+ANNOTATION: "VC_COV_UNR"
+Condition 16 "1428458034" "(( ! (depth_q == '0) ) && ((!clr_q))) 1 -1" (2 "10")
+CHECKSUM: "3358687906 1917555973"
+INSTANCE: tb.dut.gen_classes[0].u_esc_timer
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+ANNOTATION: "VC_COV_UNR"
+Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+CHECKSUM: "3358687906 1917555973"
+INSTANCE: tb.dut.gen_classes[1].u_esc_timer
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+ANNOTATION: "VC_COV_UNR"
+Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+CHECKSUM: "3358687906 1917555973"
+INSTANCE: tb.dut.gen_classes[2].u_esc_timer
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+ANNOTATION: "VC_COV_UNR"
+Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+CHECKSUM: "3358687906 1917555973"
+INSTANCE: tb.dut.gen_classes[3].u_esc_timer
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+ANNOTATION: "VC_COV_UNR"
+Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101")
+CHECKSUM: "4013022403 749591850"
+INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3339891226" "clear_status" (2) "clear_status 0,0,1"
+ANNOTATION: "VC_COV_UNR"
+Branch 1 "3667320634" "clear_status" (1) "clear_status 0,1"
+CHECKSUM: "1549052440 851307434"
+INSTANCE: tb.dut.u_alert_handler_lpg_ctrl
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3440992731" "(!lpg_used)" (0) "(!lpg_used) 1"
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg
new file mode 100644
index 0000000..ee23ca6
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Limits coverage collection only to the *_reg_top module and the TL interface
+// of the DUT.
+// Alert_handler wraps alert_handler_reg_top with alert_handler_reg_wrap, so this overwrites the
+// common cfg file to include the alert_handler_reg_wrap module.
+
++moduletree *_reg_wrap
++node tb.dut tl_*
+-module prim_cdc_rand_delay // DV construct.
+-module prim_onehot_check // FPV verified
+
+begin assert
+ +moduletree *csr_assert_fpv
+ +moduletree tlul_assert
+end
+
+// Remove everything else from toggle coverage except:
+// - `prim_alert_sender`: the `alert_test` task under `cip_base_vseq` drives `alert_test_i` and
+// verifies `alert_rx/tx` handshake in each IP.
+begin tgl
+ -tree tb
+ +module prim_alert_sender
+end
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/doc/tb.svg b/hw/top_sencha/ip_autogen/alert_handler/dv/doc/tb.svg
new file mode 100644
index 0000000..e026347
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/doc/tb.svg
@@ -0,0 +1 @@
+<svg version="1.1" viewBox="0.0 0.0 1478.0 1008.0" fill="none" stroke="none" stroke-linecap="square" stroke-miterlimit="10" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><clipPath id="p.0"><path d="m0 0l1478.0 0l0 1008.0l-1478.0 0l0 -1008.0z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="#ffffff" d="m0 0l1478.0 0l0 1008.0l-1478.0 0z" fill-rule="evenodd"/><path fill="#d9d2e9" d="m673.0 63.0l724.0 0l0 728.0l-724.0 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m673.0 63.0l724.0 0l0 728.0l-724.0 0z" fill-rule="evenodd"/><path fill="#000000" d="m1020.1132 88.45125l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm3.1051636 1.46875l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm9.344482 4.90625l0 -1.875l1.875 0l0 1.875l-1.875 0zm4.0738525 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm12.671875 2.890625l-3.6875 -9.671875l1.734375 0l2.078125 5.796875q0.328125 0.9375 0.625 1.9375q0.203125 -0.765625 0.609375 -1.828125l2.140625 -5.90625l1.6875 0l-3.65625 9.671875l-1.53125 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m776.4619 297.16666l105.60632 0l0 25.826782l-105.60632 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m776.4619 297.16666l105.60632 0l0 25.826782l-105.60632 0z" fill-rule="evenodd"/><path fill="#000000" d="m806.2752 312.3788l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm2.34375 2.78125l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm3.2874146 0l0 -10.484375l1.296875 0l0 5.96875l3.046875 -3.078125l1.671875 0l-2.90625 2.8125l3.1875 4.78125l-1.578125 0l-2.515625 -3.890625l-0.90625 0.875l0 3.015625l-1.296875 0zm6.140625 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.322998 -2.90625l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm4.380615 -2.265625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm10.65625 1.109375l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm0.07196045 4.0625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686646 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m776.4593 218.05774l105.60632 0l0 25.826782l-105.60632 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m776.4593 218.05774l105.60632 0l0 25.826782l-105.60632 0z" fill-rule="evenodd"/><path fill="#000000" d="m800.87225 234.89488l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm1.2282104 1.15625l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm2.0999146 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686035 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0zm10.284607 3.078125q-1.0625 -1.34375 -1.796875 -3.140625q-0.734375 -1.8125 -0.734375 -3.734375q0 -1.703125 0.546875 -3.265625q0.640625 -1.8125 1.984375 -3.609375l0.921875 0q-0.859375 1.484375 -1.140625 2.125q-0.4375 0.984375 -0.6875 2.0625q-0.296875 1.34375 -0.296875 2.6875q0 3.453125 2.125 6.875l-0.921875 0zm2.4274902 -3.078125l0 -10.484375l1.28125 0l0 3.75q0.90625 -1.03125 2.28125 -1.03125q0.84375 0 1.46875 0.328125q0.625 0.328125 0.890625 0.921875q0.265625 0.578125 0.265625 1.703125l0 4.8125l-1.28125 0l0 -4.8125q0 -0.96875 -0.421875 -1.40625q-0.421875 -0.4375 -1.1875 -0.4375q-0.578125 0 -1.078125 0.296875q-0.5 0.296875 -0.71875 0.8125q-0.21875 0.5 -0.21875 1.390625l0 4.15625l-1.28125 0zm7.666748 -3.796875q0 -2.109375 1.171875 -3.125q0.984375 -0.84375 2.390625 -0.84375q1.578125 0 2.5625 1.03125q1.0 1.015625 1.0 2.828125q0 1.46875 -0.4375 2.3125q-0.4375 0.828125 -1.28125 1.296875q-0.84375 0.46875 -1.84375 0.46875q-1.59375 0 -2.578125 -1.015625q-0.984375 -1.03125 -0.984375 -2.953125zm1.328125 0q0 1.453125 0.625 2.1875q0.640625 0.71875 1.609375 0.71875q0.96875 0 1.59375 -0.71875q0.640625 -0.734375 0.640625 -2.234375q0 -1.40625 -0.640625 -2.125q-0.640625 -0.734375 -1.59375 -0.734375q-0.96875 0 -1.609375 0.71875q-0.625 0.71875 -0.625 2.1875zm6.791748 1.53125l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm10.65625 1.109375l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm2.1032104 4.234375l-0.921875 0q2.140625 -3.421875 2.140625 -6.875q0 -1.34375 -0.3125 -2.671875q-0.25 -1.0625 -0.671875 -2.046875q-0.28125 -0.65625 -1.15625 -2.15625l0.921875 0q1.34375 1.796875 1.984375 3.609375q0.546875 1.5625 0.546875 3.265625q0 1.921875 -0.734375 3.734375q-0.734375 1.796875 -1.796875 3.140625z" fill-rule="nonzero"/><path fill="#fce5cd" d="m687.3097 353.7874l194.74017 0l0 25.826752l-194.74017 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m687.3097 353.7874l194.74017 0l0 25.826752l-194.74017 0z" fill-rule="evenodd"/><path fill="#000000" d="m709.47614 374.68704l0 -10.5l1.171875 0l0 0.984375q0.421875 -0.578125 0.9375 -0.859375q0.515625 -0.296875 1.265625 -0.296875q0.96875 0 1.71875 0.5q0.75 0.5 1.125 1.421875q0.375 0.90625 0.375 1.984375q0 1.171875 -0.421875 2.109375q-0.40625 0.921875 -1.21875 1.421875q-0.796875 0.5 -1.671875 0.5q-0.640625 0 -1.15625 -0.265625q-0.515625 -0.28125 -0.84375 -0.6875l0 3.6875l-1.28125 0zm1.15625 -6.65625q0 1.453125 0.59375 2.15625q0.609375 0.703125 1.453125 0.703125q0.859375 0 1.46875 -0.71875q0.609375 -0.734375 0.609375 -2.25q0 -1.453125 -0.609375 -2.171875q-0.59375 -0.734375 -1.421875 -0.734375q-0.8125 0 -1.453125 0.78125q-0.640625 0.765625 -0.640625 2.234375zm6.994812 -5.265625l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.2561646 0l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm7.635498 -2.265625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm6.65625 5.171875l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686035 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0zm7.597107 0.171875l0.625 -3.046875l-1.203125 0l0 -1.0625l1.421875 0l0.53125 -2.59375l-1.953125 0l0 -1.0625l2.15625 0l0.625 -3.078125l1.078125 0l-0.625 3.078125l2.25 0l0.625 -3.078125l1.078125 0l-0.609375 3.078125l1.234375 0l0 1.0625l-1.453125 0l-0.546875 2.59375l2.0 0l0 1.0625l-2.203125 0l-0.625 3.046875l-1.078125 0l0.625 -3.046875l-2.25 0l-0.625 3.046875l-1.078125 0zm1.90625 -4.109375l2.25 0l0.546875 -2.59375l-2.265625 0l-0.53125 2.59375zm8.932373 7.015625q-1.0625 -1.34375 -1.796875 -3.140625q-0.734375 -1.8125 -0.734375 -3.734375q0 -1.703125 0.546875 -3.265625q0.640625 -1.8125 1.984375 -3.609375l0.921875 0q-0.859375 1.484375 -1.140625 2.125q-0.4375 0.984375 -0.6875 2.0625q-0.296875 1.34375 -0.296875 2.6875q0 3.453125 2.125 6.875l-0.921875 0zm6.911865 -3.078125l-1.28125 0l0 -8.203125q-0.46875 0.4375 -1.21875 0.890625q-0.75 0.4375 -1.359375 0.65625l0 -1.25q1.078125 -0.5 1.890625 -1.21875q0.8125 -0.734375 1.140625 -1.40625l0.828125 0l0 10.53125zm4.510498 3.078125l-0.921875 0q2.140625 -3.421875 2.140625 -6.875q0 -1.34375 -0.3125 -2.671875q-0.25 -1.0625 -0.671875 -2.046875q-0.28125 -0.65625 -1.15625 -2.15625l0.921875 0q1.34375 1.796875 1.984375 3.609375q0.546875 1.5625 0.546875 3.265625q0 1.921875 -0.734375 3.734375q-0.734375 1.796875 -1.796875 3.140625zm13.030762 -3.078125l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125zm12.494812 1.34375l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm9.291748 4.53125l-2.890625 -7.59375l1.359375 0l1.625 4.546875q0.265625 0.734375 0.5 1.53125q0.15625 -0.609375 0.46875 -1.453125l1.6875 -4.625l1.328125 0l-2.875 7.59375l-1.203125 0zm5.21875 0l0 -7.59375l1.15625 0l0 1.0625q0.34375 -0.5625 0.9375 -0.890625q0.609375 -0.34375 1.359375 -0.34375q0.84375 0 1.375 0.34375q0.546875 0.34375 0.765625 0.984375q0.90625 -1.328125 2.359375 -1.328125q1.125 0 1.734375 0.625q0.609375 0.625 0.609375 1.921875l0 5.21875l-1.28125 0l0 -4.78125q0 -0.78125 -0.125 -1.109375q-0.125 -0.34375 -0.453125 -0.546875q-0.328125 -0.21875 -0.78125 -0.21875q-0.796875 0 -1.328125 0.53125q-0.53125 0.53125 -0.53125 1.703125l0 4.421875l-1.28125 0l0 -4.9375q0 -0.859375 -0.3125 -1.28125q-0.3125 -0.4375 -1.03125 -0.4375q-0.546875 0 -1.015625 0.296875q-0.453125 0.28125 -0.671875 0.828125q-0.203125 0.546875 -0.203125 1.59375l0 3.9375l-1.28125 0zm11.724426 -3.796875q0 -2.109375 1.171875 -3.125q0.984375 -0.84375 2.390625 -0.84375q1.578125 0 2.5625 1.03125q1.0 1.015625 1.0 2.828125q0 1.46875 -0.4375 2.3125q-0.4375 0.828125 -1.28125 1.296875q-0.84375 0.46875 -1.84375 0.46875q-1.59375 0 -2.578125 -1.015625q-0.984375 -1.03125 -0.984375 -2.953125zm1.328125 0q0 1.453125 0.625 2.1875q0.640625 0.71875 1.609375 0.71875q0.96875 0 1.59375 -0.71875q0.640625 -0.734375 0.640625 -2.234375q0 -1.40625 -0.640625 -2.125q-0.640625 -0.734375 -1.59375 -0.734375q-0.96875 0 -1.609375 0.71875q-0.625 0.71875 -0.625 2.1875zm12.229187 3.796875l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125zm12.494873 1.34375l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm5.994873 7.4375l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686035 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m687.32544 413.76642l194.74017 0l0 25.826752l-194.74017 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m687.32544 413.76642l194.74017 0l0 25.826752l-194.74017 0z" fill-rule="evenodd"/><path fill="#000000" d="m725.38257 434.66605l0 -10.5l1.171875 0l0 0.984375q0.421875 -0.578125 0.9375 -0.859375q0.515625 -0.296875 1.265625 -0.296875q0.96875 0 1.71875 0.5q0.75 0.5 1.125 1.421875q0.375 0.90625 0.375 1.984375q0 1.171875 -0.421875 2.109375q-0.40625 0.921875 -1.21875 1.421875q-0.796875 0.5 -1.671875 0.5q-0.640625 0 -1.15625 -0.265625q-0.515625 -0.28125 -0.84375 -0.6875l0 3.6875l-1.28125 0zm1.15625 -6.65625q0 1.453125 0.59375 2.15625q0.609375 0.703125 1.453125 0.703125q0.859375 0 1.46875 -0.71875q0.609375 -0.734375 0.609375 -2.25q0 -1.453125 -0.609375 -2.171875q-0.59375 -0.734375 -1.421875 -0.734375q-0.8125 0 -1.453125 0.78125q-0.640625 0.765625 -0.640625 2.234375zm6.994873 -5.265625l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.2561646 0l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm7.635498 -2.265625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm6.65625 5.171875l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338562 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686646 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0zm7.597107 0.171875l0.625 -3.046875l-1.203125 0l0 -1.0625l1.421875 0l0.53125 -2.59375l-1.953125 0l0 -1.0625l2.15625 0l0.625 -3.078125l1.078125 0l-0.625 3.078125l2.25 0l0.625 -3.078125l1.078125 0l-0.609375 3.078125l1.234375 0l0 1.0625l-1.453125 0l-0.546875 2.59375l2.0 0l0 1.0625l-2.203125 0l-0.625 3.046875l-1.078125 0l0.625 -3.046875l-2.25 0l-0.625 3.046875l-1.078125 0zm1.90625 -4.109375l2.25 0l0.546875 -2.59375l-2.265625 0l-0.53125 2.59375zm8.932312 7.015625q-1.0625 -1.34375 -1.796875 -3.140625q-0.734375 -1.8125 -0.734375 -3.734375q0 -1.703125 0.546875 -3.265625q0.640625 -1.8125 1.984375 -3.609375l0.921875 0q-0.859375 1.484375 -1.140625 2.125q-0.4375 0.984375 -0.6875 2.0625q-0.296875 1.34375 -0.296875 2.6875q0 3.453125 2.125 6.875l-0.921875 0zm8.755676 -11.0l-1.28125 0.09375q-0.171875 -0.75 -0.484375 -1.09375q-0.53125 -0.546875 -1.296875 -0.546875q-0.609375 0 -1.078125 0.34375q-0.609375 0.4375 -0.96875 1.296875q-0.34375 0.84375 -0.359375 2.421875q0.46875 -0.71875 1.140625 -1.0625q0.671875 -0.34375 1.40625 -0.34375q1.296875 0 2.203125 0.953125q0.90625 0.953125 0.90625 2.453125q0 0.984375 -0.4375 1.84375q-0.421875 0.84375 -1.171875 1.296875q-0.734375 0.4375 -1.6875 0.4375q-1.609375 0 -2.625 -1.171875q-1.015625 -1.1875 -1.015625 -3.90625q0 -3.046875 1.125 -4.421875q0.984375 -1.203125 2.640625 -1.203125q1.234375 0 2.03125 0.703125q0.796875 0.6875 0.953125 1.90625zm-5.265625 4.515625q0 0.671875 0.28125 1.28125q0.28125 0.609375 0.78125 0.9375q0.515625 0.3125 1.078125 0.3125q0.8125 0 1.390625 -0.65625q0.59375 -0.671875 0.59375 -1.796875q0 -1.09375 -0.578125 -1.71875q-0.578125 -0.625 -1.453125 -0.625q-0.875 0 -1.484375 0.625q-0.609375 0.625 -0.609375 1.640625zm10.854248 3.40625l0 -2.515625l-4.546875 0l0 -1.171875l4.78125 -6.796875l1.0625 0l0 6.796875l1.40625 0l0 1.171875l-1.40625 0l0 2.515625l-1.296875 0zm0 -3.6875l0 -4.734375l-3.28125 4.734375l3.28125 0zm5.229187 6.765625l-0.921875 0q2.140625 -3.421875 2.140625 -6.875q0 -1.34375 -0.3125 -2.671875q-0.25 -1.0625 -0.671875 -2.046875q-0.28125 -0.65625 -1.15625 -2.15625l0.921875 0q1.34375 1.796875 1.984375 3.609375q0.546875 1.5625 0.546875 3.265625q0 1.921875 -0.734375 3.734375q-0.734375 1.796875 -1.796875 3.140625zm8.108887 -12.09375l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.2561646 0l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm10.963623 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm1.2438354 1.15625l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm3.7087402 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686646 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#cfe2f3" d="m682.6221 591.874l676.0781 0l28.677734 28.677734l0 143.38525l-704.75586 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m682.6221 591.874l676.0781 0l28.677734 28.677734l0 143.38525l-704.75586 0z" fill-rule="evenodd"/><path fill="#000000" d="m695.79395 621.12225l0 6.359375l1.828125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.828125 0l0 -6.359375l-1.828125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l4.1875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.828125 0zm5.8012695 1.390625l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm9.80127 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm6.4262695 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm9.160645 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.05127 5.5l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm13.321289 0l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.4575195 -5.234375l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.504395 5.234375q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm7.5825195 -2.21875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm4.4887695 2.578125l0 2.375l-1.25 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0l0 4.921875l2.265625 -1.90625l-0.265625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.078125 0.28125 -0.078125l1.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.609375 0l-2.078125 1.734375l2.625 2.6875l0.625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.375 0l-2.296875 -2.359375l-0.609375 0.515625zm8.785645 -3.125l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm17.461914 -3.609375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm18.91504 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm8.55127 2.21875q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm2.9262695 -2.765625l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm7.8012695 0l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm3.6293945 -2.765625l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm17.60254 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.08252 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm9.691895 4.953125l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.48877 -2.296875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm8.45752 2.328125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.2075195 -1.984375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm14.118164 -3.09375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.86377 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm15.383789 -2.21875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm8.55127 2.21875q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm3.6293945 -2.765625l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm9.17627 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm8.42627 -3.28125l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.30127 0.984375l0 -0.984375l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0l0 5.328125q0 0.53125 -0.234375 0.953125q-0.15625 0.265625 -0.515625 0.5625q-0.34375 0.3125 -0.640625 0.4375q-0.296875 0.125 -0.78125 0.125l-1.515625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.265625 -0.078125l1.53125 0.015625q0.46875 0 0.84375 -0.25q0.390625 -0.234375 0.625 -0.703125q0.140625 -0.265625 0.140625 -0.671875l0 -1.609375q-0.84375 1.171875 -2.203125 1.171875q-1.09375 0 -1.890625 -0.8125q-0.796875 -0.8125 -0.796875 -1.953125q0 -1.15625 0.796875 -1.96875q0.796875 -0.8125 1.890625 -0.8125q1.359375 0 2.203125 1.171875zm0 1.609375q0 -0.953125 -0.640625 -1.59375q-0.640625 -0.640625 -1.53125 -0.640625q-0.90625 0 -1.546875 0.65625q-0.640625 0.640625 -0.640625 1.578125q0 0.9375 0.640625 1.59375q0.640625 0.640625 1.546875 0.640625q0.890625 0 1.53125 -0.640625q0.640625 -0.65625 0.640625 -1.59375zm16.430664 -5.0625l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm3.7231445 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125z" fill-rule="nonzero"/><path fill="#000000" d="m694.4346 638.5129l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm9.160645 -2.46875l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm11.08252 11.53125l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m791.41895 638.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm15.071289 -3.96875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.39502 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm11.524414 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.2231445 2.734375l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875zm14.477539 -5.5l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm9.160645 -2.46875l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm11.08252 11.53125l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm5.7856445 -3.5625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.05127 -1.859375l0 -0.984375l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0l0 5.328125q0 0.53125 -0.234375 0.953125q-0.15625 0.265625 -0.515625 0.5625q-0.34375 0.3125 -0.640625 0.4375q-0.296875 0.125 -0.78125 0.125l-1.515625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.265625 -0.078125l1.53125 0.015625q0.46875 0 0.84375 -0.25q0.390625 -0.234375 0.625 -0.703125q0.140625 -0.265625 0.140625 -0.671875l0 -1.609375q-0.84375 1.171875 -2.203125 1.171875q-1.09375 0 -1.890625 -0.8125q-0.796875 -0.8125 -0.796875 -1.953125q0 -1.15625 0.796875 -1.96875q0.796875 -0.8125 1.890625 -0.8125q1.359375 0 2.203125 1.171875zm0 1.609375q0 -0.953125 -0.640625 -1.59375q-0.640625 -0.640625 -1.53125 -0.640625q-0.90625 0 -1.546875 0.65625q-0.640625 0.640625 -0.640625 1.578125q0 0.9375 0.640625 1.59375q0.640625 0.640625 1.546875 0.640625q0.890625 0 1.53125 -0.640625q0.640625 -0.65625 0.640625 -1.59375zm8.89502 0.28125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm3.7231445 -2.34375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.785645 0l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm7.8012695 -3.96875l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm8.379395 1.53125l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m697.7471 655.05975l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm5.8481445 -3.015625l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm6.4418945 5.59375l0 2.375l-1.25 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0l0 4.921875l2.265625 -1.90625l-0.265625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.078125 0.28125 -0.078125l1.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.609375 0l-2.078125 1.734375l2.625 2.6875l0.625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.375 0l-2.296875 -2.359375l-0.609375 0.515625zm12.441895 5.9375l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm3.6137695 -9.0625l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.191895 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm4.9575195 -0.359375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m791.41895 654.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm15.071289 -3.96875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.39502 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm11.524414 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.2231445 2.734375l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875z" fill-rule="nonzero"/><path fill="#000000" d="m910.71924 654.341q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm6.404419 -2.765625l0 1.40625l-1.59375 0l0 -1.40625l1.59375 0zm0.171875 2.53125l0 4.578125l1.609375 0q0.46875 0 0.671875 0.1875q0.21875 0.171875 0.21875 0.484375q0 0.28125 -0.21875 0.46875q-0.203125 0.1875 -0.671875 0.1875l-4.546875 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l1.609375 0l0 -3.25l-1.078125 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l2.40625 0zm5.685669 5.171875l0 2.1875l0.796875 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.296875 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.359375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -6.03125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0l0 0.453125q0.46875 -0.3125 0.96875 -0.46875q0.5 -0.15625 1.03125 -0.15625q1.359375 0 2.328125 0.921875q0.96875 0.921875 0.96875 2.125q0 1.3125 -1.140625 2.171875q-0.953125 0.71875 -2.140625 0.71875q-0.515625 0 -1.015625 -0.140625q-0.5 -0.15625 -1.0 -0.453125zm3.953125 -2.296875q0 -0.28125 -0.21875 -0.703125q-0.21875 -0.4375 -0.6875 -0.71875q-0.453125 -0.296875 -1.0625 -0.296875q-1.0 0 -1.59375 0.75q-0.390625 0.515625 -0.390625 0.984375q0 0.53125 0.5625 1.046875q0.578125 0.5 1.421875 0.5q0.84375 0 1.40625 -0.5q0.5625 -0.5 0.5625 -1.0625zm9.388794 7.03125l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm2.62323 -12.4375l0 2.984375q0.5 -0.3125 1.0 -0.46875q0.5 -0.15625 1.015625 -0.15625q1.390625 0 2.34375 0.953125q0.96875 0.953125 0.96875 2.3125q0 1.296875 -0.921875 2.171875q-0.90625 0.859375 -2.421875 0.859375q-0.53125 0 -1.03125 -0.140625q-0.484375 -0.140625 -0.953125 -0.40625l0 0.328125l-1.5625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -5.78125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0zm4.0 5.65625q0 -0.828125 -0.59375 -1.390625q-0.578125 -0.578125 -1.40625 -0.578125q-0.84375 0 -1.421875 0.578125q-0.578125 0.5625 -0.578125 1.375q0 0.734375 0.515625 1.203125q0.53125 0.46875 1.484375 0.46875q0.953125 0 1.46875 -0.46875q0.53125 -0.46875 0.53125 -1.1875zm6.888794 2.78125l0 -0.3125q-0.5 0.265625 -1.109375 0.390625q-0.609375 0.140625 -1.09375 0.140625q-1.078125 0 -1.75 -0.5625q-0.671875 -0.578125 -0.671875 -1.265625q0 -0.84375 0.859375 -1.5625q0.859375 -0.71875 2.359375 -0.71875q0.609375 0 1.40625 0.140625l0 -0.328125q0 -0.296875 -0.265625 -0.484375q-0.25 -0.1875 -0.96875 -0.1875q-0.59375 0 -1.546875 0.234375q-0.34375 0.078125 -0.546875 0.078125q-0.265625 0 -0.453125 -0.1875q-0.171875 -0.1875 -0.171875 -0.484375q0 -0.171875 0.0625 -0.296875q0.0625 -0.125 0.171875 -0.203125q0.125 -0.078125 0.5 -0.171875q0.484375 -0.140625 1.0 -0.21875q0.515625 -0.078125 0.9375 -0.078125q1.234375 0 1.921875 0.53125q0.6875 0.53125 0.6875 1.46875l0 2.75l0.234375 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.5625 0zm0 -2.390625q-0.796875 -0.15625 -1.484375 -0.15625q-0.8125 0 -1.390625 0.40625q-0.375 0.25 -0.375 0.5q0 0.203125 0.1875 0.3125q0.3125 0.21875 0.890625 0.21875q0.46875 0 1.078125 -0.1875q0.609375 -0.1875 1.09375 -0.515625l0 -0.578125zm8.232544 -1.953125q-0.328125 -0.203125 -0.6875 -0.296875q-0.34375 -0.109375 -0.734375 -0.109375q-0.78125 0 -1.234375 0.25q-0.203125 0.109375 -0.203125 0.25q0 0.140625 0.265625 0.28125q0.21875 0.109375 0.9375 0.203125q1.328125 0.1875 1.84375 0.375q0.6875 0.234375 1.046875 0.71875q0.375 0.46875 0.375 1.0q0 0.703125 -0.625 1.1875q-0.90625 0.703125 -2.34375 0.703125q-0.578125 0 -1.078125 -0.109375q-0.484375 -0.09375 -0.890625 -0.296875q-0.109375 0.09375 -0.21875 0.140625q-0.109375 0.046875 -0.21875 0.046875q-0.3125 0 -0.5 -0.203125q-0.1875 -0.21875 -0.1875 -0.6875l0 -0.453125q0 -0.484375 0.1875 -0.6875q0.1875 -0.203125 0.484375 -0.203125q0.234375 0 0.390625 0.140625q0.171875 0.125 0.265625 0.453125q0.296875 0.25 0.71875 0.390625q0.4375 0.125 1.0 0.125q0.921875 0 1.421875 -0.28125q0.25 -0.140625 0.25 -0.296875q0 -0.265625 -0.34375 -0.4375q-0.34375 -0.15625 -1.421875 -0.28125q-1.609375 -0.171875 -2.15625 -0.65625q-0.53125 -0.46875 -0.53125 -1.171875q0 -0.703125 0.59375 -1.1875q0.828125 -0.640625 2.15625 -0.640625q0.453125 0 0.875 0.09375q0.4375 0.078125 0.828125 0.25q0.125 -0.078125 0.234375 -0.125q0.109375 -0.046875 0.1875 -0.046875q0.28125 0 0.453125 0.203125q0.1875 0.203125 0.1875 0.6875l0 0.328125q0 0.4375 -0.09375 0.59375q-0.21875 0.296875 -0.578125 0.296875q-0.234375 0 -0.421875 -0.140625q-0.171875 -0.15625 -0.234375 -0.40625zm9.90448 2.0625l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm9.810669 7.609375l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm7.654419 -6.28125l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm4.779419 -2.296875l0 0.453125q0.359375 -0.3125 0.796875 -0.46875q0.4375 -0.15625 0.953125 -0.15625q1.1875 0 1.875 0.734375q0.546875 0.578125 0.546875 1.53125l0 2.484375q0.421875 0 0.625 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.203125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.1875 -0.46875q0.203125 -0.1875 0.640625 -0.1875l0 -2.53125q0 -0.421875 -0.234375 -0.625q-0.3125 -0.265625 -0.921875 -0.265625q-0.46875 0 -0.8125 0.1875q-0.34375 0.171875 -0.875 0.75l0 2.484375q0.5 0 0.65625 0.09375q0.3125 0.1875 0.3125 0.578125q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.359375 0.3125 -0.5625q0.15625 -0.09375 0.671875 -0.09375l0 -3.25q-0.421875 0 -0.625 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.28125 0zm9.357605 4.28125l1.4375 -2.953125q-0.546875 0 -0.6875 -0.09375q-0.328125 -0.203125 -0.328125 -0.578125q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.828125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.21875 0l-2.234375 4.578125l-1.390625 0l-2.234375 -4.578125l-0.1875 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.796875 0q0.46875 0 0.671875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.359375 -0.3125 0.5625q-0.15625 0.09375 -0.6875 0.09375l1.453125 2.953125zm11.670044 5.625l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm6.388794 -9.671875q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm5.904419 1.09375l0 3.25l1.90625 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-4.03125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.796875 0l0 -3.25l-0.640625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.640625 0l0 -0.515625q0 -0.859375 0.65625 -1.4375q0.65625 -0.578125 1.890625 -0.578125q0.5625 0 1.28125 0.109375q0.71875 0.09375 0.92193604 0.28125q0.21875 0.171875 0.21875 0.453125q0 0.3125 -0.1875 0.515625q-0.18756104 0.1875 -0.45318604 0.1875q-0.125 0 -0.359375 -0.046875q-0.828125 -0.171875 -1.46875 -0.171875q-0.671875 0 -0.921875 0.203125q-0.25 0.203125 -0.25 0.484375l0 0.515625l2.0625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.0625 0zm9.482605 -0.9375l0 -0.390625l1.5625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.234375 0l0 4.859375q0 0.703125 -0.296875 1.21875q-0.296875 0.53125 -0.90625 0.90625q-0.609375 0.375 -1.375 0.375l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.46875 0q0.625 0 0.953125 -0.34375q0.34375 -0.328125 0.34375 -0.828125l0 -0.65625q-0.4375 0.296875 -0.90625 0.4375q-0.453125 0.140625 -0.9375 0.140625q-1.359375 0 -2.28125 -0.90625q-0.921875 -0.90625 -0.921875 -2.25q0 -1.328125 0.921875 -2.234375q0.921875 -0.921875 2.28125 -0.921875q0.5 0 0.953125 0.15625q0.46875 0.140625 0.890625 0.4375zm-0.015625 2.5625q0 -0.734375 -0.546875 -1.265625q-0.53125 -0.546875 -1.296875 -0.546875q-0.765625 0 -1.3125 0.546875q-0.53125 0.53125 -0.53125 1.265625q0 0.734375 0.53125 1.28125q0.546875 0.53125 1.3125 0.53125q0.765625 0 1.296875 -0.53125q0.546875 -0.546875 0.546875 -1.28125z" fill-rule="nonzero"/><path fill="#000000" d="m1036.4089 654.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm7.8012695 -3.96875l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm10.129395 -3.421875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm5.8481445 -3.015625l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm6.4418945 5.59375l0 2.375l-1.25 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0l0 4.921875l2.265625 -1.90625l-0.265625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.078125 0.28125 -0.078125l1.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.609375 0l-2.078125 1.734375l2.625 2.6875l0.625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.375 0l-2.296875 -2.359375l-0.609375 0.515625zm12.441895 5.9375l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm3.6137695 -9.0625l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.191895 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm4.9575195 -0.359375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m695.79395 667.7785l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.98877 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m791.41895 670.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm15.071289 -3.96875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.39502 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm11.524414 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.2231445 2.734375l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875z" fill-rule="nonzero"/><path fill="#000000" d="m910.71924 670.341q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm6.404419 -2.765625l0 1.40625l-1.59375 0l0 -1.40625l1.59375 0zm0.171875 2.53125l0 4.578125l1.609375 0q0.46875 0 0.671875 0.1875q0.21875 0.171875 0.21875 0.484375q0 0.28125 -0.21875 0.46875q-0.203125 0.1875 -0.671875 0.1875l-4.546875 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l1.609375 0l0 -3.25l-1.078125 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l2.40625 0zm5.685669 5.171875l0 2.1875l0.796875 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.296875 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.359375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -6.03125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0l0 0.453125q0.46875 -0.3125 0.96875 -0.46875q0.5 -0.15625 1.03125 -0.15625q1.359375 0 2.328125 0.921875q0.96875 0.921875 0.96875 2.125q0 1.3125 -1.140625 2.171875q-0.953125 0.71875 -2.140625 0.71875q-0.515625 0 -1.015625 -0.140625q-0.5 -0.15625 -1.0 -0.453125zm3.953125 -2.296875q0 -0.28125 -0.21875 -0.703125q-0.21875 -0.4375 -0.6875 -0.71875q-0.453125 -0.296875 -1.0625 -0.296875q-1.0 0 -1.59375 0.75q-0.390625 0.515625 -0.390625 0.984375q0 0.53125 0.5625 1.046875q0.578125 0.5 1.421875 0.5q0.84375 0 1.40625 -0.5q0.5625 -0.5 0.5625 -1.0625zm9.388794 7.03125l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm2.62323 -12.4375l0 2.984375q0.5 -0.3125 1.0 -0.46875q0.5 -0.15625 1.015625 -0.15625q1.390625 0 2.34375 0.953125q0.96875 0.953125 0.96875 2.3125q0 1.296875 -0.921875 2.171875q-0.90625 0.859375 -2.421875 0.859375q-0.53125 0 -1.03125 -0.140625q-0.484375 -0.140625 -0.953125 -0.40625l0 0.328125l-1.5625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -5.78125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0zm4.0 5.65625q0 -0.828125 -0.59375 -1.390625q-0.578125 -0.578125 -1.40625 -0.578125q-0.84375 0 -1.421875 0.578125q-0.578125 0.5625 -0.578125 1.375q0 0.734375 0.515625 1.203125q0.53125 0.46875 1.484375 0.46875q0.953125 0 1.46875 -0.46875q0.53125 -0.46875 0.53125 -1.1875zm6.888794 2.78125l0 -0.3125q-0.5 0.265625 -1.109375 0.390625q-0.609375 0.140625 -1.09375 0.140625q-1.078125 0 -1.75 -0.5625q-0.671875 -0.578125 -0.671875 -1.265625q0 -0.84375 0.859375 -1.5625q0.859375 -0.71875 2.359375 -0.71875q0.609375 0 1.40625 0.140625l0 -0.328125q0 -0.296875 -0.265625 -0.484375q-0.25 -0.1875 -0.96875 -0.1875q-0.59375 0 -1.546875 0.234375q-0.34375 0.078125 -0.546875 0.078125q-0.265625 0 -0.453125 -0.1875q-0.171875 -0.1875 -0.171875 -0.484375q0 -0.171875 0.0625 -0.296875q0.0625 -0.125 0.171875 -0.203125q0.125 -0.078125 0.5 -0.171875q0.484375 -0.140625 1.0 -0.21875q0.515625 -0.078125 0.9375 -0.078125q1.234375 0 1.921875 0.53125q0.6875 0.53125 0.6875 1.46875l0 2.75l0.234375 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.5625 0zm0 -2.390625q-0.796875 -0.15625 -1.484375 -0.15625q-0.8125 0 -1.390625 0.40625q-0.375 0.25 -0.375 0.5q0 0.203125 0.1875 0.3125q0.3125 0.21875 0.890625 0.21875q0.46875 0 1.078125 -0.1875q0.609375 -0.1875 1.09375 -0.515625l0 -0.578125zm8.232544 -1.953125q-0.328125 -0.203125 -0.6875 -0.296875q-0.34375 -0.109375 -0.734375 -0.109375q-0.78125 0 -1.234375 0.25q-0.203125 0.109375 -0.203125 0.25q0 0.140625 0.265625 0.28125q0.21875 0.109375 0.9375 0.203125q1.328125 0.1875 1.84375 0.375q0.6875 0.234375 1.046875 0.71875q0.375 0.46875 0.375 1.0q0 0.703125 -0.625 1.1875q-0.90625 0.703125 -2.34375 0.703125q-0.578125 0 -1.078125 -0.109375q-0.484375 -0.09375 -0.890625 -0.296875q-0.109375 0.09375 -0.21875 0.140625q-0.109375 0.046875 -0.21875 0.046875q-0.3125 0 -0.5 -0.203125q-0.1875 -0.21875 -0.1875 -0.6875l0 -0.453125q0 -0.484375 0.1875 -0.6875q0.1875 -0.203125 0.484375 -0.203125q0.234375 0 0.390625 0.140625q0.171875 0.125 0.265625 0.453125q0.296875 0.25 0.71875 0.390625q0.4375 0.125 1.0 0.125q0.921875 0 1.421875 -0.28125q0.25 -0.140625 0.25 -0.296875q0 -0.265625 -0.34375 -0.4375q-0.34375 -0.15625 -1.421875 -0.28125q-1.609375 -0.171875 -2.15625 -0.65625q-0.53125 -0.46875 -0.53125 -1.171875q0 -0.703125 0.59375 -1.1875q0.828125 -0.640625 2.15625 -0.640625q0.453125 0 0.875 0.09375q0.4375 0.078125 0.828125 0.25q0.125 -0.078125 0.234375 -0.125q0.109375 -0.046875 0.1875 -0.046875q0.28125 0 0.453125 0.203125q0.1875 0.203125 0.1875 0.6875l0 0.328125q0 0.4375 -0.09375 0.59375q-0.21875 0.296875 -0.578125 0.296875q-0.234375 0 -0.421875 -0.140625q-0.171875 -0.15625 -0.234375 -0.40625zm9.90448 2.0625l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm9.810669 7.609375l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm7.654419 -6.28125l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm4.779419 -2.296875l0 0.453125q0.359375 -0.3125 0.796875 -0.46875q0.4375 -0.15625 0.953125 -0.15625q1.1875 0 1.875 0.734375q0.546875 0.578125 0.546875 1.53125l0 2.484375q0.421875 0 0.625 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.203125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.1875 -0.46875q0.203125 -0.1875 0.640625 -0.1875l0 -2.53125q0 -0.421875 -0.234375 -0.625q-0.3125 -0.265625 -0.921875 -0.265625q-0.46875 0 -0.8125 0.1875q-0.34375 0.171875 -0.875 0.75l0 2.484375q0.5 0 0.65625 0.09375q0.3125 0.1875 0.3125 0.578125q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.359375 0.3125 -0.5625q0.15625 -0.09375 0.671875 -0.09375l0 -3.25q-0.421875 0 -0.625 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.28125 0zm9.357605 4.28125l1.4375 -2.953125q-0.546875 0 -0.6875 -0.09375q-0.328125 -0.203125 -0.328125 -0.578125q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.828125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.21875 0l-2.234375 4.578125l-1.390625 0l-2.234375 -4.578125l-0.1875 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.796875 0q0.46875 0 0.671875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.359375 -0.3125 0.5625q-0.15625 0.09375 -0.6875 0.09375l1.453125 2.953125zm11.670044 5.625l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm6.388794 -9.671875q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm5.904419 1.09375l0 3.25l1.90625 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-4.03125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.796875 0l0 -3.25l-0.640625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.640625 0l0 -0.515625q0 -0.859375 0.65625 -1.4375q0.65625 -0.578125 1.890625 -0.578125q0.5625 0 1.28125 0.109375q0.71875 0.09375 0.92193604 0.28125q0.21875 0.171875 0.21875 0.453125q0 0.3125 -0.1875 0.515625q-0.18756104 0.1875 -0.45318604 0.1875q-0.125 0 -0.359375 -0.046875q-0.828125 -0.171875 -1.46875 -0.171875q-0.671875 0 -0.921875 0.203125q-0.25 0.203125 -0.25 0.484375l0 0.515625l2.0625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.0625 0zm9.482605 -0.9375l0 -0.390625l1.5625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.234375 0l0 4.859375q0 0.703125 -0.296875 1.21875q-0.296875 0.53125 -0.90625 0.90625q-0.609375 0.375 -1.375 0.375l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.46875 0q0.625 0 0.953125 -0.34375q0.34375 -0.328125 0.34375 -0.828125l0 -0.65625q-0.4375 0.296875 -0.90625 0.4375q-0.453125 0.140625 -0.9375 0.140625q-1.359375 0 -2.28125 -0.90625q-0.921875 -0.90625 -0.921875 -2.25q0 -1.328125 0.921875 -2.234375q0.921875 -0.921875 2.28125 -0.921875q0.5 0 0.953125 0.15625q0.46875 0.140625 0.890625 0.4375zm-0.015625 2.5625q0 -0.734375 -0.546875 -1.265625q-0.53125 -0.546875 -1.296875 -0.546875q-0.765625 0 -1.3125 0.546875q-0.53125 0.53125 -0.53125 1.265625q0 0.734375 0.53125 1.28125q0.546875 0.53125 1.3125 0.53125q0.765625 0 1.296875 -0.53125q0.546875 -0.546875 0.546875 -1.28125z" fill-rule="nonzero"/><path fill="#000000" d="m1036.4089 670.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm7.8012695 -3.96875l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm8.17627 -6.703125l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.98877 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m807.3965 685.12225l0 6.359375l1.375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.3125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.390625 0l0 -6.359375l-2.1875 0l0 1.84375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -2.375l5.96875 0l0 2.375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -1.84375l-2.171875 0zm5.7700195 -1.078125l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm9.83252 -0.265625l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.27002 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm14.118164 -3.09375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.27002 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm16.07129 0.1875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm4.9418945 -0.546875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm6.9887695 3.15625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm5.1762695 -2.84375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm15.071289 2.734375l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm11.836914 -0.359375l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm5.4575195 -5.328125l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.285645 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm9.598145 8.703125l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm17.79004 4.953125l-0.65625 0l-1.171875 -3.421875l-1.171875 3.421875l-0.65625 0l-1.109375 -4.953125l-0.25 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.671875 0l0.9375 4.21875l1.140625 -3.375l0.640625 0l1.171875 3.375l0.90625 -4.21875l-0.671875 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.25 0l-1.09375 4.953125zm6.2387695 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm6.4262695 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm7.1293945 -2.46875l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm19.97754 7.96875l-0.6875 0l-3.9375 -6.640625l0 6.109375l0.984375 0q0.203125 0 0.28125 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.953125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.4375 0l0 -6.359375l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.40625 0l3.9375 6.65625l0 -6.125l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.96875 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.453125 0l0 6.890625zm7.7700195 -6.890625l0 4.453125q0 1.125 -0.75 1.890625q-0.75 0.75 -1.8125 0.75q-0.703125 0 -1.265625 -0.296875q-0.546875 -0.3125 -0.9375 -0.9375q-0.390625 -0.640625 -0.390625 -1.40625l0 -4.453125l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.96875 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 4.453125q0 0.875 0.609375 1.5q0.609375 0.609375 1.421875 0.609375q0.53125 0 0.96875 -0.234375q0.4375 -0.25 0.765625 -0.75q0.328125 -0.5 0.328125 -1.125l0 -4.453125l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.96875 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.453125 0zm5.5668945 4.65625l-0.609375 0l-2.046875 -4.65625l-0.109375 0l0 6.359375l0.984375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.953125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.4375 0l0 -6.359375l-0.328125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.3125 0l2.015625 4.59375l1.984375 -4.59375l1.3125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.34375 0l0 6.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.96875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -6.359375l-0.109375 0l-2.015625 4.65625zm11.004395 5.796875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5981445 -5.796875l-0.609375 0l-2.046875 -4.65625l-0.109375 0l0 6.359375l0.984375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.953125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.4375 0l0 -6.359375l-0.328125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.3125 0l2.015625 4.59375l1.984375 -4.59375l1.3125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.34375 0l0 6.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.96875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -6.359375l-0.109375 0l-2.015625 4.65625zm9.20752 -0.25l-3.5 0l-0.71875 1.953125l1.015625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.40625 0l2.359375 -6.359375l-1.578125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.6875 0l2.59375 6.890625l0.421875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.015625 0l-0.734375 -1.953125zm-0.203125 -0.53125l-1.46875 -3.875l-0.203125 0l-1.421875 3.875l3.09375 0zm6.5668945 -0.78125l2.53125 3.265625l0.203125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.84375 0l-2.203125 -2.828125l-2.171875 2.828125l0.84375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.703125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.046875 -0.15625q0.046875 -0.078125 0.109375 -0.09375q0.0625 -0.015625 0.390625 -0.015625l2.5 -3.265625l-2.390625 -3.09375l-0.1875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.609375 0l2.0625 2.65625l2.046875 -2.65625l-0.59375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.203125 0l-2.375 3.09375zm11.035645 7.359375l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -10.453125l0 6.359375l1.828125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.828125 0l0 -6.359375l-1.828125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l4.1875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.828125 0zm10.14502 6.890625l-0.6875 0l-3.9375 -6.640625l0 6.109375l0.984375 0q0.203125 0 0.28125 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.953125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.4375 0l0 -6.359375l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.40625 0l3.9375 6.65625l0 -6.125l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.96875 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.453125 0l0 6.890625zm5.4575195 -6.890625l0 6.359375l1.375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.3125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.390625 0l0 -6.359375l-2.1875 0l0 1.84375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -2.375l5.96875 0l0 2.375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -1.84375l-2.171875 0zm5.8012695 3.296875l0 3.0625l4.09375 0l0 -1.578125q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.125 0 0.1875 0.09375q0.078125 0.078125 0.078125 0.265625l0 2.109375l-5.875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.703125 0l0 -6.359375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l5.59375 0l0 1.828125q0 0.1875 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.125 0 -0.203125 -0.078125q-0.0625 -0.09375 -0.0625 -0.28125l0 -1.296875l-3.8125 0l0 2.765625l1.90625 0l0 -0.59375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.1875 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.734375q0 0.1875 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -0.609375l-1.90625 0zm7.8012695 0.28125l0 2.78125l0.984375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.234375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.703125 0l0 -6.359375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l3.21875 0q1.0 0 1.671875 0.640625q0.6875 0.625 0.6875 1.40625q0 0.578125 -0.421875 1.078125q-0.421875 0.5 -1.40625 0.84375q0.5625 0.390625 0.96875 0.890625q0.40625 0.5 1.296875 2.03125l0.40625 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0q-0.984375 -1.765625 -1.53125 -2.375q-0.546875 -0.609375 -1.25 -0.9375l-1.6875 0zm0 -0.53125l1.453125 0q0.6875 0 1.25 -0.25q0.578125 -0.265625 0.828125 -0.609375q0.265625 -0.34375 0.265625 -0.6875q0 -0.53125 -0.546875 -1.015625q-0.53125 -0.484375 -1.296875 -0.484375l-1.953125 0l0 3.046875zm7.8012695 0.53125l0 2.78125l0.984375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.234375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.703125 0l0 -6.359375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l3.21875 0q1.0 0 1.671875 0.640625q0.6875 0.625 0.6875 1.40625q0 0.578125 -0.421875 1.078125q-0.421875 0.5 -1.40625 0.84375q0.5625 0.390625 0.96875 0.890625q0.40625 0.5 1.296875 2.03125l0.40625 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0q-0.984375 -1.765625 -1.53125 -2.375q-0.546875 -0.609375 -1.25 -0.9375l-1.6875 0zm0 -0.53125l1.453125 0q0.6875 0 1.25 -0.25q0.578125 -0.265625 0.828125 -0.609375q0.265625 -0.34375 0.265625 -0.6875q0 -0.53125 -0.546875 -1.015625q-0.53125 -0.484375 -1.296875 -0.484375l-1.953125 0l0 3.046875zm12.11377 -3.046875l0 4.453125q0 1.125 -0.75 1.890625q-0.75 0.75 -1.8125 0.75q-0.703125 0 -1.265625 -0.296875q-0.546875 -0.3125 -0.9375 -0.9375q-0.390625 -0.640625 -0.390625 -1.40625l0 -4.453125l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.96875 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 4.453125q0 0.875 0.609375 1.5q0.609375 0.609375 1.421875 0.609375q0.53125 0 0.96875 -0.234375q0.4375 -0.25 0.765625 -0.75q0.328125 -0.5 0.328125 -1.125l0 -4.453125l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.96875 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.453125 0zm4.0668945 3.84375l0 2.515625l1.828125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.09375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.359375l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l3.109375 0q1.09375 0 1.78125 0.65625q0.703125 0.640625 0.703125 1.5q0 0.515625 -0.234375 0.9375q-0.21875 0.40625 -0.53125 0.640625q-0.484375 0.359375 -0.984375 0.515625q-0.375 0.125 -0.921875 0.125l-1.65625 0zm0 -0.53125l1.6875 0q0.59375 0 1.109375 -0.265625q0.515625 -0.265625 0.75 -0.640625q0.25 -0.390625 0.25 -0.78125q0 -0.625 -0.546875 -1.125q-0.53125 -0.5 -1.359375 -0.5l-1.890625 0l0 3.3125zm9.223145 -3.3125l0 6.359375l1.375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.3125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.390625 0l0 -6.359375l-2.1875 0l0 1.84375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -2.375l5.96875 0l0 2.375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.078125 -0.078125 -0.28125l0 -1.84375l-2.171875 0zm9.441895 0l0 -0.1875q0 -0.1875 0.0625 -0.265625q0.078125 -0.078125 0.203125 -0.078125q0.125 0 0.1875 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.359375q0 0.203125 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.125 0 -0.203125 -0.078125q-0.0625 -0.078125 -0.0625 -0.25q-0.03125 -0.53125 -0.5625 -0.953125q-0.515625 -0.421875 -1.34375 -0.421875q-0.890625 0 -1.40625 0.453125q-0.515625 0.453125 -0.515625 1.0625q0 0.328125 0.140625 0.59375q0.140625 0.25 0.375 0.421875q0.25 0.15625 0.546875 0.25q0.3125 0.09375 0.96875 0.203125q1.078125 0.1875 1.5 0.359375q0.546875 0.25 0.828125 0.6875q0.28125 0.4375 0.28125 1.03125q0 0.921875 -0.734375 1.5625q-0.71875 0.640625 -1.96875 0.640625q-1.375 0 -2.21875 -0.859375l0 0.296875q0 0.1875 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.46875q0 -0.203125 0.078125 -0.28125q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.1875 0.078125q0.078125 0.078125 0.078125 0.25q0.03125 0.578125 0.625 1.0625q0.59375 0.46875 1.59375 0.46875q1.015625 0 1.59375 -0.5q0.578125 -0.5 0.578125 -1.1875q0 -0.421875 -0.21875 -0.734375q-0.21875 -0.328125 -0.65625 -0.53125q-0.3125 -0.125 -1.28125 -0.296875q-1.328125 -0.21875 -1.90625 -0.671875q-0.578125 -0.453125 -0.578125 -1.296875q0 -0.84375 0.65625 -1.4375q0.671875 -0.609375 1.78125 -0.609375q1.109375 0 1.921875 0.703125zm15.524414 6.890625l-0.65625 0l-1.171875 -3.421875l-1.171875 3.421875l-0.65625 0l-1.109375 -4.953125l-0.25 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.671875 0l0.9375 4.21875l1.140625 -3.375l0.640625 0l1.171875 3.375l0.90625 -4.21875l-0.671875 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.25 0l-1.09375 4.953125zm6.2387695 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.129395 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm4.6450195 -2.765625l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm7.1293945 -2.46875l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm17.305664 4.8125q0 -0.734375 0.1875 -1.546875q0.1875 -0.828125 0.71875 -1.890625q0.546875 -1.078125 0.796875 -1.296875q0.078125 -0.078125 0.171875 -0.078125q0.109375 0 0.1875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.0625 -0.046875 0.140625q-0.6875 1.28125 -1.0 2.328125q-0.296875 1.03125 -0.296875 2.078125q0 1.046875 0.296875 2.09375q0.3125 1.03125 1.0 2.3125q0.046875 0.078125 0.046875 0.140625q0 0.09375 -0.078125 0.171875q-0.078125 0.09375 -0.1875 0.09375q-0.09375 0 -0.171875 -0.078125q-0.234375 -0.21875 -0.765625 -1.265625q-0.53125 -1.046875 -0.734375 -1.84375q-0.203125 -0.8125 -0.203125 -1.625zm9.61377 -1.984375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm15.602539 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.86377 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm11.571289 -0.640625q0.5 -0.71875 1.015625 -1.0625q0.53125 -0.359375 1.171875 -0.359375q0.84375 0 1.5 0.703125q0.671875 0.703125 0.671875 1.75q0 0.953125 -0.609375 1.75q-0.609375 0.78125 -1.65625 0.78125q-0.703125 0 -1.3125 -0.421875q-0.59375 -0.421875 -0.921875 -1.3125q-0.4375 -1.09375 -0.4375 -2.421875q0 -1.015625 0.40625 -1.875q0.296875 -0.65625 0.796875 -1.15625q0.515625 -0.515625 1.1875 -0.828125q0.6875 -0.328125 1.46875 -0.328125q0.53125 0 0.890625 0.21875q0.15625 0.09375 0.15625 0.25q0 0.109375 -0.078125 0.1875q-0.0625 0.078125 -0.171875 0.078125q-0.078125 0 -0.1875 -0.0625q-0.265625 -0.140625 -0.65625 -0.140625q-1.234375 0 -2.265625 1.078125q-1.015625 1.0625 -1.015625 2.515625q0 0.21875 0.046875 0.65625zm0.125 0.890625q0.234375 1.15625 0.75 1.65625q0.515625 0.484375 1.21875 0.484375q0.71875 0 1.21875 -0.546875q0.5 -0.5625 0.5 -1.453125q0 -0.828125 -0.515625 -1.375q-0.5 -0.546875 -1.140625 -0.546875q-0.609375 0 -1.1875 0.53125q-0.375 0.34375 -0.84375 1.25zm10.254395 0.25l-3.53125 0l0 -0.609375l2.96875 -5.125l1.109375 0l0 5.203125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.125 -0.078125 0.203125q-0.078125 0.0625 -0.28125 0.0625l-0.4375 0l0 1.703125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.0 0l0 -1.703125zm0 -0.53125l0 -4.65625l-0.28125 0l-2.6875 4.65625l2.96875 0zm6.9731445 -0.390625q0 0.734375 -0.203125 1.546875q-0.1875 0.8125 -0.734375 1.890625q-0.53125 1.078125 -0.78125 1.296875q-0.078125 0.078125 -0.15625 0.078125q-0.125 0 -0.203125 -0.09375q-0.078125 -0.078125 -0.078125 -0.171875q0 -0.0625 0.046875 -0.140625q0.703125 -1.28125 1.0 -2.3125q0.296875 -1.046875 0.296875 -2.09375q0 -1.046875 -0.296875 -2.078125q-0.296875 -1.046875 -1.0 -2.328125q-0.046875 -0.078125 -0.046875 -0.140625q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.203125 -0.078125q0.078125 0 0.15625 0.078125q0.234375 0.203125 0.765625 1.25q0.546875 1.046875 0.75 1.859375q0.203125 0.8125 0.203125 1.625z" fill-rule="nonzero"/><path fill="#000000" d="m807.3965 701.12225l0 6.359375l1.828125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.828125 0l0 -6.359375l-1.828125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l4.1875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.828125 0zm6.3793945 3.84375l0 2.515625l1.828125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.09375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.359375l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l3.109375 0q1.09375 0 1.78125 0.65625q0.703125 0.640625 0.703125 1.5q0 0.515625 -0.234375 0.9375q-0.21875 0.40625 -0.53125 0.640625q-0.484375 0.359375 -0.984375 0.515625q-0.375 0.125 -0.921875 0.125l-1.65625 0zm0 -0.53125l1.6875 0q0.59375 0 1.109375 -0.265625q0.515625 -0.265625 0.75 -0.640625q0.25 -0.390625 0.25 -0.78125q0 -0.625 -0.546875 -1.125q-0.53125 -0.5 -1.359375 -0.5l-1.890625 0l0 3.3125zm17.024414 -4.65625l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.27002 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm16.72754 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.8168945 0.28125l2.4375 2.34375q0.25 0 0.3125 0.03125q0.0625 0.015625 0.109375 0.09375q0.046875 0.0625 0.046875 0.140625q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.890625 0l-2.078125 -1.984375l-2.0625 1.984375l0.890625 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.078125 0.046875 -0.140625q0.046875 -0.078125 0.109375 -0.09375q0.0625 -0.03125 0.296875 -0.03125l2.453125 -2.34375l-2.171875 -2.078125q-0.234375 0 -0.296875 -0.03125q-0.0625 -0.03125 -0.109375 -0.09375q-0.046875 -0.0625 -0.046875 -0.15625q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.640625 0l1.796875 1.734375l1.8125 -1.734375l-0.640625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.046875 0.140625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.03125 -0.296875 0.03125l-2.171875 2.078125zm5.4262695 -2.625l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm8.066895 0.28125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.6762695 -1.796875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm4.4887695 -0.546875l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm12.446289 -2.765625l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.86377 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm11.399414 -5.234375l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.7387695 2.65625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm10.821289 -2.34375l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.05127 5.5l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm8.20752 -4.953125l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm3.8168945 -3.015625l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm17.00879 3.015625l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm11.035645 2.328125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.2856445 3.15625l-0.65625 0l-1.171875 -3.421875l-1.171875 3.421875l-0.65625 0l-1.109375 -4.953125l-0.25 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.671875 0l0.9375 4.21875l1.140625 -3.375l0.640625 0l1.171875 3.375l0.90625 -4.21875l-0.671875 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.25 0l-1.09375 4.953125zm8.848145 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm16.50879 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm7.8012695 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.254395 5.5l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm3.9731445 -5.5l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm4.0981445 -2.59375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm10.64502 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm5.9418945 3.609375l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25z" fill-rule="nonzero"/><path fill="#000000" d="m698.1377 716.0441l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm4.8950195 -5.5l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm7.9731445 -5.234375l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm9.004395 6.71875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m791.41895 718.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm15.071289 -3.96875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.39502 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm11.524414 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.2231445 2.734375l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875z" fill-rule="nonzero"/><path fill="#000000" d="m910.71924 718.341q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm6.404419 -2.765625l0 1.40625l-1.59375 0l0 -1.40625l1.59375 0zm0.171875 2.53125l0 4.578125l1.609375 0q0.46875 0 0.671875 0.1875q0.21875 0.171875 0.21875 0.484375q0 0.28125 -0.21875 0.46875q-0.203125 0.1875 -0.671875 0.1875l-4.546875 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l1.609375 0l0 -3.25l-1.078125 0q-0.46875 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l2.40625 0zm5.685669 5.171875l0 2.1875l0.796875 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.296875 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.359375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -6.03125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0l0 0.453125q0.46875 -0.3125 0.96875 -0.46875q0.5 -0.15625 1.03125 -0.15625q1.359375 0 2.328125 0.921875q0.96875 0.921875 0.96875 2.125q0 1.3125 -1.140625 2.171875q-0.953125 0.71875 -2.140625 0.71875q-0.515625 0 -1.015625 -0.140625q-0.5 -0.15625 -1.0 -0.453125zm3.953125 -2.296875q0 -0.28125 -0.21875 -0.703125q-0.21875 -0.4375 -0.6875 -0.71875q-0.453125 -0.296875 -1.0625 -0.296875q-1.0 0 -1.59375 0.75q-0.390625 0.515625 -0.390625 0.984375q0 0.53125 0.5625 1.046875q0.578125 0.5 1.421875 0.5q0.84375 0 1.40625 -0.5q0.5625 -0.5 0.5625 -1.0625zm9.388794 7.03125l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm2.62323 -12.4375l0 2.984375q0.5 -0.3125 1.0 -0.46875q0.5 -0.15625 1.015625 -0.15625q1.390625 0 2.34375 0.953125q0.96875 0.953125 0.96875 2.3125q0 1.296875 -0.921875 2.171875q-0.90625 0.859375 -2.421875 0.859375q-0.53125 0 -1.03125 -0.140625q-0.484375 -0.140625 -0.953125 -0.40625l0 0.328125l-1.5625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.6875 -0.1875l0.234375 0l0 -5.78125l-0.234375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.5625 0zm4.0 5.65625q0 -0.828125 -0.59375 -1.390625q-0.578125 -0.578125 -1.40625 -0.578125q-0.84375 0 -1.421875 0.578125q-0.578125 0.5625 -0.578125 1.375q0 0.734375 0.515625 1.203125q0.53125 0.46875 1.484375 0.46875q0.953125 0 1.46875 -0.46875q0.53125 -0.46875 0.53125 -1.1875zm6.888794 2.78125l0 -0.3125q-0.5 0.265625 -1.109375 0.390625q-0.609375 0.140625 -1.09375 0.140625q-1.078125 0 -1.75 -0.5625q-0.671875 -0.578125 -0.671875 -1.265625q0 -0.84375 0.859375 -1.5625q0.859375 -0.71875 2.359375 -0.71875q0.609375 0 1.40625 0.140625l0 -0.328125q0 -0.296875 -0.265625 -0.484375q-0.25 -0.1875 -0.96875 -0.1875q-0.59375 0 -1.546875 0.234375q-0.34375 0.078125 -0.546875 0.078125q-0.265625 0 -0.453125 -0.1875q-0.171875 -0.1875 -0.171875 -0.484375q0 -0.171875 0.0625 -0.296875q0.0625 -0.125 0.171875 -0.203125q0.125 -0.078125 0.5 -0.171875q0.484375 -0.140625 1.0 -0.21875q0.515625 -0.078125 0.9375 -0.078125q1.234375 0 1.921875 0.53125q0.6875 0.53125 0.6875 1.46875l0 2.75l0.234375 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.5625 0zm0 -2.390625q-0.796875 -0.15625 -1.484375 -0.15625q-0.8125 0 -1.390625 0.40625q-0.375 0.25 -0.375 0.5q0 0.203125 0.1875 0.3125q0.3125 0.21875 0.890625 0.21875q0.46875 0 1.078125 -0.1875q0.609375 -0.1875 1.09375 -0.515625l0 -0.578125zm8.232544 -1.953125q-0.328125 -0.203125 -0.6875 -0.296875q-0.34375 -0.109375 -0.734375 -0.109375q-0.78125 0 -1.234375 0.25q-0.203125 0.109375 -0.203125 0.25q0 0.140625 0.265625 0.28125q0.21875 0.109375 0.9375 0.203125q1.328125 0.1875 1.84375 0.375q0.6875 0.234375 1.046875 0.71875q0.375 0.46875 0.375 1.0q0 0.703125 -0.625 1.1875q-0.90625 0.703125 -2.34375 0.703125q-0.578125 0 -1.078125 -0.109375q-0.484375 -0.09375 -0.890625 -0.296875q-0.109375 0.09375 -0.21875 0.140625q-0.109375 0.046875 -0.21875 0.046875q-0.3125 0 -0.5 -0.203125q-0.1875 -0.21875 -0.1875 -0.6875l0 -0.453125q0 -0.484375 0.1875 -0.6875q0.1875 -0.203125 0.484375 -0.203125q0.234375 0 0.390625 0.140625q0.171875 0.125 0.265625 0.453125q0.296875 0.25 0.71875 0.390625q0.4375 0.125 1.0 0.125q0.921875 0 1.421875 -0.28125q0.25 -0.140625 0.25 -0.296875q0 -0.265625 -0.34375 -0.4375q-0.34375 -0.15625 -1.421875 -0.28125q-1.609375 -0.171875 -2.15625 -0.65625q-0.53125 -0.46875 -0.53125 -1.171875q0 -0.703125 0.59375 -1.1875q0.828125 -0.640625 2.15625 -0.640625q0.453125 0 0.875 0.09375q0.4375 0.078125 0.828125 0.25q0.125 -0.078125 0.234375 -0.125q0.109375 -0.046875 0.1875 -0.046875q0.28125 0 0.453125 0.203125q0.1875 0.203125 0.1875 0.6875l0 0.328125q0 0.4375 -0.09375 0.59375q-0.21875 0.296875 -0.578125 0.296875q-0.234375 0 -0.421875 -0.140625q-0.171875 -0.15625 -0.234375 -0.40625zm9.90448 2.0625l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm9.810669 7.609375l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm7.654419 -6.28125l-5.46875 0q0.203125 0.53125 0.734375 0.84375q0.53125 0.3125 1.4375 0.3125q0.75 0 1.96875 -0.3125q0.515625 -0.125 0.703125 -0.125q0.265625 0 0.453125 0.1875q0.1875 0.1875 0.1875 0.46875q0 0.265625 -0.203125 0.4375q-0.265625 0.25 -1.28125 0.46875q-1.0 0.21875 -1.921875 0.21875q-1.609375 0 -2.578125 -0.90625q-0.953125 -0.90625 -0.953125 -2.234375q0 -1.40625 1.03125 -2.28125q1.046875 -0.875 2.40625 -0.875q0.8125 0 1.484375 0.28125q0.6875 0.28125 1.015625 0.609375q0.46875 0.484375 0.78125 1.203125q0.203125 0.484375 0.203125 1.140625l0 0.5625zm-1.46875 -1.328125q-0.3125 -0.578125 -0.8125 -0.859375q-0.484375 -0.28125 -1.171875 -0.28125q-0.671875 0 -1.171875 0.28125q-0.5 0.28125 -0.8125 0.859375l3.96875 0zm4.779419 -2.296875l0 0.453125q0.359375 -0.3125 0.796875 -0.46875q0.4375 -0.15625 0.953125 -0.15625q1.1875 0 1.875 0.734375q0.546875 0.578125 0.546875 1.53125l0 2.484375q0.421875 0 0.625 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.203125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.1875 -0.46875q0.203125 -0.1875 0.640625 -0.1875l0 -2.53125q0 -0.421875 -0.234375 -0.625q-0.3125 -0.265625 -0.921875 -0.265625q-0.46875 0 -0.8125 0.1875q-0.34375 0.171875 -0.875 0.75l0 2.484375q0.5 0 0.65625 0.09375q0.3125 0.1875 0.3125 0.578125q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.359375 0.3125 -0.5625q0.15625 -0.09375 0.671875 -0.09375l0 -3.25q-0.421875 0 -0.625 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.28125 0zm9.357605 4.28125l1.4375 -2.953125q-0.546875 0 -0.6875 -0.09375q-0.328125 -0.203125 -0.328125 -0.578125q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.828125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.21875 0l-2.234375 4.578125l-1.390625 0l-2.234375 -4.578125l-0.1875 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l1.796875 0q0.46875 0 0.671875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.359375 -0.3125 0.5625q-0.15625 0.09375 -0.6875 0.09375l1.453125 2.953125zm11.670044 5.625l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm6.388794 -9.671875q0.234375 -0.21875 0.5 -0.21875q0.28125 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 0.859375q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.28125 0 -0.46875 -0.15625q-0.125 -0.125 -0.203125 -0.484375q-0.078125 -0.359375 -0.390625 -0.53125q-0.515625 -0.3125 -1.34375 -0.3125q-0.9375 0 -1.515625 0.5625q-0.5625 0.546875 -0.5625 1.390625q0 0.78125 0.546875 1.234375q0.546875 0.453125 1.8125 0.453125q0.828125 0 1.359375 -0.171875q0.3125 -0.109375 0.59375 -0.359375q0.28125 -0.25 0.5 -0.25q0.28125 0 0.46875 0.203125q0.203125 0.203125 0.203125 0.484375q0 0.4375 -0.59375 0.828125q-0.90625 0.59375 -2.640625 0.59375q-1.546875 0 -2.421875 -0.640625q-1.171875 -0.859375 -1.171875 -2.375q0 -1.421875 0.953125 -2.34375q0.953125 -0.9375 2.484375 -0.9375q0.546875 0 1.015625 0.109375q0.484375 0.09375 0.890625 0.296875zm5.904419 1.09375l0 3.25l1.90625 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-4.03125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.796875 0l0 -3.25l-0.640625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.28125 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.640625 0l0 -0.515625q0 -0.859375 0.65625 -1.4375q0.65625 -0.578125 1.890625 -0.578125q0.5625 0 1.28125 0.109375q0.71875 0.09375 0.92193604 0.28125q0.21875 0.171875 0.21875 0.453125q0 0.3125 -0.1875 0.515625q-0.18756104 0.1875 -0.45318604 0.1875q-0.125 0 -0.359375 -0.046875q-0.828125 -0.171875 -1.46875 -0.171875q-0.671875 0 -0.921875 0.203125q-0.25 0.203125 -0.25 0.484375l0 0.515625l2.0625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-2.0625 0zm9.482605 -0.9375l0 -0.390625l1.5625 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-0.234375 0l0 4.859375q0 0.703125 -0.296875 1.21875q-0.296875 0.53125 -0.90625 0.90625q-0.609375 0.375 -1.375 0.375l-1.515625 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.171875 -0.203125 -0.46875q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.46875 0q0.625 0 0.953125 -0.34375q0.34375 -0.328125 0.34375 -0.828125l0 -0.65625q-0.4375 0.296875 -0.90625 0.4375q-0.453125 0.140625 -0.9375 0.140625q-1.359375 0 -2.28125 -0.90625q-0.921875 -0.90625 -0.921875 -2.25q0 -1.328125 0.921875 -2.234375q0.921875 -0.921875 2.28125 -0.921875q0.5 0 0.953125 0.15625q0.46875 0.140625 0.890625 0.4375zm-0.015625 2.5625q0 -0.734375 -0.546875 -1.265625q-0.53125 -0.546875 -1.296875 -0.546875q-0.765625 0 -1.3125 0.546875q-0.53125 0.53125 -0.53125 1.265625q0 0.734375 0.53125 1.28125q0.546875 0.53125 1.3125 0.53125q0.765625 0 1.296875 -0.53125q0.546875 -0.546875 0.546875 -1.28125z" fill-rule="nonzero"/><path fill="#000000" d="m1036.4089 718.5129l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm7.8012695 -3.96875l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm10.52002 -6.4375l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm4.8950195 -5.5l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm7.9731445 -5.234375l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm9.004395 6.71875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" d="m697.0596 740.0129l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm7.3481445 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.4887695 -11.53125l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm4.5356445 -2.84375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.0043945 -5.234375l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.98877 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.5200195 -11.796875l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm8.05127 -0.546875l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm15.071289 -3.96875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.3637695 -2.34375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm8.254395 0l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.39502 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm11.524414 -5.234375l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm5.2231445 2.734375l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875zm17.10254 0l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm7.3481445 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.4887695 -11.53125l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm4.5356445 -2.84375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.0043945 -5.234375l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.98877 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.1606445 0.546875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m648.6667 17.0l-2.015747 782.01575" fill-rule="evenodd"/><path stroke="#000000" stroke-width="3.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="24.0,9.0" d="m648.6667 17.0l-2.015747 782.01575" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m28.031496 825.3753l618.6142 0l0 172.06299l-618.6142 0z" fill-rule="evenodd"/><path fill="#000000" d="m38.390873 852.29535l0 -13.359375l1.78125 0l0 11.78125l6.5625 0l0 1.578125l-8.34375 0zm16.875717 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.828842 6.5625l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.7499962 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.6718712 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.7031212 0 2.8124962 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.4531212 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.8906212 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.7812462 -0.90625 -1.8906212 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm15.953838 1.90625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141342 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.735092 -2.984375l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0z" fill-rule="nonzero"/><path fill="#000000" d="m37.875248 869.9985l1.65625 -0.140625q0.125 1.0 0.546875 1.640625q0.4375 0.640625 1.34375 1.046875q0.921875 0.390625 2.0625 0.390625q1.0 0 1.78125 -0.296875q0.78125 -0.296875 1.15625 -0.8125q0.375 -0.53125 0.375 -1.15625q0 -0.625 -0.375 -1.09375q-0.359375 -0.46875 -1.1875 -0.796875q-0.546875 -0.203125 -2.390625 -0.640625q-1.828125 -0.453125 -2.5625 -0.84375q-0.96875 -0.5 -1.4375 -1.234375q-0.46875 -0.75 -0.46875 -1.671875q0 -1.0 0.578125 -1.875q0.578125 -0.890625 1.671875 -1.34375q1.109375 -0.453125 2.453125 -0.453125q1.484375 0 2.609375 0.484375q1.140625 0.46875 1.75 1.40625q0.609375 0.921875 0.65625 2.09375l-1.6875 0.125q-0.140625 -1.265625 -0.9375 -1.90625q-0.78125 -0.65625 -2.3125 -0.65625q-1.609375 0 -2.34375 0.59375q-0.734375 0.59375 -0.734375 1.421875q0 0.71875 0.53125 1.171875q0.5 0.46875 2.65625 0.96875q2.15625 0.484375 2.953125 0.84375q1.171875 0.53125 1.71875 1.359375q0.5625 0.828125 0.5625 1.90625q0 1.0625 -0.609375 2.015625q-0.609375 0.9375 -1.75 1.46875q-1.140625 0.515625 -2.578125 0.515625q-1.8125 0 -3.046875 -0.53125q-1.21875 -0.53125 -1.921875 -1.59375q-0.6875 -1.0625 -0.71875 -2.40625zm18.990448 8.0l0 -4.734375q-0.375 0.546875 -1.0625 0.90625q-0.6875 0.34375 -1.46875 0.34375q-1.71875 0 -2.96875 -1.375q-1.234375 -1.375 -1.234375 -3.765625q0 -1.46875 0.5 -2.625q0.515625 -1.15625 1.46875 -1.75q0.96875 -0.59375 2.109375 -0.59375q1.796875 0 2.828125 1.515625l0 -1.296875l1.46875 0l0 13.375l-1.640625 0zm-5.046875 -8.5625q0 1.859375 0.78125 2.796875q0.78125 0.9375 1.875 0.9375q1.046875 0 1.796875 -0.890625q0.765625 -0.890625 0.765625 -2.703125q0 -1.9375 -0.796875 -2.90625q-0.796875 -0.96875 -1.875 -0.96875q-1.0625 0 -1.8125 0.90625q-0.734375 0.90625 -0.734375 2.828125zm15.594463 4.859375l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.8593712 0 -1.6093712 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.2343712 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm10.360092 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.188217 4.859375l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm12.853302 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.824646 5.765625l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm8.281967 0.0625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm8.203842 4.84375l3.53125 -5.03125l-3.265625 -4.640625l2.046875 0l1.484375 2.265625q0.421875 0.640625 0.671875 1.078125q0.40625 -0.59375 0.734375 -1.0625l1.640625 -2.28125l1.953125 0l-3.34375 4.546875l3.59375 5.125l-2.015625 0l-1.984375 -3.0l-0.515625 -0.8125l-2.546875 3.8125l-1.984375 0zm17.046875 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485092 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.4375 -4.921875l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm9.522858 -4.296875l1.65625 -0.140625q0.125 1.0 0.546875 1.640625q0.4375 0.640625 1.34375 1.046875q0.921875 0.390625 2.0625 0.390625q1.0 0 1.78125 -0.296875q0.78125 -0.296875 1.15625 -0.8125q0.375 -0.53125 0.375 -1.15625q0 -0.625 -0.375 -1.09375q-0.359375 -0.46875 -1.1875 -0.796875q-0.546875 -0.203125 -2.390625 -0.640625q-1.828125 -0.453125 -2.5625 -0.84375q-0.96875 -0.5 -1.4375 -1.234375q-0.46875 -0.75 -0.46875 -1.671875q0 -1.0 0.578125 -1.875q0.578125 -0.890625 1.671875 -1.34375q1.109375 -0.453125 2.453125 -0.453125q1.484375 0 2.609375 0.484375q1.140625 0.46875 1.75 1.40625q0.609375 0.921875 0.65625 2.09375l-1.6875 0.125q-0.140625 -1.265625 -0.9375 -1.90625q-0.78125 -0.65625 -2.3125 -0.65625q-1.609375 0 -2.34375 0.59375q-0.734375 0.59375 -0.734375 1.421875q0 0.71875 0.53125 1.171875q0.5 0.46875 2.65625 0.96875q2.15625 0.484375 2.953125 0.84375q1.171875 0.53125 1.71875 1.359375q0.5625 0.828125 0.5625 1.90625q0 1.0625 -0.609375 2.015625q-0.609375 0.9375 -1.75 1.46875q-1.140625 0.515625 -2.578125 0.515625q-1.8125 0 -3.046875 -0.53125q-1.21875 -0.53125 -1.921875 -1.59375q-0.6875 -1.0625 -0.71875 -2.40625zm16.849823 4.296875l-5.171875 -13.359375l1.921875 0l3.46875 9.703125q0.421875 1.171875 0.703125 2.1875q0.3125 -1.09375 0.71875 -2.1875l3.609375 -9.703125l1.796875 0l-5.234375 13.359375l-1.8125 0zm13.611252 0l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm14.931427 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.563217 4.84375l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.610092 4.828125l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm4.000717 0l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816696 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485092 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.933319 3.125l3.875 -13.8125l1.3125 0l-3.859375 13.8125l-1.328125 0zm11.600983 -11.703125l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.144806 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230164 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm6.618927 0l0 -8.40625l-1.453125 0l0 -1.265625l1.453125 0l0 -1.03125q0 -0.96875 0.171875 -1.453125q0.234375 -0.640625 0.828125 -1.03125q0.59375 -0.390625 1.671875 -0.390625q0.6875 0 1.53125 0.15625l-0.25 1.4375q-0.5 -0.09375 -0.953125 -0.09375q-0.75 0 -1.0625 0.328125q-0.3125 0.3125 -0.3125 1.1875l0 0.890625l1.890625 0l0 1.265625l-1.890625 0l0 8.40625l-1.625 0zm11.105194 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm10.516357 1.3125l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm9.640625 0.4375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485107 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm18.292664 6.8125q-1.359375 -1.703125 -2.296875 -4.0q-0.9375 -2.296875 -0.9375 -4.765625q0 -2.15625 0.703125 -4.140625q0.828125 -2.3125 2.53125 -4.59375l1.171875 0q-1.09375 1.890625 -1.453125 2.703125q-0.546875 1.25 -0.875 2.625q-0.390625 1.703125 -0.390625 3.421875q0 4.375 2.71875 8.75l-1.171875 0zm2.431427 -6.8125l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm7.917694 0.28125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm7.7819824 3.390625l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051636 -10.0l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457336 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm4.09375 7.46875l-1.1875 0q2.734375 -4.375 2.734375 -8.75q0 -1.71875 -0.390625 -3.390625q-0.3125 -1.375 -0.875 -2.625q-0.359375 -0.828125 -1.46875 -2.734375l1.1875 0q1.703125 2.28125 2.53125 4.59375q0.6875 1.984375 0.6875 4.140625q0 2.46875 -0.9375 4.765625q-0.9375 2.296875 -2.28125 4.0z" fill-rule="nonzero"/><path fill="#000000" d="m38.500248 896.29535l0 -13.359375l5.921875 0q1.78125 0 2.703125 0.359375q0.9375 0.359375 1.484375 1.28125q0.5625 0.90625 0.5625 2.015625q0 1.40625 -0.921875 2.390625q-0.921875 0.96875 -2.84375 1.234375q0.703125 0.34375 1.078125 0.671875q0.765625 0.703125 1.453125 1.765625l2.328125 3.640625l-2.21875 0l-1.765625 -2.78125q-0.78125 -1.203125 -1.28125 -1.828125q-0.5 -0.640625 -0.90625 -0.890625q-0.390625 -0.265625 -0.796875 -0.359375q-0.296875 -0.078125 -0.984375 -0.078125l-2.046875 0l0 5.9375l-1.765625 0zm1.765625 -7.453125l3.796875 0q1.21875 0 1.890625 -0.25q0.6875 -0.265625 1.046875 -0.8125q0.359375 -0.546875 0.359375 -1.1875q0 -0.953125 -0.6875 -1.5625q-0.6875 -0.609375 -2.1875 -0.609375l-4.21875 0l0 4.421875zm10.863571 2.609375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.625713 4.84375l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.6093712 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.6562462 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm4.047592 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906967 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406967 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.965271 4.828125l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm8.281967 0.0625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm8.203842 4.84375l3.53125 -5.03125l-3.265625 -4.640625l2.046875 0l1.484375 2.265625q0.421875 0.640625 0.671875 1.078125q0.40625 -0.59375 0.734375 -1.0625l1.640625 -2.28125l1.953125 0l-3.34375 4.546875l3.59375 5.125l-2.015625 0l-1.984375 -3.0l-0.515625 -0.8125l-2.546875 3.8125l-1.984375 0zm17.046875 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485092 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.4375 -4.921875l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm9.522858 -4.296875l1.65625 -0.140625q0.125 1.0 0.546875 1.640625q0.4375 0.640625 1.34375 1.046875q0.921875 0.390625 2.0625 0.390625q1.0 0 1.78125 -0.296875q0.78125 -0.296875 1.15625 -0.8125q0.375 -0.53125 0.375 -1.15625q0 -0.625 -0.375 -1.09375q-0.359375 -0.46875 -1.1875 -0.796875q-0.546875 -0.203125 -2.390625 -0.640625q-1.828125 -0.453125 -2.5625 -0.84375q-0.96875 -0.5 -1.4375 -1.234375q-0.46875 -0.75 -0.46875 -1.671875q0 -1.0 0.578125 -1.875q0.578125 -0.890625 1.671875 -1.34375q1.109375 -0.453125 2.453125 -0.453125q1.484375 0 2.609375 0.484375q1.140625 0.46875 1.75 1.40625q0.609375 0.921875 0.65625 2.09375l-1.6875 0.125q-0.140625 -1.265625 -0.9375 -1.90625q-0.78125 -0.65625 -2.3125 -0.65625q-1.609375 0 -2.34375 0.59375q-0.734375 0.59375 -0.734375 1.421875q0 0.71875 0.53125 1.171875q0.5 0.46875 2.65625 0.96875q2.15625 0.484375 2.953125 0.84375q1.171875 0.53125 1.71875 1.359375q0.5625 0.828125 0.5625 1.90625q0 1.0625 -0.609375 2.015625q-0.609375 0.9375 -1.75 1.46875q-1.140625 0.515625 -2.578125 0.515625q-1.8125 0 -3.046875 -0.53125q-1.21875 -0.53125 -1.921875 -1.59375q-0.6875 -1.0625 -0.71875 -2.40625zm16.849823 4.296875l-5.171875 -13.359375l1.921875 0l3.46875 9.703125q0.421875 1.171875 0.703125 2.1875q0.3125 -1.09375 0.71875 -2.1875l3.609375 -9.703125l1.796875 0l-5.234375 13.359375l-1.8125 0zm19.923752 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.96875 3.546875l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.504196 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5475922 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.328125 0l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485107 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm18.292664 6.8125q-1.359375 -1.703125 -2.296875 -4.0q-0.9375 -2.296875 -0.9375 -4.765625q0 -2.15625 0.703125 -4.140625q0.828125 -2.3125 2.53125 -4.59375l1.171875 0q-1.09375 1.890625 -1.453125 2.703125q-0.546875 1.25 -0.875 2.625q-0.390625 1.703125 -0.390625 3.421875q0 4.375 2.71875 8.75l-1.171875 0zm9.353302 -3.921875l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.203827 8.546875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm9.40625 -3.71875l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.688232 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm15.540802 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457306 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm4.09375 7.46875l-1.1875 0q2.734375 -4.375 2.734375 -8.75q0 -1.71875 -0.390625 -3.390625q-0.3125 -1.375 -0.875 -2.625q-0.359375 -0.828125 -1.46875 -2.734375l1.1875 0q1.703125 2.28125 2.53125 4.59375q0.6875 1.984375 0.6875 4.140625q0 2.46875 -0.9375 4.765625q-0.9375 2.296875 -2.28125 4.0z" fill-rule="nonzero"/><path fill="#000000" d="m38.390873 918.29535l0 -13.359375l5.015625 0q1.53125 0 2.453125 0.40625q0.921875 0.40625 1.4375 1.25q0.53125 0.84375 0.53125 1.765625q0 0.859375 -0.46875 1.625q-0.453125 0.75 -1.390625 1.203125q1.203125 0.359375 1.859375 1.21875q0.65625 0.859375 0.65625 2.015625q0 0.9375 -0.40625 1.75q-0.390625 0.796875 -0.984375 1.234375q-0.578125 0.4375 -1.453125 0.671875q-0.875 0.21875 -2.15625 0.21875l-5.09375 0zm1.78125 -7.75l2.875 0q1.1875 0 1.6875 -0.140625q0.671875 -0.203125 1.015625 -0.671875q0.34375 -0.46875 0.34375 -1.171875q0 -0.65625 -0.328125 -1.15625q-0.3125 -0.515625 -0.90625 -0.703125q-0.59375 -0.1875 -2.03125 -0.1875l-2.65625 0l0 4.03125zm0 6.171875l3.3125 0q0.859375 0 1.203125 -0.0625q0.609375 -0.109375 1.015625 -0.359375q0.421875 -0.265625 0.6875 -0.75q0.265625 -0.484375 0.265625 -1.125q0 -0.75 -0.390625 -1.296875q-0.375 -0.546875 -1.0625 -0.765625q-0.671875 -0.234375 -1.953125 -0.234375l-3.078125 0l0 4.59375zm10.490448 1.578125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.519821 0l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm10.672588 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.559021 5.765625l0 -13.359375l5.921875 0q1.78125 0 2.703125 0.359375q0.9375 0.359375 1.484375 1.28125q0.5625 0.90625 0.5625 2.015625q0 1.40625 -0.921875 2.390625q-0.921875 0.96875 -2.84375 1.234375q0.703125 0.34375 1.078125 0.671875q0.765625 0.703125 1.453125 1.765625l2.328125 3.640625l-2.21875 0l-1.765625 -2.78125q-0.78125 -1.203125 -1.28125 -1.828125q-0.5 -0.640625 -0.90625 -0.890625q-0.390625 -0.265625 -0.796875 -0.359375q-0.296875 -0.078125 -0.984375 -0.078125l-2.046875 0l0 5.9375l-1.765625 0zm1.765625 -7.453125l3.796875 0q1.21875 0 1.890625 -0.25q0.6875 -0.265625 1.046875 -0.8125q0.359375 -0.546875 0.359375 -1.1875q0 -0.953125 -0.6875 -1.5625q-0.6875 -0.609375 -2.1875 -0.609375l-4.21875 0l0 4.421875zm18.097946 4.34375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.453842 2.21875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm6.59375 2.078125l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm7.917679 0.28125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203842 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.063217 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm9.281967 5.015625l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816696 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm16.105896 5.765625l-2.96875 -9.671875l1.703125 0l1.53125 5.578125l0.578125 2.078125q0.046875 -0.15625 0.5 -2.0l1.546875 -5.65625l1.6875 0l1.4375 5.609375l0.484375 1.84375l0.5625 -1.859375l1.65625 -5.59375l1.59375 0l-3.03125 9.671875l-1.703125 0l-1.53125 -5.796875l-0.375 -1.640625l-1.953125 7.4375l-1.71875 0zm11.691696 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm7.722946 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051788 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm15.949646 0l0 -8.40625l-1.453125 0l0 -1.265625l1.453125 0l0 -1.03125q0 -0.96875 0.171875 -1.453125q0.234375 -0.640625 0.828125 -1.03125q0.59375 -0.390625 1.671875 -0.390625q0.6875 0 1.53125 0.15625l-0.25 1.4375q-0.5 -0.09375 -0.953125 -0.09375q-0.75 0 -1.0625 0.328125q-0.3125 0.3125 -0.3125 1.1875l0 0.890625l1.890625 0l0 1.265625l-1.890625 0l0 8.40625l-1.625 0zm4.183304 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.250717 4.84375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.457321 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906967 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406967 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.6406403 0l0 13.359375l-1.5312653 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm20.777786 1.28125l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.40625 -1.296875q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.281952 4.84375l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm6.228302 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm6.681427 -7.8125l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm16.225983 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.40625 -1.296875q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.563232 4.84375l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906982 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.824646 5.765625l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm8.844482 4.90625l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm3.5823364 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.610107 1.296875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.015625 3.546875l0 -13.359375l1.640625 0l0 7.625l3.890625 -3.9375l2.109375 0l-3.6875 3.59375l4.0625 6.078125l-2.015625 0l-3.203125 -4.953125l-1.15625 1.125l0 3.828125l-1.640625 0zm8.671875 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm18.292664 6.8125q-1.359375 -1.703125 -2.296875 -4.0q-0.9375 -2.296875 -0.9375 -4.765625q0 -2.15625 0.703125 -4.140625q0.828125 -2.3125 2.53125 -4.59375l1.171875 0q-1.09375 1.890625 -1.453125 2.703125q-0.546875 1.25 -0.875 2.625q-0.390625 1.703125 -0.390625 3.421875q0 4.375 2.71875 8.75l-1.171875 0zm3.087677 -15.390625l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.144806 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.375732 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm7.7229614 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051636 -10.0l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457336 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1569824 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.6135864 0l0 -1.875l1.875 0l0 1.875q0 1.03125 -0.375 1.65625q-0.359375 0.640625 -1.15625 0.984375l-0.453125 -0.703125q0.515625 -0.21875 0.765625 -0.671875q0.25 -0.4375 0.28125 -1.265625l-0.9375 0zm13.522827 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm7.9176636 0.28125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5476074 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.984375 2.890625l0 -13.359375l1.640625 0l0 7.625l3.890625 -3.9375l2.109375 0l-3.6875 3.59375l4.0625 6.078125l-2.015625 0l-3.203125 -4.953125l-1.15625 1.125l0 3.828125l-1.640625 0zm8.671875 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.40625 2.890625l0 -1.875l1.875 0l0 1.875q0 1.03125 -0.375 1.65625q-0.359375 0.640625 -1.15625 0.984375l-0.453125 -0.703125q0.515625 -0.21875 0.765625 -0.671875q0.25 -0.4375 0.28125 -1.265625l-0.9375 0zm16.569702 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm12.719482 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm7.9176636 -2.078125l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm4.09375 7.46875l-1.1875 0q2.734375 -4.375 2.734375 -8.75q0 -1.71875 -0.390625 -3.390625q-0.3125 -1.375 -0.875 -2.625q-0.359375 -0.828125 -1.46875 -2.734375l1.1875 0q1.703125 2.28125 2.53125 4.59375q0.6875 1.984375 0.6875 4.140625q0 2.46875 -0.9375 4.765625q-0.9375 2.296875 -2.28125 4.0z" fill-rule="nonzero"/><path fill="#000000" d="m38.468998 940.29535l0 -13.359375l4.609375 0q1.546875 0 2.375 0.203125q1.140625 0.25 1.953125 0.953125q1.0625 0.890625 1.578125 2.28125q0.53125 1.390625 0.53125 3.171875q0 1.515625 -0.359375 2.703125q-0.359375 1.171875 -0.921875 1.9375q-0.546875 0.765625 -1.203125 1.21875q-0.65625 0.4375 -1.59375 0.671875q-0.9375 0.21875 -2.140625 0.21875l-4.828125 0zm1.765625 -1.578125l2.859375 0q1.3125 0 2.0625 -0.234375q0.75 -0.25 1.203125 -0.703125q0.625 -0.625 0.96875 -1.6875q0.359375 -1.0625 0.359375 -2.578125q0 -2.09375 -0.6875 -3.21875q-0.6875 -1.125 -1.671875 -1.5q-0.703125 -0.28125 -2.28125 -0.28125l-2.8125 0l0 10.203125zm10.894821 -3.265625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm12.875713 3.375l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.8906212 0 -1.3906212 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.6249962 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm5.183304 0l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230179 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406967 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.965271 4.828125l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm8.844467 4.90625l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm3.5823212 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.610092 1.296875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.015625 3.546875l0 -13.359375l1.640625 0l0 7.625l3.890625 -3.9375l2.109375 0l-3.6875 3.59375l4.0625 6.078125l-2.015625 0l-3.203125 -4.953125l-1.15625 1.125l0 3.828125l-1.640625 0zm8.671875 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.4375 -4.921875l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm10.413483 0l0 -13.359375l1.765625 0l0 13.359375l-1.765625 0zm4.683304 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.281967 -6.640625l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457321 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm9.328125 2.359375q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm7.781967 3.390625l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230179 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324646 5.765625l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688217 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203842 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641357 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235077 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485077 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm15.167694 -8.578125l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.1448364 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm9.719482 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.984375 -8.578125l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.410461 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906982 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324646 9.46875l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm15.203857 3.59375q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1882324 4.859375l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm12.853302 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141327 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm13.413452 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051636 -10.0l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm7.7229614 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.5270386 5.1875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125z" fill-rule="nonzero"/><path fill="#000000" d="m37.000248 962.29535l5.125 -13.359375l1.90625 0l5.46875 13.359375l-2.015625 0l-1.546875 -4.046875l-5.59375 0l-1.46875 4.046875l-1.875 0zm3.859375 -5.484375l4.53125 0l-1.40625 -3.703125q-0.625 -1.6875 -0.9375 -2.765625q-0.265625 1.28125 -0.71875 2.546875l-1.46875 3.921875zm9.802948 5.484375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm7.769821 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230175 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.1249962 0 -3.3749962 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.2656212 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.218746 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.0156212 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390621 -2.65625l5.406246 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.1249962 0 -1.9062462 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125713 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm6.228302 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.688217 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm7.781967 3.390625l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230179 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm20.590271 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.594467 3.640625q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5475922 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.984375 2.890625l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm21.871521 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203842 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm20.730896 4.828125l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm8.672592 -0.015625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm12.875717 3.375l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.288483 1.46875l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm8.844467 4.90625l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm3.5823212 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.610107 1.296875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.2031403 -1.296875 -1.2031403 -3.71875q0 -1.578125 0.51564026 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.015625 3.546875l0 -13.359375l1.640625 0l0 7.625l3.890625 -3.9375l2.109375 0l-3.6875 3.59375l4.0625 6.078125l-2.015625 0l-3.203125 -4.953125l-1.15625 1.125l0 3.828125l-1.640625 0zm8.671875 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.4375 -4.921875l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm16.225952 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.40625 -1.296875q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm15.540802 3.703125l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm8.281952 -0.0625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm13.413452 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.047607 5.765625l3.53125 -5.03125l-3.265625 -4.640625l2.046875 0l1.484375 2.265625q0.421875 0.640625 0.671875 1.078125q0.40625 -0.59375 0.734375 -1.0625l1.640625 -2.28125l1.953125 0l-3.34375 4.546875l3.59375 5.125l-2.015625 0l-1.984375 -3.0l-0.515625 -0.8125l-2.546875 3.8125l-1.984375 0zm10.421875 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm3.4885864 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9489136 -1.421875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm14.558289 -1.953125q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.328857 0l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1135864 3.71875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm14.589539 -15.1875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.1448364 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm22.184021 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.047607 5.765625l3.53125 -5.03125l-3.265625 -4.640625l2.046875 0l1.484375 2.265625q0.421875 0.640625 0.671875 1.078125q0.40625 -0.59375 0.734375 -1.0625l1.640625 -2.28125l1.953125 0l-3.34375 4.546875l3.59375 5.125l-2.015625 0l-1.984375 -3.0l-0.515625 -0.8125l-2.546875 3.8125l-1.984375 0zm14.0 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230164 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641357 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906982 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406982 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm14.965271 4.828125l0 -13.359375l1.765625 0l0 13.359375l-1.765625 0zm4.8864136 0l0 -13.359375l5.046875 0q1.328125 0 2.03125 0.125q0.96875 0.171875 1.640625 0.640625q0.671875 0.453125 1.078125 1.28125q0.40625 0.828125 0.40625 1.828125q0 1.703125 -1.09375 2.890625q-1.078125 1.171875 -3.921875 1.171875l-3.421875 0l0 5.421875l-1.765625 0zm1.765625 -7.0l3.453125 0q1.71875 0 2.4375 -0.640625q0.71875 -0.640625 0.71875 -1.796875q0 -0.84375 -0.421875 -1.4375q-0.421875 -0.59375 -1.125 -0.78125q-0.4375 -0.125 -1.640625 -0.125l-3.421875 0l0 4.78125zm18.898987 5.53125l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm3.1051636 1.46875l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125z" fill-rule="nonzero"/><path fill="#000000" d="m38.390873 984.29535l0 -13.359375l1.78125 0l0 11.78125l6.5625 0l0 1.578125l-8.34375 0zm10.250717 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm3.8323212 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm9.328842 5.015625l0 -13.359375l1.6406212 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.6406212 0zm13.953838 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm13.054108 1.46875l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm8.672592 -0.015625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm12.875717 3.375l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm5.183304 0l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230179 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406967 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm14.418396 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.191696 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.144821 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm17.000717 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485092 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.4375 -4.921875l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0zm10.413483 0l0 -13.359375l1.765625 0l0 13.359375l-1.765625 0zm4.683304 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.281967 -6.640625l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457321 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm9.328125 2.359375q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm7.781967 3.390625l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230179 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324661 5.765625l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688202 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641327 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235077 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm17.902771 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9957886 -3.375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm14.480896 -6.625l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.1448364 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm9.719482 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm7.9176636 0.28125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.688232 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm9.640625 0.4375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324646 9.46875l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm15.203857 3.59375q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5476074 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.328125 0l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406982 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm13.855896 -0.015625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm19.137146 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9957886 -3.375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm20.793396 1.296875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.40625 -1.296875q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm15.5407715 3.703125l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm8.281982 -0.0625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9489136 -1.421875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m673.0 829.2651l724.0 0l0 164.28351l-724.0 0z" fill-rule="evenodd"/><path fill="#000000" d="m683.3906 856.1851l0 -13.359375l2.65625 0l3.15625 9.453125q0.4375 1.328125 0.640625 1.984375q0.234375 -0.734375 0.703125 -2.140625l3.203125 -9.296875l2.375 0l0 13.359375l-1.703125 0l0 -11.171875l-3.875 11.171875l-1.59375 0l-3.859375 -11.375l0 11.375l-1.703125 0zm22.009521 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm12.719482 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6052246 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm9.766296 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm15.563232 4.84375l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm8.672607 -0.015625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.250671 4.84375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm3.5823364 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm8.985107 5.640625l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm9.250732 8.734375l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm9.859375 -11.53125l0 -1.859375l1.859375 0l0 1.859375l-1.859375 0zm0 7.8125l0 -1.875l1.859375 0l0 1.875l-1.859375 0z" fill-rule="nonzero"/><path fill="#000000" d="m700.3722 868.9039q1.0 0 1.96875 0.53125q0.96875 0.515625 1.5 1.484375q0.53125 0.96875 0.53125 2.0q0 1.671875 -1.171875 2.84375q-1.171875 1.171875 -2.828125 1.171875q-1.671875 0 -2.84375 -1.171875q-1.171875 -1.171875 -1.171875 -2.84375q0 -1.046875 0.53125 -2.0q0.546875 -0.96875 1.5 -1.484375q0.96875 -0.53125 1.984375 -0.53125z" fill-rule="nonzero"/><path fill="#000000" d="m731.3906 878.1851l0 -13.359375l2.65625 0l3.15625 9.453125q0.4375 1.328125 0.640625 1.984375q0.234375 -0.734375 0.703125 -2.140625l3.203125 -9.296875l2.375 0l0 13.359375l-1.703125 0l0 -11.171875l-3.875 11.171875l-1.59375 0l-3.859375 -11.375l0 11.375l-1.703125 0zm14.7751465 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm8.641357 1.953125l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm13.101013 -2.078125l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.40625 -1.296875q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297546 4.84375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm15.5408325 3.703125l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm8.281982 -0.0625q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297546 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9489136 -1.421875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm21.792664 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.047607 5.765625l3.53125 -5.03125l-3.265625 -4.640625l2.046875 0l1.484375 2.265625q0.421875 0.640625 0.671875 1.078125q0.40625 -0.59375 0.734375 -1.0625l1.640625 -2.28125l1.953125 0l-3.34375 4.546875l3.59375 5.125l-2.015625 0l-1.984375 -3.0l-0.515625 -0.8125l-2.546875 3.8125l-1.984375 0zm14.0 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230164 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641357 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906921 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406982 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm14.855896 4.828125l0 -8.40625l-1.453125 0l0 -1.265625l1.453125 0l0 -1.03125q0 -0.96875 0.171875 -1.453125q0.234375 -0.640625 0.828125 -1.03125q0.59375 -0.390625 1.671875 -0.390625q0.6875 0 1.53125 0.15625l-0.25 1.4375q-0.5 -0.09375 -0.953125 -0.09375q-0.75 0 -1.0625 0.328125q-0.3125 0.3125 -0.3125 1.1875l0 0.890625l1.890625 0l0 1.265625l-1.890625 0l0 8.40625l-1.625 0zm4.7770386 0l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm5.6189575 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm24.302246 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051636 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm20.637207 2.21875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.015625 -7.921875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.1447754 3.703125l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm7.3757324 8.484375l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm13.391357 -3.703125l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm15.203857 3.71875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5476074 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm16.105957 5.765625l-2.96875 -9.671875l1.703125 0l1.53125 5.578125l0.578125 2.078125q0.046875 -0.15625 0.5 -2.0l1.546875 -5.65625l1.6875 0l1.4375 5.609375l0.484375 1.84375l0.5625 -1.859375l1.65625 -5.59375l1.59375 0l-3.03125 9.671875l-1.703125 0l-1.53125 -5.796875l-0.375 -1.640625l-1.953125 7.4375l-1.71875 0zm11.69165 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm7.7229004 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6052246 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm19.137207 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051025 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.30896 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm6.2283936 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm3.8322754 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm9.328857 5.015625l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm13.953857 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm10.366577 0l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.5270996 5.1875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm9.40625 -0.015625l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm15.516357 1.671875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324585 9.46875l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm15.203857 3.59375q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1882324 4.859375l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm12.5407715 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm22.165771 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm12.719482 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230103 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0z" fill-rule="nonzero"/><path fill="#000000" d="m700.3722 890.9039q1.0 0 1.96875 0.53125q0.96875 0.515625 1.5 1.484375q0.53125 0.96875 0.53125 2.0q0 1.671875 -1.171875 2.84375q-1.171875 1.171875 -2.828125 1.171875q-1.671875 0 -2.84375 -1.171875q-1.171875 -1.171875 -1.171875 -2.84375q0 -1.046875 0.53125 -2.0q0.546875 -0.96875 1.5 -1.484375q0.96875 -0.53125 1.984375 -0.53125z" fill-rule="nonzero"/><path fill="#000000" d="m731.7344 900.1851l0 -13.359375l1.765625 0l0 13.359375l-1.765625 0zm10.948914 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm15.906982 1.71875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.453857 4.578125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1569214 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1448364 0l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1135864 3.71875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm8.442688 -3.71875l0 -1.875l1.875 0l0 1.875q0 1.03125 -0.375 1.65625q-0.359375 0.640625 -1.15625 0.984375l-0.453125 -0.703125q0.515625 -0.21875 0.765625 -0.671875q0.25 -0.4375 0.28125 -1.265625l-0.9375 0zm16.257263 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1569824 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1447754 0l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm12.953125 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230225 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485046 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.9489136 -1.421875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm21.49585 2.890625l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm3.3913574 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm17.90271 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6052246 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm13.668335 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.296875 1.703125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.359375q0.453125 -0.71875 1.203125 -1.140625q0.765625 -0.4375 1.71875 -0.4375q1.078125 0 1.765625 0.453125q0.6875 0.4375 0.96875 1.234375q1.15625 -1.6875 2.984375 -1.6875q1.453125 0 2.21875 0.796875q0.78125 0.796875 0.78125 2.453125l0 6.640625l-1.640625 0l0 -6.09375q0 -0.984375 -0.15625 -1.40625q-0.15625 -0.4375 -0.578125 -0.703125q-0.421875 -0.265625 -0.984375 -0.265625q-1.015625 0 -1.6875 0.6875q-0.671875 0.671875 -0.671875 2.15625l0 5.625l-1.640625 0l0 -6.28125q0 -1.09375 -0.40625 -1.640625q-0.40625 -0.546875 -1.3125 -0.546875q-0.6875 0 -1.28125 0.359375q-0.59375 0.359375 -0.859375 1.0625q-0.25 0.703125 -0.25 2.03125l0 5.015625l-1.640625 0zm22.165833 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.824646 5.765625l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm15.203857 3.71875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5475464 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm17.902771 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230225 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485107 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm13.10083 -2.078125l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm2.96875 3.546875l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.504272 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.5476074 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.328125 0l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm10.40625 -4.921875l0 -1.859375l1.875 0l0 1.859375l-1.875 0zm0 7.8125l0 -1.875l1.875 0l0 1.875q0 1.03125 -0.375 1.65625q-0.359375 0.640625 -1.15625 0.984375l-0.453125 -0.703125q0.515625 -0.21875 0.765625 -0.671875q0.25 -0.4375 0.28125 -1.265625l-0.9375 0zm9.335327 -4.84375q0 -2.6875 1.484375 -3.96875q1.25 -1.078125 3.046875 -1.078125q2.0 0 3.265625 1.3125q1.265625 1.296875 1.265625 3.609375q0 1.859375 -0.5625 2.9375q-0.5625 1.0625 -1.640625 1.65625q-1.0625 0.59375 -2.328125 0.59375q-2.03125 0 -3.28125 -1.296875q-1.25 -1.3125 -1.25 -3.765625zm1.6875 0q0 1.859375 0.796875 2.796875q0.8125 0.921875 2.046875 0.921875q1.21875 0 2.03125 -0.921875q0.8125 -0.9375 0.8125 -2.84375q0 -1.796875 -0.8125 -2.71875q-0.8125 -0.921875 -2.03125 -0.921875q-1.234375 0 -2.046875 0.921875q-0.796875 0.90625 -0.796875 2.765625zm9.297607 4.84375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.328857 0l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1135254 3.71875l-0.1875 -1.53125q0.546875 0.140625 0.9375 0.140625q0.546875 0 0.875 -0.1875q0.328125 -0.171875 0.546875 -0.5q0.15625 -0.25 0.5 -1.21875q0.046875 -0.140625 0.140625 -0.40625l-3.671875 -9.6875l1.765625 0l2.015625 5.59375q0.390625 1.078125 0.703125 2.25q0.28125 -1.125 0.671875 -2.203125l2.078125 -5.640625l1.640625 0l-3.6875 9.828125q-0.59375 1.609375 -0.921875 2.203125q-0.4375 0.8125 -1.0 1.1875q-0.5625 0.375 -1.34375 0.375q-0.484375 0 -1.0625 -0.203125zm18.167725 -5.1875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6052246 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm17.90271 4.296875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230103 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485107 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm6.132324 -1.421875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.297607 9.46875l0 -4.734375q-0.375 0.546875 -1.0625 0.90625q-0.6875 0.34375 -1.46875 0.34375q-1.71875 0 -2.96875 -1.375q-1.234375 -1.375 -1.234375 -3.765625q0 -1.46875 0.5 -2.625q0.515625 -1.15625 1.46875 -1.75q0.96875 -0.59375 2.109375 -0.59375q1.796875 0 2.828125 1.515625l0 -1.296875l1.46875 0l0 13.375l-1.640625 0zm-5.046875 -8.5625q0 1.859375 0.78125 2.796875q0.78125 0.9375 1.875 0.9375q1.046875 0 1.796875 -0.890625q0.765625 -0.890625 0.765625 -2.703125q0 -1.9375 -0.796875 -2.90625q-0.796875 -0.96875 -1.875 -0.96875q-1.0625 0 -1.8125 0.90625q-0.734375 0.90625 -0.734375 2.828125zm15.594482 4.859375l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm10.672607 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.688232 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm9.640625 0.4375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm14.324585 -5.703125l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm3.4886475 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125z" fill-rule="nonzero"/><path fill="#000000" d="m737.5469 918.63824l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.015625 3.546875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688232 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.063171 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm15.953857 1.90625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.406982 5.765625l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm20.793396 4.828125l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm3.3913574 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm9.984375 -8.578125l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm4.1447754 0l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm10.063232 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625zm18.090271 3.546875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm1.6051636 1.46875l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm17.000732 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm23.293396 -7.59375l1.765625 0l0 7.71875q0 2.015625 -0.453125 3.203125q-0.453125 1.1875 -1.640625 1.9375q-1.1875 0.734375 -3.125 0.734375q-1.875 0 -3.078125 -0.640625q-1.1875 -0.65625 -1.703125 -1.875q-0.5 -1.234375 -0.5 -3.359375l0 -7.71875l1.765625 0l0 7.71875q0 1.734375 0.3125 2.5625q0.328125 0.8125 1.109375 1.265625q0.796875 0.453125 1.9375 0.453125q1.953125 0 2.78125 -0.890625q0.828125 -0.890625 0.828125 -3.390625l0 -7.71875zm8.519836 13.359375l-5.171875 -13.359375l1.921875 0l3.46875 9.703125q0.421875 1.171875 0.703125 2.1875q0.3125 -1.09375 0.71875 -2.1875l3.609375 -9.703125l1.796875 0l-5.234375 13.359375l-1.8125 0zm8.5841675 0l0 -13.359375l2.65625 0l3.15625 9.453125q0.4375 1.328125 0.640625 1.984375q0.234375 -0.734375 0.703125 -2.140625l3.203125 -9.296875l2.375 0l0 13.359375l-1.703125 0l0 -11.171875l-3.875 11.171875l-1.59375 0l-3.859375 -11.375l0 11.375l-1.703125 0zm13.8689575 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm15.500732 -3.703125l0 -11.78125l-4.40625 0l0 -1.578125l10.578125 0l0 1.578125l-4.40625 0l0 11.78125l-1.765625 0zm8.020935 0l0 -13.359375l9.65625 0l0 1.578125l-7.875 0l0 4.09375l7.375 0l0 1.5625l-7.375 0l0 4.546875l8.1875 0l0 1.578125l-9.96875 0zm11.8186035 -4.296875l1.65625 -0.140625q0.125 1.0 0.546875 1.640625q0.4375 0.640625 1.34375 1.046875q0.921875 0.390625 2.0625 0.390625q1.0 0 1.78125 -0.296875q0.78125 -0.296875 1.15625 -0.8125q0.375 -0.53125 0.375 -1.15625q0 -0.625 -0.375 -1.09375q-0.359375 -0.46875 -1.1875 -0.796875q-0.546875 -0.203125 -2.390625 -0.640625q-1.828125 -0.453125 -2.5625 -0.84375q-0.96875 -0.5 -1.4375 -1.234375q-0.46875 -0.75 -0.46875 -1.671875q0 -1.0 0.578125 -1.875q0.578125 -0.890625 1.671875 -1.34375q1.109375 -0.453125 2.453125 -0.453125q1.484375 0 2.609375 0.484375q1.140625 0.46875 1.75 1.40625q0.609375 0.921875 0.65625 2.09375l-1.6875 0.125q-0.140625 -1.265625 -0.9375 -1.90625q-0.78125 -0.65625 -2.3125 -0.65625q-1.609375 0 -2.34375 0.59375q-0.734375 0.59375 -0.734375 1.421875q0 0.71875 0.53125 1.171875q0.5 0.46875 2.65625 0.96875q2.15625 0.484375 2.953125 0.84375q1.171875 0.53125 1.71875 1.359375q0.5625 0.828125 0.5625 1.90625q0 1.0625 -0.609375 2.015625q-0.609375 0.9375 -1.75 1.46875q-1.140625 0.515625 -2.578125 0.515625q-1.8125 0 -3.046875 -0.53125q-1.21875 -0.53125 -1.921875 -1.59375q-0.6875 -1.0625 -0.71875 -2.40625zm16.443542 4.296875l0 -11.78125l-4.40625 0l0 -1.578125l10.578125 0l0 1.578125l-4.40625 0l0 11.78125l-1.765625 0zm6.270996 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.500732 -8.0l1.65625 -0.140625q0.125 1.0 0.546875 1.640625q0.4375 0.640625 1.34375 1.046875q0.921875 0.390625 2.0625 0.390625q1.0 0 1.78125 -0.296875q0.78125 -0.296875 1.15625 -0.8125q0.375 -0.53125 0.375 -1.15625q0 -0.625 -0.375 -1.09375q-0.359375 -0.46875 -1.1875 -0.796875q-0.546875 -0.203125 -2.390625 -0.640625q-1.828125 -0.453125 -2.5625 -0.84375q-0.96875 -0.5 -1.4375 -1.234375q-0.46875 -0.75 -0.46875 -1.671875q0 -1.0 0.578125 -1.875q0.578125 -0.890625 1.671875 -1.34375q1.109375 -0.453125 2.453125 -0.453125q1.484375 0 2.609375 0.484375q1.140625 0.46875 1.75 1.40625q0.609375 0.921875 0.65625 2.09375l-1.6875 0.125q-0.140625 -1.265625 -0.9375 -1.90625q-0.78125 -0.65625 -2.3125 -0.65625q-1.609375 0 -2.34375 0.59375q-0.734375 0.59375 -0.734375 1.421875q0 0.71875 0.53125 1.171875q0.5 0.46875 2.65625 0.96875q2.15625 0.484375 2.953125 0.84375q1.171875 0.53125 1.71875 1.359375q0.5625 0.828125 0.5625 1.90625q0 1.0625 -0.609375 2.015625q-0.609375 0.9375 -1.75 1.46875q-1.140625 0.515625 -2.578125 0.515625q-1.8125 0 -3.046875 -0.53125q-1.21875 -0.53125 -1.921875 -1.59375q-0.6875 -1.0625 -0.71875 -2.40625zm13.0686035 4.296875l0 -13.359375l9.65625 0l0 1.578125l-7.875 0l0 4.09375l7.375 0l0 1.5625l-7.375 0l0 4.546875l8.1875 0l0 1.578125l-9.96875 0zm22.537231 -1.4375q1.234375 0.859375 2.265625 1.25l-0.515625 1.21875q-1.4375 -0.515625 -2.875 -1.625q-1.484375 0.828125 -3.28125 0.828125q-1.8125 0 -3.296875 -0.875q-1.46875 -0.875 -2.265625 -2.453125q-0.79681396 -1.59375 -0.79681396 -3.578125q0 -1.984375 0.79681396 -3.59375q0.8125 -1.625 2.28125 -2.46875q1.484375 -0.859375 3.328125 -0.859375q1.84375 0 3.328125 0.890625q1.484375 0.875 2.265625 2.453125q0.78125 1.578125 0.78125 3.5625q0 1.65625 -0.5 2.96875q-0.5 1.3125 -1.515625 2.28125zm-3.890625 -2.25q1.53125 0.421875 2.515625 1.28125q1.5625 -1.421875 1.5625 -4.28125q0 -1.625 -0.546875 -2.828125q-0.546875 -1.21875 -1.609375 -1.875q-1.0625 -0.671875 -2.390625 -0.671875q-1.96875 0 -3.28125 1.359375q-1.296875 1.34375 -1.296875 4.03125q0 2.59375 1.28125 4.0q1.296875 1.390625 3.296875 1.390625q0.953125 0 1.78125 -0.359375q-0.828125 -0.53125 -1.75 -0.765625l0.4375 -1.28125zm13.257324 7.390625l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm8.844482 4.78125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.519775 0l0 -1.421875q-1.125 1.640625 -3.0625 1.640625q-0.859375 0 -1.609375 -0.328125q-0.734375 -0.328125 -1.09375 -0.828125q-0.359375 -0.5 -0.5 -1.21875q-0.109375 -0.46875 -0.109375 -1.53125l0 -5.984375l1.640625 0l0 5.359375q0 1.28125 0.109375 1.734375q0.15625 0.640625 0.65625 1.015625q0.5 0.375 1.234375 0.375q0.734375 0 1.375 -0.375q0.65625 -0.390625 0.921875 -1.03125q0.265625 -0.65625 0.265625 -1.890625l0 -5.1875l1.640625 0l0 9.671875l-1.46875 0zm3.3913574 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.296875 1.703125q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1882324 4.859375l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm5.9157715 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625z" fill-rule="nonzero"/><path fill="#fff8e3" d="m45.372704 129.914l0 0c0 -53.107376 43.052032 -96.15941 96.1594 -96.15941l384.6261 0l0 0c25.503052 0 49.961548 10.13105 67.994934 28.164436c18.033386 18.033386 28.164429 42.491905 28.164429 67.99497l0 594.1694c0 53.10736 -43.052002 96.159424 -96.15936 96.159424l-384.6261 0c-53.10737 0 -96.1594 -43.052063 -96.1594 -96.159424z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m45.372704 129.914l0 0c0 -53.107376 43.052032 -96.15941 96.1594 -96.15941l384.6261 0l0 0c25.503052 0 49.961548 10.13105 67.994934 28.164436c18.033386 18.033386 28.164429 42.491905 28.164429 67.99497l0 594.1694c0 53.10736 -43.052002 96.159424 -96.15936 96.159424l-384.6261 0c-53.10737 0 -96.1594 -43.052063 -96.1594 -96.159424z" fill-rule="evenodd"/><path fill="#000000" d="m258.10486 88.83872l5.125 -13.359375l1.90625 0l5.46875 13.359375l-2.015625 0l-1.546875 -4.046875l-5.59375 0l-1.46875 4.046875l-1.875 0zm3.859375 -5.484375l4.53125 0l-1.40625 -3.703125q-0.625 -1.6875 -0.9375 -2.765625q-0.265625 1.28125 -0.71875 2.546875l-1.46875 3.921875zm9.802948 5.484375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125702 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm9.806427 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.08956909 5.171875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891327 -3.703125l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688232 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203827 4.859375l0 -9.671875l1.4687805 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.6406555 0zm16.641357 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235077 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm4.7126465 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm15.469482 -5.171875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm8.230164 -1.640625l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm8.485107 2.875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm13.5625 1.421875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625z" fill-rule="nonzero"/><path fill="#fff2cc" d="m95.220474 165.63342l0 0c0 -22.825333 18.503578 -41.32892 41.328903 -41.32892l165.3107 0l0 0c10.96109 0 21.473267 4.3542786 29.223938 12.104965c7.7506714 7.7506714 12.10495 18.262833 12.10495 29.223953l0 353.02722c0 22.825317 -18.50357 41.32892 -41.328888 41.32892l-165.3107 0c-22.825325 0 -41.328903 -18.503601 -41.328903 -41.32892z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m95.220474 165.63342l0 0c0 -22.825333 18.503578 -41.32892 41.328903 -41.32892l165.3107 0l0 0c10.96109 0 21.473267 4.3542786 29.223938 12.104965c7.7506714 7.7506714 12.10495 18.262833 12.10495 29.223953l0 353.02722c0 22.825317 -18.50357 41.32892 -41.328888 41.32892l-165.3107 0c-22.825325 0 -41.328903 -18.503601 -41.328903 -41.32892z" fill-rule="evenodd"/><path fill="#000000" d="m152.07195 162.14183q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.156967 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816696 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125717 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm9.806427 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.08955383 5.171875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891342 -3.703125l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688217 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203842 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641342 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235092 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816696 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125717 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm4.712677 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm18.516327 -6.8125l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.063202 0l-3.6875 -9.671875l1.734375 0l2.078125 5.796875q0.328125 0.9375 0.625 1.9375q0.203125 -0.765625 0.609375 -1.828125l2.140625 -5.90625l1.6875 0l-3.65625 9.671875l-1.53125 0z" fill-rule="nonzero"/><path fill="#ffe599" d="m119.14173 253.60646l0 0c0 -4.4009705 3.5676956 -7.9686584 7.968666 -7.9686584l184.18864 0c2.1134338 0 4.1402893 0.83955383 5.6347046 2.3339539c1.4944153 1.4944153 2.3339844 3.521286 2.3339844 5.6347046l0 31.873703c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-184.18864 0c-4.4009705 0 -7.968666 -3.567688 -7.968666 -7.9686584z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m119.14173 253.60646l0 0c0 -4.4009705 3.5676956 -7.9686584 7.968666 -7.9686584l184.18864 0c2.1134338 0 4.1402893 0.83955383 5.6347046 2.3339539c1.4944153 1.4944153 2.3339844 3.521286 2.3339844 5.6347046l0 31.873703c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-184.18864 0c-4.4009705 0 -7.968666 -3.567688 -7.968666 -7.9686584z" fill-rule="evenodd"/><path fill="#000000" d="m141.61174 270.11423q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.2761078 3.8125l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.490524 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166733 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.7087708 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm0.07197571 4.0625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338608 -2.90625l0 -10.484375l1.28125 0l0 3.75q0.90625 -1.03125 2.28125 -1.03125q0.84375 0 1.46875 0.328125q0.625 0.328125 0.890625 0.921875q0.265625 0.578125 0.265625 1.703125l0 4.8125l-1.28125 0l0 -4.8125q0 -0.96875 -0.421875 -1.40625q-0.421875 -0.4375 -1.1875 -0.4375q-0.578125 0 -1.078125 0.296875q-0.5 0.296875 -0.71875 0.8125q-0.21875 0.5 -0.21875 1.390625l0 4.15625l-1.28125 0zm13.104233 -0.9375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.3073578 3.8125l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm13.072983 0l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125zm7.260483 3.796875l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.490524 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166733 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm3.7087708 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm8.822983 -5.171875l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm12.796875 -0.515625l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm1.890625 -1.015625q0 -2.109375 1.171875 -3.125q0.984375 -0.84375 2.390625 -0.84375q1.578125 0 2.5625 1.03125q1.0 1.015625 1.0 2.828125q0 1.46875 -0.4375 2.3125q-0.4375 0.828125 -1.28125 1.296875q-0.84375 0.46875 -1.84375 0.46875q-1.59375 0 -2.578125 -1.015625q-0.984375 -1.03125 -0.984375 -2.953125zm1.328125 0q0 1.453125 0.625 2.1875q0.640625 0.71875 1.609375 0.71875q0.96875 0 1.59375 -0.71875q0.640625 -0.734375 0.640625 -2.234375q0 -1.40625 -0.640625 -2.125q-0.640625 -0.734375 -1.59375 -0.734375q-0.96875 0 -1.609375 0.71875q-0.625 0.71875 -0.625 2.1875zm7.291733 3.796875l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm10.099396 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm8.369843 4.53125l-1.203125 0l0 -10.484375l1.296875 0l0 3.734375q0.8125 -1.015625 2.078125 -1.015625q0.703125 0 1.328125 0.28125q0.625 0.28125 1.03125 0.796875q0.40625 0.5 0.625 1.234375q0.234375 0.71875 0.234375 1.53125q0 1.96875 -0.96875 3.03125q-0.953125 1.0625 -2.3125 1.0625q-1.34375 0 -2.109375 -1.125l0 0.953125zm-0.015625 -3.859375q0 1.375 0.375 1.984375q0.609375 0.984375 1.640625 0.984375q0.84375 0 1.453125 -0.734375q0.625 -0.734375 0.625 -2.1875q0 -1.484375 -0.59375 -2.1875q-0.59375 -0.71875 -1.421875 -0.71875q-0.84375 0 -1.46875 0.734375q-0.609375 0.734375 -0.609375 2.125zm6.494873 0.0625q0 -2.109375 1.171875 -3.125q0.984375 -0.84375 2.390625 -0.84375q1.578125 0 2.5625 1.03125q1.0 1.015625 1.0 2.828125q0 1.46875 -0.4375 2.3125q-0.4375 0.828125 -1.28125 1.296875q-0.84375 0.46875 -1.84375 0.46875q-1.59375 0 -2.578125 -1.015625q-0.984375 -1.03125 -0.984375 -2.953125zm1.328125 0q0 1.453125 0.625 2.1875q0.640625 0.71875 1.609375 0.71875q0.96875 0 1.59375 -0.71875q0.640625 -0.734375 0.640625 -2.234375q0 -1.40625 -0.640625 -2.125q-0.640625 -0.734375 -1.59375 -0.734375q-0.96875 0 -1.609375 0.71875q-0.625 0.71875 -0.625 2.1875zm12.260468 2.859375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.291748 3.8125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm9.818146 0l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125z" fill-rule="nonzero"/><path fill="#d9ead3" d="m119.14173 449.1983l0 0c0 -3.7022705 3.0012817 -6.7035522 6.7035446 -6.7035522l186.7189 0c1.7778931 0 3.4829712 0.7062683 4.7401123 1.9634094c1.2571716 1.2571716 1.96344 2.9622498 1.96344 4.740143l0 26.813385c0 3.70224 -3.0012817 6.7035217 -6.7035522 6.7035217l-186.7189 0l0 0c-3.7022629 0 -6.7035446 -3.0012817 -6.7035446 -6.7035217z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m119.14173 449.1983l0 0c0 -3.7022705 3.0012817 -6.7035522 6.7035446 -6.7035522l186.7189 0c1.7778931 0 3.4829712 0.7062683 4.7401123 1.9634094c1.2571716 1.2571716 1.96344 2.9622498 1.96344 4.740143l0 26.813385c0 3.70224 -3.0012817 6.7035217 -6.7035522 6.7035217l-186.7189 0l0 0c-3.7022629 0 -6.7035446 -3.0012817 -6.7035446 -6.7035217z" fill-rule="evenodd"/><path fill="#000000" d="m194.86098 467.55252l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm1.3515625 1.265625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm2.2734375 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -4.21875q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.3359375 4.859375l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm13.6640625 1.625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625z" fill-rule="nonzero"/><path fill="#ffe599" d="m369.34122 164.08478l0 0c0 -21.970062 17.810242 -39.78032 39.780304 -39.78032l159.11652 0l0 0c10.550415 0 20.668701 4.1911316 28.128967 11.651398c7.460266 7.460251 11.651367 17.578537 11.651367 28.128922l0 356.1244c0 21.970093 -17.810242 39.780334 -39.780334 39.780334l-159.11652 0c-21.970062 0 -39.780304 -17.810242 -39.780304 -39.780334z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m369.34122 164.08478l0 0c0 -21.970062 17.810242 -39.78032 39.780304 -39.78032l159.11652 0l0 0c10.550415 0 20.668701 4.1911316 28.128967 11.651398c7.460266 7.460251 11.651367 17.578537 11.651367 28.128922l0 356.1244c0 21.970093 -17.810242 39.780334 -39.780334 39.780334l-159.11652 0c-21.970062 0 -39.780304 -17.810242 -39.780304 -39.780334z" fill-rule="evenodd"/><path fill="#000000" d="m403.9156 161.68822q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.156952 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125702 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm9.806427 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.08956909 5.171875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891327 -3.703125l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688232 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.203827 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641357 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235077 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816711 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125702 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm4.712677 3.703125l0 -1.1875l10.8594055 0l0 1.1875l-10.8594055 0zm18.516327 -6.8125l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.141357 5.765625l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm13.063232 0l-3.6875 -9.671875l1.734375 0l2.078125 5.796875q0.328125 0.9375 0.625 1.9375q0.203125 -0.765625 0.609375 -1.828125l2.140625 -5.90625l1.6875 0l-3.65625 9.671875l-1.53125 0zm5.125 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm18.203857 -7.25l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125zm3.40625 3.546875l0 -8.40625l-1.453125 0l0 -1.265625l1.453125 0l0 -1.03125q0 -0.96875 0.171875 -1.453125q0.234375 -0.640625 0.828125 -1.03125q0.59375 -0.390625 1.671875 -0.390625q0.6875 0 1.53125 0.15625l-0.25 1.4375q-0.5 -0.09375 -0.953125 -0.09375q-0.75 0 -1.0625 0.328125q-0.3125 0.3125 -0.3125 1.1875l0 0.890625l1.890625 0l0 1.265625l-1.890625 0l0 8.40625l-1.625 0zm4.4801636 0.796875l1.59375 0.234375q0.109375 0.75 0.5625 1.078125q0.609375 0.453125 1.671875 0.453125q1.140625 0 1.75 -0.453125q0.625 -0.453125 0.84375 -1.265625q0.125 -0.5 0.109375 -2.109375q-1.0625 1.265625 -2.671875 1.265625q-2.0 0 -3.09375 -1.4375q-1.09375 -1.4375 -1.09375 -3.453125q0 -1.390625 0.5 -2.5625q0.515625 -1.171875 1.453125 -1.796875q0.953125 -0.640625 2.25 -0.640625q1.703125 0 2.8125 1.375l0 -1.15625l1.515625 0l0 8.359375q0 2.265625 -0.46875 3.203125q-0.453125 0.9375 -1.453125 1.484375q-0.984375 0.546875 -2.453125 0.546875q-1.71875 0 -2.796875 -0.78125q-1.0625 -0.765625 -1.03125 -2.34375zm1.359375 -5.8125q0 1.90625 0.75 2.78125q0.765625 0.875 1.90625 0.875q1.125 0 1.890625 -0.859375q0.765625 -0.875 0.765625 -2.734375q0 -1.78125 -0.796875 -2.671875q-0.78125 -0.90625 -1.890625 -0.90625q-1.09375 0 -1.859375 0.890625q-0.765625 0.875 -0.765625 2.625z" fill-rule="nonzero"/><path fill="#ffe599" d="m119.14173 323.32037l0 0c0 -5.1315613 4.159958 -9.291504 9.291527 -9.291504l181.54294 0c2.464264 0 4.827606 0.97891235 6.570099 2.721405c1.7424927 1.7425232 2.7214355 4.105835 2.7214355 6.570099l0 37.16501c0 5.1315613 -4.159973 9.291504 -9.291534 9.291504l-181.54294 0c-5.131569 0 -9.291527 -4.1599426 -9.291527 -9.291504z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m119.14173 323.32037l0 0c0 -5.1315613 4.159958 -9.291504 9.291527 -9.291504l181.54294 0c2.464264 0 4.827606 0.97891235 6.570099 2.721405c1.7424927 1.7425232 2.7214355 4.105835 2.7214355 6.570099l0 37.16501c0 5.1315613 -4.159973 9.291504 -9.291534 9.291504l-181.54294 0c-5.131569 0 -9.291527 -4.1599426 -9.291527 -9.291504z" fill-rule="evenodd"/><path fill="#000000" d="m141.34926 341.11026l4.40625 -11.453125l1.640625 0l4.6875 11.453125l-1.734375 0l-1.328125 -3.46875l-4.796875 0l-1.25 3.46875l-1.625 0zm3.3125 -4.703125l3.890625 0l-1.203125 -3.171875q-0.546875 -1.453125 -0.8125 -2.375q-0.21875 1.09375 -0.609375 2.1875l-1.265625 3.359375zm8.421875 4.703125l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.2109375 -3.1875l0 -11.453125l1.40625 0l0 4.109375q0.984375 -1.140625 2.484375 -1.140625q0.921875 0 1.59375 0.359375q0.6875 0.359375 0.96875 1.0q0.296875 0.640625 0.296875 1.859375l0 5.265625l-1.40625 0l0 -5.265625q0 -1.046875 -0.453125 -1.53125q-0.453125 -0.484375 -1.296875 -0.484375q-0.625 0 -1.171875 0.328125q-0.546875 0.328125 -0.78125 0.890625q-0.234375 0.546875 -0.234375 1.515625l0 4.546875l-1.40625 0zm14.3046875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015625 4.171875l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.2734375 0l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm7.9296875 4.140625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm12.5078125 -3.1875l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 -9.84375l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.5390472 0l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm6.8203125 1.265625l0 -1.21875q-0.96875 1.40625 -2.640625 1.40625q-0.734375 0 -1.375 -0.28125q-0.625 -0.28125 -0.9375 -0.703125q-0.3125 -0.4375 -0.4375 -1.046875q-0.078125 -0.421875 -0.078125 -1.3125l0 -5.140625l1.40625 0l0 4.59375q0 1.109375 0.078125 1.484375q0.140625 0.5625 0.5625 0.875q0.4375 0.3125 1.0625 0.3125q0.640625 0 1.1875 -0.3125q0.5625 -0.328125 0.78125 -0.890625q0.234375 -0.5625 0.234375 -1.625l0 -4.4375l1.40625 0l0 8.296875l-1.25 0zm8.8671875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm2.2734375 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0z" fill-rule="nonzero"/><path fill="#000000" d="m182.34535 357.6259l1.390625 -0.21875q0.109375 0.84375 0.640625 1.296875q0.546875 0.4375 1.5 0.4375q0.96875 0 1.4375 -0.390625q0.46875 -0.40625 0.46875 -0.9375q0 -0.46875 -0.40625 -0.75q-0.296875 -0.1875 -1.4375 -0.46875q-1.546875 -0.390625 -2.15625 -0.671875q-0.59375 -0.296875 -0.90625 -0.796875q-0.296875 -0.5 -0.296875 -1.109375q0 -0.5625 0.25 -1.03125q0.25 -0.46875 0.6875 -0.78125q0.328125 -0.25 0.890625 -0.40625q0.578125 -0.171875 1.21875 -0.171875q0.984375 0 1.71875 0.28125q0.734375 0.28125 1.078125 0.765625q0.359375 0.46875 0.5 1.28125l-1.375 0.1875q-0.09375 -0.640625 -0.546875 -1.0q-0.453125 -0.359375 -1.265625 -0.359375q-0.96875 0 -1.390625 0.328125q-0.40625 0.3125 -0.40625 0.734375q0 0.28125 0.171875 0.5q0.171875 0.21875 0.53125 0.375q0.21875 0.078125 1.25 0.359375q1.484375 0.390625 2.078125 0.65625q0.59375 0.25 0.921875 0.734375q0.34375 0.484375 0.34375 1.203125q0 0.703125 -0.421875 1.328125q-0.40625 0.609375 -1.1875 0.953125q-0.765625 0.34375 -1.734375 0.34375q-1.625 0 -2.46875 -0.671875q-0.84375 -0.671875 -1.078125 -2.0zm14.234375 -0.1875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm13.1171875 8.140625l0 -4.078125q-0.328125 0.46875 -0.921875 0.78125q-0.578125 0.296875 -1.25 0.296875q-1.46875 0 -2.546875 -1.171875q-1.0625 -1.1875 -1.0625 -3.25q0 -1.25 0.4375 -2.234375q0.4375 -1.0 1.25 -1.5q0.828125 -0.515625 1.8125 -0.515625q1.546875 0 2.421875 1.296875l0 -1.109375l1.265625 0l0 11.484375l-1.40625 0zm-4.328125 -7.359375q0 1.59375 0.671875 2.40625q0.671875 0.796875 1.609375 0.796875q0.890625 0 1.53125 -0.765625q0.65625 -0.765625 0.65625 -2.3125q0 -1.65625 -0.6875 -2.484375q-0.671875 -0.84375 -1.59375 -0.84375q-0.921875 0 -1.5625 0.78125q-0.625 0.765625 -0.625 2.421875zm13.3828125 4.171875l0 -1.21875q-0.96875 1.40625 -2.640625 1.40625q-0.734375 0 -1.375 -0.28125q-0.625 -0.28125 -0.9375 -0.703125q-0.3125 -0.4375 -0.4375 -1.046875q-0.078125 -0.421875 -0.078125 -1.3125l0 -5.140625l1.40625 0l0 4.59375q0 1.109375 0.078125 1.484375q0.140625 0.5625 0.5625 0.875q0.4375 0.3125 1.0625 0.3125q0.640625 0 1.1875 -0.3125q0.5625 -0.328125 0.78125 -0.890625q0.234375 -0.5625 0.234375 -1.625l0 -4.4375l1.40625 0l0 8.296875l-1.25 0zm9.1328125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.3046875 -3.046875l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm8.265625 0.375l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.70310974 0 1.4374847 0.453125l-0.484375 1.296875q-0.51560974 -0.296875 -1.0312347 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0z" fill-rule="nonzero"/><path fill="#d9ead3" d="m119.14173 390.22852l0 0c0 -4.4009705 3.5676956 -7.9686584 7.968666 -7.9686584l184.18864 0c2.1134338 0 4.1402893 0.8395386 5.6347046 2.3339539c1.4944153 1.4944153 2.3339844 3.5212708 2.3339844 5.6347046l0 31.873688c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-184.18864 0c-4.4009705 0 -7.968666 -3.567688 -7.968666 -7.9686584z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m119.14173 390.22852l0 0c0 -4.4009705 3.5676956 -7.9686584 7.968666 -7.9686584l184.18864 0c2.1134338 0 4.1402893 0.8395386 5.6347046 2.3339539c1.4944153 1.4944153 2.3339844 3.5212708 2.3339844 5.6347046l0 31.873688c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-184.18864 0c-4.4009705 0 -7.968666 -3.567688 -7.968666 -7.9686584z" fill-rule="evenodd"/><path fill="#000000" d="m171.73598 407.68817l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm1.3515625 1.265625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm2.2734375 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.1953125 -3.1875l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm11.015625 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.5703125 5.640625l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm6.6796875 7.484375l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -4.21875q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm8.9765625 4.171875l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm13.3671875 3.109375q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015625 7.359375l0 -11.484375l1.28125 0l0 1.078125q0.453125 -0.640625 1.015625 -0.953125q0.578125 -0.3125 1.390625 -0.3125q1.0625 0 1.875 0.546875q0.8125 0.546875 1.21875 1.546875q0.421875 0.984375 0.421875 2.171875q0 1.28125 -0.46875 2.296875q-0.453125 1.015625 -1.328125 1.5625q-0.859375 0.546875 -1.828125 0.546875q-0.703125 0 -1.265625 -0.296875q-0.546875 -0.296875 -0.90625 -0.75l0 4.046875l-1.40625 0zm1.265625 -7.296875q0 1.609375 0.640625 2.375q0.65625 0.765625 1.578125 0.765625q0.9375 0 1.609375 -0.796875q0.671875 -0.796875 0.671875 -2.453125q0 -1.59375 -0.65625 -2.375q-0.65625 -0.796875 -1.5625 -0.796875q-0.890625 0 -1.59375 0.84375q-0.6875 0.84375 -0.6875 2.4375zm10.695297 2.84375l0.203125 1.25q-0.59373474 0.125 -1.0624847 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.4062347 0l0 1.09375l-1.4062347 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.60935974 -0.0625zm7.0546875 -1.40625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0z" fill-rule="nonzero"/><path fill="#ffe599" d="m121.514435 198.7114l0 0c0 -2.8383179 2.3009033 -5.139221 5.1392136 -5.139221l38.50898 0c1.3630066 0 2.6701813 0.54145813 3.6339722 1.505249c0.9637909 0.9637909 1.5052338 2.2709656 1.5052338 3.6339722l0 20.556213c0 2.8383179 -2.3009033 5.139221 -5.139206 5.139221l-38.50898 0c-2.8383102 0 -5.1392136 -2.3009033 -5.1392136 -5.139221z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m121.514435 198.7114l0 0c0 -2.8383179 2.3009033 -5.139221 5.1392136 -5.139221l38.50898 0c1.3630066 0 2.6701813 0.54145813 3.6339722 1.505249c0.9637909 0.9637909 1.5052338 2.2709656 1.5052338 3.6339722l0 20.556213c0 2.8383179 -2.3009033 5.139221 -5.139206 5.139221l-38.50898 0c-2.8383102 0 -5.1392136 -2.3009033 -5.1392136 -5.139221z" fill-rule="evenodd"/><path fill="#000000" d="m141.70502 211.80263l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.921875 3.046875l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0zm3.8515625 0.6875l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m488.67978 559.9895c0 12.50061 -60.835846 51.17395 -109.42984 25.00122c-48.593994 -26.17279 -84.94617 -117.19171 -109.42984 -208.21014c-24.483704 -91.01846 -37.098923 -182.03645 -61.95598 -208.21014c-24.85707 -26.173676 -61.95598 12.496933 -61.95598 24.993866" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m488.67978 559.9895c0 12.50061 -60.835846 51.17395 -109.42984 25.00122c-48.593994 -26.17279 -84.94617 -117.19171 -109.42984 -208.21014c-24.483704 -91.01846 -37.098923 -182.03645 -61.95598 -208.21014c-24.85707 -26.173676 -61.95598 12.496933 -61.95598 24.993866" fill-rule="evenodd"/><path fill="#d9ead3" d="m382.89502 462.05972l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.86853c0 3.5717773 -2.8955078 6.4673157 -6.467346 6.4673157l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m382.89502 462.05972l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.86853c0 3.5717773 -2.8955078 6.4673157 -6.467346 6.4673157l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path fill="#000000" d="m443.49316 480.581l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm1.3515625 1.265625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm2.2734375 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -4.21875q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.3359375 4.859375l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm13.6640625 1.625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -6.234375l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.921875 3.046875l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0zm3.8515625 0.6875l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625z" fill-rule="nonzero"/><path fill="#ffd966" d="m381.32022 183.19441l0 0c0 -5.1315613 4.1599426 -9.291519 9.291504 -9.291519l184.69254 0c2.4642944 0 4.8276367 0.97891235 6.5701294 2.7214203c1.7424927 1.7424927 2.7214355 4.105835 2.7214355 6.570099l0 37.164978c0 5.1315765 -4.159973 9.291534 -9.291565 9.291534l-184.69254 0c-5.1315613 0 -9.291504 -4.159958 -9.291504 -9.291534z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m381.32022 183.19441l0 0c0 -5.1315613 4.1599426 -9.291519 9.291504 -9.291519l184.69254 0c2.4642944 0 4.8276367 0.97891235 6.5701294 2.7214203c1.7424927 1.7424927 2.7214355 4.105835 2.7214355 6.570099l0 37.164978c0 5.1315765 -4.159973 9.291534 -9.291565 9.291534l-184.69254 0c-5.1315613 0 -9.291504 -4.159958 -9.291504 -9.291534z" fill-rule="evenodd"/><path fill="#000000" d="m403.59082 199.95303q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.2109375 -3.1875l0 -11.453125l1.40625 0l0 4.109375q0.984375 -1.140625 2.484375 -1.140625q0.921875 0 1.59375 0.359375q0.6875 0.359375 0.96875 1.0q0.296875 0.640625 0.296875 1.859375l0 5.265625l-1.40625 0l0 -5.265625q0 -1.046875 -0.453125 -1.53125q-0.453125 -0.484375 -1.296875 -0.484375q-0.625 0 -1.171875 0.328125q-0.546875 0.328125 -0.78125 0.890625q-0.234375 0.546875 -0.234375 1.515625l0 4.546875l-1.40625 0zm14.3046875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015625 4.171875l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.2734375 0l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm7.9296875 4.140625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.1953125 -3.1875l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm11.015625 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.5703125 5.640625l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm6.6796875 7.484375l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm11.5078125 -3.1875l-1.3125 0l0 -11.453125l1.40625 0l0 4.078125q0.890625 -1.109375 2.28125 -1.109375q0.765625 0 1.4375 0.3125q0.6875 0.296875 1.125 0.859375q0.453125 0.5625 0.703125 1.359375q0.25 0.78125 0.25 1.671875q0 2.140625 -1.0625 3.3125q-1.046875 1.15625 -2.53125 1.15625q-1.46875 0 -2.296875 -1.234375l0 1.046875zm-0.015625 -4.21875q0 1.5 0.40625 2.15625q0.65625 1.09375 1.796875 1.09375q0.921875 0 1.59375 -0.796875q0.671875 -0.8125 0.671875 -2.390625q0 -1.625 -0.65625 -2.390625q-0.640625 -0.78125 -1.546875 -0.78125q-0.921875 0 -1.59375 0.796875q-0.671875 0.796875 -0.671875 2.3125zm7.5859375 4.21875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm3.0546875 -4.15625q0 -2.296875 1.28125 -3.40625q1.078125 -0.921875 2.609375 -0.921875q1.71875 0 2.796875 1.125q1.09375 1.109375 1.09375 3.09375q0 1.59375 -0.484375 2.515625q-0.484375 0.921875 -1.40625 1.4375q-0.90625 0.5 -2.0 0.5q-1.734375 0 -2.8125 -1.109375q-1.078125 -1.125 -1.078125 -3.234375zm1.453125 0q0 1.59375 0.6875 2.390625q0.703125 0.796875 1.75 0.796875q1.046875 0 1.734375 -0.796875q0.703125 -0.796875 0.703125 -2.4375q0 -1.53125 -0.703125 -2.328125q-0.6875 -0.796875 -1.734375 -0.796875q-1.046875 0 -1.75 0.796875q-0.6875 0.78125 -0.6875 2.375zm13.3828125 1.109375l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.59375 3.046875l0 -11.453125l1.40625 0l0 6.53125l3.328125 -3.375l1.828125 0l-3.171875 3.078125l3.484375 5.21875l-1.734375 0l-2.734375 -4.25l-1.0 0.953125l0 3.296875l-1.40625 0z" fill-rule="nonzero"/><path fill="#000000" d="m469.36816 223.17178l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.1953125 -3.1875l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm10.75 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0z" fill-rule="nonzero"/><path fill="#f4cccc" d="m381.3228 247.3794l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l190.34097 0c1.71521 0 3.3602295 0.68136597 4.573059 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5718079 -2.8955078 6.4673157 -6.467285 6.4673157l-190.34097 0l0 0c-3.5718079 0 -6.4673157 -2.8955078 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m381.3228 247.3794l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l190.34097 0c1.71521 0 3.3602295 0.68136597 4.573059 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5718079 -2.8955078 6.4673157 -6.467285 6.4673157l-190.34097 0l0 0c-3.5718079 0 -6.4673157 -2.8955078 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path fill="#000000" d="m453.86685 264.11942l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.5625 3.046875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm3.5859375 0l0 -11.453125l1.40625 0l0 6.53125l3.328125 -3.375l1.828125 0l-3.171875 3.078125l3.484375 5.21875l-1.734375 0l-2.734375 -4.25l-1.0 0.953125l0 3.296875l-1.40625 0zm6.6875 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.1953125 -3.1875l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.78125 -2.484375l1.390625 -0.21875q0.109375 0.84375 0.640625 1.296875q0.546875 0.4375 1.5 0.4375q0.96875 0 1.4375 -0.390625q0.46875 -0.40625 0.46875 -0.9375q0 -0.46875 -0.40625 -0.75q-0.296875 -0.1875 -1.4375 -0.46875q-1.546875 -0.390625 -2.15625 -0.671875q-0.59375 -0.296875 -0.90625 -0.796875q-0.296875 -0.5 -0.296875 -1.109375q0 -0.5625 0.25 -1.03125q0.25 -0.46875 0.6875 -0.78125q0.328125 -0.25 0.890625 -0.40625q0.578125 -0.171875 1.21875 -0.171875q0.984375 0 1.71875 0.28125q0.734375 0.28125 1.078125 0.765625q0.359375 0.46875 0.5 1.28125l-1.375 0.1875q-0.09375 -0.640625 -0.546875 -1.0q-0.453125 -0.359375 -1.265625 -0.359375q-0.96875 0 -1.390625 0.328125q-0.40625 0.3125 -0.40625 0.734375q0 0.28125 0.171875 0.5q0.171875 0.21875 0.53125 0.375q0.21875 0.078125 1.25 0.359375q1.484375 0.390625 2.078125 0.65625q0.59375 0.25 0.921875 0.734375q0.34375 0.484375 0.34375 1.203125q0 0.703125 -0.421875 1.328125q-0.40625 0.609375 -1.1875 0.953125q-0.765625 0.34375 -1.734375 0.34375q-1.625 0 -2.46875 -0.671875q-0.84375 -0.671875 -1.078125 -2.0zm11.625 1.21875l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm12.5078125 -3.1875l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 -9.84375l0 -1.609375l1.4062805 0l0 1.609375l-1.4062805 0zm0 9.84375l0 -8.296875l1.4062805 0l0 8.296875l-1.4062805 0zm3.882843 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0z" fill-rule="nonzero"/><path fill="#f4cccc" d="m382.89633 297.4476l0 0c0 -3.5718079 2.8955078 -6.467346 6.4673157 -6.467346l187.19135 0c1.71521 0 3.3602295 0.6813965 4.573059 1.8942566c1.2128906 1.2128601 1.8942871 2.8578491 1.8942871 4.5730896l0 25.8685c0 3.5718079 -2.8955688 6.4673157 -6.467346 6.4673157l-187.19135 0l0 0c-3.5718079 0 -6.4673157 -2.8955078 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m382.89633 297.4476l0 0c0 -3.5718079 2.8955078 -6.467346 6.4673157 -6.467346l187.19135 0c1.71521 0 3.3602295 0.6813965 4.573059 1.8942566c1.2128906 1.2128601 1.8942871 2.8578491 1.8942871 4.5730896l0 25.8685c0 3.5718079 -2.8955688 6.4673157 -6.467346 6.4673157l-187.19135 0l0 0c-3.5718079 0 -6.4673157 -2.8955078 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path fill="#000000" d="m460.45932 307.39072l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.5546875 0l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm1.3671875 1.265625l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm12.5078125 -3.1875l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 -9.84375l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.8828125 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0z" fill-rule="nonzero"/><path fill="#f4cccc" d="m382.89502 405.437l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5718079 -2.8955078 6.467346 -6.467346 6.467346l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.467346z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m382.89502 405.437l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5718079 -2.8955078 6.467346 -6.467346 6.467346l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.467346z" fill-rule="evenodd"/><path fill="#000000" d="m444.03613 425.2239l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm13.6328125 1.46875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm10.1328125 4.953125l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 0l0 -8.296875l1.25 0l0 1.15625q0.390625 -0.609375 1.03125 -0.96875q0.65625 -0.375 1.484375 -0.375q0.921875 0 1.515625 0.390625q0.59375 0.375 0.828125 1.0625q0.984375 -1.453125 2.5625 -1.453125q1.234375 0 1.890625 0.6875q0.671875 0.671875 0.671875 2.09375l0 5.703125l-1.390625 0l0 -5.234375q0 -0.84375 -0.140625 -1.203125q-0.140625 -0.375 -0.5 -0.59375q-0.359375 -0.234375 -0.84375 -0.234375q-0.875 0 -1.453125 0.578125q-0.578125 0.578125 -0.578125 1.859375l0 4.828125l-1.40625 0l0 -5.390625q0 -0.9375 -0.34375 -1.40625q-0.34375 -0.46875 -1.125 -0.46875q-0.59375 0 -1.09375 0.3125q-0.5 0.3125 -0.734375 0.921875q-0.21875 0.59375 -0.21875 1.71875l0 4.3125l-1.40625 0zm12.796875 -4.15625q0 -2.296875 1.28125 -3.40625q1.078125 -0.921875 2.609375 -0.921875q1.71875 0 2.796875 1.125q1.09375 1.109375 1.09375 3.09375q0 1.59375 -0.484375 2.515625q-0.484375 0.921875 -1.40625 1.4375q-0.90625 0.5 -2.0 0.5q-1.734375 0 -2.8125 -1.109375q-1.078125 -1.125 -1.078125 -3.234375zm1.453125 0q0 1.59375 0.6875 2.390625q0.703125 0.796875 1.75 0.796875q1.046875 0 1.734375 -0.796875q0.703125 -0.796875 0.703125 -2.4375q0 -1.53125 -0.703125 -2.328125q-0.6875 -0.796875 -1.734375 -0.796875q-1.046875 0 -1.75 0.796875q-0.6875 0.78125 -0.6875 2.375zm13.3515625 4.15625l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm13.6328125 1.46875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm6.5234375 8.140625l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm12.5078125 -3.1875l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 -9.84375l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.8828125 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m319.26773 341.90286c12.518219 0 12.072876 63.98932 25.036469 121.54294c12.963593 57.55359 39.33612 108.67145 72.19043 121.54291c32.85431 12.87146 72.1904 -12.50354 72.1904 -25.00708" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m319.26773 341.90286c12.518219 0 12.072876 63.98932 25.036469 121.54294c12.963593 57.55359 39.33612 108.67145 72.19043 121.54291c32.85431 12.87146 72.1904 -12.50354 72.1904 -25.00708" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m319.26773 269.5433c12.518219 0 12.072876 83.286316 25.036469 157.72379c12.963593 74.43747 39.33612 140.02606 72.19043 157.72382c32.85431 17.697693 72.1904 -12.495483 72.1904 -24.990906" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m319.26773 269.5433c12.518219 0 12.072876 83.286316 25.036469 157.72379c12.963593 74.43747 39.33612 140.02606 72.19043 157.72382c32.85431 17.697693 72.1904 -12.495483 72.1904 -24.990906" fill-rule="evenodd"/><path fill="#cfe2f3" d="m95.220474 580.0092l446.12006 0l36.084656 36.084656l0 180.41925l-482.2047 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m95.220474 580.0092l446.12006 0l36.084656 36.084656l0 180.41925l-482.2047 0z" fill-rule="evenodd"/><path fill="#000000" d="m107.4861 614.35156l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.254395 5.5l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm4.2543945 -5.5l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.08252 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.2387695 -9.0625l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm3.4262695 -5.0625l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.3950195 0q0 -0.734375 0.1875 -1.546875q0.1875 -0.828125 0.71875 -1.890625q0.546875 -1.078125 0.796875 -1.296875q0.078125 -0.078125 0.171875 -0.078125q0.109375 0 0.1875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.0625 -0.046875 0.140625q-0.6875 1.28125 -1.0 2.328125q-0.296875 1.03125 -0.296875 2.078125q0 1.046875 0.296875 2.09375q0.3125 1.03125 1.0 2.3125q0.046875 0.078125 0.046875 0.140625q0 0.09375 -0.078125 0.171875q-0.078125 0.09375 -0.1875 0.09375q-0.09375 0 -0.171875 -0.078125q-0.234375 -0.21875 -0.765625 -1.265625q-0.53125 -1.046875 -0.734375 -1.84375q-0.203125 -0.8125 -0.203125 -1.625zm8.02002 0q0 0.734375 -0.203125 1.546875q-0.1875 0.8125 -0.734375 1.890625q-0.53125 1.078125 -0.78125 1.296875q-0.078125 0.078125 -0.15625 0.078125q-0.125 0 -0.203125 -0.09375q-0.078125 -0.078125 -0.078125 -0.171875q0 -0.0625 0.046875 -0.140625q0.703125 -1.28125 1.0 -2.3125q0.296875 -1.046875 0.296875 -2.09375q0 -1.046875 -0.296875 -2.078125q-0.296875 -1.046875 -1.0 -2.328125q-0.046875 -0.078125 -0.046875 -0.140625q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.203125 -0.078125q0.078125 0 0.15625 0.078125q0.234375 0.203125 0.765625 1.25q0.546875 1.046875 0.75 1.859375q0.203125 0.8125 0.203125 1.625zm7.5356445 -2.34375l0.21875 0q0.359375 0 0.609375 0.265625q0.25 0.25 0.25 0.59375q0 0.375 -0.25 0.625q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.265625 -0.25 -0.609375q0 -0.375 0.25 -0.625q0.265625 -0.25 0.625 -0.25zm0 3.96875l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25zm17.930664 -3.421875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm7.1137695 4.953125l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm9.285645 2.828125q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm13.211914 -0.359375l0 1.34375q1.0312347 -0.9375 1.5468597 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6874847 1.359375l0 2.921875l2.3593597 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1874847 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.254379 5.5l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm4.2543945 -5.5l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.08252 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm6.0043945 -8.703125q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125zm5.6762695 -0.25q0 -0.734375 0.1875 -1.546875q0.1875 -0.828125 0.71875 -1.890625q0.546875 -1.078125 0.796875 -1.296875q0.078125 -0.078125 0.171875 -0.078125q0.109375 0 0.1875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.0625 -0.046875 0.140625q-0.6875 1.28125 -1.0 2.328125q-0.296875 1.03125 -0.296875 2.078125q0 1.046875 0.296875 2.09375q0.3125 1.03125 1.0 2.3125q0.046875 0.078125 0.046875 0.140625q0 0.09375 -0.078125 0.171875q-0.078125 0.09375 -0.1875 0.09375q-0.09375 0 -0.171875 -0.078125q-0.234375 -0.21875 -0.765625 -1.265625q-0.53125 -1.046875 -0.734375 -1.84375q-0.203125 -0.8125 -0.203125 -1.625zm8.02002 0q0 0.734375 -0.203125 1.546875q-0.1875 0.8125 -0.734375 1.890625q-0.53125 1.078125 -0.78125 1.296875q-0.078125 0.078125 -0.15625 0.078125q-0.125 0 -0.203125 -0.09375q-0.078125 -0.078125 -0.078125 -0.171875q0 -0.0625 0.046875 -0.140625q0.703125 -1.28125 1.0 -2.3125q0.296875 -1.046875 0.296875 -2.09375q0 -1.046875 -0.296875 -2.078125q-0.296875 -1.046875 -1.0 -2.328125q-0.046875 -0.078125 -0.046875 -0.140625q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.203125 -0.078125q0.078125 0 0.15625 0.078125q0.234375 0.203125 0.765625 1.25q0.546875 1.046875 0.75 1.859375q0.203125 0.8125 0.203125 1.625zm17.274414 3.15625l-0.65625 0l-1.171875 -3.421875l-1.171875 3.421875l-0.65625 0l-1.109375 -4.953125l-0.25 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.671875 0l0.9375 4.21875l1.140625 -3.375l0.640625 0l1.171875 3.375l0.90625 -4.21875l-0.671875 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l1.453125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.25 0l-1.09375 4.953125zm4.2075195 -7.96875l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm9.83252 -0.265625l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm9.73877 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm3.8168945 -3.015625l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm19.586914 3.015625l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm4.9418945 -0.546875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm6.9887695 3.15625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm5.1762695 -2.84375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.2075195 -1.984375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm15.383789 5.140625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm4.5356445 -2.84375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm12.899414 -2.765625l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.254395 5.5l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm4.2543945 -5.5l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.285645 0.359375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875z" fill-rule="nonzero"/><path fill="#000000" d="m109.876724 630.71094q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125zm7.5512695 2.90625l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm8.86377 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm3.7231445 -2.34375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.754395 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm8.45752 2.328125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm11.243164 -2.34375l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm6.7231445 2.90625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm7.8012695 0q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm16.41504 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.8168945 0.28125l2.4375 2.34375q0.25 0 0.3125 0.03125q0.0625 0.015625 0.109375 0.09375q0.046875 0.0625 0.046875 0.140625q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.890625 0l-2.078125 -1.984375l-2.0625 1.984375l0.890625 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.078125 0.046875 -0.140625q0.046875 -0.078125 0.109375 -0.09375q0.0625 -0.03125 0.296875 -0.03125l2.453125 -2.34375l-2.171875 -2.078125q-0.234375 0 -0.296875 -0.03125q-0.0625 -0.03125 -0.109375 -0.09375q-0.046875 -0.0625 -0.046875 -0.15625q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.640625 0l1.796875 1.734375l1.8125 -1.734375l-0.640625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.046875 0.140625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.03125 -0.296875 0.03125l-2.171875 2.078125zm6.3481445 -2.625l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.770004 2.875l-5.4218597 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.7968597 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.3749847 0 -2.2968597 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.1249847 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.92185974 0 -1.5937347 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.8906097 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm6.7075195 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.066895 5.5l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.5668945 7.96875l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875zm17.38379 0l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm7.7387695 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm6.3168945 -3.09375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.7856445 0l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.316895 0.984375l0 -0.984375l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0l0 5.328125q0 0.53125 -0.234375 0.953125q-0.15625 0.265625 -0.515625 0.5625q-0.34375 0.3125 -0.640625 0.4375q-0.296875 0.125 -0.78125 0.125l-1.515625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.265625 -0.078125l1.53125 0.015625q0.46875 0 0.84375 -0.25q0.390625 -0.234375 0.625 -0.703125q0.140625 -0.265625 0.140625 -0.671875l0 -1.609375q-0.84375 1.171875 -2.203125 1.171875q-1.09375 0 -1.890625 -0.8125q-0.796875 -0.8125 -0.796875 -1.953125q0 -1.15625 0.796875 -1.96875q0.796875 -0.8125 1.890625 -0.8125q1.359375 0 2.203125 1.171875zm0 1.609375q0 -0.953125 -0.640625 -1.59375q-0.640625 -0.640625 -1.53125 -0.640625q-0.90625 0 -1.546875 0.65625q-0.640625 0.640625 -0.640625 1.578125q0 0.9375 0.640625 1.59375q0.640625 0.640625 1.546875 0.640625q0.890625 0 1.53125 -0.640625q0.640625 -0.65625 0.640625 -1.59375z" fill-rule="nonzero"/><path fill="#000000" d="m368.70923 629.3047l0 3.78125q0 1.234375 -0.890625 2.09375q-0.890625 0.859375 -2.140625 0.859375q-0.609375 0 -1.15625 -0.203125q-0.546875 -0.21875 -0.984375 -0.640625q-0.421875 -0.4375 -0.671875 -0.890625q-0.234375 -0.453125 -0.234375 -1.21875l0 -3.78125q-0.421875 0 -0.625 -0.1875q-0.203125 -0.203125 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.75 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.296875 -0.203125 0.484375q-0.203125 0.1875 -0.6875 0.1875l-0.484375 0l0 3.890625q0 0.59375 0.5 1.0625q0.5 0.453125 1.203125 0.453125q0.46875 0 0.875 -0.21875q0.421875 -0.21875 0.671875 -0.640625q0.171875 -0.265625 0.171875 -0.65625l0 -3.890625l-0.484375 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.75 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.484375q-0.203125 0.1875 -0.625 0.1875zm4.951294 4.59375l1.921875 -4.59375l-0.296875 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.78125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.359375 -0.3125 0.5625q-0.140625 0.109375 -0.609375 0.109375l-2.734375 6.546875l-1.28125 0l-2.734375 -6.546875q-0.46875 0 -0.625 -0.109375q-0.3125 -0.203125 -0.3125 -0.5625q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l1.8125 0q0.46875 0 0.671875 0.1875q0.21875 0.1875 0.21875 0.484375q0 0.296875 -0.203125 0.484375q-0.203125 0.1875 -0.6875 0.1875l-0.3125 0l1.921875 4.59375zm5.9044495 -3.359375l0 3.984375l0.484375 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.75 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.625 -0.1875l0 -5.21875q-0.34375 -0.046875 -0.53125 -0.21875q-0.171875 -0.1875 -0.171875 -0.453125q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.453125 0l1.828125 4.015625l1.78125 -4.015625l1.46875 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.265625 -0.1875 0.453125q-0.171875 0.171875 -0.515625 0.21875l0 5.21875q0.421875 0 0.625 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-1.765625 0q-0.46875 0 -0.671875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.671875 -0.1875l0.5 0l0 -3.984375l-1.53125 3.4375l-1.15625 0l-1.5625 -3.4375zm13.779449 9.3125l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm4.951294 -10.546875l0 5.21875l0.90625 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-3.125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.890625 0l0 -5.21875l-1.4375 0l0 1.25q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -2.59375l6.90625 0l0 2.59375q0 0.484375 -0.1875 0.6875q-0.171875 0.203125 -0.46875 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -1.25l-1.46875 0zm5.982544 3.25l0 1.96875l3.40625 0l0 -0.734375q0 -0.46875 0.1875 -0.671875q0.1875 -0.21875 0.484375 -0.21875q0.296875 0 0.46875 0.21875q0.1875 0.203125 0.1875 0.671875l0 2.0625l-6.265625 0q-0.484375 0 -0.703125 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.703125 -0.1875l0.203125 0l0 -5.21875l-0.203125 0q-0.484375 0 -0.703125 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.21875 -0.1875 0.703125 -0.1875l5.984375 0l0 2.03125q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -0.6875l-3.109375 0l0 1.921875l1.171875 0q0 -0.515625 0.09375 -0.671875q0.203125 -0.3125 0.578125 -0.3125q0.296875 0 0.484375 0.203125q0.1875 0.203125 0.1875 0.6875l0 1.53125q0 0.4375 -0.109375 0.578125q-0.203125 0.3125 -0.5625 0.3125q-0.375 0 -0.578125 -0.3125q-0.09375 -0.15625 -0.09375 -0.6875l-1.171875 0zm7.4200745 2.953125q-0.171875 0.21875 -0.28125 0.28125q-0.109375 0.046875 -0.265625 0.046875q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.671875l0 -0.90625q0 -0.484375 0.1875 -0.6875q0.1875 -0.203125 0.484375 -0.203125q0.234375 0 0.390625 0.125q0.171875 0.125 0.25 0.421875q0.078125 0.28125 0.171875 0.390625q0.1875 0.1875 0.671875 0.40625q0.484375 0.203125 1.0625 0.203125q0.890625 0 1.453125 -0.421875q0.375 -0.25 0.375 -0.625q0 -0.234375 -0.1875 -0.453125q-0.171875 -0.21875 -0.5625 -0.359375q-0.265625 -0.109375 -1.171875 -0.28125q-1.09375 -0.1875 -1.65625 -0.46875q-0.546875 -0.296875 -0.875 -0.8125q-0.328125 -0.53125 -0.328125 -1.125q0 -0.96875 0.796875 -1.6875q0.796875 -0.71875 2.078125 -0.71875q0.515625 0 0.953125 0.125q0.453125 0.109375 0.8125 0.34375q0.25 -0.25 0.515625 -0.25q0.296875 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 1.0q0 0.484375 -0.1875 0.6875q-0.171875 0.203125 -0.46875 0.203125q-0.25 0 -0.4375 -0.140625q-0.140625 -0.109375 -0.21875 -0.4375q-0.0625 -0.34375 -0.171875 -0.484375q-0.1875 -0.25 -0.5625 -0.40625q-0.375 -0.171875 -0.875 -0.171875q-0.71875 0 -1.140625 0.34375q-0.421875 0.328125 -0.421875 0.6875q0 0.25 0.171875 0.484375q0.171875 0.21875 0.5 0.359375q0.21875 0.078125 1.25 0.28125q1.03125 0.203125 1.578125 0.453125q0.546875 0.234375 0.90625 0.75q0.375 0.515625 0.375 1.21875q0 1.0 -0.703125 1.59375q-0.921875 0.765625 -2.359375 0.765625q-0.546875 0 -1.078125 -0.140625q-0.515625 -0.125 -1.015625 -0.390625zm10.591949 -6.203125l0 5.21875l0.90625 0q0.484375 0 0.6875 0.1875q0.203125 0.171875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875l-3.125 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.203125 -0.1875 0.6875 -0.1875l0.890625 0l0 -5.21875l-1.4375 0l0 1.25q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -2.59375l6.90625 0l0 2.59375q0 0.484375 -0.1875 0.6875q-0.171875 0.203125 -0.46875 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -1.25l-1.46875 0zm11.045044 10.546875l-7.328125 0q-0.46875 0 -0.671875 -0.1875q-0.21875 -0.171875 -0.21875 -0.46875q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l7.328125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.28125 -0.203125 0.46875q-0.203125 0.1875 -0.6875 0.1875zm4.310669 -5.953125l1.921875 -4.59375l-0.296875 0q-0.484375 0 -0.6875 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.203125 -0.1875 0.6875 -0.1875l1.78125 0q0.484375 0 0.6875 0.1875q0.203125 0.1875 0.203125 0.484375q0 0.359375 -0.3125 0.5625q-0.140625 0.109375 -0.609375 0.109375l-2.734375 6.546875l-1.28125 0l-2.734375 -6.546875q-0.46875 0 -0.625 -0.109375q-0.3125 -0.203125 -0.3125 -0.5625q0 -0.296875 0.21875 -0.484375q0.203125 -0.1875 0.671875 -0.1875l1.8125 0q0.46875 0 0.671875 0.1875q0.21875 0.1875 0.21875 0.484375q0 0.296875 -0.203125 0.484375q-0.203125 0.1875 -0.6875 0.1875l-0.3125 0l1.921875 4.59375zm6.0450745 1.609375q-0.171875 0.21875 -0.28125 0.28125q-0.109375 0.046875 -0.265625 0.046875q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.671875l0 -0.90625q0 -0.484375 0.1875 -0.6875q0.1875 -0.203125 0.484375 -0.203125q0.234375 0 0.390625 0.125q0.171875 0.125 0.25 0.421875q0.078125 0.28125 0.171875 0.390625q0.1875 0.1875 0.671875 0.40625q0.484375 0.203125 1.0625 0.203125q0.890625 0 1.453125 -0.421875q0.375 -0.25 0.375 -0.625q0 -0.234375 -0.1875 -0.453125q-0.171875 -0.21875 -0.5625 -0.359375q-0.265625 -0.109375 -1.171875 -0.28125q-1.09375 -0.1875 -1.65625 -0.46875q-0.546875 -0.296875 -0.875 -0.8125q-0.328125 -0.53125 -0.328125 -1.125q0 -0.96875 0.796875 -1.6875q0.796875 -0.71875 2.078125 -0.71875q0.515625 0 0.953125 0.125q0.453125 0.109375 0.8125 0.34375q0.25 -0.25 0.515625 -0.25q0.296875 0 0.46875 0.203125q0.1875 0.203125 0.1875 0.671875l0 1.0q0 0.484375 -0.1875 0.6875q-0.171875 0.203125 -0.46875 0.203125q-0.25 0 -0.4375 -0.140625q-0.140625 -0.109375 -0.21875 -0.4375q-0.0625 -0.34375 -0.171875 -0.484375q-0.1875 -0.25 -0.5625 -0.40625q-0.375 -0.171875 -0.875 -0.171875q-0.71875 0 -1.140625 0.34375q-0.421875 0.328125 -0.421875 0.6875q0 0.25 0.171875 0.484375q0.171875 0.21875 0.5 0.359375q0.21875 0.078125 1.25 0.28125q1.03125 0.203125 1.578125 0.453125q0.546875 0.234375 0.90625 0.75q0.375 0.515625 0.375 1.21875q0 1.0 -0.703125 1.59375q-0.921875 0.765625 -2.359375 0.765625q-0.546875 0 -1.078125 -0.140625q-0.515625 -0.125 -1.015625 -0.390625zm8.576324 -2.953125l0 1.96875l3.40625 0l0 -0.734375q0 -0.46875 0.1875 -0.671875q0.1875 -0.21875 0.484375 -0.21875q0.296875 0 0.46875 0.21875q0.1875 0.203125 0.1875 0.671875l0 2.0625l-6.265625 0q-0.484375 0 -0.703125 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.46875q0.21875 -0.1875 0.703125 -0.1875l0.203125 0l0 -5.21875l-0.203125 0q-0.484375 0 -0.703125 -0.1875q-0.203125 -0.1875 -0.203125 -0.484375q0 -0.296875 0.203125 -0.484375q0.21875 -0.1875 0.703125 -0.1875l5.984375 0l0 2.03125q0 0.484375 -0.1875 0.6875q-0.1875 0.203125 -0.484375 0.203125q-0.296875 0 -0.484375 -0.203125q-0.1875 -0.203125 -0.1875 -0.6875l0 -0.6875l-3.109375 0l0 1.921875l1.171875 0q0 -0.515625 0.09375 -0.671875q0.203125 -0.3125 0.578125 -0.3125q0.296875 0 0.484375 0.203125q0.1875 0.203125 0.1875 0.6875l0 1.53125q0 0.4375 -0.109375 0.578125q-0.203125 0.3125 -0.5625 0.3125q-0.375 0 -0.578125 -0.3125q-0.09375 -0.15625 -0.09375 -0.6875l-1.171875 0zm9.685669 3.484375l-0.046875 0.046875q0.6875 0 1.296875 0.28125q0.25 0.125 0.40625 0.125q0.234375 0 0.578125 -0.234375q0.34375 -0.21875 0.53125 -0.21875q0.28125 0 0.46875 0.1875q0.203125 0.203125 0.203125 0.484375q0 0.34375 -0.359375 0.609375q-0.71875 0.5 -1.421875 0.5q-0.375 0 -0.75 -0.140625q-0.59375 -0.234375 -0.9375 -0.234375q-0.578125 0 -1.734375 0.296875q-0.234375 0.0625 -0.375 0.0625q-0.25 0 -0.453125 -0.203125q-0.1875 -0.203125 -0.1875 -0.5q0 -0.265625 0.265625 -0.515625l0.859375 -0.828125q-1.0625 -0.453125 -1.734375 -1.484375q-0.65625 -1.03125 -0.65625 -2.359375q0 -1.953125 1.328125 -3.171875q1.0625 -0.984375 2.40625 -0.984375q1.34375 0 2.40625 0.984375q1.328125 1.21875 1.328125 3.171875q0 1.65625 -1.015625 2.828125q-1.0 1.15625 -2.40625 1.296875zm2.09375 -4.125q0 -1.21875 -0.734375 -2.015625q-0.734375 -0.796875 -1.671875 -0.796875q-0.9375 0 -1.671875 0.796875q-0.734375 0.796875 -0.734375 2.015625q0 1.203125 0.734375 2.0q0.734375 0.796875 1.671875 0.796875q0.9375 0 1.671875 -0.796875q0.734375 -0.796875 0.734375 -2.0z" fill-rule="nonzero"/><path fill="#000000" d="m475.33063 630.35156l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm5.4575195 -5.0625l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm9.348145 7.96875l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm7.7387695 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm7.5825195 5.140625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm5.6293945 -2.84375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm10.223145 0.984375l0 -0.984375l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0l0 5.328125q0 0.53125 -0.234375 0.953125q-0.15625 0.265625 -0.515625 0.5625q-0.34375 0.3125 -0.640625 0.4375q-0.296875 0.125 -0.78125 0.125l-1.515625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.265625 -0.078125l1.53125 0.015625q0.46875 0 0.84375 -0.25q0.390625 -0.234375 0.625 -0.703125q0.140625 -0.265625 0.140625 -0.671875l0 -1.609375q-0.84375 1.171875 -2.203125 1.171875q-1.09375 0 -1.890625 -0.8125q-0.796875 -0.8125 -0.796875 -1.953125q0 -1.15625 0.796875 -1.96875q0.796875 -0.8125 1.890625 -0.8125q1.359375 0 2.203125 1.171875zm0 1.609375q0 -0.953125 -0.640625 -1.59375q-0.640625 -0.640625 -1.53125 -0.640625q-0.90625 0 -1.546875 0.65625q-0.640625 0.640625 -0.640625 1.578125q0 0.9375 0.640625 1.59375q0.640625 0.640625 1.546875 0.640625q0.890625 0 1.53125 -0.640625q0.640625 -0.65625 0.640625 -1.59375z" fill-rule="nonzero"/><path fill="#000000" d="m109.876724 649.3672l-3.5 0l-0.71875 1.953125l1.015625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.40625 0l2.359375 -6.359375l-1.578125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.6875 0l2.59375 6.890625l0.421875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.015625 0l-0.734375 -1.953125zm-0.203125 -0.53125l-1.46875 -3.875l-0.203125 0l-1.421875 3.875l3.09375 0zm6.5200195 -4.953125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm15.805664 7.96875l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125zm7.4887695 -2.234375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm15.383789 5.140625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm5.6293945 -2.84375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm16.13379 0.53125l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm5.9262695 3.15625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm3.7231445 -2.34375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm8.441895 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm10.707504 5.5l0 -0.78125q-1.078125 0.984375 -2.3593597 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.2968597 0 2.3749847 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm7.5200195 0l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.5668945 7.96875l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875zm18.180664 -7.96875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.9887695 5.5l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm13.180664 -2.21875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm7.5200195 -0.546875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.410645 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm2.9262695 -2.765625l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm20.25879 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm5.8481445 -3.28125l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.5043945 0l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.03125 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.828125 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 2.59375q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.65625 0.671875 -1.578125zm8.73877 6.46875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.2387695 -11.53125l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.7231445 2.734375l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm9.004395 6.71875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125z" fill-rule="nonzero"/><path fill="#fff2cc" d="m104.34908 682.29987l0 0c0 -12.008484 9.734772 -21.743225 21.743217 -21.743225l415.50568 0c5.7666626 0 11.29718 2.2907715 15.374817 6.368408c4.0776367 4.0776367 6.368408 9.608154 6.368408 15.374817l0 86.970215c0 12.008484 -9.734741 21.743225 -21.743225 21.743225l-415.50568 0c-12.008446 0 -21.743217 -9.734741 -21.743217 -21.743225z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m104.34908 682.29987l0 0c0 -12.008484 9.734772 -21.743225 21.743217 -21.743225l415.50568 0c5.7666626 0 11.29718 2.2907715 15.374817 6.368408c4.0776367 4.0776367 6.368408 9.608154 6.368408 15.374817l0 86.970215c0 12.008484 -9.734741 21.743225 -21.743225 21.743225l-415.50568 0c-12.008446 0 -21.743217 -9.734741 -21.743217 -21.743225z" fill-rule="evenodd"/><path fill="#000000" d="m236.6328 692.6575q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.156967 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816696 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125717 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm9.806427 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.089538574 5.171875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891357 -3.703125l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688202 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641327 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235107 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816681 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm4.712677 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm13.391327 -3.703125l-1.515625 0l0 -13.359375l1.640625 0l0 4.765625q1.046875 -1.296875 2.65625 -1.296875q0.890625 0 1.6875 0.359375q0.796875 0.359375 1.3125 1.015625q0.515625 0.640625 0.796875 1.5625q0.296875 0.921875 0.296875 1.96875q0 2.484375 -1.234375 3.84375q-1.21875 1.359375 -2.953125 1.359375q-1.703125 0 -2.6875 -1.4375l0 1.21875zm-0.015625 -4.90625q0 1.734375 0.484375 2.515625q0.765625 1.265625 2.09375 1.265625q1.078125 0 1.859375 -0.9375q0.78125 -0.9375 0.78125 -2.78125q0 -1.890625 -0.75 -2.796875q-0.75 -0.90625 -1.828125 -0.90625q-1.0625 0 -1.859375 0.9375q-0.78125 0.9375 -0.78125 2.703125zm15.203857 3.71875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.7812195 0.28125 1.1405945 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.7030945 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm3.547577 1.96875l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm7.6257324 9.46875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm14.578827 -3.703125l-3.6875 -9.671875l1.734375 0l2.078125 5.796875q0.328125 0.9375 0.625 1.9375q0.203125 -0.765625 0.609375 -1.828125l2.140625 -5.90625l1.6875 0l-3.65625 9.671875l-1.53125 0zm5.984375 -2.890625l1.625 -0.25q0.125 0.96875 0.75 1.5q0.625 0.515625 1.75 0.515625q1.125 0 1.671875 -0.453125q0.546875 -0.46875 0.546875 -1.09375q0 -0.546875 -0.484375 -0.875q-0.328125 -0.21875 -1.671875 -0.546875q-1.8125 -0.46875 -2.515625 -0.796875q-0.6875 -0.328125 -1.046875 -0.90625q-0.359375 -0.59375 -0.359375 -1.3125q0 -0.640625 0.296875 -1.1875q0.296875 -0.5625 0.8125 -0.921875q0.375 -0.28125 1.03125 -0.46875q0.671875 -0.203125 1.421875 -0.203125q1.140625 0 2.0 0.328125q0.859375 0.328125 1.265625 0.890625q0.421875 0.5625 0.578125 1.5l-1.609375 0.21875q-0.109375 -0.75 -0.640625 -1.171875q-0.515625 -0.421875 -1.46875 -0.421875q-1.140625 0 -1.625 0.375q-0.46875 0.375 -0.46875 0.875q0 0.3125 0.1875 0.578125q0.203125 0.265625 0.640625 0.4375q0.234375 0.09375 1.4375 0.421875q1.75 0.453125 2.4375 0.75q0.6875 0.296875 1.078125 0.859375q0.390625 0.5625 0.390625 1.40625q0 0.828125 -0.484375 1.546875q-0.46875 0.71875 -1.375 1.125q-0.90625 0.390625 -2.046875 0.390625q-1.875 0 -2.875 -0.78125q-0.984375 -0.78125 -1.25 -2.328125zm16.609375 -0.21875l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm15.297577 9.46875l0 -4.734375q-0.375 0.546875 -1.0625 0.90625q-0.6875 0.34375 -1.46875 0.34375q-1.71875 0 -2.96875 -1.375q-1.234375 -1.375 -1.234375 -3.765625q0 -1.46875 0.5 -2.625q0.515625 -1.15625 1.46875 -1.75q0.96875 -0.59375 2.109375 -0.59375q1.796875 0 2.828125 1.515625l0 -1.296875l1.46875 0l0 13.375l-1.640625 0zm-5.046875 -8.5625q0 1.859375 0.78125 2.796875q0.78125 0.9375 1.875 0.9375q1.046875 0 1.796875 -0.890625q0.765625 -0.890625 0.765625 -2.703125q0 -1.9375 -0.796875 -2.90625q-0.796875 -0.96875 -1.875 -0.96875q-1.0625 0 -1.8125 0.90625q-0.734375 0.90625 -0.734375 2.828125z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m104.34908 725.785c-12.5 0 -26.850395 -95.968506 -25.000008 -191.93701c1.8503952 -95.968506 19.90158 -191.93701 39.803154 -191.93701" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="4.0,3.0" d="m104.34908 725.785c-12.5 0 -26.850395 -95.968506 -25.000008 -191.93701c1.8503952 -95.968506 19.90158 -191.93701 39.803154 -191.93701" fill-rule="evenodd"/><path fill="#cfe2f3" d="m115.7874 700.15485l426.32513 0l14.745728 14.745728l0 73.726746l-441.07086 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m115.7874 700.15485l426.32513 0l14.745728 14.745728l0 73.726746l-441.07086 0z" fill-rule="evenodd"/><path fill="#000000" d="m126.959274 725.73395l0 3.0625l4.09375 0l0 -1.578125q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.125 0 0.1875 0.09375q0.078125 0.078125 0.078125 0.265625l0 2.109375l-5.875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.703125 0l0 -6.359375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l5.59375 0l0 1.828125q0 0.1875 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.125 0 -0.203125 -0.078125q-0.0625 -0.09375 -0.0625 -0.28125l0 -1.296875l-3.8125 0l0 2.765625l1.90625 0l0 -0.59375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.1875 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.734375q0 0.1875 -0.078125 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -0.609375l-1.90625 0zm9.89502 0.71875l2.4375 2.34375q0.25 0 0.3125 0.03125q0.0625 0.015625 0.109375 0.09375q0.046875 0.0625 0.046875 0.140625q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.890625 0l-2.078125 -1.984375l-2.0625 1.984375l0.890625 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.078125 0.046875 -0.140625q0.046875 -0.078125 0.109375 -0.09375q0.0625 -0.03125 0.296875 -0.03125l2.453125 -2.34375l-2.171875 -2.078125q-0.234375 0 -0.296875 -0.03125q-0.0625 -0.03125 -0.109375 -0.09375q-0.046875 -0.0625 -0.046875 -0.15625q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.640625 0l1.796875 1.734375l1.8125 -1.734375l-0.640625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.046875 0.140625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.03125 -0.296875 0.03125l-2.171875 2.078125zm6.3481445 -2.625l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm11.77002 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm3.7231445 -2.34375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm13.180664 -2.21875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm7.5200195 -0.546875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.410645 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm2.9262695 -2.765625l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm20.25879 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm5.8481445 -3.28125l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm5.5043945 0l0 0.96875q0.484375 -0.578125 1.015625 -0.859375q0.546875 -0.296875 1.296875 -0.296875q0.78125 0 1.453125 0.375q0.671875 0.359375 1.0312653 1.015625q0.359375 0.65625 0.359375 1.390625q0 1.140625 -0.82814026 1.953125q-0.8125 0.8125 -2.015625 0.8125q-1.421875 0 -2.3125 -1.15625l0 3.21875l1.296875 0q0.1875 0 0.265625 0.0625q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l0.71875 0l0 -6.875l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.6250153 2.59375q0 -0.921875 -0.67189026 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.67189026 -0.65625 0.67189026 -1.578125zm8.73877 6.46875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.2387695 -11.53125l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.7231445 2.734375l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm9.004395 6.71875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125z" fill-rule="nonzero"/><path fill="#000000" d="m127.5374 742.2808l0 2.515625l1.828125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.09375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.359375l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l3.109375 0q1.09375 0 1.78125 0.65625q0.703125 0.640625 0.703125 1.5q0 0.515625 -0.234375 0.9375q-0.21875 0.40625 -0.53125 0.640625q-0.484375 0.359375 -0.984375 0.515625q-0.375 0.125 -0.921875 0.125l-1.65625 0zm0 -0.53125l1.6875 0q0.59375 0 1.109375 -0.265625q0.515625 -0.265625 0.75 -0.640625q0.25 -0.390625 0.25 -0.78125q0 -0.625 -0.546875 -1.125q-0.53125 -0.5 -1.359375 -0.5l-1.890625 0l0 3.3125zm8.316895 -1.921875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.410645 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm5.8325195 2.734375l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm7.5981445 -8.234375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm10.129395 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.2075195 -1.984375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm11.415039 -0.359375l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm7.1137695 -2.40625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm4.9575195 -0.359375l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm18.91504 0.546875l0 -0.1875q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 1.21875q-0.015625 0.1875 -0.09375 0.28125q-0.0625 0.078125 -0.1875 0.078125q-0.109375 0 -0.1875 -0.078125q-0.0625 -0.078125 -0.078125 -0.25q-0.03125 -0.4375 -0.59375 -0.84375q-0.546875 -0.40625 -1.5 -0.40625q-1.1875 0 -1.796875 0.75q-0.609375 0.734375 -0.609375 1.6875q0 1.03125 0.671875 1.703125q0.6875 0.671875 1.765625 0.671875q0.609375 0 1.25 -0.21875q0.65625 -0.234375 1.171875 -0.734375q0.140625 -0.140625 0.234375 -0.140625q0.109375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.265625 -0.640625 0.6875q-1.03125 0.671875 -2.296875 0.671875q-1.28125 0 -2.125 -0.8125q-0.828125 -0.828125 -0.828125 -2.09375q0 -1.28125 0.84375 -2.125q0.859375 -0.859375 2.140625 -0.859375q1.234375 0 2.0625 0.734375zm8.55127 2.21875q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm2.9262695 -2.765625l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.92189026 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.98439026 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm7.801285 0l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm3.6293945 -2.765625l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm9.80127 -2.46875l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.5668945 7.96875l-2.484375 -4.953125l-0.15625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.09375 0.03125 -0.15625q0.046875 -0.0625 0.109375 -0.09375q0.0625 -0.03125 0.203125 -0.03125l1.46875 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.71875 0l2.171875 4.375l2.140625 -4.375l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.078125 -0.0625 0.15625q-0.046875 0.0625 -0.109375 0.09375q-0.0625 0.015625 -0.359375 0.015625l-3.375 6.875l0.84375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-3.078125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l1.671875 0l0.9375 -1.921875zm17.38379 0l0 -0.78125q-1.078125 0.984375 -2.359375 0.984375q-0.78125 0 -1.1875 -0.421875q-0.515625 -0.5625 -0.515625 -1.296875l0 -3.4375l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0l0 3.984375q0 0.515625 0.328125 0.859375q0.328125 0.328125 0.828125 0.328125q1.296875 0 2.375 -1.1875l0 -3.4375l-0.984375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.53125 0l0 4.96875l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0zm7.7387695 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm12.446289 -2.765625l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm10.42627 5.5l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm4.9575195 2.765625l0 2.375l-1.25 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0l0 4.921875l2.265625 -1.90625l-0.265625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.078125 0.28125 -0.078125l1.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.609375 0l-2.078125 1.734375l2.625 2.6875l0.625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.375 0l-2.296875 -2.359375l-0.609375 0.515625zm10.64502 -2.765625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm15.383789 5.140625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm3.8325195 -2.84375l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm13.20752 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm3.6293945 -2.765625l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm11.316895 0.984375l0 -0.984375l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.703125 0l0 5.328125q0 0.53125 -0.234375 0.953125q-0.15625 0.265625 -0.515625 0.5625q-0.34375 0.3125 -0.640625 0.4375q-0.296875 0.125 -0.78125 0.125l-1.515625 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.265625 -0.078125l1.53125 0.015625q0.46875 0 0.84375 -0.25q0.390625 -0.234375 0.625 -0.703125q0.140625 -0.265625 0.140625 -0.671875l0 -1.609375q-0.84375 1.171875 -2.203125 1.171875q-1.09375 0 -1.890625 -0.8125q-0.796875 -0.8125 -0.796875 -1.953125q0 -1.15625 0.796875 -1.96875q0.796875 -0.8125 1.890625 -0.8125q1.359375 0 2.203125 1.171875zm0 1.609375q0 -0.953125 -0.640625 -1.59375q-0.640625 -0.640625 -1.53125 -0.640625q-0.90625 0 -1.546875 0.65625q-0.640625 0.640625 -0.640625 1.578125q0 0.9375 0.640625 1.59375q0.640625 0.640625 1.546875 0.640625q0.890625 0 1.53125 -0.640625q0.640625 -0.65625 0.640625 -1.59375zm15.352539 2.90625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm15.805664 7.96875l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125zm7.4887695 -2.234375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm5.9418945 3.609375l0.21875 0q0.359375 0 0.609375 0.25q0.25 0.25 0.25 0.609375q0 0.359375 -0.25 0.609375q-0.25 0.25 -0.609375 0.25l-0.21875 0q-0.359375 0 -0.625 -0.25q-0.25 -0.25 -0.25 -0.609375q0 -0.359375 0.25 -0.609375q0.265625 -0.25 0.625 -0.25z" fill-rule="nonzero"/><path fill="#000000" d="m130.44365 758.8433l-3.5 0l-0.71875 1.953125l1.015625 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.40625 0l2.359375 -6.359375l-1.578125 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.6875 0l2.59375 6.890625l0.421875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.984375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.015625 0l-0.734375 -1.953125zm-0.203125 -0.53125l-1.46875 -3.875l-0.203125 0l-1.421875 3.875l3.09375 0zm6.5200195 -4.953125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm7.8012695 0l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm16.868164 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm7.3481445 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.4887695 -11.53125l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm4.5356445 -2.84375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.0043945 -5.234375l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.87501526 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21876526 -0.234375 -0.39064026 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm16.71193 5.5l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125zm7.4887695 -2.234375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm15.383789 5.140625l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm5.6293945 -2.84375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.316895 2.875l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm15.868164 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm8.61377 0.109375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm8.70752 -2.734375l0 1.375l-0.796875 0l0 -1.375l0.796875 0zm0.015625 2.734375l0 4.96875l2.09375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.71875 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l2.09375 0l0 -4.421875l-1.5625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.078125 0.28125 -0.078125l2.09375 0zm7.9887695 5.5l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm10.20752 -2.625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm8.066895 -4.8125l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm13.180664 -2.21875l0 4.421875l2.34375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-4.171875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.421875l-1.15625 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.15625 0l0 -0.796875q0 -0.671875 0.53125 -1.171875q0.546875 -0.5 1.453125 -0.5q0.75 0 1.609375 0.140625q0.328125 0.046875 0.390625 0.125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.0625 -0.203125 0.0625q-0.0625 0 -0.171875 -0.015625q-0.96875 -0.140625 -1.625 -0.140625q-0.703125 0 -1.078125 0.34375q-0.375 0.34375 -0.375 0.78125l0 0.796875l2.5 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.5 0zm7.5200195 -0.546875l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.410645 2.765625q0 1.21875 -0.875 2.078125q-0.859375 0.859375 -2.09375 0.859375q-1.25 0 -2.125 -0.859375q-0.859375 -0.875 -0.859375 -2.078125q0 -1.21875 0.859375 -2.078125q0.875 -0.875 2.125 -0.875q1.234375 0 2.09375 0.859375q0.875 0.859375 0.875 2.09375zm-0.53125 0q0 -1.0 -0.71875 -1.703125q-0.71875 -0.703125 -1.734375 -0.703125q-1.015625 0 -1.734375 0.703125q-0.703125 0.703125 -0.703125 1.703125q0 0.984375 0.703125 1.703125q0.71875 0.703125 1.734375 0.703125q1.015625 0 1.734375 -0.703125q0.71875 -0.703125 0.71875 -1.703125zm2.9262695 -2.765625l0 0.546875q0.6875 -0.734375 1.375 -0.734375q0.40625 0 0.71875 0.21875q0.3125 0.21875 0.515625 0.65625q0.359375 -0.4375 0.71875 -0.65625q0.375 -0.21875 0.734375 -0.21875q0.578125 0 0.921875 0.375q0.453125 0.484375 0.453125 1.046875l0 3.734375l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.984375 0l0 -4.203125q0 -0.40625 -0.25 -0.671875q-0.25 -0.265625 -0.578125 -0.265625q-0.28125 0 -0.609375 0.21875q-0.328125 0.21875 -0.734375 0.859375l0 3.53125l0.4375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.984375 0l0 -4.171875q0 -0.421875 -0.25 -0.6875q-0.25 -0.28125 -0.5625 -0.28125q-0.28125 0 -0.5625 0.171875q-0.390625 0.265625 -0.8125 0.90625l0 3.53125l0.453125 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.453125 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0z" fill-rule="nonzero"/><path fill="#000000" d="m130.2249 777.3277l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm6.5356445 -5.3125l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm7.3481445 0l2.890625 0q0.1875 0 0.265625 0.078125q0.09375 0.078125 0.09375 0.203125q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-2.890625 0l0 3.546875q0 0.453125 0.359375 0.765625q0.375 0.3125 1.09375 0.3125q0.546875 0 1.171875 -0.15625q0.625 -0.15625 0.96875 -0.359375q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.09375 -0.078125 0.1875q-0.203125 0.203125 -1.0 0.453125q-0.78125 0.234375 -1.5 0.234375q-0.921875 0 -1.484375 -0.4375q-0.546875 -0.4375 -0.546875 -1.171875l0 -3.546875l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.984375 0l0 -1.578125q0 -0.1875 0.078125 -0.265625q0.078125 -0.078125 0.1875 -0.078125q0.125 0 0.203125 0.078125q0.078125 0.078125 0.078125 0.265625l0 1.578125zm12.441895 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.4887695 -11.53125l0 3.28125q0.515625 -0.546875 0.984375 -0.765625q0.46875 -0.234375 1.046875 -0.234375q0.609375 0 1.046875 0.21875q0.4375 0.21875 0.71875 0.671875q0.296875 0.453125 0.296875 0.953125l0 3.3125l0.609375 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.296875 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.296875 -0.078125l0.59375 0l0 -3.265625q0 -0.578125 -0.421875 -0.96875q-0.40625 -0.390625 -1.15625 -0.390625q-0.578125 0 -1.0 0.28125q-0.296875 0.203125 -0.984375 0.96875l0 3.375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l1.25 0zm11.098145 7.96875l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm4.5356445 -2.84375l0 0.8125q0.5625 -0.5625 1.015625 -0.78125q0.453125 -0.21875 1.015625 -0.21875q0.609375 0 1.109375 0.265625q0.359375 0.1875 0.640625 0.625q0.296875 0.4375 0.296875 0.90625l0 3.359375l0.453125 0q0.1875 0 0.265625 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.4375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.453125 0l0 -3.265625q0 -0.578125 -0.421875 -0.953125q-0.40625 -0.390625 -1.09375 -0.390625q-0.53125 0 -0.921875 0.21875q-0.390625 0.203125 -1.109375 1.046875l0 3.34375l0.609375 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.734375 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l0.59375 0l0 -4.421875l-0.453125 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.265625 -0.078125l0.984375 0zm12.14502 -2.46875l0 7.4375l0.703125 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-1.25 0l0 -1.0625q-0.921875 1.265625 -2.34375 1.265625q-0.734375 0 -1.40625 -0.375q-0.65625 -0.390625 -1.046875 -1.09375q-0.375 -0.71875 -0.375 -1.46875q0 -0.765625 0.375 -1.46875q0.390625 -0.703125 1.046875 -1.09375q0.671875 -0.390625 1.40625 -0.390625q1.390625 0 2.34375 1.265625l0 -3.0l-0.703125 0q-0.203125 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.25 0zm-0.546875 5.234375q0 -1.015625 -0.6875 -1.703125q-0.671875 -0.703125 -1.625 -0.703125q-0.953125 0 -1.640625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.6875 0.703125 1.640625 0.703125q0.953125 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.0043945 -5.234375l0 7.4375l2.09375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.09375 0l0 -6.890625l-1.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.078125 0zm10.410645 5.34375l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm4.8168945 -2.34375l0 1.34375q1.03125 -0.9375 1.546875 -1.203125q0.53125 -0.265625 0.96875 -0.265625q0.46875 0 0.875 0.328125q0.421875 0.3125 0.421875 0.46875q0 0.125 -0.09375 0.203125q-0.078125 0.078125 -0.1875 0.078125q-0.0625 0 -0.109375 -0.015625q-0.046875 -0.03125 -0.171875 -0.140625q-0.21875 -0.234375 -0.390625 -0.3125q-0.15625 -0.078125 -0.3125 -0.078125q-0.359375 0 -0.859375 0.28125q-0.484375 0.28125 -1.6875 1.359375l0 2.921875l2.359375 0q0.203125 0 0.28125 0.078125q0.078125 0.0625 0.078125 0.1875q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-4.1875 0q-0.1875 0 -0.28125 -0.0625q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.171875q0.09375 -0.078125 0.28125 -0.078125l1.296875 0l0 -4.4375l-0.984375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.078125 -0.078125 0.28125 -0.078125l1.515625 0zm11.98877 9.0625l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm2.2387695 -11.53125l0 3.53125q0.96875 -1.25 2.328125 -1.25q1.171875 0 2.0 0.84375q0.828125 0.84375 0.828125 2.078125q0 1.25 -0.84375 2.109375q-0.828125 0.859375 -1.984375 0.859375q-1.390625 0 -2.328125 -1.25l0 1.046875l-1.25 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l0.71875 0l0 -6.890625l-0.71875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l1.25 0zm4.625 5.234375q0 -1.015625 -0.6875 -1.703125q-0.6875 -0.703125 -1.625 -0.703125q-0.921875 0 -1.625 0.703125q-0.6875 0.6875 -0.6875 1.703125q0 1.0 0.6875 1.703125q0.703125 0.703125 1.625 0.703125q0.9375 0 1.625 -0.703125q0.6875 -0.703125 0.6875 -1.703125zm6.7231445 2.734375l0 -0.765625q-1.171875 0.96875 -2.484375 0.96875q-0.953125 0 -1.5 -0.484375q-0.53125 -0.484375 -0.53125 -1.1875q0 -0.765625 0.703125 -1.34375q0.71875 -0.578125 2.078125 -0.578125q0.359375 0 0.796875 0.046875q0.4375 0.046875 0.9375 0.140625l0 -0.859375q0 -0.4375 -0.40625 -0.75q-0.40625 -0.328125 -1.21875 -0.328125q-0.625 0 -1.75 0.359375q-0.203125 0.0625 -0.265625 0.0625q-0.09375 0 -0.171875 -0.078125q-0.0625 -0.078125 -0.0625 -0.1875q0 -0.109375 0.0625 -0.171875q0.078125 -0.09375 0.71875 -0.265625q0.984375 -0.265625 1.484375 -0.265625q1.015625 0 1.578125 0.5q0.5625 0.5 0.5625 1.125l0 3.53125l0.71875 0q0.1875 0 0.265625 0.078125q0.09375 0.0625 0.09375 0.1875q0 0.109375 -0.09375 0.1875q-0.078125 0.078125 -0.265625 0.078125l-1.25 0zm0 -2.65625q-0.375 -0.109375 -0.796875 -0.15625q-0.421875 -0.046875 -0.875 -0.046875q-1.171875 0 -1.828125 0.5q-0.484375 0.375 -0.484375 0.890625q0 0.484375 0.375 0.8125q0.375 0.328125 1.09375 0.328125q0.703125 0 1.296875 -0.265625q0.59375 -0.28125 1.21875 -0.890625l0 -1.171875zm8.02002 -2.484375q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.29689026 0.390625 0.29689026 0.84375q0 0.6875 -0.65626526 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.926285 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm9.004395 6.71875l-7.09375 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.0625 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.09375 -0.0625 0.28125 -0.0625l7.09375 0q0.1875 0 0.265625 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.125 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125zm4.7231445 -3.5625l-0.90625 0l-2.1875 -4.953125l-0.546875 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.0 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.890625 0l1.953125 4.421875l0.234375 0l1.921875 -4.421875l-0.890625 0q-0.1875 0 -0.28125 -0.078125q-0.078125 -0.078125 -0.078125 -0.203125q0 -0.109375 0.078125 -0.1875q0.09375 -0.078125 0.28125 -0.078125l2.015625 0q0.1875 0 0.265625 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.265625 0.078125l-0.546875 0l-2.15625 4.953125zm9.08252 -5.140625q0 -0.1875 0.078125 -0.265625q0.078125 -0.09375 0.1875 -0.09375q0.125 0 0.203125 0.09375q0.078125 0.078125 0.078125 0.265625l0 0.921875q0 0.1875 -0.078125 0.28125q-0.078125 0.078125 -0.203125 0.078125q-0.09375 0 -0.171875 -0.0625q-0.078125 -0.078125 -0.09375 -0.25q-0.03125 -0.375 -0.390625 -0.625q-0.515625 -0.34375 -1.375 -0.34375q-0.890625 0 -1.390625 0.359375q-0.375 0.265625 -0.375 0.609375q0 0.375 0.453125 0.625q0.296875 0.1875 1.140625 0.28125q1.125 0.109375 1.546875 0.265625q0.625 0.21875 0.921875 0.625q0.296875 0.390625 0.296875 0.84375q0 0.6875 -0.65625 1.21875q-0.640625 0.515625 -1.90625 0.515625q-1.265625 0 -2.078125 -0.640625q0 0.21875 -0.03125 0.28125q-0.015625 0.0625 -0.09375 0.109375q-0.0625 0.046875 -0.140625 0.046875q-0.109375 0 -0.1875 -0.078125q-0.078125 -0.09375 -0.078125 -0.28125l0 -1.09375q0 -0.1875 0.0625 -0.265625q0.078125 -0.09375 0.203125 -0.09375q0.109375 0 0.1875 0.078125q0.09375 0.078125 0.09375 0.21875q0 0.296875 0.140625 0.484375q0.21875 0.3125 0.703125 0.515625q0.484375 0.1875 1.1875 0.1875q1.046875 0 1.546875 -0.375q0.515625 -0.390625 0.515625 -0.828125q0 -0.5 -0.515625 -0.796875q-0.515625 -0.296875 -1.515625 -0.390625q-0.984375 -0.109375 -1.421875 -0.265625q-0.4375 -0.171875 -0.671875 -0.5q-0.234375 -0.328125 -0.234375 -0.71875q0 -0.671875 0.671875 -1.078125q0.671875 -0.40625 1.59375 -0.40625q1.109375 0 1.796875 0.546875zm8.92627 2.515625l-5.421875 0q0.125 1.03125 0.859375 1.671875q0.734375 0.625 1.796875 0.625q0.59375 0 1.25 -0.1875q0.65625 -0.203125 1.0625 -0.53125q0.125 -0.09375 0.21875 -0.09375q0.09375 0 0.171875 0.078125q0.078125 0.078125 0.078125 0.1875q0 0.109375 -0.09375 0.21875q-0.3125 0.3125 -1.09375 0.59375q-0.765625 0.265625 -1.59375 0.265625q-1.375 0 -2.296875 -0.890625q-0.90625 -0.90625 -0.90625 -2.171875q0 -1.171875 0.859375 -2.0q0.859375 -0.828125 2.125 -0.828125q1.3125 0 2.15625 0.859375q0.84375 0.84375 0.828125 2.203125zm-0.53125 -0.53125q-0.15625 -0.890625 -0.84375 -1.4375q-0.671875 -0.546875 -1.609375 -0.546875q-0.921875 0 -1.59375 0.546875q-0.671875 0.53125 -0.84375 1.4375l4.890625 0zm7.5200195 -1.375l0 -0.96875l1.25 0q0.203125 0 0.28125 0.078125q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-0.71875 0l0 6.875l0.71875 0q0.203125 0 0.28125 0.0625q0.078125 0.078125 0.078125 0.203125q0 0.109375 -0.078125 0.1875q-0.078125 0.078125 -0.28125 0.078125l-2.546875 0q-0.1875 0 -0.265625 -0.078125q-0.078125 -0.078125 -0.078125 -0.1875q0 -0.125 0.078125 -0.203125q0.078125 -0.0625 0.265625 -0.0625l1.296875 0l0 -3.21875q-0.890625 1.15625 -2.3125 1.15625q-1.203125 0 -2.03125 -0.8125q-0.8125 -0.8125 -0.8125 -1.953125q0 -1.15625 0.8125 -1.96875q0.828125 -0.8125 2.03125 -0.8125q1.421875 0 2.3125 1.15625zm0 1.625q0 -0.921875 -0.671875 -1.578125q-0.671875 -0.65625 -1.640625 -0.65625q-0.96875 0 -1.640625 0.65625q-0.671875 0.65625 -0.671875 1.578125q0 0.90625 0.671875 1.578125q0.671875 0.65625 1.640625 0.65625q0.96875 0 1.640625 -0.65625q0.671875 -0.671875 0.671875 -1.578125z" fill-rule="nonzero"/><path fill="#ffe599" d="m181.12599 185.21538l0 0c0 -4.4009705 3.567688 -7.9686584 7.9686584 -7.9686584l122.20439 0c2.1134338 0 4.1402893 0.83955383 5.6347046 2.333969c1.4944153 1.4944153 2.3339844 3.5212708 2.3339844 5.6346893l0 31.873703c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-122.20439 0c-4.4009705 0 -7.9686584 -3.567688 -7.9686584 -7.9686584z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m181.12599 185.21538l0 0c0 -4.4009705 3.567688 -7.9686584 7.9686584 -7.9686584l122.20439 0c2.1134338 0 4.1402893 0.83955383 5.6347046 2.333969c1.4944153 1.4944153 2.3339844 3.5212708 2.3339844 5.6346893l0 31.873703c0 4.4009705 -3.5677185 7.9686584 -7.968689 7.9686584l-122.20439 0c-4.4009705 0 -7.9686584 -3.567688 -7.9686584 -7.9686584z" fill-rule="evenodd"/><path fill="#000000" d="m205.51717 202.90941q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.2109375 -3.1875l0 -11.453125l1.40625 0l0 4.109375q0.984375 -1.140625 2.484375 -1.140625q0.921875 0 1.59375 0.359375q0.6875 0.359375 0.96875 1.0q0.296875 0.640625 0.296875 1.859375l0 5.265625l-1.40625 0l0 -5.265625q0 -1.046875 -0.453125 -1.53125q-0.453125 -0.484375 -1.296875 -0.484375q-0.625 0 -1.171875 0.328125q-0.546875 0.328125 -0.78125 0.890625q-0.234375 0.546875 -0.234375 1.515625l0 4.546875l-1.40625 0zm14.3046875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.35935974 1.0l-1.4687347 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015472 4.171875l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.2734375 0l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm7.9296875 4.140625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0z" fill-rule="nonzero"/><path fill="#000000" d="m227.13435 220.26878l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.1953125 0l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm4.390625 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.617172 -6.234375l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.0312347 -1.125 -1.0312347 -3.203125q0 -1.34375 0.43748474 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.0625 -1.109375q0 -2.296875 1.28125 -3.40625q1.078125 -0.921875 2.609375 -0.921875q1.71875 0 2.796875 1.125q1.09375 1.109375 1.09375 3.09375q0 1.59375 -0.484375 2.515625q-0.484375 0.921875 -1.40625 1.4375q-0.90625 0.5 -2.0 0.5q-1.734375 0 -2.8125 -1.109375q-1.078125 -1.125 -1.078125 -3.234375zm1.453125 0q0 1.59375 0.6875 2.390625q0.703125 0.796875 1.75 0.796875q1.046875 0 1.734375 -0.796875q0.703125 -0.796875 0.703125 -2.4375q0 -1.53125 -0.703125 -2.328125q-0.6875 -0.796875 -1.734375 -0.796875q-1.046875 0 -1.75 0.796875q-0.6875 0.78125 -0.6875 2.375zm10.2734375 4.15625l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m488.67978 559.9895c0 12.5 -39.3349 47.255676 -72.18787 25.0c-32.852966 -22.255615 -59.223938 -101.52255 -72.18787 -191.91733c-12.963928 -90.394745 -12.520782 -191.91731 -25.041565 -191.91731" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m488.67978 559.9895c0 12.5 -39.3349 47.255676 -72.18787 25.0c-32.852966 -22.255615 -59.223938 -101.52255 -72.18787 -191.91733c-12.963928 -90.394745 -12.520782 -191.91731 -25.041565 -191.91731" fill-rule="evenodd"/><path fill="#d9ead3" d="m119.14173 505.9962l0 0c0 -3.70224 3.0012817 -6.7035217 6.7035446 -6.7035217l186.7189 0c1.7778931 0 3.4829712 0.7062378 4.7401123 1.9634094c1.2571716 1.2571716 1.96344 2.9622192 1.96344 4.7401123l0 26.813385c0 3.7022705 -3.0012817 6.7035522 -6.7035522 6.7035522l-186.7189 0l0 0c-3.7022629 0 -6.7035446 -3.0012817 -6.7035446 -6.7035522z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m119.14173 505.9962l0 0c0 -3.70224 3.0012817 -6.7035217 6.7035446 -6.7035217l186.7189 0c1.7778931 0 3.4829712 0.7062378 4.7401123 1.9634094c1.2571716 1.2571716 1.96344 2.9622192 1.96344 4.7401123l0 26.813385c0 3.7022705 -3.0012817 6.7035522 -6.7035522 6.7035522l-186.7189 0l0 0c-3.7022629 0 -6.7035446 -3.0012817 -6.7035446 -6.7035522z" fill-rule="evenodd"/><path fill="#000000" d="m168.74379 524.5848q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.8828125 -5.859375l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.2734375 2.46875l1.390625 -0.21875q0.109375 0.84375 0.640625 1.296875q0.546875 0.4375 1.5 0.4375q0.96875 0 1.4375 -0.390625q0.46875 -0.40625 0.46875 -0.9375q0 -0.46875 -0.40625 -0.75q-0.296875 -0.1875 -1.4375 -0.46875q-1.546875 -0.390625 -2.15625 -0.671875q-0.59375 -0.296875 -0.90625 -0.796875q-0.296875 -0.5 -0.296875 -1.109375q0 -0.5625 0.25 -1.03125q0.25 -0.46875 0.6875 -0.78125q0.328125 -0.25 0.890625 -0.40625q0.578125 -0.171875 1.21875 -0.171875q0.984375 0 1.71875 0.28125q0.734375 0.28125 1.078125 0.765625q0.359375 0.46875 0.5 1.28125l-1.375 0.1875q-0.09375 -0.640625 -0.546875 -1.0q-0.453125 -0.359375 -1.265625 -0.359375q-0.96875 0 -1.390625 0.328125q-0.40625 0.3125 -0.40625 0.734375q0 0.28125 0.171875 0.5q0.171875 0.21875 0.53125 0.375q0.21875 0.078125 1.25 0.359375q1.484375 0.390625 2.078125 0.65625q0.59375 0.25 0.921875 0.734375q0.34375 0.484375 0.34375 1.203125q0 0.703125 -0.421875 1.328125q-0.40625 0.609375 -1.1875 0.953125q-0.765625 0.34375 -1.734375 0.34375q-1.625 0 -2.46875 -0.671875q-0.84375 -0.671875 -1.078125 -2.0zm13.96875 -0.5625l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm1.28125 6.234375l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -4.21875q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.3359375 4.859375l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm13.664078 1.625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.8906403 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.0781403 -1.15625 2.7968903 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875153 0q0.07814026 1.375 0.76564026 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625z" fill-rule="nonzero"/><path fill="#ffffff" d="m991.7638 141.39633l216.0 0l0 356.78738l-216.0 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m991.7638 141.39633l216.0 0l0 356.78738l-216.0 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1071.8583 143.0971l166.07874 0l0 38.80316l-166.07874 0z" fill-rule="evenodd"/><path fill="#000000" d="m1088.4052 168.8296q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.1569824 4.859375l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.81665 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm9.8063965 -1.46875l0.234375 1.453125q-0.6875 0.140625 -1.234375 0.140625q-0.890625 0 -1.390625 -0.28125q-0.484375 -0.28125 -0.6875 -0.734375q-0.203125 -0.46875 -0.203125 -1.9375l0 -5.578125l-1.203125 0l0 -1.265625l1.203125 0l0 -2.390625l1.625 -0.984375l0 3.375l1.65625 0l0 1.265625l-1.65625 0l0 5.671875q0 0.6875 0.078125 0.890625q0.09375 0.203125 0.28125 0.328125q0.203125 0.109375 0.578125 0.109375q0.265625 0 0.71875 -0.0625zm0.08959961 5.171875l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891357 -3.703125l0 -13.359375l1.640625 0l0 4.796875q1.140625 -1.328125 2.890625 -1.328125q1.078125 0 1.859375 0.421875q0.796875 0.421875 1.140625 1.171875q0.34375 0.75 0.34375 2.171875l0 6.125l-1.640625 0l0 -6.125q0 -1.234375 -0.53125 -1.796875q-0.53125 -0.5625 -1.515625 -0.5625q-0.71875 0 -1.359375 0.390625q-0.640625 0.375 -0.921875 1.015625q-0.265625 0.640625 -0.265625 1.78125l0 5.296875l-1.640625 0zm16.688232 -1.1875q-0.921875 0.765625 -1.765625 1.09375q-0.828125 0.3125 -1.796875 0.3125q-1.59375 0 -2.453125 -0.78125q-0.859375 -0.78125 -0.859375 -1.984375q0 -0.71875 0.328125 -1.296875q0.328125 -0.59375 0.84375 -0.9375q0.53125 -0.359375 1.1875 -0.546875q0.46875 -0.125 1.453125 -0.25q1.984375 -0.234375 2.921875 -0.5625q0.015625 -0.34375 0.015625 -0.421875q0 -1.0 -0.46875 -1.421875q-0.625 -0.546875 -1.875 -0.546875q-1.15625 0 -1.703125 0.40625q-0.546875 0.40625 -0.8125 1.421875l-1.609375 -0.21875q0.21875 -1.015625 0.71875 -1.640625q0.5 -0.640625 1.453125 -0.984375q0.953125 -0.34375 2.1875 -0.34375q1.25 0 2.015625 0.296875q0.78125 0.28125 1.140625 0.734375q0.375 0.4375 0.515625 1.109375q0.078125 0.421875 0.078125 1.515625l0 2.1875q0 2.28125 0.109375 2.890625q0.109375 0.59375 0.40625 1.15625l-1.703125 0q-0.265625 -0.515625 -0.328125 -1.1875zm-0.140625 -3.671875q-0.890625 0.375 -2.671875 0.625q-1.015625 0.140625 -1.4375 0.328125q-0.421875 0.1875 -0.65625 0.53125q-0.21875 0.34375 -0.21875 0.78125q0 0.65625 0.5 1.09375q0.5 0.4375 1.453125 0.4375q0.9375 0 1.671875 -0.40625q0.75 -0.421875 1.09375 -1.140625q0.265625 -0.5625 0.265625 -1.640625l0 -0.609375zm4.2038574 4.859375l0 -9.671875l1.46875 0l0 1.375q1.0625 -1.59375 3.078125 -1.59375q0.875 0 1.609375 0.3125q0.734375 0.3125 1.09375 0.828125q0.375 0.5 0.515625 1.203125q0.09375 0.453125 0.09375 1.59375l0 5.953125l-1.640625 0l0 -5.890625q0 -1.0 -0.203125 -1.484375q-0.1875 -0.5 -0.671875 -0.796875q-0.484375 -0.296875 -1.140625 -0.296875q-1.046875 0 -1.8125 0.671875q-0.75 0.65625 -0.75 2.515625l0 5.28125l-1.640625 0zm16.641235 0l0 -1.21875q-0.90625 1.4375 -2.703125 1.4375q-1.15625 0 -2.125 -0.640625q-0.96875 -0.640625 -1.5 -1.78125q-0.53125 -1.140625 -0.53125 -2.625q0 -1.453125 0.484375 -2.625q0.484375 -1.1875 1.4375 -1.8125q0.96875 -0.625 2.171875 -0.625q0.875 0 1.546875 0.375q0.6875 0.359375 1.109375 0.953125l0 -4.796875l1.640625 0l0 13.359375l-1.53125 0zm-5.171875 -4.828125q0 1.859375 0.78125 2.78125q0.78125 0.921875 1.84375 0.921875q1.078125 0 1.828125 -0.875q0.75 -0.890625 0.75 -2.6875q0 -1.984375 -0.765625 -2.90625q-0.765625 -0.9375 -1.890625 -0.9375q-1.078125 0 -1.8125 0.890625q-0.734375 0.890625 -0.734375 2.8125zm9.235107 4.828125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm10.816772 -3.109375l1.6875 0.203125q-0.40625 1.484375 -1.484375 2.3125q-1.078125 0.8125 -2.765625 0.8125q-2.125 0 -3.375 -1.296875q-1.234375 -1.3125 -1.234375 -3.671875q0 -2.453125 1.25 -3.796875q1.265625 -1.34375 3.265625 -1.34375q1.9375 0 3.15625 1.328125q1.234375 1.3125 1.234375 3.703125q0 0.15625 0 0.4375l-7.21875 0q0.09375 1.59375 0.90625 2.453125q0.8125 0.84375 2.015625 0.84375q0.90625 0 1.546875 -0.46875q0.640625 -0.484375 1.015625 -1.515625zm-5.390625 -2.65625l5.40625 0q-0.109375 -1.21875 -0.625 -1.828125q-0.78125 -0.953125 -2.03125 -0.953125q-1.125 0 -1.90625 0.765625q-0.765625 0.75 -0.84375 2.015625zm9.125732 5.765625l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0z" fill-rule="nonzero"/><path fill="#cfe2f3" d="m1018.063 193.57217l125.07092 0l0 144.37796l-125.07092 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m1018.063 193.57217l125.07092 0l0 144.37796l-125.07092 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1018.063 193.57217l129.1654 0l0 61.35434l-129.1654 0z" fill-rule="evenodd"/><path fill="#000000" d="m1028.1099 217.93217l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm11.015625 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.5703125 5.640625l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm12.4375 -5.546875l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.5546875 0l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm7.0546875 -1.40625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm5.671875 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0zm9.5234375 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm9.0078125 1.125l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm8.265625 0.375l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m1143.1339 224.5958l48.188965 1.0078735" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m1143.1339 224.5958l42.190186 0.8824158" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m1185.2896 227.12958l4.5716553 -1.5564728l-4.5025635 -1.7462616z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1188.2677 268.99213l-45.13379 -0.6929016" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m1188.2677 268.99213l-39.13452 -0.60079956" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m1149.1584 266.73978l-4.562866 1.5818787l4.512207 1.7211914z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1149.7979 224.5958l66.64575 0l0 25.826782l-66.64575 0z" fill-rule="evenodd"/><path fill="#000000" d="m1159.6572 246.3958l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.188477 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.3031006 4.703125l1.140625 0.15625q0.078125 0.53125 0.40625 0.78125q0.4375 0.3125 1.1875 0.3125q0.8125 0 1.25 -0.328125q0.453125 -0.3125 0.609375 -0.90625q0.09375 -0.359375 0.078125 -1.5q-0.765625 0.90625 -1.90625 0.90625q-1.4375 0 -2.21875 -1.03125q-0.78125 -1.03125 -0.78125 -2.46875q0 -0.984375 0.359375 -1.8125q0.359375 -0.84375 1.03125 -1.296875q0.6875 -0.453125 1.609375 -0.453125q1.21875 0 2.015625 0.984375l0 -0.828125l1.078125 0l0 5.96875q0 1.609375 -0.328125 2.28125q-0.328125 0.6875 -1.046875 1.078125q-0.703125 0.390625 -1.75 0.390625q-1.234375 0 -2.0 -0.5625q-0.75 -0.5625 -0.734375 -1.671875zm0.984375 -4.15625q0 1.359375 0.53125 1.984375q0.546875 0.625 1.359375 0.625q0.796875 0 1.34375 -0.625q0.546875 -0.625 0.546875 -1.953125q0 -1.265625 -0.5625 -1.90625q-0.5625 -0.640625 -1.359375 -0.640625q-0.765625 0 -1.3125 0.640625q-0.546875 0.625 -0.546875 1.875zm12.474976 2.453125l0 1.125l-6.296875 0q-0.015625 -0.421875 0.140625 -0.8125q0.234375 -0.640625 0.765625 -1.265625q0.53125 -0.625 1.53125 -1.453125q1.5625 -1.265625 2.109375 -2.015625q0.546875 -0.75 0.546875 -1.40625q0 -0.703125 -0.5 -1.171875q-0.5 -0.484375 -1.296875 -0.484375q-0.859375 0 -1.375 0.515625q-0.5 0.5 -0.5 1.390625l-1.203125 -0.109375q0.125 -1.359375 0.921875 -2.0625q0.8125 -0.703125 2.171875 -0.703125q1.375 0 2.171875 0.765625q0.8125 0.75 0.8125 1.875q0 0.578125 -0.234375 1.140625q-0.234375 0.546875 -0.78125 1.15625q-0.546875 0.609375 -1.8125 1.671875q-1.046875 0.890625 -1.359375 1.21875q-0.296875 0.3125 -0.484375 0.625l4.671875 0zm1.5843506 1.125l0 -9.546875l1.171875 0l0 3.421875q0.828125 -0.9375 2.078125 -0.9375q0.765625 0 1.328125 0.296875q0.5625 0.296875 0.8125 0.84375q0.25 0.53125 0.25 1.546875l0 4.375l-1.171875 0l0 -4.375q0 -0.890625 -0.390625 -1.28125q-0.375 -0.40625 -1.078125 -0.40625q-0.515625 0 -0.984375 0.28125q-0.453125 0.265625 -0.65625 0.734375q-0.1875 0.453125 -0.1875 1.265625l0 3.78125l-1.171875 0zm8.693726 0l-2.125 -6.90625l1.21875 0l1.09375 3.984375l0.421875 1.484375q0.015625 -0.109375 0.359375 -1.421875l1.09375 -4.046875l1.203125 0l1.03125 4.0l0.34375 1.328125l0.40625 -1.34375l1.171875 -3.984375l1.140625 0l-2.15625 6.90625l-1.21875 0l-1.09375 -4.140625l-0.265625 -1.171875l-1.40625 5.3125l-1.21875 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m1149.7979 264.0315l66.64575 0l0 25.826782l-66.64575 0z" fill-rule="evenodd"/><path fill="#000000" d="m1159.6729 285.83148l0 -9.546875l1.171875 0l0 3.421875q0.828125 -0.9375 2.078125 -0.9375q0.765625 0 1.328125 0.296875q0.5625 0.296875 0.8125 0.84375q0.25 0.53125 0.25 1.546875l0 4.375l-1.171875 0l0 -4.375q0 -0.890625 -0.390625 -1.28125q-0.375 -0.40625 -1.078125 -0.40625q-0.515625 0 -0.984375 0.28125q-0.453125 0.265625 -0.65625 0.734375q-0.1875 0.453125 -0.1875 1.265625l0 3.78125l-1.171875 0zm8.693726 0l-2.125 -6.90625l1.21875 0l1.09375 3.984375l0.421875 1.484375q0.015625 -0.109375 0.359375 -1.421875l1.09375 -4.046875l1.203125 0l1.03125 4.0l0.34375 1.328125l0.40625 -1.34375l1.171875 -3.984375l1.140625 0l-2.15625 6.90625l-1.21875 0l-1.09375 -4.140625l-0.265625 -1.171875l-1.40625 5.3125l-1.21875 0zm14.172119 -1.125l0 1.125l-6.296875 0q-0.015625 -0.421875 0.140625 -0.8125q0.234375 -0.640625 0.765625 -1.265625q0.53125 -0.625 1.53125 -1.453125q1.5625 -1.265625 2.109375 -2.015625q0.546875 -0.75 0.546875 -1.40625q0 -0.703125 -0.5 -1.171875q-0.5 -0.484375 -1.296875 -0.484375q-0.859375 0 -1.375 0.515625q-0.5 0.5 -0.5 1.390625l-1.203125 -0.109375q0.125 -1.359375 0.921875 -2.0625q0.8125 -0.703125 2.171875 -0.703125q1.375 0 2.171875 0.765625q0.8125 0.75 0.8125 1.875q0 0.578125 -0.234375 1.140625q-0.234375 0.546875 -0.78125 1.15625q-0.546875 0.609375 -1.8125 1.671875q-1.046875 0.890625 -1.359375 1.21875q-0.296875 0.3125 -0.484375 0.625l4.671875 0zm1.5687256 1.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.1883545 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.3031006 4.703125l1.140625 0.15625q0.078125 0.53125 0.40625 0.78125q0.4375 0.3125 1.1875 0.3125q0.8125 0 1.25 -0.328125q0.453125 -0.3125 0.609375 -0.90625q0.09375 -0.359375 0.078125 -1.5q-0.765625 0.90625 -1.90625 0.90625q-1.4375 0 -2.21875 -1.03125q-0.78125 -1.03125 -0.78125 -2.46875q0 -0.984375 0.359375 -1.8125q0.359375 -0.84375 1.03125 -1.296875q0.6875 -0.453125 1.609375 -0.453125q1.21875 0 2.015625 0.984375l0 -0.828125l1.078125 0l0 5.96875q0 1.609375 -0.328125 2.28125q-0.328125 0.6875 -1.046875 1.078125q-0.703125 0.390625 -1.75 0.390625q-1.234375 0 -2.0 -0.5625q-0.75 -0.5625 -0.734375 -1.671875zm0.984375 -4.15625q0 1.359375 0.53125 1.984375q0.546875 0.625 1.359375 0.625q0.796875 0 1.34375 -0.625q0.546875 -0.625 0.546875 -1.953125q0 -1.265625 -0.5625 -1.90625q-0.5625 -0.640625 -1.359375 -0.640625q-0.765625 0 -1.3125 0.640625q-0.546875 0.625 -0.546875 1.875z" fill-rule="nonzero"/><path fill="#ffffff" d="m882.0656 230.97113l19.40155 -19.40158l0 9.70079l71.08667 0l0 -9.70079l19.40155 19.40158l-19.40155 19.401566l0 -9.700775l-71.08667 0l0 9.700775z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m882.0656 230.97113l19.40155 -19.40158l0 9.70079l71.08667 0l0 -9.70079l19.40155 19.40158l-19.40155 19.401566l0 -9.700775l-71.08667 0l0 9.700775z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m919.23096 232.53543l72.72443 0l0 40.22049l-72.72443 0z" fill-rule="evenodd"/><path fill="#000000" d="m931.6841 254.33543l0 -8.421875l-3.140625 0l0 -1.125l7.5625 0l0 1.125l-3.15625 0l0 8.421875l-1.265625 0zm5.6569824 0l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0zm13.724976 -9.546875l1.265625 0l0 5.515625q0 1.4375 -0.328125 2.296875q-0.3125 0.84375 -1.171875 1.375q-0.84375 0.515625 -2.21875 0.515625q-1.34375 0 -2.203125 -0.453125q-0.84375 -0.46875 -1.21875 -1.34375q-0.359375 -0.875 -0.359375 -2.390625l0 -5.515625l1.265625 0l0 5.515625q0 1.234375 0.21875 1.828125q0.234375 0.59375 0.796875 0.921875q0.5625 0.3125 1.390625 0.3125q1.390625 0 1.96875 -0.625q0.59375 -0.640625 0.59375 -2.4375l0 -5.515625zm3.312683 9.546875l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0z" fill-rule="nonzero"/><path fill="#000000" d="m933.59033 270.33542l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm11.365601 1.234375l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm8.443726 4.125l-2.625 -6.90625l1.234375 0l1.484375 4.140625q0.234375 0.65625 0.4375 1.390625q0.15625 -0.546875 0.4375 -1.3125l1.53125 -4.21875l1.21875 0l-2.625 6.90625l-1.09375 0zm4.7578125 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm7.4611206 -2.53125l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm6.8828125 0.3125l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m881.3924 309.43176l109.88977 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m881.3924 309.43176l103.88977 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m985.28217 311.0835l4.538086 -1.6517334l-4.538086 -1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m881.874 365.0525l109.88977 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m881.874 365.0525l103.88977 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m985.7638 366.70422l4.538086 -1.6517334l-4.538086 -1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m991.9554 426.67978l-109.88977 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m991.9554 426.67978l-103.88977 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m888.0656 425.02805l-4.538086 1.6517334l4.538086 1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m911.2113 302.7979l66.64563 0l0 25.826752l-66.64563 0z" fill-rule="evenodd"/><path fill="#000000" d="m925.6019 322.06665l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm2.1328125 2.53125l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm2.5391846 -3.453125q0 -1.921875 1.078125 -2.84375q0.890625 -0.765625 2.171875 -0.765625q1.421875 0 2.328125 0.9375q0.90625 0.921875 0.90625 2.578125q0 1.328125 -0.40625 2.09375q-0.390625 0.765625 -1.15625 1.1875q-0.765625 0.421875 -1.671875 0.421875q-1.453125 0 -2.359375 -0.921875q-0.890625 -0.9375 -0.890625 -2.6875zm1.203125 0q0 1.328125 0.578125 1.984375q0.59375 0.65625 1.46875 0.65625q0.875 0 1.453125 -0.65625q0.578125 -0.671875 0.578125 -2.03125q0 -1.28125 -0.59375 -1.9375q-0.578125 -0.65625 -1.4375 -0.65625q-0.875 0 -1.46875 0.65625q-0.578125 0.65625 -0.578125 1.984375zm11.162476 0.921875l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm2.1640625 2.53125l0 -9.546875l1.171875 0l0 5.453125l2.765625 -2.8125l1.515625 0l-2.640625 2.5625l2.90625 4.34375l-1.4375 0l-2.28125 -3.53125l-0.828125 0.796875l0 2.734375l-1.171875 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m911.2126 362.33597l89.543335 0l0 25.826752l-89.543335 0z" fill-rule="evenodd"/><path fill="#000000" d="m925.57196 384.13596l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm11.365601 1.234375l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm8.443726 4.125l-2.625 -6.90625l1.234375 0l1.484375 4.140625q0.234375 0.65625 0.4375 1.390625q0.15625 -0.546875 0.4375 -1.3125l1.53125 -4.21875l1.21875 0l-2.625 6.90625l-1.09375 0zm4.7421875 0l0 -6.90625l1.046875 0l0 0.96875q0.328125 -0.515625 0.859375 -0.8125q0.546875 -0.3125 1.234375 -0.3125q0.78125 0 1.265625 0.3125q0.484375 0.3125 0.6875 0.890625q0.828125 -1.203125 2.140625 -1.203125q1.03125 0 1.578125 0.578125q0.5625 0.5625 0.5625 1.734375l0 4.75l-1.171875 0l0 -4.359375q0 -0.703125 -0.125 -1.0q-0.109375 -0.3125 -0.40625 -0.5q-0.296875 -0.1875 -0.703125 -0.1875q-0.71875 0 -1.203125 0.484375q-0.484375 0.484375 -0.484375 1.546875l0 4.015625l-1.171875 0l0 -4.484375q0 -0.78125 -0.296875 -1.171875q-0.28125 -0.390625 -0.921875 -0.390625q-0.5 0 -0.921875 0.265625q-0.421875 0.25 -0.609375 0.75q-0.1875 0.5 -0.1875 1.453125l0 3.578125l-1.171875 0zm10.664917 -3.453125q0 -1.921875 1.078125 -2.84375q0.890625 -0.765625 2.171875 -0.765625q1.421875 0 2.328125 0.9375q0.90625 0.921875 0.90625 2.578125q0 1.328125 -0.40625 2.09375q-0.390625 0.765625 -1.15625 1.1875q-0.765625 0.421875 -1.671875 0.421875q-1.453125 0 -2.359375 -0.921875q-0.890625 -0.9375 -0.890625 -2.6875zm1.203125 0q0 1.328125 0.578125 1.984375q0.59375 0.65625 1.46875 0.65625q0.875 0 1.453125 -0.65625q0.578125 -0.671875 0.578125 -2.03125q0 -1.28125 -0.59375 -1.9375q-0.578125 -0.65625 -1.4375 -0.65625q-0.875 0 -1.46875 0.65625q-0.578125 0.65625 -0.578125 1.984375zm11.131226 3.453125l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm11.365601 1.234375l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m1000.7559 418.33597l-89.543335 0l0 25.826752l89.543335 0z" fill-rule="evenodd"/><path fill="#000000" d="m921.1032 431.94846l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm2.9454956 0l0 -6.90625l1.0625 0l0 0.984375q0.75 -1.140625 2.1875 -1.140625q0.625 0 1.15625 0.21875q0.53125 0.21875 0.78125 0.59375q0.265625 0.359375 0.375 0.859375q0.0625 0.328125 0.0625 1.140625l0 4.25l-1.171875 0l0 -4.203125q0 -0.71875 -0.140625 -1.0625q-0.140625 -0.359375 -0.484375 -0.5625q-0.34375 -0.21875 -0.8125 -0.21875q-0.75 0 -1.296875 0.46875q-0.546875 0.46875 -0.546875 1.796875l0 3.78125l-1.171875 0zm9.974976 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm5.874817 -1.171875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.5062256 4.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm4.4384155 0l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm8.9852295 0l0 -1.015625q-0.8125 1.171875 -2.1875 1.171875q-0.609375 0 -1.140625 -0.234375q-0.53125 -0.234375 -0.796875 -0.578125q-0.25 -0.359375 -0.359375 -0.875q-0.0625 -0.34375 -0.0625 -1.09375l0 -4.28125l1.171875 0l0 3.828125q0 0.921875 0.0625 1.234375q0.109375 0.46875 0.46875 0.734375q0.359375 0.25 0.890625 0.25q0.515625 0 0.984375 -0.265625q0.46875 -0.265625 0.65625 -0.734375q0.1875 -0.46875 0.1875 -1.34375l0 -3.703125l1.171875 0l0 6.90625l-1.046875 0zm2.8812256 2.65625l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125zm8.912476 2.375l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm0.6717529 -1.015625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625z" fill-rule="nonzero"/><path fill="#fce5cd" d="m1289.6509 386.0551l105.60632 0l0 40.22049l-105.60632 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="8.0,3.0,1.0,3.0" d="m1289.6509 386.0551l105.60632 0l0 40.22049l-105.60632 0z" fill-rule="evenodd"/><path fill="#000000" d="m1307.0833 399.79224l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm6.666626 2.265625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm12.796875 -0.515625l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm1.1875 5.6875l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.322998 -2.90625l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm10.099487 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm12.135376 1.75l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm7.578125 0.328125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.182373 -4.484375l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm5.3656006 0l-2.890625 -7.59375l1.359375 0l1.625 4.546875q0.265625 0.734375 0.5 1.53125q0.15625 -0.609375 0.46875 -1.453125l1.6875 -4.625l1.328125 0l-2.875 7.59375l-1.203125 0zm10.421875 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0z" fill-rule="nonzero"/><path fill="#000000" d="m1334.4957 423.1516l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686035 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#ffffff" d="m1207.7643 408.00787l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m1207.7643 408.00787l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1216.4436 420.75592l94.20471 0l0 40.22046l-94.20471 0z" fill-rule="evenodd"/><path fill="#000000" d="m1231.053 440.33716l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.0531006 2.0625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625zm11.6484375 -0.46875l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm1.0703125 5.1875l0 -0.859375l7.765625 0l0 0.859375l-7.765625 0zm11.053101 -3.703125l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm0.35925293 1.046875l2.53125 -3.59375l-2.34375 -3.3125l1.46875 0l1.0625 1.609375q0.296875 0.46875 0.484375 0.78125q0.28125 -0.4375 0.515625 -0.765625l1.171875 -1.625l1.40625 0l-2.390625 3.25l2.5625 3.65625l-1.4375 0l-1.421875 -2.140625l-0.375 -0.59375l-1.8125 2.734375l-1.421875 0zm6.5703125 0.15625l2.765625 -9.859375l0.9375 0l-2.765625 9.859375l-0.9375 0zm4.562256 -0.15625l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm3.6728516 0l2.53125 -3.59375l-2.34375 -3.3125l1.46875 0l1.0625 1.609375q0.296875 0.46875 0.484375 0.78125q0.28125 -0.4375 0.515625 -0.765625l1.171875 -1.625l1.40625 0l-2.390625 3.25l2.5625 3.65625l-1.4375 0l-1.421875 -2.140625l-0.375 -0.59375l-1.8125 2.734375l-1.421875 0z" fill-rule="nonzero"/><path fill="#d9ead3" d="m382.89502 511.7789l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5717773 -2.8955078 6.467346 -6.467346 6.467346l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955688 -6.4673157 -6.467346z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m382.89502 511.7789l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19131 0c1.715271 0 3.3602295 0.68136597 4.57312 1.8942261c1.2128296 1.2128601 1.8942261 2.8578491 1.8942261 4.5730896l0 25.8685c0 3.5717773 -2.8955078 6.467346 -6.467346 6.467346l-187.19131 0l0 0c-3.5718079 0 -6.4673157 -2.8955688 -6.4673157 -6.467346z" fill-rule="evenodd"/><path fill="#000000" d="m403.1377 530.53455q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.2109375 -3.1875l0 -11.453125l1.40625 0l0 4.109375q0.984375 -1.140625 2.484375 -1.140625q0.921875 0 1.59375 0.359375q0.6875 0.359375 0.96875 1.0q0.296875 0.640625 0.296875 1.859375l0 5.265625l-1.40625 0l0 -5.265625q0 -1.046875 -0.453125 -1.53125q-0.453125 -0.484375 -1.296875 -0.484375q-0.625 0 -1.171875 0.328125q-0.546875 0.328125 -0.78125 0.890625q-0.234375 0.546875 -0.234375 1.515625l0 4.546875l-1.40625 0zm14.3046875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015625 4.171875l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.2734375 0l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm7.9296875 4.140625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -4.21875q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.3359375 4.859375l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm13.6640625 1.625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8359375 4.953125l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm15.6171875 -6.234375l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm2.921875 3.046875l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0zm3.8515625 0.6875l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625z" fill-rule="nonzero"/><path fill="#ffffff" d="m1207.7643 308.1181l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m1207.7643 308.1181l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1216.1392 322.03674l109.88977 0l0 40.22049l-109.88977 0z" fill-rule="evenodd"/><path fill="#000000" d="m1230.5298 342.97736q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm2.9749756 3.46875l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm7.7110596 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.5062256 4.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm7.0164795 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm0.06237793 3.703125l0 -0.859375l7.765625 0l0 0.859375l-7.765625 0zm11.053101 -3.703125l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm0.35925293 1.046875l2.53125 -3.59375l-2.34375 -3.3125l1.46875 0l1.0625 1.609375q0.296875 0.46875 0.484375 0.78125q0.28125 -0.4375 0.515625 -0.765625l1.171875 -1.625l1.40625 0l-2.390625 3.25l2.5625 3.65625l-1.4375 0l-1.421875 -2.140625l-0.375 -0.59375l-1.8125 2.734375l-1.421875 0zm6.5703125 0.15625l2.765625 -9.859375l0.9375 0l-2.765625 9.859375l-0.9375 0zm4.562378 -0.15625l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm3.6727295 0l2.53125 -3.59375l-2.34375 -3.3125l1.46875 0l1.0625 1.609375q0.296875 0.46875 0.484375 0.78125q0.28125 -0.4375 0.515625 -0.765625l1.171875 -1.625l1.40625 0l-2.390625 3.25l2.5625 3.65625l-1.4375 0l-1.421875 -2.140625l-0.375 -0.59375l-1.8125 2.734375l-1.421875 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m1289.6509 288.00787l105.60632 0l0 40.22046l-105.60632 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="8.0,3.0,1.0,3.0" d="m1289.6509 288.00787l105.60632 0l0 40.22046l-105.60632 0z" fill-rule="evenodd"/><path fill="#000000" d="m1307.6383 303.26062q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.276123 3.8125l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.4904785 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.70874 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm0.072021484 4.0625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm8.822998 -5.171875l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm13.046875 -0.1875l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.182373 4.53125l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm13.072998 0l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125zm12.494751 1.34375l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0z" fill-rule="nonzero"/><path fill="#000000" d="m1334.4957 325.10437l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686035 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#f4cccc" d="m382.89633 352.31766l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19135 0c1.71521 0 3.3602295 0.68136597 4.573059 1.8942261c1.2128906 1.2128601 1.8942871 2.8578491 1.8942871 4.5730896l0 25.86853c0 3.5717773 -2.8955688 6.4673157 -6.467346 6.4673157l-187.19135 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m382.89633 352.31766l0 0c0 -3.5718079 2.8955078 -6.4673157 6.4673157 -6.4673157l187.19135 0c1.71521 0 3.3602295 0.68136597 4.573059 1.8942261c1.2128906 1.2128601 1.8942871 2.8578491 1.8942871 4.5730896l0 25.86853c0 3.5717773 -2.8955688 6.4673157 -6.467346 6.4673157l-187.19135 0l0 0c-3.5718079 0 -6.4673157 -2.8955383 -6.4673157 -6.4673157z" fill-rule="evenodd"/><path fill="#000000" d="m430.27963 371.0733q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.5703125 4.171875l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm8.40625 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm0.0703125 4.453125l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm10.2109375 -3.1875l0 -11.453125l1.40625 0l0 4.109375q0.984375 -1.140625 2.484375 -1.140625q0.921875 0 1.59375 0.359375q0.6875 0.359375 0.96875 1.0q0.296875 0.640625 0.296875 1.859375l0 5.265625l-1.40625 0l0 -5.265625q0 -1.046875 -0.453125 -1.53125q-0.453125 -0.484375 -1.296875 -0.484375q-0.625 0 -1.171875 0.328125q-0.546875 0.328125 -0.78125 0.890625q-0.234375 0.546875 -0.234375 1.515625l0 4.546875l-1.40625 0zm14.3046875 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm3.6015625 4.171875l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm14.2734375 0l0 -1.046875q-0.78125 1.234375 -2.3125 1.234375q-1.0 0 -1.828125 -0.546875q-0.828125 -0.546875 -1.296875 -1.53125q-0.453125 -0.984375 -0.453125 -2.25q0 -1.25 0.40625 -2.25q0.421875 -1.015625 1.25 -1.546875q0.828125 -0.546875 1.859375 -0.546875q0.75 0 1.328125 0.3125q0.59375 0.3125 0.953125 0.828125l0 -4.109375l1.40625 0l0 11.453125l-1.3125 0zm-4.4375 -4.140625q0 1.59375 0.671875 2.390625q0.671875 0.78125 1.578125 0.78125q0.921875 0 1.5625 -0.75q0.65625 -0.765625 0.65625 -2.3125q0 -1.703125 -0.65625 -2.5q-0.65625 -0.796875 -1.625 -0.796875q-0.9375 0 -1.5625 0.765625q-0.625 0.765625 -0.625 2.421875zm7.9296875 4.140625l0 -11.453125l1.40625 0l0 11.453125l-1.40625 0zm9.2578125 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.820282 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm4.03125 3.1875l0 -1.015625l9.328125 0l0 1.015625l-9.328125 0zm12.5078125 -3.1875l-3.15625 -8.296875l1.484375 0l1.78125 4.96875q0.296875 0.796875 0.53125 1.671875q0.1875 -0.65625 0.53125 -1.578125l1.84375 -5.0625l1.4375 0l-3.140625 8.296875l-1.3125 0zm5.703125 -9.84375l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.8828125 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m687.2992 465.54987l194.74017 0l0 25.826782l-194.74017 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m687.2992 465.54987l194.74017 0l0 25.826782l-194.74017 0z" fill-rule="evenodd"/><path fill="#000000" d="m740.07434 482.60574q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.276123 3.8125l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.4904785 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.7088013 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm0.07196045 4.0625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 -2.90625l0 -10.484375l1.28125 0l0 3.75q0.90625 -1.03125 2.28125 -1.03125q0.84375 0 1.46875 0.328125q0.625 0.328125 0.890625 0.921875q0.265625 0.578125 0.265625 1.703125l0 4.8125l-1.28125 0l0 -4.8125q0 -0.96875 -0.421875 -1.40625q-0.421875 -0.4375 -1.1875 -0.4375q-0.578125 0 -1.078125 0.296875q-0.5 0.296875 -0.71875 0.8125q-0.21875 0.5 -0.21875 1.390625l0 4.15625l-1.28125 0zm13.104187 -0.9375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm3.307373 3.8125l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm13.072998 0l0 -0.953125q-0.71875 1.125 -2.125 1.125q-0.90625 0 -1.671875 -0.5q-0.75 -0.5 -1.171875 -1.390625q-0.421875 -0.90625 -0.421875 -2.078125q0 -1.140625 0.375 -2.0625q0.390625 -0.921875 1.140625 -1.40625q0.765625 -0.5 1.703125 -0.5q0.6875 0 1.21875 0.296875q0.53125 0.28125 0.875 0.734375l0 -3.75l1.28125 0l0 10.484375l-1.203125 0zm-4.0625 -3.796875q0 1.46875 0.609375 2.1875q0.625 0.71875 1.453125 0.71875q0.84375 0 1.4375 -0.6875q0.59375 -0.6875 0.59375 -2.109375q0 -1.5625 -0.609375 -2.28125q-0.59375 -0.734375 -1.484375 -0.734375q-0.84375 0 -1.421875 0.703125q-0.578125 0.703125 -0.578125 2.203125zm7.260498 3.796875l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.4904785 -2.453125l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm3.7088013 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338562 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm3.5686646 0l0 -6.59375l-1.140625 0l0 -1.0l1.140625 0l0 -0.8125q0 -0.765625 0.125 -1.140625q0.1875 -0.5 0.65625 -0.8125q0.46875 -0.3125 1.3125 -0.3125q0.546875 0 1.203125 0.125l-0.1875 1.125q-0.40625 -0.0625 -0.765625 -0.0625q-0.578125 0 -0.828125 0.25q-0.234375 0.25 -0.234375 0.9375l0 0.703125l1.46875 0l0 1.0l-1.46875 0l0 6.59375l-1.28125 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m991.4803 478.46457l-109.88971 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m991.4803 478.46457l-103.88971 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m887.5906 476.81284l-4.538147 1.6517334l4.538147 1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m1000.3648 469.90894l-89.543274 0l0 40.22046l89.543274 0z" fill-rule="evenodd"/><path fill="#000000" d="m920.6809 491.70892l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm2.9766846 2.65625l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125zm6.1312256 4.0l1.140625 0.15625q0.078125 0.53125 0.40625 0.78125q0.4375 0.3125 1.1875 0.3125q0.8125 0 1.25 -0.328125q0.453125 -0.3125 0.609375 -0.90625q0.09375 -0.359375 0.078125 -1.5q-0.765625 0.90625 -1.90625 0.90625q-1.4375 0 -2.21875 -1.03125q-0.78125 -1.03125 -0.78125 -2.46875q0 -0.984375 0.359375 -1.8125q0.359375 -0.84375 1.03125 -1.296875q0.6875 -0.453125 1.609375 -0.453125q1.21875 0 2.015625 0.984375l0 -0.828125l1.078125 0l0 5.96875q0 1.609375 -0.328125 2.28125q-0.328125 0.6875 -1.046875 1.078125q-0.703125 0.390625 -1.75 0.390625q-1.234375 0 -2.0 -0.5625q-0.75 -0.5625 -0.734375 -1.671875zm0.984375 -4.15625q0 1.359375 0.53125 1.984375q0.546875 0.625 1.359375 0.625q0.796875 0 1.34375 -0.625q0.546875 -0.625 0.546875 -1.953125q0 -1.265625 -0.5625 -1.90625q-0.5625 -0.640625 -1.359375 -0.640625q-0.765625 0 -1.3125 0.640625q-0.546875 0.625 -0.546875 1.875zm14.8654785 2.71875q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm2.9906006 3.46875l0 -6.90625l1.0625 0l0 0.984375q0.75 -1.140625 2.1875 -1.140625q0.625 0 1.15625 0.21875q0.53125 0.21875 0.78125 0.59375q0.265625 0.359375 0.375 0.859375q0.0625 0.328125 0.0625 1.140625l0 4.25l-1.171875 0l0 -4.203125q0 -0.71875 -0.140625 -1.0625q-0.140625 -0.359375 -0.484375 -0.5625q-0.34375 -0.21875 -0.8125 -0.21875q-0.75 0 -1.296875 0.46875q-0.546875 0.46875 -0.546875 1.796875l0 3.78125l-1.171875 0zm11.896851 0l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0z" fill-rule="nonzero"/><path fill="#000000" d="m925.21216 505.17767l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm2.1328125 2.53125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm8.9696045 -0.859375q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm2.5218506 1.40625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625zm7.1328125 2.0625l0 -9.546875l1.171875 0l0 3.421875q0.828125 -0.9375 2.078125 -0.9375q0.765625 0 1.328125 0.296875q0.5625 0.296875 0.8125 0.84375q0.25 0.53125 0.25 1.546875l0 4.375l-1.171875 0l0 -4.375q0 -0.890625 -0.390625 -1.28125q-0.375 -0.40625 -1.078125 -0.40625q-0.515625 0 -0.984375 0.28125q-0.453125 0.265625 -0.65625 0.734375q-0.1875 0.453125 -0.1875 1.265625l0 3.78125l-1.171875 0zm11.896851 0l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm11.162476 3.453125l0 -1.015625q-0.8125 1.171875 -2.1875 1.171875q-0.609375 0 -1.140625 -0.234375q-0.53125 -0.234375 -0.796875 -0.578125q-0.25 -0.359375 -0.359375 -0.875q-0.0625 -0.34375 -0.0625 -1.09375l0 -4.28125l1.171875 0l0 3.828125q0 0.921875 0.0625 1.234375q0.109375 0.46875 0.46875 0.734375q0.359375 0.25 0.890625 0.25q0.515625 0 0.984375 -0.265625q0.46875 -0.265625 0.65625 -0.734375q0.1875 -0.46875 0.1875 -1.34375l0 -3.703125l1.171875 0l0 6.90625l-1.046875 0zm2.8812256 0l0 -6.90625l1.046875 0l0 0.96875q0.328125 -0.515625 0.859375 -0.8125q0.546875 -0.3125 1.234375 -0.3125q0.78125 0 1.265625 0.3125q0.484375 0.3125 0.6875 0.890625q0.828125 -1.203125 2.140625 -1.203125q1.03125 0 1.578125 0.578125q0.5625 0.5625 0.5625 1.734375l0 4.75l-1.171875 0l0 -4.359375q0 -0.703125 -0.125 -1.0q-0.109375 -0.3125 -0.40625 -0.5q-0.296875 -0.1875 -0.703125 -0.1875q-0.71875 0 -1.203125 0.484375q-0.484375 0.484375 -0.484375 1.546875l0 4.015625l-1.171875 0l0 -4.484375q0 -0.78125 -0.296875 -1.171875q-0.28125 -0.390625 -0.921875 -0.390625q-0.5 0 -0.921875 0.265625q-0.421875 0.25 -0.609375 0.75q-0.1875 0.5 -0.1875 1.453125l0 3.578125l-1.171875 0zm11.102417 2.65625l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125z" fill-rule="nonzero"/></g></svg>
\ No newline at end of file
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.core
new file mode 100644
index 0000000..bc4e036
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.core
@@ -0,0 +1,42 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:alert_handler_env:0.1"
+description: "ALERT_HANDLER DV UVM environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:cip_lib
+ - lowrisc:ip:alert_handler_component # import alert_pkg
+ - lowrisc:prim:mubi # import prim_mubi_pkg
+ files:
+ - alert_handler_env_pkg.sv
+ - alert_handler_if.sv
+ - alert_handler_env_cfg.sv: {is_include_file: true}
+ - alert_handler_env_cov.sv: {is_include_file: true}
+ - alert_handler_virtual_sequencer.sv: {is_include_file: true}
+ - alert_handler_scoreboard.sv: {is_include_file: true}
+ - alert_handler_env.sv: {is_include_file: true}
+ - seq_lib/alert_handler_vseq_list.sv: {is_include_file: true}
+ - seq_lib/alert_handler_base_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_common_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_smoke_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_random_alerts_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_random_classes_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_esc_intr_timeout_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_esc_alert_accum_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_sig_int_fail_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_entropy_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_ping_timeout_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_lpg_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_lpg_stub_clk_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_entropy_stress_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_stress_all_vseq.sv: {is_include_file: true}
+ - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.sv
new file mode 100644
index 0000000..1a3a5b5
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env.sv
@@ -0,0 +1,80 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_env extends cip_base_env #(
+ .CFG_T (alert_handler_env_cfg),
+ .COV_T (alert_handler_env_cov),
+ .VIRTUAL_SEQUENCER_T(alert_handler_virtual_sequencer),
+ .SCOREBOARD_T (alert_handler_scoreboard)
+ );
+ `uvm_component_utils(alert_handler_env)
+
+ `uvm_component_new
+
+ alert_esc_agent alert_host_agent[];
+ alert_esc_agent esc_device_agent[];
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+
+ // build alert agents
+ alert_host_agent = new[NUM_ALERTS];
+ virtual_sequencer.alert_host_seqr_h = new[NUM_ALERTS];
+ foreach (alert_host_agent[i]) begin
+ alert_host_agent[i] = alert_esc_agent::type_id::create(
+ $sformatf("alert_host_agent[%0d]", i), this);
+ uvm_config_db#(alert_esc_agent_cfg)::set(this,
+ $sformatf("alert_host_agent[%0d]", i), "cfg", cfg.alert_host_cfg[i]);
+ cfg.alert_host_cfg[i].en_cov = cfg.en_cov;
+ cfg.alert_host_cfg[i].clk_freq_mhz = int'(cfg.clk_freq_mhz);
+ end
+
+ // build escalator agents
+ esc_device_agent = new[NUM_ESCS];
+ virtual_sequencer.esc_device_seqr_h = new[NUM_ESCS];
+ foreach (esc_device_agent[i]) begin
+ esc_device_agent[i] = alert_esc_agent::type_id::create(
+ $sformatf("esc_device_agent[%0d]", i), this);
+ uvm_config_db#(alert_esc_agent_cfg)::set(this,
+ $sformatf("esc_device_agent[%0d]", i), "cfg", cfg.esc_device_cfg[i]);
+ cfg.esc_device_cfg[i].en_cov = cfg.en_cov;
+ end
+
+ // get vifs
+ if (!uvm_config_db#(crashdump_vif)::get(this, "", "crashdump_vif", cfg.crashdump_vif)) begin
+ `uvm_fatal(get_full_name(), "failed to get crashdump_vif from uvm_config_db")
+ end
+ if (!uvm_config_db#(alert_handler_vif)::get(this, "", "alert_handler_vif",
+ cfg.alert_handler_vif)) begin
+ `uvm_fatal(`gfn, "failed to get alert_handler_vif from uvm_config_db")
+ end
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ if (cfg.en_scb) begin
+ foreach (alert_host_agent[i]) begin
+ alert_host_agent[i].monitor.alert_esc_port.connect(
+ scoreboard.alert_fifo[i].analysis_export);
+ end
+ foreach (esc_device_agent[i]) begin
+ esc_device_agent[i].monitor.alert_esc_port.connect(
+ scoreboard.esc_fifo[i].analysis_export);
+ end
+ end
+ if (cfg.is_active) begin
+ foreach (alert_host_agent[i]) begin
+ if (cfg.alert_host_cfg[i].is_active) begin
+ virtual_sequencer.alert_host_seqr_h[i] = alert_host_agent[i].sequencer;
+ end
+ end
+ end
+ foreach (esc_device_agent[i]) begin
+ if (cfg.esc_device_cfg[i].is_active) begin
+ virtual_sequencer.esc_device_seqr_h[i] = esc_device_agent[i].sequencer;
+ end
+ end
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv
new file mode 100644
index 0000000..c55befa
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv
@@ -0,0 +1,59 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_block));
+
+ // ext component cfgs
+ esc_en_vif esc_en_vif;
+ crashdump_vif crashdump_vif;
+ alert_handler_vif alert_handler_vif;
+ rand alert_esc_agent_cfg alert_host_cfg[];
+ rand alert_esc_agent_cfg esc_device_cfg[];
+
+ `uvm_object_utils_begin(alert_handler_env_cfg)
+ `uvm_field_array_object(alert_host_cfg, UVM_DEFAULT)
+ `uvm_field_array_object(esc_device_cfg, UVM_DEFAULT)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+ virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ num_edn = 1;
+ super.initialize(csr_base_addr);
+ shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1;
+ shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1;
+
+ // set num_interrupts & num_alerts
+ begin
+ uvm_reg rg = ral.get_reg_by_name("intr_state");
+ if (rg != null) begin
+ num_interrupts = ral.intr_state.get_n_used_bits();
+ end
+ end
+
+ alert_host_cfg = new[NUM_ALERTS];
+ esc_device_cfg = new[NUM_ESCS];
+ foreach (alert_host_cfg[i]) begin
+ alert_host_cfg[i] =
+ alert_esc_agent_cfg::type_id::create($sformatf("alert_host_cfg[%0d]", i));
+ alert_host_cfg[i].if_mode = dv_utils_pkg::Host;
+ alert_host_cfg[i].is_async = ASYNC_ON[i];
+ end
+ foreach (esc_device_cfg[i]) begin
+ esc_device_cfg[i] =
+ alert_esc_agent_cfg::type_id::create($sformatf("esc_device_cfg[%0d]", i));
+ esc_device_cfg[i].if_mode = dv_utils_pkg::Device;
+ esc_device_cfg[i].is_alert = 0;
+ end
+ // only support 1 outstanding TL items in tlul_adapter
+ m_tl_agent_cfg.max_outstanding_req = 1;
+ endfunction
+
+ // Override shadow register naming checks. The alert handler does not expose any alert signals,
+ // hence no alerts are defined in Hjson.
+ virtual function void check_shadow_reg_alerts();
+ // Nothing to check.
+ endfunction
+
+endclass
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv
new file mode 100644
index 0000000..69bcfe9
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv
@@ -0,0 +1,186 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_ping_with_lpg_cg_wrap;
+ covergroup alert_ping_with_lpg_cg(string name) with function sample (bit lpg_en);
+ option.per_instance = 1;
+ option.name = name;
+ lpg_cg: coverpoint lpg_en {
+ bins lpg_en = {1};
+ bins lpg_dis = {0};
+ }
+ endgroup
+
+ function new(string name);
+ alert_ping_with_lpg_cg = new(name);
+ endfunction
+endclass
+
+class alert_handler_env_cov extends cip_base_env_cov #(.CFG_T(alert_handler_env_cfg));
+ `uvm_component_utils(alert_handler_env_cov)
+
+ alert_ping_with_lpg_cg_wrap ping_with_lpg_cg_wrap[NUM_ALERTS];
+
+ // covergroups
+ covergroup accum_cnt_cg with function sample(int class_index, int cnt);
+ class_index_cp: coverpoint class_index {
+ bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ }
+ // Due to the limited simulation time, this only collect accum coverage until 2000. For the
+ // saturation case, design has assertions to cover that.
+ accum_cnt_cp: coverpoint cnt {
+ bins accum_cnt_0 = {0};
+ bins accum_cnt_10 = {[1:10]};
+ bins accum_cnt_50 = {[11:50]};
+ bins accum_cnt_100 = {[51:100]};
+ bins accum_cnt_1000 = {[101:1000]};
+ bins accum_cnt_2000 = {[1001:2000]};
+ }
+ class_cnt_cross: cross class_index_cp, accum_cnt_cp;
+ endgroup : accum_cnt_cg
+
+ covergroup intr_timeout_cnt_cg with function sample(int class_index, int cnt);
+ class_index_cp: coverpoint class_index {
+ bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ }
+ intr_timeout_cnt_cp: coverpoint cnt {
+ bins intr_timeout_cnt[10] = {[0:1000]};
+ }
+ class_cnt_cross: cross class_index_cp, intr_timeout_cnt_cp;
+ endgroup
+
+ covergroup esc_sig_length_cg with function sample(int sig_index, int sig_len);
+ esc_sig_index_cp: coverpoint sig_index {
+ bins index[NUM_ESC_SIGNALS] = {[0:NUM_ESC_SIGNALS-1]};
+ }
+ esc_sig_len_cp: coverpoint sig_len {
+ bins len_2 = {2};
+ bins lens_less_than_1000[10] = {[3:1000]};
+ }
+ len_per_esc_sig: cross esc_sig_index_cp, esc_sig_len_cp;
+ endgroup : esc_sig_length_cg
+
+ covergroup clear_intr_cnt_cg with function sample(int class_index);
+ clear_intr_cnt_cp: coverpoint class_index {
+ bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ }
+ endgroup
+
+ covergroup clear_esc_cnt_cg with function sample(int class_index);
+ clear_esc_cnt_cp: coverpoint class_index {
+ bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ }
+ endgroup
+
+ covergroup alert_cause_cg with function sample(int alert_index, int class_index);
+ alert_cause_cp: coverpoint alert_index {
+ bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]};
+ illegal_bins il = default;
+ }
+ class_index_cp: coverpoint class_index {
+ bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ illegal_bins il = default;
+ }
+ alert_cause_cross_class_index: cross alert_cause_cp, class_index_cp;
+ endgroup
+
+ covergroup alert_loc_alert_cause_cg with function sample(local_alert_type_e local_alert,
+ int alert_index,
+ int class_index);
+ loc_alert_cause_cp: coverpoint local_alert {
+ bins alert_ping_fail = {LocalAlertPingFail};
+ bins alert_integrity_fail = {LocalAlertIntFail};
+ illegal_bins il = default;
+ }
+ alert_index_cp: coverpoint alert_index {
+ bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]};
+ illegal_bins il = default;
+ }
+ class_index_cp: coverpoint class_index {
+ bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ illegal_bins il = default;
+ }
+ loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, alert_index_cp;
+ loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp;
+ endgroup
+
+ covergroup esc_loc_alert_cause_cg with function sample(local_alert_type_e local_alert,
+ int esc_index,
+ int class_index);
+ loc_alert_cause_cp: coverpoint local_alert {
+ bins esc_ping_fail = {LocalEscPingFail};
+ bins esc_integrity_fail = {LocalEscIntFail};
+ illegal_bins il = default;
+ }
+ esc_index_cp: coverpoint esc_index {
+ bins alert[NUM_ESCS] = {[0:NUM_ESCS-1]};
+ illegal_bins il = default;
+ }
+ class_index_cp: coverpoint class_index {
+ bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]};
+ illegal_bins il = default;
+ }
+ loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, esc_index_cp;
+ loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp;
+ endgroup
+
+ covergroup crashdump_trigger_cg with function sample(bit [1:0] phase);
+ crashdump_trigger_phase_cp: coverpoint phase {
+ bins phase_0 = {0};
+ bins phase_1 = {1};
+ bins phase_2 = {2};
+ bins phase_3 = {3};
+ }
+ endgroup
+
+ // Covergroup to make sure simulation is long enough to fetch more than five EDN requests.
+ covergroup num_edn_reqs_cg with function sample(int num_edn_reqs);
+ num_edn_reqs_cp: coverpoint num_edn_reqs {
+ bins less_than_five_reqs = {[1:4]};
+ bins five_or_more_reqs = {[5:$]};
+ }
+ endgroup
+
+ covergroup num_checked_pings_cg with function sample (int num_pings);
+ num_pings_cp: coverpoint num_pings {
+ bins less_than_ten_pings = {[1:9]};
+ bins ten_to_twenty_pings = {[10:19]};
+ bins more_than_twenty_pings = {[20:$]};
+ }
+ endgroup
+
+ covergroup cycles_between_pings_cg with function sample (int num_cycles_between_pings);
+ num_cycles_cp: coverpoint num_cycles_between_pings{
+ bins less_than_5000_cycs = {[1:4_999]};
+ bins less_than_100k_cycs = {[5_000:99_999]};
+ bins less_than_200k_cycs = {[100_000:199_999]};
+ bins less_than_300k_cycs = {[200_000:299_999]};
+ bins less_than_400k_cycs = {[300_000:399_999]};
+ bins less_than_500k_cycs = {[400_000:499_999]};
+ bins more_than_500k_cycs = {[500_000:'hFFFF]};
+ }
+ endgroup
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ accum_cnt_cg = new();
+ intr_timeout_cnt_cg = new();
+ esc_sig_length_cg = new();
+ clear_intr_cnt_cg = new();
+ clear_esc_cnt_cg = new();
+ alert_cause_cg = new();
+ alert_loc_alert_cause_cg = new();
+ esc_loc_alert_cause_cg = new();
+ crashdump_trigger_cg = new();
+
+ num_edn_reqs_cg = new();
+ num_checked_pings_cg = new();
+ cycles_between_pings_cg = new();
+
+ foreach (ping_with_lpg_cg_wrap[i]) begin
+ ping_with_lpg_cg_wrap[i] = new($sformatf("ping_with_lpg_cg_wrap[%0d]", i));
+ end
+ endfunction : new
+
+endclass
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv
new file mode 100644
index 0000000..64922cf
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv
@@ -0,0 +1,106 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package alert_handler_env_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import top_pkg::*;
+ import dv_utils_pkg::*;
+ import csr_utils_pkg::*;
+ import tl_agent_pkg::*;
+ import alert_esc_agent_pkg::*;
+ import alert_handler_ral_pkg::*;
+ import dv_base_reg_pkg::*;
+ import cip_base_pkg::*;
+ import push_pull_agent_pkg::*;
+ import sec_cm_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // parameters
+ parameter uint NUM_ALERTS = alert_handler_reg_pkg::NAlerts;
+ parameter uint NUM_EDN = 1;
+ parameter uint NUM_ESCS = 4;
+ parameter uint NUM_MAX_ESC_SEV = 8;
+ parameter uint NUM_ESC_SIGNALS = 4;
+ parameter uint NUM_ALERT_CLASSES = 4;
+ parameter uint NUM_ESC_PHASES = 4;
+ parameter uint NUM_ALERT_CLASS_MSB = $clog2(NUM_ALERT_CLASSES) - 1;
+ parameter uint MIN_CYCLE_PER_PHASE = 2;
+ parameter uint NUM_LOCAL_ALERTS = 7;
+ parameter bit [NUM_ALERTS-1:0] ASYNC_ON = alert_handler_reg_pkg::AsyncOn;
+ // ignore esc signal cycle count after ping occurs - as ping response might ended up adding one
+ // extra cycle to the calculated cnt, or even combine two signals into one.
+ parameter uint IGNORE_CNT_CHECK_NS = 100_000_000;
+ // set the max ping timeout cycle to constrain the simulation run time
+ parameter uint MAX_PING_TIMEOUT_CYCLE = 300;
+
+ // Alert_handler ping timer design should automatically fetch EDN entropy every 500k clock
+ // cycles. We set the threshold to 600k clock cycles.
+ parameter uint MAX_EDN_REQ_WAIT_CYCLES = 600_000;
+
+ parameter uint NUM_CRASHDUMP = NUM_ALERT_CLASSES * (alert_handler_reg_pkg::AccuCntDw
+ + alert_handler_reg_pkg::EscCntDw + 3) +
+ NUM_ALERTS + NUM_LOCAL_ALERTS;
+ parameter bit[15:0] MAX_PING_WAIT_CYCLES = '1;
+
+ // types
+ typedef enum {
+ EscPhase0,
+ EscPhase1,
+ EscPhase2,
+ EscPhase3
+ } esc_phase_e;
+
+ typedef enum {
+ AlertClassCtrlEn,
+ AlertClassCtrlLock,
+ AlertClassCtrlEnE0,
+ AlertClassCtrlEnE1,
+ AlertClassCtrlEnE2,
+ AlertClassCtrlEnE3,
+ AlertClassCtrlMapE0,
+ AlertClassCtrlMapE1,
+ AlertClassCtrlMapE2,
+ AlertClassCtrlMapE3
+ } alert_class_ctrl_e;
+
+ typedef enum {
+ EscStateIdle = 'b000,
+ EscStateTimeout = 'b001,
+ EscStateTerminal = 'b011,
+ EscStatePhase0 = 'b100,
+ EscStatePhase1 = 'b101,
+ EscStatePhase2 = 'b110,
+ EscStatePhase3 = 'b111
+ } esc_state_e;
+
+ typedef enum {
+ LocalAlertPingFail,
+ LocalEscPingFail,
+ LocalAlertIntFail,
+ LocalEscIntFail,
+ LocalBusIntgFail,
+ LocalShadowRegUpdateErr,
+ LocalShadowRegStorageErr
+ } local_alert_type_e;
+
+ // forward declare classes to allow typedefs below
+ typedef virtual pins_if #(NUM_MAX_ESC_SEV) esc_en_vif;
+ typedef virtual pins_if #(NUM_CRASHDUMP) crashdump_vif;
+ typedef virtual alert_handler_if alert_handler_vif;
+
+ // functions
+
+ // package sources
+ `include "alert_handler_env_cfg.sv"
+ `include "alert_handler_env_cov.sv"
+ `include "alert_handler_virtual_sequencer.sv"
+ `include "alert_handler_scoreboard.sv"
+ `include "alert_handler_env.sv"
+ `include "alert_handler_vseq_list.sv"
+
+endpackage
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_if.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_if.sv
new file mode 100644
index 0000000..d585864
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_if.sv
@@ -0,0 +1,60 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Interface for LPG and crashdump output.
+interface alert_handler_if(input clk, input rst_n);
+ import uvm_pkg::*;
+ import alert_pkg::*;
+ import prim_mubi_pkg::*;
+ import cip_base_pkg::*;
+ import alert_handler_env_pkg::*;
+
+ mubi4_t [NLpg-1:0] lpg_cg_en;
+ mubi4_t [NLpg-1:0] lpg_rst_en;
+
+ logic [NUM_ALERTS-1:0] alert_ping_reqs;
+ logic [NUM_ESCS-1:0] esc_ping_reqs;
+
+ string msg_id = "alert_handler_if";
+
+ function automatic void init();
+ mubi4_t mubi_false_val = get_rand_mubi4_val(0, 1, 1);
+ lpg_cg_en = '{default: mubi_false_val};
+ lpg_rst_en = '{default: mubi_false_val};
+ endfunction
+
+ function automatic bit get_lpg_status(int index);
+ check_lpg_index(index);
+ return (lpg_cg_en[index] == MuBi4True || lpg_rst_en[index] == MuBi4True);
+ endfunction
+
+ function automatic void set_lpg_cg_en(int index);
+ check_lpg_index(index);
+ lpg_cg_en[index] = MuBi4True;
+ endfunction
+
+ function automatic void set_lpg_rst_en(int index);
+ check_lpg_index(index);
+ lpg_rst_en[index] = MuBi4True;
+ endfunction
+
+ function automatic void check_lpg_index(int index);
+ if (index >= NLpg) begin
+ `uvm_fatal(msg_id, $sformatf("Alert_handler has %0d LPGs but attempts to set index %0d",
+ NLpg, index))
+ end
+ endfunction
+
+ task automatic set_wait_cyc_mask(logic [PING_CNT_DW-1:0] val);
+ static logic [PING_CNT_DW-1:0] val_static;
+ begin
+ val_static = val;
+ force tb.dut.u_ping_timer.wait_cyc_mask_i = val_static;
+ end
+ endtask
+
+ task automatic release_wait_cyc_mask();
+ release tb.dut.u_ping_timer.wait_cyc_mask_i;
+ endtask
+endinterface
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv
new file mode 100644
index 0000000..122f128
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv
@@ -0,0 +1,771 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`define ASSIGN_CLASS_PHASE_REGS(index, i) \
+ reg_esc_phase_cycs_per_class_q[``index``] = \
+ {ral.class``i``_phase0_cyc_shadowed, ral.class``i``_phase1_cyc_shadowed, \
+ ral.class``i``_phase2_cyc_shadowed, ral.class``i``_phase3_cyc_shadowed};
+
+class alert_handler_scoreboard extends cip_base_scoreboard #(
+ .CFG_T(alert_handler_env_cfg),
+ .RAL_T(alert_handler_reg_block),
+ .COV_T(alert_handler_env_cov)
+ );
+ `uvm_component_utils(alert_handler_scoreboard)
+
+ // esc_phase_cyc_per_class_q: each class has four phase cycles, stores each cycle length
+ // --- class --- phase0_cyc --- phase1_cyc --- phase2_cyc --- phase3_cyc ---
+ // --- A -classa_phase0_cyc - classa_phase1_cyc - classa_phase2_cyc - classa_phase3_cyc --
+ // --- B -classb_phase0_cyc - classb_phase1_cyc - classb_phase2_cyc - classb_phase3_cyc --
+ // --- C -classc_phase0_cyc - classc_phase1_cyc - classc_phase2_cyc - classc_phase3_cyc --
+ // --- D -classd_phase0_cyc - classd_phase1_cyc - classd_phase2_cyc - classd_phase3_cyc --
+ dv_base_reg reg_esc_phase_cycs_per_class_q[NUM_ALERT_CLASSES][$];
+
+ uvm_reg_field intr_state_fields[$];
+ uvm_reg_field intr_state_field;
+ // once escalation triggers, no alerts can trigger another escalation in the same class
+ // until the class esc is cleared
+ bit [NUM_ALERT_CLASSES-1:0] under_esc_classes;
+ bit [NUM_ALERT_CLASSES-1:0] under_intr_classes;
+ bit [NUM_ALERT_CLASSES-1:0] clr_esc_under_intr;
+ int intr_cnter_per_class [NUM_ALERT_CLASSES];
+ int accum_cnter_per_class [NUM_ALERT_CLASSES];
+ esc_state_e state_per_class [NUM_ALERT_CLASSES];
+ int esc_signal_release [NUM_ESC_SIGNALS];
+ int esc_sig_class [NUM_ESC_SIGNALS]; // one class can increment one esc signal at a time
+ // For different alert classify in the same class and trigger at the same cycle, design only
+ // count once. So record the alert triggered timing here
+ realtime last_triggered_alert_per_class[NUM_ALERT_CLASSES];
+
+ string class_name[] = {"a", "b", "c", "d"};
+ bit [TL_DW-1:0] intr_state_val;
+
+ bit [NUM_ALERT_CLASSES-1:0] crashdump_triggered = 0;
+
+ bit ping_timer_en;
+
+ // TLM agent fifos
+ uvm_tlm_analysis_fifo #(alert_esc_seq_item) alert_fifo[NUM_ALERTS];
+ uvm_tlm_analysis_fifo #(alert_esc_seq_item) esc_fifo[NUM_ESCS];
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ ral.intr_state.get_fields(intr_state_fields);
+ `ASSIGN_CLASS_PHASE_REGS(0, a)
+ `ASSIGN_CLASS_PHASE_REGS(1, b)
+ `ASSIGN_CLASS_PHASE_REGS(2, c)
+ `ASSIGN_CLASS_PHASE_REGS(3, d)
+
+ foreach (alert_fifo[i]) alert_fifo[i] = new($sformatf("alert_fifo[%0d]", i), this);
+ foreach (esc_fifo[i]) esc_fifo[i] = new($sformatf("esc_fifo[%0d]" , i), this);
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ endfunction
+
+ task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ fork
+ process_alert_fifo();
+ process_esc_fifo();
+ process_edn_fifos();
+ check_ping_timer();
+ check_crashdump();
+ check_intr_timeout_trigger_esc();
+ esc_phase_signal_cnter();
+ release_esc_signal();
+ join_none
+ endtask
+
+ virtual task process_alert_fifo();
+ foreach (alert_fifo[i]) begin
+ automatic int index = i;
+ automatic int lpg_index = alert_handler_reg_pkg::LpgMap[index];
+ fork
+ forever begin
+ bit alert_en, loc_alert_en;
+ alert_esc_seq_item act_item;
+ alert_fifo[index].get(act_item);
+ alert_en = ral.alert_en_shadowed[index].get_mirrored_value() &&
+ prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_cg_en[lpg_index]) &&
+ prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_rst_en[lpg_index]);
+
+ // Check that ping mechanism will only ping alerts that have been enabled and locked.
+ if (act_item.alert_esc_type == AlertEscPingTrans) begin
+ `DV_CHECK(alert_en, $sformatf("alert %0s ping triggered but not enabled", index))
+ `DV_CHECK((`gmv(ral.alert_regwen[index]) == 0),
+ $sformatf("alert %0s ping triggered but not locked", index))
+ end
+
+ if (alert_en) begin
+ // alert detected
+ if (act_item.alert_esc_type == AlertEscSigTrans && !act_item.ping_timeout &&
+ act_item.alert_handshake_sta == AlertReceived) begin
+ process_alert_sig(index, 0);
+ // alert integrity fail
+ end else if (act_item.alert_esc_type == AlertEscIntFail) begin
+ loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertIntFail].get_mirrored_value();
+ if (loc_alert_en) process_alert_sig(index, 1, LocalAlertIntFail);
+ end else if (act_item.alert_esc_type == AlertEscPingTrans &&
+ act_item.ping_timeout) begin
+ loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertPingFail].get_mirrored_value();
+ if (loc_alert_en) begin
+ process_alert_sig(index, 1, LocalAlertPingFail);
+ `uvm_info(`gfn, $sformatf("alert %0d ping timeout, timeout_cyc reg is %0d",
+ index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW);
+ end
+ end
+ end
+ end
+ join_none
+ end
+ endtask : process_alert_fifo
+
+ virtual task process_esc_fifo();
+ foreach (esc_fifo[i]) begin
+ automatic int index = i;
+ fork
+ forever begin
+ alert_esc_seq_item act_item;
+ esc_fifo[index].get(act_item);
+ // escalation triggered, check signal length
+ if (act_item.alert_esc_type == AlertEscSigTrans &&
+ act_item.esc_handshake_sta == EscRespComplete) begin
+ check_esc_signal(act_item.sig_cycle_cnt, index);
+ // escalation integrity fail
+ end else if (act_item.alert_esc_type == AlertEscIntFail ||
+ (act_item.esc_handshake_sta == EscIntFail && !act_item.ping_timeout)) begin
+ bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscIntFail].get_mirrored_value();
+ if (loc_alert_en) process_alert_sig(index, 1, LocalEscIntFail);
+ // escalation ping timeout
+ end else if (act_item.alert_esc_type == AlertEscPingTrans) begin
+ if (act_item.ping_timeout) begin
+ bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscPingFail].get_mirrored_value();
+ if (loc_alert_en) begin
+ process_alert_sig(index, 1, LocalEscPingFail);
+ `uvm_info(`gfn, $sformatf("esc %0d ping timeout, timeout_cyc reg is %0d",
+ index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW);
+ end
+ end
+ end
+ end
+ join_none
+ end
+ endtask : process_esc_fifo
+
+ // Alert_handler ping timer is designed to fetch EDN value periodically.
+ virtual task process_edn_fifos();
+ fork begin: isolation_fork
+ int num_edn_reqs;
+ forever begin
+ wait (cfg.under_reset == 0);
+ fork
+ begin
+ check_edn_request_cycles();
+ num_edn_reqs++;
+ if (cfg.en_cov) cov.num_edn_reqs_cg.sample(num_edn_reqs);
+ end
+ begin
+ wait (cfg.under_reset == 1);
+ num_edn_reqs = 0;
+ end
+ join_any
+ disable fork;
+ end
+ end join
+ endtask
+
+ virtual task check_edn_request_cycles();
+ int edn_wait_cycles;
+ fork
+ begin : isolation_fork
+ fork
+ begin
+ while (edn_wait_cycles < MAX_EDN_REQ_WAIT_CYCLES) begin
+ cfg.clk_rst_vif.wait_clks(1);
+ edn_wait_cycles++;
+ end
+ `uvm_error(`gfn, "Timeout occured waiting for an EDN request!");
+ end
+ begin
+ push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item;
+ edn_fifos[0].get(edn_item);
+ end
+ join_any
+ disable fork;
+ end
+ join
+ endtask
+
+ // this task process alert signal by checking if intergrity fail, then classify it to the
+ // mapping classes, then check if escalation is triggered by accumulation
+ // this task delayed to a negedge clk to avoid updating and checking regs at the same time
+ virtual task process_alert_sig(int alert_i, bit is_int_err,
+ local_alert_type_e local_alert_type = LocalAlertIntFail);
+ fork
+ begin
+ cfg.clk_rst_vif.wait_n_clks(1);
+ if (!under_reset) begin
+ bit [TL_DW-1:0] intr_en, class_ctrl;
+ bit [NUM_ALERT_CLASS_MSB:0] class_i;
+ if (!is_int_err) begin
+ class_i = `gmv(ral.alert_class_shadowed[alert_i]);
+ void'(ral.alert_cause[alert_i].predict(1));
+ if (cfg.en_cov) cov.alert_cause_cg.sample(alert_i, class_i);
+ end else begin
+ class_i = `gmv(ral.loc_alert_class_shadowed[int'(local_alert_type)]);
+ void'(ral.loc_alert_cause[int'(local_alert_type)].predict(
+ .value(1), .kind(UVM_PREDICT_READ)));
+ if (cfg.en_cov) begin
+ if (local_alert_type inside {LocalAlertPingFail, LocalAlertIntFail}) begin
+ cov.alert_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i);
+ end else begin
+ cov.esc_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i);
+ end
+ end
+ end
+
+ intr_state_field = intr_state_fields[class_i];
+ void'(intr_state_field.predict(.value(1), .kind(UVM_PREDICT_READ)));
+ intr_en = ral.intr_enable.get_mirrored_value();
+
+ // calculate escalation
+ class_ctrl = get_class_ctrl(class_i);
+ `uvm_info(`gfn, $sformatf("class %0d is triggered, class ctrl=%0h, under_esc=%0b",
+ class_i, class_ctrl, under_esc_classes[class_i]), UVM_DEBUG)
+ // if class escalation is enabled, add alert to accumulation count
+ if (class_ctrl[AlertClassCtrlEn] &&
+ (class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0)) begin
+ alert_accum_cal(class_i);
+ end
+
+ // according to issue #841, interrupt will have one clock cycle delay
+ cfg.clk_rst_vif.wait_n_clks(1);
+ if (!under_reset) begin
+ `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[class_i], intr_en[class_i],
+ $sformatf("Interrupt class_%s, is_local_err %0b, local_alert_type %s",
+ class_name[class_i],is_int_err, local_alert_type));
+ if (!under_intr_classes[class_i] && intr_en[class_i]) under_intr_classes[class_i] = 1;
+ end
+ end
+ end
+ join_none
+ endtask
+
+ // calculate alert accumulation count per class, if accumulation exceeds the threshold,
+ // and if current class is not under escalation, then predict escalation
+ // note: if more than one alerts triggered on the same clk cycle, only accumulates one
+ virtual function void alert_accum_cal(int class_i);
+ bit [TL_DW-1:0] accum_thresh = get_class_accum_thresh(class_i);
+ realtime curr_time = $realtime();
+ if (curr_time != last_triggered_alert_per_class[class_i] && !cfg.under_reset) begin
+ last_triggered_alert_per_class[class_i] = curr_time;
+ // avoid accum_cnt saturate
+ if (accum_cnter_per_class[class_i] < 'hffff) begin
+ accum_cnter_per_class[class_i] += 1;
+ if (accum_cnter_per_class[class_i] > accum_thresh && !under_esc_classes[class_i]) begin
+ predict_esc(class_i);
+ end
+ end
+ end
+ `uvm_info(`gfn,
+ $sformatf("alert_accum: class=%0d, alert_cnt=%0d, thresh=%0d, under_esc=%0b",
+ class_i, accum_cnter_per_class[class_i], accum_thresh,
+ under_esc_classes[class_i]), UVM_DEBUG)
+ endfunction
+
+ // if clren register is disabled, predict escalation signals by setting the corresponding
+ // under_esc_classes bit based on class_ctrl's lock bit
+ virtual function void predict_esc(int class_i);
+ bit [TL_DW-1:0] class_ctrl = get_class_ctrl(class_i);
+ if (class_ctrl[AlertClassCtrlLock]) begin
+ uvm_reg clren_rg;
+ clren_rg = ral.get_reg_by_name($sformatf("class%s_clr_regwen", class_name[class_i]));
+ `DV_CHECK_NE_FATAL(clren_rg, null)
+ void'(clren_rg.predict(0));
+ end
+ under_esc_classes[class_i] = 1;
+ endfunction
+
+ // check if escalation signal's duration length is correct
+ virtual function void check_esc_signal(int cycle_cnt, int esc_sig_i);
+ int class_a = `gmv(ral.classa_ctrl_shadowed);
+ int class_b = `gmv(ral.classb_ctrl_shadowed);
+ int class_c = `gmv(ral.classc_ctrl_shadowed);
+ int class_d = `gmv(ral.classd_ctrl_shadowed);
+ int sig_index = AlertClassCtrlEnE0+esc_sig_i;
+ bit [NUM_ALERT_CLASSES-1:0] select_class = {class_d[sig_index], class_c[sig_index],
+ class_b[sig_index], class_a[sig_index]};
+
+
+ // Only compare the escalation signal length if exactly one class is assigned to this signal.
+ // Otherwise scb cannot predict the accurate cycle length if multiple classes are merged.
+ if ($countones(select_class) == 1) begin
+ int exp_cycle, phase, class_i;
+ // Find the class that triggers the escalation, and find which phase the escalation signal is
+ // reflecting.
+ for (class_i = 0; class_i < NUM_ALERT_CLASSES; class_i++) begin
+ if (select_class[class_i] == 1) begin
+ phase = `gmv(ral.get_reg_by_name($sformatf("class%0s_ctrl_shadowed",
+ class_name[class_i])));
+ break;
+ end
+ end
+ phase = phase[(AlertClassCtrlMapE0 + esc_sig_i * 2) +: 2];
+ exp_cycle = `gmv(ral.get_reg_by_name($sformatf("class%0s_phase%0d_cyc_shadowed",
+ class_name[class_i], phase))) + 1;
+ // Minimal phase length is 2 cycles.
+ exp_cycle = exp_cycle < 2 ? 2 : exp_cycle;
+ `uvm_info(`gfn, $sformatf("esc_signal_%0d, esc phase %0d, esc class %0d",
+ esc_sig_i, phase, class_i), UVM_HIGH);
+
+ // If the escalation signal is interrupted by reset or esc_clear, we expect the signal length
+ // to be shorter than the phase_cycle_length.
+ if (cfg.under_reset || under_esc_classes[class_i] == 0) begin
+ `DV_CHECK_LE(cycle_cnt, exp_cycle)
+ end else begin
+ `DV_CHECK_EQ(cycle_cnt, exp_cycle)
+ end
+ if (cfg.en_cov) cov.esc_sig_length_cg.sample(esc_sig_i, cycle_cnt);
+ end
+ esc_sig_class[esc_sig_i] = 0;
+ endfunction
+
+ virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
+ uvm_reg csr;
+ dv_base_reg dv_base_csr;
+ bit do_read_check = 1'b1;
+ bit write = item.is_write();
+ uvm_reg_addr_t csr_addr = {item.a_addr[TL_AW-1:2], 2'b00};
+
+ // if access was to a valid csr, get the csr handle
+ if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin
+ csr = ral.default_map.get_reg_by_offset(csr_addr);
+ `DV_CHECK_NE_FATAL(csr, null)
+ `downcast(dv_base_csr, csr)
+ end
+ if (csr == null) begin
+ // we hit an oob addr - expect error response and return
+ `DV_CHECK_EQ(item.d_error, 1'b1)
+ return;
+ end
+
+ if (channel == AddrChannel) begin
+ // if incoming access is a write to a valid csr, then make updates right away
+ if (write) begin
+ string csr_name = csr.get_name();
+ void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
+ // process the csr req
+ // for write, update local variable and fifo at address phase
+ case (csr_name)
+ // add individual case item for each csr
+ "intr_test": begin
+ bit [TL_DW-1:0] intr_state_exp = item.a_data | ral.intr_state.get_mirrored_value();
+ if (cfg.en_cov) begin
+ bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value();
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_state_exp[i]);
+ end
+ end
+ void'(ral.intr_state.predict(.value(intr_state_exp), .kind(UVM_PREDICT_DIRECT)));
+ end
+ // disable intr_enable or clear intr_state will clear the interrupt timeout cnter
+ "intr_state": begin
+ fork
+ begin
+ // after interrupt is set, it needs one clock cycle to update the value and stop
+ // the intr_timeout counter
+ cfg.clk_rst_vif.wait_clks(1);
+ if (!cfg.under_reset) begin
+ foreach (under_intr_classes[i]) begin
+ if (item.a_data[i]) begin
+ under_intr_classes[i] = 0;
+ clr_esc_under_intr[i] = 0;
+ if (!under_esc_classes[i]) state_per_class[i] = EscStateIdle;
+ end
+ end
+ void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE),
+ .be(item.a_mask)));
+ end
+ end
+ join_none
+ end
+ "intr_enable": begin
+ foreach (under_intr_classes[i]) begin
+ if (item.a_data[i] == 0) under_intr_classes[i] = 0;
+ end
+ end
+ "classa_clr_shadowed": begin
+ if (!dv_base_csr.is_staged() && ral.classa_clr_regwen.get_mirrored_value()) begin
+ clr_reset_esc_class(0);
+ end
+ end
+ "classb_clr_shadowed": begin
+ if (!dv_base_csr.is_staged() && ral.classb_clr_regwen.get_mirrored_value()) begin
+ clr_reset_esc_class(1);
+ end
+ end
+ "classc_clr_shadowed": begin
+ if (!dv_base_csr.is_staged() && ral.classc_clr_regwen.get_mirrored_value()) begin
+ clr_reset_esc_class(2);
+ end
+ end
+ "classd_clr_shadowed": begin
+ if (!dv_base_csr.is_staged() && ral.classd_clr_regwen.get_mirrored_value()) begin
+ clr_reset_esc_class(3);
+ end
+ end
+ "ping_timer_en_shadowed": begin
+ if (shadowed_reg_wr_completed(dv_base_csr) &&
+ item.a_data &&
+ `gmv(ral.ping_timer_regwen)) begin
+ ping_timer_en = 1;
+ end
+ end
+ default: begin
+ // TODO: align all names with shadow post_fix and re-enable this check.
+ //`uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
+ end
+ endcase
+ end
+ end
+
+ // process the csr req
+ // for read, update predication at address phase and compare at data phase
+
+ if (!write) begin
+ // On reads, if do_read_check, is set, then check mirrored_value against item.d_data
+ if (channel == DataChannel) begin
+ if (cfg.en_cov) begin
+ if (csr.get_name() == "intr_state") begin
+ bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value();
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ cov.intr_cg.sample(i, intr_en[i], item.d_data[i]);
+ cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]);
+ end
+ end else begin
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin
+ cov.accum_cnt_cg.sample(i, item.d_data);
+ end
+ end
+ end
+ end
+ if (csr.get_name == "intr_state") begin
+ `DV_CHECK_EQ(intr_state_val, item.d_data, $sformatf("reg name: %0s", "intr_state"))
+ do_read_check = 0;
+ end
+ if (do_read_check) begin
+ `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data,
+ $sformatf("reg name: %0s", csr.get_full_name()))
+ end
+ void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ)));
+ end else begin
+ // predict in address phase to avoid the register's value changed during the read
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ if (csr.get_name() == $sformatf("class%s_esc_cnt", class_name[i])) begin
+ void'(csr.predict(.value(intr_cnter_per_class[i]), .kind(UVM_PREDICT_READ)));
+ end else if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin
+ void'(csr.predict(.value(accum_cnter_per_class[i]), .kind(UVM_PREDICT_READ)));
+ end else if (csr.get_name() == $sformatf("class%s_state", class_name[i])) begin
+ void'(csr.predict(.value(state_per_class[i]), .kind(UVM_PREDICT_READ)));
+ end
+ end
+ if (csr.get_name() == "intr_state") intr_state_val = csr.get_mirrored_value();
+ end
+ end
+ endtask
+
+ virtual task check_ping_timer();
+ int num_checked_pings;
+ fork begin : isolation_fork
+ forever begin
+ wait (ping_timer_en == 1);
+ fork
+ begin
+ wait (cfg.under_reset == 1);
+ ping_timer_en = 0;
+ num_checked_pings = 0;
+ end
+ begin
+ check_ping_triggered_cycles();
+ num_checked_pings++;
+ if (cfg.en_cov) cov.num_checked_pings_cg.sample(num_checked_pings);
+ end
+ join_any
+ disable fork;
+ end
+ end join
+ endtask
+
+ // This task checks if pings are triggered within the expected time.
+ //
+ // The ping timer is 16 bits so ideally we should see alert_ping -> esc_ping -> alert_ping ...
+ // with the max length of 16'hFFFF clock cycle. However alert_ping is randomly selected so we
+ // can not guarantee the random alert index is valid (exists), enabld, and locked.
+ // However, esc ping timer should are always expected to trigger.
+ // So the max wait time is 'hFFFF*2.
+ // This task also used the probed design signal instead of detected ping requests from monitor.
+ // Because if esc ping request and real esc request come at the same time, design will ignore the
+ // ping requests. But the probed signal will still set to 1.
+ virtual task check_ping_triggered_cycles();
+ int ping_wait_cycs;
+ while (ping_wait_cycs <= MAX_PING_WAIT_CYCLES * 2) begin
+ if (cfg.alert_handler_vif.alert_ping_reqs > 0) begin
+ if (cfg.en_cov) begin
+ int alert_id = $clog2(cfg.alert_handler_vif.alert_ping_reqs);
+ cov.ping_with_lpg_cg_wrap[alert_id].alert_ping_with_lpg_cg.sample(
+ cfg.alert_host_cfg[alert_id].en_alert_lpg);
+ end
+ break;
+ end
+ if (cfg.alert_handler_vif.esc_ping_reqs > 0) break;
+ cfg.clk_rst_vif.wait_clks(1);
+ ping_wait_cycs++;
+ end
+ if (ping_wait_cycs > MAX_PING_WAIT_CYCLES * 2) begin
+ `uvm_error(`gfn, "Timeout occured waiting for a ping.");
+ end
+ if (cfg.en_cov) cov.cycles_between_pings_cg.sample(ping_wait_cycs);
+
+ // Wait for ping request to finish to avoid infinite loop.
+ wait (cfg.alert_handler_vif.alert_ping_reqs == 0 && cfg.alert_handler_vif.esc_ping_reqs == 0);
+ endtask
+
+ virtual task check_crashdump();
+ forever begin
+ wait (cfg.under_reset == 0 && cfg.en_scb == 1);
+ @(cfg.crashdump_vif.pins) begin
+ alert_pkg::alert_crashdump_t crashdump_val =
+ alert_pkg::alert_crashdump_t'(cfg.crashdump_vif.sample());
+
+ // Wait two negedge clock cycles to make sure csr mirrored values are updated.
+ `DV_SPINWAIT_EXIT(cfg.clk_rst_vif.wait_n_clks(2);, wait (cfg.under_reset == 1);)
+
+ if (!cfg.under_reset) begin
+ // If crashdump reached the phase programmed at `crashdump_trigger_shadowed`,
+ // `crashdump_o` value should keep stable until reset.
+ if (crashdump_triggered) begin
+ `uvm_fatal(`gfn,
+ "crashdump value should not change after trigger condition is reached!")
+ end
+
+ foreach (crashdump_val.class_esc_state[i]) begin
+ uvm_reg crashdump_trigger_csr = ral.get_reg_by_name(
+ $sformatf("class%0s_crashdump_trigger_shadowed", class_name[i]));
+ if (crashdump_val.class_esc_state[i] == (`gmv(crashdump_trigger_csr) + 3'b100)) begin
+ crashdump_triggered[i] = 1;
+ if (cfg.en_cov) cov.crashdump_trigger_cg.sample(`gmv(crashdump_trigger_csr));
+ break;
+ end
+ end
+
+ for (int i = 0; i < NUM_ALERTS; i++) begin
+ `DV_CHECK_EQ(crashdump_val.alert_cause[i], `gmv(ral.alert_cause[i]))
+ end
+ for (int i = 0; i < NUM_LOCAL_ALERTS; i++) begin
+ `DV_CHECK_EQ(crashdump_val.loc_alert_cause[i], `gmv(ral.loc_alert_cause[i]))
+ end
+ end
+ end
+ end
+ endtask
+
+ // a counter to count how long each interrupt pins stay high until it is being reset
+ // if counter exceeds threshold, call predict_esc() function to calculate related esc
+ virtual task check_intr_timeout_trigger_esc();
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ fork
+ automatic int class_i = i;
+ begin : intr_sig_counter
+ forever @(under_intr_classes[class_i] && !under_esc_classes[class_i]) begin
+ fork
+ begin
+ bit [TL_DW-1:0] timeout_cyc, class_ctrl;
+ // if escalation cleared but interrupt not cleared, wait one more clk cycle for the
+ // FSM to reset to Idle, then start to count
+ if (clr_esc_under_intr[class_i]) cfg.clk_rst_vif.wait_n_clks(1);
+ clr_esc_under_intr[class_i] = 0;
+ // wait a clk for esc signal to go high
+ cfg.clk_rst_vif.wait_n_clks(1);
+ class_ctrl = get_class_ctrl(class_i);
+ if (class_ctrl[AlertClassCtrlEn] &&
+ class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0) begin
+ intr_cnter_per_class[class_i] = 1;
+ `uvm_info(`gfn, $sformatf("Class %0d start counter", class_i), UVM_HIGH)
+ timeout_cyc = get_class_timeout_cyc(class_i);
+ if (timeout_cyc > 0) begin
+ state_per_class[class_i] = EscStateTimeout;
+ while (under_intr_classes[class_i]) begin
+ @(cfg.clk_rst_vif.cbn);
+ if (intr_cnter_per_class[class_i] >= timeout_cyc) begin
+ predict_esc(class_i);
+ if (cfg.en_cov) cov.intr_timeout_cnt_cg.sample(class_i, timeout_cyc);
+ end
+ intr_cnter_per_class[class_i] += 1;
+ `uvm_info(`gfn, $sformatf("counter_%0d value: %0d", class_i,
+ intr_cnter_per_class[class_i]), UVM_HIGH)
+ end
+ end
+ intr_cnter_per_class[class_i] = 0;
+ end
+ end
+ begin
+ wait(under_esc_classes[class_i]);
+ end
+ join_any
+ disable fork;
+ end // end forever
+ end
+ join_none
+ end
+ endtask
+
+ // two counters for phases cycle length and esc signals cycle length
+ // phase cycle cnter: "intr_cnter_per_class" is used to check "esc_cnt" registers
+ virtual task esc_phase_signal_cnter();
+ for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin
+ fork
+ automatic int class_i = i;
+ begin : esc_phases_counter
+ forever @(!cfg.under_reset && under_esc_classes[class_i]) begin
+ fork
+ begin : inc_esc_cnt
+ for (int phase_i = 0; phase_i < NUM_ESC_PHASES; phase_i++) begin
+ int phase_thresh = `gmv(reg_esc_phase_cycs_per_class_q[class_i][phase_i]);
+ bit[TL_DW-1:0] class_ctrl = get_class_ctrl(class_i);
+ int enabled_sig_q[$];
+ for (int sig_i = 0; sig_i < NUM_ESC_SIGNALS; sig_i++) begin
+ if (class_ctrl[sig_i*2+7 -: 2] == phase_i && class_ctrl[sig_i+2]) begin
+ enabled_sig_q.push_back(sig_i);
+ end
+ end
+ if (under_esc_classes[class_i]) begin
+ intr_cnter_per_class[class_i] = 1;
+ state_per_class[class_i] = esc_state_e'(phase_i + int'(EscStatePhase0));
+ cfg.clk_rst_vif.wait_n_clks(1);
+ while (under_esc_classes[class_i] &&
+ intr_cnter_per_class[class_i] < phase_thresh) begin
+ intr_cnter_per_class[class_i]++;
+ cfg.clk_rst_vif.wait_n_clks(1);
+ end
+ foreach (enabled_sig_q[i]) begin
+ int index = enabled_sig_q[i];
+ if (esc_sig_class[index] == (class_i + 1)) esc_signal_release[index] = 1;
+ end
+ end
+ end // end four phases
+ intr_cnter_per_class[class_i] = 0;
+ if (under_esc_classes[class_i]) state_per_class[class_i] = EscStateTerminal;
+ end
+ begin
+ wait(cfg.under_reset || !under_esc_classes[class_i]);
+ if (!under_esc_classes[class_i]) begin
+ // wait 1 clk cycles until esc_signal_release is set
+ cfg.clk_rst_vif.wait_clks(1);
+ end
+ end
+ join_any
+ disable fork;
+ intr_cnter_per_class[class_i] = 0;
+ end // end forever
+ end
+ join_none
+ end
+ endtask
+
+ // release escalation signal after one clock cycle, to ensure happens at the end of the clock
+ // cycle, waited 1 clks here
+ virtual task release_esc_signal();
+ for (int i = 0; i < NUM_ESC_SIGNALS; i++) begin
+ fork
+ automatic int sig_i = i;
+ forever @ (esc_signal_release[sig_i]) begin
+ cfg.clk_rst_vif.wait_clks(1);
+ esc_sig_class[sig_i] = 0;
+ esc_signal_release[sig_i] = 0;
+ end
+ join_none
+ end
+ endtask
+
+ virtual function void reset(string kind = "HARD");
+ super.reset(kind);
+ under_intr_classes = '{default:0};
+ intr_cnter_per_class = '{default:0};
+ under_esc_classes = '{default:0};
+ esc_sig_class = '{default:0};
+ accum_cnter_per_class = '{default:0};
+ state_per_class = '{default:EscStateIdle};
+ clr_esc_under_intr = 0;
+ crashdump_triggered = 0;
+ ping_timer_en = 0;
+ last_triggered_alert_per_class = '{default:$realtime};
+ endfunction
+
+ // clear accumulative counters, and escalation counters if they are under escalation
+ // interrupt timeout counters cannot be cleared by this
+ task clr_reset_esc_class(int i);
+ fork
+ automatic int class_i = i;
+ begin
+ cfg.clk_rst_vif.wait_clks(1);
+ // TODO(#13026): Update `crashdump_triggered`.
+ // crashdump_triggered[class_i] = 0;
+ crashdump_triggered = 0;
+ if (under_intr_classes[class_i]) begin
+ if (cfg.en_cov) cov.clear_intr_cnt_cg.sample(class_i);
+ clr_esc_under_intr[class_i] = 1;
+ end
+ if (under_esc_classes [class_i]) begin
+ if (cfg.en_cov) cov.clear_esc_cnt_cg.sample(class_i);
+ intr_cnter_per_class[class_i] = 0;
+ end
+ under_esc_classes[class_i] = 0;
+ cfg.clk_rst_vif.wait_n_clks(1);
+ last_triggered_alert_per_class[class_i] = $realtime;
+ accum_cnter_per_class[class_i] = 0;
+ if (state_per_class[class_i] != EscStateTimeout) state_per_class[class_i] = EscStateIdle;
+ end
+ join_none
+ endtask
+
+ function void check_phase(uvm_phase phase);
+ super.check_phase(phase);
+ endfunction
+
+ // get class_ctrl register mirrored value by class
+ function bit [TL_DW-1:0] get_class_ctrl(int class_i);
+ uvm_reg class_ctrl_rg;
+ class_ctrl_rg = ral.get_reg_by_name($sformatf("class%s_ctrl_shadowed", class_name[class_i]));
+ `DV_CHECK_NE_FATAL(class_ctrl_rg, null)
+ return class_ctrl_rg.get_mirrored_value();
+ endfunction
+
+ // get class_accum_thresh register mirrored value by class
+ function bit [TL_DW-1:0] get_class_accum_thresh(int class_i);
+ uvm_reg class_thresh_rg;
+ class_thresh_rg = ral.get_reg_by_name($sformatf("class%s_accum_thresh_shadowed",
+ class_name[class_i]));
+ `DV_CHECK_NE_FATAL(class_thresh_rg, null)
+ return class_thresh_rg.get_mirrored_value();
+ endfunction
+
+ // get class_timeout_cyc register mirrored value by class
+ function bit [TL_DW-1:0] get_class_timeout_cyc(int class_i);
+ dv_base_reg class_timeout_rg =
+ ral.get_dv_base_reg_by_name($sformatf("class%s_timeout_cyc_shadowed",
+ class_name[class_i]));
+ return class_timeout_rg.get_mirrored_value();
+ endfunction
+
+ function bit shadowed_reg_wr_completed(dv_base_reg dv_base_reg);
+ return (!dv_base_reg.is_staged() && !dv_base_reg.get_shadow_update_err());
+ endfunction
+
+endclass
+`undef ASSIGN_CLASS_PHASE_REGS
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv
new file mode 100644
index 0000000..af0fa9f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv
@@ -0,0 +1,16 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_virtual_sequencer extends cip_base_virtual_sequencer #(
+ .CFG_T(alert_handler_env_cfg),
+ .COV_T(alert_handler_env_cov)
+ );
+ alert_esc_sequencer alert_host_seqr_h[];
+ alert_esc_sequencer esc_device_seqr_h[];
+
+ `uvm_component_utils(alert_handler_virtual_sequencer)
+
+ `uvm_component_new
+
+endclass
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv
new file mode 100644
index 0000000..eb36c58
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv
@@ -0,0 +1,108 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This sequence force the alert accumulation count to large value, then check if the accum count
+// will saturate and won't overflow.
+
+`define CLASS_CNT_PATH(class_i, i) \
+ string class_``class_i``_path_0 = \
+ "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0]"; \
+ string class_``class_i``_path_1 = \
+ "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[1]";
+
+`define CHECK_ALERT_ACCUM_CNT(class_i, i) \
+ csr_rd_check(.ptr(ral.class``class_i``_accum_cnt), \
+ .compare_value(saturated_class == ``i`` ? \
+ MAX_ACCUM_CNT : MAX_ACCUM_CNT - num_alerts_to_saturate));
+
+class alert_handler_alert_accum_saturation_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_alert_accum_saturation_vseq)
+
+ `uvm_object_new
+
+ parameter uint MAX_ACCUM_CNT = 'hffff;
+ rand int num_alerts_to_saturate;
+ rand bit [1:0] saturated_class; // only 4 classes: a, b, c, d
+
+ `CLASS_CNT_PATH(a, 0)
+ `CLASS_CNT_PATH(b, 1)
+ `CLASS_CNT_PATH(c, 2)
+ `CLASS_CNT_PATH(d, 3)
+
+ constraint num_alerts_to_saturate_c {
+ num_alerts_to_saturate inside {[1 : 10]};
+ $countones(alert_trigger) == 1;
+ }
+
+ function void pre_randomize();
+ this.enable_one_alert_c.constraint_mode(0);
+ this.enable_classa_only_c.constraint_mode(0);
+ endfunction
+
+ virtual task pre_start();
+ // Force accum counts to a large value.
+ `DV_CHECK(uvm_hdl_force(class_a_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate)));
+ `DV_CHECK(uvm_hdl_force(class_a_path_1, (num_alerts_to_saturate)));
+
+ `DV_CHECK(uvm_hdl_force(class_b_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate)));
+ `DV_CHECK(uvm_hdl_force(class_b_path_1, (num_alerts_to_saturate)));
+
+ `DV_CHECK(uvm_hdl_force(class_c_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate)));
+ `DV_CHECK(uvm_hdl_force(class_c_path_1, (num_alerts_to_saturate)));
+
+ `DV_CHECK(uvm_hdl_force(class_d_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate)));
+ `DV_CHECK(uvm_hdl_force(class_d_path_1, (num_alerts_to_saturate)));
+
+ super.pre_start();
+ endtask
+
+ virtual task body();
+ // Assign all alerts to one class.
+ foreach (alert_class_map[i]) alert_class_map[i] = saturated_class;
+ alert_handler_init(.intr_en('1),
+ .alert_en('1),
+ .alert_class(alert_class_map),
+ .loc_alert_en(0),
+ .loc_alert_class(0));
+ csr_wr(ral.classa_accum_thresh_shadowed, '1);
+ csr_wr(ral.classb_accum_thresh_shadowed, '1);
+ csr_wr(ral.classc_accum_thresh_shadowed, '1);
+ csr_wr(ral.classd_accum_thresh_shadowed, '1);
+
+ // Enable and lock all alert classes.
+ csr_wr(ral.classa_ctrl_shadowed.en, 1);
+ csr_wr(ral.classb_ctrl_shadowed.en, 1);
+ csr_wr(ral.classc_ctrl_shadowed.en, 1);
+ csr_wr(ral.classd_ctrl_shadowed.en, 1);
+
+ `DV_CHECK(uvm_hdl_release(class_a_path_0));
+ `DV_CHECK(uvm_hdl_release(class_a_path_1));
+ `DV_CHECK(uvm_hdl_release(class_b_path_0));
+ `DV_CHECK(uvm_hdl_release(class_b_path_1));
+ `DV_CHECK(uvm_hdl_release(class_c_path_0));
+ `DV_CHECK(uvm_hdl_release(class_c_path_1));
+ `DV_CHECK(uvm_hdl_release(class_d_path_0));
+ `DV_CHECK(uvm_hdl_release(class_d_path_1));
+
+ `uvm_info(`gfn, $sformatf("Saturate class %0d, alerts to saturate %0d", saturated_class,
+ num_alerts_to_saturate), UVM_LOW)
+
+ // First round will reach the max count value, afterwards check if the max value saturates and
+ // won't overflow.
+ repeat ($urandom_range(2, 5)) begin
+ repeat (num_alerts_to_saturate) begin
+ `DV_CHECK_MEMBER_RANDOMIZE_FATAL(alert_trigger)
+ drive_alert(alert_trigger, alert_int_err);
+ csr_rd_check(.ptr(ral.intr_state), .compare_value(1 << saturated_class));
+ csr_wr(.ptr(ral.intr_state), .value(1 << saturated_class));
+ end
+
+ `CHECK_ALERT_ACCUM_CNT(a, 0)
+ `CHECK_ALERT_ACCUM_CNT(b, 1)
+ `CHECK_ALERT_ACCUM_CNT(c, 2)
+ `CHECK_ALERT_ACCUM_CNT(d, 3)
+ end
+ endtask
+
+endclass : alert_handler_alert_accum_saturation_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
new file mode 100644
index 0000000..0f5b660
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
@@ -0,0 +1,353 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`define RAND_AND_WR_CLASS_PHASES_CYCLE(i) \
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase0_cyc_shadowed, \
+ class``i``_phase0_cyc_shadowed.value inside {[0: max_phase_cyc]};); \
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase1_cyc_shadowed, \
+ class``i``_phase1_cyc_shadowed.value inside {[0: max_phase_cyc]};); \
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase2_cyc_shadowed, \
+ class``i``_phase2_cyc_shadowed.value inside {[0: max_phase_cyc]};); \
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase3_cyc_shadowed, \
+ class``i``_phase3_cyc_shadowed.value inside {[0: max_phase_cyc]};); \
+ csr_update(ral.class``i``_phase0_cyc_shadowed); \
+ csr_update(ral.class``i``_phase1_cyc_shadowed); \
+ csr_update(ral.class``i``_phase2_cyc_shadowed); \
+ csr_update(ral.class``i``_phase3_cyc_shadowed);
+
+`define RAND_WRITE_CLASS_CTRL(i, en_bit, lock_bit) \
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_ctrl_shadowed, \
+ en.value == en_bit; lock.value == lock_bit;) \
+ csr_wr(.ptr(ral.class``i``_ctrl_shadowed), .value(ral.class``i``_ctrl_shadowed.get()));
+
+class alert_handler_base_vseq extends cip_base_vseq #(
+ .CFG_T (alert_handler_env_cfg),
+ .RAL_T (alert_handler_reg_block),
+ .COV_T (alert_handler_env_cov),
+ .VIRTUAL_SEQUENCER_T (alert_handler_virtual_sequencer)
+ );
+ `uvm_object_utils(alert_handler_base_vseq)
+
+ // various knobs to enable certain routines
+ bit do_alert_handler_init = 1'b0;
+ bit config_locked = 1'b0;
+
+ `uvm_object_new
+
+ virtual task dut_init(string reset_kind = "HARD");
+ cfg.alert_handler_vif.init();
+ super.dut_init();
+ if (do_alert_handler_init) alert_handler_init();
+ config_locked = 0;
+ endtask
+
+ virtual task dut_shutdown();
+ // nothing special yet
+ endtask
+
+ // setup basic alert_handler features
+ // alert_class default 0 -> all alert will trigger interrupt classA
+ virtual task alert_handler_init(
+ bit [NUM_ALERT_CLASSES-1:0] intr_en = '1,
+ bit [NUM_ALERTS-1:0] alert_en = '1,
+ bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class = 'h0,
+ bit [NUM_LOCAL_ALERTS-1:0] loc_alert_en = '1,
+ bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class = 'h0);
+
+ csr_wr(.ptr(ral.intr_enable), .value(intr_en));
+ foreach (alert_en[i]) csr_wr(.ptr(ral.alert_en_shadowed[i]),
+ .value(alert_en[i]));
+ foreach (alert_class[i]) csr_wr(.ptr(ral.alert_class_shadowed[i]),
+ .value(alert_class[i]));
+ foreach (loc_alert_en[i]) csr_wr(.ptr(ral.loc_alert_en_shadowed[i]),
+ .value(loc_alert_en[i]));
+ foreach (loc_alert_class[i]) csr_wr(.ptr(ral.loc_alert_class_shadowed[i]),
+ .value(loc_alert_class[i]));
+ endtask
+
+ virtual task alert_handler_rand_wr_class_ctrl(bit [NUM_ALERT_CLASSES-1:0] lock_bit,
+ bit [NUM_ALERT_CLASSES-1:0] class_en);
+ `RAND_WRITE_CLASS_CTRL(a, class_en[0], lock_bit[0])
+ `RAND_WRITE_CLASS_CTRL(b, class_en[1], lock_bit[1])
+ `RAND_WRITE_CLASS_CTRL(c, class_en[2], lock_bit[2])
+ `RAND_WRITE_CLASS_CTRL(d, class_en[3], lock_bit[3])
+ endtask
+
+ virtual task alert_handler_wr_regwen_regs(bit [NUM_ALERT_CLASSES-1:0] regwen = 0,
+ bit [NUM_ALERTS-1:0] alert_regwen = 0,
+ bit [NUM_LOCAL_ALERTS-1:0] loc_alert_regwen = 0,
+ bit ping_timer_regwen = 0,
+ bit [NUM_ALERT_CLASSES-1:0] class_regwen = 0);
+
+ csr_wr(.ptr(ral.classa_clr_regwen), .value(regwen[0]));
+ csr_wr(.ptr(ral.classb_clr_regwen), .value(regwen[1]));
+ csr_wr(.ptr(ral.classc_clr_regwen), .value(regwen[2]));
+ csr_wr(.ptr(ral.classd_clr_regwen), .value(regwen[3]));
+
+ foreach (alert_regwen[i]) csr_wr(.ptr(ral.alert_regwen[i]), .value(alert_regwen[i]));
+
+ foreach (loc_alert_regwen[i]) begin
+ csr_wr(.ptr(ral.loc_alert_regwen[i]), .value(loc_alert_regwen[i]));
+ end
+
+ csr_wr(.ptr(ral.ping_timer_regwen), .value(ping_timer_regwen));
+
+ csr_wr(.ptr(ral.classa_regwen), .value(class_regwen[0]));
+ csr_wr(.ptr(ral.classb_regwen), .value(class_regwen[1]));
+ csr_wr(.ptr(ral.classc_regwen), .value(class_regwen[2]));
+ csr_wr(.ptr(ral.classd_regwen), .value(class_regwen[3]));
+ endtask
+
+ // If do_lock_config is set, write value 1 to ping_timer_en register.
+ // If not set, this task has 50% of chance to write value 1 to ping_timer_en register.
+ virtual task lock_config(bit do_lock_config);
+ if (do_lock_config || $urandom_range(0, 1)) begin
+ csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(do_lock_config));
+ end
+ endtask
+
+ virtual task drive_alert(bit[NUM_ALERTS-1:0] alert_trigger, bit[NUM_ALERTS-1:0] alert_int_err);
+ fork
+ begin : isolation_fork
+ foreach (alert_trigger[i]) begin
+ if (alert_trigger[i]) begin
+ automatic int index = i;
+ fork
+ begin
+ alert_sender_seq alert_seq;
+ `uvm_create_on(alert_seq, p_sequencer.alert_host_seqr_h[index]);
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(alert_seq, int_err == alert_int_err[index];)
+ `uvm_send(alert_seq)
+ end
+ join_none
+ end
+ end
+ wait fork;
+ end
+ join
+ endtask
+
+ // This sequence will drive standalone esc_resp_p/n without esc_p/n
+ virtual task drive_esc_rsp(bit [NUM_ESCS-1:0] esc_int_errs);
+ fork
+ begin : isolation_fork
+ foreach (cfg.esc_device_cfg[i]) begin
+ automatic int index = i;
+ if (esc_int_errs[index]) begin
+ fork
+ begin
+ esc_receiver_esc_rsp_seq esc_seq =
+ esc_receiver_esc_rsp_seq::type_id::create("esc_seq");
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == 1; standalone_int_err == 1;
+ ping_timeout == 0;)
+ esc_seq.start(p_sequencer.esc_device_seqr_h[index]);
+ end
+ join_none
+ end
+ end
+ wait fork;
+ end
+ join
+ endtask
+
+ // alert_handler scb will compare the read value with expected value
+ // Not using "clear_all_interrupts" function in cip_base_vseq because of the signal interity
+ // error: after clearing intr_state, intr_state might come back to 1 in the next cycle.
+ virtual task check_alert_interrupts();
+ bit [TL_DW-1:0] intr;
+ // Wait until there is no ping handshake.
+ // This will avoid the case where interrupt is set and cleared at the same cycle.
+ `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0)
+ csr_rd(.ptr(ral.intr_state), .value(intr));
+ `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0)
+ csr_wr(.ptr(ral.intr_state), .value('1));
+ endtask
+
+ virtual task clear_esc();
+ csr_wr(.ptr(ral.classa_clr_shadowed), .value(1));
+ csr_wr(.ptr(ral.classb_clr_shadowed), .value(1));
+ csr_wr(.ptr(ral.classc_clr_shadowed), .value(1));
+ csr_wr(.ptr(ral.classd_clr_shadowed), .value(1));
+ endtask
+
+ // checking for csr_rd is done in scb
+ virtual task read_alert_cause();
+ bit [TL_DW-1:0] alert_cause;
+ foreach (ral.alert_cause[i]) begin
+ if ($urandom_range(0, 1)) begin
+ csr_rd(.ptr(ral.alert_cause[i]), .value(alert_cause));
+ end
+ end
+ foreach (ral.loc_alert_cause[i]) begin
+ if ($urandom_range(0, 1)) begin
+ csr_rd(.ptr(ral.loc_alert_cause[i]), .value(alert_cause));
+ end
+ end
+ endtask
+
+ virtual task read_esc_status();
+ bit [TL_DW-1:0] csr_val;
+ csr_rd(.ptr(ral.classa_accum_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classb_accum_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classc_accum_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classd_accum_cnt), .value(csr_val));
+
+ csr_rd(.ptr(ral.classa_state), .value(csr_val));
+ csr_rd(.ptr(ral.classb_state), .value(csr_val));
+ csr_rd(.ptr(ral.classc_state), .value(csr_val));
+ csr_rd(.ptr(ral.classd_state), .value(csr_val));
+
+ csr_rd(.ptr(ral.classa_esc_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classb_esc_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classc_esc_cnt), .value(csr_val));
+ csr_rd(.ptr(ral.classd_esc_cnt), .value(csr_val));
+ endtask
+
+ virtual task wait_alert_handshake_done();
+ cfg.clk_rst_vif.wait_clks(2);
+ foreach (cfg.alert_host_cfg[i]) begin
+ if (!cfg.alert_host_cfg[i].en_alert_lpg) cfg.alert_host_cfg[i].vif.wait_ack_complete();
+ end
+ endtask
+
+ virtual function bit check_esc_done(bit[TL_DW-1:0] vals[$]);
+ foreach (vals[i]) begin
+ esc_state_e val = esc_state_e'(vals[i]);
+ if (val inside {EscStatePhase0, EscStatePhase1, EscStatePhase2, EscStatePhase3}) return 0;
+ end
+ return 1;
+ endfunction
+
+ virtual task wait_esc_handshake_done();
+ bit [TL_DW-1:0] csr_vals[4];
+ do begin
+ csr_rd(.ptr(ral.classa_state), .value(csr_vals[0]));
+ csr_rd(.ptr(ral.classb_state), .value(csr_vals[1]));
+ csr_rd(.ptr(ral.classc_state), .value(csr_vals[2]));
+ csr_rd(.ptr(ral.classd_state), .value(csr_vals[3]));
+ end while (!check_esc_done(csr_vals));
+ // check if there is any esc ping
+ foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].vif.wait_esc_complete();
+ endtask
+
+ // This task wait until any alert or esc protocol received a ping from LFSR.
+ // This task will also return the protocol index:
+ // alert index starts from 1; esc index stats from NUM_ALERTS
+ virtual task wait_alert_esc_ping(ref int ping_index);
+ int ping_i;
+ fork
+ begin : isolation_fork
+ foreach (cfg.alert_host_cfg[i]) begin
+ automatic int index = i;
+ fork
+ begin
+ cfg.alert_host_cfg[index].vif.wait_alert_ping();
+ ping_i = index + 1;
+ end
+ join_none
+ end
+ foreach (cfg.esc_device_cfg[i]) begin
+ automatic int index = i;
+ fork
+ begin
+ cfg.esc_device_cfg[index].vif.wait_esc_ping();
+ ping_i = index + NUM_ALERTS + 1;
+ end
+ join_none
+ end
+ wait (ping_i > 0);
+ disable fork;
+ ping_index = ping_i;
+ end
+ join
+ endtask
+
+ function void enable_lpg_group(bit [NUM_ALERTS-1:0] alert_en_i);
+ foreach (alert_en_i[i]) begin
+ if (alert_en_i[i]) set_alert_lpg(i);
+ end
+ endfunction
+
+ // Enable alert's LPG based on alert_i input.
+ //
+ // Only enable this alert's LPG if the lgp input `lpg_cg_en` or `lpg_rst_en` if not Mubi4True.
+ // Because one LPG will turn off a set of alert sensers. So this task will also set all LPG's
+ // alert_host_cfgs' `en_alert_lpg` to 1.
+ virtual function void set_alert_lpg(int alert_i);
+ int lpg_i = alert_handler_reg_pkg::LpgMap[alert_i];
+ bit [1:0] set_lpg;
+
+ if (cfg.alert_handler_vif.get_lpg_status(lpg_i) == 0) begin
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(set_lpg, set_lpg > 0;);
+ if (set_lpg[0]) cfg.alert_handler_vif.set_lpg_cg_en(lpg_i);
+ if (set_lpg[1]) cfg.alert_handler_vif.set_lpg_rst_en(lpg_i);
+ foreach (alert_handler_reg_pkg::LpgMap[i]) begin
+ if (alert_handler_reg_pkg::LpgMap[i] == lpg_i) cfg.alert_host_cfg[i].en_alert_lpg = 1;
+ end
+ end
+ endfunction
+
+ virtual task alert_handler_crashdump_phases(bit [1:0] classa_phase = $urandom(),
+ bit [1:0] classb_phase = $urandom(),
+ bit [1:0] classc_phase = $urandom(),
+ bit [1:0] classd_phase = $urandom());
+ csr_wr(.ptr(ral.classa_crashdump_trigger_shadowed), .value(classa_phase));
+ csr_wr(.ptr(ral.classb_crashdump_trigger_shadowed), .value(classb_phase));
+ csr_wr(.ptr(ral.classc_crashdump_trigger_shadowed), .value(classc_phase));
+ csr_wr(.ptr(ral.classd_crashdump_trigger_shadowed), .value(classd_phase));
+ endtask
+
+ virtual task wr_phases_cycle(int max_phase_cyc);
+ `RAND_AND_WR_CLASS_PHASES_CYCLE(a);
+ `RAND_AND_WR_CLASS_PHASES_CYCLE(b);
+ `RAND_AND_WR_CLASS_PHASES_CYCLE(c);
+ `RAND_AND_WR_CLASS_PHASES_CYCLE(d);
+ endtask
+
+ virtual task wr_intr_timeout_cycle(bit[TL_DW-1:0] intr_timeout_cyc[NUM_ALERT_CLASSES]);
+ csr_wr(.ptr(ral.classa_timeout_cyc_shadowed), .value(intr_timeout_cyc[0]));
+ csr_wr(.ptr(ral.classb_timeout_cyc_shadowed), .value(intr_timeout_cyc[1]));
+ csr_wr(.ptr(ral.classc_timeout_cyc_shadowed), .value(intr_timeout_cyc[2]));
+ csr_wr(.ptr(ral.classd_timeout_cyc_shadowed), .value(intr_timeout_cyc[3]));
+ endtask
+
+ virtual task wr_class_accum_threshold(bit[TL_DW-1:0] accum_thresh[NUM_ALERT_CLASSES]);
+ csr_wr(.ptr(ral.classa_accum_thresh_shadowed), .value(accum_thresh[0]));
+ csr_wr(.ptr(ral.classb_accum_thresh_shadowed), .value(accum_thresh[1]));
+ csr_wr(.ptr(ral.classc_accum_thresh_shadowed), .value(accum_thresh[2]));
+ csr_wr(.ptr(ral.classd_accum_thresh_shadowed), .value(accum_thresh[3]));
+ endtask
+
+ virtual task wr_ping_timeout_cycle(bit[TL_DW-1:0] timeout_val);
+ csr_wr(.ptr(ral.ping_timeout_cyc_shadowed), .value(timeout_val));
+ if (`gmv(ral.ping_timer_regwen)) begin
+ if (timeout_val == 0) timeout_val = 1;
+ foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout_cycle = timeout_val;
+ foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].ping_timeout_cycle = timeout_val;
+ end
+ endtask
+
+ // This sequence will automatically response to all escalation ping and esc responses
+ virtual task run_esc_rsp_seq_nonblocking(bit [NUM_ESCS-1:0] esc_int_errs = '0,
+ bit [NUM_ESCS-1:0] ping_timeout_errs = '0);
+ foreach (cfg.esc_device_cfg[i]) begin
+ automatic int index = i;
+ fork
+ forever begin
+ bit esc_int_err = esc_int_errs[index] ? $urandom_range(0, 1) : 0;
+ bit ping_timeout_err = ping_timeout_errs[index] ? $urandom_range(0, 1) : 0;
+ esc_receiver_esc_rsp_seq esc_seq =
+ esc_receiver_esc_rsp_seq::type_id::create("esc_seq");
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == esc_int_err; standalone_int_err == 0;
+ ping_timeout == ping_timeout_err;)
+ esc_seq.start(p_sequencer.esc_device_seqr_h[index]);
+ end
+ join_none
+ end
+ endtask
+
+endclass : alert_handler_base_vseq
+
+`undef RAND_AND_WR_CLASS_PHASES_CYCLE
+`undef RAND_WRITE_CLASS_CTRL
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv
new file mode 100644
index 0000000..aab1078
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv
@@ -0,0 +1,160 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_common_vseq extends alert_handler_base_vseq;
+ `uvm_object_utils(alert_handler_common_vseq)
+
+ constraint num_trans_c {
+ num_trans inside {[1:2]};
+ }
+
+ `uvm_object_new
+
+ virtual task pre_start();
+ super.pre_start();
+ if (common_seq_type == "tl_intg_err") begin
+ // If `en_csr_vseq_w_tl_intg = 1`, this vseq will check tl intg error won't affect any other
+ // tl transaction.
+ // If `en_csr_vseq_w_tl_intg = 0`, this vseq will check status, interrupts, and class_count
+ // registers are updated correctly by DUT.
+ en_csr_vseq_w_tl_intg = $urandom_range(0, 1);
+ `uvm_info(`gfn, $sformatf("en_csr_vseq_w_tl_intg = %0b", en_csr_vseq_w_tl_intg), UVM_MEDIUM)
+ end
+ endtask
+
+ virtual task body();
+ // run alert/esc ping response sequences without error or timeout to prevent triggering local
+ // alert failure
+ run_esc_rsp_seq_nonblocking(0);
+ run_common_vseq_wrapper(num_trans);
+ endtask : body
+
+ // If the tl_intg_err sequence does not run csr_rw in parallel, enable loc_alert error and enable
+ // interrupts.
+ // If the tl_intg_err sequence runs with csr_rw, do not enable loc_alert because it might trigger
+ // escalation and affect register predications.
+ virtual task run_tl_intg_err_vseq_sub(string ral_name);
+ if (en_csr_vseq_w_tl_intg == 0) begin
+ csr_wr(.ptr(ral.loc_alert_en_shadowed[LocalBusIntgFail]),
+ .value($urandom_range(0, 1)),
+ .predict(1));
+ csr_wr(.ptr(ral.loc_alert_class_shadowed[LocalBusIntgFail]),
+ .value($urandom_range(0, 3)),
+ .predict(1));
+ csr_wr(.ptr(ral.classa_ctrl_shadowed.en), .value(1));
+ csr_wr(.ptr(ral.classb_ctrl_shadowed.en), .value(1));
+ csr_wr(.ptr(ral.classc_ctrl_shadowed.en), .value(1));
+ csr_wr(.ptr(ral.classd_ctrl_shadowed.en), .value(1));
+ end
+ super.run_tl_intg_err_vseq_sub(ral_name);
+ endtask
+
+ // Override the task to check corresponding CSR status is updated correctly.
+ virtual task check_tl_intg_error_response();
+ bit exp_val = `gmv(ral.loc_alert_en_shadowed[LocalBusIntgFail]);
+ csr_rd_check(.ptr(ral.loc_alert_cause[LocalBusIntgFail]), .compare_value(exp_val));
+
+ // Only check interrupt, accumlate count, and alert_cause registers if the local alert is
+ // enabled.
+ // However, this task does not check escalation port because the common escalation path is
+ // checked in other tests that enabled scb.
+ if (exp_val == 1) begin
+ bit [TL_DW-1:0] class_i = `gmv(ral.loc_alert_class_shadowed[LocalBusIntgFail]);
+ bit [TL_DW-1:0] accum_cnt;
+ csr_rd_check(.ptr(ral.intr_state), .compare_value(1'b1 << class_i));
+ case (class_i)
+ 0: csr_rd(.ptr(ral.classa_accum_cnt), .value(accum_cnt));
+ 1: csr_rd(.ptr(ral.classb_accum_cnt), .value(accum_cnt));
+ 2: csr_rd(.ptr(ral.classc_accum_cnt), .value(accum_cnt));
+ 3: csr_rd(.ptr(ral.classd_accum_cnt), .value(accum_cnt));
+ default: `uvm_fatal(`gfn, $sformatf("Invalid class index %0d", class_i))
+ endcase
+ // Once tl_intg_err triggered, the error will be set to 1 until reset, so the counter will
+ // continuously increment.
+ `DV_CHECK_LT(0, accum_cnt, "Accumulated count should be larger than 0");
+ end
+ endtask
+
+ // If the common sequence is tl integrity error sequence, we override this task to disable local
+ // alert for tl_intg_err and lock this register. Because tl_intg_err can trigger local alert and
+ // eventually triggers escalation. Then the auto predications for escalation related registers
+ // such as `class_clr` and `clr_regwen` registers are not correct.
+ virtual task run_csr_vseq(string csr_test_type,
+ int num_test_csrs = 0,
+ bit do_rand_wr_and_reset = 1,
+ dv_base_reg_block models[$] = {},
+ string ral_name = "");
+ if (common_seq_type == "tl_intg_err") begin
+ csr_wr(.ptr(ral.loc_alert_regwen[LocalBusIntgFail]), .value(0), .predict(1));
+ end
+ super.run_csr_vseq(csr_test_type, num_test_csrs, do_rand_wr_and_reset, models, ral_name);
+ endtask
+
+ virtual function void predict_shadow_reg_status(bit predict_update_err = 0,
+ bit predict_storage_err = 0);
+ if (predict_update_err) begin
+ foreach (cfg.shadow_update_err_status_fields[status_field]) begin
+ if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegUpdateErr])) begin
+ void'(status_field.predict(cfg.shadow_update_err_status_fields[status_field]));
+ end
+ end
+ end
+ if (predict_storage_err) begin
+ foreach (cfg.shadow_storage_err_status_fields[status_field]) begin
+ if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegStorageErr])) begin
+ void'(status_field.predict(cfg.shadow_storage_err_status_fields[status_field]));
+ end
+ end
+ end
+ endfunction
+
+ virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy);
+ if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin
+ bit val;
+ csr_rd(.ptr(ral.loc_alert_cause[LocalAlertPingFail]), .value(val));
+ `DV_CHECK_EQ(val, 1, "local alert ping fail mismatch")
+ csr_rd(.ptr(ral.loc_alert_cause[LocalEscPingFail]), .value(val));
+ `DV_CHECK_EQ(val, 1, "local escalation ping fail mismatch")
+ end else begin
+ foreach (cfg.esc_device_cfg[i]) begin
+ `DV_CHECK_EQ(cfg.esc_device_cfg[i].vif.esc_tx.esc_p, 1,
+ $sformatf("escalation protocol_%0d is not set", i));
+ end
+ end
+ // Let the simulation wait a few clock cycles before reset to make sure assertions are checked.
+ cfg.clk_rst_vif.wait_clks($urandom_range(2, 10));
+ endtask
+
+ virtual task sec_cm_inject_fault(sec_cm_base_if_proxy if_proxy);
+ if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin
+ // Enable ping timer to get ping counter error
+ csr_wr(ral.ping_timer_en_shadowed, 1);
+
+ // Enable loc_alerts
+ foreach (ral.loc_alert_en_shadowed[i]) csr_wr(ral.loc_alert_en_shadowed[i], 1);
+ end
+ super.sec_cm_inject_fault(if_proxy);
+ endtask : sec_cm_inject_fault
+
+ virtual task pre_run_sec_cm_fi_vseq();
+ // Disable prim_sparse_fsm assertions.
+ $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A");
+ $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A");
+ $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A");
+ $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A");
+
+ // Because the assertion contains `=>` statement.
+ // Wait one clock cycle until the assertions are fully disabled.
+ cfg.clk_rst_vif.wait_clks(1);
+ endtask : pre_run_sec_cm_fi_vseq
+
+ virtual task post_run_sec_cm_fi_vseq();
+ // Enable prim_sparse_fsm assertions.
+ $asserton(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A");
+ $asserton(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A");
+ $asserton(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A");
+ $asserton(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A");
+ endtask : post_run_sec_cm_fi_vseq
+
+endclass
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv
new file mode 100644
index 0000000..56e3e56
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv
@@ -0,0 +1,103 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This sequence uses a fixed setting to enable all alerts and locks them to class A.
+// Then enable all local alerts and locks them to class B.
+// Randomly force the `wait_cyc_mask_i` from design to a valid small number to fasten the ping
+// request mechanism.
+// Finally this sequence wait until alerts are pinged certain times.
+class alert_handler_entropy_stress_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_entropy_stress_vseq)
+
+ `uvm_object_new
+
+ rand bit [7:0] forced_mask_val;
+ rand int num_pings;
+
+ constraint valid_mask_val_c {
+ forced_mask_val >= 'h7;
+ $onehot(32'(forced_mask_val) + 1) == 1;
+ }
+
+ constraint num_pings_c {
+ if (forced_mask_val > 'hf0) {
+ num_pings inside {[1 : 2]};
+ } else {
+ num_pings inside {[1 : 3]};
+ }
+ }
+
+ virtual task pre_start();
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ cfg.alert_handler_vif.set_wait_cyc_mask(forced_mask_val);
+
+ foreach (cfg.alert_host_cfg[i]) begin
+ cfg.alert_host_cfg[i].alert_delay_max = 0;
+ cfg.alert_host_cfg[i].ping_delay_max = 0;
+ end
+ super.pre_start();
+ endtask
+
+ task body();
+ bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class;
+
+ foreach (loc_alert_class[i]) loc_alert_class[i] = 1;
+
+ `uvm_info(`gfn, "Test started", UVM_LOW)
+
+ run_esc_rsp_seq_nonblocking();
+
+ alert_handler_init(.intr_en('1), // Enable all interrupts
+ .alert_en('1), // Enable all alerts
+ .alert_class(0), // Set all alerts to class A
+ .loc_alert_en('1), // Enable all local alerts
+ .loc_alert_class(loc_alert_class)); // Set all local alerts to class B
+
+ // Enable all classes and lock them.
+ alert_handler_rand_wr_class_ctrl('1, '1);
+
+ // Enable ping timer.
+ csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(1));
+
+ // Lock alerts and configurations.
+ alert_handler_wr_regwen_regs(.regwen(0),
+ .alert_regwen(0),
+ .loc_alert_regwen(0),
+ .ping_timer_regwen(0),
+ .class_regwen(0));
+
+ // Wait for all alerts to be pinged at least once.
+ fork begin : isolation_fork
+ int num_alerts = NUM_ALERTS;
+ for (int i = 0; i < NUM_ALERTS; i++) begin
+ automatic int index = i;
+ fork begin
+ repeat (num_pings) cfg.alert_host_cfg[index].vif.wait_alert_ping();
+ num_alerts--;
+ `uvm_info(`gfn, $sformatf("alert %0d received %0d ping request.\n %0d alerts remaining.",
+ index, num_pings, num_alerts), UVM_LOW);
+ end join_none
+ end
+ wait fork;
+ end join
+
+ cfg.clk_rst_vif.wait_clks($urandom_range(50, 500));
+
+ // Check no error or local alerts triggered.
+ foreach (ral.alert_cause[i]) begin
+ csr_rd_check(.ptr(ral.alert_cause[i]), .compare_value(0));
+ end
+ foreach (ral.loc_alert_cause[i]) begin
+ csr_rd_check(.ptr(ral.loc_alert_cause[i]), .compare_value(0));
+ end
+
+ // Wait some random delays, then release the force signal, issue reset.
+ // This will allow the test to pass ok_to_end check from alert/esc_monitors and
+ // push_pull_agent.
+ cfg.clk_rst_vif.wait_clks($urandom_range(0, 5));
+ cfg.alert_handler_vif.release_wait_cyc_mask();
+ dut_init();
+ endtask
+
+endclass : alert_handler_entropy_stress_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv
new file mode 100644
index 0000000..6d333b9
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv
@@ -0,0 +1,41 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence enable entropy by writing 1 to the lock_regen register.
+
+class alert_handler_entropy_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_entropy_vseq)
+
+ `uvm_object_new
+
+ // large number of num_trans to make sure covers all alerts and escalation pings
+ constraint num_trans_c {
+ num_trans inside {[400:1000]};
+ }
+
+ // increase the possibility to enable more alerts, because alert_handler only sends ping on
+ // enabled alerts
+ constraint enable_one_alert_c {
+ alert_en dist {'1 :/ 9, [0:('1-1'b1)] :/ 1};
+ (~alert_regwen) dist {'1 :/ 9, [0:('1-1'b1)] :/ 1};
+ }
+
+ constraint sig_int_c {
+ esc_int_err == 0;
+ }
+
+ constraint lock_bit_c {
+ do_lock_config == 1;
+ }
+
+ constraint esc_accum_thresh_c {
+ foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};}
+ }
+
+ function void pre_randomize();
+ this.enable_classa_only_c.constraint_mode(0);
+ verbosity = UVM_HIGH;
+ endfunction
+
+endclass : alert_handler_entropy_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv
new file mode 100644
index 0000000..690ae56
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv
@@ -0,0 +1,34 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence triggers escalation by accumulating alerts in the same class.
+// difference from smoke test, this sequence set the threshold to larger numbers.
+
+class alert_handler_esc_alert_accum_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_esc_alert_accum_vseq)
+
+ `uvm_object_new
+
+ constraint disable_clr_esc_c {
+ do_clr_esc == 0;
+ }
+
+ constraint enable_alert_accum_esc_only_c {
+ do_esc_intr_timeout == 0; // disable interrupt timeout triggered escalation
+ }
+
+ constraint num_trans_c {
+ num_trans inside {[1:100]};
+ }
+
+ constraint esc_accum_thresh_c {
+ foreach (accum_thresh[i]) {accum_thresh[i] inside {[0:100]};}
+ }
+
+ function void pre_randomize();
+ this.enable_one_alert_c.constraint_mode(0);
+ this.enable_classa_only_c.constraint_mode(0);
+ endfunction
+
+endclass : alert_handler_esc_alert_accum_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv
new file mode 100644
index 0000000..3e054ec
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence triggers escalation by the interrupt timeout
+
+class alert_handler_esc_intr_timeout_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_esc_intr_timeout_vseq)
+
+ `uvm_object_new
+
+ constraint esc_due_to_intr_timeout_only_c {
+ foreach (accum_thresh[i]) {accum_thresh[i] > 1;} // prevent alert accumulation triggers esc
+ do_esc_intr_timeout == 1;
+ }
+
+ function void pre_randomize();
+ this.enable_one_alert_c.constraint_mode(0);
+ this.enable_classa_only_c.constraint_mode(0);
+ endfunction
+
+endclass : alert_handler_esc_intr_timeout_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv
new file mode 100644
index 0000000..2eff261
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This sequence check LPG by randomly turn off alert_handler's clock, and check if ping timer can
+// resume correctly without sending some spurious ping errors.
+class alert_handler_lpg_stub_clk_vseq extends alert_handler_lpg_vseq;
+ `uvm_object_utils(alert_handler_lpg_stub_clk_vseq)
+
+ `uvm_object_new
+
+ constraint loc_alert_en_c {
+ local_alert_en[LocalAlertPingFail] == 1;
+ local_alert_en[LocalEscPingFail] == 1;
+ }
+
+ constraint ping_fail_c {
+ alert_ping_timeout == 0;
+ esc_ping_timeout == 0;
+ }
+
+ task body();
+ fork begin : isolation_fork
+ trigger_non_blocking_seqs();
+ fork
+ rand_stub_clk();
+ run_smoke_seq();
+ join
+ disable fork; // disable non-blocking seqs for stress_all tests
+ end join
+ endtask : body
+
+ virtual task rand_stub_clk();
+ repeat($urandom_range(1, 5)) begin
+ int clk_stub_ps = cfg.clk_rst_vif.clk_period_ps * $urandom_range(2, 1_000);
+ cfg.clk_rst_vif.wait_clks($urandom_range(0, 100_000));
+ cfg.clk_rst_vif.stop_clk();
+ #((clk_stub_ps)*1ps);
+ cfg.clk_rst_vif.start_clk();
+ end
+ endtask
+
+endclass : alert_handler_lpg_stub_clk_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv
new file mode 100644
index 0000000..f78508b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_lpg_vseq extends alert_handler_entropy_vseq;
+ `uvm_object_utils(alert_handler_lpg_vseq)
+
+ `uvm_object_new
+
+ constraint sig_int_c {
+ alert_int_err == 0;
+ esc_int_err == 0;
+ esc_standalone_int_err == 0;
+ }
+
+ constraint loc_alert_en_c {
+ local_alert_en[LocalAlertPingFail] > 0;
+ }
+
+ constraint ping_fail_c {
+ alert_ping_timeout == alert_en;
+ esc_ping_timeout == 0;
+ }
+
+ // disable interrupt timeout
+ constraint esc_intr_timeout_c {
+ foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;}
+ }
+
+ function void pre_randomize();
+ this.enable_classa_only_c.constraint_mode(0);
+ this.enable_one_alert_c.constraint_mode(0);
+ verbosity = UVM_HIGH;
+ endfunction
+
+ task body();
+ fork
+ begin : isolation_fork
+ trigger_non_blocking_seqs();
+ fork
+ enable_lpg_group(alert_en);
+ run_smoke_seq();
+ join
+ disable fork; // disable non-blocking seqs for stress_all tests
+ end // end isolation_fork
+ join
+ endtask : body
+endclass : alert_handler_lpg_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
new file mode 100644
index 0000000..e23b8bd
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv
@@ -0,0 +1,79 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence test corner cases for alert or escalation pings:
+// 1). ping integrity fail or timeout
+// 2). ping interrupted by a reset signal
+// 3). escalation ping interrupted by real escalation signal (this could happen because escalation
+// ping and real escalation share the same esc_p/n signals)
+
+class alert_handler_ping_timeout_vseq extends alert_handler_entropy_vseq;
+ `uvm_object_utils(alert_handler_ping_timeout_vseq)
+
+ `uvm_object_new
+
+ constraint num_trans_c {
+ num_trans inside {[5:30]};
+ }
+
+ constraint alert_trigger_c {
+ alert_trigger == 0;
+ }
+
+ constraint intr_en_c {
+ intr_en == '1;
+ }
+
+ constraint sig_int_c {
+ alert_int_err == 0;
+ esc_int_err == 0;
+ esc_standalone_int_err == 0;
+ }
+
+ constraint loc_alert_en_c {
+ local_alert_en[LocalEscPingFail] == 1;
+ local_alert_en[LocalAlertPingFail] == 1;
+ }
+
+ constraint ping_fail_c {
+ alert_ping_timeout == '1;
+ esc_ping_timeout == '1;
+ }
+
+ // At least enable and lock `NUM_ALERTS-4` alerts to avoid this sequence running too long.
+ // This constraint also ensures at least one alert is locked and enabled so that we can ensure at
+ // least one alert ping will fire.
+ constraint enable_one_alert_c {
+ $countones(alert_en) dist {NUM_ALERTS :/ 8, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 2};
+ $countones(~alert_regwen) dist {NUM_ALERTS :/ 5, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 5};
+ (~alert_regwen) & alert_en > 0;
+ }
+
+ constraint ping_timeout_cyc_c {
+ ping_timeout_cyc inside {[1:MAX_PING_TIMEOUT_CYCLE]};
+ }
+
+ // disable interrupt timeout
+ constraint esc_intr_timeout_c {
+ foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;}
+ }
+
+ function void pre_randomize();
+ this.enable_classa_only_c.constraint_mode(0);
+ endfunction
+
+ // In this sequence, because we disable all external alerts, so to ensure local alerts are
+ // triggerd, we wait for interrupt pins to fire then wait for alert and escalation handshake
+ // to finish.
+ virtual task wait_alert_esc_done();
+ wait (cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]);
+ // Wait two clock cycles to avoid building a cycle-accurate scb.
+ cfg.clk_rst_vif.wait_clks(2);
+ `uvm_info(`gfn, $sformatf("Interrupt pin = %0h", cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]),
+ UVM_LOW)
+ check_alert_interrupts();
+ super.wait_alert_esc_done();
+ endtask
+
+endclass : alert_handler_ping_timeout_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv
new file mode 100644
index 0000000..2e12865
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence enable random alert inputs, and rand wr phase cycles
+
+class alert_handler_random_alerts_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_random_alerts_vseq)
+
+ `uvm_object_new
+
+ constraint esc_accum_thresh_c {
+ foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:5] :/ 5};}
+ }
+
+ function void pre_randomize();
+ this.enable_one_alert_c.constraint_mode(0);
+ endfunction
+
+endclass : alert_handler_random_alerts_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv
new file mode 100644
index 0000000..8f58bf9
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence enable random classes, and rand wr phase cycles
+
+class alert_handler_random_classes_vseq extends alert_handler_random_alerts_vseq;
+ `uvm_object_utils(alert_handler_random_classes_vseq)
+
+ `uvm_object_new
+
+ function void pre_randomize();
+ super.pre_randomize();
+ this.enable_classa_only_c.constraint_mode(0);
+ endfunction
+
+endclass : alert_handler_random_classes_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv
new file mode 100644
index 0000000..a37ae09
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// this sequence enable signal intergrity fail.
+
+class alert_handler_sig_int_fail_vseq extends alert_handler_smoke_vseq;
+ `uvm_object_utils(alert_handler_sig_int_fail_vseq)
+
+ `uvm_object_new
+
+ constraint esc_accum_thresh_c {
+ foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};}
+ }
+
+ function void pre_randomize();
+ this.enable_one_alert_c.constraint_mode(0);
+ this.enable_classa_only_c.constraint_mode(0);
+ this.sig_int_c.constraint_mode(0);
+ endfunction
+
+endclass : alert_handler_sig_int_fail_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
new file mode 100644
index 0000000..98ea46f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv
@@ -0,0 +1,221 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// basic smoke test vseq
+class alert_handler_smoke_vseq extends alert_handler_base_vseq;
+ `uvm_object_utils(alert_handler_smoke_vseq)
+
+ `uvm_object_new
+
+ rand bit [NUM_ALERT_CLASSES-1:0] intr_en;
+ rand bit [NUM_ALERT_CLASSES-1:0] clr_regwen;
+ rand bit [NUM_ALERT_CLASSES-1:0] class_regwen;
+ rand bit [NUM_ALERT_CLASSES-1:0] clr_en;
+ rand bit [NUM_ALERT_CLASSES-1:0] lock_bit_en;
+ rand bit [NUM_ALERT_CLASSES-1:0] class_en;
+ rand bit [NUM_ALERTS-1:0] alert_regwen;
+ rand bit [NUM_ALERTS-1:0] alert_trigger;
+ rand bit [NUM_ALERTS-1:0] alert_int_err;
+ rand bit [NUM_ALERTS-1:0] alert_en;
+ rand bit [NUM_ALERTS-1:0] alert_ping_timeout;
+ rand bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class_map;
+ rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_regwen;
+ rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_en;
+ rand bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] local_alert_class_map;
+ rand bit [NUM_ESCS-1:0] esc_int_err;
+ rand bit [NUM_ESCS-1:0] esc_standalone_int_err;
+ rand bit [NUM_ESCS-1:0] esc_ping_timeout;
+
+ rand bit ping_timer_regwen;
+ rand bit do_clr_esc;
+ rand bit do_wr_phases_cyc;
+ rand bit do_esc_intr_timeout;
+ rand bit do_lock_config;
+ rand bit [TL_DW-1:0] ping_timeout_cyc;
+ rand bit [TL_DW-1:0] max_phase_cyc;
+ rand bit [TL_DW-1:0] intr_timeout_cyc [NUM_ALERT_CLASSES];
+ rand bit [TL_DW-1:0] accum_thresh [NUM_ALERT_CLASSES];
+
+ int max_wait_phases_cyc = MIN_CYCLE_PER_PHASE * NUM_ESC_PHASES;
+ int max_intr_timeout_cyc;
+
+ uvm_verbosity verbosity = UVM_LOW;
+
+ constraint lock_bit_c {
+ do_lock_config dist {1 := 1, 0 := 49};
+ }
+
+ constraint clr_and_lock_en_c {
+ lock_bit_en dist {0 :/ 6, [1:'b1111] :/ 4};
+ }
+
+ constraint regwen_c {
+ clr_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6};
+ class_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6};
+ alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6};
+ local_alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6};
+ ping_timer_regwen dist { 0 :/ 4 , 1 :/ 6};
+ }
+
+ constraint enable_one_alert_c {
+ $onehot(alert_en);
+ }
+
+ constraint max_phase_cyc_c {
+ max_phase_cyc inside {[0:1_000]};
+ }
+
+ // Set min to 120 cycles to avoid alert ping timeout due to random delay.
+ // The max delay after ping request is 10 cycles plus 2 cycles async delay.
+ // Also the alert_sender and alert_handlers are in different clock domains, with a max 10 times
+ // difference in clock frequency.
+ constraint ping_timeout_cyc_c {
+ ping_timeout_cyc inside {[120:MAX_PING_TIMEOUT_CYCLE]};
+ }
+
+ constraint enable_classa_only_c {
+ alert_class_map == 0; // all the alerts assign to classa
+ local_alert_class_map == 0; // all local alerts assign to classa
+ class_en dist {1 :/ 8, 0 :/ 1, [2:'1-1'b1] :/ 1};
+ }
+
+ // constraint to trigger escalation
+ constraint esc_accum_thresh_c {
+ foreach (accum_thresh[i]) {soft accum_thresh[i] inside {[0:1]};}
+ }
+
+ constraint esc_intr_timeout_c {
+ foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] inside {[1:1_000]};}
+ }
+
+ constraint sig_int_c {
+ alert_int_err == 0;
+ esc_int_err == 0;
+ esc_standalone_int_err == 0;
+ }
+
+ constraint ping_fail_c {
+ alert_ping_timeout == 0;
+ esc_ping_timeout == 0;
+ }
+
+ task pre_start();
+ super.pre_start();
+ // This is the input for a nonblocking sequence. The value won't be changed until the
+ // nonblockings sequence end.
+ esc_ping_timeout.rand_mode(0);
+ esc_int_err.rand_mode(0);
+ endtask
+
+ task body();
+ fork
+ begin : isolation_fork
+ trigger_non_blocking_seqs();
+ run_smoke_seq();
+ disable fork; // disable non-blocking seqs for stress_all tests
+ end // end fork
+ join
+ endtask : body
+
+ virtual task trigger_non_blocking_seqs();
+ `uvm_info(`gfn, $sformatf("esc_int_err %0h esc_ping_timeout %0h",
+ esc_int_err, esc_ping_timeout), UVM_LOW);
+ run_esc_rsp_seq_nonblocking(esc_int_err, esc_ping_timeout);
+ endtask
+
+ virtual task run_smoke_seq();
+ `uvm_info(`gfn, $sformatf("num_trans=%0d", num_trans), UVM_LOW)
+ if (verbosity != UVM_LOW) begin
+ `uvm_info(`gfn,
+ $sformatf("Config: intr_en=%0b, alert=%0b, alert_en=%0b, loc_alert_en=%0b",
+ intr_en, alert_trigger, alert_en, local_alert_en), UVM_LOW)
+ end
+
+ for (int i = 1; i <= num_trans; i++) begin
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+
+ // Assign ping timeout value to each alert agent.
+ foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout = alert_ping_timeout[i];
+
+ `uvm_info(`gfn, $sformatf(
+ "start seq %0d/%0d: intr_en=0x%0h, alert=0x%0h, alert_en=0x%0h, loc_alert_en=0x%0h",
+ i, num_trans, intr_en, alert_trigger, alert_en, local_alert_en), verbosity)
+
+ // write initial settings (enable and mapping csrs)
+ alert_handler_init(.intr_en(intr_en),
+ .alert_en(alert_en),
+ .alert_class(alert_class_map),
+ .loc_alert_en(local_alert_en),
+ .loc_alert_class(local_alert_class_map));
+
+ // write class_ctrl
+ alert_handler_rand_wr_class_ctrl(lock_bit_en, class_en);
+
+ // randomize crashdump triggered phases
+ alert_handler_crashdump_phases();
+
+ // randomly write phase cycle registers
+ // always set phase_cycle for the first iteration, in order to pass stress_all test
+ if (do_wr_phases_cyc || i == 1) wr_phases_cycle(max_phase_cyc);
+
+ // randomly write interrupt timeout resigers and accumulative threshold registers
+ if (do_esc_intr_timeout) wr_intr_timeout_cycle(intr_timeout_cyc);
+ wr_class_accum_threshold(accum_thresh);
+ wr_ping_timeout_cycle(ping_timeout_cyc);
+
+ // when all configuration registers are set, write lock register
+ lock_config(do_lock_config);
+
+ // once all above configs are written, lock them with regwen
+ alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen,
+ class_regwen);
+
+ // if config is not locked, update max_intr_timeout and max_wait_phases cycles
+ if (!config_locked) begin
+ bit [TL_DW-1:0] max_intr_timeout_cyc;
+ bit [TL_DW-1:0] max_q[$] = intr_timeout_cyc.max();
+ max_intr_timeout_cyc = max_q[0];
+ max_wait_phases_cyc = max2(max_wait_phases_cyc, max_phase_cyc * NUM_ESC_PHASES);
+ if (do_lock_config) config_locked = 1;
+ end
+
+ // drive esc standalone responses and alerts
+ if (esc_standalone_int_err) drive_esc_rsp(esc_standalone_int_err);
+ drive_alert(alert_trigger, alert_int_err);
+
+ if (do_esc_intr_timeout) begin
+ cfg.clk_rst_vif.wait_clks(max_intr_timeout_cyc);
+ // this task checks three sets of registers related to alert/esc status:
+ // alert_accum_cnt, esc_cnt, class_state
+ read_esc_status();
+ end
+ // only check interrupt when no esc_int_err, otherwise clear interrupt might happen the
+ // same cycle as interrupt triggered by esc_int_err
+ if ((esc_int_err == 0) && (esc_ping_timeout == 0)) check_alert_interrupts();
+
+ // if ping timeout enabled, wait for ping timeout done before checking escalation phases
+ if ((esc_int_err | alert_ping_timeout) > 0) begin
+ cfg.clk_rst_vif.wait_clks(MAX_PING_TIMEOUT_CYCLE);
+ end
+
+ // wait escalation done, and random interrupt with clear_esc
+ wait_alert_esc_done();
+
+ read_alert_cause();
+ read_esc_status();
+ if (do_clr_esc) clear_esc();
+ check_alert_interrupts();
+ end
+ endtask
+
+ virtual task wait_alert_esc_done();
+ wait_alert_handshake_done();
+ if ($urandom_range(0, 1) && (esc_int_err == 0)) begin
+ cfg.clk_rst_vif.wait_clks($urandom_range(0, max_wait_phases_cyc));
+ clear_esc();
+ end
+ wait_esc_handshake_done();
+ endtask
+
+endclass : alert_handler_smoke_vseq
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv
new file mode 100644
index 0000000..f962108
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv
@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// combine all alert_handler seqs (except below seqs) in one seq to run sequentially
+// 1. csr seq, which requires scb to be disabled
+class alert_handler_stress_all_vseq extends alert_handler_base_vseq;
+ `uvm_object_utils(alert_handler_stress_all_vseq)
+
+ `uvm_object_new
+
+ task body();
+ bit entropy_test_flag; // this flag ensures entropy test only runs once due to its long runtime
+ string seq_names[] = {"alert_handler_smoke_vseq",
+ "alert_handler_random_alerts_vseq",
+ "alert_handler_random_classes_vseq",
+ "alert_handler_esc_intr_timeout_vseq",
+ "alert_handler_esc_alert_accum_vseq",
+ "alert_handler_sig_int_fail_vseq",
+ "alert_handler_entropy_vseq"};
+ for (int i = 1; i <= num_trans; i++) begin
+ uvm_sequence seq;
+ alert_handler_base_vseq alert_vseq;
+ uint seq_idx = entropy_test_flag ? $urandom_range(0, seq_names.size - 2) :
+ $urandom_range(0, seq_names.size - 1);
+ if (seq_names[seq_idx] == "alert_handler_entropy_vseq") entropy_test_flag = 1;
+
+ seq = create_seq_by_name(seq_names[seq_idx]);
+ `downcast(alert_vseq, seq)
+
+ // if upper seq disables do_apply_reset for this seq, then can't issue reset
+ // as upper seq may drive reset
+ if (do_apply_reset) begin
+ alert_vseq.do_apply_reset = $urandom_range(0, 1);
+ // config_locked will be set unless reset is issued
+ alert_vseq.config_locked = alert_vseq.do_apply_reset ? 0 : config_locked;
+ end else begin
+ alert_vseq.do_apply_reset = 0;
+ alert_vseq.config_locked = config_locked;
+ end
+
+ alert_vseq.set_sequencer(p_sequencer);
+ `DV_CHECK_RANDOMIZE_FATAL(alert_vseq)
+ if (seq_names[seq_idx] == "alert_common_vseq") begin
+ alert_handler_common_vseq common_vseq;
+ `downcast(common_vseq, alert_vseq);
+ common_vseq.common_seq_type = "intr_test";
+ end
+
+ alert_vseq.start(p_sequencer);
+ config_locked = alert_vseq.config_locked;
+ end
+ endtask : body
+
+endclass
+
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv
new file mode 100644
index 0000000..0cb38df
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv
@@ -0,0 +1,19 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "alert_handler_base_vseq.sv"
+`include "alert_handler_smoke_vseq.sv"
+`include "alert_handler_common_vseq.sv"
+`include "alert_handler_random_alerts_vseq.sv"
+`include "alert_handler_random_classes_vseq.sv"
+`include "alert_handler_esc_intr_timeout_vseq.sv"
+`include "alert_handler_esc_alert_accum_vseq.sv"
+`include "alert_handler_sig_int_fail_vseq.sv"
+`include "alert_handler_entropy_vseq.sv"
+`include "alert_handler_ping_timeout_vseq.sv"
+`include "alert_handler_lpg_vseq.sv"
+`include "alert_handler_lpg_stub_clk_vseq.sv"
+`include "alert_handler_entropy_stress_vseq.sv"
+`include "alert_handler_stress_all_vseq.sv"
+`include "alert_handler_alert_accum_saturation_vseq.sv"
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv
new file mode 100644
index 0000000..f084fad
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv
@@ -0,0 +1,23 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module alert_handler_bind;
+
+ bind alert_handler tlul_assert #(
+ .EndpointType("Device")
+ ) tlul_assert_device (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+ bind alert_handler alert_handler_csr_assert_fpv alert_handler_csr_assert (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core b/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core
new file mode 100644
index 0000000..b165a4b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core
@@ -0,0 +1,38 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler_sva:0.1
+description: "ALERT_HANDLER assertion modules and bind file."
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:tlul:headers
+ - lowrisc:fpv:csr_assert_gen
+ files:
+ - alert_handler_bind.sv
+ file_type: systemVerilogSource
+
+ files_formal:
+ depend:
+ - lowrisc:opentitan:top_sencha_alert_handler:0.1
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../../data/alert_handler.hjson
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
+ generate:
+ - csr_assert_gen
+
+ formal:
+ <<: *default_target
+ filesets:
+ - files_formal
+ - files_dv
+ toplevel: alert_handler
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core b/hw/top_sencha/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core
new file mode 100644
index 0000000..edd71ff
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core
@@ -0,0 +1,18 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:alert_handler_tb:0.1"
+description: "ALERT_HANDLER UVM TB environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:alert_handler_test:0.1
+ files:
+ - tb.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/tb/tb.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/tb/tb.sv
new file mode 100644
index 0000000..2687b98
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/tb/tb.sv
@@ -0,0 +1,115 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module tb;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_utils_pkg::*;
+ import alert_handler_env_pkg::*;
+ import alert_handler_test_pkg::*;
+ import alert_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ wire clk, rst_n, rst_shadowed_n;
+ wire devmode;
+ wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
+ wire [NUM_MAX_ESC_SEV-1:0] esc_en;
+ wire [NUM_CRASHDUMP-1:0] crashdump;
+
+ // interfaces
+ clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
+ rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n));
+ pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts);
+ pins_if #(NUM_CRASHDUMP) crashdump_if(crashdump);
+ pins_if #(1) devmode_if(devmode);
+ tl_if tl_if(.clk(clk), .rst_n(rst_n));
+ alert_handler_if alert_handler_if(.clk(clk), .rst_n(rst_n));
+ alert_esc_if esc_device_if [NUM_ESCS](.clk(clk), .rst_n(rst_n));
+ alert_esc_if alert_host_if [NUM_ALERTS](.clk(clk), .rst_n(rst_n));
+ alert_esc_probe_if probe_if[NUM_ESCS](.clk(clk), .rst_n(rst_n));
+
+ // dut signals
+ prim_alert_pkg::alert_rx_t [NUM_ALERTS-1:0] alert_rx;
+ prim_alert_pkg::alert_tx_t [NUM_ALERTS-1:0] alert_tx;
+
+ prim_esc_pkg::esc_rx_t [NUM_ESCS-1:0] esc_rx;
+ prim_esc_pkg::esc_tx_t [NUM_ESCS-1:0] esc_tx;
+
+ for (genvar k = 0; k < NUM_ALERTS; k++) begin : gen_alert_if
+ assign alert_tx[k].alert_p = alert_host_if[k].alert_tx.alert_p;
+ assign alert_tx[k].alert_n = alert_host_if[k].alert_tx.alert_n;
+ assign alert_host_if[k].alert_rx.ack_p = alert_rx[k].ack_p;
+ assign alert_host_if[k].alert_rx.ack_n = alert_rx[k].ack_n;
+ assign alert_host_if[k].alert_rx.ping_p = alert_rx[k].ping_p;
+ assign alert_host_if[k].alert_rx.ping_n = alert_rx[k].ping_n;
+ assign alert_handler_if.alert_ping_reqs[k] = dut.gen_alerts[k].u_alert_receiver.ping_req_i;
+ initial begin
+ uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.alert_host_agent[%0d]", k),
+ "vif", alert_host_if[k]);
+ end
+ end
+
+
+ for (genvar k = 0; k < NUM_ESCS; k++) begin : gen_esc_if
+ assign esc_rx[k].resp_p = esc_device_if[k].esc_rx.resp_p;
+ assign esc_rx[k].resp_n = esc_device_if[k].esc_rx.resp_n;
+ assign esc_device_if[k].esc_tx.esc_p = esc_tx[k].esc_p;
+ assign esc_device_if[k].esc_tx.esc_n = esc_tx[k].esc_n;
+ assign probe_if[k].esc_en = dut.esc_sig_req[k];
+ assign alert_handler_if.esc_ping_reqs[k] = dut.gen_esc_sev[k].u_esc_sender.ping_req_i;
+ initial begin
+ uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.esc_device_agent[%0d]", k),
+ "vif", esc_device_if[k]);
+ uvm_config_db#(virtual alert_esc_probe_if)::set(null,
+ $sformatf("*.env.esc_device_agent[%0d]", k), "probe_vif", probe_if[k]);
+ end
+ end
+
+ // edn_clk, edn_rst_n and edn_if are defined and driven in below macro
+ `DV_EDN_IF_CONNECT
+
+ // main dut
+ alert_handler dut (
+ .clk_i ( clk ),
+ .rst_ni ( rst_n ),
+ .rst_shadowed_ni ( rst_shadowed_n),
+ .clk_edn_i ( edn_clk ),
+ .rst_edn_ni ( edn_rst_n ),
+ .tl_i ( tl_if.h2d ),
+ .tl_o ( tl_if.d2h ),
+ .intr_classa_o ( interrupts[0] ),
+ .intr_classb_o ( interrupts[1] ),
+ .intr_classc_o ( interrupts[2] ),
+ .intr_classd_o ( interrupts[3] ),
+ .lpg_cg_en_i ( alert_handler_if.lpg_cg_en ),
+ .lpg_rst_en_i ( alert_handler_if.lpg_rst_en ),
+ .crashdump_o ( crashdump ),
+ .edn_o ( edn_if[0].req ),
+ .edn_i ( {edn_if[0].ack, edn_if[0].d_data} ),
+ .alert_rx_o ( alert_rx ),
+ .alert_tx_i ( alert_tx ),
+ .esc_rx_i ( esc_rx ),
+ .esc_tx_o ( esc_tx )
+ );
+
+ initial begin
+ // drive clk and rst_n from clk_if
+ clk_rst_if.set_active();
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif",
+ rst_shadowed_if);
+ uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
+ uvm_config_db#(crashdump_vif)::set(null, "*.env", "crashdump_vif", crashdump_if);
+ uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
+ uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
+ uvm_config_db#(virtual alert_handler_if)::set(null, "*.env", "alert_handler_vif",
+ alert_handler_if);
+ $timeformat(-12, 0, " ps", 12);
+ run_test();
+ end
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv
new file mode 100644
index 0000000..ff8d256
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv
@@ -0,0 +1,21 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class alert_handler_base_test extends cip_base_test #(
+ .ENV_T(alert_handler_env),
+ .CFG_T(alert_handler_env_cfg)
+ );
+
+ `uvm_component_utils(alert_handler_base_test)
+ `uvm_component_new
+
+ // the base class dv_base_test creates the following instances:
+ // alert_handler_env_cfg: cfg
+ // alert_handler_env: env
+
+ // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
+ // the run_phase; as such, nothing more needs to be done
+
+endclass : alert_handler_base_test
+
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test.core b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test.core
new file mode 100644
index 0000000..06a3f50
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:alert_handler_test:0.1"
+description: "ALERT_HANDLER DV UVM test"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:alert_handler_env
+ files:
+ - alert_handler_test_pkg.sv
+ - alert_handler_base_test.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv
new file mode 100644
index 0000000..c3f6d76
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package alert_handler_test_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import cip_base_pkg::*;
+ import alert_handler_env_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // local types
+
+ // functions
+
+ // package sources
+ `include "alert_handler_base_test.sv"
+
+endpackage
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core
new file mode 100644
index 0000000..6264f52
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core
@@ -0,0 +1,31 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler_esc_timer_fpv:0.1
+description: "alert_handler_esc_timer FPV target"
+filesets:
+ files_formal:
+ depend:
+ - lowrisc:prim:all
+ - lowrisc:opentitan:top_sencha_alert_handler
+ files:
+ - vip/alert_handler_esc_timer_assert_fpv.sv
+ - tb/alert_handler_esc_timer_bind_fpv.sv
+ - tb/alert_handler_esc_timer_tb.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ # note, this setting is just used
+ # to generate a file list for jg
+ default_tool: icarus
+ filesets:
+ - files_formal
+ toplevel: alert_handler_esc_timer_tb
+
+ formal:
+ <<: *default_target
+
+ lint:
+ <<: *default_target
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core
new file mode 100644
index 0000000..2f0cd19
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core
@@ -0,0 +1,31 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_alert_handler_ping_timer_fpv:0.1
+description: "ALERT_HANDLER FPV target"
+filesets:
+ files_formal:
+ depend:
+ - lowrisc:prim:all
+ - lowrisc:opentitan:top_sencha_alert_handler
+ files:
+ - vip/alert_handler_ping_timer_assert_fpv.sv
+ - tb/alert_handler_ping_timer_bind_fpv.sv
+ - tb/alert_handler_ping_timer_tb.sv
+ file_type: systemVerilogSource
+
+targets:
+ default: &default_target
+ # note, this setting is just used
+ # to generate a file list for jg
+ default_tool: icarus
+ filesets:
+ - files_formal
+ toplevel: alert_handler_ping_timer_tb
+
+ formal:
+ <<: *default_target
+
+ lint:
+ <<: *default_target
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv
new file mode 100644
index 0000000..8837855
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+module alert_handler_esc_timer_bind_fpv;
+
+
+ bind alert_handler_esc_timer
+ alert_handler_esc_timer_assert_fpv i_alert_handler_esc_timer_assert_fpv (
+ .clk_i,
+ .rst_ni,
+ .en_i,
+ .clr_i,
+ .accu_trig_i,
+ .accu_fail_i,
+ .timeout_en_i,
+ .timeout_cyc_i,
+ .esc_en_i,
+ .esc_map_i,
+ .phase_cyc_i,
+ .crashdump_phase_i,
+ .latch_crashdump_o,
+ .esc_trig_o,
+ .esc_cnt_o,
+ .esc_sig_req_o,
+ .esc_state_o
+ );
+
+
+endmodule : alert_handler_esc_timer_bind_fpv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
new file mode 100644
index 0000000..25b641f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
@@ -0,0 +1,49 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Testbench module for alert_handler_esc_timer.
+// Intended to be used with a formal tool.
+
+module alert_handler_esc_timer_tb import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input en_i,
+ input clr_i,
+ input accu_trig_i,
+ input accu_fail_i,
+ input timeout_en_i,
+ input [EscCntDw-1:0] timeout_cyc_i,
+ input [N_ESC_SEV-1:0] esc_en_i,
+ input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i,
+ input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i,
+ input [PHASE_DW-1:0] crashdump_phase_i,
+ output logic latch_crashdump_o,
+ output logic esc_trig_o,
+ output logic[EscCntDw-1:0] esc_cnt_o,
+ output logic[N_ESC_SEV-1:0] esc_sig_req_o,
+ output cstate_e esc_state_o
+);
+
+ alert_handler_esc_timer i_alert_handler_esc_timer (
+ .clk_i,
+ .rst_ni,
+ .en_i,
+ .clr_i,
+ .accu_trig_i,
+ .accu_fail_i,
+ .timeout_en_i,
+ .timeout_cyc_i,
+ .esc_en_i,
+ .esc_map_i,
+ .phase_cyc_i,
+ .crashdump_phase_i,
+ .latch_crashdump_o,
+ .esc_trig_o,
+ .esc_cnt_o,
+ .esc_sig_req_o,
+ .esc_state_o
+ );
+
+
+endmodule : alert_handler_esc_timer_tb
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv
new file mode 100644
index 0000000..78ecf33
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv
@@ -0,0 +1,29 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+module alert_handler_ping_timer_bind_fpv;
+
+
+ bind alert_handler_ping_timer
+ alert_handler_ping_timer_assert_fpv i_alert_handler_ping_timer_assert_fpv (
+ .clk_i,
+ .rst_ni,
+ .edn_req_o,
+ .edn_ack_i,
+ .edn_data_i,
+ .en_i,
+ .alert_ping_en_i,
+ .ping_timeout_cyc_i,
+ .wait_cyc_mask_i,
+ .alert_ping_req_o,
+ .esc_ping_req_o,
+ .alert_ping_ok_i,
+ .esc_ping_ok_i,
+ .alert_ping_fail_o,
+ .esc_ping_fail_o
+ );
+
+
+endmodule : alert_handler_ping_timer_bind_fpv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
new file mode 100644
index 0000000..2b85385
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Testbench module for ping timer in alert handler. Intended to use with
+// a formal tool.
+
+module alert_handler_ping_timer_tb import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ output logic edn_req_o,
+ input edn_ack_i,
+ input [LfsrWidth-1:0] edn_data_i,
+ input en_i,
+ input [NAlerts-1:0] alert_ping_en_i,
+ input [PING_CNT_DW-1:0] ping_timeout_cyc_i,
+ input [PING_CNT_DW-1:0] wait_cyc_mask_i,
+ output logic [NAlerts-1:0] alert_ping_req_o,
+ output logic [N_ESC_SEV-1:0] esc_ping_req_o,
+ input [NAlerts-1:0] alert_ping_ok_i,
+ input [N_ESC_SEV-1:0] esc_ping_ok_i,
+ output logic alert_ping_fail_o,
+ output logic esc_ping_fail_o
+);
+
+ alert_handler_ping_timer #(
+ // disable max length check in FPV, otherwise this
+ // will not converge within acceptable compute time
+ .MaxLenSVA ( 1'b0 )
+ ) i_alert_handler_ping_timer (
+ .clk_i ,
+ .rst_ni ,
+ .edn_req_o ,
+ .edn_ack_i ,
+ .edn_data_i ,
+ .en_i ,
+ .alert_ping_en_i ,
+ .ping_timeout_cyc_i,
+ .wait_cyc_mask_i ,
+ .alert_ping_req_o ,
+ .esc_ping_req_o ,
+ .alert_ping_ok_i ,
+ .esc_ping_ok_i ,
+ .alert_ping_fail_o ,
+ .esc_ping_fail_o
+ );
+
+endmodule : alert_handler_ping_timer_tb
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv
new file mode 100644
index 0000000..8a85ebb
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv
@@ -0,0 +1,150 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Assertions for alert_handler_esc_timer.
+// Intended to be used with a formal tool.
+
+`include "prim_assert.sv"
+
+module alert_handler_esc_timer_assert_fpv import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input en_i,
+ input clr_i,
+ input accu_trig_i,
+ input accu_fail_i,
+ input timeout_en_i,
+ input [EscCntDw-1:0] timeout_cyc_i,
+ input [N_ESC_SEV-1:0] esc_en_i,
+ input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i,
+ input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i,
+ input [PHASE_DW-1:0] crashdump_phase_i,
+ input logic latch_crashdump_o,
+ input logic esc_trig_o,
+ input logic[EscCntDw-1:0] esc_cnt_o,
+ input logic[N_ESC_SEV-1:0] esc_sig_req_o,
+ input cstate_e esc_state_o
+);
+
+ ///////////////////////////////
+ // Declarations & Parameters //
+ ///////////////////////////////
+
+ // constrain the state-spaces
+ localparam int unsigned MAX_TIMEOUT_CYCLES = 10;
+ localparam int unsigned MAX_PHASE_CYCLES = 10;
+
+ // symbolic vars for phase map check
+ logic [1:0] esc_sel;
+ logic [1:0] phase_sel;
+ localparam cstate_e Phases [4] = {Phase0, Phase1, Phase2, Phase3};
+
+ // set regs
+ logic esc_has_triggered_q;
+
+
+ /////////////////
+ // Assumptions //
+ /////////////////
+
+ `ASSUME(TimeoutCycles_M, timeout_cyc_i < MAX_TIMEOUT_CYCLES)
+ `ASSUME(TimeoutCyclesConst_M, ##1 $stable(timeout_cyc_i))
+
+ `ASSUME(PhaseCycles_M, phase_cyc_i < MAX_PHASE_CYCLES)
+ `ASSUME(PhaseCyclesConst_M, ##1 $stable(phase_cyc_i))
+
+ `ASSUME(CrashdumpPhaseConst_M, ##1 $stable(crashdump_phase_i))
+
+ `ASSUME(EscSelConst_M, ##1 $stable(esc_sel))
+ `ASSUME(PhaseSelConst_M, ##1 $stable(phase_sel))
+
+ ////////////////////////
+ // Forward Assertions //
+ ////////////////////////
+
+ // if the class is not enabled and we are in IDLE state,
+ // neither of the two escalation mechanisms shall fire
+ `ASSERT(ClassDisabledNoEscTrig_A, esc_state_o == Idle && !en_i |-> !esc_trig_o)
+ `ASSERT(ClassDisabledNoEsc_A, esc_state_o == Idle && !en_i && !alert_handler_esc_timer.fsm_error
+ |-> !esc_sig_req_o)
+ `ASSERT(EscDisabledNoEsc_A, !esc_en_i[esc_sel] && !alert_handler_esc_timer.fsm_error |->
+ !esc_sig_req_o[esc_sel])
+
+ // if timeout counter is enabled due to a pending interrupt, check escalation
+ // assume accumulation trigger is not asserted during this sequence
+ `ASSERT(TimeoutEscTrig_A, esc_state_o == Idle ##1 en_i && $rose(timeout_en_i) &&
+ (timeout_cyc_i > 0) ##1 timeout_en_i [*MAX_TIMEOUT_CYCLES] |=> esc_has_triggered_q,
+ clk_i, !rst_ni || accu_trig_i || clr_i || accu_fail_i)
+
+ // check whether an accum trig leads to escalation if enabled
+ `ASSERT(AccumEscTrig_A, ##1 en_i && accu_trig_i && esc_state_o inside {Idle, Timeout} |=>
+ esc_has_triggered_q, clk_i, !rst_ni || clr_i || accu_fail_i)
+
+ // check escalation cnt and state out
+ parameter logic [alert_handler_esc_timer.StateWidth-1:0] StateEncodings [8] = '{
+ alert_handler_esc_timer.IdleSt,
+ alert_handler_esc_timer.TimeoutSt,
+ alert_handler_esc_timer.FsmErrorSt,
+ alert_handler_esc_timer.TerminalSt,
+ alert_handler_esc_timer.Phase0St,
+ alert_handler_esc_timer.Phase1St,
+ alert_handler_esc_timer.Phase2St,
+ alert_handler_esc_timer.Phase3St
+ };
+ `ASSERT(EscStateOut_A, alert_handler_esc_timer.state_q == StateEncodings[esc_state_o])
+ `ASSERT(EscCntOut_A, alert_handler_esc_timer.u_prim_count.cnt_q[0] == esc_cnt_o)
+
+ // check clr input
+ // we cannot use clr to exit from the timeout state
+ `ASSERT(ClrCheck_A, clr_i && !(esc_state_o inside {Idle, Timeout, FsmError}) && !accu_fail_i |=>
+ esc_state_o == Idle)
+
+ // check escalation map
+ `ASSERT(PhaseEscMap_A, esc_state_o == Phases[phase_sel] && esc_map_i[esc_sel] == phase_sel &&
+ esc_en_i[esc_sel] |-> esc_sig_req_o[esc_sel])
+
+ // check terminal state is reached eventually if triggered and not cleared
+ `ASSERT(TerminalState_A, esc_trig_o |-> strong(##[1:$] esc_state_o == Terminal),
+ clk_i, !rst_ni || clr_i || accu_fail_i)
+
+ // check that the crashdump capture trigger is asserted correctly
+ `ASSERT(CrashdumpTrigger_A,
+ ##1 $changed(esc_state_o) &&
+ esc_state_o == cstate_e'(4 + crashdump_phase_i)
+ <->
+ $past(latch_crashdump_o), esc_state_o == FsmError)
+
+ /////////////////////////
+ // Backward Assertions //
+ /////////////////////////
+
+ // escalation can only be triggered when in Idle or Timeout state. Trigger mechanisms are either
+ // the accumulation trigger or a timeout trigger
+ `ASSERT(EscTrigBkwd_A, esc_trig_o |-> esc_state_o inside {Idle, Timeout} && accu_trig_i ||
+ esc_state_o == Timeout && esc_cnt_o >= timeout_cyc_i)
+ `ASSERT(NoEscTrigBkwd_A, !esc_trig_o |-> !(esc_state_o inside {Idle, Timeout}) ||
+ !en_i || !accu_trig_i || !timeout_en_i || clr_i)
+
+ // escalation signals can only be asserted in the escalation phase states, or
+ // if we are in the terminal FsmError state
+ `ASSERT(EscBkwd_A, esc_sig_req_o[esc_sel] |-> esc_en_i[esc_sel] &&
+ esc_has_triggered_q || alert_handler_esc_timer.fsm_error)
+ `ASSERT(NoEscBkwd_A, !esc_sig_req_o[esc_sel] |-> !esc_en_i[esc_sel] ||
+ esc_state_o != Phases[esc_map_i[esc_sel]] && esc_state_o != FsmError,
+ clk_i, !rst_ni || clr_i)
+
+ //////////////////////
+ // Helper Processes //
+ //////////////////////
+
+ // set registers
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
+ if (!rst_ni) begin
+ esc_has_triggered_q <= 1'b0;
+ end else begin
+ esc_has_triggered_q <= esc_has_triggered_q & ~clr_i | esc_trig_o;
+ end
+ end
+
+endmodule : alert_handler_esc_timer_assert_fpv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv b/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv
new file mode 100644
index 0000000..9bb7de4
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv
@@ -0,0 +1,132 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Assertions for ping timer in alert handler. Intended to use with
+// a formal tool.
+
+`include "prim_assert.sv"
+
+module alert_handler_ping_timer_assert_fpv import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input edn_req_o,
+ input edn_ack_i,
+ input [LfsrWidth-1:0] edn_data_i,
+ input en_i,
+ input [NAlerts-1:0] alert_ping_en_i,
+ input [PING_CNT_DW-1:0] ping_timeout_cyc_i,
+ input [PING_CNT_DW-1:0] wait_cyc_mask_i,
+ input [NAlerts-1:0] alert_ping_req_o,
+ input [N_ESC_SEV-1:0] esc_ping_req_o,
+ input [NAlerts-1:0] alert_ping_ok_i,
+ input [N_ESC_SEV-1:0] esc_ping_ok_i,
+ input alert_ping_fail_o,
+ input esc_ping_fail_o
+);
+
+ localparam int unsigned PingEnDw = N_ESC_SEV + NAlerts;
+ logic [PingEnDw-1:0] ping_en_vector, ping_en_mask, ping_ok_vector;
+
+ assign ping_en_vector = {esc_ping_req_o, alert_ping_req_o};
+ assign ping_en_mask = {N_ESC_SEV'('1), alert_ping_en_i};
+ assign ping_ok_vector = {esc_ping_ok_i, alert_ping_ok_i};
+
+ /////////////////
+ // Assumptions //
+ /////////////////
+
+ localparam int MaxWaitCntDw = 3;
+
+ // symbolic variables. we want to assess all valid indices
+ logic [$clog2(PingEnDw)-1:0] ping_en_sel;
+ logic [$clog2(N_ESC_SEV)-1:0] esc_idx;
+ `ASSUME_FPV(PingEnSelRange_M, ping_en_sel < PingEnDw)
+ `ASSUME_FPV(PingEnSelStable_M, ##1 $stable(ping_en_sel))
+ `ASSUME_FPV(EscIdxRange_M, esc_idx < N_ESC_SEV)
+ `ASSUME_FPV(EscIdxStable_M, ##1 $stable(esc_idx))
+ // assume that the alert enable configuration is locked once en_i is high
+ // this is ensured by the CSR regfile on the outside
+ `ASSUME_FPV(ConfigLocked0_M, en_i |-> $stable(alert_ping_en_i))
+ `ASSUME_FPV(ConfigLocked1_M, en_i |-> $stable(ping_timeout_cyc_i))
+ // enable stays high forever, once it has been asserted
+ `ASSUME(ConfigLocked2_M, en_i |=> en_i)
+ // reduce state space by reducing length of wait period
+ `ASSUME_FPV(WaitPeriod0_M, wait_cyc_mask_i == {MaxWaitCntDw{1'b1}})
+ `ASSUME_FPV(WaitPeriod1_M, ping_timeout_cyc_i <= {MaxWaitCntDw{1'b1}})
+
+ ////////////////////////
+ // Forward Assertions //
+ ////////////////////////
+
+ // no pings on disabled alerts
+ `ASSERT(DisabledNoAlertPings_A, ((~alert_ping_en_i) & alert_ping_req_o) == 0)
+ // no pings when not enabled
+ `ASSERT(NoPingsWhenDisabled0_A, !en_i |-> !alert_ping_req_o)
+ `ASSERT(NoPingsWhenDisabled1_A, !en_i |-> !esc_ping_req_o)
+ `ASSERT(NoPingsWhenDisabled2_A, en_i && !ping_en_mask[ping_en_sel] |->
+ !ping_en_vector[ping_en_sel])
+
+ // spurious pings (i.e. pings that where not requested)
+ // on alert channels
+ `ASSERT(SpuriousPingsDetected0_A, en_i && !ping_en_vector[ping_en_sel] &&
+ ping_ok_vector[ping_en_sel] && ping_en_sel < NAlerts |->
+ alert_ping_fail_o)
+ // on escalation channels
+ `ASSERT(SpuriousPingsDetected1_A, en_i && !ping_en_vector[ping_en_sel] &&
+ ping_ok_vector[ping_en_sel] && ping_en_sel >= NAlerts |->
+ esc_ping_fail_o)
+ // response must be one hot
+ `ASSERT(SpuriousPingsDetected2_A, en_i && !$onehot0(ping_ok_vector) |->
+ esc_ping_fail_o || alert_ping_fail_o)
+
+ // ensure that the number of cycles between pings on a specific escalation channel
+ // are within bounds. we try to prove this property with a margin of 2x here, whereas
+ // the ping receivers actually work with a margin of 4x to stay on the safe side.
+ localparam int MarginFactor = 2;
+ localparam int NumWaitCounts = 2;
+ localparam int NumTimeoutCounts = 2;
+ localparam int PingPeriodBound = MarginFactor * // margin to apply
+ N_ESC_SEV * // number of escalation channels to ping
+ (NumWaitCounts + // 1 alert and 1 esc wait count
+ NumTimeoutCounts) * // 1 alert and 1 esc timeout count
+ 2**MaxWaitCntDw; // maximum counter value
+
+ `ASSERT(EscalationPingPeriodWithinBounds_A,
+ $rose(esc_ping_req_o[esc_idx])
+ |->
+ ##[1 : PingPeriodBound]
+ $rose(esc_ping_req_o[esc_idx]))
+
+ /////////////////////////
+ // Backward Assertions //
+ /////////////////////////
+
+ // no pings when not enabled
+ `ASSERT(NoPingsWhenDisabledBkwd0_A, alert_ping_req_o |-> en_i)
+ `ASSERT(NoPingsWhenDisabledBkwd1_A, esc_ping_req_o |-> en_i)
+
+ // spurious pings (i.e. pings that where not requested)
+ // on alert channels
+ `ASSERT(SpuriousPingsDetectedBkwd0_A, !alert_ping_fail_o |->
+ !en_i || ping_en_vector[ping_en_sel] ||
+ !ping_ok_vector[ping_en_sel] || ping_en_sel >= NAlerts)
+ // on escalation channels
+ `ASSERT(SpuriousPingsDetectedBkwd1_A, !esc_ping_fail_o |->
+ !en_i || ping_en_vector[ping_en_sel] ||
+ !ping_ok_vector[ping_en_sel] || ping_en_sel < NAlerts)
+ // response must be one hot
+ `ASSERT(SpuriousPingsDetectedBkwd2_A, !esc_ping_fail_o && !alert_ping_fail_o |->
+ !en_i || $onehot0(ping_ok_vector))
+
+ //////////////////////////////////////////////////////////
+ // Currently not Tested in FPV due to large state space //
+ //////////////////////////////////////////////////////////
+
+ // 1) if an alert is enabled, it should be pinged eventually
+ // when entropy input is disabled
+ // 2) ping ok within timeout -> ok
+ // 3) ping ok after timeout -> alert
+ // 4) no ping response -> alert
+
+endmodule : alert_handler_ping_timer_assert_fpv
diff --git a/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.vlt b/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.vlt
new file mode 100644
index 0000000..0e2406e
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.vlt
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`verilator_config
+
+// Tell the Verilator scheduler to split up hw2reg_wrap into separate fields
+// when scheduling processes. This structure is used (among other things) to
+// communicate between alert_handler_accu and alert_handler_esc_timer instances
+// and tracking it as one big blob causes spurious apparent circular
+// dependencies.
+split_var -module "alert_handler" -var "hw2reg_wrap"
diff --git a/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.waiver b/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.waiver
new file mode 100644
index 0000000..457e158
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/lint/alert_handler.waiver
@@ -0,0 +1,44 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for alert handler
+
+waive -rules ENUM_RANGE -location {alert_handler_esc_timer.sv} -regexp {state_q} \
+ -comment "State is used to index timeout cycle counts"
+
+waive -rules NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \
+ -comment "Upper bits of permuted array are not read"
+
+waive -rules HIER_NET_NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \
+ -comment "Upper bits of permuted array are not read"
+
+waive -rules HIER_NET_NOT_READ -location {alert_handler.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \
+ -comment "Register interface doesn't use upper address and param, user filed"
+
+waive -rules INSIDE_OP_CONTEXT -location {prim_esc_sender.sv} -regexp {inside} \
+ -comment "Inside operator is used within SVA"
+
+waive -rules CASE_INC -location {alert_handler_esc_timer.sv} -regexp {'b010} \
+ -comment "Not all case tags are required."
+
+waive -rules CASE_INC -location {alert_handler_ping_timer.sv} -regexp {'b11} \
+ -comment "Not all case tags are required."
+
+waive -rules CASE_INC -location {prim_esc_sender.sv} -regexp {'b111} \
+ -comment "Not all case tags are required."
+
+waive -rules ONE_BIT_VEC -location {prim_lfsr.sv} -regexp {InDw - 1:0} \
+ -comment "Data input may be one bit wide."
+
+waive -rules VAR_INDEX -location {alert_handler_esc_timer.sv} -regexp {phase_cyc_i\[phase_idx\]} \
+ -comment "This indexing expression is correct."
+
+waive -rules VAR_INDEX -location {alert_handler_ping_timer.sv} -regexp {enable_mask\[id_to_ping\]} \
+ -comment "This indexing expression is correct."
+
+waive -rules CLOCK_USE -location {alert_handler_lpg_ctrl.sv} -msg {'clk_i' is connected to 'prim_lc_sync' port 'clk_i', and used as} \
+ -comment "This clock connection is only used for assertions internal to the prim module."
+
+waive -rules RESET_USE -location {alert_handler_lpg_ctrl.sv} -msg {'rst_ni' is connected to 'prim_lc_sync' port 'rst_ni', and used as} \
+ -comment "This reset connection is only used for assertions internal to the prim module."
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler.sv
new file mode 100644
index 0000000..96ca04d
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler.sv
@@ -0,0 +1,334 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Alert handler top
+
+`include "prim_assert.sv"
+
+module alert_handler
+ import alert_pkg::*;
+ import prim_alert_pkg::*;
+ import prim_esc_pkg::*;
+#(
+ // Compile time random constants, to be overriden by topgen.
+ parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
+) (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+ input clk_edn_i,
+ input rst_edn_ni,
+ // Bus Interface (device)
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // Interrupt Requests
+ output logic intr_classa_o,
+ output logic intr_classb_o,
+ output logic intr_classc_o,
+ output logic intr_classd_o,
+ // Clock gating and reset info from rstmgr and clkmgr
+ // SEC_CM: LPG.INTERSIG.MUBI
+ input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i,
+ input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i,
+ // State information for HW crashdump
+ output alert_crashdump_t crashdump_o,
+ // Entropy Input
+ output edn_pkg::edn_req_t edn_o,
+ input edn_pkg::edn_rsp_t edn_i,
+ // Alert Sources
+ // SEC_CM: ALERT.INTERSIG.DIFF
+ input alert_tx_t [NAlerts-1:0] alert_tx_i,
+ output alert_rx_t [NAlerts-1:0] alert_rx_o,
+ // Escalation outputs
+ // SEC_CM: ESC.INTERSIG.DIFF
+ input esc_rx_t [N_ESC_SEV-1:0] esc_rx_i,
+ output esc_tx_t [N_ESC_SEV-1:0] esc_tx_o
+);
+
+ //////////////////////////////////
+ // Regfile Breakout and Mapping //
+ //////////////////////////////////
+
+ logic [N_CLASSES-1:0] latch_crashdump;
+ logic [N_LOC_ALERT-1:0] loc_alert_trig;
+ logic [N_CLASSES-1:0] irq;
+ hw2reg_wrap_t hw2reg_wrap;
+ reg2hw_wrap_t reg2hw_wrap;
+
+ assign {intr_classd_o,
+ intr_classc_o,
+ intr_classb_o,
+ intr_classa_o} = irq;
+
+ // SEC_CM: CONFIG.SHADOW
+ // SEC_CM: PING_TIMER.CONFIG.REGWEN
+ // SEC_CM: ALERT.CONFIG.REGWEN
+ // SEC_CM: ALERT_LOC.CONFIG.REGWEN
+ // SEC_CM: CLASS.CONFIG.REGWEN
+ alert_handler_reg_wrap u_reg_wrap (
+ .clk_i,
+ .rst_ni,
+ .rst_shadowed_ni,
+ .tl_i,
+ .tl_o,
+ .irq_o ( irq ),
+ .latch_crashdump_i ( latch_crashdump ),
+ .crashdump_o,
+ .hw2reg_wrap,
+ .reg2hw_wrap,
+ // SEC_CM: BUS.INTEGRITY
+ .fatal_integ_alert_o(loc_alert_trig[4])
+ );
+
+ // SEC_CM: CONFIG.SHADOW
+ assign loc_alert_trig[5] = reg2hw_wrap.shadowed_err_update;
+ assign loc_alert_trig[6] = reg2hw_wrap.shadowed_err_storage;
+
+ ////////////////
+ // Ping Timer //
+ ////////////////
+
+ logic [NAlerts-1:0] alert_ping_req;
+ logic [NAlerts-1:0] alert_ping_ok;
+ logic [N_ESC_SEV-1:0] esc_ping_req;
+ logic [N_ESC_SEV-1:0] esc_ping_ok;
+
+ logic edn_req, edn_ack;
+ logic [LfsrWidth-1:0] edn_data;
+
+ prim_edn_req #(
+ .OutWidth(LfsrWidth)
+ ) u_edn_req (
+ // Alert handler side
+ .clk_i,
+ .rst_ni,
+ .req_chk_i ( 1'b1 ),
+ .req_i ( edn_req ),
+ .ack_o ( edn_ack ),
+ .data_o ( edn_data ),
+ .fips_o ( ),
+ .err_o ( ),
+ // EDN side
+ .clk_edn_i,
+ .rst_edn_ni,
+ .edn_o ( edn_o ),
+ .edn_i ( edn_i )
+ );
+
+ alert_handler_ping_timer #(
+ .RndCnstLfsrSeed(RndCnstLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstLfsrPerm)
+ ) u_ping_timer (
+ .clk_i,
+ .rst_ni,
+ .edn_req_o ( edn_req ),
+ .edn_ack_i ( edn_ack ),
+ .edn_data_i ( edn_data ),
+ .en_i ( reg2hw_wrap.ping_enable ),
+ .alert_ping_en_i ( reg2hw_wrap.alert_ping_en ),
+ .ping_timeout_cyc_i ( reg2hw_wrap.ping_timeout_cyc ),
+ // set this to the maximum width in the design.
+ // can be overridden in DV and FPV to shorten the wait periods.
+ // note however that this needs to be a right-aligned mask.
+ // also, do not set this to a value lower than 0x7.
+ .wait_cyc_mask_i ( {PING_CNT_DW{1'b1}} ),
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
+ .alert_ping_req_o ( alert_ping_req ),
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
+ .esc_ping_req_o ( esc_ping_req ),
+ .alert_ping_ok_i ( alert_ping_ok ),
+ .esc_ping_ok_i ( esc_ping_ok ),
+ .alert_ping_fail_o ( loc_alert_trig[0] ),
+ .esc_ping_fail_o ( loc_alert_trig[1] )
+ );
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerEscCnterCheck_A,
+ u_ping_timer.u_prim_count_esc_cnt,
+ loc_alert_trig[0] & loc_alert_trig[1],
+ (reg2hw_wrap.ping_enable == 0))
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerCnterCheck_A,
+ u_ping_timer.u_prim_count_cnt,
+ loc_alert_trig[0] & loc_alert_trig[1],
+ (reg2hw_wrap.ping_enable == 0))
+ `ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(PingTimerDoubleLfsrCheck_A,
+ u_ping_timer.u_prim_double_lfsr,
+ loc_alert_trig[0] & loc_alert_trig[1],
+ (reg2hw_wrap.ping_enable == 0))
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(PingTimerFsmCheck_A,
+ u_ping_timer.u_state_regs,
+ loc_alert_trig[0] & loc_alert_trig[1],
+ (reg2hw_wrap.ping_enable == 0))
+
+ /////////////////////////////
+ // Low-power group control //
+ /////////////////////////////
+
+ prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig;
+ alert_handler_lpg_ctrl u_alert_handler_lpg_ctrl (
+ .clk_i,
+ .rst_ni,
+ // SEC_CM: LPG.INTERSIG.MUBI
+ .lpg_cg_en_i,
+ .lpg_rst_en_i,
+ .alert_init_trig_o ( alert_init_trig )
+ );
+
+ /////////////////////
+ // Alert Receivers //
+ /////////////////////
+
+ logic [NAlerts-1:0] alert_integfail;
+ logic [NAlerts-1:0] alert_trig;
+
+ // Target interrupt notification
+ for (genvar k = 0 ; k < NAlerts ; k++) begin : gen_alerts
+ prim_alert_receiver #(
+ .AsyncOn(AsyncOn[k])
+ ) u_alert_receiver (
+ .clk_i,
+ .rst_ni,
+ .init_trig_i ( alert_init_trig[k] ),
+ .ping_req_i ( alert_ping_req[k] ),
+ .ping_ok_o ( alert_ping_ok[k] ),
+ .integ_fail_o ( alert_integfail[k] ),
+ .alert_o ( alert_trig[k] ),
+ // SEC_CM: ALERT.INTERSIG.DIFF
+ .alert_rx_o ( alert_rx_o[k] ),
+ .alert_tx_i ( alert_tx_i[k] )
+ );
+ end
+
+ assign loc_alert_trig[2] = |(reg2hw_wrap.alert_en & alert_integfail);
+
+ ///////////////////////////////////////
+ // Set alert cause bits and classify //
+ ///////////////////////////////////////
+
+ alert_handler_class u_class (
+ .alert_trig_i ( alert_trig ),
+ .loc_alert_trig_i ( loc_alert_trig ),
+ .alert_en_i ( reg2hw_wrap.alert_en ),
+ .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ),
+ .alert_class_i ( reg2hw_wrap.alert_class ),
+ .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ),
+ .alert_cause_o ( hw2reg_wrap.alert_cause ),
+ .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ),
+ .class_trig_o ( hw2reg_wrap.class_trig )
+ );
+
+ ////////////////////////////////////
+ // Escalation Handling of Classes //
+ ////////////////////////////////////
+
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_req;
+
+ for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes
+ logic class_accu_fail, class_accu_trig;
+ alert_handler_accu u_accu (
+ .clk_i,
+ .rst_ni,
+ .class_en_i ( reg2hw_wrap.class_en[k] ),
+ .clr_i ( reg2hw_wrap.class_clr[k] ),
+ .class_trig_i ( hw2reg_wrap.class_trig[k] ),
+ .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ),
+ .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ),
+ .accu_trig_o ( class_accu_trig ),
+ .accu_fail_o ( class_accu_fail )
+ );
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(AccuCnterCheck_A,
+ u_accu.u_prim_count,
+ esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p)
+
+ alert_handler_esc_timer u_esc_timer (
+ .clk_i,
+ .rst_ni,
+ .en_i ( reg2hw_wrap.class_en[k] ),
+ // this clear does not apply to interrupts
+ .clr_i ( reg2hw_wrap.class_clr[k] ),
+ // an interrupt enables the timeout
+ .timeout_en_i ( irq[k] ),
+ .accu_trig_i ( class_accu_trig ),
+ .accu_fail_i ( class_accu_fail ),
+ .timeout_cyc_i ( reg2hw_wrap.class_timeout_cyc[k] ),
+ .esc_en_i ( reg2hw_wrap.class_esc_en[k] ),
+ .esc_map_i ( reg2hw_wrap.class_esc_map[k] ),
+ .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ),
+ .crashdump_phase_i ( reg2hw_wrap.class_crashdump_phase[k] ),
+ .latch_crashdump_o ( latch_crashdump[k] ),
+ .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ),
+ .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ),
+ .esc_state_o ( hw2reg_wrap.class_esc_state[k] ),
+ .esc_sig_req_o ( class_esc_sig_req[k] )
+ );
+
+ `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(EscTimerCnterCheck_A,
+ u_esc_timer.u_prim_count,
+ esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p)
+ `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(EscTimerFsmCheck_A,
+ u_esc_timer.u_state_regs,
+ esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p)
+ end
+
+ ////////////////////////
+ // Escalation Senders //
+ ////////////////////////
+
+ logic [N_ESC_SEV-1:0] esc_sig_req;
+ logic [N_ESC_SEV-1:0] esc_integfail;
+ logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_req_trsp;
+
+ for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev
+ for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp
+ assign esc_sig_req_trsp[k][j] = class_esc_sig_req[j][k];
+ end
+
+ assign esc_sig_req[k] = |esc_sig_req_trsp[k];
+ // SEC_CM: ESC_RX.INTERSIG.BKGN_CHK
+ // Note: This countermeasure is actually implemented on the receiver side. We currently cannot
+ // put this RTL label inside that module due to the way our countermeasure annotation check
+ // script discovers the RTL files. The label is thus put here. Please refer to
+ // prim_esc_receiver.sv for the actual implementation of this mechanism.
+ prim_esc_sender u_esc_sender (
+ .clk_i,
+ .rst_ni,
+ .ping_req_i ( esc_ping_req[k] ),
+ .ping_ok_o ( esc_ping_ok[k] ),
+ .integ_fail_o ( esc_integfail[k] ),
+ .esc_req_i ( esc_sig_req[k] ),
+ // SEC_CM: ESC.INTERSIG.DIFF
+ .esc_rx_i ( esc_rx_i[k] ),
+ .esc_tx_o ( esc_tx_o[k] )
+ );
+ end
+
+ assign loc_alert_trig[3] = |esc_integfail;
+
+ ////////////////
+ // Assertions //
+ ////////////////
+
+ // check whether all outputs have a good known state after reset
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(IrqAKnownO_A, intr_classa_o)
+ `ASSERT_KNOWN(IrqBKnownO_A, intr_classb_o)
+ `ASSERT_KNOWN(IrqCKnownO_A, intr_classc_o)
+ `ASSERT_KNOWN(IrqDKnownO_A, intr_classd_o)
+ `ASSERT_KNOWN(CrashdumpKnownO_A, crashdump_o)
+ `ASSERT_KNOWN(AckPKnownO_A, alert_rx_o)
+ `ASSERT_KNOWN(EscPKnownO_A, esc_tx_o)
+ `ASSERT_KNOWN(EdnKnownO_A, edn_o)
+
+ // this restriction is due to specifics in the ping selection mechanism
+ `ASSERT_INIT(CheckNAlerts, NAlerts < (256 - N_CLASSES))
+ `ASSERT_INIT(CheckEscCntDw, EscCntDw <= 32)
+ `ASSERT_INIT(CheckAccuCntDw, AccuCntDw <= 32)
+ `ASSERT_INIT(CheckNClasses, N_CLASSES <= 8)
+ `ASSERT_INIT(CheckNEscSev, N_ESC_SEV <= 8)
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehotCheck_A,
+ u_reg_wrap.u_reg, loc_alert_trig[4])
+endmodule
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_accu.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_accu.sv
new file mode 100644
index 0000000..fc581d8
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_accu.sv
@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module accumulates incoming alert triggers. Once the current accumulator
+// value is greater or equal the accumulator threshold, the next occurence of
+// class_trig_i will trigger escalation.
+//
+// Note that the accumulator is implemented using a saturation counter which
+// does not wrap around.
+//
+
+`include "prim_assert.sv"
+
+module alert_handler_accu import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input class_en_i, // class enable
+ input clr_i, // clear the accumulator
+ input class_trig_i, // increments the accu
+ input [AccuCntDw-1:0] thresh_i, // escalation trigger threshold
+ output logic [AccuCntDw-1:0] accu_cnt_o, // output of current accu value
+ output logic accu_trig_o, // escalation trigger output
+ output logic accu_fail_o // asserted if the tandem accu counters are not equal
+);
+
+ logic trig_gated, accu_en;
+ assign trig_gated = class_trig_i & class_en_i;
+ assign accu_en = trig_gated && !(&accu_cnt_o);
+
+ // SEC_CM: ACCU.CTR.REDUN
+ // We employ two redundant counters to guard against FI attacks.
+ // If any of the two is glitched and the two counter states do not agree,
+ // the check_fail_o signal is asserted which will move the corresponding escalation
+ // FSM into a terminal error state where all escalation actions will be permanently asserted.
+ prim_count #(
+ .Width(AccuCntDw),
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler.
+ .EnableAlertTriggerSVA(0)
+ ) u_prim_count (
+ .clk_i,
+ .rst_ni,
+ .clr_i,
+ .set_i(1'b0),
+ .set_cnt_i('0),
+ .incr_en_i(accu_en),
+ .decr_en_i(1'b0),
+ .step_i(AccuCntDw'(1)),
+ .cnt_o(accu_cnt_o),
+ .cnt_next_o(),
+ .err_o(accu_fail_o)
+ );
+
+ assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
+
+ ////////////////
+ // Assertions //
+ ////////////////
+
+ `ASSERT(DisabledNoTrigFwd_A, !class_en_i |-> !accu_trig_o)
+ `ASSERT(DisabledNoTrigBkwd_A, accu_trig_o |-> class_en_i)
+ `ASSERT(CountSaturateStable_A, accu_cnt_o == {AccuCntDw{1'b1}} |=> $stable(accu_cnt_o))
+endmodule : alert_handler_accu
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_class.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_class.sv
new file mode 100644
index 0000000..79af26b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_class.sv
@@ -0,0 +1,49 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module gates the alert triggers with their enable bits, and correctly bins
+// the enabled alerts into the class that they have been assigned to. The module
+// produces the alert cause and class trigger signals.
+//
+
+module alert_handler_class import alert_pkg::*; (
+ input [NAlerts-1:0] alert_trig_i, // alert trigger
+ input [N_LOC_ALERT-1:0] loc_alert_trig_i, // alert trigger
+ input [NAlerts-1:0] alert_en_i, // alert enable
+ input [N_LOC_ALERT-1:0] loc_alert_en_i, // alert enable
+ input [NAlerts-1:0] [CLASS_DW-1:0] alert_class_i, // class assignment
+ input [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class_i, // class assignment
+
+ output logic [NAlerts-1:0] alert_cause_o, // alert cause
+ output logic [N_LOC_ALERT-1:0] loc_alert_cause_o, // alert cause
+ output logic [N_CLASSES-1:0] class_trig_o // class triggered
+);
+
+ // assign alert cause
+ assign alert_cause_o = alert_en_i & alert_trig_i;
+ assign loc_alert_cause_o = loc_alert_en_i & loc_alert_trig_i;
+
+ // classification mapping
+ logic [N_CLASSES-1:0][NAlerts-1:0] class_masks;
+ logic [N_CLASSES-1:0][N_LOC_ALERT-1:0] loc_class_masks;
+
+ // this is basically an address to onehot0 decoder
+ always_comb begin : p_class_mask
+ class_masks = '0;
+ loc_class_masks = '0;
+ for (int unsigned kk = 0; kk < NAlerts; kk++) begin
+ class_masks[alert_class_i[kk]][kk] = 1'b1;
+ end
+ for (int unsigned kk = 0; kk < N_LOC_ALERT; kk++) begin
+ loc_class_masks[loc_alert_class_i[kk]][kk] = 1'b1;
+ end
+ end
+
+ // mask and OR reduction, followed by class enable gating
+ for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classifier
+ assign class_trig_o[k] = (|{ alert_cause_o & class_masks[k],
+ loc_alert_cause_o & loc_class_masks[k] });
+ end
+
+endmodule : alert_handler_class
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv
new file mode 100644
index 0000000..3147fd2
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv
@@ -0,0 +1,411 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module implements the escalation timer, which times the four escalation
+// phases. There are two mechanisms that can trigger the escalation protocol:
+//
+// 1) via accum_trigger_i, which will be asserted once the accumulator value
+// exceeds a programmable amount of alert occurences.
+//
+// 2) via an interrupt timeout, if this is enabled. If this functionality is
+// enabled, the internal escalation counter is reused to check whether the
+// interrupt times out. If it does time out, the outcome is the same as if
+// accum_trigger_i where asserted.
+//
+// Note that escalation always takes precedence over the interrupt timeout.
+//
+
+`include "prim_assert.sv"
+
+module alert_handler_esc_timer import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input en_i, // enables timeout/escalation
+ input clr_i, // aborts escalation
+ input accu_trig_i, // this triggers escalation
+ input accu_fail_i, // this moves the FSM into a terminal error state
+ input timeout_en_i, // enables timeout
+ input [EscCntDw-1:0] timeout_cyc_i, // interrupt timeout. 0 = disabled
+ input [N_ESC_SEV-1:0] esc_en_i, // escalation signal enables
+ input [N_ESC_SEV-1:0]
+ [PHASE_DW-1:0] esc_map_i, // escalation signal / phase map
+ input [N_PHASES-1:0]
+ [EscCntDw-1:0] phase_cyc_i, // cycle counts of individual phases
+ input [PHASE_DW-1:0] crashdump_phase_i, // determines when to assert latch_crashdump_o
+ output logic latch_crashdump_o, // asserted when entering escalation
+ output logic esc_trig_o, // asserted if escalation triggers
+ output logic [EscCntDw-1:0] esc_cnt_o, // current timeout / escalation count
+ output logic [N_ESC_SEV-1:0] esc_sig_req_o, // escalation signal outputs
+ // current state output
+ // 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3
+ output cstate_e esc_state_o
+);
+
+ ////////////////////
+ // Tandem Counter //
+ ////////////////////
+
+ // We employ two redundant counters to guard against FI attacks.
+ // If any of the two is glitched and the two counter states do not agree,
+ // the FSM below is moved into a terminal error state and escalation actions
+ // are permanently asserted.
+ logic cnt_en, cnt_clr, cnt_error;
+
+ // SEC_CM: ESC_TIMER.CTR.REDUN
+ prim_count #(
+ .Width(EscCntDw),
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler.
+ .EnableAlertTriggerSVA(0)
+ ) u_prim_count (
+ .clk_i,
+ .rst_ni,
+ .clr_i(cnt_clr && !cnt_en),
+ .set_i(cnt_clr && cnt_en),
+ .set_cnt_i(EscCntDw'(1)),
+ .incr_en_i(cnt_en),
+ .decr_en_i(1'b0),
+ .step_i(EscCntDw'(1)),
+ .cnt_o(esc_cnt_o),
+ .cnt_next_o(),
+ .err_o(cnt_error)
+ );
+
+ // threshold test, the thresholds are muxed further below
+ // depending on the current state
+ logic cnt_ge;
+ logic [EscCntDw-1:0] thresh;
+ assign cnt_ge = (esc_cnt_o >= thresh);
+
+ //////////////
+ // Main FSM //
+ //////////////
+
+ logic [N_PHASES-1:0] phase_oh;
+
+ // SEC_CM: ESC_TIMER.FSM.SPARSE
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
+ // -s 784905746 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (46.43%)
+ // 6: |||||||||||||||||||| (46.43%)
+ // 7: ||| (7.14%)
+ // 8: --
+ // 9: --
+ // 10: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 7
+ // Minimum Hamming weight: 3
+ // Maximum Hamming weight: 9
+ //
+ localparam int StateWidth = 10;
+ typedef enum logic [StateWidth-1:0] {
+ IdleSt = 10'b1011011010,
+ TimeoutSt = 10'b0000100110,
+ Phase0St = 10'b1110000101,
+ Phase1St = 10'b0101010100,
+ Phase2St = 10'b0000011001,
+ Phase3St = 10'b1001100001,
+ TerminalSt = 10'b1101111111,
+ FsmErrorSt = 10'b0111101000
+ } state_e;
+
+ logic fsm_error;
+ state_e state_d, state_q;
+
+ always_comb begin : p_fsm
+ // default
+ state_d = state_q;
+ esc_state_o = Idle;
+ cnt_en = 1'b0;
+ cnt_clr = 1'b0;
+ esc_trig_o = 1'b0;
+ phase_oh = '0;
+ thresh = timeout_cyc_i;
+ fsm_error = 1'b0;
+ latch_crashdump_o = 1'b0;
+
+ unique case (state_q)
+ // wait for an escalation trigger or an alert trigger
+ // the latter will trigger an interrupt timeout
+ IdleSt: begin
+ cnt_clr = 1'b1;
+ esc_state_o = Idle;
+
+ if (accu_trig_i && en_i && !clr_i) begin
+ state_d = Phase0St;
+ cnt_en = 1'b1;
+ esc_trig_o = 1'b1;
+ // the counter is zero in this state. so if the
+ // timeout count is zero (==disabled), cnt_ge will be true.
+ end else if (timeout_en_i && !cnt_ge && en_i) begin
+ cnt_en = 1'b1;
+ state_d = TimeoutSt;
+ end
+ end
+ // we are in interrupt timeout state
+ // in case an escalation comes in, we immediately have to
+ // switch over to the first escalation phase.
+ // in case the interrupt timeout hits it's cycle count, we
+ // also enter escalation phase0.
+ // ongoing timeouts can always be cleared.
+ TimeoutSt: begin
+ esc_state_o = Timeout;
+
+ if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
+ state_d = Phase0St;
+ cnt_en = 1'b1;
+ cnt_clr = 1'b1;
+ esc_trig_o = 1'b1;
+ // the timeout enable is connected to the irq state
+ // if that is cleared, stop the timeout counter
+ end else if (timeout_en_i) begin
+ cnt_en = 1'b1;
+ end else begin
+ state_d = IdleSt;
+ cnt_clr = 1'b1;
+ end
+ end
+ // note: autolocking the clear signal is done in the regfile
+ Phase0St: begin
+ cnt_en = 1'b1;
+ phase_oh[0] = 1'b1;
+ thresh = phase_cyc_i[0];
+ esc_state_o = Phase0;
+ latch_crashdump_o = (crashdump_phase_i == 2'b00);
+
+ if (clr_i) begin
+ state_d = IdleSt;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b0;
+ end else if (cnt_ge) begin
+ state_d = Phase1St;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b1;
+ end
+ end
+ Phase1St: begin
+ cnt_en = 1'b1;
+ phase_oh[1] = 1'b1;
+ thresh = phase_cyc_i[1];
+ esc_state_o = Phase1;
+ latch_crashdump_o = (crashdump_phase_i == 2'b01);
+
+ if (clr_i) begin
+ state_d = IdleSt;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b0;
+ end else if (cnt_ge) begin
+ state_d = Phase2St;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b1;
+ end
+ end
+ Phase2St: begin
+ cnt_en = 1'b1;
+ phase_oh[2] = 1'b1;
+ thresh = phase_cyc_i[2];
+ esc_state_o = Phase2;
+ latch_crashdump_o = (crashdump_phase_i == 2'b10);
+
+
+ if (clr_i) begin
+ state_d = IdleSt;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b0;
+ end else if (cnt_ge) begin
+ state_d = Phase3St;
+ cnt_clr = 1'b1;
+ end
+ end
+ Phase3St: begin
+ cnt_en = 1'b1;
+ phase_oh[3] = 1'b1;
+ thresh = phase_cyc_i[3];
+ esc_state_o = Phase3;
+ latch_crashdump_o = (crashdump_phase_i == 2'b11);
+
+ if (clr_i) begin
+ state_d = IdleSt;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b0;
+ end else if (cnt_ge) begin
+ state_d = TerminalSt;
+ cnt_clr = 1'b1;
+ cnt_en = 1'b0;
+ end
+ end
+ // final, terminal state after escalation.
+ // if clr is locked down, only a system reset
+ // will get us out of this state
+ TerminalSt: begin
+ cnt_clr = 1'b1;
+ esc_state_o = Terminal;
+ if (clr_i) begin
+ state_d = IdleSt;
+ end
+ end
+ // error state, only reached if the FSM has been
+ // glitched. in this state, we trigger all escalation
+ // actions at once.
+ FsmErrorSt: begin
+ esc_state_o = FsmError;
+ fsm_error = 1'b1;
+ end
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
+ // catch glitches.
+ default: begin
+ state_d = FsmErrorSt;
+ esc_state_o = FsmError;
+ fsm_error = 1'b1;
+ end
+ endcase
+
+ // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
+ // if any of the duplicate counter pairs has an inconsistent state
+ // we move into the terminal FSM error state.
+ if (accu_fail_i || cnt_error) begin
+ state_d = FsmErrorSt;
+ fsm_error = 1'b1;
+ end
+ end
+
+ logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
+ for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
+ // generate configuration mask for escalation enable signals
+ assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
+ // mask reduce current phase state vector
+ // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
+ assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
+ end
+
+ ///////////////////
+ // FSM Registers //
+ ///////////////////
+
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler. The
+ // EnableAlertTriggerSVA parameter is therefore set to 0.
+ `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
+
+ ////////////////
+ // Assertions //
+ ////////////////
+
+ // a clear should always bring us back to idle
+ `ASSERT(CheckClr_A,
+ !accu_fail_i &&
+ clr_i &&
+ !(state_q inside {IdleSt, TimeoutSt, FsmErrorSt})
+ |=>
+ state_q == IdleSt)
+ // if currently in idle and not enabled, must remain here
+ `ASSERT(CheckEn_A,
+ !accu_fail_i &&
+ state_q == IdleSt &&
+ !en_i
+ |=>
+ state_q == IdleSt)
+ // Check if accumulation trigger correctly captured
+ `ASSERT(CheckAccumTrig0_A,
+ !accu_fail_i &&
+ accu_trig_i &&
+ state_q == IdleSt &&
+ en_i &&
+ !clr_i
+ |=>
+ state_q == Phase0St)
+ `ASSERT(CheckAccumTrig1_A,
+ !accu_fail_i &&
+ accu_trig_i &&
+ state_q == TimeoutSt &&
+ en_i &&
+ !clr_i
+ |=>
+ state_q == Phase0St)
+ // Check if timeout correctly captured
+ `ASSERT(CheckTimeout0_A,
+ !accu_fail_i &&
+ state_q == IdleSt &&
+ timeout_en_i &&
+ en_i &&
+ timeout_cyc_i != 0 &&
+ !accu_trig_i
+ |=>
+ state_q == TimeoutSt)
+ `ASSERT(CheckTimeoutSt1_A,
+ !accu_fail_i &&
+ state_q == TimeoutSt &&
+ timeout_en_i &&
+ esc_cnt_o < timeout_cyc_i &&
+ !accu_trig_i
+ |=>
+ state_q == TimeoutSt)
+ `ASSERT(CheckTimeoutSt2_A,
+ !accu_fail_i &&
+ state_q == TimeoutSt &&
+ !timeout_en_i &&
+ !accu_trig_i
+ |=>
+ state_q == IdleSt)
+ // Check if timeout correctly triggers escalation
+ `ASSERT(CheckTimeoutStTrig_A,
+ !accu_fail_i &&
+ state_q == TimeoutSt &&
+ timeout_en_i &&
+ esc_cnt_o == timeout_cyc_i
+ |=>
+ state_q == Phase0St)
+ // Check whether escalation phases are correctly switched
+ `ASSERT(CheckPhase0_A,
+ !accu_fail_i &&
+ state_q == Phase0St &&
+ !clr_i &&
+ esc_cnt_o >= phase_cyc_i[0]
+ |=>
+ state_q == Phase1St)
+ `ASSERT(CheckPhase1_A,
+ !accu_fail_i &&
+ state_q == Phase1St &&
+ !clr_i &&
+ esc_cnt_o >= phase_cyc_i[1]
+ |=>
+ state_q == Phase2St)
+ `ASSERT(CheckPhase2_A,
+ !accu_fail_i &&
+ state_q == Phase2St &&
+ !clr_i &&
+ esc_cnt_o >= phase_cyc_i[2]
+ |=>
+ state_q == Phase3St)
+ `ASSERT(CheckPhase3_A,
+ !accu_fail_i &&
+ state_q == Phase3St &&
+ !clr_i &&
+ esc_cnt_o >= phase_cyc_i[3]
+ |=>
+ state_q == TerminalSt)
+ `ASSERT(AccuFailToFsmError_A,
+ accu_fail_i
+ |=>
+ state_q == FsmErrorSt)
+ `ASSERT(ErrorStIsTerminal_A,
+ state_q == FsmErrorSt
+ |=>
+ state_q == FsmErrorSt)
+ `ASSERT(ErrorStAllEscAsserted_A,
+ state_q == FsmErrorSt
+ |->
+ esc_sig_req_o == '1)
+
+endmodule : alert_handler_esc_timer
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv
new file mode 100644
index 0000000..4fc4586
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv
@@ -0,0 +1,90 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module gathers and synchronizes the clock gating and reset indication signals for all
+// low-power groups (LPGs), synchronizes them to the alert handler clock domain. The clock gating
+// and reset indication signals are then logically OR'ed to produce one multibit value for each
+// LPG. The LPG multibit values are then mapped to the alert channels using the LpgMap parameter,
+// and each multibit output value is buffered independently.
+//
+
+`include "prim_assert.sv"
+
+module alert_handler_lpg_ctrl import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ // Low power clk and rst indication signals.
+ input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i,
+ input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i,
+ // Init requests going to the individual alert channels.
+ output prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig_o
+);
+
+ import prim_mubi_pkg::mubi4_t;
+ import prim_mubi_pkg::mubi4_or_hi;
+ import prim_mubi_pkg::MuBi4True;
+
+ ///////////////////////////////////////////////////
+ // Aggregate multibit indication signals per LPG //
+ ///////////////////////////////////////////////////
+
+ mubi4_t [NLpg-1:0] synced_lpg_cg_en, synced_lpg_rst_en, lpg_init_trig;
+ for (genvar k = 0; k < NLpg; k++) begin : gen_lpgs
+ prim_mubi4_sync #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sync_cg_en (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(lpg_cg_en_i[k]),
+ .mubi_o(synced_lpg_cg_en[k:k])
+ );
+ prim_mubi4_sync #(
+ .ResetValue(MuBi4True)
+ ) u_prim_mubi4_sync_rst_en (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(lpg_rst_en_i[k]),
+ .mubi_o(synced_lpg_rst_en[k:k])
+ );
+
+ // Perform a logical OR operation of the multibit life cycle signals.
+ // I.e., if any of the incoming multibit signals is On, the output will also be On.
+ // Otherwise, the output may have any value other than On.
+ assign lpg_init_trig[k] = mubi4_or_hi(synced_lpg_cg_en[k], synced_lpg_rst_en[k]);
+ end
+
+ //////////////////////////////////
+ // LPG to Alert Channel Mapping //
+ //////////////////////////////////
+
+ // select the correct lpg for the alert channel at index j and buffer the multibit signal for each
+ // alert channel.
+ for (genvar j=0; j < NAlerts; j++) begin : gen_alert_map
+ prim_mubi4_sync #(
+ .AsyncOn(0) // no sync flops
+ ) u_prim_mubi4_sync_lpg_en (
+ .clk_i,
+ .rst_ni,
+ .mubi_i(lpg_init_trig[LpgMap[j]]),
+ .mubi_o({alert_init_trig_o[j]})
+ );
+ end
+
+ // explicitly read all unused lpg triggers to avoid lint errors.
+ logic [NLpg-1:0] lpg_used;
+ logic unused_lpg_init_trig;
+ always_comb begin
+ lpg_used = '0;
+ unused_lpg_init_trig = 1'b0;
+ for (int j=0; j < NAlerts; j++) begin
+ lpg_used[LpgMap[j]] |= 1'b1;
+ end
+ for (int k=0; k < NLpg; k++) begin
+ if (!lpg_used) begin
+ unused_lpg_init_trig ^= ^lpg_init_trig[k];
+ end
+ end
+ end
+
+endmodule : alert_handler_lpg_ctrl
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv
new file mode 100644
index 0000000..5888785
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv
@@ -0,0 +1,429 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// This module implements the ping mechanism. Once enabled, this module uses an
+// LFSR-based PRNG to
+//
+// a) determine the next peripheral index to be pinged (can be an alert receiver or an
+// escalation sender). it it is detected that this particular peripheral is disabled,
+// another index will be drawn from the PRNG.
+//
+// b) determine the amount of pause cycles to wait before pinging the peripheral selected in a).
+//
+// Once the ping timer waited for the amount of pause cycles determined in b), it asserts
+// the ping enable signal of the peripheral determined in a). If that peripheral does
+// not respond within the ping timeout window, an internal alert will be raised.
+//
+// Further, if a spurious ping_ok signal is detected (i.e., a ping ok that has not been
+// requested), the ping timer will also raise an internal alert.
+//
+
+`include "prim_assert.sv"
+
+module alert_handler_ping_timer import alert_pkg::*; #(
+ // Compile time random constants, to be overriden by topgen.
+ parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
+ // Enable this for DV, disable this for long LFSRs in FPV
+ parameter bit MaxLenSVA = 1'b1,
+ // Can be disabled in cases where entropy
+ // inputs are unused in order to not distort coverage
+ // (the SVA will be unreachable in such cases)
+ parameter bit LockupSVA = 1'b1
+) (
+ input clk_i,
+ input rst_ni,
+ output logic edn_req_o, // request to EDN
+ input edn_ack_i, // ack from EDN
+ input [LfsrWidth-1:0] edn_data_i, // from EDN
+ input en_i, // enable ping testing
+ input [NAlerts-1:0] alert_ping_en_i, // determines which alerts to ping
+ input [PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles
+ input [PING_CNT_DW-1:0] wait_cyc_mask_i, // mask to shorten the counters in DV / FPV
+ output logic [NAlerts-1:0] alert_ping_req_o, // request to alert receivers
+ output logic [N_ESC_SEV-1:0] esc_ping_req_o, // enable to esc senders
+ input [NAlerts-1:0] alert_ping_ok_i, // response from alert receivers
+ input [N_ESC_SEV-1:0] esc_ping_ok_i, // response from esc senders
+ output logic alert_ping_fail_o, // any of the alert receivers failed
+ output logic esc_ping_fail_o // any of the esc senders failed
+);
+
+ localparam int unsigned IdDw = $clog2(NAlerts);
+
+ // Entropy reseeding is triggered every time this counter expires.
+ // The expected wait time between pings is 2**(PING_CNT_DW-1) on average.
+ // We do not need to reseed the LFSR very often, and the constant below is chosen
+ // such that on average the LFSR is reseeded every 16th ping.
+ localparam int unsigned ReseedLfsrExtraBits = 3;
+ localparam int unsigned ReseedLfsrWidth = PING_CNT_DW + ReseedLfsrExtraBits;
+
+ // A few smoke checks for the DV mask:
+ // 1) make sure the value is a right-aligned mask.
+ // this can be done by checking that mask+1 is a power of 2.
+ // 2) also make sure that the value is always >= 0x7.
+ `ASSERT(WaitCycMaskMin_A, wait_cyc_mask_i >= 'h7)
+ `ASSERT(WaitCycMaskIsRightAlignedMask_A, $onehot(32'(wait_cyc_mask_i) + 1))
+
+ ////////////////////
+ // Reseed counter //
+ ////////////////////
+
+ logic reseed_en;
+ logic [ReseedLfsrWidth-1:0] reseed_timer_d, reseed_timer_q;
+
+ assign reseed_timer_d = (reseed_timer_q > '0) ? reseed_timer_q - 1'b1 :
+ (reseed_en) ? {wait_cyc_mask_i,
+ {ReseedLfsrExtraBits{1'b1}}} : '0;
+ assign edn_req_o = (reseed_timer_q == '0);
+ assign reseed_en = edn_req_o & edn_ack_i;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
+ if (!rst_ni) begin
+ reseed_timer_q <= '0;
+ end else begin
+ reseed_timer_q <= reseed_timer_d;
+ end
+ end
+
+ ///////////////////////////
+ // Tandem LFSR Instances //
+ ///////////////////////////
+
+ logic cnt_set, lfsr_err;
+ logic [LfsrWidth-1:0] entropy;
+ logic [PING_CNT_DW + IdDw - 1:0] lfsr_state;
+ assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0;
+
+ // SEC_CM: PING_TIMER.LFSR.REDUN
+ // We employ two redundant LFSRs to guard against FI attacks.
+ // If any of the two is glitched and the two LFSR states do not agree,
+ // the FSM below is moved into a terminal error state and all ping alerts
+ // are permanently asserted.
+ prim_double_lfsr #(
+ .LfsrDw ( LfsrWidth ),
+ .EntropyDw ( LfsrWidth ),
+ .StateOutDw ( PING_CNT_DW + IdDw ),
+ .DefaultSeed ( RndCnstLfsrSeed ),
+ .StatePermEn ( 1'b1 ),
+ .StatePerm ( RndCnstLfsrPerm ),
+ .MaxLenSVA ( MaxLenSVA ),
+ .LockupSVA ( LockupSVA ),
+ .ExtSeedSVA ( 1'b0 ), // ext seed is unused
+ .EnableAlertTriggerSVA ( 1'b0 )
+ ) u_prim_double_lfsr (
+ .clk_i,
+ .rst_ni,
+ .seed_en_i ( 1'b0 ),
+ .seed_i ( '0 ),
+ .lfsr_en_i ( reseed_en || cnt_set ),
+ .entropy_i ( entropy ),
+ .state_o ( lfsr_state ),
+ .err_o ( lfsr_err )
+ );
+
+ logic [IdDw-1:0] id_to_ping_d, id_to_ping_q;
+ // The subtraction below ensures that the alert ID is always in range. If
+ // all alerts are enabled, an alert ID drawn in this way will always be
+ // valid. This comes at the cost of a bias towards certain alert IDs that
+ // will be pinged twice as often on average - but it ensures that we have
+ // less alert IDs that need to be skipped since they are invalid.
+ assign id_to_ping_d = (lfsr_state[PING_CNT_DW +: IdDw] >= NAlerts) ?
+ lfsr_state[PING_CNT_DW +: IdDw] - NAlerts :
+ lfsr_state[PING_CNT_DW +: IdDw];
+
+ // we need to hold the ID stable while the ping is ongoing since this will result in
+ // spurious ping responses otherwise.
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_id_reg
+ if (!rst_ni) begin
+ id_to_ping_q <= '0;
+ end else begin
+ if (cnt_set) begin
+ id_to_ping_q <= id_to_ping_d;
+ end
+ end
+ end
+
+ // align the enable mask with powers of two for the indexing operation below.
+ logic [2**IdDw-1:0] enable_mask;
+ assign enable_mask = (2**IdDw)'(alert_ping_en_i);
+
+ // check if the randomly drawn alert ID is actually valid and the alert is enabled
+ logic id_vld;
+ assign id_vld = enable_mask[id_to_ping_q];
+
+ //////////////////////////////////
+ // Escalation Counter Instances //
+ //////////////////////////////////
+
+ // As opposed to the alert ID, the escalation sender ID to be pinged is not drawn at random.
+ // Rather, we cycle through the escalation senders one by one in a deterministic fashion.
+ // This allows us to provide guarantees needed for the ping timeout / auto escalation feature
+ // implemented at the escalation receiver side.
+ //
+ // In particular, with N_ESC_SEV escalation senders in the design, we can guarantee
+ // that each escalation channel will be pinged at least once every
+ //
+ // N_ESC_SEV x (NUM_WAIT_COUNT + NUM_TIMEOUT_COUNT) x 2**PING_CNT_DW
+ //
+ // cycles - independently of the reseeding operation.
+ //
+ // - N_ESC_SEV: # escalation channels to ping.
+ // - NUM_WAIT_COUNT: # wait counts between subsequent escalation channel pings.
+ // - NUM_TIMEOUT_COUNT: # timeout counts between subsequent escalation channel pings.
+ // - 2**PING_CNT_DW: # maximum counter value.
+ //
+ // This guarantee is used inside the escalation receivers to monitor the pings sent out by the
+ // alert handler. I.e., once the alert handler has started to send out pings, each escalation
+ // receiver employs a timeout window within which it expects the next ping to arrive. If
+ // escalation pings cease to arrive at an escalation receiver for any reason, this will
+ // automatically trigger the associated escalation countermeasure.
+ //
+ // In order to have enough margin, the escalation receiver timeout counters use a threshold that
+ // is 4x higher than the value calculated above. With N_ESC_SEV = 4, PING_CNT_DW = 16 and
+ // NUM_WAIT_COUNT = NUM_TIMEOUT_COUNT = 2 this amounts to a 22bit timeout threshold.
+ //
+ // We employ two redundant counters to guard against FI attacks.
+ // If any of the two is glitched and the two counter states do not agree,
+ // the FSM below is moved into a terminal error state and all ping alerts
+ // are permanently asserted.
+
+ logic esc_cnt_en, esc_cnt_clr, esc_cnt_error;
+ logic [PING_CNT_DW-1:0] esc_cnt;
+ assign esc_cnt_clr = (esc_cnt >= PING_CNT_DW'(N_ESC_SEV-1)) && esc_cnt_en;
+
+ // SEC_CM: PING_TIMER.CTR.REDUN
+ prim_count #(
+ .Width(PING_CNT_DW),
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler.
+ .EnableAlertTriggerSVA(0)
+ ) u_prim_count_esc_cnt (
+ .clk_i,
+ .rst_ni,
+ .clr_i(esc_cnt_clr),
+ .set_i(1'b0),
+ .set_cnt_i('0),
+ .incr_en_i(esc_cnt_en),
+ .decr_en_i(1'b0),
+ .step_i(PING_CNT_DW'(1)),
+ .cnt_o(esc_cnt),
+ .cnt_next_o(),
+ .err_o(esc_cnt_error)
+ );
+
+ /////////////////////////////
+ // Timer Counter Instances //
+ /////////////////////////////
+
+ // We employ two redundant counters to guard against FI attacks.
+ // If any of the two is glitched and the two counter states do not agree,
+ // the FSM below is moved into a terminal error state and all ping alerts
+ // are permanently asserted.
+ logic [PING_CNT_DW-1:0] cnt, cnt_setval;
+ logic wait_cnt_set, timeout_cnt_set, timer_expired, cnt_error;
+ assign timer_expired = (cnt == '0);
+ assign cnt_set = wait_cnt_set || timeout_cnt_set;
+
+ // SEC_CM: PING_TIMER.CTR.REDUN
+ prim_count #(
+ .Width(PING_CNT_DW),
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler.
+ .EnableAlertTriggerSVA(0)
+ ) u_prim_count_cnt (
+ .clk_i,
+ .rst_ni,
+ .clr_i(1'b0),
+ .set_i(cnt_set),
+ .set_cnt_i(cnt_setval),
+ .incr_en_i(1'b0),
+ .decr_en_i(!timer_expired), // we are counting down here.
+ .step_i(PING_CNT_DW'(1'b1)),
+ .cnt_o(cnt),
+ .cnt_next_o(),
+ .err_o(cnt_error)
+ );
+
+ // the constant offset ensures a minimum cycle spacing between pings.
+ logic unused_bits;
+ logic [PING_CNT_DW-1:0] wait_cyc;
+ assign wait_cyc = (lfsr_state[PING_CNT_DW-1:0] | PING_CNT_DW'(3'b100));
+ assign unused_bits = lfsr_state[2];
+
+ // note that the masks are used for DV/FPV only in order to reduce the state space.
+ assign cnt_setval = (wait_cnt_set) ? (wait_cyc & wait_cyc_mask_i) : ping_timeout_cyc_i;
+
+ ////////////////////////////
+ // Ping and Timeout Logic //
+ ////////////////////////////
+
+ logic alert_ping_en, esc_ping_en;
+ logic spurious_alert_ping, spurious_esc_ping;
+
+ // generate ping enable vector
+ assign alert_ping_req_o = NAlerts'(alert_ping_en) << id_to_ping_q;
+ assign esc_ping_req_o = N_ESC_SEV'(esc_ping_en) << esc_cnt;
+
+ // under normal operation, these signals should never be asserted.
+ // we place hand instantiated buffers here such that these signals are not
+ // optimized away during synthesis (these buffers will receive a keep or size_only
+ // attribute in our Vivado and DC synthesis flows).
+ prim_buf u_prim_buf_spurious_alert_ping (
+ .in_i(|(alert_ping_ok_i & ~alert_ping_req_o)),
+ .out_o(spurious_alert_ping)
+ );
+ prim_buf u_prim_buf_spurious_esc_ping (
+ .in_i(|(esc_ping_ok_i & ~esc_ping_req_o)),
+ .out_o(spurious_esc_ping)
+ );
+
+ // SEC_CM: PING_TIMER.FSM.SPARSE
+ // Encoding generated with:
+ // $ ./util/design/sparse-fsm-encode.py -d 5 -m 6 -n 9 \
+ // -s 728582219 --language=sv
+ //
+ // Hamming distance histogram:
+ //
+ // 0: --
+ // 1: --
+ // 2: --
+ // 3: --
+ // 4: --
+ // 5: |||||||||||||||||||| (60.00%)
+ // 6: ||||||||||||| (40.00%)
+ // 7: --
+ // 8: --
+ // 9: --
+ //
+ // Minimum Hamming distance: 5
+ // Maximum Hamming distance: 6
+ // Minimum Hamming weight: 2
+ // Maximum Hamming weight: 6
+ //
+ localparam int StateWidth = 9;
+ typedef enum logic [StateWidth-1:0] {
+ InitSt = 9'b011001011,
+ AlertWaitSt = 9'b110000000,
+ AlertPingSt = 9'b101110001,
+ EscWaitSt = 9'b010110110,
+ EscPingSt = 9'b000011101,
+ FsmErrorSt = 9'b101101110
+ } state_e;
+
+ state_e state_d, state_q;
+
+ always_comb begin : p_fsm
+ // default
+ state_d = state_q;
+ wait_cnt_set = 1'b0;
+ timeout_cnt_set = 1'b0;
+ esc_cnt_en = 1'b0;
+ alert_ping_en = 1'b0;
+ esc_ping_en = 1'b0;
+ // this captures spurious ping responses
+ alert_ping_fail_o = spurious_alert_ping;
+ esc_ping_fail_o = spurious_esc_ping;
+
+ unique case (state_q)
+ // wait until activated
+ // we never return to this state
+ // once activated!
+ InitSt: begin
+ if (en_i) begin
+ state_d = AlertWaitSt;
+ wait_cnt_set = 1'b1;
+ end
+ end
+ // wait for random amount of cycles
+ AlertWaitSt: begin
+ if (timer_expired) begin
+ state_d = AlertPingSt;
+ timeout_cnt_set = 1'b1;
+ end
+ end
+ // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK
+ // send out an alert ping request and wait for a ping
+ // response or a ping timeout (whatever comes first).
+ // if the alert ID is not valid, we drop the request and
+ // proceed to the next ping.
+ AlertPingSt: begin
+ alert_ping_en = id_vld;
+ if (timer_expired || |(alert_ping_ok_i & alert_ping_req_o) || !id_vld) begin
+ state_d = EscWaitSt;
+ wait_cnt_set = 1'b1;
+ if (timer_expired) begin
+ alert_ping_fail_o = 1'b1;
+ end
+ end
+ end
+ // wait for random amount of cycles
+ EscWaitSt: begin
+ if (timer_expired) begin
+ state_d = EscPingSt;
+ timeout_cnt_set = 1'b1;
+ end
+ end
+ // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK
+ // send out an escalation ping request and wait for a ping
+ // response or a ping timeout (whatever comes first)
+ EscPingSt: begin
+ esc_ping_en = 1'b1;
+ if (timer_expired || |(esc_ping_ok_i & esc_ping_req_o)) begin
+ state_d = AlertWaitSt;
+ wait_cnt_set = 1'b1;
+ esc_cnt_en = 1'b1;
+ if (timer_expired) begin
+ esc_ping_fail_o = 1'b1;
+ end
+ end
+ end
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
+ // terminal FSM error state.
+ // if we for some reason end up in this state (e.g. malicious glitching)
+ // we are going to assert both ping fails continuously
+ FsmErrorSt: begin
+ alert_ping_fail_o = 1'b1;
+ esc_ping_fail_o = 1'b1;
+ end
+ default: begin
+ state_d = FsmErrorSt;
+ alert_ping_fail_o = 1'b1;
+ esc_ping_fail_o = 1'b1;
+ end
+ endcase
+
+ // SEC_CM: PING_TIMER.FSM.LOCAL_ESC
+ // if the two LFSR or counter states do not agree,
+ // we move into the terminal state.
+ if (lfsr_err || cnt_error || esc_cnt_error) begin
+ state_d = FsmErrorSt;
+ alert_ping_fail_o = 1'b1;
+ esc_ping_fail_o = 1'b1;
+ end
+ end
+
+ ///////////////////
+ // FSM Registers //
+ ///////////////////
+
+ // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
+ // an alert signal, this condition is handled internally in the alert handler. The
+ // EnableAlertTriggerSVA parameter is therefore set to 0.
+ `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, InitSt, clk_i, rst_ni, 0)
+
+ ////////////////
+ // Assertions //
+ ////////////////
+
+ // make sure the ID width is within bounds.
+ `ASSERT_INIT(MaxIdDw_A, IdDw <= (LfsrWidth - PING_CNT_DW))
+
+ // only one module is pinged at a time.
+ `ASSERT(PingOH0_A, $onehot0({alert_ping_req_o, esc_ping_req_o}))
+
+ // we should never get into the ping state without knowing which module to ping.
+ `ASSERT(AlertPingOH_A, alert_ping_en |-> $onehot(alert_ping_req_o))
+ `ASSERT(EscPingOH_A, esc_ping_en |-> $onehot(esc_ping_req_o))
+
+endmodule : alert_handler_ping_timer
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
new file mode 100644
index 0000000..189121b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -0,0 +1,1921 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package alert_handler_reg_pkg;
+
+ // Param list
+ parameter int NAlerts = 75;
+ parameter int NLpg = 32;
+ parameter int NLpgWidth = 6;
+ parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = {
+ 6'd26,
+ 6'd26,
+ 6'd26,
+ 6'd26,
+ 6'd30,
+ 6'd29,
+ 6'd27,
+ 6'd25,
+ 6'd5,
+ 6'd0,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd19,
+ 6'd23,
+ 6'd23,
+ 6'd22,
+ 6'd22,
+ 6'd21,
+ 6'd20,
+ 6'd20,
+ 6'd19,
+ 6'd18,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd17,
+ 6'd16,
+ 6'd12,
+ 6'd12,
+ 6'd14,
+ 6'd11,
+ 6'd13,
+ 6'd13,
+ 6'd12,
+ 6'd11,
+ 6'd11,
+ 6'd11,
+ 6'd11,
+ 6'd10,
+ 6'd9,
+ 6'd8,
+ 6'd7,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd6,
+ 6'd5,
+ 6'd0,
+ 6'd4,
+ 6'd3,
+ 6'd2,
+ 6'd1,
+ 6'd0,
+ 6'd0,
+ 6'd0,
+ 6'd0,
+ 6'd0
+};
+ parameter int EscCntDw = 32;
+ parameter int AccuCntDw = 16;
+ parameter logic [NAlerts-1:0] AsyncOn = {
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1,
+ 1'b1
+};
+ parameter int N_CLASSES = 4;
+ parameter int N_ESC_SEV = 4;
+ parameter int N_PHASES = 4;
+ parameter int N_LOC_ALERT = 7;
+ parameter int PING_CNT_DW = 16;
+ parameter int PHASE_DW = 2;
+ parameter int CLASS_DW = 2;
+ parameter int LOCAL_ALERT_ID_ALERT_PINGFAIL = 0;
+ parameter int LOCAL_ALERT_ID_ESC_PINGFAIL = 1;
+ parameter int LOCAL_ALERT_ID_ALERT_INTEGFAIL = 2;
+ parameter int LOCAL_ALERT_ID_ESC_INTEGFAIL = 3;
+ parameter int LOCAL_ALERT_ID_BUS_INTEGFAIL = 4;
+ parameter int LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR = 5;
+ parameter int LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR = 6;
+ parameter int LOCAL_ALERT_ID_LAST = 6;
+
+ // Address widths within the block
+ parameter int BlockAw = 11;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } classa;
+ struct packed {
+ logic q;
+ } classb;
+ struct packed {
+ logic q;
+ } classc;
+ struct packed {
+ logic q;
+ } classd;
+ } alert_handler_reg2hw_intr_state_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } classa;
+ struct packed {
+ logic q;
+ } classb;
+ struct packed {
+ logic q;
+ } classc;
+ struct packed {
+ logic q;
+ } classd;
+ } alert_handler_reg2hw_intr_enable_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ logic qe;
+ } classa;
+ struct packed {
+ logic q;
+ logic qe;
+ } classb;
+ struct packed {
+ logic q;
+ logic qe;
+ } classc;
+ struct packed {
+ logic q;
+ logic qe;
+ } classd;
+ } alert_handler_reg2hw_intr_test_reg_t;
+
+ typedef struct packed {
+ logic [15:0] q;
+ } alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_ping_timer_en_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_alert_regwen_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_alert_en_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_alert_class_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_alert_cause_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } alert_handler_reg2hw_loc_alert_cause_mreg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } lock;
+ struct packed {
+ logic q;
+ } en_e0;
+ struct packed {
+ logic q;
+ } en_e1;
+ struct packed {
+ logic q;
+ } en_e2;
+ struct packed {
+ logic q;
+ } en_e3;
+ struct packed {
+ logic [1:0] q;
+ } map_e0;
+ struct packed {
+ logic [1:0] q;
+ } map_e1;
+ struct packed {
+ logic [1:0] q;
+ } map_e2;
+ struct packed {
+ logic [1:0] q;
+ } map_e3;
+ } alert_handler_reg2hw_classa_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } alert_handler_reg2hw_classa_clr_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [15:0] q;
+ } alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } lock;
+ struct packed {
+ logic q;
+ } en_e0;
+ struct packed {
+ logic q;
+ } en_e1;
+ struct packed {
+ logic q;
+ } en_e2;
+ struct packed {
+ logic q;
+ } en_e3;
+ struct packed {
+ logic [1:0] q;
+ } map_e0;
+ struct packed {
+ logic [1:0] q;
+ } map_e1;
+ struct packed {
+ logic [1:0] q;
+ } map_e2;
+ struct packed {
+ logic [1:0] q;
+ } map_e3;
+ } alert_handler_reg2hw_classb_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } alert_handler_reg2hw_classb_clr_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [15:0] q;
+ } alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } lock;
+ struct packed {
+ logic q;
+ } en_e0;
+ struct packed {
+ logic q;
+ } en_e1;
+ struct packed {
+ logic q;
+ } en_e2;
+ struct packed {
+ logic q;
+ } en_e3;
+ struct packed {
+ logic [1:0] q;
+ } map_e0;
+ struct packed {
+ logic [1:0] q;
+ } map_e1;
+ struct packed {
+ logic [1:0] q;
+ } map_e2;
+ struct packed {
+ logic [1:0] q;
+ } map_e3;
+ } alert_handler_reg2hw_classc_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } alert_handler_reg2hw_classc_clr_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [15:0] q;
+ } alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic q;
+ } en;
+ struct packed {
+ logic q;
+ } lock;
+ struct packed {
+ logic q;
+ } en_e0;
+ struct packed {
+ logic q;
+ } en_e1;
+ struct packed {
+ logic q;
+ } en_e2;
+ struct packed {
+ logic q;
+ } en_e3;
+ struct packed {
+ logic [1:0] q;
+ } map_e0;
+ struct packed {
+ logic [1:0] q;
+ } map_e1;
+ struct packed {
+ logic [1:0] q;
+ } map_e2;
+ struct packed {
+ logic [1:0] q;
+ } map_e3;
+ } alert_handler_reg2hw_classd_ctrl_shadowed_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } alert_handler_reg2hw_classd_clr_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [15:0] q;
+ } alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ } alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } classa;
+ struct packed {
+ logic d;
+ logic de;
+ } classb;
+ struct packed {
+ logic d;
+ logic de;
+ } classc;
+ struct packed {
+ logic d;
+ logic de;
+ } classd;
+ } alert_handler_hw2reg_intr_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_alert_cause_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_loc_alert_cause_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_classa_clr_regwen_reg_t;
+
+ typedef struct packed {
+ logic [15:0] d;
+ } alert_handler_hw2reg_classa_accum_cnt_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } alert_handler_hw2reg_classa_esc_cnt_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } alert_handler_hw2reg_classa_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_classb_clr_regwen_reg_t;
+
+ typedef struct packed {
+ logic [15:0] d;
+ } alert_handler_hw2reg_classb_accum_cnt_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } alert_handler_hw2reg_classb_esc_cnt_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } alert_handler_hw2reg_classb_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_classc_clr_regwen_reg_t;
+
+ typedef struct packed {
+ logic [15:0] d;
+ } alert_handler_hw2reg_classc_accum_cnt_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } alert_handler_hw2reg_classc_esc_cnt_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } alert_handler_hw2reg_classc_state_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } alert_handler_hw2reg_classd_clr_regwen_reg_t;
+
+ typedef struct packed {
+ logic [15:0] d;
+ } alert_handler_hw2reg_classd_accum_cnt_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } alert_handler_hw2reg_classd_esc_cnt_reg_t;
+
+ typedef struct packed {
+ logic [2:0] d;
+ } alert_handler_hw2reg_classd_state_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1211:1208]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1207:1204]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1203:1196]
+ alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1195:1180]
+ alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1179:1179]
+ alert_handler_reg2hw_alert_regwen_mreg_t [74:0] alert_regwen; // [1178:1104]
+ alert_handler_reg2hw_alert_en_shadowed_mreg_t [74:0] alert_en_shadowed; // [1103:1029]
+ alert_handler_reg2hw_alert_class_shadowed_mreg_t [74:0] alert_class_shadowed; // [1028:879]
+ alert_handler_reg2hw_alert_cause_mreg_t [74:0] alert_cause; // [878:804]
+ alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797]
+ alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0]
+ loc_alert_class_shadowed; // [796:783]
+ alert_handler_reg2hw_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [782:776]
+ alert_handler_reg2hw_classa_ctrl_shadowed_reg_t classa_ctrl_shadowed; // [775:762]
+ alert_handler_reg2hw_classa_clr_shadowed_reg_t classa_clr_shadowed; // [761:760]
+ alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t
+ classa_accum_thresh_shadowed; // [759:744]
+ alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t classa_timeout_cyc_shadowed; // [743:712]
+ alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t
+ classa_crashdump_trigger_shadowed; // [711:710]
+ alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t classa_phase0_cyc_shadowed; // [709:678]
+ alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t classa_phase1_cyc_shadowed; // [677:646]
+ alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t classa_phase2_cyc_shadowed; // [645:614]
+ alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t classa_phase3_cyc_shadowed; // [613:582]
+ alert_handler_reg2hw_classb_ctrl_shadowed_reg_t classb_ctrl_shadowed; // [581:568]
+ alert_handler_reg2hw_classb_clr_shadowed_reg_t classb_clr_shadowed; // [567:566]
+ alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t
+ classb_accum_thresh_shadowed; // [565:550]
+ alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t classb_timeout_cyc_shadowed; // [549:518]
+ alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t
+ classb_crashdump_trigger_shadowed; // [517:516]
+ alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t classb_phase0_cyc_shadowed; // [515:484]
+ alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t classb_phase1_cyc_shadowed; // [483:452]
+ alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t classb_phase2_cyc_shadowed; // [451:420]
+ alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t classb_phase3_cyc_shadowed; // [419:388]
+ alert_handler_reg2hw_classc_ctrl_shadowed_reg_t classc_ctrl_shadowed; // [387:374]
+ alert_handler_reg2hw_classc_clr_shadowed_reg_t classc_clr_shadowed; // [373:372]
+ alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t
+ classc_accum_thresh_shadowed; // [371:356]
+ alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t classc_timeout_cyc_shadowed; // [355:324]
+ alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t
+ classc_crashdump_trigger_shadowed; // [323:322]
+ alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t classc_phase0_cyc_shadowed; // [321:290]
+ alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t classc_phase1_cyc_shadowed; // [289:258]
+ alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t classc_phase2_cyc_shadowed; // [257:226]
+ alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t classc_phase3_cyc_shadowed; // [225:194]
+ alert_handler_reg2hw_classd_ctrl_shadowed_reg_t classd_ctrl_shadowed; // [193:180]
+ alert_handler_reg2hw_classd_clr_shadowed_reg_t classd_clr_shadowed; // [179:178]
+ alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t
+ classd_accum_thresh_shadowed; // [177:162]
+ alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t classd_timeout_cyc_shadowed; // [161:130]
+ alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t
+ classd_crashdump_trigger_shadowed; // [129:128]
+ alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t classd_phase0_cyc_shadowed; // [127:96]
+ alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t classd_phase1_cyc_shadowed; // [95:64]
+ alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t classd_phase2_cyc_shadowed; // [63:32]
+ alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t classd_phase3_cyc_shadowed; // [31:0]
+ } alert_handler_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [383:376]
+ alert_handler_hw2reg_alert_cause_mreg_t [74:0] alert_cause; // [375:226]
+ alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212]
+ alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
+ alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
+ alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [193:162]
+ alert_handler_hw2reg_classa_state_reg_t classa_state; // [161:159]
+ alert_handler_hw2reg_classb_clr_regwen_reg_t classb_clr_regwen; // [158:157]
+ alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [156:141]
+ alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [140:109]
+ alert_handler_hw2reg_classb_state_reg_t classb_state; // [108:106]
+ alert_handler_hw2reg_classc_clr_regwen_reg_t classc_clr_regwen; // [105:104]
+ alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [103:88]
+ alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [87:56]
+ alert_handler_hw2reg_classc_state_reg_t classc_state; // [55:53]
+ alert_handler_hw2reg_classd_clr_regwen_reg_t classd_clr_regwen; // [52:51]
+ alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [50:35]
+ alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [34:3]
+ alert_handler_hw2reg_classd_state_reg_t classd_state; // [2:0]
+ } alert_handler_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 10;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET = 11'h 14;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 11'h b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 11'h b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 11'h bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 11'h c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 11'h c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_44_OFFSET = 11'h c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_48_OFFSET = 11'h d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_49_OFFSET = 11'h dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_50_OFFSET = 11'h e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_51_OFFSET = 11'h e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_52_OFFSET = 11'h e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_53_OFFSET = 11'h ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_54_OFFSET = 11'h f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_68_OFFSET = 11'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_69_OFFSET = 11'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_70_OFFSET = 11'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_71_OFFSET = 11'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_72_OFFSET = 11'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_73_OFFSET = 11'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_74_OFFSET = 11'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET = 11'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET = 11'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET = 11'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET = 11'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET = 11'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET = 11'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET = 11'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET = 11'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET = 11'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET = 11'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET = 11'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET = 11'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET = 11'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET = 11'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET = 11'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET = 11'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET = 11'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET = 11'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 3c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 3c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 3cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 3d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 3d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 3d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 3dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 3e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 3e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 3ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 3f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 3f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 3f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 3fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 400;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 404;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 408;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 40c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 410;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 414;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 418;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 41c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 420;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 424;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 428;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 42c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 430;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 438;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 43c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 440;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 444;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 448;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 44c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 450;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 454;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 458;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 45c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 460;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 464;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 468;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 46c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 470;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 474;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 478;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 47c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 480;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 484;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 488;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 48c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 490;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 494;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 498;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 49c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 4a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 4a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 4a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_68_OFFSET = 11'h 4ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_69_OFFSET = 11'h 4b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_70_OFFSET = 11'h 4b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_71_OFFSET = 11'h 4b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_72_OFFSET = 11'h 4bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_73_OFFSET = 11'h 4c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_74_OFFSET = 11'h 4c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 4c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 4cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 4d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 4d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 4d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 4dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 4e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 4e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 4e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 4ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 4f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 4f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 4f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 4fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 500;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 504;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 508;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 50c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 510;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 514;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 518;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 51c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 520;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 524;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 528;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 52c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 530;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 534;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 538;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 53c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 540;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 544;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 548;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 54c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 550;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 554;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 558;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 55c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 560;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 564;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 568;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 56c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 570;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 574;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 578;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 57c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 580;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 584;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 588;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 58c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 590;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 594;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 598;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 59c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 5a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 5a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 5a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 5ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 5b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 5b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 5b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 5bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 5c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 5c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 5c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 5cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 5d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 5d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 5d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 5dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 5e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 5e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 5e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 5ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 5f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 5f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 5f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 5fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 600;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 604;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 608;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 60c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 610;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 614;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
+ parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSA_RESVAL = 1'h 0;
+ parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSB_RESVAL = 1'h 0;
+ parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSC_RESVAL = 1'h 0;
+ parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSD_RESVAL = 1'h 0;
+ parameter logic [15:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_RESVAL = 16'h 0;
+ parameter logic [31:0] ALERT_HANDLER_CLASSA_ESC_CNT_RESVAL = 32'h 0;
+ parameter logic [2:0] ALERT_HANDLER_CLASSA_STATE_RESVAL = 3'h 0;
+ parameter logic [15:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_RESVAL = 16'h 0;
+ parameter logic [31:0] ALERT_HANDLER_CLASSB_ESC_CNT_RESVAL = 32'h 0;
+ parameter logic [2:0] ALERT_HANDLER_CLASSB_STATE_RESVAL = 3'h 0;
+ parameter logic [15:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_RESVAL = 16'h 0;
+ parameter logic [31:0] ALERT_HANDLER_CLASSC_ESC_CNT_RESVAL = 32'h 0;
+ parameter logic [2:0] ALERT_HANDLER_CLASSC_STATE_RESVAL = 3'h 0;
+ parameter logic [15:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_RESVAL = 16'h 0;
+ parameter logic [31:0] ALERT_HANDLER_CLASSD_ESC_CNT_RESVAL = 32'h 0;
+ parameter logic [2:0] ALERT_HANDLER_CLASSD_STATE_RESVAL = 3'h 0;
+
+ // Register index
+ typedef enum int {
+ ALERT_HANDLER_INTR_STATE,
+ ALERT_HANDLER_INTR_ENABLE,
+ ALERT_HANDLER_INTR_TEST,
+ ALERT_HANDLER_PING_TIMER_REGWEN,
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED,
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED,
+ ALERT_HANDLER_ALERT_REGWEN_0,
+ ALERT_HANDLER_ALERT_REGWEN_1,
+ ALERT_HANDLER_ALERT_REGWEN_2,
+ ALERT_HANDLER_ALERT_REGWEN_3,
+ ALERT_HANDLER_ALERT_REGWEN_4,
+ ALERT_HANDLER_ALERT_REGWEN_5,
+ ALERT_HANDLER_ALERT_REGWEN_6,
+ ALERT_HANDLER_ALERT_REGWEN_7,
+ ALERT_HANDLER_ALERT_REGWEN_8,
+ ALERT_HANDLER_ALERT_REGWEN_9,
+ ALERT_HANDLER_ALERT_REGWEN_10,
+ ALERT_HANDLER_ALERT_REGWEN_11,
+ ALERT_HANDLER_ALERT_REGWEN_12,
+ ALERT_HANDLER_ALERT_REGWEN_13,
+ ALERT_HANDLER_ALERT_REGWEN_14,
+ ALERT_HANDLER_ALERT_REGWEN_15,
+ ALERT_HANDLER_ALERT_REGWEN_16,
+ ALERT_HANDLER_ALERT_REGWEN_17,
+ ALERT_HANDLER_ALERT_REGWEN_18,
+ ALERT_HANDLER_ALERT_REGWEN_19,
+ ALERT_HANDLER_ALERT_REGWEN_20,
+ ALERT_HANDLER_ALERT_REGWEN_21,
+ ALERT_HANDLER_ALERT_REGWEN_22,
+ ALERT_HANDLER_ALERT_REGWEN_23,
+ ALERT_HANDLER_ALERT_REGWEN_24,
+ ALERT_HANDLER_ALERT_REGWEN_25,
+ ALERT_HANDLER_ALERT_REGWEN_26,
+ ALERT_HANDLER_ALERT_REGWEN_27,
+ ALERT_HANDLER_ALERT_REGWEN_28,
+ ALERT_HANDLER_ALERT_REGWEN_29,
+ ALERT_HANDLER_ALERT_REGWEN_30,
+ ALERT_HANDLER_ALERT_REGWEN_31,
+ ALERT_HANDLER_ALERT_REGWEN_32,
+ ALERT_HANDLER_ALERT_REGWEN_33,
+ ALERT_HANDLER_ALERT_REGWEN_34,
+ ALERT_HANDLER_ALERT_REGWEN_35,
+ ALERT_HANDLER_ALERT_REGWEN_36,
+ ALERT_HANDLER_ALERT_REGWEN_37,
+ ALERT_HANDLER_ALERT_REGWEN_38,
+ ALERT_HANDLER_ALERT_REGWEN_39,
+ ALERT_HANDLER_ALERT_REGWEN_40,
+ ALERT_HANDLER_ALERT_REGWEN_41,
+ ALERT_HANDLER_ALERT_REGWEN_42,
+ ALERT_HANDLER_ALERT_REGWEN_43,
+ ALERT_HANDLER_ALERT_REGWEN_44,
+ ALERT_HANDLER_ALERT_REGWEN_45,
+ ALERT_HANDLER_ALERT_REGWEN_46,
+ ALERT_HANDLER_ALERT_REGWEN_47,
+ ALERT_HANDLER_ALERT_REGWEN_48,
+ ALERT_HANDLER_ALERT_REGWEN_49,
+ ALERT_HANDLER_ALERT_REGWEN_50,
+ ALERT_HANDLER_ALERT_REGWEN_51,
+ ALERT_HANDLER_ALERT_REGWEN_52,
+ ALERT_HANDLER_ALERT_REGWEN_53,
+ ALERT_HANDLER_ALERT_REGWEN_54,
+ ALERT_HANDLER_ALERT_REGWEN_55,
+ ALERT_HANDLER_ALERT_REGWEN_56,
+ ALERT_HANDLER_ALERT_REGWEN_57,
+ ALERT_HANDLER_ALERT_REGWEN_58,
+ ALERT_HANDLER_ALERT_REGWEN_59,
+ ALERT_HANDLER_ALERT_REGWEN_60,
+ ALERT_HANDLER_ALERT_REGWEN_61,
+ ALERT_HANDLER_ALERT_REGWEN_62,
+ ALERT_HANDLER_ALERT_REGWEN_63,
+ ALERT_HANDLER_ALERT_REGWEN_64,
+ ALERT_HANDLER_ALERT_REGWEN_65,
+ ALERT_HANDLER_ALERT_REGWEN_66,
+ ALERT_HANDLER_ALERT_REGWEN_67,
+ ALERT_HANDLER_ALERT_REGWEN_68,
+ ALERT_HANDLER_ALERT_REGWEN_69,
+ ALERT_HANDLER_ALERT_REGWEN_70,
+ ALERT_HANDLER_ALERT_REGWEN_71,
+ ALERT_HANDLER_ALERT_REGWEN_72,
+ ALERT_HANDLER_ALERT_REGWEN_73,
+ ALERT_HANDLER_ALERT_REGWEN_74,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_0,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_1,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_2,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_3,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_4,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_5,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_6,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_7,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_8,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_9,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_10,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_11,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_12,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_13,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_14,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_15,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_16,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_17,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_18,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_19,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_20,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_21,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_22,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_23,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_24,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_25,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_26,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_27,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_28,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_29,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_30,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_31,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_32,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_33,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_34,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_35,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_36,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_37,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_38,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_39,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_40,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_41,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_42,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_43,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_44,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_45,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_46,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_47,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_48,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_49,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_50,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_51,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_52,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_53,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_54,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_55,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_56,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_57,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_58,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_59,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_60,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_61,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_62,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_63,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_64,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_65,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_66,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_67,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_68,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_69,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_70,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_71,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_72,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_73,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_74,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_1,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_2,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_3,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_4,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_5,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_6,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_7,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_8,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_9,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_10,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_11,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_12,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_13,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_14,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_15,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_16,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_17,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_18,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_19,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_20,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_21,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_22,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_23,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_24,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_25,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_26,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_27,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_28,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_29,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_30,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_31,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_32,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_33,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_34,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_35,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_36,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_37,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_38,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_39,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_40,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_41,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_42,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_43,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_44,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_45,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_46,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_47,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_48,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_49,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_50,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_51,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_52,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_53,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_54,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_55,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_56,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_57,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_58,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_59,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_60,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_61,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_62,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_63,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_64,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_65,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_66,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_67,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_68,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_69,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_70,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_71,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_72,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_73,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_74,
+ ALERT_HANDLER_ALERT_CAUSE_0,
+ ALERT_HANDLER_ALERT_CAUSE_1,
+ ALERT_HANDLER_ALERT_CAUSE_2,
+ ALERT_HANDLER_ALERT_CAUSE_3,
+ ALERT_HANDLER_ALERT_CAUSE_4,
+ ALERT_HANDLER_ALERT_CAUSE_5,
+ ALERT_HANDLER_ALERT_CAUSE_6,
+ ALERT_HANDLER_ALERT_CAUSE_7,
+ ALERT_HANDLER_ALERT_CAUSE_8,
+ ALERT_HANDLER_ALERT_CAUSE_9,
+ ALERT_HANDLER_ALERT_CAUSE_10,
+ ALERT_HANDLER_ALERT_CAUSE_11,
+ ALERT_HANDLER_ALERT_CAUSE_12,
+ ALERT_HANDLER_ALERT_CAUSE_13,
+ ALERT_HANDLER_ALERT_CAUSE_14,
+ ALERT_HANDLER_ALERT_CAUSE_15,
+ ALERT_HANDLER_ALERT_CAUSE_16,
+ ALERT_HANDLER_ALERT_CAUSE_17,
+ ALERT_HANDLER_ALERT_CAUSE_18,
+ ALERT_HANDLER_ALERT_CAUSE_19,
+ ALERT_HANDLER_ALERT_CAUSE_20,
+ ALERT_HANDLER_ALERT_CAUSE_21,
+ ALERT_HANDLER_ALERT_CAUSE_22,
+ ALERT_HANDLER_ALERT_CAUSE_23,
+ ALERT_HANDLER_ALERT_CAUSE_24,
+ ALERT_HANDLER_ALERT_CAUSE_25,
+ ALERT_HANDLER_ALERT_CAUSE_26,
+ ALERT_HANDLER_ALERT_CAUSE_27,
+ ALERT_HANDLER_ALERT_CAUSE_28,
+ ALERT_HANDLER_ALERT_CAUSE_29,
+ ALERT_HANDLER_ALERT_CAUSE_30,
+ ALERT_HANDLER_ALERT_CAUSE_31,
+ ALERT_HANDLER_ALERT_CAUSE_32,
+ ALERT_HANDLER_ALERT_CAUSE_33,
+ ALERT_HANDLER_ALERT_CAUSE_34,
+ ALERT_HANDLER_ALERT_CAUSE_35,
+ ALERT_HANDLER_ALERT_CAUSE_36,
+ ALERT_HANDLER_ALERT_CAUSE_37,
+ ALERT_HANDLER_ALERT_CAUSE_38,
+ ALERT_HANDLER_ALERT_CAUSE_39,
+ ALERT_HANDLER_ALERT_CAUSE_40,
+ ALERT_HANDLER_ALERT_CAUSE_41,
+ ALERT_HANDLER_ALERT_CAUSE_42,
+ ALERT_HANDLER_ALERT_CAUSE_43,
+ ALERT_HANDLER_ALERT_CAUSE_44,
+ ALERT_HANDLER_ALERT_CAUSE_45,
+ ALERT_HANDLER_ALERT_CAUSE_46,
+ ALERT_HANDLER_ALERT_CAUSE_47,
+ ALERT_HANDLER_ALERT_CAUSE_48,
+ ALERT_HANDLER_ALERT_CAUSE_49,
+ ALERT_HANDLER_ALERT_CAUSE_50,
+ ALERT_HANDLER_ALERT_CAUSE_51,
+ ALERT_HANDLER_ALERT_CAUSE_52,
+ ALERT_HANDLER_ALERT_CAUSE_53,
+ ALERT_HANDLER_ALERT_CAUSE_54,
+ ALERT_HANDLER_ALERT_CAUSE_55,
+ ALERT_HANDLER_ALERT_CAUSE_56,
+ ALERT_HANDLER_ALERT_CAUSE_57,
+ ALERT_HANDLER_ALERT_CAUSE_58,
+ ALERT_HANDLER_ALERT_CAUSE_59,
+ ALERT_HANDLER_ALERT_CAUSE_60,
+ ALERT_HANDLER_ALERT_CAUSE_61,
+ ALERT_HANDLER_ALERT_CAUSE_62,
+ ALERT_HANDLER_ALERT_CAUSE_63,
+ ALERT_HANDLER_ALERT_CAUSE_64,
+ ALERT_HANDLER_ALERT_CAUSE_65,
+ ALERT_HANDLER_ALERT_CAUSE_66,
+ ALERT_HANDLER_ALERT_CAUSE_67,
+ ALERT_HANDLER_ALERT_CAUSE_68,
+ ALERT_HANDLER_ALERT_CAUSE_69,
+ ALERT_HANDLER_ALERT_CAUSE_70,
+ ALERT_HANDLER_ALERT_CAUSE_71,
+ ALERT_HANDLER_ALERT_CAUSE_72,
+ ALERT_HANDLER_ALERT_CAUSE_73,
+ ALERT_HANDLER_ALERT_CAUSE_74,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_0,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_1,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_2,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_3,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_4,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_5,
+ ALERT_HANDLER_LOC_ALERT_REGWEN_6,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_0,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_1,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_2,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_3,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_4,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_5,
+ ALERT_HANDLER_LOC_ALERT_CAUSE_6,
+ ALERT_HANDLER_CLASSA_REGWEN,
+ ALERT_HANDLER_CLASSA_CTRL_SHADOWED,
+ ALERT_HANDLER_CLASSA_CLR_REGWEN,
+ ALERT_HANDLER_CLASSA_CLR_SHADOWED,
+ ALERT_HANDLER_CLASSA_ACCUM_CNT,
+ ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED,
+ ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED,
+ ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSA_ESC_CNT,
+ ALERT_HANDLER_CLASSA_STATE,
+ ALERT_HANDLER_CLASSB_REGWEN,
+ ALERT_HANDLER_CLASSB_CTRL_SHADOWED,
+ ALERT_HANDLER_CLASSB_CLR_REGWEN,
+ ALERT_HANDLER_CLASSB_CLR_SHADOWED,
+ ALERT_HANDLER_CLASSB_ACCUM_CNT,
+ ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED,
+ ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED,
+ ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSB_ESC_CNT,
+ ALERT_HANDLER_CLASSB_STATE,
+ ALERT_HANDLER_CLASSC_REGWEN,
+ ALERT_HANDLER_CLASSC_CTRL_SHADOWED,
+ ALERT_HANDLER_CLASSC_CLR_REGWEN,
+ ALERT_HANDLER_CLASSC_CLR_SHADOWED,
+ ALERT_HANDLER_CLASSC_ACCUM_CNT,
+ ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED,
+ ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED,
+ ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSC_ESC_CNT,
+ ALERT_HANDLER_CLASSC_STATE,
+ ALERT_HANDLER_CLASSD_REGWEN,
+ ALERT_HANDLER_CLASSD_CTRL_SHADOWED,
+ ALERT_HANDLER_CLASSD_CLR_REGWEN,
+ ALERT_HANDLER_CLASSD_CLR_SHADOWED,
+ ALERT_HANDLER_CLASSD_ACCUM_CNT,
+ ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED,
+ ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED,
+ ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED,
+ ALERT_HANDLER_CLASSD_ESC_CNT,
+ ALERT_HANDLER_CLASSD_STATE
+ } alert_handler_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [390] = '{
+ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
+ 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
+ 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
+ 4'b 0001, // index[ 3] ALERT_HANDLER_PING_TIMER_REGWEN
+ 4'b 0011, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[ 5] ALERT_HANDLER_PING_TIMER_EN_SHADOWED
+ 4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_REGWEN_0
+ 4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_REGWEN_1
+ 4'b 0001, // index[ 8] ALERT_HANDLER_ALERT_REGWEN_2
+ 4'b 0001, // index[ 9] ALERT_HANDLER_ALERT_REGWEN_3
+ 4'b 0001, // index[ 10] ALERT_HANDLER_ALERT_REGWEN_4
+ 4'b 0001, // index[ 11] ALERT_HANDLER_ALERT_REGWEN_5
+ 4'b 0001, // index[ 12] ALERT_HANDLER_ALERT_REGWEN_6
+ 4'b 0001, // index[ 13] ALERT_HANDLER_ALERT_REGWEN_7
+ 4'b 0001, // index[ 14] ALERT_HANDLER_ALERT_REGWEN_8
+ 4'b 0001, // index[ 15] ALERT_HANDLER_ALERT_REGWEN_9
+ 4'b 0001, // index[ 16] ALERT_HANDLER_ALERT_REGWEN_10
+ 4'b 0001, // index[ 17] ALERT_HANDLER_ALERT_REGWEN_11
+ 4'b 0001, // index[ 18] ALERT_HANDLER_ALERT_REGWEN_12
+ 4'b 0001, // index[ 19] ALERT_HANDLER_ALERT_REGWEN_13
+ 4'b 0001, // index[ 20] ALERT_HANDLER_ALERT_REGWEN_14
+ 4'b 0001, // index[ 21] ALERT_HANDLER_ALERT_REGWEN_15
+ 4'b 0001, // index[ 22] ALERT_HANDLER_ALERT_REGWEN_16
+ 4'b 0001, // index[ 23] ALERT_HANDLER_ALERT_REGWEN_17
+ 4'b 0001, // index[ 24] ALERT_HANDLER_ALERT_REGWEN_18
+ 4'b 0001, // index[ 25] ALERT_HANDLER_ALERT_REGWEN_19
+ 4'b 0001, // index[ 26] ALERT_HANDLER_ALERT_REGWEN_20
+ 4'b 0001, // index[ 27] ALERT_HANDLER_ALERT_REGWEN_21
+ 4'b 0001, // index[ 28] ALERT_HANDLER_ALERT_REGWEN_22
+ 4'b 0001, // index[ 29] ALERT_HANDLER_ALERT_REGWEN_23
+ 4'b 0001, // index[ 30] ALERT_HANDLER_ALERT_REGWEN_24
+ 4'b 0001, // index[ 31] ALERT_HANDLER_ALERT_REGWEN_25
+ 4'b 0001, // index[ 32] ALERT_HANDLER_ALERT_REGWEN_26
+ 4'b 0001, // index[ 33] ALERT_HANDLER_ALERT_REGWEN_27
+ 4'b 0001, // index[ 34] ALERT_HANDLER_ALERT_REGWEN_28
+ 4'b 0001, // index[ 35] ALERT_HANDLER_ALERT_REGWEN_29
+ 4'b 0001, // index[ 36] ALERT_HANDLER_ALERT_REGWEN_30
+ 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_REGWEN_31
+ 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_REGWEN_32
+ 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_REGWEN_33
+ 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34
+ 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_REGWEN_35
+ 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_REGWEN_36
+ 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37
+ 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38
+ 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_REGWEN_39
+ 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40
+ 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41
+ 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42
+ 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43
+ 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_REGWEN_44
+ 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45
+ 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46
+ 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47
+ 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_REGWEN_48
+ 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_REGWEN_49
+ 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_REGWEN_50
+ 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_REGWEN_51
+ 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_REGWEN_52
+ 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_REGWEN_53
+ 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_REGWEN_54
+ 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55
+ 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56
+ 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57
+ 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58
+ 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_REGWEN_68
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_REGWEN_69
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_REGWEN_70
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_REGWEN_71
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_REGWEN_72
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_REGWEN_73
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_REGWEN_74
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_7
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_8
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_9
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_10
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_11
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_12
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_13
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_14
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_15
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_16
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_17
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_18
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_19
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_20
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_21
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_22
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_23
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_24
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_25
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_26
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_27
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_28
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_29
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_30
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_31
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_32
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_33
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_34
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_35
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_36
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_37
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_38
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_39
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_40
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_41
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_42
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_43
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_44
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_45
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_46
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_47
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_48
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_49
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_50
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_51
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_52
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_53
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_54
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_55
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_56
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_SHADOWED_57
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_SHADOWED_58
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_SHADOWED_59
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_SHADOWED_60
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_EN_SHADOWED_61
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_EN_SHADOWED_62
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_EN_SHADOWED_63
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_EN_SHADOWED_64
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_EN_SHADOWED_65
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_EN_SHADOWED_66
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_EN_SHADOWED_67
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_EN_SHADOWED_68
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_EN_SHADOWED_69
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_EN_SHADOWED_70
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_EN_SHADOWED_71
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_EN_SHADOWED_72
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_EN_SHADOWED_73
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_EN_SHADOWED_74
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
+ 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
+ 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
+ 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
+ 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
+ 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
+ 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
+ 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
+ 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
+ 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
+ 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
+ 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
+ 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
+ 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
+ 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
+ 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
+ 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
+ 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
+ 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
+ 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
+ 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
+ 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
+ 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
+ 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
+ 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
+ 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
+ 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
+ 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
+ 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
+ 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
+ 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
+ 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
+ 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
+ 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
+ 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
+ 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
+ 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
+ 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
+ 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
+ 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
+ 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
+ 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
+ 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
+ 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
+ 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
+ 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
+ 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59
+ 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60
+ 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61
+ 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62
+ 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63
+ 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64
+ 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65
+ 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66
+ 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67
+ 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68
+ 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69
+ 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70
+ 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71
+ 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72
+ 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73
+ 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74
+ 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_41
+ 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_42
+ 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CAUSE_43
+ 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CAUSE_44
+ 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CAUSE_45
+ 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CAUSE_46
+ 4'b 0001, // index[278] ALERT_HANDLER_ALERT_CAUSE_47
+ 4'b 0001, // index[279] ALERT_HANDLER_ALERT_CAUSE_48
+ 4'b 0001, // index[280] ALERT_HANDLER_ALERT_CAUSE_49
+ 4'b 0001, // index[281] ALERT_HANDLER_ALERT_CAUSE_50
+ 4'b 0001, // index[282] ALERT_HANDLER_ALERT_CAUSE_51
+ 4'b 0001, // index[283] ALERT_HANDLER_ALERT_CAUSE_52
+ 4'b 0001, // index[284] ALERT_HANDLER_ALERT_CAUSE_53
+ 4'b 0001, // index[285] ALERT_HANDLER_ALERT_CAUSE_54
+ 4'b 0001, // index[286] ALERT_HANDLER_ALERT_CAUSE_55
+ 4'b 0001, // index[287] ALERT_HANDLER_ALERT_CAUSE_56
+ 4'b 0001, // index[288] ALERT_HANDLER_ALERT_CAUSE_57
+ 4'b 0001, // index[289] ALERT_HANDLER_ALERT_CAUSE_58
+ 4'b 0001, // index[290] ALERT_HANDLER_ALERT_CAUSE_59
+ 4'b 0001, // index[291] ALERT_HANDLER_ALERT_CAUSE_60
+ 4'b 0001, // index[292] ALERT_HANDLER_ALERT_CAUSE_61
+ 4'b 0001, // index[293] ALERT_HANDLER_ALERT_CAUSE_62
+ 4'b 0001, // index[294] ALERT_HANDLER_ALERT_CAUSE_63
+ 4'b 0001, // index[295] ALERT_HANDLER_ALERT_CAUSE_64
+ 4'b 0001, // index[296] ALERT_HANDLER_ALERT_CAUSE_65
+ 4'b 0001, // index[297] ALERT_HANDLER_ALERT_CAUSE_66
+ 4'b 0001, // index[298] ALERT_HANDLER_ALERT_CAUSE_67
+ 4'b 0001, // index[299] ALERT_HANDLER_ALERT_CAUSE_68
+ 4'b 0001, // index[300] ALERT_HANDLER_ALERT_CAUSE_69
+ 4'b 0001, // index[301] ALERT_HANDLER_ALERT_CAUSE_70
+ 4'b 0001, // index[302] ALERT_HANDLER_ALERT_CAUSE_71
+ 4'b 0001, // index[303] ALERT_HANDLER_ALERT_CAUSE_72
+ 4'b 0001, // index[304] ALERT_HANDLER_ALERT_CAUSE_73
+ 4'b 0001, // index[305] ALERT_HANDLER_ALERT_CAUSE_74
+ 4'b 0001, // index[306] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[307] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[308] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[309] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[310] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[311] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+ 4'b 0001, // index[312] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+ 4'b 0001, // index[313] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[314] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[315] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[316] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[317] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[318] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[319] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[320] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[321] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[322] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[323] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[324] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[325] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[326] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[327] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[328] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[329] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[330] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[331] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[332] ALERT_HANDLER_LOC_ALERT_CAUSE_5
+ 4'b 0001, // index[333] ALERT_HANDLER_LOC_ALERT_CAUSE_6
+ 4'b 0001, // index[334] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[335] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
+ 4'b 0001, // index[336] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[337] ALERT_HANDLER_CLASSA_CLR_SHADOWED
+ 4'b 0011, // index[338] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[339] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[340] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[341] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[342] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[343] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[344] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[345] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[346] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[347] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[348] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[349] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
+ 4'b 0001, // index[350] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[351] ALERT_HANDLER_CLASSB_CLR_SHADOWED
+ 4'b 0011, // index[352] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[353] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[354] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[355] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[356] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[357] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[358] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[359] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[360] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[361] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[362] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[363] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
+ 4'b 0001, // index[364] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[365] ALERT_HANDLER_CLASSC_CLR_SHADOWED
+ 4'b 0011, // index[366] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[367] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[368] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[369] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[370] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[371] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[372] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[373] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[374] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[375] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[376] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[377] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
+ 4'b 0001, // index[378] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[379] ALERT_HANDLER_CLASSD_CLR_SHADOWED
+ 4'b 0011, // index[380] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[381] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[382] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[383] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[384] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[385] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[386] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[387] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[388] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[389] ALERT_HANDLER_CLASSD_STATE
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
new file mode 100644
index 0000000..141c82b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
@@ -0,0 +1,21500 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module alert_handler_reg_top (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
+ input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
+
+ output logic shadowed_storage_err_o,
+ output logic shadowed_update_err_o,
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import alert_handler_reg_pkg::* ;
+
+ localparam int AW = 11;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [389:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(390)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_we;
+ logic intr_state_classa_qs;
+ logic intr_state_classa_wd;
+ logic intr_state_classb_qs;
+ logic intr_state_classb_wd;
+ logic intr_state_classc_qs;
+ logic intr_state_classc_wd;
+ logic intr_state_classd_qs;
+ logic intr_state_classd_wd;
+ logic intr_enable_we;
+ logic intr_enable_classa_qs;
+ logic intr_enable_classa_wd;
+ logic intr_enable_classb_qs;
+ logic intr_enable_classb_wd;
+ logic intr_enable_classc_qs;
+ logic intr_enable_classc_wd;
+ logic intr_enable_classd_qs;
+ logic intr_enable_classd_wd;
+ logic intr_test_we;
+ logic intr_test_classa_wd;
+ logic intr_test_classb_wd;
+ logic intr_test_classc_wd;
+ logic intr_test_classd_wd;
+ logic ping_timer_regwen_we;
+ logic ping_timer_regwen_qs;
+ logic ping_timer_regwen_wd;
+ logic ping_timeout_cyc_shadowed_re;
+ logic ping_timeout_cyc_shadowed_we;
+ logic [15:0] ping_timeout_cyc_shadowed_qs;
+ logic [15:0] ping_timeout_cyc_shadowed_wd;
+ logic ping_timeout_cyc_shadowed_storage_err;
+ logic ping_timeout_cyc_shadowed_update_err;
+ logic ping_timer_en_shadowed_re;
+ logic ping_timer_en_shadowed_we;
+ logic ping_timer_en_shadowed_qs;
+ logic ping_timer_en_shadowed_wd;
+ logic ping_timer_en_shadowed_storage_err;
+ logic ping_timer_en_shadowed_update_err;
+ logic alert_regwen_0_we;
+ logic alert_regwen_0_qs;
+ logic alert_regwen_0_wd;
+ logic alert_regwen_1_we;
+ logic alert_regwen_1_qs;
+ logic alert_regwen_1_wd;
+ logic alert_regwen_2_we;
+ logic alert_regwen_2_qs;
+ logic alert_regwen_2_wd;
+ logic alert_regwen_3_we;
+ logic alert_regwen_3_qs;
+ logic alert_regwen_3_wd;
+ logic alert_regwen_4_we;
+ logic alert_regwen_4_qs;
+ logic alert_regwen_4_wd;
+ logic alert_regwen_5_we;
+ logic alert_regwen_5_qs;
+ logic alert_regwen_5_wd;
+ logic alert_regwen_6_we;
+ logic alert_regwen_6_qs;
+ logic alert_regwen_6_wd;
+ logic alert_regwen_7_we;
+ logic alert_regwen_7_qs;
+ logic alert_regwen_7_wd;
+ logic alert_regwen_8_we;
+ logic alert_regwen_8_qs;
+ logic alert_regwen_8_wd;
+ logic alert_regwen_9_we;
+ logic alert_regwen_9_qs;
+ logic alert_regwen_9_wd;
+ logic alert_regwen_10_we;
+ logic alert_regwen_10_qs;
+ logic alert_regwen_10_wd;
+ logic alert_regwen_11_we;
+ logic alert_regwen_11_qs;
+ logic alert_regwen_11_wd;
+ logic alert_regwen_12_we;
+ logic alert_regwen_12_qs;
+ logic alert_regwen_12_wd;
+ logic alert_regwen_13_we;
+ logic alert_regwen_13_qs;
+ logic alert_regwen_13_wd;
+ logic alert_regwen_14_we;
+ logic alert_regwen_14_qs;
+ logic alert_regwen_14_wd;
+ logic alert_regwen_15_we;
+ logic alert_regwen_15_qs;
+ logic alert_regwen_15_wd;
+ logic alert_regwen_16_we;
+ logic alert_regwen_16_qs;
+ logic alert_regwen_16_wd;
+ logic alert_regwen_17_we;
+ logic alert_regwen_17_qs;
+ logic alert_regwen_17_wd;
+ logic alert_regwen_18_we;
+ logic alert_regwen_18_qs;
+ logic alert_regwen_18_wd;
+ logic alert_regwen_19_we;
+ logic alert_regwen_19_qs;
+ logic alert_regwen_19_wd;
+ logic alert_regwen_20_we;
+ logic alert_regwen_20_qs;
+ logic alert_regwen_20_wd;
+ logic alert_regwen_21_we;
+ logic alert_regwen_21_qs;
+ logic alert_regwen_21_wd;
+ logic alert_regwen_22_we;
+ logic alert_regwen_22_qs;
+ logic alert_regwen_22_wd;
+ logic alert_regwen_23_we;
+ logic alert_regwen_23_qs;
+ logic alert_regwen_23_wd;
+ logic alert_regwen_24_we;
+ logic alert_regwen_24_qs;
+ logic alert_regwen_24_wd;
+ logic alert_regwen_25_we;
+ logic alert_regwen_25_qs;
+ logic alert_regwen_25_wd;
+ logic alert_regwen_26_we;
+ logic alert_regwen_26_qs;
+ logic alert_regwen_26_wd;
+ logic alert_regwen_27_we;
+ logic alert_regwen_27_qs;
+ logic alert_regwen_27_wd;
+ logic alert_regwen_28_we;
+ logic alert_regwen_28_qs;
+ logic alert_regwen_28_wd;
+ logic alert_regwen_29_we;
+ logic alert_regwen_29_qs;
+ logic alert_regwen_29_wd;
+ logic alert_regwen_30_we;
+ logic alert_regwen_30_qs;
+ logic alert_regwen_30_wd;
+ logic alert_regwen_31_we;
+ logic alert_regwen_31_qs;
+ logic alert_regwen_31_wd;
+ logic alert_regwen_32_we;
+ logic alert_regwen_32_qs;
+ logic alert_regwen_32_wd;
+ logic alert_regwen_33_we;
+ logic alert_regwen_33_qs;
+ logic alert_regwen_33_wd;
+ logic alert_regwen_34_we;
+ logic alert_regwen_34_qs;
+ logic alert_regwen_34_wd;
+ logic alert_regwen_35_we;
+ logic alert_regwen_35_qs;
+ logic alert_regwen_35_wd;
+ logic alert_regwen_36_we;
+ logic alert_regwen_36_qs;
+ logic alert_regwen_36_wd;
+ logic alert_regwen_37_we;
+ logic alert_regwen_37_qs;
+ logic alert_regwen_37_wd;
+ logic alert_regwen_38_we;
+ logic alert_regwen_38_qs;
+ logic alert_regwen_38_wd;
+ logic alert_regwen_39_we;
+ logic alert_regwen_39_qs;
+ logic alert_regwen_39_wd;
+ logic alert_regwen_40_we;
+ logic alert_regwen_40_qs;
+ logic alert_regwen_40_wd;
+ logic alert_regwen_41_we;
+ logic alert_regwen_41_qs;
+ logic alert_regwen_41_wd;
+ logic alert_regwen_42_we;
+ logic alert_regwen_42_qs;
+ logic alert_regwen_42_wd;
+ logic alert_regwen_43_we;
+ logic alert_regwen_43_qs;
+ logic alert_regwen_43_wd;
+ logic alert_regwen_44_we;
+ logic alert_regwen_44_qs;
+ logic alert_regwen_44_wd;
+ logic alert_regwen_45_we;
+ logic alert_regwen_45_qs;
+ logic alert_regwen_45_wd;
+ logic alert_regwen_46_we;
+ logic alert_regwen_46_qs;
+ logic alert_regwen_46_wd;
+ logic alert_regwen_47_we;
+ logic alert_regwen_47_qs;
+ logic alert_regwen_47_wd;
+ logic alert_regwen_48_we;
+ logic alert_regwen_48_qs;
+ logic alert_regwen_48_wd;
+ logic alert_regwen_49_we;
+ logic alert_regwen_49_qs;
+ logic alert_regwen_49_wd;
+ logic alert_regwen_50_we;
+ logic alert_regwen_50_qs;
+ logic alert_regwen_50_wd;
+ logic alert_regwen_51_we;
+ logic alert_regwen_51_qs;
+ logic alert_regwen_51_wd;
+ logic alert_regwen_52_we;
+ logic alert_regwen_52_qs;
+ logic alert_regwen_52_wd;
+ logic alert_regwen_53_we;
+ logic alert_regwen_53_qs;
+ logic alert_regwen_53_wd;
+ logic alert_regwen_54_we;
+ logic alert_regwen_54_qs;
+ logic alert_regwen_54_wd;
+ logic alert_regwen_55_we;
+ logic alert_regwen_55_qs;
+ logic alert_regwen_55_wd;
+ logic alert_regwen_56_we;
+ logic alert_regwen_56_qs;
+ logic alert_regwen_56_wd;
+ logic alert_regwen_57_we;
+ logic alert_regwen_57_qs;
+ logic alert_regwen_57_wd;
+ logic alert_regwen_58_we;
+ logic alert_regwen_58_qs;
+ logic alert_regwen_58_wd;
+ logic alert_regwen_59_we;
+ logic alert_regwen_59_qs;
+ logic alert_regwen_59_wd;
+ logic alert_regwen_60_we;
+ logic alert_regwen_60_qs;
+ logic alert_regwen_60_wd;
+ logic alert_regwen_61_we;
+ logic alert_regwen_61_qs;
+ logic alert_regwen_61_wd;
+ logic alert_regwen_62_we;
+ logic alert_regwen_62_qs;
+ logic alert_regwen_62_wd;
+ logic alert_regwen_63_we;
+ logic alert_regwen_63_qs;
+ logic alert_regwen_63_wd;
+ logic alert_regwen_64_we;
+ logic alert_regwen_64_qs;
+ logic alert_regwen_64_wd;
+ logic alert_regwen_65_we;
+ logic alert_regwen_65_qs;
+ logic alert_regwen_65_wd;
+ logic alert_regwen_66_we;
+ logic alert_regwen_66_qs;
+ logic alert_regwen_66_wd;
+ logic alert_regwen_67_we;
+ logic alert_regwen_67_qs;
+ logic alert_regwen_67_wd;
+ logic alert_regwen_68_we;
+ logic alert_regwen_68_qs;
+ logic alert_regwen_68_wd;
+ logic alert_regwen_69_we;
+ logic alert_regwen_69_qs;
+ logic alert_regwen_69_wd;
+ logic alert_regwen_70_we;
+ logic alert_regwen_70_qs;
+ logic alert_regwen_70_wd;
+ logic alert_regwen_71_we;
+ logic alert_regwen_71_qs;
+ logic alert_regwen_71_wd;
+ logic alert_regwen_72_we;
+ logic alert_regwen_72_qs;
+ logic alert_regwen_72_wd;
+ logic alert_regwen_73_we;
+ logic alert_regwen_73_qs;
+ logic alert_regwen_73_wd;
+ logic alert_regwen_74_we;
+ logic alert_regwen_74_qs;
+ logic alert_regwen_74_wd;
+ logic alert_en_shadowed_0_re;
+ logic alert_en_shadowed_0_we;
+ logic alert_en_shadowed_0_qs;
+ logic alert_en_shadowed_0_wd;
+ logic alert_en_shadowed_0_storage_err;
+ logic alert_en_shadowed_0_update_err;
+ logic alert_en_shadowed_1_re;
+ logic alert_en_shadowed_1_we;
+ logic alert_en_shadowed_1_qs;
+ logic alert_en_shadowed_1_wd;
+ logic alert_en_shadowed_1_storage_err;
+ logic alert_en_shadowed_1_update_err;
+ logic alert_en_shadowed_2_re;
+ logic alert_en_shadowed_2_we;
+ logic alert_en_shadowed_2_qs;
+ logic alert_en_shadowed_2_wd;
+ logic alert_en_shadowed_2_storage_err;
+ logic alert_en_shadowed_2_update_err;
+ logic alert_en_shadowed_3_re;
+ logic alert_en_shadowed_3_we;
+ logic alert_en_shadowed_3_qs;
+ logic alert_en_shadowed_3_wd;
+ logic alert_en_shadowed_3_storage_err;
+ logic alert_en_shadowed_3_update_err;
+ logic alert_en_shadowed_4_re;
+ logic alert_en_shadowed_4_we;
+ logic alert_en_shadowed_4_qs;
+ logic alert_en_shadowed_4_wd;
+ logic alert_en_shadowed_4_storage_err;
+ logic alert_en_shadowed_4_update_err;
+ logic alert_en_shadowed_5_re;
+ logic alert_en_shadowed_5_we;
+ logic alert_en_shadowed_5_qs;
+ logic alert_en_shadowed_5_wd;
+ logic alert_en_shadowed_5_storage_err;
+ logic alert_en_shadowed_5_update_err;
+ logic alert_en_shadowed_6_re;
+ logic alert_en_shadowed_6_we;
+ logic alert_en_shadowed_6_qs;
+ logic alert_en_shadowed_6_wd;
+ logic alert_en_shadowed_6_storage_err;
+ logic alert_en_shadowed_6_update_err;
+ logic alert_en_shadowed_7_re;
+ logic alert_en_shadowed_7_we;
+ logic alert_en_shadowed_7_qs;
+ logic alert_en_shadowed_7_wd;
+ logic alert_en_shadowed_7_storage_err;
+ logic alert_en_shadowed_7_update_err;
+ logic alert_en_shadowed_8_re;
+ logic alert_en_shadowed_8_we;
+ logic alert_en_shadowed_8_qs;
+ logic alert_en_shadowed_8_wd;
+ logic alert_en_shadowed_8_storage_err;
+ logic alert_en_shadowed_8_update_err;
+ logic alert_en_shadowed_9_re;
+ logic alert_en_shadowed_9_we;
+ logic alert_en_shadowed_9_qs;
+ logic alert_en_shadowed_9_wd;
+ logic alert_en_shadowed_9_storage_err;
+ logic alert_en_shadowed_9_update_err;
+ logic alert_en_shadowed_10_re;
+ logic alert_en_shadowed_10_we;
+ logic alert_en_shadowed_10_qs;
+ logic alert_en_shadowed_10_wd;
+ logic alert_en_shadowed_10_storage_err;
+ logic alert_en_shadowed_10_update_err;
+ logic alert_en_shadowed_11_re;
+ logic alert_en_shadowed_11_we;
+ logic alert_en_shadowed_11_qs;
+ logic alert_en_shadowed_11_wd;
+ logic alert_en_shadowed_11_storage_err;
+ logic alert_en_shadowed_11_update_err;
+ logic alert_en_shadowed_12_re;
+ logic alert_en_shadowed_12_we;
+ logic alert_en_shadowed_12_qs;
+ logic alert_en_shadowed_12_wd;
+ logic alert_en_shadowed_12_storage_err;
+ logic alert_en_shadowed_12_update_err;
+ logic alert_en_shadowed_13_re;
+ logic alert_en_shadowed_13_we;
+ logic alert_en_shadowed_13_qs;
+ logic alert_en_shadowed_13_wd;
+ logic alert_en_shadowed_13_storage_err;
+ logic alert_en_shadowed_13_update_err;
+ logic alert_en_shadowed_14_re;
+ logic alert_en_shadowed_14_we;
+ logic alert_en_shadowed_14_qs;
+ logic alert_en_shadowed_14_wd;
+ logic alert_en_shadowed_14_storage_err;
+ logic alert_en_shadowed_14_update_err;
+ logic alert_en_shadowed_15_re;
+ logic alert_en_shadowed_15_we;
+ logic alert_en_shadowed_15_qs;
+ logic alert_en_shadowed_15_wd;
+ logic alert_en_shadowed_15_storage_err;
+ logic alert_en_shadowed_15_update_err;
+ logic alert_en_shadowed_16_re;
+ logic alert_en_shadowed_16_we;
+ logic alert_en_shadowed_16_qs;
+ logic alert_en_shadowed_16_wd;
+ logic alert_en_shadowed_16_storage_err;
+ logic alert_en_shadowed_16_update_err;
+ logic alert_en_shadowed_17_re;
+ logic alert_en_shadowed_17_we;
+ logic alert_en_shadowed_17_qs;
+ logic alert_en_shadowed_17_wd;
+ logic alert_en_shadowed_17_storage_err;
+ logic alert_en_shadowed_17_update_err;
+ logic alert_en_shadowed_18_re;
+ logic alert_en_shadowed_18_we;
+ logic alert_en_shadowed_18_qs;
+ logic alert_en_shadowed_18_wd;
+ logic alert_en_shadowed_18_storage_err;
+ logic alert_en_shadowed_18_update_err;
+ logic alert_en_shadowed_19_re;
+ logic alert_en_shadowed_19_we;
+ logic alert_en_shadowed_19_qs;
+ logic alert_en_shadowed_19_wd;
+ logic alert_en_shadowed_19_storage_err;
+ logic alert_en_shadowed_19_update_err;
+ logic alert_en_shadowed_20_re;
+ logic alert_en_shadowed_20_we;
+ logic alert_en_shadowed_20_qs;
+ logic alert_en_shadowed_20_wd;
+ logic alert_en_shadowed_20_storage_err;
+ logic alert_en_shadowed_20_update_err;
+ logic alert_en_shadowed_21_re;
+ logic alert_en_shadowed_21_we;
+ logic alert_en_shadowed_21_qs;
+ logic alert_en_shadowed_21_wd;
+ logic alert_en_shadowed_21_storage_err;
+ logic alert_en_shadowed_21_update_err;
+ logic alert_en_shadowed_22_re;
+ logic alert_en_shadowed_22_we;
+ logic alert_en_shadowed_22_qs;
+ logic alert_en_shadowed_22_wd;
+ logic alert_en_shadowed_22_storage_err;
+ logic alert_en_shadowed_22_update_err;
+ logic alert_en_shadowed_23_re;
+ logic alert_en_shadowed_23_we;
+ logic alert_en_shadowed_23_qs;
+ logic alert_en_shadowed_23_wd;
+ logic alert_en_shadowed_23_storage_err;
+ logic alert_en_shadowed_23_update_err;
+ logic alert_en_shadowed_24_re;
+ logic alert_en_shadowed_24_we;
+ logic alert_en_shadowed_24_qs;
+ logic alert_en_shadowed_24_wd;
+ logic alert_en_shadowed_24_storage_err;
+ logic alert_en_shadowed_24_update_err;
+ logic alert_en_shadowed_25_re;
+ logic alert_en_shadowed_25_we;
+ logic alert_en_shadowed_25_qs;
+ logic alert_en_shadowed_25_wd;
+ logic alert_en_shadowed_25_storage_err;
+ logic alert_en_shadowed_25_update_err;
+ logic alert_en_shadowed_26_re;
+ logic alert_en_shadowed_26_we;
+ logic alert_en_shadowed_26_qs;
+ logic alert_en_shadowed_26_wd;
+ logic alert_en_shadowed_26_storage_err;
+ logic alert_en_shadowed_26_update_err;
+ logic alert_en_shadowed_27_re;
+ logic alert_en_shadowed_27_we;
+ logic alert_en_shadowed_27_qs;
+ logic alert_en_shadowed_27_wd;
+ logic alert_en_shadowed_27_storage_err;
+ logic alert_en_shadowed_27_update_err;
+ logic alert_en_shadowed_28_re;
+ logic alert_en_shadowed_28_we;
+ logic alert_en_shadowed_28_qs;
+ logic alert_en_shadowed_28_wd;
+ logic alert_en_shadowed_28_storage_err;
+ logic alert_en_shadowed_28_update_err;
+ logic alert_en_shadowed_29_re;
+ logic alert_en_shadowed_29_we;
+ logic alert_en_shadowed_29_qs;
+ logic alert_en_shadowed_29_wd;
+ logic alert_en_shadowed_29_storage_err;
+ logic alert_en_shadowed_29_update_err;
+ logic alert_en_shadowed_30_re;
+ logic alert_en_shadowed_30_we;
+ logic alert_en_shadowed_30_qs;
+ logic alert_en_shadowed_30_wd;
+ logic alert_en_shadowed_30_storage_err;
+ logic alert_en_shadowed_30_update_err;
+ logic alert_en_shadowed_31_re;
+ logic alert_en_shadowed_31_we;
+ logic alert_en_shadowed_31_qs;
+ logic alert_en_shadowed_31_wd;
+ logic alert_en_shadowed_31_storage_err;
+ logic alert_en_shadowed_31_update_err;
+ logic alert_en_shadowed_32_re;
+ logic alert_en_shadowed_32_we;
+ logic alert_en_shadowed_32_qs;
+ logic alert_en_shadowed_32_wd;
+ logic alert_en_shadowed_32_storage_err;
+ logic alert_en_shadowed_32_update_err;
+ logic alert_en_shadowed_33_re;
+ logic alert_en_shadowed_33_we;
+ logic alert_en_shadowed_33_qs;
+ logic alert_en_shadowed_33_wd;
+ logic alert_en_shadowed_33_storage_err;
+ logic alert_en_shadowed_33_update_err;
+ logic alert_en_shadowed_34_re;
+ logic alert_en_shadowed_34_we;
+ logic alert_en_shadowed_34_qs;
+ logic alert_en_shadowed_34_wd;
+ logic alert_en_shadowed_34_storage_err;
+ logic alert_en_shadowed_34_update_err;
+ logic alert_en_shadowed_35_re;
+ logic alert_en_shadowed_35_we;
+ logic alert_en_shadowed_35_qs;
+ logic alert_en_shadowed_35_wd;
+ logic alert_en_shadowed_35_storage_err;
+ logic alert_en_shadowed_35_update_err;
+ logic alert_en_shadowed_36_re;
+ logic alert_en_shadowed_36_we;
+ logic alert_en_shadowed_36_qs;
+ logic alert_en_shadowed_36_wd;
+ logic alert_en_shadowed_36_storage_err;
+ logic alert_en_shadowed_36_update_err;
+ logic alert_en_shadowed_37_re;
+ logic alert_en_shadowed_37_we;
+ logic alert_en_shadowed_37_qs;
+ logic alert_en_shadowed_37_wd;
+ logic alert_en_shadowed_37_storage_err;
+ logic alert_en_shadowed_37_update_err;
+ logic alert_en_shadowed_38_re;
+ logic alert_en_shadowed_38_we;
+ logic alert_en_shadowed_38_qs;
+ logic alert_en_shadowed_38_wd;
+ logic alert_en_shadowed_38_storage_err;
+ logic alert_en_shadowed_38_update_err;
+ logic alert_en_shadowed_39_re;
+ logic alert_en_shadowed_39_we;
+ logic alert_en_shadowed_39_qs;
+ logic alert_en_shadowed_39_wd;
+ logic alert_en_shadowed_39_storage_err;
+ logic alert_en_shadowed_39_update_err;
+ logic alert_en_shadowed_40_re;
+ logic alert_en_shadowed_40_we;
+ logic alert_en_shadowed_40_qs;
+ logic alert_en_shadowed_40_wd;
+ logic alert_en_shadowed_40_storage_err;
+ logic alert_en_shadowed_40_update_err;
+ logic alert_en_shadowed_41_re;
+ logic alert_en_shadowed_41_we;
+ logic alert_en_shadowed_41_qs;
+ logic alert_en_shadowed_41_wd;
+ logic alert_en_shadowed_41_storage_err;
+ logic alert_en_shadowed_41_update_err;
+ logic alert_en_shadowed_42_re;
+ logic alert_en_shadowed_42_we;
+ logic alert_en_shadowed_42_qs;
+ logic alert_en_shadowed_42_wd;
+ logic alert_en_shadowed_42_storage_err;
+ logic alert_en_shadowed_42_update_err;
+ logic alert_en_shadowed_43_re;
+ logic alert_en_shadowed_43_we;
+ logic alert_en_shadowed_43_qs;
+ logic alert_en_shadowed_43_wd;
+ logic alert_en_shadowed_43_storage_err;
+ logic alert_en_shadowed_43_update_err;
+ logic alert_en_shadowed_44_re;
+ logic alert_en_shadowed_44_we;
+ logic alert_en_shadowed_44_qs;
+ logic alert_en_shadowed_44_wd;
+ logic alert_en_shadowed_44_storage_err;
+ logic alert_en_shadowed_44_update_err;
+ logic alert_en_shadowed_45_re;
+ logic alert_en_shadowed_45_we;
+ logic alert_en_shadowed_45_qs;
+ logic alert_en_shadowed_45_wd;
+ logic alert_en_shadowed_45_storage_err;
+ logic alert_en_shadowed_45_update_err;
+ logic alert_en_shadowed_46_re;
+ logic alert_en_shadowed_46_we;
+ logic alert_en_shadowed_46_qs;
+ logic alert_en_shadowed_46_wd;
+ logic alert_en_shadowed_46_storage_err;
+ logic alert_en_shadowed_46_update_err;
+ logic alert_en_shadowed_47_re;
+ logic alert_en_shadowed_47_we;
+ logic alert_en_shadowed_47_qs;
+ logic alert_en_shadowed_47_wd;
+ logic alert_en_shadowed_47_storage_err;
+ logic alert_en_shadowed_47_update_err;
+ logic alert_en_shadowed_48_re;
+ logic alert_en_shadowed_48_we;
+ logic alert_en_shadowed_48_qs;
+ logic alert_en_shadowed_48_wd;
+ logic alert_en_shadowed_48_storage_err;
+ logic alert_en_shadowed_48_update_err;
+ logic alert_en_shadowed_49_re;
+ logic alert_en_shadowed_49_we;
+ logic alert_en_shadowed_49_qs;
+ logic alert_en_shadowed_49_wd;
+ logic alert_en_shadowed_49_storage_err;
+ logic alert_en_shadowed_49_update_err;
+ logic alert_en_shadowed_50_re;
+ logic alert_en_shadowed_50_we;
+ logic alert_en_shadowed_50_qs;
+ logic alert_en_shadowed_50_wd;
+ logic alert_en_shadowed_50_storage_err;
+ logic alert_en_shadowed_50_update_err;
+ logic alert_en_shadowed_51_re;
+ logic alert_en_shadowed_51_we;
+ logic alert_en_shadowed_51_qs;
+ logic alert_en_shadowed_51_wd;
+ logic alert_en_shadowed_51_storage_err;
+ logic alert_en_shadowed_51_update_err;
+ logic alert_en_shadowed_52_re;
+ logic alert_en_shadowed_52_we;
+ logic alert_en_shadowed_52_qs;
+ logic alert_en_shadowed_52_wd;
+ logic alert_en_shadowed_52_storage_err;
+ logic alert_en_shadowed_52_update_err;
+ logic alert_en_shadowed_53_re;
+ logic alert_en_shadowed_53_we;
+ logic alert_en_shadowed_53_qs;
+ logic alert_en_shadowed_53_wd;
+ logic alert_en_shadowed_53_storage_err;
+ logic alert_en_shadowed_53_update_err;
+ logic alert_en_shadowed_54_re;
+ logic alert_en_shadowed_54_we;
+ logic alert_en_shadowed_54_qs;
+ logic alert_en_shadowed_54_wd;
+ logic alert_en_shadowed_54_storage_err;
+ logic alert_en_shadowed_54_update_err;
+ logic alert_en_shadowed_55_re;
+ logic alert_en_shadowed_55_we;
+ logic alert_en_shadowed_55_qs;
+ logic alert_en_shadowed_55_wd;
+ logic alert_en_shadowed_55_storage_err;
+ logic alert_en_shadowed_55_update_err;
+ logic alert_en_shadowed_56_re;
+ logic alert_en_shadowed_56_we;
+ logic alert_en_shadowed_56_qs;
+ logic alert_en_shadowed_56_wd;
+ logic alert_en_shadowed_56_storage_err;
+ logic alert_en_shadowed_56_update_err;
+ logic alert_en_shadowed_57_re;
+ logic alert_en_shadowed_57_we;
+ logic alert_en_shadowed_57_qs;
+ logic alert_en_shadowed_57_wd;
+ logic alert_en_shadowed_57_storage_err;
+ logic alert_en_shadowed_57_update_err;
+ logic alert_en_shadowed_58_re;
+ logic alert_en_shadowed_58_we;
+ logic alert_en_shadowed_58_qs;
+ logic alert_en_shadowed_58_wd;
+ logic alert_en_shadowed_58_storage_err;
+ logic alert_en_shadowed_58_update_err;
+ logic alert_en_shadowed_59_re;
+ logic alert_en_shadowed_59_we;
+ logic alert_en_shadowed_59_qs;
+ logic alert_en_shadowed_59_wd;
+ logic alert_en_shadowed_59_storage_err;
+ logic alert_en_shadowed_59_update_err;
+ logic alert_en_shadowed_60_re;
+ logic alert_en_shadowed_60_we;
+ logic alert_en_shadowed_60_qs;
+ logic alert_en_shadowed_60_wd;
+ logic alert_en_shadowed_60_storage_err;
+ logic alert_en_shadowed_60_update_err;
+ logic alert_en_shadowed_61_re;
+ logic alert_en_shadowed_61_we;
+ logic alert_en_shadowed_61_qs;
+ logic alert_en_shadowed_61_wd;
+ logic alert_en_shadowed_61_storage_err;
+ logic alert_en_shadowed_61_update_err;
+ logic alert_en_shadowed_62_re;
+ logic alert_en_shadowed_62_we;
+ logic alert_en_shadowed_62_qs;
+ logic alert_en_shadowed_62_wd;
+ logic alert_en_shadowed_62_storage_err;
+ logic alert_en_shadowed_62_update_err;
+ logic alert_en_shadowed_63_re;
+ logic alert_en_shadowed_63_we;
+ logic alert_en_shadowed_63_qs;
+ logic alert_en_shadowed_63_wd;
+ logic alert_en_shadowed_63_storage_err;
+ logic alert_en_shadowed_63_update_err;
+ logic alert_en_shadowed_64_re;
+ logic alert_en_shadowed_64_we;
+ logic alert_en_shadowed_64_qs;
+ logic alert_en_shadowed_64_wd;
+ logic alert_en_shadowed_64_storage_err;
+ logic alert_en_shadowed_64_update_err;
+ logic alert_en_shadowed_65_re;
+ logic alert_en_shadowed_65_we;
+ logic alert_en_shadowed_65_qs;
+ logic alert_en_shadowed_65_wd;
+ logic alert_en_shadowed_65_storage_err;
+ logic alert_en_shadowed_65_update_err;
+ logic alert_en_shadowed_66_re;
+ logic alert_en_shadowed_66_we;
+ logic alert_en_shadowed_66_qs;
+ logic alert_en_shadowed_66_wd;
+ logic alert_en_shadowed_66_storage_err;
+ logic alert_en_shadowed_66_update_err;
+ logic alert_en_shadowed_67_re;
+ logic alert_en_shadowed_67_we;
+ logic alert_en_shadowed_67_qs;
+ logic alert_en_shadowed_67_wd;
+ logic alert_en_shadowed_67_storage_err;
+ logic alert_en_shadowed_67_update_err;
+ logic alert_en_shadowed_68_re;
+ logic alert_en_shadowed_68_we;
+ logic alert_en_shadowed_68_qs;
+ logic alert_en_shadowed_68_wd;
+ logic alert_en_shadowed_68_storage_err;
+ logic alert_en_shadowed_68_update_err;
+ logic alert_en_shadowed_69_re;
+ logic alert_en_shadowed_69_we;
+ logic alert_en_shadowed_69_qs;
+ logic alert_en_shadowed_69_wd;
+ logic alert_en_shadowed_69_storage_err;
+ logic alert_en_shadowed_69_update_err;
+ logic alert_en_shadowed_70_re;
+ logic alert_en_shadowed_70_we;
+ logic alert_en_shadowed_70_qs;
+ logic alert_en_shadowed_70_wd;
+ logic alert_en_shadowed_70_storage_err;
+ logic alert_en_shadowed_70_update_err;
+ logic alert_en_shadowed_71_re;
+ logic alert_en_shadowed_71_we;
+ logic alert_en_shadowed_71_qs;
+ logic alert_en_shadowed_71_wd;
+ logic alert_en_shadowed_71_storage_err;
+ logic alert_en_shadowed_71_update_err;
+ logic alert_en_shadowed_72_re;
+ logic alert_en_shadowed_72_we;
+ logic alert_en_shadowed_72_qs;
+ logic alert_en_shadowed_72_wd;
+ logic alert_en_shadowed_72_storage_err;
+ logic alert_en_shadowed_72_update_err;
+ logic alert_en_shadowed_73_re;
+ logic alert_en_shadowed_73_we;
+ logic alert_en_shadowed_73_qs;
+ logic alert_en_shadowed_73_wd;
+ logic alert_en_shadowed_73_storage_err;
+ logic alert_en_shadowed_73_update_err;
+ logic alert_en_shadowed_74_re;
+ logic alert_en_shadowed_74_we;
+ logic alert_en_shadowed_74_qs;
+ logic alert_en_shadowed_74_wd;
+ logic alert_en_shadowed_74_storage_err;
+ logic alert_en_shadowed_74_update_err;
+ logic alert_class_shadowed_0_re;
+ logic alert_class_shadowed_0_we;
+ logic [1:0] alert_class_shadowed_0_qs;
+ logic [1:0] alert_class_shadowed_0_wd;
+ logic alert_class_shadowed_0_storage_err;
+ logic alert_class_shadowed_0_update_err;
+ logic alert_class_shadowed_1_re;
+ logic alert_class_shadowed_1_we;
+ logic [1:0] alert_class_shadowed_1_qs;
+ logic [1:0] alert_class_shadowed_1_wd;
+ logic alert_class_shadowed_1_storage_err;
+ logic alert_class_shadowed_1_update_err;
+ logic alert_class_shadowed_2_re;
+ logic alert_class_shadowed_2_we;
+ logic [1:0] alert_class_shadowed_2_qs;
+ logic [1:0] alert_class_shadowed_2_wd;
+ logic alert_class_shadowed_2_storage_err;
+ logic alert_class_shadowed_2_update_err;
+ logic alert_class_shadowed_3_re;
+ logic alert_class_shadowed_3_we;
+ logic [1:0] alert_class_shadowed_3_qs;
+ logic [1:0] alert_class_shadowed_3_wd;
+ logic alert_class_shadowed_3_storage_err;
+ logic alert_class_shadowed_3_update_err;
+ logic alert_class_shadowed_4_re;
+ logic alert_class_shadowed_4_we;
+ logic [1:0] alert_class_shadowed_4_qs;
+ logic [1:0] alert_class_shadowed_4_wd;
+ logic alert_class_shadowed_4_storage_err;
+ logic alert_class_shadowed_4_update_err;
+ logic alert_class_shadowed_5_re;
+ logic alert_class_shadowed_5_we;
+ logic [1:0] alert_class_shadowed_5_qs;
+ logic [1:0] alert_class_shadowed_5_wd;
+ logic alert_class_shadowed_5_storage_err;
+ logic alert_class_shadowed_5_update_err;
+ logic alert_class_shadowed_6_re;
+ logic alert_class_shadowed_6_we;
+ logic [1:0] alert_class_shadowed_6_qs;
+ logic [1:0] alert_class_shadowed_6_wd;
+ logic alert_class_shadowed_6_storage_err;
+ logic alert_class_shadowed_6_update_err;
+ logic alert_class_shadowed_7_re;
+ logic alert_class_shadowed_7_we;
+ logic [1:0] alert_class_shadowed_7_qs;
+ logic [1:0] alert_class_shadowed_7_wd;
+ logic alert_class_shadowed_7_storage_err;
+ logic alert_class_shadowed_7_update_err;
+ logic alert_class_shadowed_8_re;
+ logic alert_class_shadowed_8_we;
+ logic [1:0] alert_class_shadowed_8_qs;
+ logic [1:0] alert_class_shadowed_8_wd;
+ logic alert_class_shadowed_8_storage_err;
+ logic alert_class_shadowed_8_update_err;
+ logic alert_class_shadowed_9_re;
+ logic alert_class_shadowed_9_we;
+ logic [1:0] alert_class_shadowed_9_qs;
+ logic [1:0] alert_class_shadowed_9_wd;
+ logic alert_class_shadowed_9_storage_err;
+ logic alert_class_shadowed_9_update_err;
+ logic alert_class_shadowed_10_re;
+ logic alert_class_shadowed_10_we;
+ logic [1:0] alert_class_shadowed_10_qs;
+ logic [1:0] alert_class_shadowed_10_wd;
+ logic alert_class_shadowed_10_storage_err;
+ logic alert_class_shadowed_10_update_err;
+ logic alert_class_shadowed_11_re;
+ logic alert_class_shadowed_11_we;
+ logic [1:0] alert_class_shadowed_11_qs;
+ logic [1:0] alert_class_shadowed_11_wd;
+ logic alert_class_shadowed_11_storage_err;
+ logic alert_class_shadowed_11_update_err;
+ logic alert_class_shadowed_12_re;
+ logic alert_class_shadowed_12_we;
+ logic [1:0] alert_class_shadowed_12_qs;
+ logic [1:0] alert_class_shadowed_12_wd;
+ logic alert_class_shadowed_12_storage_err;
+ logic alert_class_shadowed_12_update_err;
+ logic alert_class_shadowed_13_re;
+ logic alert_class_shadowed_13_we;
+ logic [1:0] alert_class_shadowed_13_qs;
+ logic [1:0] alert_class_shadowed_13_wd;
+ logic alert_class_shadowed_13_storage_err;
+ logic alert_class_shadowed_13_update_err;
+ logic alert_class_shadowed_14_re;
+ logic alert_class_shadowed_14_we;
+ logic [1:0] alert_class_shadowed_14_qs;
+ logic [1:0] alert_class_shadowed_14_wd;
+ logic alert_class_shadowed_14_storage_err;
+ logic alert_class_shadowed_14_update_err;
+ logic alert_class_shadowed_15_re;
+ logic alert_class_shadowed_15_we;
+ logic [1:0] alert_class_shadowed_15_qs;
+ logic [1:0] alert_class_shadowed_15_wd;
+ logic alert_class_shadowed_15_storage_err;
+ logic alert_class_shadowed_15_update_err;
+ logic alert_class_shadowed_16_re;
+ logic alert_class_shadowed_16_we;
+ logic [1:0] alert_class_shadowed_16_qs;
+ logic [1:0] alert_class_shadowed_16_wd;
+ logic alert_class_shadowed_16_storage_err;
+ logic alert_class_shadowed_16_update_err;
+ logic alert_class_shadowed_17_re;
+ logic alert_class_shadowed_17_we;
+ logic [1:0] alert_class_shadowed_17_qs;
+ logic [1:0] alert_class_shadowed_17_wd;
+ logic alert_class_shadowed_17_storage_err;
+ logic alert_class_shadowed_17_update_err;
+ logic alert_class_shadowed_18_re;
+ logic alert_class_shadowed_18_we;
+ logic [1:0] alert_class_shadowed_18_qs;
+ logic [1:0] alert_class_shadowed_18_wd;
+ logic alert_class_shadowed_18_storage_err;
+ logic alert_class_shadowed_18_update_err;
+ logic alert_class_shadowed_19_re;
+ logic alert_class_shadowed_19_we;
+ logic [1:0] alert_class_shadowed_19_qs;
+ logic [1:0] alert_class_shadowed_19_wd;
+ logic alert_class_shadowed_19_storage_err;
+ logic alert_class_shadowed_19_update_err;
+ logic alert_class_shadowed_20_re;
+ logic alert_class_shadowed_20_we;
+ logic [1:0] alert_class_shadowed_20_qs;
+ logic [1:0] alert_class_shadowed_20_wd;
+ logic alert_class_shadowed_20_storage_err;
+ logic alert_class_shadowed_20_update_err;
+ logic alert_class_shadowed_21_re;
+ logic alert_class_shadowed_21_we;
+ logic [1:0] alert_class_shadowed_21_qs;
+ logic [1:0] alert_class_shadowed_21_wd;
+ logic alert_class_shadowed_21_storage_err;
+ logic alert_class_shadowed_21_update_err;
+ logic alert_class_shadowed_22_re;
+ logic alert_class_shadowed_22_we;
+ logic [1:0] alert_class_shadowed_22_qs;
+ logic [1:0] alert_class_shadowed_22_wd;
+ logic alert_class_shadowed_22_storage_err;
+ logic alert_class_shadowed_22_update_err;
+ logic alert_class_shadowed_23_re;
+ logic alert_class_shadowed_23_we;
+ logic [1:0] alert_class_shadowed_23_qs;
+ logic [1:0] alert_class_shadowed_23_wd;
+ logic alert_class_shadowed_23_storage_err;
+ logic alert_class_shadowed_23_update_err;
+ logic alert_class_shadowed_24_re;
+ logic alert_class_shadowed_24_we;
+ logic [1:0] alert_class_shadowed_24_qs;
+ logic [1:0] alert_class_shadowed_24_wd;
+ logic alert_class_shadowed_24_storage_err;
+ logic alert_class_shadowed_24_update_err;
+ logic alert_class_shadowed_25_re;
+ logic alert_class_shadowed_25_we;
+ logic [1:0] alert_class_shadowed_25_qs;
+ logic [1:0] alert_class_shadowed_25_wd;
+ logic alert_class_shadowed_25_storage_err;
+ logic alert_class_shadowed_25_update_err;
+ logic alert_class_shadowed_26_re;
+ logic alert_class_shadowed_26_we;
+ logic [1:0] alert_class_shadowed_26_qs;
+ logic [1:0] alert_class_shadowed_26_wd;
+ logic alert_class_shadowed_26_storage_err;
+ logic alert_class_shadowed_26_update_err;
+ logic alert_class_shadowed_27_re;
+ logic alert_class_shadowed_27_we;
+ logic [1:0] alert_class_shadowed_27_qs;
+ logic [1:0] alert_class_shadowed_27_wd;
+ logic alert_class_shadowed_27_storage_err;
+ logic alert_class_shadowed_27_update_err;
+ logic alert_class_shadowed_28_re;
+ logic alert_class_shadowed_28_we;
+ logic [1:0] alert_class_shadowed_28_qs;
+ logic [1:0] alert_class_shadowed_28_wd;
+ logic alert_class_shadowed_28_storage_err;
+ logic alert_class_shadowed_28_update_err;
+ logic alert_class_shadowed_29_re;
+ logic alert_class_shadowed_29_we;
+ logic [1:0] alert_class_shadowed_29_qs;
+ logic [1:0] alert_class_shadowed_29_wd;
+ logic alert_class_shadowed_29_storage_err;
+ logic alert_class_shadowed_29_update_err;
+ logic alert_class_shadowed_30_re;
+ logic alert_class_shadowed_30_we;
+ logic [1:0] alert_class_shadowed_30_qs;
+ logic [1:0] alert_class_shadowed_30_wd;
+ logic alert_class_shadowed_30_storage_err;
+ logic alert_class_shadowed_30_update_err;
+ logic alert_class_shadowed_31_re;
+ logic alert_class_shadowed_31_we;
+ logic [1:0] alert_class_shadowed_31_qs;
+ logic [1:0] alert_class_shadowed_31_wd;
+ logic alert_class_shadowed_31_storage_err;
+ logic alert_class_shadowed_31_update_err;
+ logic alert_class_shadowed_32_re;
+ logic alert_class_shadowed_32_we;
+ logic [1:0] alert_class_shadowed_32_qs;
+ logic [1:0] alert_class_shadowed_32_wd;
+ logic alert_class_shadowed_32_storage_err;
+ logic alert_class_shadowed_32_update_err;
+ logic alert_class_shadowed_33_re;
+ logic alert_class_shadowed_33_we;
+ logic [1:0] alert_class_shadowed_33_qs;
+ logic [1:0] alert_class_shadowed_33_wd;
+ logic alert_class_shadowed_33_storage_err;
+ logic alert_class_shadowed_33_update_err;
+ logic alert_class_shadowed_34_re;
+ logic alert_class_shadowed_34_we;
+ logic [1:0] alert_class_shadowed_34_qs;
+ logic [1:0] alert_class_shadowed_34_wd;
+ logic alert_class_shadowed_34_storage_err;
+ logic alert_class_shadowed_34_update_err;
+ logic alert_class_shadowed_35_re;
+ logic alert_class_shadowed_35_we;
+ logic [1:0] alert_class_shadowed_35_qs;
+ logic [1:0] alert_class_shadowed_35_wd;
+ logic alert_class_shadowed_35_storage_err;
+ logic alert_class_shadowed_35_update_err;
+ logic alert_class_shadowed_36_re;
+ logic alert_class_shadowed_36_we;
+ logic [1:0] alert_class_shadowed_36_qs;
+ logic [1:0] alert_class_shadowed_36_wd;
+ logic alert_class_shadowed_36_storage_err;
+ logic alert_class_shadowed_36_update_err;
+ logic alert_class_shadowed_37_re;
+ logic alert_class_shadowed_37_we;
+ logic [1:0] alert_class_shadowed_37_qs;
+ logic [1:0] alert_class_shadowed_37_wd;
+ logic alert_class_shadowed_37_storage_err;
+ logic alert_class_shadowed_37_update_err;
+ logic alert_class_shadowed_38_re;
+ logic alert_class_shadowed_38_we;
+ logic [1:0] alert_class_shadowed_38_qs;
+ logic [1:0] alert_class_shadowed_38_wd;
+ logic alert_class_shadowed_38_storage_err;
+ logic alert_class_shadowed_38_update_err;
+ logic alert_class_shadowed_39_re;
+ logic alert_class_shadowed_39_we;
+ logic [1:0] alert_class_shadowed_39_qs;
+ logic [1:0] alert_class_shadowed_39_wd;
+ logic alert_class_shadowed_39_storage_err;
+ logic alert_class_shadowed_39_update_err;
+ logic alert_class_shadowed_40_re;
+ logic alert_class_shadowed_40_we;
+ logic [1:0] alert_class_shadowed_40_qs;
+ logic [1:0] alert_class_shadowed_40_wd;
+ logic alert_class_shadowed_40_storage_err;
+ logic alert_class_shadowed_40_update_err;
+ logic alert_class_shadowed_41_re;
+ logic alert_class_shadowed_41_we;
+ logic [1:0] alert_class_shadowed_41_qs;
+ logic [1:0] alert_class_shadowed_41_wd;
+ logic alert_class_shadowed_41_storage_err;
+ logic alert_class_shadowed_41_update_err;
+ logic alert_class_shadowed_42_re;
+ logic alert_class_shadowed_42_we;
+ logic [1:0] alert_class_shadowed_42_qs;
+ logic [1:0] alert_class_shadowed_42_wd;
+ logic alert_class_shadowed_42_storage_err;
+ logic alert_class_shadowed_42_update_err;
+ logic alert_class_shadowed_43_re;
+ logic alert_class_shadowed_43_we;
+ logic [1:0] alert_class_shadowed_43_qs;
+ logic [1:0] alert_class_shadowed_43_wd;
+ logic alert_class_shadowed_43_storage_err;
+ logic alert_class_shadowed_43_update_err;
+ logic alert_class_shadowed_44_re;
+ logic alert_class_shadowed_44_we;
+ logic [1:0] alert_class_shadowed_44_qs;
+ logic [1:0] alert_class_shadowed_44_wd;
+ logic alert_class_shadowed_44_storage_err;
+ logic alert_class_shadowed_44_update_err;
+ logic alert_class_shadowed_45_re;
+ logic alert_class_shadowed_45_we;
+ logic [1:0] alert_class_shadowed_45_qs;
+ logic [1:0] alert_class_shadowed_45_wd;
+ logic alert_class_shadowed_45_storage_err;
+ logic alert_class_shadowed_45_update_err;
+ logic alert_class_shadowed_46_re;
+ logic alert_class_shadowed_46_we;
+ logic [1:0] alert_class_shadowed_46_qs;
+ logic [1:0] alert_class_shadowed_46_wd;
+ logic alert_class_shadowed_46_storage_err;
+ logic alert_class_shadowed_46_update_err;
+ logic alert_class_shadowed_47_re;
+ logic alert_class_shadowed_47_we;
+ logic [1:0] alert_class_shadowed_47_qs;
+ logic [1:0] alert_class_shadowed_47_wd;
+ logic alert_class_shadowed_47_storage_err;
+ logic alert_class_shadowed_47_update_err;
+ logic alert_class_shadowed_48_re;
+ logic alert_class_shadowed_48_we;
+ logic [1:0] alert_class_shadowed_48_qs;
+ logic [1:0] alert_class_shadowed_48_wd;
+ logic alert_class_shadowed_48_storage_err;
+ logic alert_class_shadowed_48_update_err;
+ logic alert_class_shadowed_49_re;
+ logic alert_class_shadowed_49_we;
+ logic [1:0] alert_class_shadowed_49_qs;
+ logic [1:0] alert_class_shadowed_49_wd;
+ logic alert_class_shadowed_49_storage_err;
+ logic alert_class_shadowed_49_update_err;
+ logic alert_class_shadowed_50_re;
+ logic alert_class_shadowed_50_we;
+ logic [1:0] alert_class_shadowed_50_qs;
+ logic [1:0] alert_class_shadowed_50_wd;
+ logic alert_class_shadowed_50_storage_err;
+ logic alert_class_shadowed_50_update_err;
+ logic alert_class_shadowed_51_re;
+ logic alert_class_shadowed_51_we;
+ logic [1:0] alert_class_shadowed_51_qs;
+ logic [1:0] alert_class_shadowed_51_wd;
+ logic alert_class_shadowed_51_storage_err;
+ logic alert_class_shadowed_51_update_err;
+ logic alert_class_shadowed_52_re;
+ logic alert_class_shadowed_52_we;
+ logic [1:0] alert_class_shadowed_52_qs;
+ logic [1:0] alert_class_shadowed_52_wd;
+ logic alert_class_shadowed_52_storage_err;
+ logic alert_class_shadowed_52_update_err;
+ logic alert_class_shadowed_53_re;
+ logic alert_class_shadowed_53_we;
+ logic [1:0] alert_class_shadowed_53_qs;
+ logic [1:0] alert_class_shadowed_53_wd;
+ logic alert_class_shadowed_53_storage_err;
+ logic alert_class_shadowed_53_update_err;
+ logic alert_class_shadowed_54_re;
+ logic alert_class_shadowed_54_we;
+ logic [1:0] alert_class_shadowed_54_qs;
+ logic [1:0] alert_class_shadowed_54_wd;
+ logic alert_class_shadowed_54_storage_err;
+ logic alert_class_shadowed_54_update_err;
+ logic alert_class_shadowed_55_re;
+ logic alert_class_shadowed_55_we;
+ logic [1:0] alert_class_shadowed_55_qs;
+ logic [1:0] alert_class_shadowed_55_wd;
+ logic alert_class_shadowed_55_storage_err;
+ logic alert_class_shadowed_55_update_err;
+ logic alert_class_shadowed_56_re;
+ logic alert_class_shadowed_56_we;
+ logic [1:0] alert_class_shadowed_56_qs;
+ logic [1:0] alert_class_shadowed_56_wd;
+ logic alert_class_shadowed_56_storage_err;
+ logic alert_class_shadowed_56_update_err;
+ logic alert_class_shadowed_57_re;
+ logic alert_class_shadowed_57_we;
+ logic [1:0] alert_class_shadowed_57_qs;
+ logic [1:0] alert_class_shadowed_57_wd;
+ logic alert_class_shadowed_57_storage_err;
+ logic alert_class_shadowed_57_update_err;
+ logic alert_class_shadowed_58_re;
+ logic alert_class_shadowed_58_we;
+ logic [1:0] alert_class_shadowed_58_qs;
+ logic [1:0] alert_class_shadowed_58_wd;
+ logic alert_class_shadowed_58_storage_err;
+ logic alert_class_shadowed_58_update_err;
+ logic alert_class_shadowed_59_re;
+ logic alert_class_shadowed_59_we;
+ logic [1:0] alert_class_shadowed_59_qs;
+ logic [1:0] alert_class_shadowed_59_wd;
+ logic alert_class_shadowed_59_storage_err;
+ logic alert_class_shadowed_59_update_err;
+ logic alert_class_shadowed_60_re;
+ logic alert_class_shadowed_60_we;
+ logic [1:0] alert_class_shadowed_60_qs;
+ logic [1:0] alert_class_shadowed_60_wd;
+ logic alert_class_shadowed_60_storage_err;
+ logic alert_class_shadowed_60_update_err;
+ logic alert_class_shadowed_61_re;
+ logic alert_class_shadowed_61_we;
+ logic [1:0] alert_class_shadowed_61_qs;
+ logic [1:0] alert_class_shadowed_61_wd;
+ logic alert_class_shadowed_61_storage_err;
+ logic alert_class_shadowed_61_update_err;
+ logic alert_class_shadowed_62_re;
+ logic alert_class_shadowed_62_we;
+ logic [1:0] alert_class_shadowed_62_qs;
+ logic [1:0] alert_class_shadowed_62_wd;
+ logic alert_class_shadowed_62_storage_err;
+ logic alert_class_shadowed_62_update_err;
+ logic alert_class_shadowed_63_re;
+ logic alert_class_shadowed_63_we;
+ logic [1:0] alert_class_shadowed_63_qs;
+ logic [1:0] alert_class_shadowed_63_wd;
+ logic alert_class_shadowed_63_storage_err;
+ logic alert_class_shadowed_63_update_err;
+ logic alert_class_shadowed_64_re;
+ logic alert_class_shadowed_64_we;
+ logic [1:0] alert_class_shadowed_64_qs;
+ logic [1:0] alert_class_shadowed_64_wd;
+ logic alert_class_shadowed_64_storage_err;
+ logic alert_class_shadowed_64_update_err;
+ logic alert_class_shadowed_65_re;
+ logic alert_class_shadowed_65_we;
+ logic [1:0] alert_class_shadowed_65_qs;
+ logic [1:0] alert_class_shadowed_65_wd;
+ logic alert_class_shadowed_65_storage_err;
+ logic alert_class_shadowed_65_update_err;
+ logic alert_class_shadowed_66_re;
+ logic alert_class_shadowed_66_we;
+ logic [1:0] alert_class_shadowed_66_qs;
+ logic [1:0] alert_class_shadowed_66_wd;
+ logic alert_class_shadowed_66_storage_err;
+ logic alert_class_shadowed_66_update_err;
+ logic alert_class_shadowed_67_re;
+ logic alert_class_shadowed_67_we;
+ logic [1:0] alert_class_shadowed_67_qs;
+ logic [1:0] alert_class_shadowed_67_wd;
+ logic alert_class_shadowed_67_storage_err;
+ logic alert_class_shadowed_67_update_err;
+ logic alert_class_shadowed_68_re;
+ logic alert_class_shadowed_68_we;
+ logic [1:0] alert_class_shadowed_68_qs;
+ logic [1:0] alert_class_shadowed_68_wd;
+ logic alert_class_shadowed_68_storage_err;
+ logic alert_class_shadowed_68_update_err;
+ logic alert_class_shadowed_69_re;
+ logic alert_class_shadowed_69_we;
+ logic [1:0] alert_class_shadowed_69_qs;
+ logic [1:0] alert_class_shadowed_69_wd;
+ logic alert_class_shadowed_69_storage_err;
+ logic alert_class_shadowed_69_update_err;
+ logic alert_class_shadowed_70_re;
+ logic alert_class_shadowed_70_we;
+ logic [1:0] alert_class_shadowed_70_qs;
+ logic [1:0] alert_class_shadowed_70_wd;
+ logic alert_class_shadowed_70_storage_err;
+ logic alert_class_shadowed_70_update_err;
+ logic alert_class_shadowed_71_re;
+ logic alert_class_shadowed_71_we;
+ logic [1:0] alert_class_shadowed_71_qs;
+ logic [1:0] alert_class_shadowed_71_wd;
+ logic alert_class_shadowed_71_storage_err;
+ logic alert_class_shadowed_71_update_err;
+ logic alert_class_shadowed_72_re;
+ logic alert_class_shadowed_72_we;
+ logic [1:0] alert_class_shadowed_72_qs;
+ logic [1:0] alert_class_shadowed_72_wd;
+ logic alert_class_shadowed_72_storage_err;
+ logic alert_class_shadowed_72_update_err;
+ logic alert_class_shadowed_73_re;
+ logic alert_class_shadowed_73_we;
+ logic [1:0] alert_class_shadowed_73_qs;
+ logic [1:0] alert_class_shadowed_73_wd;
+ logic alert_class_shadowed_73_storage_err;
+ logic alert_class_shadowed_73_update_err;
+ logic alert_class_shadowed_74_re;
+ logic alert_class_shadowed_74_we;
+ logic [1:0] alert_class_shadowed_74_qs;
+ logic [1:0] alert_class_shadowed_74_wd;
+ logic alert_class_shadowed_74_storage_err;
+ logic alert_class_shadowed_74_update_err;
+ logic alert_cause_0_we;
+ logic alert_cause_0_qs;
+ logic alert_cause_0_wd;
+ logic alert_cause_1_we;
+ logic alert_cause_1_qs;
+ logic alert_cause_1_wd;
+ logic alert_cause_2_we;
+ logic alert_cause_2_qs;
+ logic alert_cause_2_wd;
+ logic alert_cause_3_we;
+ logic alert_cause_3_qs;
+ logic alert_cause_3_wd;
+ logic alert_cause_4_we;
+ logic alert_cause_4_qs;
+ logic alert_cause_4_wd;
+ logic alert_cause_5_we;
+ logic alert_cause_5_qs;
+ logic alert_cause_5_wd;
+ logic alert_cause_6_we;
+ logic alert_cause_6_qs;
+ logic alert_cause_6_wd;
+ logic alert_cause_7_we;
+ logic alert_cause_7_qs;
+ logic alert_cause_7_wd;
+ logic alert_cause_8_we;
+ logic alert_cause_8_qs;
+ logic alert_cause_8_wd;
+ logic alert_cause_9_we;
+ logic alert_cause_9_qs;
+ logic alert_cause_9_wd;
+ logic alert_cause_10_we;
+ logic alert_cause_10_qs;
+ logic alert_cause_10_wd;
+ logic alert_cause_11_we;
+ logic alert_cause_11_qs;
+ logic alert_cause_11_wd;
+ logic alert_cause_12_we;
+ logic alert_cause_12_qs;
+ logic alert_cause_12_wd;
+ logic alert_cause_13_we;
+ logic alert_cause_13_qs;
+ logic alert_cause_13_wd;
+ logic alert_cause_14_we;
+ logic alert_cause_14_qs;
+ logic alert_cause_14_wd;
+ logic alert_cause_15_we;
+ logic alert_cause_15_qs;
+ logic alert_cause_15_wd;
+ logic alert_cause_16_we;
+ logic alert_cause_16_qs;
+ logic alert_cause_16_wd;
+ logic alert_cause_17_we;
+ logic alert_cause_17_qs;
+ logic alert_cause_17_wd;
+ logic alert_cause_18_we;
+ logic alert_cause_18_qs;
+ logic alert_cause_18_wd;
+ logic alert_cause_19_we;
+ logic alert_cause_19_qs;
+ logic alert_cause_19_wd;
+ logic alert_cause_20_we;
+ logic alert_cause_20_qs;
+ logic alert_cause_20_wd;
+ logic alert_cause_21_we;
+ logic alert_cause_21_qs;
+ logic alert_cause_21_wd;
+ logic alert_cause_22_we;
+ logic alert_cause_22_qs;
+ logic alert_cause_22_wd;
+ logic alert_cause_23_we;
+ logic alert_cause_23_qs;
+ logic alert_cause_23_wd;
+ logic alert_cause_24_we;
+ logic alert_cause_24_qs;
+ logic alert_cause_24_wd;
+ logic alert_cause_25_we;
+ logic alert_cause_25_qs;
+ logic alert_cause_25_wd;
+ logic alert_cause_26_we;
+ logic alert_cause_26_qs;
+ logic alert_cause_26_wd;
+ logic alert_cause_27_we;
+ logic alert_cause_27_qs;
+ logic alert_cause_27_wd;
+ logic alert_cause_28_we;
+ logic alert_cause_28_qs;
+ logic alert_cause_28_wd;
+ logic alert_cause_29_we;
+ logic alert_cause_29_qs;
+ logic alert_cause_29_wd;
+ logic alert_cause_30_we;
+ logic alert_cause_30_qs;
+ logic alert_cause_30_wd;
+ logic alert_cause_31_we;
+ logic alert_cause_31_qs;
+ logic alert_cause_31_wd;
+ logic alert_cause_32_we;
+ logic alert_cause_32_qs;
+ logic alert_cause_32_wd;
+ logic alert_cause_33_we;
+ logic alert_cause_33_qs;
+ logic alert_cause_33_wd;
+ logic alert_cause_34_we;
+ logic alert_cause_34_qs;
+ logic alert_cause_34_wd;
+ logic alert_cause_35_we;
+ logic alert_cause_35_qs;
+ logic alert_cause_35_wd;
+ logic alert_cause_36_we;
+ logic alert_cause_36_qs;
+ logic alert_cause_36_wd;
+ logic alert_cause_37_we;
+ logic alert_cause_37_qs;
+ logic alert_cause_37_wd;
+ logic alert_cause_38_we;
+ logic alert_cause_38_qs;
+ logic alert_cause_38_wd;
+ logic alert_cause_39_we;
+ logic alert_cause_39_qs;
+ logic alert_cause_39_wd;
+ logic alert_cause_40_we;
+ logic alert_cause_40_qs;
+ logic alert_cause_40_wd;
+ logic alert_cause_41_we;
+ logic alert_cause_41_qs;
+ logic alert_cause_41_wd;
+ logic alert_cause_42_we;
+ logic alert_cause_42_qs;
+ logic alert_cause_42_wd;
+ logic alert_cause_43_we;
+ logic alert_cause_43_qs;
+ logic alert_cause_43_wd;
+ logic alert_cause_44_we;
+ logic alert_cause_44_qs;
+ logic alert_cause_44_wd;
+ logic alert_cause_45_we;
+ logic alert_cause_45_qs;
+ logic alert_cause_45_wd;
+ logic alert_cause_46_we;
+ logic alert_cause_46_qs;
+ logic alert_cause_46_wd;
+ logic alert_cause_47_we;
+ logic alert_cause_47_qs;
+ logic alert_cause_47_wd;
+ logic alert_cause_48_we;
+ logic alert_cause_48_qs;
+ logic alert_cause_48_wd;
+ logic alert_cause_49_we;
+ logic alert_cause_49_qs;
+ logic alert_cause_49_wd;
+ logic alert_cause_50_we;
+ logic alert_cause_50_qs;
+ logic alert_cause_50_wd;
+ logic alert_cause_51_we;
+ logic alert_cause_51_qs;
+ logic alert_cause_51_wd;
+ logic alert_cause_52_we;
+ logic alert_cause_52_qs;
+ logic alert_cause_52_wd;
+ logic alert_cause_53_we;
+ logic alert_cause_53_qs;
+ logic alert_cause_53_wd;
+ logic alert_cause_54_we;
+ logic alert_cause_54_qs;
+ logic alert_cause_54_wd;
+ logic alert_cause_55_we;
+ logic alert_cause_55_qs;
+ logic alert_cause_55_wd;
+ logic alert_cause_56_we;
+ logic alert_cause_56_qs;
+ logic alert_cause_56_wd;
+ logic alert_cause_57_we;
+ logic alert_cause_57_qs;
+ logic alert_cause_57_wd;
+ logic alert_cause_58_we;
+ logic alert_cause_58_qs;
+ logic alert_cause_58_wd;
+ logic alert_cause_59_we;
+ logic alert_cause_59_qs;
+ logic alert_cause_59_wd;
+ logic alert_cause_60_we;
+ logic alert_cause_60_qs;
+ logic alert_cause_60_wd;
+ logic alert_cause_61_we;
+ logic alert_cause_61_qs;
+ logic alert_cause_61_wd;
+ logic alert_cause_62_we;
+ logic alert_cause_62_qs;
+ logic alert_cause_62_wd;
+ logic alert_cause_63_we;
+ logic alert_cause_63_qs;
+ logic alert_cause_63_wd;
+ logic alert_cause_64_we;
+ logic alert_cause_64_qs;
+ logic alert_cause_64_wd;
+ logic alert_cause_65_we;
+ logic alert_cause_65_qs;
+ logic alert_cause_65_wd;
+ logic alert_cause_66_we;
+ logic alert_cause_66_qs;
+ logic alert_cause_66_wd;
+ logic alert_cause_67_we;
+ logic alert_cause_67_qs;
+ logic alert_cause_67_wd;
+ logic alert_cause_68_we;
+ logic alert_cause_68_qs;
+ logic alert_cause_68_wd;
+ logic alert_cause_69_we;
+ logic alert_cause_69_qs;
+ logic alert_cause_69_wd;
+ logic alert_cause_70_we;
+ logic alert_cause_70_qs;
+ logic alert_cause_70_wd;
+ logic alert_cause_71_we;
+ logic alert_cause_71_qs;
+ logic alert_cause_71_wd;
+ logic alert_cause_72_we;
+ logic alert_cause_72_qs;
+ logic alert_cause_72_wd;
+ logic alert_cause_73_we;
+ logic alert_cause_73_qs;
+ logic alert_cause_73_wd;
+ logic alert_cause_74_we;
+ logic alert_cause_74_qs;
+ logic alert_cause_74_wd;
+ logic loc_alert_regwen_0_we;
+ logic loc_alert_regwen_0_qs;
+ logic loc_alert_regwen_0_wd;
+ logic loc_alert_regwen_1_we;
+ logic loc_alert_regwen_1_qs;
+ logic loc_alert_regwen_1_wd;
+ logic loc_alert_regwen_2_we;
+ logic loc_alert_regwen_2_qs;
+ logic loc_alert_regwen_2_wd;
+ logic loc_alert_regwen_3_we;
+ logic loc_alert_regwen_3_qs;
+ logic loc_alert_regwen_3_wd;
+ logic loc_alert_regwen_4_we;
+ logic loc_alert_regwen_4_qs;
+ logic loc_alert_regwen_4_wd;
+ logic loc_alert_regwen_5_we;
+ logic loc_alert_regwen_5_qs;
+ logic loc_alert_regwen_5_wd;
+ logic loc_alert_regwen_6_we;
+ logic loc_alert_regwen_6_qs;
+ logic loc_alert_regwen_6_wd;
+ logic loc_alert_en_shadowed_0_re;
+ logic loc_alert_en_shadowed_0_we;
+ logic loc_alert_en_shadowed_0_qs;
+ logic loc_alert_en_shadowed_0_wd;
+ logic loc_alert_en_shadowed_0_storage_err;
+ logic loc_alert_en_shadowed_0_update_err;
+ logic loc_alert_en_shadowed_1_re;
+ logic loc_alert_en_shadowed_1_we;
+ logic loc_alert_en_shadowed_1_qs;
+ logic loc_alert_en_shadowed_1_wd;
+ logic loc_alert_en_shadowed_1_storage_err;
+ logic loc_alert_en_shadowed_1_update_err;
+ logic loc_alert_en_shadowed_2_re;
+ logic loc_alert_en_shadowed_2_we;
+ logic loc_alert_en_shadowed_2_qs;
+ logic loc_alert_en_shadowed_2_wd;
+ logic loc_alert_en_shadowed_2_storage_err;
+ logic loc_alert_en_shadowed_2_update_err;
+ logic loc_alert_en_shadowed_3_re;
+ logic loc_alert_en_shadowed_3_we;
+ logic loc_alert_en_shadowed_3_qs;
+ logic loc_alert_en_shadowed_3_wd;
+ logic loc_alert_en_shadowed_3_storage_err;
+ logic loc_alert_en_shadowed_3_update_err;
+ logic loc_alert_en_shadowed_4_re;
+ logic loc_alert_en_shadowed_4_we;
+ logic loc_alert_en_shadowed_4_qs;
+ logic loc_alert_en_shadowed_4_wd;
+ logic loc_alert_en_shadowed_4_storage_err;
+ logic loc_alert_en_shadowed_4_update_err;
+ logic loc_alert_en_shadowed_5_re;
+ logic loc_alert_en_shadowed_5_we;
+ logic loc_alert_en_shadowed_5_qs;
+ logic loc_alert_en_shadowed_5_wd;
+ logic loc_alert_en_shadowed_5_storage_err;
+ logic loc_alert_en_shadowed_5_update_err;
+ logic loc_alert_en_shadowed_6_re;
+ logic loc_alert_en_shadowed_6_we;
+ logic loc_alert_en_shadowed_6_qs;
+ logic loc_alert_en_shadowed_6_wd;
+ logic loc_alert_en_shadowed_6_storage_err;
+ logic loc_alert_en_shadowed_6_update_err;
+ logic loc_alert_class_shadowed_0_re;
+ logic loc_alert_class_shadowed_0_we;
+ logic [1:0] loc_alert_class_shadowed_0_qs;
+ logic [1:0] loc_alert_class_shadowed_0_wd;
+ logic loc_alert_class_shadowed_0_storage_err;
+ logic loc_alert_class_shadowed_0_update_err;
+ logic loc_alert_class_shadowed_1_re;
+ logic loc_alert_class_shadowed_1_we;
+ logic [1:0] loc_alert_class_shadowed_1_qs;
+ logic [1:0] loc_alert_class_shadowed_1_wd;
+ logic loc_alert_class_shadowed_1_storage_err;
+ logic loc_alert_class_shadowed_1_update_err;
+ logic loc_alert_class_shadowed_2_re;
+ logic loc_alert_class_shadowed_2_we;
+ logic [1:0] loc_alert_class_shadowed_2_qs;
+ logic [1:0] loc_alert_class_shadowed_2_wd;
+ logic loc_alert_class_shadowed_2_storage_err;
+ logic loc_alert_class_shadowed_2_update_err;
+ logic loc_alert_class_shadowed_3_re;
+ logic loc_alert_class_shadowed_3_we;
+ logic [1:0] loc_alert_class_shadowed_3_qs;
+ logic [1:0] loc_alert_class_shadowed_3_wd;
+ logic loc_alert_class_shadowed_3_storage_err;
+ logic loc_alert_class_shadowed_3_update_err;
+ logic loc_alert_class_shadowed_4_re;
+ logic loc_alert_class_shadowed_4_we;
+ logic [1:0] loc_alert_class_shadowed_4_qs;
+ logic [1:0] loc_alert_class_shadowed_4_wd;
+ logic loc_alert_class_shadowed_4_storage_err;
+ logic loc_alert_class_shadowed_4_update_err;
+ logic loc_alert_class_shadowed_5_re;
+ logic loc_alert_class_shadowed_5_we;
+ logic [1:0] loc_alert_class_shadowed_5_qs;
+ logic [1:0] loc_alert_class_shadowed_5_wd;
+ logic loc_alert_class_shadowed_5_storage_err;
+ logic loc_alert_class_shadowed_5_update_err;
+ logic loc_alert_class_shadowed_6_re;
+ logic loc_alert_class_shadowed_6_we;
+ logic [1:0] loc_alert_class_shadowed_6_qs;
+ logic [1:0] loc_alert_class_shadowed_6_wd;
+ logic loc_alert_class_shadowed_6_storage_err;
+ logic loc_alert_class_shadowed_6_update_err;
+ logic loc_alert_cause_0_we;
+ logic loc_alert_cause_0_qs;
+ logic loc_alert_cause_0_wd;
+ logic loc_alert_cause_1_we;
+ logic loc_alert_cause_1_qs;
+ logic loc_alert_cause_1_wd;
+ logic loc_alert_cause_2_we;
+ logic loc_alert_cause_2_qs;
+ logic loc_alert_cause_2_wd;
+ logic loc_alert_cause_3_we;
+ logic loc_alert_cause_3_qs;
+ logic loc_alert_cause_3_wd;
+ logic loc_alert_cause_4_we;
+ logic loc_alert_cause_4_qs;
+ logic loc_alert_cause_4_wd;
+ logic loc_alert_cause_5_we;
+ logic loc_alert_cause_5_qs;
+ logic loc_alert_cause_5_wd;
+ logic loc_alert_cause_6_we;
+ logic loc_alert_cause_6_qs;
+ logic loc_alert_cause_6_wd;
+ logic classa_regwen_we;
+ logic classa_regwen_qs;
+ logic classa_regwen_wd;
+ logic classa_ctrl_shadowed_re;
+ logic classa_ctrl_shadowed_we;
+ logic classa_ctrl_shadowed_en_qs;
+ logic classa_ctrl_shadowed_en_wd;
+ logic classa_ctrl_shadowed_en_storage_err;
+ logic classa_ctrl_shadowed_en_update_err;
+ logic classa_ctrl_shadowed_lock_qs;
+ logic classa_ctrl_shadowed_lock_wd;
+ logic classa_ctrl_shadowed_lock_storage_err;
+ logic classa_ctrl_shadowed_lock_update_err;
+ logic classa_ctrl_shadowed_en_e0_qs;
+ logic classa_ctrl_shadowed_en_e0_wd;
+ logic classa_ctrl_shadowed_en_e0_storage_err;
+ logic classa_ctrl_shadowed_en_e0_update_err;
+ logic classa_ctrl_shadowed_en_e1_qs;
+ logic classa_ctrl_shadowed_en_e1_wd;
+ logic classa_ctrl_shadowed_en_e1_storage_err;
+ logic classa_ctrl_shadowed_en_e1_update_err;
+ logic classa_ctrl_shadowed_en_e2_qs;
+ logic classa_ctrl_shadowed_en_e2_wd;
+ logic classa_ctrl_shadowed_en_e2_storage_err;
+ logic classa_ctrl_shadowed_en_e2_update_err;
+ logic classa_ctrl_shadowed_en_e3_qs;
+ logic classa_ctrl_shadowed_en_e3_wd;
+ logic classa_ctrl_shadowed_en_e3_storage_err;
+ logic classa_ctrl_shadowed_en_e3_update_err;
+ logic [1:0] classa_ctrl_shadowed_map_e0_qs;
+ logic [1:0] classa_ctrl_shadowed_map_e0_wd;
+ logic classa_ctrl_shadowed_map_e0_storage_err;
+ logic classa_ctrl_shadowed_map_e0_update_err;
+ logic [1:0] classa_ctrl_shadowed_map_e1_qs;
+ logic [1:0] classa_ctrl_shadowed_map_e1_wd;
+ logic classa_ctrl_shadowed_map_e1_storage_err;
+ logic classa_ctrl_shadowed_map_e1_update_err;
+ logic [1:0] classa_ctrl_shadowed_map_e2_qs;
+ logic [1:0] classa_ctrl_shadowed_map_e2_wd;
+ logic classa_ctrl_shadowed_map_e2_storage_err;
+ logic classa_ctrl_shadowed_map_e2_update_err;
+ logic [1:0] classa_ctrl_shadowed_map_e3_qs;
+ logic [1:0] classa_ctrl_shadowed_map_e3_wd;
+ logic classa_ctrl_shadowed_map_e3_storage_err;
+ logic classa_ctrl_shadowed_map_e3_update_err;
+ logic classa_clr_regwen_we;
+ logic classa_clr_regwen_qs;
+ logic classa_clr_regwen_wd;
+ logic classa_clr_shadowed_re;
+ logic classa_clr_shadowed_we;
+ logic classa_clr_shadowed_qs;
+ logic classa_clr_shadowed_wd;
+ logic classa_clr_shadowed_storage_err;
+ logic classa_clr_shadowed_update_err;
+ logic classa_accum_cnt_re;
+ logic [15:0] classa_accum_cnt_qs;
+ logic classa_accum_thresh_shadowed_re;
+ logic classa_accum_thresh_shadowed_we;
+ logic [15:0] classa_accum_thresh_shadowed_qs;
+ logic [15:0] classa_accum_thresh_shadowed_wd;
+ logic classa_accum_thresh_shadowed_storage_err;
+ logic classa_accum_thresh_shadowed_update_err;
+ logic classa_timeout_cyc_shadowed_re;
+ logic classa_timeout_cyc_shadowed_we;
+ logic [31:0] classa_timeout_cyc_shadowed_qs;
+ logic [31:0] classa_timeout_cyc_shadowed_wd;
+ logic classa_timeout_cyc_shadowed_storage_err;
+ logic classa_timeout_cyc_shadowed_update_err;
+ logic classa_crashdump_trigger_shadowed_re;
+ logic classa_crashdump_trigger_shadowed_we;
+ logic [1:0] classa_crashdump_trigger_shadowed_qs;
+ logic [1:0] classa_crashdump_trigger_shadowed_wd;
+ logic classa_crashdump_trigger_shadowed_storage_err;
+ logic classa_crashdump_trigger_shadowed_update_err;
+ logic classa_phase0_cyc_shadowed_re;
+ logic classa_phase0_cyc_shadowed_we;
+ logic [31:0] classa_phase0_cyc_shadowed_qs;
+ logic [31:0] classa_phase0_cyc_shadowed_wd;
+ logic classa_phase0_cyc_shadowed_storage_err;
+ logic classa_phase0_cyc_shadowed_update_err;
+ logic classa_phase1_cyc_shadowed_re;
+ logic classa_phase1_cyc_shadowed_we;
+ logic [31:0] classa_phase1_cyc_shadowed_qs;
+ logic [31:0] classa_phase1_cyc_shadowed_wd;
+ logic classa_phase1_cyc_shadowed_storage_err;
+ logic classa_phase1_cyc_shadowed_update_err;
+ logic classa_phase2_cyc_shadowed_re;
+ logic classa_phase2_cyc_shadowed_we;
+ logic [31:0] classa_phase2_cyc_shadowed_qs;
+ logic [31:0] classa_phase2_cyc_shadowed_wd;
+ logic classa_phase2_cyc_shadowed_storage_err;
+ logic classa_phase2_cyc_shadowed_update_err;
+ logic classa_phase3_cyc_shadowed_re;
+ logic classa_phase3_cyc_shadowed_we;
+ logic [31:0] classa_phase3_cyc_shadowed_qs;
+ logic [31:0] classa_phase3_cyc_shadowed_wd;
+ logic classa_phase3_cyc_shadowed_storage_err;
+ logic classa_phase3_cyc_shadowed_update_err;
+ logic classa_esc_cnt_re;
+ logic [31:0] classa_esc_cnt_qs;
+ logic classa_state_re;
+ logic [2:0] classa_state_qs;
+ logic classb_regwen_we;
+ logic classb_regwen_qs;
+ logic classb_regwen_wd;
+ logic classb_ctrl_shadowed_re;
+ logic classb_ctrl_shadowed_we;
+ logic classb_ctrl_shadowed_en_qs;
+ logic classb_ctrl_shadowed_en_wd;
+ logic classb_ctrl_shadowed_en_storage_err;
+ logic classb_ctrl_shadowed_en_update_err;
+ logic classb_ctrl_shadowed_lock_qs;
+ logic classb_ctrl_shadowed_lock_wd;
+ logic classb_ctrl_shadowed_lock_storage_err;
+ logic classb_ctrl_shadowed_lock_update_err;
+ logic classb_ctrl_shadowed_en_e0_qs;
+ logic classb_ctrl_shadowed_en_e0_wd;
+ logic classb_ctrl_shadowed_en_e0_storage_err;
+ logic classb_ctrl_shadowed_en_e0_update_err;
+ logic classb_ctrl_shadowed_en_e1_qs;
+ logic classb_ctrl_shadowed_en_e1_wd;
+ logic classb_ctrl_shadowed_en_e1_storage_err;
+ logic classb_ctrl_shadowed_en_e1_update_err;
+ logic classb_ctrl_shadowed_en_e2_qs;
+ logic classb_ctrl_shadowed_en_e2_wd;
+ logic classb_ctrl_shadowed_en_e2_storage_err;
+ logic classb_ctrl_shadowed_en_e2_update_err;
+ logic classb_ctrl_shadowed_en_e3_qs;
+ logic classb_ctrl_shadowed_en_e3_wd;
+ logic classb_ctrl_shadowed_en_e3_storage_err;
+ logic classb_ctrl_shadowed_en_e3_update_err;
+ logic [1:0] classb_ctrl_shadowed_map_e0_qs;
+ logic [1:0] classb_ctrl_shadowed_map_e0_wd;
+ logic classb_ctrl_shadowed_map_e0_storage_err;
+ logic classb_ctrl_shadowed_map_e0_update_err;
+ logic [1:0] classb_ctrl_shadowed_map_e1_qs;
+ logic [1:0] classb_ctrl_shadowed_map_e1_wd;
+ logic classb_ctrl_shadowed_map_e1_storage_err;
+ logic classb_ctrl_shadowed_map_e1_update_err;
+ logic [1:0] classb_ctrl_shadowed_map_e2_qs;
+ logic [1:0] classb_ctrl_shadowed_map_e2_wd;
+ logic classb_ctrl_shadowed_map_e2_storage_err;
+ logic classb_ctrl_shadowed_map_e2_update_err;
+ logic [1:0] classb_ctrl_shadowed_map_e3_qs;
+ logic [1:0] classb_ctrl_shadowed_map_e3_wd;
+ logic classb_ctrl_shadowed_map_e3_storage_err;
+ logic classb_ctrl_shadowed_map_e3_update_err;
+ logic classb_clr_regwen_we;
+ logic classb_clr_regwen_qs;
+ logic classb_clr_regwen_wd;
+ logic classb_clr_shadowed_re;
+ logic classb_clr_shadowed_we;
+ logic classb_clr_shadowed_qs;
+ logic classb_clr_shadowed_wd;
+ logic classb_clr_shadowed_storage_err;
+ logic classb_clr_shadowed_update_err;
+ logic classb_accum_cnt_re;
+ logic [15:0] classb_accum_cnt_qs;
+ logic classb_accum_thresh_shadowed_re;
+ logic classb_accum_thresh_shadowed_we;
+ logic [15:0] classb_accum_thresh_shadowed_qs;
+ logic [15:0] classb_accum_thresh_shadowed_wd;
+ logic classb_accum_thresh_shadowed_storage_err;
+ logic classb_accum_thresh_shadowed_update_err;
+ logic classb_timeout_cyc_shadowed_re;
+ logic classb_timeout_cyc_shadowed_we;
+ logic [31:0] classb_timeout_cyc_shadowed_qs;
+ logic [31:0] classb_timeout_cyc_shadowed_wd;
+ logic classb_timeout_cyc_shadowed_storage_err;
+ logic classb_timeout_cyc_shadowed_update_err;
+ logic classb_crashdump_trigger_shadowed_re;
+ logic classb_crashdump_trigger_shadowed_we;
+ logic [1:0] classb_crashdump_trigger_shadowed_qs;
+ logic [1:0] classb_crashdump_trigger_shadowed_wd;
+ logic classb_crashdump_trigger_shadowed_storage_err;
+ logic classb_crashdump_trigger_shadowed_update_err;
+ logic classb_phase0_cyc_shadowed_re;
+ logic classb_phase0_cyc_shadowed_we;
+ logic [31:0] classb_phase0_cyc_shadowed_qs;
+ logic [31:0] classb_phase0_cyc_shadowed_wd;
+ logic classb_phase0_cyc_shadowed_storage_err;
+ logic classb_phase0_cyc_shadowed_update_err;
+ logic classb_phase1_cyc_shadowed_re;
+ logic classb_phase1_cyc_shadowed_we;
+ logic [31:0] classb_phase1_cyc_shadowed_qs;
+ logic [31:0] classb_phase1_cyc_shadowed_wd;
+ logic classb_phase1_cyc_shadowed_storage_err;
+ logic classb_phase1_cyc_shadowed_update_err;
+ logic classb_phase2_cyc_shadowed_re;
+ logic classb_phase2_cyc_shadowed_we;
+ logic [31:0] classb_phase2_cyc_shadowed_qs;
+ logic [31:0] classb_phase2_cyc_shadowed_wd;
+ logic classb_phase2_cyc_shadowed_storage_err;
+ logic classb_phase2_cyc_shadowed_update_err;
+ logic classb_phase3_cyc_shadowed_re;
+ logic classb_phase3_cyc_shadowed_we;
+ logic [31:0] classb_phase3_cyc_shadowed_qs;
+ logic [31:0] classb_phase3_cyc_shadowed_wd;
+ logic classb_phase3_cyc_shadowed_storage_err;
+ logic classb_phase3_cyc_shadowed_update_err;
+ logic classb_esc_cnt_re;
+ logic [31:0] classb_esc_cnt_qs;
+ logic classb_state_re;
+ logic [2:0] classb_state_qs;
+ logic classc_regwen_we;
+ logic classc_regwen_qs;
+ logic classc_regwen_wd;
+ logic classc_ctrl_shadowed_re;
+ logic classc_ctrl_shadowed_we;
+ logic classc_ctrl_shadowed_en_qs;
+ logic classc_ctrl_shadowed_en_wd;
+ logic classc_ctrl_shadowed_en_storage_err;
+ logic classc_ctrl_shadowed_en_update_err;
+ logic classc_ctrl_shadowed_lock_qs;
+ logic classc_ctrl_shadowed_lock_wd;
+ logic classc_ctrl_shadowed_lock_storage_err;
+ logic classc_ctrl_shadowed_lock_update_err;
+ logic classc_ctrl_shadowed_en_e0_qs;
+ logic classc_ctrl_shadowed_en_e0_wd;
+ logic classc_ctrl_shadowed_en_e0_storage_err;
+ logic classc_ctrl_shadowed_en_e0_update_err;
+ logic classc_ctrl_shadowed_en_e1_qs;
+ logic classc_ctrl_shadowed_en_e1_wd;
+ logic classc_ctrl_shadowed_en_e1_storage_err;
+ logic classc_ctrl_shadowed_en_e1_update_err;
+ logic classc_ctrl_shadowed_en_e2_qs;
+ logic classc_ctrl_shadowed_en_e2_wd;
+ logic classc_ctrl_shadowed_en_e2_storage_err;
+ logic classc_ctrl_shadowed_en_e2_update_err;
+ logic classc_ctrl_shadowed_en_e3_qs;
+ logic classc_ctrl_shadowed_en_e3_wd;
+ logic classc_ctrl_shadowed_en_e3_storage_err;
+ logic classc_ctrl_shadowed_en_e3_update_err;
+ logic [1:0] classc_ctrl_shadowed_map_e0_qs;
+ logic [1:0] classc_ctrl_shadowed_map_e0_wd;
+ logic classc_ctrl_shadowed_map_e0_storage_err;
+ logic classc_ctrl_shadowed_map_e0_update_err;
+ logic [1:0] classc_ctrl_shadowed_map_e1_qs;
+ logic [1:0] classc_ctrl_shadowed_map_e1_wd;
+ logic classc_ctrl_shadowed_map_e1_storage_err;
+ logic classc_ctrl_shadowed_map_e1_update_err;
+ logic [1:0] classc_ctrl_shadowed_map_e2_qs;
+ logic [1:0] classc_ctrl_shadowed_map_e2_wd;
+ logic classc_ctrl_shadowed_map_e2_storage_err;
+ logic classc_ctrl_shadowed_map_e2_update_err;
+ logic [1:0] classc_ctrl_shadowed_map_e3_qs;
+ logic [1:0] classc_ctrl_shadowed_map_e3_wd;
+ logic classc_ctrl_shadowed_map_e3_storage_err;
+ logic classc_ctrl_shadowed_map_e3_update_err;
+ logic classc_clr_regwen_we;
+ logic classc_clr_regwen_qs;
+ logic classc_clr_regwen_wd;
+ logic classc_clr_shadowed_re;
+ logic classc_clr_shadowed_we;
+ logic classc_clr_shadowed_qs;
+ logic classc_clr_shadowed_wd;
+ logic classc_clr_shadowed_storage_err;
+ logic classc_clr_shadowed_update_err;
+ logic classc_accum_cnt_re;
+ logic [15:0] classc_accum_cnt_qs;
+ logic classc_accum_thresh_shadowed_re;
+ logic classc_accum_thresh_shadowed_we;
+ logic [15:0] classc_accum_thresh_shadowed_qs;
+ logic [15:0] classc_accum_thresh_shadowed_wd;
+ logic classc_accum_thresh_shadowed_storage_err;
+ logic classc_accum_thresh_shadowed_update_err;
+ logic classc_timeout_cyc_shadowed_re;
+ logic classc_timeout_cyc_shadowed_we;
+ logic [31:0] classc_timeout_cyc_shadowed_qs;
+ logic [31:0] classc_timeout_cyc_shadowed_wd;
+ logic classc_timeout_cyc_shadowed_storage_err;
+ logic classc_timeout_cyc_shadowed_update_err;
+ logic classc_crashdump_trigger_shadowed_re;
+ logic classc_crashdump_trigger_shadowed_we;
+ logic [1:0] classc_crashdump_trigger_shadowed_qs;
+ logic [1:0] classc_crashdump_trigger_shadowed_wd;
+ logic classc_crashdump_trigger_shadowed_storage_err;
+ logic classc_crashdump_trigger_shadowed_update_err;
+ logic classc_phase0_cyc_shadowed_re;
+ logic classc_phase0_cyc_shadowed_we;
+ logic [31:0] classc_phase0_cyc_shadowed_qs;
+ logic [31:0] classc_phase0_cyc_shadowed_wd;
+ logic classc_phase0_cyc_shadowed_storage_err;
+ logic classc_phase0_cyc_shadowed_update_err;
+ logic classc_phase1_cyc_shadowed_re;
+ logic classc_phase1_cyc_shadowed_we;
+ logic [31:0] classc_phase1_cyc_shadowed_qs;
+ logic [31:0] classc_phase1_cyc_shadowed_wd;
+ logic classc_phase1_cyc_shadowed_storage_err;
+ logic classc_phase1_cyc_shadowed_update_err;
+ logic classc_phase2_cyc_shadowed_re;
+ logic classc_phase2_cyc_shadowed_we;
+ logic [31:0] classc_phase2_cyc_shadowed_qs;
+ logic [31:0] classc_phase2_cyc_shadowed_wd;
+ logic classc_phase2_cyc_shadowed_storage_err;
+ logic classc_phase2_cyc_shadowed_update_err;
+ logic classc_phase3_cyc_shadowed_re;
+ logic classc_phase3_cyc_shadowed_we;
+ logic [31:0] classc_phase3_cyc_shadowed_qs;
+ logic [31:0] classc_phase3_cyc_shadowed_wd;
+ logic classc_phase3_cyc_shadowed_storage_err;
+ logic classc_phase3_cyc_shadowed_update_err;
+ logic classc_esc_cnt_re;
+ logic [31:0] classc_esc_cnt_qs;
+ logic classc_state_re;
+ logic [2:0] classc_state_qs;
+ logic classd_regwen_we;
+ logic classd_regwen_qs;
+ logic classd_regwen_wd;
+ logic classd_ctrl_shadowed_re;
+ logic classd_ctrl_shadowed_we;
+ logic classd_ctrl_shadowed_en_qs;
+ logic classd_ctrl_shadowed_en_wd;
+ logic classd_ctrl_shadowed_en_storage_err;
+ logic classd_ctrl_shadowed_en_update_err;
+ logic classd_ctrl_shadowed_lock_qs;
+ logic classd_ctrl_shadowed_lock_wd;
+ logic classd_ctrl_shadowed_lock_storage_err;
+ logic classd_ctrl_shadowed_lock_update_err;
+ logic classd_ctrl_shadowed_en_e0_qs;
+ logic classd_ctrl_shadowed_en_e0_wd;
+ logic classd_ctrl_shadowed_en_e0_storage_err;
+ logic classd_ctrl_shadowed_en_e0_update_err;
+ logic classd_ctrl_shadowed_en_e1_qs;
+ logic classd_ctrl_shadowed_en_e1_wd;
+ logic classd_ctrl_shadowed_en_e1_storage_err;
+ logic classd_ctrl_shadowed_en_e1_update_err;
+ logic classd_ctrl_shadowed_en_e2_qs;
+ logic classd_ctrl_shadowed_en_e2_wd;
+ logic classd_ctrl_shadowed_en_e2_storage_err;
+ logic classd_ctrl_shadowed_en_e2_update_err;
+ logic classd_ctrl_shadowed_en_e3_qs;
+ logic classd_ctrl_shadowed_en_e3_wd;
+ logic classd_ctrl_shadowed_en_e3_storage_err;
+ logic classd_ctrl_shadowed_en_e3_update_err;
+ logic [1:0] classd_ctrl_shadowed_map_e0_qs;
+ logic [1:0] classd_ctrl_shadowed_map_e0_wd;
+ logic classd_ctrl_shadowed_map_e0_storage_err;
+ logic classd_ctrl_shadowed_map_e0_update_err;
+ logic [1:0] classd_ctrl_shadowed_map_e1_qs;
+ logic [1:0] classd_ctrl_shadowed_map_e1_wd;
+ logic classd_ctrl_shadowed_map_e1_storage_err;
+ logic classd_ctrl_shadowed_map_e1_update_err;
+ logic [1:0] classd_ctrl_shadowed_map_e2_qs;
+ logic [1:0] classd_ctrl_shadowed_map_e2_wd;
+ logic classd_ctrl_shadowed_map_e2_storage_err;
+ logic classd_ctrl_shadowed_map_e2_update_err;
+ logic [1:0] classd_ctrl_shadowed_map_e3_qs;
+ logic [1:0] classd_ctrl_shadowed_map_e3_wd;
+ logic classd_ctrl_shadowed_map_e3_storage_err;
+ logic classd_ctrl_shadowed_map_e3_update_err;
+ logic classd_clr_regwen_we;
+ logic classd_clr_regwen_qs;
+ logic classd_clr_regwen_wd;
+ logic classd_clr_shadowed_re;
+ logic classd_clr_shadowed_we;
+ logic classd_clr_shadowed_qs;
+ logic classd_clr_shadowed_wd;
+ logic classd_clr_shadowed_storage_err;
+ logic classd_clr_shadowed_update_err;
+ logic classd_accum_cnt_re;
+ logic [15:0] classd_accum_cnt_qs;
+ logic classd_accum_thresh_shadowed_re;
+ logic classd_accum_thresh_shadowed_we;
+ logic [15:0] classd_accum_thresh_shadowed_qs;
+ logic [15:0] classd_accum_thresh_shadowed_wd;
+ logic classd_accum_thresh_shadowed_storage_err;
+ logic classd_accum_thresh_shadowed_update_err;
+ logic classd_timeout_cyc_shadowed_re;
+ logic classd_timeout_cyc_shadowed_we;
+ logic [31:0] classd_timeout_cyc_shadowed_qs;
+ logic [31:0] classd_timeout_cyc_shadowed_wd;
+ logic classd_timeout_cyc_shadowed_storage_err;
+ logic classd_timeout_cyc_shadowed_update_err;
+ logic classd_crashdump_trigger_shadowed_re;
+ logic classd_crashdump_trigger_shadowed_we;
+ logic [1:0] classd_crashdump_trigger_shadowed_qs;
+ logic [1:0] classd_crashdump_trigger_shadowed_wd;
+ logic classd_crashdump_trigger_shadowed_storage_err;
+ logic classd_crashdump_trigger_shadowed_update_err;
+ logic classd_phase0_cyc_shadowed_re;
+ logic classd_phase0_cyc_shadowed_we;
+ logic [31:0] classd_phase0_cyc_shadowed_qs;
+ logic [31:0] classd_phase0_cyc_shadowed_wd;
+ logic classd_phase0_cyc_shadowed_storage_err;
+ logic classd_phase0_cyc_shadowed_update_err;
+ logic classd_phase1_cyc_shadowed_re;
+ logic classd_phase1_cyc_shadowed_we;
+ logic [31:0] classd_phase1_cyc_shadowed_qs;
+ logic [31:0] classd_phase1_cyc_shadowed_wd;
+ logic classd_phase1_cyc_shadowed_storage_err;
+ logic classd_phase1_cyc_shadowed_update_err;
+ logic classd_phase2_cyc_shadowed_re;
+ logic classd_phase2_cyc_shadowed_we;
+ logic [31:0] classd_phase2_cyc_shadowed_qs;
+ logic [31:0] classd_phase2_cyc_shadowed_wd;
+ logic classd_phase2_cyc_shadowed_storage_err;
+ logic classd_phase2_cyc_shadowed_update_err;
+ logic classd_phase3_cyc_shadowed_re;
+ logic classd_phase3_cyc_shadowed_we;
+ logic [31:0] classd_phase3_cyc_shadowed_qs;
+ logic [31:0] classd_phase3_cyc_shadowed_wd;
+ logic classd_phase3_cyc_shadowed_storage_err;
+ logic classd_phase3_cyc_shadowed_update_err;
+ logic classd_esc_cnt_re;
+ logic [31:0] classd_esc_cnt_qs;
+ logic classd_state_re;
+ logic [2:0] classd_state_qs;
+
+ // Register instances
+ // R[intr_state]: V(False)
+ // F[classa]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_classa (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_classa_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classa.de),
+ .d (hw2reg.intr_state.classa.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classa.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_classa_qs)
+ );
+
+ // F[classb]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_classb (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_classb_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classb.de),
+ .d (hw2reg.intr_state.classb.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classb.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_classb_qs)
+ );
+
+ // F[classc]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_classc (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_classc_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classc.de),
+ .d (hw2reg.intr_state.classc.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classc.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_classc_qs)
+ );
+
+ // F[classd]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_intr_state_classd (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_state_we),
+ .wd (intr_state_classd_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classd.de),
+ .d (hw2reg.intr_state.classd.d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classd.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_state_classd_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+ // F[classa]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classa (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_classa_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classa.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_classa_qs)
+ );
+
+ // F[classb]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classb (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_classb_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classb.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_classb_qs)
+ );
+
+ // F[classc]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classc (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_classc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classc.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_classc_qs)
+ );
+
+ // F[classd]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classd (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (intr_enable_we),
+ .wd (intr_enable_classd_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classd.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (intr_enable_classd_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+ logic intr_test_qe;
+ logic [3:0] intr_test_flds_we;
+ assign intr_test_qe = &intr_test_flds_we;
+ // F[classa]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classa (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_classa_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[0]),
+ .q (reg2hw.intr_test.classa.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.classa.qe = intr_test_qe;
+
+ // F[classb]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classb (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_classb_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[1]),
+ .q (reg2hw.intr_test.classb.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.classb.qe = intr_test_qe;
+
+ // F[classc]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classc (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_classc_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[2]),
+ .q (reg2hw.intr_test.classc.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.classc.qe = intr_test_qe;
+
+ // F[classd]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classd (
+ .re (1'b0),
+ .we (intr_test_we),
+ .wd (intr_test_classd_wd),
+ .d ('0),
+ .qre (),
+ .qe (intr_test_flds_we[3]),
+ .q (reg2hw.intr_test.classd.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.intr_test.classd.qe = intr_test_qe;
+
+
+ // R[ping_timer_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_ping_timer_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ping_timer_regwen_we),
+ .wd (ping_timer_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ping_timer_regwen_qs)
+ );
+
+
+ // R[ping_timeout_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic ping_timeout_cyc_shadowed_gated_we;
+ assign ping_timeout_cyc_shadowed_gated_we = ping_timeout_cyc_shadowed_we & ping_timer_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (16),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (16'h100)
+ ) u_ping_timeout_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (ping_timeout_cyc_shadowed_re),
+ .we (ping_timeout_cyc_shadowed_gated_we),
+ .wd (ping_timeout_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ping_timeout_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ping_timeout_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (ping_timeout_cyc_shadowed_update_err),
+ .err_storage (ping_timeout_cyc_shadowed_storage_err)
+ );
+
+
+ // R[ping_timer_en_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic ping_timer_en_shadowed_gated_we;
+ assign ping_timer_en_shadowed_gated_we = ping_timer_en_shadowed_we & ping_timer_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1S),
+ .RESVAL (1'h0)
+ ) u_ping_timer_en_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (ping_timer_en_shadowed_re),
+ .we (ping_timer_en_shadowed_gated_we),
+ .wd (ping_timer_en_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ping_timer_en_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ping_timer_en_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (ping_timer_en_shadowed_update_err),
+ .err_storage (ping_timer_en_shadowed_storage_err)
+ );
+
+
+ // Subregister 0 of Multireg alert_regwen
+ // R[alert_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_0_we),
+ .wd (alert_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg alert_regwen
+ // R[alert_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_1_we),
+ .wd (alert_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg alert_regwen
+ // R[alert_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_2_we),
+ .wd (alert_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg alert_regwen
+ // R[alert_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_3_we),
+ .wd (alert_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg alert_regwen
+ // R[alert_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_4_we),
+ .wd (alert_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg alert_regwen
+ // R[alert_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_5_we),
+ .wd (alert_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg alert_regwen
+ // R[alert_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_6_we),
+ .wd (alert_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg alert_regwen
+ // R[alert_regwen_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_7_we),
+ .wd (alert_regwen_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg alert_regwen
+ // R[alert_regwen_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_8_we),
+ .wd (alert_regwen_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg alert_regwen
+ // R[alert_regwen_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_9_we),
+ .wd (alert_regwen_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg alert_regwen
+ // R[alert_regwen_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_10_we),
+ .wd (alert_regwen_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg alert_regwen
+ // R[alert_regwen_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_11_we),
+ .wd (alert_regwen_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg alert_regwen
+ // R[alert_regwen_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_12_we),
+ .wd (alert_regwen_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg alert_regwen
+ // R[alert_regwen_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_13_we),
+ .wd (alert_regwen_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg alert_regwen
+ // R[alert_regwen_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_14_we),
+ .wd (alert_regwen_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg alert_regwen
+ // R[alert_regwen_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_15_we),
+ .wd (alert_regwen_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg alert_regwen
+ // R[alert_regwen_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_16_we),
+ .wd (alert_regwen_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg alert_regwen
+ // R[alert_regwen_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_17_we),
+ .wd (alert_regwen_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg alert_regwen
+ // R[alert_regwen_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_18_we),
+ .wd (alert_regwen_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg alert_regwen
+ // R[alert_regwen_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_19_we),
+ .wd (alert_regwen_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg alert_regwen
+ // R[alert_regwen_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_20_we),
+ .wd (alert_regwen_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg alert_regwen
+ // R[alert_regwen_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_21_we),
+ .wd (alert_regwen_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg alert_regwen
+ // R[alert_regwen_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_22_we),
+ .wd (alert_regwen_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg alert_regwen
+ // R[alert_regwen_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_23_we),
+ .wd (alert_regwen_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg alert_regwen
+ // R[alert_regwen_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_24_we),
+ .wd (alert_regwen_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg alert_regwen
+ // R[alert_regwen_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_25_we),
+ .wd (alert_regwen_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg alert_regwen
+ // R[alert_regwen_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_26_we),
+ .wd (alert_regwen_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg alert_regwen
+ // R[alert_regwen_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_27_we),
+ .wd (alert_regwen_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg alert_regwen
+ // R[alert_regwen_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_28_we),
+ .wd (alert_regwen_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg alert_regwen
+ // R[alert_regwen_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_29_we),
+ .wd (alert_regwen_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg alert_regwen
+ // R[alert_regwen_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_30_we),
+ .wd (alert_regwen_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg alert_regwen
+ // R[alert_regwen_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_31_we),
+ .wd (alert_regwen_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg alert_regwen
+ // R[alert_regwen_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_32_we),
+ .wd (alert_regwen_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg alert_regwen
+ // R[alert_regwen_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_33_we),
+ .wd (alert_regwen_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg alert_regwen
+ // R[alert_regwen_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_34_we),
+ .wd (alert_regwen_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg alert_regwen
+ // R[alert_regwen_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_35_we),
+ .wd (alert_regwen_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg alert_regwen
+ // R[alert_regwen_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_36_we),
+ .wd (alert_regwen_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg alert_regwen
+ // R[alert_regwen_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_37_we),
+ .wd (alert_regwen_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg alert_regwen
+ // R[alert_regwen_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_38_we),
+ .wd (alert_regwen_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg alert_regwen
+ // R[alert_regwen_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_39_we),
+ .wd (alert_regwen_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg alert_regwen
+ // R[alert_regwen_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_40_we),
+ .wd (alert_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg alert_regwen
+ // R[alert_regwen_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_41_we),
+ .wd (alert_regwen_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg alert_regwen
+ // R[alert_regwen_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_42_we),
+ .wd (alert_regwen_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg alert_regwen
+ // R[alert_regwen_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_43_we),
+ .wd (alert_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg alert_regwen
+ // R[alert_regwen_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_44_we),
+ .wd (alert_regwen_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg alert_regwen
+ // R[alert_regwen_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_45_we),
+ .wd (alert_regwen_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg alert_regwen
+ // R[alert_regwen_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_46_we),
+ .wd (alert_regwen_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg alert_regwen
+ // R[alert_regwen_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_47_we),
+ .wd (alert_regwen_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg alert_regwen
+ // R[alert_regwen_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_48_we),
+ .wd (alert_regwen_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg alert_regwen
+ // R[alert_regwen_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_49_we),
+ .wd (alert_regwen_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg alert_regwen
+ // R[alert_regwen_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_50_we),
+ .wd (alert_regwen_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg alert_regwen
+ // R[alert_regwen_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_51_we),
+ .wd (alert_regwen_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg alert_regwen
+ // R[alert_regwen_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_52_we),
+ .wd (alert_regwen_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_52_qs)
+ );
+
+
+ // Subregister 53 of Multireg alert_regwen
+ // R[alert_regwen_53]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_53_we),
+ .wd (alert_regwen_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_53_qs)
+ );
+
+
+ // Subregister 54 of Multireg alert_regwen
+ // R[alert_regwen_54]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_54_we),
+ .wd (alert_regwen_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_54_qs)
+ );
+
+
+ // Subregister 55 of Multireg alert_regwen
+ // R[alert_regwen_55]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_55_we),
+ .wd (alert_regwen_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_55_qs)
+ );
+
+
+ // Subregister 56 of Multireg alert_regwen
+ // R[alert_regwen_56]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_56_we),
+ .wd (alert_regwen_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_56_qs)
+ );
+
+
+ // Subregister 57 of Multireg alert_regwen
+ // R[alert_regwen_57]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_57_we),
+ .wd (alert_regwen_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_57_qs)
+ );
+
+
+ // Subregister 58 of Multireg alert_regwen
+ // R[alert_regwen_58]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_58_we),
+ .wd (alert_regwen_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_58_qs)
+ );
+
+
+ // Subregister 59 of Multireg alert_regwen
+ // R[alert_regwen_59]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_59_we),
+ .wd (alert_regwen_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_59_qs)
+ );
+
+
+ // Subregister 60 of Multireg alert_regwen
+ // R[alert_regwen_60]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_60_we),
+ .wd (alert_regwen_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_60_qs)
+ );
+
+
+ // Subregister 61 of Multireg alert_regwen
+ // R[alert_regwen_61]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_61_we),
+ .wd (alert_regwen_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_61_qs)
+ );
+
+
+ // Subregister 62 of Multireg alert_regwen
+ // R[alert_regwen_62]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_62_we),
+ .wd (alert_regwen_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_62_qs)
+ );
+
+
+ // Subregister 63 of Multireg alert_regwen
+ // R[alert_regwen_63]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_63_we),
+ .wd (alert_regwen_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_63_qs)
+ );
+
+
+ // Subregister 64 of Multireg alert_regwen
+ // R[alert_regwen_64]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_64_we),
+ .wd (alert_regwen_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_64_qs)
+ );
+
+
+ // Subregister 65 of Multireg alert_regwen
+ // R[alert_regwen_65]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_65_we),
+ .wd (alert_regwen_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_65_qs)
+ );
+
+
+ // Subregister 66 of Multireg alert_regwen
+ // R[alert_regwen_66]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_66_we),
+ .wd (alert_regwen_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_66_qs)
+ );
+
+
+ // Subregister 67 of Multireg alert_regwen
+ // R[alert_regwen_67]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_67_we),
+ .wd (alert_regwen_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_67_qs)
+ );
+
+
+ // Subregister 68 of Multireg alert_regwen
+ // R[alert_regwen_68]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_68_we),
+ .wd (alert_regwen_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_68_qs)
+ );
+
+
+ // Subregister 69 of Multireg alert_regwen
+ // R[alert_regwen_69]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_69_we),
+ .wd (alert_regwen_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_69_qs)
+ );
+
+
+ // Subregister 70 of Multireg alert_regwen
+ // R[alert_regwen_70]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_70_we),
+ .wd (alert_regwen_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_70_qs)
+ );
+
+
+ // Subregister 71 of Multireg alert_regwen
+ // R[alert_regwen_71]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_71_we),
+ .wd (alert_regwen_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_71_qs)
+ );
+
+
+ // Subregister 72 of Multireg alert_regwen
+ // R[alert_regwen_72]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_72_we),
+ .wd (alert_regwen_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_72_qs)
+ );
+
+
+ // Subregister 73 of Multireg alert_regwen
+ // R[alert_regwen_73]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_73_we),
+ .wd (alert_regwen_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_73_qs)
+ );
+
+
+ // Subregister 74 of Multireg alert_regwen
+ // R[alert_regwen_74]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_74_we),
+ .wd (alert_regwen_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_regwen_74_qs)
+ );
+
+
+ // Subregister 0 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_0_gated_we;
+ assign alert_en_shadowed_0_gated_we = alert_en_shadowed_0_we & alert_regwen_0_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_0_re),
+ .we (alert_en_shadowed_0_gated_we),
+ .wd (alert_en_shadowed_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_0_update_err),
+ .err_storage (alert_en_shadowed_0_storage_err)
+ );
+
+
+ // Subregister 1 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_1_gated_we;
+ assign alert_en_shadowed_1_gated_we = alert_en_shadowed_1_we & alert_regwen_1_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_1_re),
+ .we (alert_en_shadowed_1_gated_we),
+ .wd (alert_en_shadowed_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_1_update_err),
+ .err_storage (alert_en_shadowed_1_storage_err)
+ );
+
+
+ // Subregister 2 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_2_gated_we;
+ assign alert_en_shadowed_2_gated_we = alert_en_shadowed_2_we & alert_regwen_2_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_2_re),
+ .we (alert_en_shadowed_2_gated_we),
+ .wd (alert_en_shadowed_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_2_update_err),
+ .err_storage (alert_en_shadowed_2_storage_err)
+ );
+
+
+ // Subregister 3 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_3_gated_we;
+ assign alert_en_shadowed_3_gated_we = alert_en_shadowed_3_we & alert_regwen_3_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_3_re),
+ .we (alert_en_shadowed_3_gated_we),
+ .wd (alert_en_shadowed_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_3_update_err),
+ .err_storage (alert_en_shadowed_3_storage_err)
+ );
+
+
+ // Subregister 4 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_4_gated_we;
+ assign alert_en_shadowed_4_gated_we = alert_en_shadowed_4_we & alert_regwen_4_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_4_re),
+ .we (alert_en_shadowed_4_gated_we),
+ .wd (alert_en_shadowed_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_4_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_4_update_err),
+ .err_storage (alert_en_shadowed_4_storage_err)
+ );
+
+
+ // Subregister 5 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_5_gated_we;
+ assign alert_en_shadowed_5_gated_we = alert_en_shadowed_5_we & alert_regwen_5_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_5_re),
+ .we (alert_en_shadowed_5_gated_we),
+ .wd (alert_en_shadowed_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_5_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_5_update_err),
+ .err_storage (alert_en_shadowed_5_storage_err)
+ );
+
+
+ // Subregister 6 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_6_gated_we;
+ assign alert_en_shadowed_6_gated_we = alert_en_shadowed_6_we & alert_regwen_6_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_6_re),
+ .we (alert_en_shadowed_6_gated_we),
+ .wd (alert_en_shadowed_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_6_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_6_update_err),
+ .err_storage (alert_en_shadowed_6_storage_err)
+ );
+
+
+ // Subregister 7 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_7_gated_we;
+ assign alert_en_shadowed_7_gated_we = alert_en_shadowed_7_we & alert_regwen_7_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_7_re),
+ .we (alert_en_shadowed_7_gated_we),
+ .wd (alert_en_shadowed_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_7_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_7_update_err),
+ .err_storage (alert_en_shadowed_7_storage_err)
+ );
+
+
+ // Subregister 8 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_8_gated_we;
+ assign alert_en_shadowed_8_gated_we = alert_en_shadowed_8_we & alert_regwen_8_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_8_re),
+ .we (alert_en_shadowed_8_gated_we),
+ .wd (alert_en_shadowed_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_8_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_8_update_err),
+ .err_storage (alert_en_shadowed_8_storage_err)
+ );
+
+
+ // Subregister 9 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_9_gated_we;
+ assign alert_en_shadowed_9_gated_we = alert_en_shadowed_9_we & alert_regwen_9_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_9_re),
+ .we (alert_en_shadowed_9_gated_we),
+ .wd (alert_en_shadowed_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_9_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_9_update_err),
+ .err_storage (alert_en_shadowed_9_storage_err)
+ );
+
+
+ // Subregister 10 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_10_gated_we;
+ assign alert_en_shadowed_10_gated_we = alert_en_shadowed_10_we & alert_regwen_10_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_10_re),
+ .we (alert_en_shadowed_10_gated_we),
+ .wd (alert_en_shadowed_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_10_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_10_update_err),
+ .err_storage (alert_en_shadowed_10_storage_err)
+ );
+
+
+ // Subregister 11 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_11_gated_we;
+ assign alert_en_shadowed_11_gated_we = alert_en_shadowed_11_we & alert_regwen_11_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_11_re),
+ .we (alert_en_shadowed_11_gated_we),
+ .wd (alert_en_shadowed_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_11_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_11_update_err),
+ .err_storage (alert_en_shadowed_11_storage_err)
+ );
+
+
+ // Subregister 12 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_12_gated_we;
+ assign alert_en_shadowed_12_gated_we = alert_en_shadowed_12_we & alert_regwen_12_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_12_re),
+ .we (alert_en_shadowed_12_gated_we),
+ .wd (alert_en_shadowed_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_12_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_12_update_err),
+ .err_storage (alert_en_shadowed_12_storage_err)
+ );
+
+
+ // Subregister 13 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_13_gated_we;
+ assign alert_en_shadowed_13_gated_we = alert_en_shadowed_13_we & alert_regwen_13_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_13_re),
+ .we (alert_en_shadowed_13_gated_we),
+ .wd (alert_en_shadowed_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_13_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_13_update_err),
+ .err_storage (alert_en_shadowed_13_storage_err)
+ );
+
+
+ // Subregister 14 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_14_gated_we;
+ assign alert_en_shadowed_14_gated_we = alert_en_shadowed_14_we & alert_regwen_14_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_14_re),
+ .we (alert_en_shadowed_14_gated_we),
+ .wd (alert_en_shadowed_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_14_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_14_update_err),
+ .err_storage (alert_en_shadowed_14_storage_err)
+ );
+
+
+ // Subregister 15 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_15_gated_we;
+ assign alert_en_shadowed_15_gated_we = alert_en_shadowed_15_we & alert_regwen_15_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_15_re),
+ .we (alert_en_shadowed_15_gated_we),
+ .wd (alert_en_shadowed_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_15_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_15_update_err),
+ .err_storage (alert_en_shadowed_15_storage_err)
+ );
+
+
+ // Subregister 16 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_16_gated_we;
+ assign alert_en_shadowed_16_gated_we = alert_en_shadowed_16_we & alert_regwen_16_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_16_re),
+ .we (alert_en_shadowed_16_gated_we),
+ .wd (alert_en_shadowed_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_16_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_16_update_err),
+ .err_storage (alert_en_shadowed_16_storage_err)
+ );
+
+
+ // Subregister 17 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_17_gated_we;
+ assign alert_en_shadowed_17_gated_we = alert_en_shadowed_17_we & alert_regwen_17_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_17_re),
+ .we (alert_en_shadowed_17_gated_we),
+ .wd (alert_en_shadowed_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_17_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_17_update_err),
+ .err_storage (alert_en_shadowed_17_storage_err)
+ );
+
+
+ // Subregister 18 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_18_gated_we;
+ assign alert_en_shadowed_18_gated_we = alert_en_shadowed_18_we & alert_regwen_18_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_18_re),
+ .we (alert_en_shadowed_18_gated_we),
+ .wd (alert_en_shadowed_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_18_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_18_update_err),
+ .err_storage (alert_en_shadowed_18_storage_err)
+ );
+
+
+ // Subregister 19 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_19_gated_we;
+ assign alert_en_shadowed_19_gated_we = alert_en_shadowed_19_we & alert_regwen_19_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_19_re),
+ .we (alert_en_shadowed_19_gated_we),
+ .wd (alert_en_shadowed_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_19_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_19_update_err),
+ .err_storage (alert_en_shadowed_19_storage_err)
+ );
+
+
+ // Subregister 20 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_20_gated_we;
+ assign alert_en_shadowed_20_gated_we = alert_en_shadowed_20_we & alert_regwen_20_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_20_re),
+ .we (alert_en_shadowed_20_gated_we),
+ .wd (alert_en_shadowed_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_20_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_20_update_err),
+ .err_storage (alert_en_shadowed_20_storage_err)
+ );
+
+
+ // Subregister 21 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_21_gated_we;
+ assign alert_en_shadowed_21_gated_we = alert_en_shadowed_21_we & alert_regwen_21_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_21_re),
+ .we (alert_en_shadowed_21_gated_we),
+ .wd (alert_en_shadowed_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_21_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_21_update_err),
+ .err_storage (alert_en_shadowed_21_storage_err)
+ );
+
+
+ // Subregister 22 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_22_gated_we;
+ assign alert_en_shadowed_22_gated_we = alert_en_shadowed_22_we & alert_regwen_22_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_22_re),
+ .we (alert_en_shadowed_22_gated_we),
+ .wd (alert_en_shadowed_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_22_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_22_update_err),
+ .err_storage (alert_en_shadowed_22_storage_err)
+ );
+
+
+ // Subregister 23 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_23_gated_we;
+ assign alert_en_shadowed_23_gated_we = alert_en_shadowed_23_we & alert_regwen_23_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_23_re),
+ .we (alert_en_shadowed_23_gated_we),
+ .wd (alert_en_shadowed_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_23_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_23_update_err),
+ .err_storage (alert_en_shadowed_23_storage_err)
+ );
+
+
+ // Subregister 24 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_24_gated_we;
+ assign alert_en_shadowed_24_gated_we = alert_en_shadowed_24_we & alert_regwen_24_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_24_re),
+ .we (alert_en_shadowed_24_gated_we),
+ .wd (alert_en_shadowed_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_24_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_24_update_err),
+ .err_storage (alert_en_shadowed_24_storage_err)
+ );
+
+
+ // Subregister 25 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_25_gated_we;
+ assign alert_en_shadowed_25_gated_we = alert_en_shadowed_25_we & alert_regwen_25_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_25_re),
+ .we (alert_en_shadowed_25_gated_we),
+ .wd (alert_en_shadowed_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_25_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_25_update_err),
+ .err_storage (alert_en_shadowed_25_storage_err)
+ );
+
+
+ // Subregister 26 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_26_gated_we;
+ assign alert_en_shadowed_26_gated_we = alert_en_shadowed_26_we & alert_regwen_26_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_26_re),
+ .we (alert_en_shadowed_26_gated_we),
+ .wd (alert_en_shadowed_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_26_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_26_update_err),
+ .err_storage (alert_en_shadowed_26_storage_err)
+ );
+
+
+ // Subregister 27 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_27_gated_we;
+ assign alert_en_shadowed_27_gated_we = alert_en_shadowed_27_we & alert_regwen_27_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_27_re),
+ .we (alert_en_shadowed_27_gated_we),
+ .wd (alert_en_shadowed_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_27_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_27_update_err),
+ .err_storage (alert_en_shadowed_27_storage_err)
+ );
+
+
+ // Subregister 28 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_28_gated_we;
+ assign alert_en_shadowed_28_gated_we = alert_en_shadowed_28_we & alert_regwen_28_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_28_re),
+ .we (alert_en_shadowed_28_gated_we),
+ .wd (alert_en_shadowed_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_28_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_28_update_err),
+ .err_storage (alert_en_shadowed_28_storage_err)
+ );
+
+
+ // Subregister 29 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_29_gated_we;
+ assign alert_en_shadowed_29_gated_we = alert_en_shadowed_29_we & alert_regwen_29_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_29_re),
+ .we (alert_en_shadowed_29_gated_we),
+ .wd (alert_en_shadowed_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_29_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_29_update_err),
+ .err_storage (alert_en_shadowed_29_storage_err)
+ );
+
+
+ // Subregister 30 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_30_gated_we;
+ assign alert_en_shadowed_30_gated_we = alert_en_shadowed_30_we & alert_regwen_30_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_30_re),
+ .we (alert_en_shadowed_30_gated_we),
+ .wd (alert_en_shadowed_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_30_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_30_update_err),
+ .err_storage (alert_en_shadowed_30_storage_err)
+ );
+
+
+ // Subregister 31 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_31_gated_we;
+ assign alert_en_shadowed_31_gated_we = alert_en_shadowed_31_we & alert_regwen_31_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_31_re),
+ .we (alert_en_shadowed_31_gated_we),
+ .wd (alert_en_shadowed_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_31_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_31_update_err),
+ .err_storage (alert_en_shadowed_31_storage_err)
+ );
+
+
+ // Subregister 32 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_32_gated_we;
+ assign alert_en_shadowed_32_gated_we = alert_en_shadowed_32_we & alert_regwen_32_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_32_re),
+ .we (alert_en_shadowed_32_gated_we),
+ .wd (alert_en_shadowed_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_32_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_32_update_err),
+ .err_storage (alert_en_shadowed_32_storage_err)
+ );
+
+
+ // Subregister 33 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_33_gated_we;
+ assign alert_en_shadowed_33_gated_we = alert_en_shadowed_33_we & alert_regwen_33_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_33_re),
+ .we (alert_en_shadowed_33_gated_we),
+ .wd (alert_en_shadowed_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_33_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_33_update_err),
+ .err_storage (alert_en_shadowed_33_storage_err)
+ );
+
+
+ // Subregister 34 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_34_gated_we;
+ assign alert_en_shadowed_34_gated_we = alert_en_shadowed_34_we & alert_regwen_34_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_34_re),
+ .we (alert_en_shadowed_34_gated_we),
+ .wd (alert_en_shadowed_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_34_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_34_update_err),
+ .err_storage (alert_en_shadowed_34_storage_err)
+ );
+
+
+ // Subregister 35 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_35_gated_we;
+ assign alert_en_shadowed_35_gated_we = alert_en_shadowed_35_we & alert_regwen_35_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_35_re),
+ .we (alert_en_shadowed_35_gated_we),
+ .wd (alert_en_shadowed_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_35_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_35_update_err),
+ .err_storage (alert_en_shadowed_35_storage_err)
+ );
+
+
+ // Subregister 36 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_36_gated_we;
+ assign alert_en_shadowed_36_gated_we = alert_en_shadowed_36_we & alert_regwen_36_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_36_re),
+ .we (alert_en_shadowed_36_gated_we),
+ .wd (alert_en_shadowed_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_36_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_36_update_err),
+ .err_storage (alert_en_shadowed_36_storage_err)
+ );
+
+
+ // Subregister 37 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_37_gated_we;
+ assign alert_en_shadowed_37_gated_we = alert_en_shadowed_37_we & alert_regwen_37_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_37_re),
+ .we (alert_en_shadowed_37_gated_we),
+ .wd (alert_en_shadowed_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_37_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_37_update_err),
+ .err_storage (alert_en_shadowed_37_storage_err)
+ );
+
+
+ // Subregister 38 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_38_gated_we;
+ assign alert_en_shadowed_38_gated_we = alert_en_shadowed_38_we & alert_regwen_38_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_38_re),
+ .we (alert_en_shadowed_38_gated_we),
+ .wd (alert_en_shadowed_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_38_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_38_update_err),
+ .err_storage (alert_en_shadowed_38_storage_err)
+ );
+
+
+ // Subregister 39 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_39_gated_we;
+ assign alert_en_shadowed_39_gated_we = alert_en_shadowed_39_we & alert_regwen_39_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_39_re),
+ .we (alert_en_shadowed_39_gated_we),
+ .wd (alert_en_shadowed_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_39_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_39_update_err),
+ .err_storage (alert_en_shadowed_39_storage_err)
+ );
+
+
+ // Subregister 40 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_40_gated_we;
+ assign alert_en_shadowed_40_gated_we = alert_en_shadowed_40_we & alert_regwen_40_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_40_re),
+ .we (alert_en_shadowed_40_gated_we),
+ .wd (alert_en_shadowed_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_40_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_40_update_err),
+ .err_storage (alert_en_shadowed_40_storage_err)
+ );
+
+
+ // Subregister 41 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_41_gated_we;
+ assign alert_en_shadowed_41_gated_we = alert_en_shadowed_41_we & alert_regwen_41_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_41_re),
+ .we (alert_en_shadowed_41_gated_we),
+ .wd (alert_en_shadowed_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_41_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_41_update_err),
+ .err_storage (alert_en_shadowed_41_storage_err)
+ );
+
+
+ // Subregister 42 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_42_gated_we;
+ assign alert_en_shadowed_42_gated_we = alert_en_shadowed_42_we & alert_regwen_42_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_42_re),
+ .we (alert_en_shadowed_42_gated_we),
+ .wd (alert_en_shadowed_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_42_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_42_update_err),
+ .err_storage (alert_en_shadowed_42_storage_err)
+ );
+
+
+ // Subregister 43 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_43_gated_we;
+ assign alert_en_shadowed_43_gated_we = alert_en_shadowed_43_we & alert_regwen_43_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_43_re),
+ .we (alert_en_shadowed_43_gated_we),
+ .wd (alert_en_shadowed_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_43_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_43_update_err),
+ .err_storage (alert_en_shadowed_43_storage_err)
+ );
+
+
+ // Subregister 44 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_44_gated_we;
+ assign alert_en_shadowed_44_gated_we = alert_en_shadowed_44_we & alert_regwen_44_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_44_re),
+ .we (alert_en_shadowed_44_gated_we),
+ .wd (alert_en_shadowed_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_44_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_44_update_err),
+ .err_storage (alert_en_shadowed_44_storage_err)
+ );
+
+
+ // Subregister 45 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_45_gated_we;
+ assign alert_en_shadowed_45_gated_we = alert_en_shadowed_45_we & alert_regwen_45_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_45_re),
+ .we (alert_en_shadowed_45_gated_we),
+ .wd (alert_en_shadowed_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_45_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_45_update_err),
+ .err_storage (alert_en_shadowed_45_storage_err)
+ );
+
+
+ // Subregister 46 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_46_gated_we;
+ assign alert_en_shadowed_46_gated_we = alert_en_shadowed_46_we & alert_regwen_46_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_46_re),
+ .we (alert_en_shadowed_46_gated_we),
+ .wd (alert_en_shadowed_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_46_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_46_update_err),
+ .err_storage (alert_en_shadowed_46_storage_err)
+ );
+
+
+ // Subregister 47 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_47_gated_we;
+ assign alert_en_shadowed_47_gated_we = alert_en_shadowed_47_we & alert_regwen_47_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_47_re),
+ .we (alert_en_shadowed_47_gated_we),
+ .wd (alert_en_shadowed_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_47_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_47_update_err),
+ .err_storage (alert_en_shadowed_47_storage_err)
+ );
+
+
+ // Subregister 48 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_48_gated_we;
+ assign alert_en_shadowed_48_gated_we = alert_en_shadowed_48_we & alert_regwen_48_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_48_re),
+ .we (alert_en_shadowed_48_gated_we),
+ .wd (alert_en_shadowed_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_48_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_48_update_err),
+ .err_storage (alert_en_shadowed_48_storage_err)
+ );
+
+
+ // Subregister 49 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_49_gated_we;
+ assign alert_en_shadowed_49_gated_we = alert_en_shadowed_49_we & alert_regwen_49_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_49_re),
+ .we (alert_en_shadowed_49_gated_we),
+ .wd (alert_en_shadowed_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_49_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_49_update_err),
+ .err_storage (alert_en_shadowed_49_storage_err)
+ );
+
+
+ // Subregister 50 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_50_gated_we;
+ assign alert_en_shadowed_50_gated_we = alert_en_shadowed_50_we & alert_regwen_50_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_50_re),
+ .we (alert_en_shadowed_50_gated_we),
+ .wd (alert_en_shadowed_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_50_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_50_update_err),
+ .err_storage (alert_en_shadowed_50_storage_err)
+ );
+
+
+ // Subregister 51 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_51_gated_we;
+ assign alert_en_shadowed_51_gated_we = alert_en_shadowed_51_we & alert_regwen_51_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_51_re),
+ .we (alert_en_shadowed_51_gated_we),
+ .wd (alert_en_shadowed_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_51_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_51_update_err),
+ .err_storage (alert_en_shadowed_51_storage_err)
+ );
+
+
+ // Subregister 52 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_52_gated_we;
+ assign alert_en_shadowed_52_gated_we = alert_en_shadowed_52_we & alert_regwen_52_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_52_re),
+ .we (alert_en_shadowed_52_gated_we),
+ .wd (alert_en_shadowed_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_52_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_52_update_err),
+ .err_storage (alert_en_shadowed_52_storage_err)
+ );
+
+
+ // Subregister 53 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_53]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_53_gated_we;
+ assign alert_en_shadowed_53_gated_we = alert_en_shadowed_53_we & alert_regwen_53_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_53_re),
+ .we (alert_en_shadowed_53_gated_we),
+ .wd (alert_en_shadowed_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_53_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_53_update_err),
+ .err_storage (alert_en_shadowed_53_storage_err)
+ );
+
+
+ // Subregister 54 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_54]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_54_gated_we;
+ assign alert_en_shadowed_54_gated_we = alert_en_shadowed_54_we & alert_regwen_54_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_54_re),
+ .we (alert_en_shadowed_54_gated_we),
+ .wd (alert_en_shadowed_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_54_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_54_update_err),
+ .err_storage (alert_en_shadowed_54_storage_err)
+ );
+
+
+ // Subregister 55 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_55]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_55_gated_we;
+ assign alert_en_shadowed_55_gated_we = alert_en_shadowed_55_we & alert_regwen_55_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_55_re),
+ .we (alert_en_shadowed_55_gated_we),
+ .wd (alert_en_shadowed_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_55_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_55_update_err),
+ .err_storage (alert_en_shadowed_55_storage_err)
+ );
+
+
+ // Subregister 56 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_56]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_56_gated_we;
+ assign alert_en_shadowed_56_gated_we = alert_en_shadowed_56_we & alert_regwen_56_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_56_re),
+ .we (alert_en_shadowed_56_gated_we),
+ .wd (alert_en_shadowed_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_56_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_56_update_err),
+ .err_storage (alert_en_shadowed_56_storage_err)
+ );
+
+
+ // Subregister 57 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_57]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_57_gated_we;
+ assign alert_en_shadowed_57_gated_we = alert_en_shadowed_57_we & alert_regwen_57_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_57_re),
+ .we (alert_en_shadowed_57_gated_we),
+ .wd (alert_en_shadowed_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_57_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_57_update_err),
+ .err_storage (alert_en_shadowed_57_storage_err)
+ );
+
+
+ // Subregister 58 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_58]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_58_gated_we;
+ assign alert_en_shadowed_58_gated_we = alert_en_shadowed_58_we & alert_regwen_58_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_58_re),
+ .we (alert_en_shadowed_58_gated_we),
+ .wd (alert_en_shadowed_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_58_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_58_update_err),
+ .err_storage (alert_en_shadowed_58_storage_err)
+ );
+
+
+ // Subregister 59 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_59]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_59_gated_we;
+ assign alert_en_shadowed_59_gated_we = alert_en_shadowed_59_we & alert_regwen_59_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_59_re),
+ .we (alert_en_shadowed_59_gated_we),
+ .wd (alert_en_shadowed_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_59_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_59_update_err),
+ .err_storage (alert_en_shadowed_59_storage_err)
+ );
+
+
+ // Subregister 60 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_60]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_60_gated_we;
+ assign alert_en_shadowed_60_gated_we = alert_en_shadowed_60_we & alert_regwen_60_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_60_re),
+ .we (alert_en_shadowed_60_gated_we),
+ .wd (alert_en_shadowed_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_60_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_60_update_err),
+ .err_storage (alert_en_shadowed_60_storage_err)
+ );
+
+
+ // Subregister 61 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_61]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_61_gated_we;
+ assign alert_en_shadowed_61_gated_we = alert_en_shadowed_61_we & alert_regwen_61_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_61_re),
+ .we (alert_en_shadowed_61_gated_we),
+ .wd (alert_en_shadowed_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_61_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_61_update_err),
+ .err_storage (alert_en_shadowed_61_storage_err)
+ );
+
+
+ // Subregister 62 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_62]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_62_gated_we;
+ assign alert_en_shadowed_62_gated_we = alert_en_shadowed_62_we & alert_regwen_62_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_62_re),
+ .we (alert_en_shadowed_62_gated_we),
+ .wd (alert_en_shadowed_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_62_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_62_update_err),
+ .err_storage (alert_en_shadowed_62_storage_err)
+ );
+
+
+ // Subregister 63 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_63]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_63_gated_we;
+ assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_63_re),
+ .we (alert_en_shadowed_63_gated_we),
+ .wd (alert_en_shadowed_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_63_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_63_update_err),
+ .err_storage (alert_en_shadowed_63_storage_err)
+ );
+
+
+ // Subregister 64 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_64]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_64_gated_we;
+ assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_64_re),
+ .we (alert_en_shadowed_64_gated_we),
+ .wd (alert_en_shadowed_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_64_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_64_update_err),
+ .err_storage (alert_en_shadowed_64_storage_err)
+ );
+
+
+ // Subregister 65 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_65]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_65_gated_we;
+ assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_65_re),
+ .we (alert_en_shadowed_65_gated_we),
+ .wd (alert_en_shadowed_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_65_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_65_update_err),
+ .err_storage (alert_en_shadowed_65_storage_err)
+ );
+
+
+ // Subregister 66 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_66]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_66_gated_we;
+ assign alert_en_shadowed_66_gated_we = alert_en_shadowed_66_we & alert_regwen_66_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_66_re),
+ .we (alert_en_shadowed_66_gated_we),
+ .wd (alert_en_shadowed_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_66_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_66_update_err),
+ .err_storage (alert_en_shadowed_66_storage_err)
+ );
+
+
+ // Subregister 67 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_67]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_67_gated_we;
+ assign alert_en_shadowed_67_gated_we = alert_en_shadowed_67_we & alert_regwen_67_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_67_re),
+ .we (alert_en_shadowed_67_gated_we),
+ .wd (alert_en_shadowed_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_67_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_67_update_err),
+ .err_storage (alert_en_shadowed_67_storage_err)
+ );
+
+
+ // Subregister 68 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_68]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_68_gated_we;
+ assign alert_en_shadowed_68_gated_we = alert_en_shadowed_68_we & alert_regwen_68_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_68_re),
+ .we (alert_en_shadowed_68_gated_we),
+ .wd (alert_en_shadowed_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_68_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_68_update_err),
+ .err_storage (alert_en_shadowed_68_storage_err)
+ );
+
+
+ // Subregister 69 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_69]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_69_gated_we;
+ assign alert_en_shadowed_69_gated_we = alert_en_shadowed_69_we & alert_regwen_69_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_69_re),
+ .we (alert_en_shadowed_69_gated_we),
+ .wd (alert_en_shadowed_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_69_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_69_update_err),
+ .err_storage (alert_en_shadowed_69_storage_err)
+ );
+
+
+ // Subregister 70 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_70]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_70_gated_we;
+ assign alert_en_shadowed_70_gated_we = alert_en_shadowed_70_we & alert_regwen_70_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_70_re),
+ .we (alert_en_shadowed_70_gated_we),
+ .wd (alert_en_shadowed_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_70_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_70_update_err),
+ .err_storage (alert_en_shadowed_70_storage_err)
+ );
+
+
+ // Subregister 71 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_71]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_71_gated_we;
+ assign alert_en_shadowed_71_gated_we = alert_en_shadowed_71_we & alert_regwen_71_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_71_re),
+ .we (alert_en_shadowed_71_gated_we),
+ .wd (alert_en_shadowed_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_71_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_71_update_err),
+ .err_storage (alert_en_shadowed_71_storage_err)
+ );
+
+
+ // Subregister 72 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_72]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_72_gated_we;
+ assign alert_en_shadowed_72_gated_we = alert_en_shadowed_72_we & alert_regwen_72_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_72_re),
+ .we (alert_en_shadowed_72_gated_we),
+ .wd (alert_en_shadowed_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_72_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_72_update_err),
+ .err_storage (alert_en_shadowed_72_storage_err)
+ );
+
+
+ // Subregister 73 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_73]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_73_gated_we;
+ assign alert_en_shadowed_73_gated_we = alert_en_shadowed_73_we & alert_regwen_73_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_73_re),
+ .we (alert_en_shadowed_73_gated_we),
+ .wd (alert_en_shadowed_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_73_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_73_update_err),
+ .err_storage (alert_en_shadowed_73_storage_err)
+ );
+
+
+ // Subregister 74 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_74]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_en_shadowed_74_gated_we;
+ assign alert_en_shadowed_74_gated_we = alert_en_shadowed_74_we & alert_regwen_74_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_74_re),
+ .we (alert_en_shadowed_74_gated_we),
+ .wd (alert_en_shadowed_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_74_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_en_shadowed_74_update_err),
+ .err_storage (alert_en_shadowed_74_storage_err)
+ );
+
+
+ // Subregister 0 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_0_gated_we;
+ assign alert_class_shadowed_0_gated_we = alert_class_shadowed_0_we & alert_regwen_0_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_0_re),
+ .we (alert_class_shadowed_0_gated_we),
+ .wd (alert_class_shadowed_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_0_update_err),
+ .err_storage (alert_class_shadowed_0_storage_err)
+ );
+
+
+ // Subregister 1 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_1_gated_we;
+ assign alert_class_shadowed_1_gated_we = alert_class_shadowed_1_we & alert_regwen_1_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_1_re),
+ .we (alert_class_shadowed_1_gated_we),
+ .wd (alert_class_shadowed_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_1_update_err),
+ .err_storage (alert_class_shadowed_1_storage_err)
+ );
+
+
+ // Subregister 2 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_2_gated_we;
+ assign alert_class_shadowed_2_gated_we = alert_class_shadowed_2_we & alert_regwen_2_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_2_re),
+ .we (alert_class_shadowed_2_gated_we),
+ .wd (alert_class_shadowed_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_2_update_err),
+ .err_storage (alert_class_shadowed_2_storage_err)
+ );
+
+
+ // Subregister 3 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_3_gated_we;
+ assign alert_class_shadowed_3_gated_we = alert_class_shadowed_3_we & alert_regwen_3_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_3_re),
+ .we (alert_class_shadowed_3_gated_we),
+ .wd (alert_class_shadowed_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_3_update_err),
+ .err_storage (alert_class_shadowed_3_storage_err)
+ );
+
+
+ // Subregister 4 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_4_gated_we;
+ assign alert_class_shadowed_4_gated_we = alert_class_shadowed_4_we & alert_regwen_4_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_4_re),
+ .we (alert_class_shadowed_4_gated_we),
+ .wd (alert_class_shadowed_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_4_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_4_update_err),
+ .err_storage (alert_class_shadowed_4_storage_err)
+ );
+
+
+ // Subregister 5 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_5_gated_we;
+ assign alert_class_shadowed_5_gated_we = alert_class_shadowed_5_we & alert_regwen_5_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_5_re),
+ .we (alert_class_shadowed_5_gated_we),
+ .wd (alert_class_shadowed_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_5_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_5_update_err),
+ .err_storage (alert_class_shadowed_5_storage_err)
+ );
+
+
+ // Subregister 6 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_6_gated_we;
+ assign alert_class_shadowed_6_gated_we = alert_class_shadowed_6_we & alert_regwen_6_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_6_re),
+ .we (alert_class_shadowed_6_gated_we),
+ .wd (alert_class_shadowed_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_6_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_6_update_err),
+ .err_storage (alert_class_shadowed_6_storage_err)
+ );
+
+
+ // Subregister 7 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_7]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_7_gated_we;
+ assign alert_class_shadowed_7_gated_we = alert_class_shadowed_7_we & alert_regwen_7_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_7_re),
+ .we (alert_class_shadowed_7_gated_we),
+ .wd (alert_class_shadowed_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_7_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_7_update_err),
+ .err_storage (alert_class_shadowed_7_storage_err)
+ );
+
+
+ // Subregister 8 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_8]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_8_gated_we;
+ assign alert_class_shadowed_8_gated_we = alert_class_shadowed_8_we & alert_regwen_8_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_8_re),
+ .we (alert_class_shadowed_8_gated_we),
+ .wd (alert_class_shadowed_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_8_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_8_update_err),
+ .err_storage (alert_class_shadowed_8_storage_err)
+ );
+
+
+ // Subregister 9 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_9]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_9_gated_we;
+ assign alert_class_shadowed_9_gated_we = alert_class_shadowed_9_we & alert_regwen_9_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_9_re),
+ .we (alert_class_shadowed_9_gated_we),
+ .wd (alert_class_shadowed_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_9_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_9_update_err),
+ .err_storage (alert_class_shadowed_9_storage_err)
+ );
+
+
+ // Subregister 10 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_10]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_10_gated_we;
+ assign alert_class_shadowed_10_gated_we = alert_class_shadowed_10_we & alert_regwen_10_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_10_re),
+ .we (alert_class_shadowed_10_gated_we),
+ .wd (alert_class_shadowed_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_10_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_10_update_err),
+ .err_storage (alert_class_shadowed_10_storage_err)
+ );
+
+
+ // Subregister 11 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_11]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_11_gated_we;
+ assign alert_class_shadowed_11_gated_we = alert_class_shadowed_11_we & alert_regwen_11_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_11_re),
+ .we (alert_class_shadowed_11_gated_we),
+ .wd (alert_class_shadowed_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_11_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_11_update_err),
+ .err_storage (alert_class_shadowed_11_storage_err)
+ );
+
+
+ // Subregister 12 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_12]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_12_gated_we;
+ assign alert_class_shadowed_12_gated_we = alert_class_shadowed_12_we & alert_regwen_12_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_12_re),
+ .we (alert_class_shadowed_12_gated_we),
+ .wd (alert_class_shadowed_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_12_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_12_update_err),
+ .err_storage (alert_class_shadowed_12_storage_err)
+ );
+
+
+ // Subregister 13 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_13]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_13_gated_we;
+ assign alert_class_shadowed_13_gated_we = alert_class_shadowed_13_we & alert_regwen_13_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_13_re),
+ .we (alert_class_shadowed_13_gated_we),
+ .wd (alert_class_shadowed_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_13_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_13_update_err),
+ .err_storage (alert_class_shadowed_13_storage_err)
+ );
+
+
+ // Subregister 14 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_14]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_14_gated_we;
+ assign alert_class_shadowed_14_gated_we = alert_class_shadowed_14_we & alert_regwen_14_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_14_re),
+ .we (alert_class_shadowed_14_gated_we),
+ .wd (alert_class_shadowed_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_14_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_14_update_err),
+ .err_storage (alert_class_shadowed_14_storage_err)
+ );
+
+
+ // Subregister 15 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_15]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_15_gated_we;
+ assign alert_class_shadowed_15_gated_we = alert_class_shadowed_15_we & alert_regwen_15_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_15_re),
+ .we (alert_class_shadowed_15_gated_we),
+ .wd (alert_class_shadowed_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_15_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_15_update_err),
+ .err_storage (alert_class_shadowed_15_storage_err)
+ );
+
+
+ // Subregister 16 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_16]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_16_gated_we;
+ assign alert_class_shadowed_16_gated_we = alert_class_shadowed_16_we & alert_regwen_16_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_16_re),
+ .we (alert_class_shadowed_16_gated_we),
+ .wd (alert_class_shadowed_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_16_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_16_update_err),
+ .err_storage (alert_class_shadowed_16_storage_err)
+ );
+
+
+ // Subregister 17 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_17]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_17_gated_we;
+ assign alert_class_shadowed_17_gated_we = alert_class_shadowed_17_we & alert_regwen_17_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_17_re),
+ .we (alert_class_shadowed_17_gated_we),
+ .wd (alert_class_shadowed_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_17_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_17_update_err),
+ .err_storage (alert_class_shadowed_17_storage_err)
+ );
+
+
+ // Subregister 18 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_18]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_18_gated_we;
+ assign alert_class_shadowed_18_gated_we = alert_class_shadowed_18_we & alert_regwen_18_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_18_re),
+ .we (alert_class_shadowed_18_gated_we),
+ .wd (alert_class_shadowed_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_18_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_18_update_err),
+ .err_storage (alert_class_shadowed_18_storage_err)
+ );
+
+
+ // Subregister 19 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_19]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_19_gated_we;
+ assign alert_class_shadowed_19_gated_we = alert_class_shadowed_19_we & alert_regwen_19_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_19_re),
+ .we (alert_class_shadowed_19_gated_we),
+ .wd (alert_class_shadowed_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_19_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_19_update_err),
+ .err_storage (alert_class_shadowed_19_storage_err)
+ );
+
+
+ // Subregister 20 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_20]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_20_gated_we;
+ assign alert_class_shadowed_20_gated_we = alert_class_shadowed_20_we & alert_regwen_20_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_20_re),
+ .we (alert_class_shadowed_20_gated_we),
+ .wd (alert_class_shadowed_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_20_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_20_update_err),
+ .err_storage (alert_class_shadowed_20_storage_err)
+ );
+
+
+ // Subregister 21 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_21]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_21_gated_we;
+ assign alert_class_shadowed_21_gated_we = alert_class_shadowed_21_we & alert_regwen_21_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_21_re),
+ .we (alert_class_shadowed_21_gated_we),
+ .wd (alert_class_shadowed_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_21_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_21_update_err),
+ .err_storage (alert_class_shadowed_21_storage_err)
+ );
+
+
+ // Subregister 22 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_22]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_22_gated_we;
+ assign alert_class_shadowed_22_gated_we = alert_class_shadowed_22_we & alert_regwen_22_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_22_re),
+ .we (alert_class_shadowed_22_gated_we),
+ .wd (alert_class_shadowed_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_22_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_22_update_err),
+ .err_storage (alert_class_shadowed_22_storage_err)
+ );
+
+
+ // Subregister 23 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_23]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_23_gated_we;
+ assign alert_class_shadowed_23_gated_we = alert_class_shadowed_23_we & alert_regwen_23_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_23_re),
+ .we (alert_class_shadowed_23_gated_we),
+ .wd (alert_class_shadowed_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_23_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_23_update_err),
+ .err_storage (alert_class_shadowed_23_storage_err)
+ );
+
+
+ // Subregister 24 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_24]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_24_gated_we;
+ assign alert_class_shadowed_24_gated_we = alert_class_shadowed_24_we & alert_regwen_24_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_24_re),
+ .we (alert_class_shadowed_24_gated_we),
+ .wd (alert_class_shadowed_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_24_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_24_update_err),
+ .err_storage (alert_class_shadowed_24_storage_err)
+ );
+
+
+ // Subregister 25 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_25]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_25_gated_we;
+ assign alert_class_shadowed_25_gated_we = alert_class_shadowed_25_we & alert_regwen_25_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_25_re),
+ .we (alert_class_shadowed_25_gated_we),
+ .wd (alert_class_shadowed_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_25_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_25_update_err),
+ .err_storage (alert_class_shadowed_25_storage_err)
+ );
+
+
+ // Subregister 26 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_26]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_26_gated_we;
+ assign alert_class_shadowed_26_gated_we = alert_class_shadowed_26_we & alert_regwen_26_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_26_re),
+ .we (alert_class_shadowed_26_gated_we),
+ .wd (alert_class_shadowed_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_26_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_26_update_err),
+ .err_storage (alert_class_shadowed_26_storage_err)
+ );
+
+
+ // Subregister 27 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_27]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_27_gated_we;
+ assign alert_class_shadowed_27_gated_we = alert_class_shadowed_27_we & alert_regwen_27_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_27_re),
+ .we (alert_class_shadowed_27_gated_we),
+ .wd (alert_class_shadowed_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_27_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_27_update_err),
+ .err_storage (alert_class_shadowed_27_storage_err)
+ );
+
+
+ // Subregister 28 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_28]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_28_gated_we;
+ assign alert_class_shadowed_28_gated_we = alert_class_shadowed_28_we & alert_regwen_28_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_28_re),
+ .we (alert_class_shadowed_28_gated_we),
+ .wd (alert_class_shadowed_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_28_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_28_update_err),
+ .err_storage (alert_class_shadowed_28_storage_err)
+ );
+
+
+ // Subregister 29 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_29]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_29_gated_we;
+ assign alert_class_shadowed_29_gated_we = alert_class_shadowed_29_we & alert_regwen_29_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_29_re),
+ .we (alert_class_shadowed_29_gated_we),
+ .wd (alert_class_shadowed_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_29_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_29_update_err),
+ .err_storage (alert_class_shadowed_29_storage_err)
+ );
+
+
+ // Subregister 30 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_30]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_30_gated_we;
+ assign alert_class_shadowed_30_gated_we = alert_class_shadowed_30_we & alert_regwen_30_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_30_re),
+ .we (alert_class_shadowed_30_gated_we),
+ .wd (alert_class_shadowed_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_30_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_30_update_err),
+ .err_storage (alert_class_shadowed_30_storage_err)
+ );
+
+
+ // Subregister 31 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_31]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_31_gated_we;
+ assign alert_class_shadowed_31_gated_we = alert_class_shadowed_31_we & alert_regwen_31_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_31_re),
+ .we (alert_class_shadowed_31_gated_we),
+ .wd (alert_class_shadowed_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_31_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_31_update_err),
+ .err_storage (alert_class_shadowed_31_storage_err)
+ );
+
+
+ // Subregister 32 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_32]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_32_gated_we;
+ assign alert_class_shadowed_32_gated_we = alert_class_shadowed_32_we & alert_regwen_32_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_32_re),
+ .we (alert_class_shadowed_32_gated_we),
+ .wd (alert_class_shadowed_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_32_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_32_update_err),
+ .err_storage (alert_class_shadowed_32_storage_err)
+ );
+
+
+ // Subregister 33 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_33]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_33_gated_we;
+ assign alert_class_shadowed_33_gated_we = alert_class_shadowed_33_we & alert_regwen_33_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_33_re),
+ .we (alert_class_shadowed_33_gated_we),
+ .wd (alert_class_shadowed_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_33_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_33_update_err),
+ .err_storage (alert_class_shadowed_33_storage_err)
+ );
+
+
+ // Subregister 34 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_34]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_34_gated_we;
+ assign alert_class_shadowed_34_gated_we = alert_class_shadowed_34_we & alert_regwen_34_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_34_re),
+ .we (alert_class_shadowed_34_gated_we),
+ .wd (alert_class_shadowed_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_34_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_34_update_err),
+ .err_storage (alert_class_shadowed_34_storage_err)
+ );
+
+
+ // Subregister 35 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_35]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_35_gated_we;
+ assign alert_class_shadowed_35_gated_we = alert_class_shadowed_35_we & alert_regwen_35_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_35_re),
+ .we (alert_class_shadowed_35_gated_we),
+ .wd (alert_class_shadowed_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_35_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_35_update_err),
+ .err_storage (alert_class_shadowed_35_storage_err)
+ );
+
+
+ // Subregister 36 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_36]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_36_gated_we;
+ assign alert_class_shadowed_36_gated_we = alert_class_shadowed_36_we & alert_regwen_36_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_36_re),
+ .we (alert_class_shadowed_36_gated_we),
+ .wd (alert_class_shadowed_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_36_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_36_update_err),
+ .err_storage (alert_class_shadowed_36_storage_err)
+ );
+
+
+ // Subregister 37 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_37]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_37_gated_we;
+ assign alert_class_shadowed_37_gated_we = alert_class_shadowed_37_we & alert_regwen_37_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_37_re),
+ .we (alert_class_shadowed_37_gated_we),
+ .wd (alert_class_shadowed_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_37_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_37_update_err),
+ .err_storage (alert_class_shadowed_37_storage_err)
+ );
+
+
+ // Subregister 38 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_38]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_38_gated_we;
+ assign alert_class_shadowed_38_gated_we = alert_class_shadowed_38_we & alert_regwen_38_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_38_re),
+ .we (alert_class_shadowed_38_gated_we),
+ .wd (alert_class_shadowed_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_38_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_38_update_err),
+ .err_storage (alert_class_shadowed_38_storage_err)
+ );
+
+
+ // Subregister 39 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_39]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_39_gated_we;
+ assign alert_class_shadowed_39_gated_we = alert_class_shadowed_39_we & alert_regwen_39_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_39_re),
+ .we (alert_class_shadowed_39_gated_we),
+ .wd (alert_class_shadowed_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_39_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_39_update_err),
+ .err_storage (alert_class_shadowed_39_storage_err)
+ );
+
+
+ // Subregister 40 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_40]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_40_gated_we;
+ assign alert_class_shadowed_40_gated_we = alert_class_shadowed_40_we & alert_regwen_40_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_40_re),
+ .we (alert_class_shadowed_40_gated_we),
+ .wd (alert_class_shadowed_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_40_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_40_update_err),
+ .err_storage (alert_class_shadowed_40_storage_err)
+ );
+
+
+ // Subregister 41 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_41]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_41_gated_we;
+ assign alert_class_shadowed_41_gated_we = alert_class_shadowed_41_we & alert_regwen_41_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_41_re),
+ .we (alert_class_shadowed_41_gated_we),
+ .wd (alert_class_shadowed_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_41_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_41_update_err),
+ .err_storage (alert_class_shadowed_41_storage_err)
+ );
+
+
+ // Subregister 42 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_42]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_42_gated_we;
+ assign alert_class_shadowed_42_gated_we = alert_class_shadowed_42_we & alert_regwen_42_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_42_re),
+ .we (alert_class_shadowed_42_gated_we),
+ .wd (alert_class_shadowed_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_42_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_42_update_err),
+ .err_storage (alert_class_shadowed_42_storage_err)
+ );
+
+
+ // Subregister 43 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_43]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_43_gated_we;
+ assign alert_class_shadowed_43_gated_we = alert_class_shadowed_43_we & alert_regwen_43_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_43_re),
+ .we (alert_class_shadowed_43_gated_we),
+ .wd (alert_class_shadowed_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_43_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_43_update_err),
+ .err_storage (alert_class_shadowed_43_storage_err)
+ );
+
+
+ // Subregister 44 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_44]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_44_gated_we;
+ assign alert_class_shadowed_44_gated_we = alert_class_shadowed_44_we & alert_regwen_44_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_44_re),
+ .we (alert_class_shadowed_44_gated_we),
+ .wd (alert_class_shadowed_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_44_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_44_update_err),
+ .err_storage (alert_class_shadowed_44_storage_err)
+ );
+
+
+ // Subregister 45 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_45]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_45_gated_we;
+ assign alert_class_shadowed_45_gated_we = alert_class_shadowed_45_we & alert_regwen_45_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_45_re),
+ .we (alert_class_shadowed_45_gated_we),
+ .wd (alert_class_shadowed_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_45_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_45_update_err),
+ .err_storage (alert_class_shadowed_45_storage_err)
+ );
+
+
+ // Subregister 46 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_46]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_46_gated_we;
+ assign alert_class_shadowed_46_gated_we = alert_class_shadowed_46_we & alert_regwen_46_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_46_re),
+ .we (alert_class_shadowed_46_gated_we),
+ .wd (alert_class_shadowed_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_46_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_46_update_err),
+ .err_storage (alert_class_shadowed_46_storage_err)
+ );
+
+
+ // Subregister 47 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_47]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_47_gated_we;
+ assign alert_class_shadowed_47_gated_we = alert_class_shadowed_47_we & alert_regwen_47_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_47_re),
+ .we (alert_class_shadowed_47_gated_we),
+ .wd (alert_class_shadowed_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_47_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_47_update_err),
+ .err_storage (alert_class_shadowed_47_storage_err)
+ );
+
+
+ // Subregister 48 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_48]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_48_gated_we;
+ assign alert_class_shadowed_48_gated_we = alert_class_shadowed_48_we & alert_regwen_48_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_48_re),
+ .we (alert_class_shadowed_48_gated_we),
+ .wd (alert_class_shadowed_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_48_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_48_update_err),
+ .err_storage (alert_class_shadowed_48_storage_err)
+ );
+
+
+ // Subregister 49 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_49]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_49_gated_we;
+ assign alert_class_shadowed_49_gated_we = alert_class_shadowed_49_we & alert_regwen_49_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_49_re),
+ .we (alert_class_shadowed_49_gated_we),
+ .wd (alert_class_shadowed_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_49_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_49_update_err),
+ .err_storage (alert_class_shadowed_49_storage_err)
+ );
+
+
+ // Subregister 50 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_50]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_50_gated_we;
+ assign alert_class_shadowed_50_gated_we = alert_class_shadowed_50_we & alert_regwen_50_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_50_re),
+ .we (alert_class_shadowed_50_gated_we),
+ .wd (alert_class_shadowed_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_50_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_50_update_err),
+ .err_storage (alert_class_shadowed_50_storage_err)
+ );
+
+
+ // Subregister 51 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_51]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_51_gated_we;
+ assign alert_class_shadowed_51_gated_we = alert_class_shadowed_51_we & alert_regwen_51_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_51_re),
+ .we (alert_class_shadowed_51_gated_we),
+ .wd (alert_class_shadowed_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_51_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_51_update_err),
+ .err_storage (alert_class_shadowed_51_storage_err)
+ );
+
+
+ // Subregister 52 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_52]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_52_gated_we;
+ assign alert_class_shadowed_52_gated_we = alert_class_shadowed_52_we & alert_regwen_52_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_52_re),
+ .we (alert_class_shadowed_52_gated_we),
+ .wd (alert_class_shadowed_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_52_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_52_update_err),
+ .err_storage (alert_class_shadowed_52_storage_err)
+ );
+
+
+ // Subregister 53 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_53]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_53_gated_we;
+ assign alert_class_shadowed_53_gated_we = alert_class_shadowed_53_we & alert_regwen_53_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_53_re),
+ .we (alert_class_shadowed_53_gated_we),
+ .wd (alert_class_shadowed_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_53_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_53_update_err),
+ .err_storage (alert_class_shadowed_53_storage_err)
+ );
+
+
+ // Subregister 54 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_54]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_54_gated_we;
+ assign alert_class_shadowed_54_gated_we = alert_class_shadowed_54_we & alert_regwen_54_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_54_re),
+ .we (alert_class_shadowed_54_gated_we),
+ .wd (alert_class_shadowed_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_54_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_54_update_err),
+ .err_storage (alert_class_shadowed_54_storage_err)
+ );
+
+
+ // Subregister 55 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_55]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_55_gated_we;
+ assign alert_class_shadowed_55_gated_we = alert_class_shadowed_55_we & alert_regwen_55_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_55_re),
+ .we (alert_class_shadowed_55_gated_we),
+ .wd (alert_class_shadowed_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_55_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_55_update_err),
+ .err_storage (alert_class_shadowed_55_storage_err)
+ );
+
+
+ // Subregister 56 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_56]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_56_gated_we;
+ assign alert_class_shadowed_56_gated_we = alert_class_shadowed_56_we & alert_regwen_56_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_56_re),
+ .we (alert_class_shadowed_56_gated_we),
+ .wd (alert_class_shadowed_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_56_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_56_update_err),
+ .err_storage (alert_class_shadowed_56_storage_err)
+ );
+
+
+ // Subregister 57 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_57]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_57_gated_we;
+ assign alert_class_shadowed_57_gated_we = alert_class_shadowed_57_we & alert_regwen_57_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_57_re),
+ .we (alert_class_shadowed_57_gated_we),
+ .wd (alert_class_shadowed_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_57_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_57_update_err),
+ .err_storage (alert_class_shadowed_57_storage_err)
+ );
+
+
+ // Subregister 58 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_58]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_58_gated_we;
+ assign alert_class_shadowed_58_gated_we = alert_class_shadowed_58_we & alert_regwen_58_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_58_re),
+ .we (alert_class_shadowed_58_gated_we),
+ .wd (alert_class_shadowed_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_58_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_58_update_err),
+ .err_storage (alert_class_shadowed_58_storage_err)
+ );
+
+
+ // Subregister 59 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_59]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_59_gated_we;
+ assign alert_class_shadowed_59_gated_we = alert_class_shadowed_59_we & alert_regwen_59_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_59_re),
+ .we (alert_class_shadowed_59_gated_we),
+ .wd (alert_class_shadowed_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_59_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_59_update_err),
+ .err_storage (alert_class_shadowed_59_storage_err)
+ );
+
+
+ // Subregister 60 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_60]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_60_gated_we;
+ assign alert_class_shadowed_60_gated_we = alert_class_shadowed_60_we & alert_regwen_60_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_60_re),
+ .we (alert_class_shadowed_60_gated_we),
+ .wd (alert_class_shadowed_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_60_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_60_update_err),
+ .err_storage (alert_class_shadowed_60_storage_err)
+ );
+
+
+ // Subregister 61 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_61]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_61_gated_we;
+ assign alert_class_shadowed_61_gated_we = alert_class_shadowed_61_we & alert_regwen_61_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_61_re),
+ .we (alert_class_shadowed_61_gated_we),
+ .wd (alert_class_shadowed_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_61_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_61_update_err),
+ .err_storage (alert_class_shadowed_61_storage_err)
+ );
+
+
+ // Subregister 62 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_62]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_62_gated_we;
+ assign alert_class_shadowed_62_gated_we = alert_class_shadowed_62_we & alert_regwen_62_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_62_re),
+ .we (alert_class_shadowed_62_gated_we),
+ .wd (alert_class_shadowed_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_62_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_62_update_err),
+ .err_storage (alert_class_shadowed_62_storage_err)
+ );
+
+
+ // Subregister 63 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_63]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_63_gated_we;
+ assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_63_re),
+ .we (alert_class_shadowed_63_gated_we),
+ .wd (alert_class_shadowed_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_63_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_63_update_err),
+ .err_storage (alert_class_shadowed_63_storage_err)
+ );
+
+
+ // Subregister 64 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_64]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_64_gated_we;
+ assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_64_re),
+ .we (alert_class_shadowed_64_gated_we),
+ .wd (alert_class_shadowed_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_64_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_64_update_err),
+ .err_storage (alert_class_shadowed_64_storage_err)
+ );
+
+
+ // Subregister 65 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_65]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_65_gated_we;
+ assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_65_re),
+ .we (alert_class_shadowed_65_gated_we),
+ .wd (alert_class_shadowed_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_65_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_65_update_err),
+ .err_storage (alert_class_shadowed_65_storage_err)
+ );
+
+
+ // Subregister 66 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_66]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_66_gated_we;
+ assign alert_class_shadowed_66_gated_we = alert_class_shadowed_66_we & alert_regwen_66_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_66_re),
+ .we (alert_class_shadowed_66_gated_we),
+ .wd (alert_class_shadowed_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_66_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_66_update_err),
+ .err_storage (alert_class_shadowed_66_storage_err)
+ );
+
+
+ // Subregister 67 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_67]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_67_gated_we;
+ assign alert_class_shadowed_67_gated_we = alert_class_shadowed_67_we & alert_regwen_67_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_67_re),
+ .we (alert_class_shadowed_67_gated_we),
+ .wd (alert_class_shadowed_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_67_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_67_update_err),
+ .err_storage (alert_class_shadowed_67_storage_err)
+ );
+
+
+ // Subregister 68 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_68]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_68_gated_we;
+ assign alert_class_shadowed_68_gated_we = alert_class_shadowed_68_we & alert_regwen_68_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_68_re),
+ .we (alert_class_shadowed_68_gated_we),
+ .wd (alert_class_shadowed_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_68_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_68_update_err),
+ .err_storage (alert_class_shadowed_68_storage_err)
+ );
+
+
+ // Subregister 69 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_69]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_69_gated_we;
+ assign alert_class_shadowed_69_gated_we = alert_class_shadowed_69_we & alert_regwen_69_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_69_re),
+ .we (alert_class_shadowed_69_gated_we),
+ .wd (alert_class_shadowed_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_69_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_69_update_err),
+ .err_storage (alert_class_shadowed_69_storage_err)
+ );
+
+
+ // Subregister 70 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_70]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_70_gated_we;
+ assign alert_class_shadowed_70_gated_we = alert_class_shadowed_70_we & alert_regwen_70_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_70_re),
+ .we (alert_class_shadowed_70_gated_we),
+ .wd (alert_class_shadowed_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_70_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_70_update_err),
+ .err_storage (alert_class_shadowed_70_storage_err)
+ );
+
+
+ // Subregister 71 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_71]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_71_gated_we;
+ assign alert_class_shadowed_71_gated_we = alert_class_shadowed_71_we & alert_regwen_71_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_71_re),
+ .we (alert_class_shadowed_71_gated_we),
+ .wd (alert_class_shadowed_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_71_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_71_update_err),
+ .err_storage (alert_class_shadowed_71_storage_err)
+ );
+
+
+ // Subregister 72 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_72]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_72_gated_we;
+ assign alert_class_shadowed_72_gated_we = alert_class_shadowed_72_we & alert_regwen_72_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_72_re),
+ .we (alert_class_shadowed_72_gated_we),
+ .wd (alert_class_shadowed_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_72_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_72_update_err),
+ .err_storage (alert_class_shadowed_72_storage_err)
+ );
+
+
+ // Subregister 73 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_73]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_73_gated_we;
+ assign alert_class_shadowed_73_gated_we = alert_class_shadowed_73_we & alert_regwen_73_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_73_re),
+ .we (alert_class_shadowed_73_gated_we),
+ .wd (alert_class_shadowed_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_73_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_73_update_err),
+ .err_storage (alert_class_shadowed_73_storage_err)
+ );
+
+
+ // Subregister 74 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_74]: V(False)
+ // Create REGWEN-gated WE signal
+ logic alert_class_shadowed_74_gated_we;
+ assign alert_class_shadowed_74_gated_we = alert_class_shadowed_74_we & alert_regwen_74_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_74_re),
+ .we (alert_class_shadowed_74_gated_we),
+ .wd (alert_class_shadowed_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_74_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (alert_class_shadowed_74_update_err),
+ .err_storage (alert_class_shadowed_74_storage_err)
+ );
+
+
+ // Subregister 0 of Multireg alert_cause
+ // R[alert_cause_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_0_we),
+ .wd (alert_cause_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[0].de),
+ .d (hw2reg.alert_cause[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg alert_cause
+ // R[alert_cause_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_1_we),
+ .wd (alert_cause_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[1].de),
+ .d (hw2reg.alert_cause[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg alert_cause
+ // R[alert_cause_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_2_we),
+ .wd (alert_cause_2_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[2].de),
+ .d (hw2reg.alert_cause[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg alert_cause
+ // R[alert_cause_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_3_we),
+ .wd (alert_cause_3_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[3].de),
+ .d (hw2reg.alert_cause[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg alert_cause
+ // R[alert_cause_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_4_we),
+ .wd (alert_cause_4_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[4].de),
+ .d (hw2reg.alert_cause[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg alert_cause
+ // R[alert_cause_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_5_we),
+ .wd (alert_cause_5_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[5].de),
+ .d (hw2reg.alert_cause[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg alert_cause
+ // R[alert_cause_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_6_we),
+ .wd (alert_cause_6_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[6].de),
+ .d (hw2reg.alert_cause[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_6_qs)
+ );
+
+
+ // Subregister 7 of Multireg alert_cause
+ // R[alert_cause_7]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_7_we),
+ .wd (alert_cause_7_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[7].de),
+ .d (hw2reg.alert_cause[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_7_qs)
+ );
+
+
+ // Subregister 8 of Multireg alert_cause
+ // R[alert_cause_8]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_8_we),
+ .wd (alert_cause_8_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[8].de),
+ .d (hw2reg.alert_cause[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_8_qs)
+ );
+
+
+ // Subregister 9 of Multireg alert_cause
+ // R[alert_cause_9]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_9_we),
+ .wd (alert_cause_9_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[9].de),
+ .d (hw2reg.alert_cause[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_9_qs)
+ );
+
+
+ // Subregister 10 of Multireg alert_cause
+ // R[alert_cause_10]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_10_we),
+ .wd (alert_cause_10_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[10].de),
+ .d (hw2reg.alert_cause[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_10_qs)
+ );
+
+
+ // Subregister 11 of Multireg alert_cause
+ // R[alert_cause_11]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_11_we),
+ .wd (alert_cause_11_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[11].de),
+ .d (hw2reg.alert_cause[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_11_qs)
+ );
+
+
+ // Subregister 12 of Multireg alert_cause
+ // R[alert_cause_12]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_12_we),
+ .wd (alert_cause_12_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[12].de),
+ .d (hw2reg.alert_cause[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_12_qs)
+ );
+
+
+ // Subregister 13 of Multireg alert_cause
+ // R[alert_cause_13]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_13_we),
+ .wd (alert_cause_13_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[13].de),
+ .d (hw2reg.alert_cause[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_13_qs)
+ );
+
+
+ // Subregister 14 of Multireg alert_cause
+ // R[alert_cause_14]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_14_we),
+ .wd (alert_cause_14_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[14].de),
+ .d (hw2reg.alert_cause[14].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_14_qs)
+ );
+
+
+ // Subregister 15 of Multireg alert_cause
+ // R[alert_cause_15]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_15_we),
+ .wd (alert_cause_15_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[15].de),
+ .d (hw2reg.alert_cause[15].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_15_qs)
+ );
+
+
+ // Subregister 16 of Multireg alert_cause
+ // R[alert_cause_16]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_16_we),
+ .wd (alert_cause_16_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[16].de),
+ .d (hw2reg.alert_cause[16].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_16_qs)
+ );
+
+
+ // Subregister 17 of Multireg alert_cause
+ // R[alert_cause_17]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_17_we),
+ .wd (alert_cause_17_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[17].de),
+ .d (hw2reg.alert_cause[17].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_17_qs)
+ );
+
+
+ // Subregister 18 of Multireg alert_cause
+ // R[alert_cause_18]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_18_we),
+ .wd (alert_cause_18_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[18].de),
+ .d (hw2reg.alert_cause[18].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_18_qs)
+ );
+
+
+ // Subregister 19 of Multireg alert_cause
+ // R[alert_cause_19]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_19_we),
+ .wd (alert_cause_19_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[19].de),
+ .d (hw2reg.alert_cause[19].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_19_qs)
+ );
+
+
+ // Subregister 20 of Multireg alert_cause
+ // R[alert_cause_20]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_20_we),
+ .wd (alert_cause_20_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[20].de),
+ .d (hw2reg.alert_cause[20].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_20_qs)
+ );
+
+
+ // Subregister 21 of Multireg alert_cause
+ // R[alert_cause_21]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_21_we),
+ .wd (alert_cause_21_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[21].de),
+ .d (hw2reg.alert_cause[21].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_21_qs)
+ );
+
+
+ // Subregister 22 of Multireg alert_cause
+ // R[alert_cause_22]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_22_we),
+ .wd (alert_cause_22_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[22].de),
+ .d (hw2reg.alert_cause[22].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_22_qs)
+ );
+
+
+ // Subregister 23 of Multireg alert_cause
+ // R[alert_cause_23]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_23_we),
+ .wd (alert_cause_23_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[23].de),
+ .d (hw2reg.alert_cause[23].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_23_qs)
+ );
+
+
+ // Subregister 24 of Multireg alert_cause
+ // R[alert_cause_24]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_24_we),
+ .wd (alert_cause_24_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[24].de),
+ .d (hw2reg.alert_cause[24].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_24_qs)
+ );
+
+
+ // Subregister 25 of Multireg alert_cause
+ // R[alert_cause_25]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_25_we),
+ .wd (alert_cause_25_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[25].de),
+ .d (hw2reg.alert_cause[25].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_25_qs)
+ );
+
+
+ // Subregister 26 of Multireg alert_cause
+ // R[alert_cause_26]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_26_we),
+ .wd (alert_cause_26_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[26].de),
+ .d (hw2reg.alert_cause[26].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_26_qs)
+ );
+
+
+ // Subregister 27 of Multireg alert_cause
+ // R[alert_cause_27]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_27_we),
+ .wd (alert_cause_27_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[27].de),
+ .d (hw2reg.alert_cause[27].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_27_qs)
+ );
+
+
+ // Subregister 28 of Multireg alert_cause
+ // R[alert_cause_28]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_28_we),
+ .wd (alert_cause_28_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[28].de),
+ .d (hw2reg.alert_cause[28].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_28_qs)
+ );
+
+
+ // Subregister 29 of Multireg alert_cause
+ // R[alert_cause_29]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_29_we),
+ .wd (alert_cause_29_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[29].de),
+ .d (hw2reg.alert_cause[29].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_29_qs)
+ );
+
+
+ // Subregister 30 of Multireg alert_cause
+ // R[alert_cause_30]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_30_we),
+ .wd (alert_cause_30_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[30].de),
+ .d (hw2reg.alert_cause[30].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_30_qs)
+ );
+
+
+ // Subregister 31 of Multireg alert_cause
+ // R[alert_cause_31]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_31_we),
+ .wd (alert_cause_31_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[31].de),
+ .d (hw2reg.alert_cause[31].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_31_qs)
+ );
+
+
+ // Subregister 32 of Multireg alert_cause
+ // R[alert_cause_32]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_32_we),
+ .wd (alert_cause_32_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[32].de),
+ .d (hw2reg.alert_cause[32].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_32_qs)
+ );
+
+
+ // Subregister 33 of Multireg alert_cause
+ // R[alert_cause_33]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_33_we),
+ .wd (alert_cause_33_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[33].de),
+ .d (hw2reg.alert_cause[33].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_33_qs)
+ );
+
+
+ // Subregister 34 of Multireg alert_cause
+ // R[alert_cause_34]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_34_we),
+ .wd (alert_cause_34_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[34].de),
+ .d (hw2reg.alert_cause[34].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_34_qs)
+ );
+
+
+ // Subregister 35 of Multireg alert_cause
+ // R[alert_cause_35]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_35_we),
+ .wd (alert_cause_35_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[35].de),
+ .d (hw2reg.alert_cause[35].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_35_qs)
+ );
+
+
+ // Subregister 36 of Multireg alert_cause
+ // R[alert_cause_36]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_36_we),
+ .wd (alert_cause_36_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[36].de),
+ .d (hw2reg.alert_cause[36].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_36_qs)
+ );
+
+
+ // Subregister 37 of Multireg alert_cause
+ // R[alert_cause_37]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_37_we),
+ .wd (alert_cause_37_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[37].de),
+ .d (hw2reg.alert_cause[37].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_37_qs)
+ );
+
+
+ // Subregister 38 of Multireg alert_cause
+ // R[alert_cause_38]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_38_we),
+ .wd (alert_cause_38_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[38].de),
+ .d (hw2reg.alert_cause[38].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_38_qs)
+ );
+
+
+ // Subregister 39 of Multireg alert_cause
+ // R[alert_cause_39]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_39_we),
+ .wd (alert_cause_39_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[39].de),
+ .d (hw2reg.alert_cause[39].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_39_qs)
+ );
+
+
+ // Subregister 40 of Multireg alert_cause
+ // R[alert_cause_40]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_40_we),
+ .wd (alert_cause_40_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[40].de),
+ .d (hw2reg.alert_cause[40].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_40_qs)
+ );
+
+
+ // Subregister 41 of Multireg alert_cause
+ // R[alert_cause_41]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_41_we),
+ .wd (alert_cause_41_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[41].de),
+ .d (hw2reg.alert_cause[41].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_41_qs)
+ );
+
+
+ // Subregister 42 of Multireg alert_cause
+ // R[alert_cause_42]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_42_we),
+ .wd (alert_cause_42_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[42].de),
+ .d (hw2reg.alert_cause[42].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_42_qs)
+ );
+
+
+ // Subregister 43 of Multireg alert_cause
+ // R[alert_cause_43]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_43_we),
+ .wd (alert_cause_43_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[43].de),
+ .d (hw2reg.alert_cause[43].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_43_qs)
+ );
+
+
+ // Subregister 44 of Multireg alert_cause
+ // R[alert_cause_44]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_44_we),
+ .wd (alert_cause_44_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[44].de),
+ .d (hw2reg.alert_cause[44].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_44_qs)
+ );
+
+
+ // Subregister 45 of Multireg alert_cause
+ // R[alert_cause_45]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_45_we),
+ .wd (alert_cause_45_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[45].de),
+ .d (hw2reg.alert_cause[45].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_45_qs)
+ );
+
+
+ // Subregister 46 of Multireg alert_cause
+ // R[alert_cause_46]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_46_we),
+ .wd (alert_cause_46_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[46].de),
+ .d (hw2reg.alert_cause[46].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_46_qs)
+ );
+
+
+ // Subregister 47 of Multireg alert_cause
+ // R[alert_cause_47]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_47_we),
+ .wd (alert_cause_47_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[47].de),
+ .d (hw2reg.alert_cause[47].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_47_qs)
+ );
+
+
+ // Subregister 48 of Multireg alert_cause
+ // R[alert_cause_48]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_48_we),
+ .wd (alert_cause_48_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[48].de),
+ .d (hw2reg.alert_cause[48].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_48_qs)
+ );
+
+
+ // Subregister 49 of Multireg alert_cause
+ // R[alert_cause_49]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_49_we),
+ .wd (alert_cause_49_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[49].de),
+ .d (hw2reg.alert_cause[49].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_49_qs)
+ );
+
+
+ // Subregister 50 of Multireg alert_cause
+ // R[alert_cause_50]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_50_we),
+ .wd (alert_cause_50_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[50].de),
+ .d (hw2reg.alert_cause[50].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_50_qs)
+ );
+
+
+ // Subregister 51 of Multireg alert_cause
+ // R[alert_cause_51]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_51_we),
+ .wd (alert_cause_51_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[51].de),
+ .d (hw2reg.alert_cause[51].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_51_qs)
+ );
+
+
+ // Subregister 52 of Multireg alert_cause
+ // R[alert_cause_52]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_52_we),
+ .wd (alert_cause_52_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[52].de),
+ .d (hw2reg.alert_cause[52].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_52_qs)
+ );
+
+
+ // Subregister 53 of Multireg alert_cause
+ // R[alert_cause_53]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_53_we),
+ .wd (alert_cause_53_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[53].de),
+ .d (hw2reg.alert_cause[53].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_53_qs)
+ );
+
+
+ // Subregister 54 of Multireg alert_cause
+ // R[alert_cause_54]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_54_we),
+ .wd (alert_cause_54_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[54].de),
+ .d (hw2reg.alert_cause[54].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_54_qs)
+ );
+
+
+ // Subregister 55 of Multireg alert_cause
+ // R[alert_cause_55]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_55_we),
+ .wd (alert_cause_55_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[55].de),
+ .d (hw2reg.alert_cause[55].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_55_qs)
+ );
+
+
+ // Subregister 56 of Multireg alert_cause
+ // R[alert_cause_56]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_56_we),
+ .wd (alert_cause_56_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[56].de),
+ .d (hw2reg.alert_cause[56].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_56_qs)
+ );
+
+
+ // Subregister 57 of Multireg alert_cause
+ // R[alert_cause_57]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_57_we),
+ .wd (alert_cause_57_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[57].de),
+ .d (hw2reg.alert_cause[57].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_57_qs)
+ );
+
+
+ // Subregister 58 of Multireg alert_cause
+ // R[alert_cause_58]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_58_we),
+ .wd (alert_cause_58_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[58].de),
+ .d (hw2reg.alert_cause[58].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_58_qs)
+ );
+
+
+ // Subregister 59 of Multireg alert_cause
+ // R[alert_cause_59]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_59_we),
+ .wd (alert_cause_59_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[59].de),
+ .d (hw2reg.alert_cause[59].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_59_qs)
+ );
+
+
+ // Subregister 60 of Multireg alert_cause
+ // R[alert_cause_60]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_60_we),
+ .wd (alert_cause_60_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[60].de),
+ .d (hw2reg.alert_cause[60].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_60_qs)
+ );
+
+
+ // Subregister 61 of Multireg alert_cause
+ // R[alert_cause_61]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_61_we),
+ .wd (alert_cause_61_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[61].de),
+ .d (hw2reg.alert_cause[61].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_61_qs)
+ );
+
+
+ // Subregister 62 of Multireg alert_cause
+ // R[alert_cause_62]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_62_we),
+ .wd (alert_cause_62_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[62].de),
+ .d (hw2reg.alert_cause[62].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_62_qs)
+ );
+
+
+ // Subregister 63 of Multireg alert_cause
+ // R[alert_cause_63]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_63_we),
+ .wd (alert_cause_63_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[63].de),
+ .d (hw2reg.alert_cause[63].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_63_qs)
+ );
+
+
+ // Subregister 64 of Multireg alert_cause
+ // R[alert_cause_64]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_64_we),
+ .wd (alert_cause_64_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[64].de),
+ .d (hw2reg.alert_cause[64].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_64_qs)
+ );
+
+
+ // Subregister 65 of Multireg alert_cause
+ // R[alert_cause_65]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_65_we),
+ .wd (alert_cause_65_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[65].de),
+ .d (hw2reg.alert_cause[65].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_65_qs)
+ );
+
+
+ // Subregister 66 of Multireg alert_cause
+ // R[alert_cause_66]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_66_we),
+ .wd (alert_cause_66_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[66].de),
+ .d (hw2reg.alert_cause[66].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_66_qs)
+ );
+
+
+ // Subregister 67 of Multireg alert_cause
+ // R[alert_cause_67]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_67_we),
+ .wd (alert_cause_67_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[67].de),
+ .d (hw2reg.alert_cause[67].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_67_qs)
+ );
+
+
+ // Subregister 68 of Multireg alert_cause
+ // R[alert_cause_68]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_68_we),
+ .wd (alert_cause_68_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[68].de),
+ .d (hw2reg.alert_cause[68].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_68_qs)
+ );
+
+
+ // Subregister 69 of Multireg alert_cause
+ // R[alert_cause_69]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_69_we),
+ .wd (alert_cause_69_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[69].de),
+ .d (hw2reg.alert_cause[69].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_69_qs)
+ );
+
+
+ // Subregister 70 of Multireg alert_cause
+ // R[alert_cause_70]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_70_we),
+ .wd (alert_cause_70_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[70].de),
+ .d (hw2reg.alert_cause[70].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_70_qs)
+ );
+
+
+ // Subregister 71 of Multireg alert_cause
+ // R[alert_cause_71]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_71_we),
+ .wd (alert_cause_71_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[71].de),
+ .d (hw2reg.alert_cause[71].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_71_qs)
+ );
+
+
+ // Subregister 72 of Multireg alert_cause
+ // R[alert_cause_72]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_72_we),
+ .wd (alert_cause_72_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[72].de),
+ .d (hw2reg.alert_cause[72].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_72_qs)
+ );
+
+
+ // Subregister 73 of Multireg alert_cause
+ // R[alert_cause_73]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_73_we),
+ .wd (alert_cause_73_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[73].de),
+ .d (hw2reg.alert_cause[73].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_73_qs)
+ );
+
+
+ // Subregister 74 of Multireg alert_cause
+ // R[alert_cause_74]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_74_we),
+ .wd (alert_cause_74_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[74].de),
+ .d (hw2reg.alert_cause[74].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (alert_cause_74_qs)
+ );
+
+
+ // Subregister 0 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_0_we),
+ .wd (loc_alert_regwen_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_1_we),
+ .wd (loc_alert_regwen_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_2_we),
+ .wd (loc_alert_regwen_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_3_we),
+ .wd (loc_alert_regwen_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_4_we),
+ .wd (loc_alert_regwen_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_5_we),
+ .wd (loc_alert_regwen_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg loc_alert_regwen
+ // R[loc_alert_regwen_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_loc_alert_regwen_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_regwen_6_we),
+ .wd (loc_alert_regwen_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_regwen_6_qs)
+ );
+
+
+ // Subregister 0 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_0_gated_we;
+ assign loc_alert_en_shadowed_0_gated_we = loc_alert_en_shadowed_0_we & loc_alert_regwen_0_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_0_re),
+ .we (loc_alert_en_shadowed_0_gated_we),
+ .wd (loc_alert_en_shadowed_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_0_update_err),
+ .err_storage (loc_alert_en_shadowed_0_storage_err)
+ );
+
+
+ // Subregister 1 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_1_gated_we;
+ assign loc_alert_en_shadowed_1_gated_we = loc_alert_en_shadowed_1_we & loc_alert_regwen_1_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_1_re),
+ .we (loc_alert_en_shadowed_1_gated_we),
+ .wd (loc_alert_en_shadowed_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_1_update_err),
+ .err_storage (loc_alert_en_shadowed_1_storage_err)
+ );
+
+
+ // Subregister 2 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_2_gated_we;
+ assign loc_alert_en_shadowed_2_gated_we = loc_alert_en_shadowed_2_we & loc_alert_regwen_2_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_2_re),
+ .we (loc_alert_en_shadowed_2_gated_we),
+ .wd (loc_alert_en_shadowed_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_2_update_err),
+ .err_storage (loc_alert_en_shadowed_2_storage_err)
+ );
+
+
+ // Subregister 3 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_3_gated_we;
+ assign loc_alert_en_shadowed_3_gated_we = loc_alert_en_shadowed_3_we & loc_alert_regwen_3_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_3_re),
+ .we (loc_alert_en_shadowed_3_gated_we),
+ .wd (loc_alert_en_shadowed_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_3_update_err),
+ .err_storage (loc_alert_en_shadowed_3_storage_err)
+ );
+
+
+ // Subregister 4 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_4_gated_we;
+ assign loc_alert_en_shadowed_4_gated_we = loc_alert_en_shadowed_4_we & loc_alert_regwen_4_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_4_re),
+ .we (loc_alert_en_shadowed_4_gated_we),
+ .wd (loc_alert_en_shadowed_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_4_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_4_update_err),
+ .err_storage (loc_alert_en_shadowed_4_storage_err)
+ );
+
+
+ // Subregister 5 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_5_gated_we;
+ assign loc_alert_en_shadowed_5_gated_we = loc_alert_en_shadowed_5_we & loc_alert_regwen_5_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_5_re),
+ .we (loc_alert_en_shadowed_5_gated_we),
+ .wd (loc_alert_en_shadowed_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_5_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_5_update_err),
+ .err_storage (loc_alert_en_shadowed_5_storage_err)
+ );
+
+
+ // Subregister 6 of Multireg loc_alert_en_shadowed
+ // R[loc_alert_en_shadowed_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_en_shadowed_6_gated_we;
+ assign loc_alert_en_shadowed_6_gated_we = loc_alert_en_shadowed_6_we & loc_alert_regwen_6_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_shadowed_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_en_shadowed_6_re),
+ .we (loc_alert_en_shadowed_6_gated_we),
+ .wd (loc_alert_en_shadowed_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en_shadowed[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_en_shadowed_6_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_en_shadowed_6_update_err),
+ .err_storage (loc_alert_en_shadowed_6_storage_err)
+ );
+
+
+ // Subregister 0 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_0]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_0_gated_we;
+ assign loc_alert_class_shadowed_0_gated_we =
+ loc_alert_class_shadowed_0_we & loc_alert_regwen_0_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_0_re),
+ .we (loc_alert_class_shadowed_0_gated_we),
+ .wd (loc_alert_class_shadowed_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_0_update_err),
+ .err_storage (loc_alert_class_shadowed_0_storage_err)
+ );
+
+
+ // Subregister 1 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_1]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_1_gated_we;
+ assign loc_alert_class_shadowed_1_gated_we =
+ loc_alert_class_shadowed_1_we & loc_alert_regwen_1_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_1_re),
+ .we (loc_alert_class_shadowed_1_gated_we),
+ .wd (loc_alert_class_shadowed_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_1_update_err),
+ .err_storage (loc_alert_class_shadowed_1_storage_err)
+ );
+
+
+ // Subregister 2 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_2]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_2_gated_we;
+ assign loc_alert_class_shadowed_2_gated_we =
+ loc_alert_class_shadowed_2_we & loc_alert_regwen_2_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_2_re),
+ .we (loc_alert_class_shadowed_2_gated_we),
+ .wd (loc_alert_class_shadowed_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_2_update_err),
+ .err_storage (loc_alert_class_shadowed_2_storage_err)
+ );
+
+
+ // Subregister 3 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_3]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_3_gated_we;
+ assign loc_alert_class_shadowed_3_gated_we =
+ loc_alert_class_shadowed_3_we & loc_alert_regwen_3_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_3_re),
+ .we (loc_alert_class_shadowed_3_gated_we),
+ .wd (loc_alert_class_shadowed_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_3_update_err),
+ .err_storage (loc_alert_class_shadowed_3_storage_err)
+ );
+
+
+ // Subregister 4 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_4]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_4_gated_we;
+ assign loc_alert_class_shadowed_4_gated_we =
+ loc_alert_class_shadowed_4_we & loc_alert_regwen_4_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_4_re),
+ .we (loc_alert_class_shadowed_4_gated_we),
+ .wd (loc_alert_class_shadowed_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_4_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_4_update_err),
+ .err_storage (loc_alert_class_shadowed_4_storage_err)
+ );
+
+
+ // Subregister 5 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_5]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_5_gated_we;
+ assign loc_alert_class_shadowed_5_gated_we =
+ loc_alert_class_shadowed_5_we & loc_alert_regwen_5_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_5_re),
+ .we (loc_alert_class_shadowed_5_gated_we),
+ .wd (loc_alert_class_shadowed_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_5_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_5_update_err),
+ .err_storage (loc_alert_class_shadowed_5_storage_err)
+ );
+
+
+ // Subregister 6 of Multireg loc_alert_class_shadowed
+ // R[loc_alert_class_shadowed_6]: V(False)
+ // Create REGWEN-gated WE signal
+ logic loc_alert_class_shadowed_6_gated_we;
+ assign loc_alert_class_shadowed_6_gated_we =
+ loc_alert_class_shadowed_6_we & loc_alert_regwen_6_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_shadowed_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (loc_alert_class_shadowed_6_re),
+ .we (loc_alert_class_shadowed_6_gated_we),
+ .wd (loc_alert_class_shadowed_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class_shadowed[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_class_shadowed_6_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (loc_alert_class_shadowed_6_update_err),
+ .err_storage (loc_alert_class_shadowed_6_storage_err)
+ );
+
+
+ // Subregister 0 of Multireg loc_alert_cause
+ // R[loc_alert_cause_0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_0_we),
+ .wd (loc_alert_cause_0_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[0].de),
+ .d (hw2reg.loc_alert_cause[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_0_qs)
+ );
+
+
+ // Subregister 1 of Multireg loc_alert_cause
+ // R[loc_alert_cause_1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_1_we),
+ .wd (loc_alert_cause_1_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[1].de),
+ .d (hw2reg.loc_alert_cause[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_1_qs)
+ );
+
+
+ // Subregister 2 of Multireg loc_alert_cause
+ // R[loc_alert_cause_2]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_2_we),
+ .wd (loc_alert_cause_2_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[2].de),
+ .d (hw2reg.loc_alert_cause[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_2_qs)
+ );
+
+
+ // Subregister 3 of Multireg loc_alert_cause
+ // R[loc_alert_cause_3]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_3_we),
+ .wd (loc_alert_cause_3_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[3].de),
+ .d (hw2reg.loc_alert_cause[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_3_qs)
+ );
+
+
+ // Subregister 4 of Multireg loc_alert_cause
+ // R[loc_alert_cause_4]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_4_we),
+ .wd (loc_alert_cause_4_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[4].de),
+ .d (hw2reg.loc_alert_cause[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_4_qs)
+ );
+
+
+ // Subregister 5 of Multireg loc_alert_cause
+ // R[loc_alert_cause_5]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_5_we),
+ .wd (loc_alert_cause_5_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[5].de),
+ .d (hw2reg.loc_alert_cause[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_5_qs)
+ );
+
+
+ // Subregister 6 of Multireg loc_alert_cause
+ // R[loc_alert_cause_6]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (loc_alert_cause_6_we),
+ .wd (loc_alert_cause_6_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause[6].de),
+ .d (hw2reg.loc_alert_cause[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_6_qs)
+ );
+
+
+ // R[classa_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classa_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classa_regwen_we),
+ .wd (classa_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_regwen_qs)
+ );
+
+
+ // R[classa_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_ctrl_shadowed_gated_we;
+ assign classa_ctrl_shadowed_gated_we = classa_ctrl_shadowed_we & classa_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classa_ctrl_shadowed_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_en_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_en_update_err),
+ .err_storage (classa_ctrl_shadowed_en_storage_err)
+ );
+
+ // F[lock]: 1:1
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classa_ctrl_shadowed_lock (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.lock.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_lock_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_lock_update_err),
+ .err_storage (classa_ctrl_shadowed_lock_storage_err)
+ );
+
+ // F[en_e0]: 2:2
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_shadowed_en_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.en_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_en_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_en_e0_update_err),
+ .err_storage (classa_ctrl_shadowed_en_e0_storage_err)
+ );
+
+ // F[en_e1]: 3:3
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_shadowed_en_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.en_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_en_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_en_e1_update_err),
+ .err_storage (classa_ctrl_shadowed_en_e1_storage_err)
+ );
+
+ // F[en_e2]: 4:4
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_shadowed_en_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.en_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_en_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_en_e2_update_err),
+ .err_storage (classa_ctrl_shadowed_en_e2_storage_err)
+ );
+
+ // F[en_e3]: 5:5
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_shadowed_en_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.en_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_en_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_en_e3_update_err),
+ .err_storage (classa_ctrl_shadowed_en_e3_storage_err)
+ );
+
+ // F[map_e0]: 7:6
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classa_ctrl_shadowed_map_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.map_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_map_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_map_e0_update_err),
+ .err_storage (classa_ctrl_shadowed_map_e0_storage_err)
+ );
+
+ // F[map_e1]: 9:8
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h1)
+ ) u_classa_ctrl_shadowed_map_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.map_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_map_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_map_e1_update_err),
+ .err_storage (classa_ctrl_shadowed_map_e1_storage_err)
+ );
+
+ // F[map_e2]: 11:10
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_classa_ctrl_shadowed_map_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.map_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_map_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_map_e2_update_err),
+ .err_storage (classa_ctrl_shadowed_map_e2_storage_err)
+ );
+
+ // F[map_e3]: 13:12
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h3)
+ ) u_classa_ctrl_shadowed_map_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_ctrl_shadowed_re),
+ .we (classa_ctrl_shadowed_gated_we),
+ .wd (classa_ctrl_shadowed_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl_shadowed.map_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_ctrl_shadowed_map_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_ctrl_shadowed_map_e3_update_err),
+ .err_storage (classa_ctrl_shadowed_map_e3_storage_err)
+ );
+
+
+ // R[classa_clr_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classa_clr_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classa_clr_regwen_we),
+ .wd (classa_clr_regwen_wd),
+
+ // from internal hardware
+ .de (hw2reg.classa_clr_regwen.de),
+ .d (hw2reg.classa_clr_regwen.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_clr_regwen_qs)
+ );
+
+
+ // R[classa_clr_shadowed]: V(False)
+ logic classa_clr_shadowed_qe;
+ logic [0:0] classa_clr_shadowed_flds_we;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_classa_clr_shadowed0_qe (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .d_i(&classa_clr_shadowed_flds_we),
+ .q_o(classa_clr_shadowed_qe)
+ );
+ // Create REGWEN-gated WE signal
+ logic classa_clr_shadowed_gated_we;
+ assign classa_clr_shadowed_gated_we = classa_clr_shadowed_we & classa_clr_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classa_clr_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_clr_shadowed_re),
+ .we (classa_clr_shadowed_gated_we),
+ .wd (classa_clr_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (classa_clr_shadowed_flds_we[0]),
+ .q (reg2hw.classa_clr_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_clr_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_clr_shadowed_update_err),
+ .err_storage (classa_clr_shadowed_storage_err)
+ );
+ assign reg2hw.classa_clr_shadowed.qe = classa_clr_shadowed_qe;
+
+
+ // R[classa_accum_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classa_accum_cnt (
+ .re (classa_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classa_accum_cnt_qs)
+ );
+
+
+ // R[classa_accum_thresh_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_accum_thresh_shadowed_gated_we;
+ assign classa_accum_thresh_shadowed_gated_we = classa_accum_thresh_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (16),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (16'h0)
+ ) u_classa_accum_thresh_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_accum_thresh_shadowed_re),
+ .we (classa_accum_thresh_shadowed_gated_we),
+ .wd (classa_accum_thresh_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_accum_thresh_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_accum_thresh_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_accum_thresh_shadowed_update_err),
+ .err_storage (classa_accum_thresh_shadowed_storage_err)
+ );
+
+
+ // R[classa_timeout_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_timeout_cyc_shadowed_gated_we;
+ assign classa_timeout_cyc_shadowed_gated_we = classa_timeout_cyc_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classa_timeout_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_timeout_cyc_shadowed_re),
+ .we (classa_timeout_cyc_shadowed_gated_we),
+ .wd (classa_timeout_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_timeout_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_timeout_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_timeout_cyc_shadowed_update_err),
+ .err_storage (classa_timeout_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classa_crashdump_trigger_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_crashdump_trigger_shadowed_gated_we;
+ assign classa_crashdump_trigger_shadowed_gated_we =
+ classa_crashdump_trigger_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classa_crashdump_trigger_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_crashdump_trigger_shadowed_re),
+ .we (classa_crashdump_trigger_shadowed_gated_we),
+ .wd (classa_crashdump_trigger_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_crashdump_trigger_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_crashdump_trigger_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_crashdump_trigger_shadowed_update_err),
+ .err_storage (classa_crashdump_trigger_shadowed_storage_err)
+ );
+
+
+ // R[classa_phase0_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_phase0_cyc_shadowed_gated_we;
+ assign classa_phase0_cyc_shadowed_gated_we = classa_phase0_cyc_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classa_phase0_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_phase0_cyc_shadowed_re),
+ .we (classa_phase0_cyc_shadowed_gated_we),
+ .wd (classa_phase0_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase0_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_phase0_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_phase0_cyc_shadowed_update_err),
+ .err_storage (classa_phase0_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classa_phase1_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_phase1_cyc_shadowed_gated_we;
+ assign classa_phase1_cyc_shadowed_gated_we = classa_phase1_cyc_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classa_phase1_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_phase1_cyc_shadowed_re),
+ .we (classa_phase1_cyc_shadowed_gated_we),
+ .wd (classa_phase1_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase1_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_phase1_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_phase1_cyc_shadowed_update_err),
+ .err_storage (classa_phase1_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classa_phase2_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_phase2_cyc_shadowed_gated_we;
+ assign classa_phase2_cyc_shadowed_gated_we = classa_phase2_cyc_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classa_phase2_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_phase2_cyc_shadowed_re),
+ .we (classa_phase2_cyc_shadowed_gated_we),
+ .wd (classa_phase2_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase2_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_phase2_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_phase2_cyc_shadowed_update_err),
+ .err_storage (classa_phase2_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classa_phase3_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classa_phase3_cyc_shadowed_gated_we;
+ assign classa_phase3_cyc_shadowed_gated_we = classa_phase3_cyc_shadowed_we & classa_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classa_phase3_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classa_phase3_cyc_shadowed_re),
+ .we (classa_phase3_cyc_shadowed_gated_we),
+ .wd (classa_phase3_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase3_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classa_phase3_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classa_phase3_cyc_shadowed_update_err),
+ .err_storage (classa_phase3_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classa_esc_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classa_esc_cnt (
+ .re (classa_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classa_esc_cnt_qs)
+ );
+
+
+ // R[classa_state]: V(True)
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classa_state (
+ .re (classa_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classa_state_qs)
+ );
+
+
+ // R[classb_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classb_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classb_regwen_we),
+ .wd (classb_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_regwen_qs)
+ );
+
+
+ // R[classb_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_ctrl_shadowed_gated_we;
+ assign classb_ctrl_shadowed_gated_we = classb_ctrl_shadowed_we & classb_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classb_ctrl_shadowed_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_en_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_en_update_err),
+ .err_storage (classb_ctrl_shadowed_en_storage_err)
+ );
+
+ // F[lock]: 1:1
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classb_ctrl_shadowed_lock (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.lock.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_lock_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_lock_update_err),
+ .err_storage (classb_ctrl_shadowed_lock_storage_err)
+ );
+
+ // F[en_e0]: 2:2
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_shadowed_en_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.en_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_en_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_en_e0_update_err),
+ .err_storage (classb_ctrl_shadowed_en_e0_storage_err)
+ );
+
+ // F[en_e1]: 3:3
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_shadowed_en_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.en_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_en_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_en_e1_update_err),
+ .err_storage (classb_ctrl_shadowed_en_e1_storage_err)
+ );
+
+ // F[en_e2]: 4:4
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_shadowed_en_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.en_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_en_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_en_e2_update_err),
+ .err_storage (classb_ctrl_shadowed_en_e2_storage_err)
+ );
+
+ // F[en_e3]: 5:5
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_shadowed_en_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.en_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_en_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_en_e3_update_err),
+ .err_storage (classb_ctrl_shadowed_en_e3_storage_err)
+ );
+
+ // F[map_e0]: 7:6
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classb_ctrl_shadowed_map_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.map_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_map_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_map_e0_update_err),
+ .err_storage (classb_ctrl_shadowed_map_e0_storage_err)
+ );
+
+ // F[map_e1]: 9:8
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h1)
+ ) u_classb_ctrl_shadowed_map_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.map_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_map_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_map_e1_update_err),
+ .err_storage (classb_ctrl_shadowed_map_e1_storage_err)
+ );
+
+ // F[map_e2]: 11:10
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_classb_ctrl_shadowed_map_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.map_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_map_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_map_e2_update_err),
+ .err_storage (classb_ctrl_shadowed_map_e2_storage_err)
+ );
+
+ // F[map_e3]: 13:12
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h3)
+ ) u_classb_ctrl_shadowed_map_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_ctrl_shadowed_re),
+ .we (classb_ctrl_shadowed_gated_we),
+ .wd (classb_ctrl_shadowed_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl_shadowed.map_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_ctrl_shadowed_map_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_ctrl_shadowed_map_e3_update_err),
+ .err_storage (classb_ctrl_shadowed_map_e3_storage_err)
+ );
+
+
+ // R[classb_clr_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classb_clr_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classb_clr_regwen_we),
+ .wd (classb_clr_regwen_wd),
+
+ // from internal hardware
+ .de (hw2reg.classb_clr_regwen.de),
+ .d (hw2reg.classb_clr_regwen.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_clr_regwen_qs)
+ );
+
+
+ // R[classb_clr_shadowed]: V(False)
+ logic classb_clr_shadowed_qe;
+ logic [0:0] classb_clr_shadowed_flds_we;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_classb_clr_shadowed0_qe (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .d_i(&classb_clr_shadowed_flds_we),
+ .q_o(classb_clr_shadowed_qe)
+ );
+ // Create REGWEN-gated WE signal
+ logic classb_clr_shadowed_gated_we;
+ assign classb_clr_shadowed_gated_we = classb_clr_shadowed_we & classb_clr_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classb_clr_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_clr_shadowed_re),
+ .we (classb_clr_shadowed_gated_we),
+ .wd (classb_clr_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (classb_clr_shadowed_flds_we[0]),
+ .q (reg2hw.classb_clr_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_clr_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_clr_shadowed_update_err),
+ .err_storage (classb_clr_shadowed_storage_err)
+ );
+ assign reg2hw.classb_clr_shadowed.qe = classb_clr_shadowed_qe;
+
+
+ // R[classb_accum_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classb_accum_cnt (
+ .re (classb_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classb_accum_cnt_qs)
+ );
+
+
+ // R[classb_accum_thresh_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_accum_thresh_shadowed_gated_we;
+ assign classb_accum_thresh_shadowed_gated_we = classb_accum_thresh_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (16),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (16'h0)
+ ) u_classb_accum_thresh_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_accum_thresh_shadowed_re),
+ .we (classb_accum_thresh_shadowed_gated_we),
+ .wd (classb_accum_thresh_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_accum_thresh_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_accum_thresh_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_accum_thresh_shadowed_update_err),
+ .err_storage (classb_accum_thresh_shadowed_storage_err)
+ );
+
+
+ // R[classb_timeout_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_timeout_cyc_shadowed_gated_we;
+ assign classb_timeout_cyc_shadowed_gated_we = classb_timeout_cyc_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classb_timeout_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_timeout_cyc_shadowed_re),
+ .we (classb_timeout_cyc_shadowed_gated_we),
+ .wd (classb_timeout_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_timeout_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_timeout_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_timeout_cyc_shadowed_update_err),
+ .err_storage (classb_timeout_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classb_crashdump_trigger_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_crashdump_trigger_shadowed_gated_we;
+ assign classb_crashdump_trigger_shadowed_gated_we =
+ classb_crashdump_trigger_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classb_crashdump_trigger_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_crashdump_trigger_shadowed_re),
+ .we (classb_crashdump_trigger_shadowed_gated_we),
+ .wd (classb_crashdump_trigger_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_crashdump_trigger_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_crashdump_trigger_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_crashdump_trigger_shadowed_update_err),
+ .err_storage (classb_crashdump_trigger_shadowed_storage_err)
+ );
+
+
+ // R[classb_phase0_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_phase0_cyc_shadowed_gated_we;
+ assign classb_phase0_cyc_shadowed_gated_we = classb_phase0_cyc_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classb_phase0_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_phase0_cyc_shadowed_re),
+ .we (classb_phase0_cyc_shadowed_gated_we),
+ .wd (classb_phase0_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase0_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_phase0_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_phase0_cyc_shadowed_update_err),
+ .err_storage (classb_phase0_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classb_phase1_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_phase1_cyc_shadowed_gated_we;
+ assign classb_phase1_cyc_shadowed_gated_we = classb_phase1_cyc_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classb_phase1_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_phase1_cyc_shadowed_re),
+ .we (classb_phase1_cyc_shadowed_gated_we),
+ .wd (classb_phase1_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase1_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_phase1_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_phase1_cyc_shadowed_update_err),
+ .err_storage (classb_phase1_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classb_phase2_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_phase2_cyc_shadowed_gated_we;
+ assign classb_phase2_cyc_shadowed_gated_we = classb_phase2_cyc_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classb_phase2_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_phase2_cyc_shadowed_re),
+ .we (classb_phase2_cyc_shadowed_gated_we),
+ .wd (classb_phase2_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase2_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_phase2_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_phase2_cyc_shadowed_update_err),
+ .err_storage (classb_phase2_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classb_phase3_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classb_phase3_cyc_shadowed_gated_we;
+ assign classb_phase3_cyc_shadowed_gated_we = classb_phase3_cyc_shadowed_we & classb_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classb_phase3_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classb_phase3_cyc_shadowed_re),
+ .we (classb_phase3_cyc_shadowed_gated_we),
+ .wd (classb_phase3_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase3_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classb_phase3_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classb_phase3_cyc_shadowed_update_err),
+ .err_storage (classb_phase3_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classb_esc_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classb_esc_cnt (
+ .re (classb_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classb_esc_cnt_qs)
+ );
+
+
+ // R[classb_state]: V(True)
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classb_state (
+ .re (classb_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classb_state_qs)
+ );
+
+
+ // R[classc_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classc_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classc_regwen_we),
+ .wd (classc_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_regwen_qs)
+ );
+
+
+ // R[classc_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_ctrl_shadowed_gated_we;
+ assign classc_ctrl_shadowed_gated_we = classc_ctrl_shadowed_we & classc_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classc_ctrl_shadowed_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_en_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_en_update_err),
+ .err_storage (classc_ctrl_shadowed_en_storage_err)
+ );
+
+ // F[lock]: 1:1
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classc_ctrl_shadowed_lock (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.lock.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_lock_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_lock_update_err),
+ .err_storage (classc_ctrl_shadowed_lock_storage_err)
+ );
+
+ // F[en_e0]: 2:2
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_shadowed_en_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.en_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_en_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_en_e0_update_err),
+ .err_storage (classc_ctrl_shadowed_en_e0_storage_err)
+ );
+
+ // F[en_e1]: 3:3
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_shadowed_en_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.en_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_en_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_en_e1_update_err),
+ .err_storage (classc_ctrl_shadowed_en_e1_storage_err)
+ );
+
+ // F[en_e2]: 4:4
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_shadowed_en_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.en_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_en_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_en_e2_update_err),
+ .err_storage (classc_ctrl_shadowed_en_e2_storage_err)
+ );
+
+ // F[en_e3]: 5:5
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_shadowed_en_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.en_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_en_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_en_e3_update_err),
+ .err_storage (classc_ctrl_shadowed_en_e3_storage_err)
+ );
+
+ // F[map_e0]: 7:6
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classc_ctrl_shadowed_map_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.map_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_map_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_map_e0_update_err),
+ .err_storage (classc_ctrl_shadowed_map_e0_storage_err)
+ );
+
+ // F[map_e1]: 9:8
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h1)
+ ) u_classc_ctrl_shadowed_map_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.map_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_map_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_map_e1_update_err),
+ .err_storage (classc_ctrl_shadowed_map_e1_storage_err)
+ );
+
+ // F[map_e2]: 11:10
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_classc_ctrl_shadowed_map_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.map_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_map_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_map_e2_update_err),
+ .err_storage (classc_ctrl_shadowed_map_e2_storage_err)
+ );
+
+ // F[map_e3]: 13:12
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h3)
+ ) u_classc_ctrl_shadowed_map_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_ctrl_shadowed_re),
+ .we (classc_ctrl_shadowed_gated_we),
+ .wd (classc_ctrl_shadowed_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl_shadowed.map_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_ctrl_shadowed_map_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_ctrl_shadowed_map_e3_update_err),
+ .err_storage (classc_ctrl_shadowed_map_e3_storage_err)
+ );
+
+
+ // R[classc_clr_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classc_clr_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classc_clr_regwen_we),
+ .wd (classc_clr_regwen_wd),
+
+ // from internal hardware
+ .de (hw2reg.classc_clr_regwen.de),
+ .d (hw2reg.classc_clr_regwen.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_clr_regwen_qs)
+ );
+
+
+ // R[classc_clr_shadowed]: V(False)
+ logic classc_clr_shadowed_qe;
+ logic [0:0] classc_clr_shadowed_flds_we;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_classc_clr_shadowed0_qe (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .d_i(&classc_clr_shadowed_flds_we),
+ .q_o(classc_clr_shadowed_qe)
+ );
+ // Create REGWEN-gated WE signal
+ logic classc_clr_shadowed_gated_we;
+ assign classc_clr_shadowed_gated_we = classc_clr_shadowed_we & classc_clr_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classc_clr_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_clr_shadowed_re),
+ .we (classc_clr_shadowed_gated_we),
+ .wd (classc_clr_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (classc_clr_shadowed_flds_we[0]),
+ .q (reg2hw.classc_clr_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_clr_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_clr_shadowed_update_err),
+ .err_storage (classc_clr_shadowed_storage_err)
+ );
+ assign reg2hw.classc_clr_shadowed.qe = classc_clr_shadowed_qe;
+
+
+ // R[classc_accum_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classc_accum_cnt (
+ .re (classc_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classc_accum_cnt_qs)
+ );
+
+
+ // R[classc_accum_thresh_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_accum_thresh_shadowed_gated_we;
+ assign classc_accum_thresh_shadowed_gated_we = classc_accum_thresh_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (16),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (16'h0)
+ ) u_classc_accum_thresh_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_accum_thresh_shadowed_re),
+ .we (classc_accum_thresh_shadowed_gated_we),
+ .wd (classc_accum_thresh_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_accum_thresh_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_accum_thresh_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_accum_thresh_shadowed_update_err),
+ .err_storage (classc_accum_thresh_shadowed_storage_err)
+ );
+
+
+ // R[classc_timeout_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_timeout_cyc_shadowed_gated_we;
+ assign classc_timeout_cyc_shadowed_gated_we = classc_timeout_cyc_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classc_timeout_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_timeout_cyc_shadowed_re),
+ .we (classc_timeout_cyc_shadowed_gated_we),
+ .wd (classc_timeout_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_timeout_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_timeout_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_timeout_cyc_shadowed_update_err),
+ .err_storage (classc_timeout_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classc_crashdump_trigger_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_crashdump_trigger_shadowed_gated_we;
+ assign classc_crashdump_trigger_shadowed_gated_we =
+ classc_crashdump_trigger_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classc_crashdump_trigger_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_crashdump_trigger_shadowed_re),
+ .we (classc_crashdump_trigger_shadowed_gated_we),
+ .wd (classc_crashdump_trigger_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_crashdump_trigger_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_crashdump_trigger_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_crashdump_trigger_shadowed_update_err),
+ .err_storage (classc_crashdump_trigger_shadowed_storage_err)
+ );
+
+
+ // R[classc_phase0_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_phase0_cyc_shadowed_gated_we;
+ assign classc_phase0_cyc_shadowed_gated_we = classc_phase0_cyc_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classc_phase0_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_phase0_cyc_shadowed_re),
+ .we (classc_phase0_cyc_shadowed_gated_we),
+ .wd (classc_phase0_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase0_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_phase0_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_phase0_cyc_shadowed_update_err),
+ .err_storage (classc_phase0_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classc_phase1_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_phase1_cyc_shadowed_gated_we;
+ assign classc_phase1_cyc_shadowed_gated_we = classc_phase1_cyc_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classc_phase1_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_phase1_cyc_shadowed_re),
+ .we (classc_phase1_cyc_shadowed_gated_we),
+ .wd (classc_phase1_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase1_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_phase1_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_phase1_cyc_shadowed_update_err),
+ .err_storage (classc_phase1_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classc_phase2_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_phase2_cyc_shadowed_gated_we;
+ assign classc_phase2_cyc_shadowed_gated_we = classc_phase2_cyc_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classc_phase2_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_phase2_cyc_shadowed_re),
+ .we (classc_phase2_cyc_shadowed_gated_we),
+ .wd (classc_phase2_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase2_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_phase2_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_phase2_cyc_shadowed_update_err),
+ .err_storage (classc_phase2_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classc_phase3_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classc_phase3_cyc_shadowed_gated_we;
+ assign classc_phase3_cyc_shadowed_gated_we = classc_phase3_cyc_shadowed_we & classc_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classc_phase3_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classc_phase3_cyc_shadowed_re),
+ .we (classc_phase3_cyc_shadowed_gated_we),
+ .wd (classc_phase3_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase3_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classc_phase3_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classc_phase3_cyc_shadowed_update_err),
+ .err_storage (classc_phase3_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classc_esc_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classc_esc_cnt (
+ .re (classc_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classc_esc_cnt_qs)
+ );
+
+
+ // R[classc_state]: V(True)
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classc_state (
+ .re (classc_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classc_state_qs)
+ );
+
+
+ // R[classd_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classd_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classd_regwen_we),
+ .wd (classd_regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_regwen_qs)
+ );
+
+
+ // R[classd_ctrl_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_ctrl_shadowed_gated_we;
+ assign classd_ctrl_shadowed_gated_we = classd_ctrl_shadowed_we & classd_regwen_qs;
+ // F[en]: 0:0
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classd_ctrl_shadowed_en (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.en.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_en_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_en_update_err),
+ .err_storage (classd_ctrl_shadowed_en_storage_err)
+ );
+
+ // F[lock]: 1:1
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classd_ctrl_shadowed_lock (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.lock.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_lock_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_lock_update_err),
+ .err_storage (classd_ctrl_shadowed_lock_storage_err)
+ );
+
+ // F[en_e0]: 2:2
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_shadowed_en_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.en_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_en_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_en_e0_update_err),
+ .err_storage (classd_ctrl_shadowed_en_e0_storage_err)
+ );
+
+ // F[en_e1]: 3:3
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_shadowed_en_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.en_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_en_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_en_e1_update_err),
+ .err_storage (classd_ctrl_shadowed_en_e1_storage_err)
+ );
+
+ // F[en_e2]: 4:4
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_shadowed_en_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.en_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_en_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_en_e2_update_err),
+ .err_storage (classd_ctrl_shadowed_en_e2_storage_err)
+ );
+
+ // F[en_e3]: 5:5
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_shadowed_en_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.en_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_en_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_en_e3_update_err),
+ .err_storage (classd_ctrl_shadowed_en_e3_storage_err)
+ );
+
+ // F[map_e0]: 7:6
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classd_ctrl_shadowed_map_e0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.map_e0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_map_e0_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_map_e0_update_err),
+ .err_storage (classd_ctrl_shadowed_map_e0_storage_err)
+ );
+
+ // F[map_e1]: 9:8
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h1)
+ ) u_classd_ctrl_shadowed_map_e1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.map_e1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_map_e1_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_map_e1_update_err),
+ .err_storage (classd_ctrl_shadowed_map_e1_storage_err)
+ );
+
+ // F[map_e2]: 11:10
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h2)
+ ) u_classd_ctrl_shadowed_map_e2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.map_e2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_map_e2_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_map_e2_update_err),
+ .err_storage (classd_ctrl_shadowed_map_e2_storage_err)
+ );
+
+ // F[map_e3]: 13:12
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h3)
+ ) u_classd_ctrl_shadowed_map_e3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_ctrl_shadowed_re),
+ .we (classd_ctrl_shadowed_gated_we),
+ .wd (classd_ctrl_shadowed_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl_shadowed.map_e3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_ctrl_shadowed_map_e3_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_ctrl_shadowed_map_e3_update_err),
+ .err_storage (classd_ctrl_shadowed_map_e3_storage_err)
+ );
+
+
+ // R[classd_clr_regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_classd_clr_regwen (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (classd_clr_regwen_we),
+ .wd (classd_clr_regwen_wd),
+
+ // from internal hardware
+ .de (hw2reg.classd_clr_regwen.de),
+ .d (hw2reg.classd_clr_regwen.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_clr_regwen_qs)
+ );
+
+
+ // R[classd_clr_shadowed]: V(False)
+ logic classd_clr_shadowed_qe;
+ logic [0:0] classd_clr_shadowed_flds_we;
+ prim_flop #(
+ .Width(1),
+ .ResetValue(0)
+ ) u_classd_clr_shadowed0_qe (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .d_i(&classd_clr_shadowed_flds_we),
+ .q_o(classd_clr_shadowed_qe)
+ );
+ // Create REGWEN-gated WE signal
+ logic classd_clr_shadowed_gated_we;
+ assign classd_clr_shadowed_gated_we = classd_clr_shadowed_we & classd_clr_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_classd_clr_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_clr_shadowed_re),
+ .we (classd_clr_shadowed_gated_we),
+ .wd (classd_clr_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (classd_clr_shadowed_flds_we[0]),
+ .q (reg2hw.classd_clr_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_clr_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_clr_shadowed_update_err),
+ .err_storage (classd_clr_shadowed_storage_err)
+ );
+ assign reg2hw.classd_clr_shadowed.qe = classd_clr_shadowed_qe;
+
+
+ // R[classd_accum_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classd_accum_cnt (
+ .re (classd_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classd_accum_cnt_qs)
+ );
+
+
+ // R[classd_accum_thresh_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_accum_thresh_shadowed_gated_we;
+ assign classd_accum_thresh_shadowed_gated_we = classd_accum_thresh_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (16),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (16'h0)
+ ) u_classd_accum_thresh_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_accum_thresh_shadowed_re),
+ .we (classd_accum_thresh_shadowed_gated_we),
+ .wd (classd_accum_thresh_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_accum_thresh_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_accum_thresh_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_accum_thresh_shadowed_update_err),
+ .err_storage (classd_accum_thresh_shadowed_storage_err)
+ );
+
+
+ // R[classd_timeout_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_timeout_cyc_shadowed_gated_we;
+ assign classd_timeout_cyc_shadowed_gated_we = classd_timeout_cyc_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classd_timeout_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_timeout_cyc_shadowed_re),
+ .we (classd_timeout_cyc_shadowed_gated_we),
+ .wd (classd_timeout_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_timeout_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_timeout_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_timeout_cyc_shadowed_update_err),
+ .err_storage (classd_timeout_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classd_crashdump_trigger_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_crashdump_trigger_shadowed_gated_we;
+ assign classd_crashdump_trigger_shadowed_gated_we =
+ classd_crashdump_trigger_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_classd_crashdump_trigger_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_crashdump_trigger_shadowed_re),
+ .we (classd_crashdump_trigger_shadowed_gated_we),
+ .wd (classd_crashdump_trigger_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_crashdump_trigger_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_crashdump_trigger_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_crashdump_trigger_shadowed_update_err),
+ .err_storage (classd_crashdump_trigger_shadowed_storage_err)
+ );
+
+
+ // R[classd_phase0_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_phase0_cyc_shadowed_gated_we;
+ assign classd_phase0_cyc_shadowed_gated_we = classd_phase0_cyc_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classd_phase0_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_phase0_cyc_shadowed_re),
+ .we (classd_phase0_cyc_shadowed_gated_we),
+ .wd (classd_phase0_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase0_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_phase0_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_phase0_cyc_shadowed_update_err),
+ .err_storage (classd_phase0_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classd_phase1_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_phase1_cyc_shadowed_gated_we;
+ assign classd_phase1_cyc_shadowed_gated_we = classd_phase1_cyc_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classd_phase1_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_phase1_cyc_shadowed_re),
+ .we (classd_phase1_cyc_shadowed_gated_we),
+ .wd (classd_phase1_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase1_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_phase1_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_phase1_cyc_shadowed_update_err),
+ .err_storage (classd_phase1_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classd_phase2_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_phase2_cyc_shadowed_gated_we;
+ assign classd_phase2_cyc_shadowed_gated_we = classd_phase2_cyc_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classd_phase2_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_phase2_cyc_shadowed_re),
+ .we (classd_phase2_cyc_shadowed_gated_we),
+ .wd (classd_phase2_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase2_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_phase2_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_phase2_cyc_shadowed_update_err),
+ .err_storage (classd_phase2_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classd_phase3_cyc_shadowed]: V(False)
+ // Create REGWEN-gated WE signal
+ logic classd_phase3_cyc_shadowed_gated_we;
+ assign classd_phase3_cyc_shadowed_gated_we = classd_phase3_cyc_shadowed_we & classd_regwen_qs;
+ prim_subreg_shadow #(
+ .DW (32),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (32'h0)
+ ) u_classd_phase3_cyc_shadowed (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (classd_phase3_cyc_shadowed_re),
+ .we (classd_phase3_cyc_shadowed_gated_we),
+ .wd (classd_phase3_cyc_shadowed_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase3_cyc_shadowed.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (classd_phase3_cyc_shadowed_qs),
+
+ // Shadow register phase. Relevant for hwext only.
+ .phase (),
+
+ // Shadow register error conditions
+ .err_update (classd_phase3_cyc_shadowed_update_err),
+ .err_storage (classd_phase3_cyc_shadowed_storage_err)
+ );
+
+
+ // R[classd_esc_cnt]: V(True)
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classd_esc_cnt (
+ .re (classd_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classd_esc_cnt_qs)
+ );
+
+
+ // R[classd_state]: V(True)
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classd_state (
+ .re (classd_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .ds (),
+ .qs (classd_state_qs)
+ );
+
+
+
+ logic [389:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET);
+ addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[ 5] = (reg_addr == ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET);
+ addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_0_OFFSET);
+ addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_1_OFFSET);
+ addr_hit[ 8] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_2_OFFSET);
+ addr_hit[ 9] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_3_OFFSET);
+ addr_hit[ 10] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_4_OFFSET);
+ addr_hit[ 11] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_5_OFFSET);
+ addr_hit[ 12] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_6_OFFSET);
+ addr_hit[ 13] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_7_OFFSET);
+ addr_hit[ 14] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_8_OFFSET);
+ addr_hit[ 15] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_9_OFFSET);
+ addr_hit[ 16] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_10_OFFSET);
+ addr_hit[ 17] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_11_OFFSET);
+ addr_hit[ 18] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_12_OFFSET);
+ addr_hit[ 19] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_13_OFFSET);
+ addr_hit[ 20] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_14_OFFSET);
+ addr_hit[ 21] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_15_OFFSET);
+ addr_hit[ 22] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_16_OFFSET);
+ addr_hit[ 23] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_17_OFFSET);
+ addr_hit[ 24] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_18_OFFSET);
+ addr_hit[ 25] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_19_OFFSET);
+ addr_hit[ 26] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_20_OFFSET);
+ addr_hit[ 27] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_21_OFFSET);
+ addr_hit[ 28] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_22_OFFSET);
+ addr_hit[ 29] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_23_OFFSET);
+ addr_hit[ 30] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_24_OFFSET);
+ addr_hit[ 31] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_25_OFFSET);
+ addr_hit[ 32] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_26_OFFSET);
+ addr_hit[ 33] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_27_OFFSET);
+ addr_hit[ 34] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_28_OFFSET);
+ addr_hit[ 35] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_29_OFFSET);
+ addr_hit[ 36] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_30_OFFSET);
+ addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_31_OFFSET);
+ addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_32_OFFSET);
+ addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_33_OFFSET);
+ addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET);
+ addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_35_OFFSET);
+ addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_36_OFFSET);
+ addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET);
+ addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET);
+ addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_39_OFFSET);
+ addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET);
+ addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET);
+ addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET);
+ addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET);
+ addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_44_OFFSET);
+ addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET);
+ addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET);
+ addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET);
+ addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_48_OFFSET);
+ addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_49_OFFSET);
+ addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_50_OFFSET);
+ addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_51_OFFSET);
+ addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_52_OFFSET);
+ addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_53_OFFSET);
+ addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_54_OFFSET);
+ addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET);
+ addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET);
+ addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET);
+ addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET);
+ addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_68_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_69_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_70_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_71_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_72_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_73_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_74_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+ addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+ addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+ addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+ addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+ addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+ addr_hit[278] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+ addr_hit[279] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+ addr_hit[280] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+ addr_hit[281] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+ addr_hit[282] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
+ addr_hit[283] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
+ addr_hit[284] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
+ addr_hit[285] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
+ addr_hit[286] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
+ addr_hit[287] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
+ addr_hit[288] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
+ addr_hit[289] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
+ addr_hit[290] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
+ addr_hit[291] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET);
+ addr_hit[292] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET);
+ addr_hit[293] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET);
+ addr_hit[294] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET);
+ addr_hit[295] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET);
+ addr_hit[296] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET);
+ addr_hit[297] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET);
+ addr_hit[298] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET);
+ addr_hit[299] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_68_OFFSET);
+ addr_hit[300] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_69_OFFSET);
+ addr_hit[301] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_70_OFFSET);
+ addr_hit[302] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_71_OFFSET);
+ addr_hit[303] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_72_OFFSET);
+ addr_hit[304] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_73_OFFSET);
+ addr_hit[305] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_74_OFFSET);
+ addr_hit[306] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[307] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[308] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[309] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[310] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[311] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+ addr_hit[312] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+ addr_hit[313] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[314] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[315] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[316] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[317] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[318] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[319] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[320] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[321] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[322] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[323] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[324] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[325] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[326] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[327] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[328] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[329] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[330] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[331] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[332] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
+ addr_hit[333] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
+ addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
+ addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
+ addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
+ addr_hit[350] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[351] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
+ addr_hit[352] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[353] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[354] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[355] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[356] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[357] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[358] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[359] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[360] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[361] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[362] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[363] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
+ addr_hit[364] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[365] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
+ addr_hit[366] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[367] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[368] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[369] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[370] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[371] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[372] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[373] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[374] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[375] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[376] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[377] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
+ addr_hit[378] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[379] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
+ addr_hit[380] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[381] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[382] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[383] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[384] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[385] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[386] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[387] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[388] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[389] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(ALERT_HANDLER_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(ALERT_HANDLER_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(ALERT_HANDLER_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(ALERT_HANDLER_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(ALERT_HANDLER_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(ALERT_HANDLER_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(ALERT_HANDLER_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(ALERT_HANDLER_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(ALERT_HANDLER_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(ALERT_HANDLER_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[ 10] & (|(ALERT_HANDLER_PERMIT[ 10] & ~reg_be))) |
+ (addr_hit[ 11] & (|(ALERT_HANDLER_PERMIT[ 11] & ~reg_be))) |
+ (addr_hit[ 12] & (|(ALERT_HANDLER_PERMIT[ 12] & ~reg_be))) |
+ (addr_hit[ 13] & (|(ALERT_HANDLER_PERMIT[ 13] & ~reg_be))) |
+ (addr_hit[ 14] & (|(ALERT_HANDLER_PERMIT[ 14] & ~reg_be))) |
+ (addr_hit[ 15] & (|(ALERT_HANDLER_PERMIT[ 15] & ~reg_be))) |
+ (addr_hit[ 16] & (|(ALERT_HANDLER_PERMIT[ 16] & ~reg_be))) |
+ (addr_hit[ 17] & (|(ALERT_HANDLER_PERMIT[ 17] & ~reg_be))) |
+ (addr_hit[ 18] & (|(ALERT_HANDLER_PERMIT[ 18] & ~reg_be))) |
+ (addr_hit[ 19] & (|(ALERT_HANDLER_PERMIT[ 19] & ~reg_be))) |
+ (addr_hit[ 20] & (|(ALERT_HANDLER_PERMIT[ 20] & ~reg_be))) |
+ (addr_hit[ 21] & (|(ALERT_HANDLER_PERMIT[ 21] & ~reg_be))) |
+ (addr_hit[ 22] & (|(ALERT_HANDLER_PERMIT[ 22] & ~reg_be))) |
+ (addr_hit[ 23] & (|(ALERT_HANDLER_PERMIT[ 23] & ~reg_be))) |
+ (addr_hit[ 24] & (|(ALERT_HANDLER_PERMIT[ 24] & ~reg_be))) |
+ (addr_hit[ 25] & (|(ALERT_HANDLER_PERMIT[ 25] & ~reg_be))) |
+ (addr_hit[ 26] & (|(ALERT_HANDLER_PERMIT[ 26] & ~reg_be))) |
+ (addr_hit[ 27] & (|(ALERT_HANDLER_PERMIT[ 27] & ~reg_be))) |
+ (addr_hit[ 28] & (|(ALERT_HANDLER_PERMIT[ 28] & ~reg_be))) |
+ (addr_hit[ 29] & (|(ALERT_HANDLER_PERMIT[ 29] & ~reg_be))) |
+ (addr_hit[ 30] & (|(ALERT_HANDLER_PERMIT[ 30] & ~reg_be))) |
+ (addr_hit[ 31] & (|(ALERT_HANDLER_PERMIT[ 31] & ~reg_be))) |
+ (addr_hit[ 32] & (|(ALERT_HANDLER_PERMIT[ 32] & ~reg_be))) |
+ (addr_hit[ 33] & (|(ALERT_HANDLER_PERMIT[ 33] & ~reg_be))) |
+ (addr_hit[ 34] & (|(ALERT_HANDLER_PERMIT[ 34] & ~reg_be))) |
+ (addr_hit[ 35] & (|(ALERT_HANDLER_PERMIT[ 35] & ~reg_be))) |
+ (addr_hit[ 36] & (|(ALERT_HANDLER_PERMIT[ 36] & ~reg_be))) |
+ (addr_hit[ 37] & (|(ALERT_HANDLER_PERMIT[ 37] & ~reg_be))) |
+ (addr_hit[ 38] & (|(ALERT_HANDLER_PERMIT[ 38] & ~reg_be))) |
+ (addr_hit[ 39] & (|(ALERT_HANDLER_PERMIT[ 39] & ~reg_be))) |
+ (addr_hit[ 40] & (|(ALERT_HANDLER_PERMIT[ 40] & ~reg_be))) |
+ (addr_hit[ 41] & (|(ALERT_HANDLER_PERMIT[ 41] & ~reg_be))) |
+ (addr_hit[ 42] & (|(ALERT_HANDLER_PERMIT[ 42] & ~reg_be))) |
+ (addr_hit[ 43] & (|(ALERT_HANDLER_PERMIT[ 43] & ~reg_be))) |
+ (addr_hit[ 44] & (|(ALERT_HANDLER_PERMIT[ 44] & ~reg_be))) |
+ (addr_hit[ 45] & (|(ALERT_HANDLER_PERMIT[ 45] & ~reg_be))) |
+ (addr_hit[ 46] & (|(ALERT_HANDLER_PERMIT[ 46] & ~reg_be))) |
+ (addr_hit[ 47] & (|(ALERT_HANDLER_PERMIT[ 47] & ~reg_be))) |
+ (addr_hit[ 48] & (|(ALERT_HANDLER_PERMIT[ 48] & ~reg_be))) |
+ (addr_hit[ 49] & (|(ALERT_HANDLER_PERMIT[ 49] & ~reg_be))) |
+ (addr_hit[ 50] & (|(ALERT_HANDLER_PERMIT[ 50] & ~reg_be))) |
+ (addr_hit[ 51] & (|(ALERT_HANDLER_PERMIT[ 51] & ~reg_be))) |
+ (addr_hit[ 52] & (|(ALERT_HANDLER_PERMIT[ 52] & ~reg_be))) |
+ (addr_hit[ 53] & (|(ALERT_HANDLER_PERMIT[ 53] & ~reg_be))) |
+ (addr_hit[ 54] & (|(ALERT_HANDLER_PERMIT[ 54] & ~reg_be))) |
+ (addr_hit[ 55] & (|(ALERT_HANDLER_PERMIT[ 55] & ~reg_be))) |
+ (addr_hit[ 56] & (|(ALERT_HANDLER_PERMIT[ 56] & ~reg_be))) |
+ (addr_hit[ 57] & (|(ALERT_HANDLER_PERMIT[ 57] & ~reg_be))) |
+ (addr_hit[ 58] & (|(ALERT_HANDLER_PERMIT[ 58] & ~reg_be))) |
+ (addr_hit[ 59] & (|(ALERT_HANDLER_PERMIT[ 59] & ~reg_be))) |
+ (addr_hit[ 60] & (|(ALERT_HANDLER_PERMIT[ 60] & ~reg_be))) |
+ (addr_hit[ 61] & (|(ALERT_HANDLER_PERMIT[ 61] & ~reg_be))) |
+ (addr_hit[ 62] & (|(ALERT_HANDLER_PERMIT[ 62] & ~reg_be))) |
+ (addr_hit[ 63] & (|(ALERT_HANDLER_PERMIT[ 63] & ~reg_be))) |
+ (addr_hit[ 64] & (|(ALERT_HANDLER_PERMIT[ 64] & ~reg_be))) |
+ (addr_hit[ 65] & (|(ALERT_HANDLER_PERMIT[ 65] & ~reg_be))) |
+ (addr_hit[ 66] & (|(ALERT_HANDLER_PERMIT[ 66] & ~reg_be))) |
+ (addr_hit[ 67] & (|(ALERT_HANDLER_PERMIT[ 67] & ~reg_be))) |
+ (addr_hit[ 68] & (|(ALERT_HANDLER_PERMIT[ 68] & ~reg_be))) |
+ (addr_hit[ 69] & (|(ALERT_HANDLER_PERMIT[ 69] & ~reg_be))) |
+ (addr_hit[ 70] & (|(ALERT_HANDLER_PERMIT[ 70] & ~reg_be))) |
+ (addr_hit[ 71] & (|(ALERT_HANDLER_PERMIT[ 71] & ~reg_be))) |
+ (addr_hit[ 72] & (|(ALERT_HANDLER_PERMIT[ 72] & ~reg_be))) |
+ (addr_hit[ 73] & (|(ALERT_HANDLER_PERMIT[ 73] & ~reg_be))) |
+ (addr_hit[ 74] & (|(ALERT_HANDLER_PERMIT[ 74] & ~reg_be))) |
+ (addr_hit[ 75] & (|(ALERT_HANDLER_PERMIT[ 75] & ~reg_be))) |
+ (addr_hit[ 76] & (|(ALERT_HANDLER_PERMIT[ 76] & ~reg_be))) |
+ (addr_hit[ 77] & (|(ALERT_HANDLER_PERMIT[ 77] & ~reg_be))) |
+ (addr_hit[ 78] & (|(ALERT_HANDLER_PERMIT[ 78] & ~reg_be))) |
+ (addr_hit[ 79] & (|(ALERT_HANDLER_PERMIT[ 79] & ~reg_be))) |
+ (addr_hit[ 80] & (|(ALERT_HANDLER_PERMIT[ 80] & ~reg_be))) |
+ (addr_hit[ 81] & (|(ALERT_HANDLER_PERMIT[ 81] & ~reg_be))) |
+ (addr_hit[ 82] & (|(ALERT_HANDLER_PERMIT[ 82] & ~reg_be))) |
+ (addr_hit[ 83] & (|(ALERT_HANDLER_PERMIT[ 83] & ~reg_be))) |
+ (addr_hit[ 84] & (|(ALERT_HANDLER_PERMIT[ 84] & ~reg_be))) |
+ (addr_hit[ 85] & (|(ALERT_HANDLER_PERMIT[ 85] & ~reg_be))) |
+ (addr_hit[ 86] & (|(ALERT_HANDLER_PERMIT[ 86] & ~reg_be))) |
+ (addr_hit[ 87] & (|(ALERT_HANDLER_PERMIT[ 87] & ~reg_be))) |
+ (addr_hit[ 88] & (|(ALERT_HANDLER_PERMIT[ 88] & ~reg_be))) |
+ (addr_hit[ 89] & (|(ALERT_HANDLER_PERMIT[ 89] & ~reg_be))) |
+ (addr_hit[ 90] & (|(ALERT_HANDLER_PERMIT[ 90] & ~reg_be))) |
+ (addr_hit[ 91] & (|(ALERT_HANDLER_PERMIT[ 91] & ~reg_be))) |
+ (addr_hit[ 92] & (|(ALERT_HANDLER_PERMIT[ 92] & ~reg_be))) |
+ (addr_hit[ 93] & (|(ALERT_HANDLER_PERMIT[ 93] & ~reg_be))) |
+ (addr_hit[ 94] & (|(ALERT_HANDLER_PERMIT[ 94] & ~reg_be))) |
+ (addr_hit[ 95] & (|(ALERT_HANDLER_PERMIT[ 95] & ~reg_be))) |
+ (addr_hit[ 96] & (|(ALERT_HANDLER_PERMIT[ 96] & ~reg_be))) |
+ (addr_hit[ 97] & (|(ALERT_HANDLER_PERMIT[ 97] & ~reg_be))) |
+ (addr_hit[ 98] & (|(ALERT_HANDLER_PERMIT[ 98] & ~reg_be))) |
+ (addr_hit[ 99] & (|(ALERT_HANDLER_PERMIT[ 99] & ~reg_be))) |
+ (addr_hit[100] & (|(ALERT_HANDLER_PERMIT[100] & ~reg_be))) |
+ (addr_hit[101] & (|(ALERT_HANDLER_PERMIT[101] & ~reg_be))) |
+ (addr_hit[102] & (|(ALERT_HANDLER_PERMIT[102] & ~reg_be))) |
+ (addr_hit[103] & (|(ALERT_HANDLER_PERMIT[103] & ~reg_be))) |
+ (addr_hit[104] & (|(ALERT_HANDLER_PERMIT[104] & ~reg_be))) |
+ (addr_hit[105] & (|(ALERT_HANDLER_PERMIT[105] & ~reg_be))) |
+ (addr_hit[106] & (|(ALERT_HANDLER_PERMIT[106] & ~reg_be))) |
+ (addr_hit[107] & (|(ALERT_HANDLER_PERMIT[107] & ~reg_be))) |
+ (addr_hit[108] & (|(ALERT_HANDLER_PERMIT[108] & ~reg_be))) |
+ (addr_hit[109] & (|(ALERT_HANDLER_PERMIT[109] & ~reg_be))) |
+ (addr_hit[110] & (|(ALERT_HANDLER_PERMIT[110] & ~reg_be))) |
+ (addr_hit[111] & (|(ALERT_HANDLER_PERMIT[111] & ~reg_be))) |
+ (addr_hit[112] & (|(ALERT_HANDLER_PERMIT[112] & ~reg_be))) |
+ (addr_hit[113] & (|(ALERT_HANDLER_PERMIT[113] & ~reg_be))) |
+ (addr_hit[114] & (|(ALERT_HANDLER_PERMIT[114] & ~reg_be))) |
+ (addr_hit[115] & (|(ALERT_HANDLER_PERMIT[115] & ~reg_be))) |
+ (addr_hit[116] & (|(ALERT_HANDLER_PERMIT[116] & ~reg_be))) |
+ (addr_hit[117] & (|(ALERT_HANDLER_PERMIT[117] & ~reg_be))) |
+ (addr_hit[118] & (|(ALERT_HANDLER_PERMIT[118] & ~reg_be))) |
+ (addr_hit[119] & (|(ALERT_HANDLER_PERMIT[119] & ~reg_be))) |
+ (addr_hit[120] & (|(ALERT_HANDLER_PERMIT[120] & ~reg_be))) |
+ (addr_hit[121] & (|(ALERT_HANDLER_PERMIT[121] & ~reg_be))) |
+ (addr_hit[122] & (|(ALERT_HANDLER_PERMIT[122] & ~reg_be))) |
+ (addr_hit[123] & (|(ALERT_HANDLER_PERMIT[123] & ~reg_be))) |
+ (addr_hit[124] & (|(ALERT_HANDLER_PERMIT[124] & ~reg_be))) |
+ (addr_hit[125] & (|(ALERT_HANDLER_PERMIT[125] & ~reg_be))) |
+ (addr_hit[126] & (|(ALERT_HANDLER_PERMIT[126] & ~reg_be))) |
+ (addr_hit[127] & (|(ALERT_HANDLER_PERMIT[127] & ~reg_be))) |
+ (addr_hit[128] & (|(ALERT_HANDLER_PERMIT[128] & ~reg_be))) |
+ (addr_hit[129] & (|(ALERT_HANDLER_PERMIT[129] & ~reg_be))) |
+ (addr_hit[130] & (|(ALERT_HANDLER_PERMIT[130] & ~reg_be))) |
+ (addr_hit[131] & (|(ALERT_HANDLER_PERMIT[131] & ~reg_be))) |
+ (addr_hit[132] & (|(ALERT_HANDLER_PERMIT[132] & ~reg_be))) |
+ (addr_hit[133] & (|(ALERT_HANDLER_PERMIT[133] & ~reg_be))) |
+ (addr_hit[134] & (|(ALERT_HANDLER_PERMIT[134] & ~reg_be))) |
+ (addr_hit[135] & (|(ALERT_HANDLER_PERMIT[135] & ~reg_be))) |
+ (addr_hit[136] & (|(ALERT_HANDLER_PERMIT[136] & ~reg_be))) |
+ (addr_hit[137] & (|(ALERT_HANDLER_PERMIT[137] & ~reg_be))) |
+ (addr_hit[138] & (|(ALERT_HANDLER_PERMIT[138] & ~reg_be))) |
+ (addr_hit[139] & (|(ALERT_HANDLER_PERMIT[139] & ~reg_be))) |
+ (addr_hit[140] & (|(ALERT_HANDLER_PERMIT[140] & ~reg_be))) |
+ (addr_hit[141] & (|(ALERT_HANDLER_PERMIT[141] & ~reg_be))) |
+ (addr_hit[142] & (|(ALERT_HANDLER_PERMIT[142] & ~reg_be))) |
+ (addr_hit[143] & (|(ALERT_HANDLER_PERMIT[143] & ~reg_be))) |
+ (addr_hit[144] & (|(ALERT_HANDLER_PERMIT[144] & ~reg_be))) |
+ (addr_hit[145] & (|(ALERT_HANDLER_PERMIT[145] & ~reg_be))) |
+ (addr_hit[146] & (|(ALERT_HANDLER_PERMIT[146] & ~reg_be))) |
+ (addr_hit[147] & (|(ALERT_HANDLER_PERMIT[147] & ~reg_be))) |
+ (addr_hit[148] & (|(ALERT_HANDLER_PERMIT[148] & ~reg_be))) |
+ (addr_hit[149] & (|(ALERT_HANDLER_PERMIT[149] & ~reg_be))) |
+ (addr_hit[150] & (|(ALERT_HANDLER_PERMIT[150] & ~reg_be))) |
+ (addr_hit[151] & (|(ALERT_HANDLER_PERMIT[151] & ~reg_be))) |
+ (addr_hit[152] & (|(ALERT_HANDLER_PERMIT[152] & ~reg_be))) |
+ (addr_hit[153] & (|(ALERT_HANDLER_PERMIT[153] & ~reg_be))) |
+ (addr_hit[154] & (|(ALERT_HANDLER_PERMIT[154] & ~reg_be))) |
+ (addr_hit[155] & (|(ALERT_HANDLER_PERMIT[155] & ~reg_be))) |
+ (addr_hit[156] & (|(ALERT_HANDLER_PERMIT[156] & ~reg_be))) |
+ (addr_hit[157] & (|(ALERT_HANDLER_PERMIT[157] & ~reg_be))) |
+ (addr_hit[158] & (|(ALERT_HANDLER_PERMIT[158] & ~reg_be))) |
+ (addr_hit[159] & (|(ALERT_HANDLER_PERMIT[159] & ~reg_be))) |
+ (addr_hit[160] & (|(ALERT_HANDLER_PERMIT[160] & ~reg_be))) |
+ (addr_hit[161] & (|(ALERT_HANDLER_PERMIT[161] & ~reg_be))) |
+ (addr_hit[162] & (|(ALERT_HANDLER_PERMIT[162] & ~reg_be))) |
+ (addr_hit[163] & (|(ALERT_HANDLER_PERMIT[163] & ~reg_be))) |
+ (addr_hit[164] & (|(ALERT_HANDLER_PERMIT[164] & ~reg_be))) |
+ (addr_hit[165] & (|(ALERT_HANDLER_PERMIT[165] & ~reg_be))) |
+ (addr_hit[166] & (|(ALERT_HANDLER_PERMIT[166] & ~reg_be))) |
+ (addr_hit[167] & (|(ALERT_HANDLER_PERMIT[167] & ~reg_be))) |
+ (addr_hit[168] & (|(ALERT_HANDLER_PERMIT[168] & ~reg_be))) |
+ (addr_hit[169] & (|(ALERT_HANDLER_PERMIT[169] & ~reg_be))) |
+ (addr_hit[170] & (|(ALERT_HANDLER_PERMIT[170] & ~reg_be))) |
+ (addr_hit[171] & (|(ALERT_HANDLER_PERMIT[171] & ~reg_be))) |
+ (addr_hit[172] & (|(ALERT_HANDLER_PERMIT[172] & ~reg_be))) |
+ (addr_hit[173] & (|(ALERT_HANDLER_PERMIT[173] & ~reg_be))) |
+ (addr_hit[174] & (|(ALERT_HANDLER_PERMIT[174] & ~reg_be))) |
+ (addr_hit[175] & (|(ALERT_HANDLER_PERMIT[175] & ~reg_be))) |
+ (addr_hit[176] & (|(ALERT_HANDLER_PERMIT[176] & ~reg_be))) |
+ (addr_hit[177] & (|(ALERT_HANDLER_PERMIT[177] & ~reg_be))) |
+ (addr_hit[178] & (|(ALERT_HANDLER_PERMIT[178] & ~reg_be))) |
+ (addr_hit[179] & (|(ALERT_HANDLER_PERMIT[179] & ~reg_be))) |
+ (addr_hit[180] & (|(ALERT_HANDLER_PERMIT[180] & ~reg_be))) |
+ (addr_hit[181] & (|(ALERT_HANDLER_PERMIT[181] & ~reg_be))) |
+ (addr_hit[182] & (|(ALERT_HANDLER_PERMIT[182] & ~reg_be))) |
+ (addr_hit[183] & (|(ALERT_HANDLER_PERMIT[183] & ~reg_be))) |
+ (addr_hit[184] & (|(ALERT_HANDLER_PERMIT[184] & ~reg_be))) |
+ (addr_hit[185] & (|(ALERT_HANDLER_PERMIT[185] & ~reg_be))) |
+ (addr_hit[186] & (|(ALERT_HANDLER_PERMIT[186] & ~reg_be))) |
+ (addr_hit[187] & (|(ALERT_HANDLER_PERMIT[187] & ~reg_be))) |
+ (addr_hit[188] & (|(ALERT_HANDLER_PERMIT[188] & ~reg_be))) |
+ (addr_hit[189] & (|(ALERT_HANDLER_PERMIT[189] & ~reg_be))) |
+ (addr_hit[190] & (|(ALERT_HANDLER_PERMIT[190] & ~reg_be))) |
+ (addr_hit[191] & (|(ALERT_HANDLER_PERMIT[191] & ~reg_be))) |
+ (addr_hit[192] & (|(ALERT_HANDLER_PERMIT[192] & ~reg_be))) |
+ (addr_hit[193] & (|(ALERT_HANDLER_PERMIT[193] & ~reg_be))) |
+ (addr_hit[194] & (|(ALERT_HANDLER_PERMIT[194] & ~reg_be))) |
+ (addr_hit[195] & (|(ALERT_HANDLER_PERMIT[195] & ~reg_be))) |
+ (addr_hit[196] & (|(ALERT_HANDLER_PERMIT[196] & ~reg_be))) |
+ (addr_hit[197] & (|(ALERT_HANDLER_PERMIT[197] & ~reg_be))) |
+ (addr_hit[198] & (|(ALERT_HANDLER_PERMIT[198] & ~reg_be))) |
+ (addr_hit[199] & (|(ALERT_HANDLER_PERMIT[199] & ~reg_be))) |
+ (addr_hit[200] & (|(ALERT_HANDLER_PERMIT[200] & ~reg_be))) |
+ (addr_hit[201] & (|(ALERT_HANDLER_PERMIT[201] & ~reg_be))) |
+ (addr_hit[202] & (|(ALERT_HANDLER_PERMIT[202] & ~reg_be))) |
+ (addr_hit[203] & (|(ALERT_HANDLER_PERMIT[203] & ~reg_be))) |
+ (addr_hit[204] & (|(ALERT_HANDLER_PERMIT[204] & ~reg_be))) |
+ (addr_hit[205] & (|(ALERT_HANDLER_PERMIT[205] & ~reg_be))) |
+ (addr_hit[206] & (|(ALERT_HANDLER_PERMIT[206] & ~reg_be))) |
+ (addr_hit[207] & (|(ALERT_HANDLER_PERMIT[207] & ~reg_be))) |
+ (addr_hit[208] & (|(ALERT_HANDLER_PERMIT[208] & ~reg_be))) |
+ (addr_hit[209] & (|(ALERT_HANDLER_PERMIT[209] & ~reg_be))) |
+ (addr_hit[210] & (|(ALERT_HANDLER_PERMIT[210] & ~reg_be))) |
+ (addr_hit[211] & (|(ALERT_HANDLER_PERMIT[211] & ~reg_be))) |
+ (addr_hit[212] & (|(ALERT_HANDLER_PERMIT[212] & ~reg_be))) |
+ (addr_hit[213] & (|(ALERT_HANDLER_PERMIT[213] & ~reg_be))) |
+ (addr_hit[214] & (|(ALERT_HANDLER_PERMIT[214] & ~reg_be))) |
+ (addr_hit[215] & (|(ALERT_HANDLER_PERMIT[215] & ~reg_be))) |
+ (addr_hit[216] & (|(ALERT_HANDLER_PERMIT[216] & ~reg_be))) |
+ (addr_hit[217] & (|(ALERT_HANDLER_PERMIT[217] & ~reg_be))) |
+ (addr_hit[218] & (|(ALERT_HANDLER_PERMIT[218] & ~reg_be))) |
+ (addr_hit[219] & (|(ALERT_HANDLER_PERMIT[219] & ~reg_be))) |
+ (addr_hit[220] & (|(ALERT_HANDLER_PERMIT[220] & ~reg_be))) |
+ (addr_hit[221] & (|(ALERT_HANDLER_PERMIT[221] & ~reg_be))) |
+ (addr_hit[222] & (|(ALERT_HANDLER_PERMIT[222] & ~reg_be))) |
+ (addr_hit[223] & (|(ALERT_HANDLER_PERMIT[223] & ~reg_be))) |
+ (addr_hit[224] & (|(ALERT_HANDLER_PERMIT[224] & ~reg_be))) |
+ (addr_hit[225] & (|(ALERT_HANDLER_PERMIT[225] & ~reg_be))) |
+ (addr_hit[226] & (|(ALERT_HANDLER_PERMIT[226] & ~reg_be))) |
+ (addr_hit[227] & (|(ALERT_HANDLER_PERMIT[227] & ~reg_be))) |
+ (addr_hit[228] & (|(ALERT_HANDLER_PERMIT[228] & ~reg_be))) |
+ (addr_hit[229] & (|(ALERT_HANDLER_PERMIT[229] & ~reg_be))) |
+ (addr_hit[230] & (|(ALERT_HANDLER_PERMIT[230] & ~reg_be))) |
+ (addr_hit[231] & (|(ALERT_HANDLER_PERMIT[231] & ~reg_be))) |
+ (addr_hit[232] & (|(ALERT_HANDLER_PERMIT[232] & ~reg_be))) |
+ (addr_hit[233] & (|(ALERT_HANDLER_PERMIT[233] & ~reg_be))) |
+ (addr_hit[234] & (|(ALERT_HANDLER_PERMIT[234] & ~reg_be))) |
+ (addr_hit[235] & (|(ALERT_HANDLER_PERMIT[235] & ~reg_be))) |
+ (addr_hit[236] & (|(ALERT_HANDLER_PERMIT[236] & ~reg_be))) |
+ (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be))) |
+ (addr_hit[238] & (|(ALERT_HANDLER_PERMIT[238] & ~reg_be))) |
+ (addr_hit[239] & (|(ALERT_HANDLER_PERMIT[239] & ~reg_be))) |
+ (addr_hit[240] & (|(ALERT_HANDLER_PERMIT[240] & ~reg_be))) |
+ (addr_hit[241] & (|(ALERT_HANDLER_PERMIT[241] & ~reg_be))) |
+ (addr_hit[242] & (|(ALERT_HANDLER_PERMIT[242] & ~reg_be))) |
+ (addr_hit[243] & (|(ALERT_HANDLER_PERMIT[243] & ~reg_be))) |
+ (addr_hit[244] & (|(ALERT_HANDLER_PERMIT[244] & ~reg_be))) |
+ (addr_hit[245] & (|(ALERT_HANDLER_PERMIT[245] & ~reg_be))) |
+ (addr_hit[246] & (|(ALERT_HANDLER_PERMIT[246] & ~reg_be))) |
+ (addr_hit[247] & (|(ALERT_HANDLER_PERMIT[247] & ~reg_be))) |
+ (addr_hit[248] & (|(ALERT_HANDLER_PERMIT[248] & ~reg_be))) |
+ (addr_hit[249] & (|(ALERT_HANDLER_PERMIT[249] & ~reg_be))) |
+ (addr_hit[250] & (|(ALERT_HANDLER_PERMIT[250] & ~reg_be))) |
+ (addr_hit[251] & (|(ALERT_HANDLER_PERMIT[251] & ~reg_be))) |
+ (addr_hit[252] & (|(ALERT_HANDLER_PERMIT[252] & ~reg_be))) |
+ (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be))) |
+ (addr_hit[254] & (|(ALERT_HANDLER_PERMIT[254] & ~reg_be))) |
+ (addr_hit[255] & (|(ALERT_HANDLER_PERMIT[255] & ~reg_be))) |
+ (addr_hit[256] & (|(ALERT_HANDLER_PERMIT[256] & ~reg_be))) |
+ (addr_hit[257] & (|(ALERT_HANDLER_PERMIT[257] & ~reg_be))) |
+ (addr_hit[258] & (|(ALERT_HANDLER_PERMIT[258] & ~reg_be))) |
+ (addr_hit[259] & (|(ALERT_HANDLER_PERMIT[259] & ~reg_be))) |
+ (addr_hit[260] & (|(ALERT_HANDLER_PERMIT[260] & ~reg_be))) |
+ (addr_hit[261] & (|(ALERT_HANDLER_PERMIT[261] & ~reg_be))) |
+ (addr_hit[262] & (|(ALERT_HANDLER_PERMIT[262] & ~reg_be))) |
+ (addr_hit[263] & (|(ALERT_HANDLER_PERMIT[263] & ~reg_be))) |
+ (addr_hit[264] & (|(ALERT_HANDLER_PERMIT[264] & ~reg_be))) |
+ (addr_hit[265] & (|(ALERT_HANDLER_PERMIT[265] & ~reg_be))) |
+ (addr_hit[266] & (|(ALERT_HANDLER_PERMIT[266] & ~reg_be))) |
+ (addr_hit[267] & (|(ALERT_HANDLER_PERMIT[267] & ~reg_be))) |
+ (addr_hit[268] & (|(ALERT_HANDLER_PERMIT[268] & ~reg_be))) |
+ (addr_hit[269] & (|(ALERT_HANDLER_PERMIT[269] & ~reg_be))) |
+ (addr_hit[270] & (|(ALERT_HANDLER_PERMIT[270] & ~reg_be))) |
+ (addr_hit[271] & (|(ALERT_HANDLER_PERMIT[271] & ~reg_be))) |
+ (addr_hit[272] & (|(ALERT_HANDLER_PERMIT[272] & ~reg_be))) |
+ (addr_hit[273] & (|(ALERT_HANDLER_PERMIT[273] & ~reg_be))) |
+ (addr_hit[274] & (|(ALERT_HANDLER_PERMIT[274] & ~reg_be))) |
+ (addr_hit[275] & (|(ALERT_HANDLER_PERMIT[275] & ~reg_be))) |
+ (addr_hit[276] & (|(ALERT_HANDLER_PERMIT[276] & ~reg_be))) |
+ (addr_hit[277] & (|(ALERT_HANDLER_PERMIT[277] & ~reg_be))) |
+ (addr_hit[278] & (|(ALERT_HANDLER_PERMIT[278] & ~reg_be))) |
+ (addr_hit[279] & (|(ALERT_HANDLER_PERMIT[279] & ~reg_be))) |
+ (addr_hit[280] & (|(ALERT_HANDLER_PERMIT[280] & ~reg_be))) |
+ (addr_hit[281] & (|(ALERT_HANDLER_PERMIT[281] & ~reg_be))) |
+ (addr_hit[282] & (|(ALERT_HANDLER_PERMIT[282] & ~reg_be))) |
+ (addr_hit[283] & (|(ALERT_HANDLER_PERMIT[283] & ~reg_be))) |
+ (addr_hit[284] & (|(ALERT_HANDLER_PERMIT[284] & ~reg_be))) |
+ (addr_hit[285] & (|(ALERT_HANDLER_PERMIT[285] & ~reg_be))) |
+ (addr_hit[286] & (|(ALERT_HANDLER_PERMIT[286] & ~reg_be))) |
+ (addr_hit[287] & (|(ALERT_HANDLER_PERMIT[287] & ~reg_be))) |
+ (addr_hit[288] & (|(ALERT_HANDLER_PERMIT[288] & ~reg_be))) |
+ (addr_hit[289] & (|(ALERT_HANDLER_PERMIT[289] & ~reg_be))) |
+ (addr_hit[290] & (|(ALERT_HANDLER_PERMIT[290] & ~reg_be))) |
+ (addr_hit[291] & (|(ALERT_HANDLER_PERMIT[291] & ~reg_be))) |
+ (addr_hit[292] & (|(ALERT_HANDLER_PERMIT[292] & ~reg_be))) |
+ (addr_hit[293] & (|(ALERT_HANDLER_PERMIT[293] & ~reg_be))) |
+ (addr_hit[294] & (|(ALERT_HANDLER_PERMIT[294] & ~reg_be))) |
+ (addr_hit[295] & (|(ALERT_HANDLER_PERMIT[295] & ~reg_be))) |
+ (addr_hit[296] & (|(ALERT_HANDLER_PERMIT[296] & ~reg_be))) |
+ (addr_hit[297] & (|(ALERT_HANDLER_PERMIT[297] & ~reg_be))) |
+ (addr_hit[298] & (|(ALERT_HANDLER_PERMIT[298] & ~reg_be))) |
+ (addr_hit[299] & (|(ALERT_HANDLER_PERMIT[299] & ~reg_be))) |
+ (addr_hit[300] & (|(ALERT_HANDLER_PERMIT[300] & ~reg_be))) |
+ (addr_hit[301] & (|(ALERT_HANDLER_PERMIT[301] & ~reg_be))) |
+ (addr_hit[302] & (|(ALERT_HANDLER_PERMIT[302] & ~reg_be))) |
+ (addr_hit[303] & (|(ALERT_HANDLER_PERMIT[303] & ~reg_be))) |
+ (addr_hit[304] & (|(ALERT_HANDLER_PERMIT[304] & ~reg_be))) |
+ (addr_hit[305] & (|(ALERT_HANDLER_PERMIT[305] & ~reg_be))) |
+ (addr_hit[306] & (|(ALERT_HANDLER_PERMIT[306] & ~reg_be))) |
+ (addr_hit[307] & (|(ALERT_HANDLER_PERMIT[307] & ~reg_be))) |
+ (addr_hit[308] & (|(ALERT_HANDLER_PERMIT[308] & ~reg_be))) |
+ (addr_hit[309] & (|(ALERT_HANDLER_PERMIT[309] & ~reg_be))) |
+ (addr_hit[310] & (|(ALERT_HANDLER_PERMIT[310] & ~reg_be))) |
+ (addr_hit[311] & (|(ALERT_HANDLER_PERMIT[311] & ~reg_be))) |
+ (addr_hit[312] & (|(ALERT_HANDLER_PERMIT[312] & ~reg_be))) |
+ (addr_hit[313] & (|(ALERT_HANDLER_PERMIT[313] & ~reg_be))) |
+ (addr_hit[314] & (|(ALERT_HANDLER_PERMIT[314] & ~reg_be))) |
+ (addr_hit[315] & (|(ALERT_HANDLER_PERMIT[315] & ~reg_be))) |
+ (addr_hit[316] & (|(ALERT_HANDLER_PERMIT[316] & ~reg_be))) |
+ (addr_hit[317] & (|(ALERT_HANDLER_PERMIT[317] & ~reg_be))) |
+ (addr_hit[318] & (|(ALERT_HANDLER_PERMIT[318] & ~reg_be))) |
+ (addr_hit[319] & (|(ALERT_HANDLER_PERMIT[319] & ~reg_be))) |
+ (addr_hit[320] & (|(ALERT_HANDLER_PERMIT[320] & ~reg_be))) |
+ (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be))) |
+ (addr_hit[322] & (|(ALERT_HANDLER_PERMIT[322] & ~reg_be))) |
+ (addr_hit[323] & (|(ALERT_HANDLER_PERMIT[323] & ~reg_be))) |
+ (addr_hit[324] & (|(ALERT_HANDLER_PERMIT[324] & ~reg_be))) |
+ (addr_hit[325] & (|(ALERT_HANDLER_PERMIT[325] & ~reg_be))) |
+ (addr_hit[326] & (|(ALERT_HANDLER_PERMIT[326] & ~reg_be))) |
+ (addr_hit[327] & (|(ALERT_HANDLER_PERMIT[327] & ~reg_be))) |
+ (addr_hit[328] & (|(ALERT_HANDLER_PERMIT[328] & ~reg_be))) |
+ (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be))) |
+ (addr_hit[330] & (|(ALERT_HANDLER_PERMIT[330] & ~reg_be))) |
+ (addr_hit[331] & (|(ALERT_HANDLER_PERMIT[331] & ~reg_be))) |
+ (addr_hit[332] & (|(ALERT_HANDLER_PERMIT[332] & ~reg_be))) |
+ (addr_hit[333] & (|(ALERT_HANDLER_PERMIT[333] & ~reg_be))) |
+ (addr_hit[334] & (|(ALERT_HANDLER_PERMIT[334] & ~reg_be))) |
+ (addr_hit[335] & (|(ALERT_HANDLER_PERMIT[335] & ~reg_be))) |
+ (addr_hit[336] & (|(ALERT_HANDLER_PERMIT[336] & ~reg_be))) |
+ (addr_hit[337] & (|(ALERT_HANDLER_PERMIT[337] & ~reg_be))) |
+ (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) |
+ (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) |
+ (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) |
+ (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) |
+ (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) |
+ (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) |
+ (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) |
+ (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) |
+ (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) |
+ (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) |
+ (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) |
+ (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))) |
+ (addr_hit[350] & (|(ALERT_HANDLER_PERMIT[350] & ~reg_be))) |
+ (addr_hit[351] & (|(ALERT_HANDLER_PERMIT[351] & ~reg_be))) |
+ (addr_hit[352] & (|(ALERT_HANDLER_PERMIT[352] & ~reg_be))) |
+ (addr_hit[353] & (|(ALERT_HANDLER_PERMIT[353] & ~reg_be))) |
+ (addr_hit[354] & (|(ALERT_HANDLER_PERMIT[354] & ~reg_be))) |
+ (addr_hit[355] & (|(ALERT_HANDLER_PERMIT[355] & ~reg_be))) |
+ (addr_hit[356] & (|(ALERT_HANDLER_PERMIT[356] & ~reg_be))) |
+ (addr_hit[357] & (|(ALERT_HANDLER_PERMIT[357] & ~reg_be))) |
+ (addr_hit[358] & (|(ALERT_HANDLER_PERMIT[358] & ~reg_be))) |
+ (addr_hit[359] & (|(ALERT_HANDLER_PERMIT[359] & ~reg_be))) |
+ (addr_hit[360] & (|(ALERT_HANDLER_PERMIT[360] & ~reg_be))) |
+ (addr_hit[361] & (|(ALERT_HANDLER_PERMIT[361] & ~reg_be))) |
+ (addr_hit[362] & (|(ALERT_HANDLER_PERMIT[362] & ~reg_be))) |
+ (addr_hit[363] & (|(ALERT_HANDLER_PERMIT[363] & ~reg_be))) |
+ (addr_hit[364] & (|(ALERT_HANDLER_PERMIT[364] & ~reg_be))) |
+ (addr_hit[365] & (|(ALERT_HANDLER_PERMIT[365] & ~reg_be))) |
+ (addr_hit[366] & (|(ALERT_HANDLER_PERMIT[366] & ~reg_be))) |
+ (addr_hit[367] & (|(ALERT_HANDLER_PERMIT[367] & ~reg_be))) |
+ (addr_hit[368] & (|(ALERT_HANDLER_PERMIT[368] & ~reg_be))) |
+ (addr_hit[369] & (|(ALERT_HANDLER_PERMIT[369] & ~reg_be))) |
+ (addr_hit[370] & (|(ALERT_HANDLER_PERMIT[370] & ~reg_be))) |
+ (addr_hit[371] & (|(ALERT_HANDLER_PERMIT[371] & ~reg_be))) |
+ (addr_hit[372] & (|(ALERT_HANDLER_PERMIT[372] & ~reg_be))) |
+ (addr_hit[373] & (|(ALERT_HANDLER_PERMIT[373] & ~reg_be))) |
+ (addr_hit[374] & (|(ALERT_HANDLER_PERMIT[374] & ~reg_be))) |
+ (addr_hit[375] & (|(ALERT_HANDLER_PERMIT[375] & ~reg_be))) |
+ (addr_hit[376] & (|(ALERT_HANDLER_PERMIT[376] & ~reg_be))) |
+ (addr_hit[377] & (|(ALERT_HANDLER_PERMIT[377] & ~reg_be))) |
+ (addr_hit[378] & (|(ALERT_HANDLER_PERMIT[378] & ~reg_be))) |
+ (addr_hit[379] & (|(ALERT_HANDLER_PERMIT[379] & ~reg_be))) |
+ (addr_hit[380] & (|(ALERT_HANDLER_PERMIT[380] & ~reg_be))) |
+ (addr_hit[381] & (|(ALERT_HANDLER_PERMIT[381] & ~reg_be))) |
+ (addr_hit[382] & (|(ALERT_HANDLER_PERMIT[382] & ~reg_be))) |
+ (addr_hit[383] & (|(ALERT_HANDLER_PERMIT[383] & ~reg_be))) |
+ (addr_hit[384] & (|(ALERT_HANDLER_PERMIT[384] & ~reg_be))) |
+ (addr_hit[385] & (|(ALERT_HANDLER_PERMIT[385] & ~reg_be))) |
+ (addr_hit[386] & (|(ALERT_HANDLER_PERMIT[386] & ~reg_be))) |
+ (addr_hit[387] & (|(ALERT_HANDLER_PERMIT[387] & ~reg_be))) |
+ (addr_hit[388] & (|(ALERT_HANDLER_PERMIT[388] & ~reg_be))) |
+ (addr_hit[389] & (|(ALERT_HANDLER_PERMIT[389] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign intr_state_classa_wd = reg_wdata[0];
+
+ assign intr_state_classb_wd = reg_wdata[1];
+
+ assign intr_state_classc_wd = reg_wdata[2];
+
+ assign intr_state_classd_wd = reg_wdata[3];
+ assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign intr_enable_classa_wd = reg_wdata[0];
+
+ assign intr_enable_classb_wd = reg_wdata[1];
+
+ assign intr_enable_classc_wd = reg_wdata[2];
+
+ assign intr_enable_classd_wd = reg_wdata[3];
+ assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign intr_test_classa_wd = reg_wdata[0];
+
+ assign intr_test_classb_wd = reg_wdata[1];
+
+ assign intr_test_classc_wd = reg_wdata[2];
+
+ assign intr_test_classd_wd = reg_wdata[3];
+ assign ping_timer_regwen_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign ping_timer_regwen_wd = reg_wdata[0];
+ assign ping_timeout_cyc_shadowed_re = addr_hit[4] & reg_re & !reg_error;
+ assign ping_timeout_cyc_shadowed_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign ping_timeout_cyc_shadowed_wd = reg_wdata[15:0];
+ assign ping_timer_en_shadowed_re = addr_hit[5] & reg_re & !reg_error;
+ assign ping_timer_en_shadowed_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign ping_timer_en_shadowed_wd = reg_wdata[0];
+ assign alert_regwen_0_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign alert_regwen_0_wd = reg_wdata[0];
+ assign alert_regwen_1_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign alert_regwen_1_wd = reg_wdata[0];
+ assign alert_regwen_2_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign alert_regwen_2_wd = reg_wdata[0];
+ assign alert_regwen_3_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign alert_regwen_3_wd = reg_wdata[0];
+ assign alert_regwen_4_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign alert_regwen_4_wd = reg_wdata[0];
+ assign alert_regwen_5_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign alert_regwen_5_wd = reg_wdata[0];
+ assign alert_regwen_6_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign alert_regwen_6_wd = reg_wdata[0];
+ assign alert_regwen_7_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign alert_regwen_7_wd = reg_wdata[0];
+ assign alert_regwen_8_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign alert_regwen_8_wd = reg_wdata[0];
+ assign alert_regwen_9_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign alert_regwen_9_wd = reg_wdata[0];
+ assign alert_regwen_10_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign alert_regwen_10_wd = reg_wdata[0];
+ assign alert_regwen_11_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign alert_regwen_11_wd = reg_wdata[0];
+ assign alert_regwen_12_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign alert_regwen_12_wd = reg_wdata[0];
+ assign alert_regwen_13_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign alert_regwen_13_wd = reg_wdata[0];
+ assign alert_regwen_14_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign alert_regwen_14_wd = reg_wdata[0];
+ assign alert_regwen_15_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign alert_regwen_15_wd = reg_wdata[0];
+ assign alert_regwen_16_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign alert_regwen_16_wd = reg_wdata[0];
+ assign alert_regwen_17_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign alert_regwen_17_wd = reg_wdata[0];
+ assign alert_regwen_18_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign alert_regwen_18_wd = reg_wdata[0];
+ assign alert_regwen_19_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign alert_regwen_19_wd = reg_wdata[0];
+ assign alert_regwen_20_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign alert_regwen_20_wd = reg_wdata[0];
+ assign alert_regwen_21_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign alert_regwen_21_wd = reg_wdata[0];
+ assign alert_regwen_22_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign alert_regwen_22_wd = reg_wdata[0];
+ assign alert_regwen_23_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign alert_regwen_23_wd = reg_wdata[0];
+ assign alert_regwen_24_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign alert_regwen_24_wd = reg_wdata[0];
+ assign alert_regwen_25_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign alert_regwen_25_wd = reg_wdata[0];
+ assign alert_regwen_26_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign alert_regwen_26_wd = reg_wdata[0];
+ assign alert_regwen_27_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign alert_regwen_27_wd = reg_wdata[0];
+ assign alert_regwen_28_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign alert_regwen_28_wd = reg_wdata[0];
+ assign alert_regwen_29_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign alert_regwen_29_wd = reg_wdata[0];
+ assign alert_regwen_30_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign alert_regwen_30_wd = reg_wdata[0];
+ assign alert_regwen_31_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign alert_regwen_31_wd = reg_wdata[0];
+ assign alert_regwen_32_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign alert_regwen_32_wd = reg_wdata[0];
+ assign alert_regwen_33_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign alert_regwen_33_wd = reg_wdata[0];
+ assign alert_regwen_34_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign alert_regwen_34_wd = reg_wdata[0];
+ assign alert_regwen_35_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign alert_regwen_35_wd = reg_wdata[0];
+ assign alert_regwen_36_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign alert_regwen_36_wd = reg_wdata[0];
+ assign alert_regwen_37_we = addr_hit[43] & reg_we & !reg_error;
+
+ assign alert_regwen_37_wd = reg_wdata[0];
+ assign alert_regwen_38_we = addr_hit[44] & reg_we & !reg_error;
+
+ assign alert_regwen_38_wd = reg_wdata[0];
+ assign alert_regwen_39_we = addr_hit[45] & reg_we & !reg_error;
+
+ assign alert_regwen_39_wd = reg_wdata[0];
+ assign alert_regwen_40_we = addr_hit[46] & reg_we & !reg_error;
+
+ assign alert_regwen_40_wd = reg_wdata[0];
+ assign alert_regwen_41_we = addr_hit[47] & reg_we & !reg_error;
+
+ assign alert_regwen_41_wd = reg_wdata[0];
+ assign alert_regwen_42_we = addr_hit[48] & reg_we & !reg_error;
+
+ assign alert_regwen_42_wd = reg_wdata[0];
+ assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error;
+
+ assign alert_regwen_43_wd = reg_wdata[0];
+ assign alert_regwen_44_we = addr_hit[50] & reg_we & !reg_error;
+
+ assign alert_regwen_44_wd = reg_wdata[0];
+ assign alert_regwen_45_we = addr_hit[51] & reg_we & !reg_error;
+
+ assign alert_regwen_45_wd = reg_wdata[0];
+ assign alert_regwen_46_we = addr_hit[52] & reg_we & !reg_error;
+
+ assign alert_regwen_46_wd = reg_wdata[0];
+ assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error;
+
+ assign alert_regwen_47_wd = reg_wdata[0];
+ assign alert_regwen_48_we = addr_hit[54] & reg_we & !reg_error;
+
+ assign alert_regwen_48_wd = reg_wdata[0];
+ assign alert_regwen_49_we = addr_hit[55] & reg_we & !reg_error;
+
+ assign alert_regwen_49_wd = reg_wdata[0];
+ assign alert_regwen_50_we = addr_hit[56] & reg_we & !reg_error;
+
+ assign alert_regwen_50_wd = reg_wdata[0];
+ assign alert_regwen_51_we = addr_hit[57] & reg_we & !reg_error;
+
+ assign alert_regwen_51_wd = reg_wdata[0];
+ assign alert_regwen_52_we = addr_hit[58] & reg_we & !reg_error;
+
+ assign alert_regwen_52_wd = reg_wdata[0];
+ assign alert_regwen_53_we = addr_hit[59] & reg_we & !reg_error;
+
+ assign alert_regwen_53_wd = reg_wdata[0];
+ assign alert_regwen_54_we = addr_hit[60] & reg_we & !reg_error;
+
+ assign alert_regwen_54_wd = reg_wdata[0];
+ assign alert_regwen_55_we = addr_hit[61] & reg_we & !reg_error;
+
+ assign alert_regwen_55_wd = reg_wdata[0];
+ assign alert_regwen_56_we = addr_hit[62] & reg_we & !reg_error;
+
+ assign alert_regwen_56_wd = reg_wdata[0];
+ assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error;
+
+ assign alert_regwen_57_wd = reg_wdata[0];
+ assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error;
+
+ assign alert_regwen_58_wd = reg_wdata[0];
+ assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error;
+
+ assign alert_regwen_59_wd = reg_wdata[0];
+ assign alert_regwen_60_we = addr_hit[66] & reg_we & !reg_error;
+
+ assign alert_regwen_60_wd = reg_wdata[0];
+ assign alert_regwen_61_we = addr_hit[67] & reg_we & !reg_error;
+
+ assign alert_regwen_61_wd = reg_wdata[0];
+ assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error;
+
+ assign alert_regwen_62_wd = reg_wdata[0];
+ assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error;
+
+ assign alert_regwen_63_wd = reg_wdata[0];
+ assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error;
+
+ assign alert_regwen_64_wd = reg_wdata[0];
+ assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error;
+
+ assign alert_regwen_65_wd = reg_wdata[0];
+ assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error;
+
+ assign alert_regwen_66_wd = reg_wdata[0];
+ assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error;
+
+ assign alert_regwen_67_wd = reg_wdata[0];
+ assign alert_regwen_68_we = addr_hit[74] & reg_we & !reg_error;
+
+ assign alert_regwen_68_wd = reg_wdata[0];
+ assign alert_regwen_69_we = addr_hit[75] & reg_we & !reg_error;
+
+ assign alert_regwen_69_wd = reg_wdata[0];
+ assign alert_regwen_70_we = addr_hit[76] & reg_we & !reg_error;
+
+ assign alert_regwen_70_wd = reg_wdata[0];
+ assign alert_regwen_71_we = addr_hit[77] & reg_we & !reg_error;
+
+ assign alert_regwen_71_wd = reg_wdata[0];
+ assign alert_regwen_72_we = addr_hit[78] & reg_we & !reg_error;
+
+ assign alert_regwen_72_wd = reg_wdata[0];
+ assign alert_regwen_73_we = addr_hit[79] & reg_we & !reg_error;
+
+ assign alert_regwen_73_wd = reg_wdata[0];
+ assign alert_regwen_74_we = addr_hit[80] & reg_we & !reg_error;
+
+ assign alert_regwen_74_wd = reg_wdata[0];
+ assign alert_en_shadowed_0_re = addr_hit[81] & reg_re & !reg_error;
+ assign alert_en_shadowed_0_we = addr_hit[81] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_0_wd = reg_wdata[0];
+ assign alert_en_shadowed_1_re = addr_hit[82] & reg_re & !reg_error;
+ assign alert_en_shadowed_1_we = addr_hit[82] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_1_wd = reg_wdata[0];
+ assign alert_en_shadowed_2_re = addr_hit[83] & reg_re & !reg_error;
+ assign alert_en_shadowed_2_we = addr_hit[83] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_2_wd = reg_wdata[0];
+ assign alert_en_shadowed_3_re = addr_hit[84] & reg_re & !reg_error;
+ assign alert_en_shadowed_3_we = addr_hit[84] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_3_wd = reg_wdata[0];
+ assign alert_en_shadowed_4_re = addr_hit[85] & reg_re & !reg_error;
+ assign alert_en_shadowed_4_we = addr_hit[85] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_4_wd = reg_wdata[0];
+ assign alert_en_shadowed_5_re = addr_hit[86] & reg_re & !reg_error;
+ assign alert_en_shadowed_5_we = addr_hit[86] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_5_wd = reg_wdata[0];
+ assign alert_en_shadowed_6_re = addr_hit[87] & reg_re & !reg_error;
+ assign alert_en_shadowed_6_we = addr_hit[87] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_6_wd = reg_wdata[0];
+ assign alert_en_shadowed_7_re = addr_hit[88] & reg_re & !reg_error;
+ assign alert_en_shadowed_7_we = addr_hit[88] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_7_wd = reg_wdata[0];
+ assign alert_en_shadowed_8_re = addr_hit[89] & reg_re & !reg_error;
+ assign alert_en_shadowed_8_we = addr_hit[89] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_8_wd = reg_wdata[0];
+ assign alert_en_shadowed_9_re = addr_hit[90] & reg_re & !reg_error;
+ assign alert_en_shadowed_9_we = addr_hit[90] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_9_wd = reg_wdata[0];
+ assign alert_en_shadowed_10_re = addr_hit[91] & reg_re & !reg_error;
+ assign alert_en_shadowed_10_we = addr_hit[91] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_10_wd = reg_wdata[0];
+ assign alert_en_shadowed_11_re = addr_hit[92] & reg_re & !reg_error;
+ assign alert_en_shadowed_11_we = addr_hit[92] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_11_wd = reg_wdata[0];
+ assign alert_en_shadowed_12_re = addr_hit[93] & reg_re & !reg_error;
+ assign alert_en_shadowed_12_we = addr_hit[93] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_12_wd = reg_wdata[0];
+ assign alert_en_shadowed_13_re = addr_hit[94] & reg_re & !reg_error;
+ assign alert_en_shadowed_13_we = addr_hit[94] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_13_wd = reg_wdata[0];
+ assign alert_en_shadowed_14_re = addr_hit[95] & reg_re & !reg_error;
+ assign alert_en_shadowed_14_we = addr_hit[95] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_14_wd = reg_wdata[0];
+ assign alert_en_shadowed_15_re = addr_hit[96] & reg_re & !reg_error;
+ assign alert_en_shadowed_15_we = addr_hit[96] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_15_wd = reg_wdata[0];
+ assign alert_en_shadowed_16_re = addr_hit[97] & reg_re & !reg_error;
+ assign alert_en_shadowed_16_we = addr_hit[97] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_16_wd = reg_wdata[0];
+ assign alert_en_shadowed_17_re = addr_hit[98] & reg_re & !reg_error;
+ assign alert_en_shadowed_17_we = addr_hit[98] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_17_wd = reg_wdata[0];
+ assign alert_en_shadowed_18_re = addr_hit[99] & reg_re & !reg_error;
+ assign alert_en_shadowed_18_we = addr_hit[99] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_18_wd = reg_wdata[0];
+ assign alert_en_shadowed_19_re = addr_hit[100] & reg_re & !reg_error;
+ assign alert_en_shadowed_19_we = addr_hit[100] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_19_wd = reg_wdata[0];
+ assign alert_en_shadowed_20_re = addr_hit[101] & reg_re & !reg_error;
+ assign alert_en_shadowed_20_we = addr_hit[101] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_20_wd = reg_wdata[0];
+ assign alert_en_shadowed_21_re = addr_hit[102] & reg_re & !reg_error;
+ assign alert_en_shadowed_21_we = addr_hit[102] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_21_wd = reg_wdata[0];
+ assign alert_en_shadowed_22_re = addr_hit[103] & reg_re & !reg_error;
+ assign alert_en_shadowed_22_we = addr_hit[103] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_22_wd = reg_wdata[0];
+ assign alert_en_shadowed_23_re = addr_hit[104] & reg_re & !reg_error;
+ assign alert_en_shadowed_23_we = addr_hit[104] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_23_wd = reg_wdata[0];
+ assign alert_en_shadowed_24_re = addr_hit[105] & reg_re & !reg_error;
+ assign alert_en_shadowed_24_we = addr_hit[105] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_24_wd = reg_wdata[0];
+ assign alert_en_shadowed_25_re = addr_hit[106] & reg_re & !reg_error;
+ assign alert_en_shadowed_25_we = addr_hit[106] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_25_wd = reg_wdata[0];
+ assign alert_en_shadowed_26_re = addr_hit[107] & reg_re & !reg_error;
+ assign alert_en_shadowed_26_we = addr_hit[107] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_26_wd = reg_wdata[0];
+ assign alert_en_shadowed_27_re = addr_hit[108] & reg_re & !reg_error;
+ assign alert_en_shadowed_27_we = addr_hit[108] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_27_wd = reg_wdata[0];
+ assign alert_en_shadowed_28_re = addr_hit[109] & reg_re & !reg_error;
+ assign alert_en_shadowed_28_we = addr_hit[109] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_28_wd = reg_wdata[0];
+ assign alert_en_shadowed_29_re = addr_hit[110] & reg_re & !reg_error;
+ assign alert_en_shadowed_29_we = addr_hit[110] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_29_wd = reg_wdata[0];
+ assign alert_en_shadowed_30_re = addr_hit[111] & reg_re & !reg_error;
+ assign alert_en_shadowed_30_we = addr_hit[111] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_30_wd = reg_wdata[0];
+ assign alert_en_shadowed_31_re = addr_hit[112] & reg_re & !reg_error;
+ assign alert_en_shadowed_31_we = addr_hit[112] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_31_wd = reg_wdata[0];
+ assign alert_en_shadowed_32_re = addr_hit[113] & reg_re & !reg_error;
+ assign alert_en_shadowed_32_we = addr_hit[113] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_32_wd = reg_wdata[0];
+ assign alert_en_shadowed_33_re = addr_hit[114] & reg_re & !reg_error;
+ assign alert_en_shadowed_33_we = addr_hit[114] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_33_wd = reg_wdata[0];
+ assign alert_en_shadowed_34_re = addr_hit[115] & reg_re & !reg_error;
+ assign alert_en_shadowed_34_we = addr_hit[115] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_34_wd = reg_wdata[0];
+ assign alert_en_shadowed_35_re = addr_hit[116] & reg_re & !reg_error;
+ assign alert_en_shadowed_35_we = addr_hit[116] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_35_wd = reg_wdata[0];
+ assign alert_en_shadowed_36_re = addr_hit[117] & reg_re & !reg_error;
+ assign alert_en_shadowed_36_we = addr_hit[117] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_36_wd = reg_wdata[0];
+ assign alert_en_shadowed_37_re = addr_hit[118] & reg_re & !reg_error;
+ assign alert_en_shadowed_37_we = addr_hit[118] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_37_wd = reg_wdata[0];
+ assign alert_en_shadowed_38_re = addr_hit[119] & reg_re & !reg_error;
+ assign alert_en_shadowed_38_we = addr_hit[119] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_38_wd = reg_wdata[0];
+ assign alert_en_shadowed_39_re = addr_hit[120] & reg_re & !reg_error;
+ assign alert_en_shadowed_39_we = addr_hit[120] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_39_wd = reg_wdata[0];
+ assign alert_en_shadowed_40_re = addr_hit[121] & reg_re & !reg_error;
+ assign alert_en_shadowed_40_we = addr_hit[121] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_40_wd = reg_wdata[0];
+ assign alert_en_shadowed_41_re = addr_hit[122] & reg_re & !reg_error;
+ assign alert_en_shadowed_41_we = addr_hit[122] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_41_wd = reg_wdata[0];
+ assign alert_en_shadowed_42_re = addr_hit[123] & reg_re & !reg_error;
+ assign alert_en_shadowed_42_we = addr_hit[123] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_42_wd = reg_wdata[0];
+ assign alert_en_shadowed_43_re = addr_hit[124] & reg_re & !reg_error;
+ assign alert_en_shadowed_43_we = addr_hit[124] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_43_wd = reg_wdata[0];
+ assign alert_en_shadowed_44_re = addr_hit[125] & reg_re & !reg_error;
+ assign alert_en_shadowed_44_we = addr_hit[125] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_44_wd = reg_wdata[0];
+ assign alert_en_shadowed_45_re = addr_hit[126] & reg_re & !reg_error;
+ assign alert_en_shadowed_45_we = addr_hit[126] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_45_wd = reg_wdata[0];
+ assign alert_en_shadowed_46_re = addr_hit[127] & reg_re & !reg_error;
+ assign alert_en_shadowed_46_we = addr_hit[127] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_46_wd = reg_wdata[0];
+ assign alert_en_shadowed_47_re = addr_hit[128] & reg_re & !reg_error;
+ assign alert_en_shadowed_47_we = addr_hit[128] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_47_wd = reg_wdata[0];
+ assign alert_en_shadowed_48_re = addr_hit[129] & reg_re & !reg_error;
+ assign alert_en_shadowed_48_we = addr_hit[129] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_48_wd = reg_wdata[0];
+ assign alert_en_shadowed_49_re = addr_hit[130] & reg_re & !reg_error;
+ assign alert_en_shadowed_49_we = addr_hit[130] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_49_wd = reg_wdata[0];
+ assign alert_en_shadowed_50_re = addr_hit[131] & reg_re & !reg_error;
+ assign alert_en_shadowed_50_we = addr_hit[131] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_50_wd = reg_wdata[0];
+ assign alert_en_shadowed_51_re = addr_hit[132] & reg_re & !reg_error;
+ assign alert_en_shadowed_51_we = addr_hit[132] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_51_wd = reg_wdata[0];
+ assign alert_en_shadowed_52_re = addr_hit[133] & reg_re & !reg_error;
+ assign alert_en_shadowed_52_we = addr_hit[133] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_52_wd = reg_wdata[0];
+ assign alert_en_shadowed_53_re = addr_hit[134] & reg_re & !reg_error;
+ assign alert_en_shadowed_53_we = addr_hit[134] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_53_wd = reg_wdata[0];
+ assign alert_en_shadowed_54_re = addr_hit[135] & reg_re & !reg_error;
+ assign alert_en_shadowed_54_we = addr_hit[135] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_54_wd = reg_wdata[0];
+ assign alert_en_shadowed_55_re = addr_hit[136] & reg_re & !reg_error;
+ assign alert_en_shadowed_55_we = addr_hit[136] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_55_wd = reg_wdata[0];
+ assign alert_en_shadowed_56_re = addr_hit[137] & reg_re & !reg_error;
+ assign alert_en_shadowed_56_we = addr_hit[137] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_56_wd = reg_wdata[0];
+ assign alert_en_shadowed_57_re = addr_hit[138] & reg_re & !reg_error;
+ assign alert_en_shadowed_57_we = addr_hit[138] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_57_wd = reg_wdata[0];
+ assign alert_en_shadowed_58_re = addr_hit[139] & reg_re & !reg_error;
+ assign alert_en_shadowed_58_we = addr_hit[139] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_58_wd = reg_wdata[0];
+ assign alert_en_shadowed_59_re = addr_hit[140] & reg_re & !reg_error;
+ assign alert_en_shadowed_59_we = addr_hit[140] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_59_wd = reg_wdata[0];
+ assign alert_en_shadowed_60_re = addr_hit[141] & reg_re & !reg_error;
+ assign alert_en_shadowed_60_we = addr_hit[141] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_60_wd = reg_wdata[0];
+ assign alert_en_shadowed_61_re = addr_hit[142] & reg_re & !reg_error;
+ assign alert_en_shadowed_61_we = addr_hit[142] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_61_wd = reg_wdata[0];
+ assign alert_en_shadowed_62_re = addr_hit[143] & reg_re & !reg_error;
+ assign alert_en_shadowed_62_we = addr_hit[143] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_62_wd = reg_wdata[0];
+ assign alert_en_shadowed_63_re = addr_hit[144] & reg_re & !reg_error;
+ assign alert_en_shadowed_63_we = addr_hit[144] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_63_wd = reg_wdata[0];
+ assign alert_en_shadowed_64_re = addr_hit[145] & reg_re & !reg_error;
+ assign alert_en_shadowed_64_we = addr_hit[145] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_64_wd = reg_wdata[0];
+ assign alert_en_shadowed_65_re = addr_hit[146] & reg_re & !reg_error;
+ assign alert_en_shadowed_65_we = addr_hit[146] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_65_wd = reg_wdata[0];
+ assign alert_en_shadowed_66_re = addr_hit[147] & reg_re & !reg_error;
+ assign alert_en_shadowed_66_we = addr_hit[147] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_66_wd = reg_wdata[0];
+ assign alert_en_shadowed_67_re = addr_hit[148] & reg_re & !reg_error;
+ assign alert_en_shadowed_67_we = addr_hit[148] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_67_wd = reg_wdata[0];
+ assign alert_en_shadowed_68_re = addr_hit[149] & reg_re & !reg_error;
+ assign alert_en_shadowed_68_we = addr_hit[149] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_68_wd = reg_wdata[0];
+ assign alert_en_shadowed_69_re = addr_hit[150] & reg_re & !reg_error;
+ assign alert_en_shadowed_69_we = addr_hit[150] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_69_wd = reg_wdata[0];
+ assign alert_en_shadowed_70_re = addr_hit[151] & reg_re & !reg_error;
+ assign alert_en_shadowed_70_we = addr_hit[151] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_70_wd = reg_wdata[0];
+ assign alert_en_shadowed_71_re = addr_hit[152] & reg_re & !reg_error;
+ assign alert_en_shadowed_71_we = addr_hit[152] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_71_wd = reg_wdata[0];
+ assign alert_en_shadowed_72_re = addr_hit[153] & reg_re & !reg_error;
+ assign alert_en_shadowed_72_we = addr_hit[153] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_72_wd = reg_wdata[0];
+ assign alert_en_shadowed_73_re = addr_hit[154] & reg_re & !reg_error;
+ assign alert_en_shadowed_73_we = addr_hit[154] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_73_wd = reg_wdata[0];
+ assign alert_en_shadowed_74_re = addr_hit[155] & reg_re & !reg_error;
+ assign alert_en_shadowed_74_we = addr_hit[155] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_74_wd = reg_wdata[0];
+ assign alert_class_shadowed_0_re = addr_hit[156] & reg_re & !reg_error;
+ assign alert_class_shadowed_0_we = addr_hit[156] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_0_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_1_re = addr_hit[157] & reg_re & !reg_error;
+ assign alert_class_shadowed_1_we = addr_hit[157] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_1_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_2_re = addr_hit[158] & reg_re & !reg_error;
+ assign alert_class_shadowed_2_we = addr_hit[158] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_2_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_3_re = addr_hit[159] & reg_re & !reg_error;
+ assign alert_class_shadowed_3_we = addr_hit[159] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_3_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_4_re = addr_hit[160] & reg_re & !reg_error;
+ assign alert_class_shadowed_4_we = addr_hit[160] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_4_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_5_re = addr_hit[161] & reg_re & !reg_error;
+ assign alert_class_shadowed_5_we = addr_hit[161] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_5_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_6_re = addr_hit[162] & reg_re & !reg_error;
+ assign alert_class_shadowed_6_we = addr_hit[162] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_6_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_7_re = addr_hit[163] & reg_re & !reg_error;
+ assign alert_class_shadowed_7_we = addr_hit[163] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_7_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_8_re = addr_hit[164] & reg_re & !reg_error;
+ assign alert_class_shadowed_8_we = addr_hit[164] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_8_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_9_re = addr_hit[165] & reg_re & !reg_error;
+ assign alert_class_shadowed_9_we = addr_hit[165] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_9_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_10_re = addr_hit[166] & reg_re & !reg_error;
+ assign alert_class_shadowed_10_we = addr_hit[166] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_10_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_11_re = addr_hit[167] & reg_re & !reg_error;
+ assign alert_class_shadowed_11_we = addr_hit[167] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_11_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_12_re = addr_hit[168] & reg_re & !reg_error;
+ assign alert_class_shadowed_12_we = addr_hit[168] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_12_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_13_re = addr_hit[169] & reg_re & !reg_error;
+ assign alert_class_shadowed_13_we = addr_hit[169] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_13_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_14_re = addr_hit[170] & reg_re & !reg_error;
+ assign alert_class_shadowed_14_we = addr_hit[170] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_14_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_15_re = addr_hit[171] & reg_re & !reg_error;
+ assign alert_class_shadowed_15_we = addr_hit[171] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_15_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_16_re = addr_hit[172] & reg_re & !reg_error;
+ assign alert_class_shadowed_16_we = addr_hit[172] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_16_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_17_re = addr_hit[173] & reg_re & !reg_error;
+ assign alert_class_shadowed_17_we = addr_hit[173] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_17_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_18_re = addr_hit[174] & reg_re & !reg_error;
+ assign alert_class_shadowed_18_we = addr_hit[174] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_18_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_19_re = addr_hit[175] & reg_re & !reg_error;
+ assign alert_class_shadowed_19_we = addr_hit[175] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_19_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_20_re = addr_hit[176] & reg_re & !reg_error;
+ assign alert_class_shadowed_20_we = addr_hit[176] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_20_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_21_re = addr_hit[177] & reg_re & !reg_error;
+ assign alert_class_shadowed_21_we = addr_hit[177] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_21_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_22_re = addr_hit[178] & reg_re & !reg_error;
+ assign alert_class_shadowed_22_we = addr_hit[178] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_22_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_23_re = addr_hit[179] & reg_re & !reg_error;
+ assign alert_class_shadowed_23_we = addr_hit[179] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_23_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_24_re = addr_hit[180] & reg_re & !reg_error;
+ assign alert_class_shadowed_24_we = addr_hit[180] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_24_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_25_re = addr_hit[181] & reg_re & !reg_error;
+ assign alert_class_shadowed_25_we = addr_hit[181] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_25_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_26_re = addr_hit[182] & reg_re & !reg_error;
+ assign alert_class_shadowed_26_we = addr_hit[182] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_26_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_27_re = addr_hit[183] & reg_re & !reg_error;
+ assign alert_class_shadowed_27_we = addr_hit[183] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_27_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_28_re = addr_hit[184] & reg_re & !reg_error;
+ assign alert_class_shadowed_28_we = addr_hit[184] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_28_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_29_re = addr_hit[185] & reg_re & !reg_error;
+ assign alert_class_shadowed_29_we = addr_hit[185] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_29_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_30_re = addr_hit[186] & reg_re & !reg_error;
+ assign alert_class_shadowed_30_we = addr_hit[186] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_30_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_31_re = addr_hit[187] & reg_re & !reg_error;
+ assign alert_class_shadowed_31_we = addr_hit[187] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_31_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_32_re = addr_hit[188] & reg_re & !reg_error;
+ assign alert_class_shadowed_32_we = addr_hit[188] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_32_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_33_re = addr_hit[189] & reg_re & !reg_error;
+ assign alert_class_shadowed_33_we = addr_hit[189] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_33_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_34_re = addr_hit[190] & reg_re & !reg_error;
+ assign alert_class_shadowed_34_we = addr_hit[190] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_34_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_35_re = addr_hit[191] & reg_re & !reg_error;
+ assign alert_class_shadowed_35_we = addr_hit[191] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_35_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_36_re = addr_hit[192] & reg_re & !reg_error;
+ assign alert_class_shadowed_36_we = addr_hit[192] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_36_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_37_re = addr_hit[193] & reg_re & !reg_error;
+ assign alert_class_shadowed_37_we = addr_hit[193] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_37_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_38_re = addr_hit[194] & reg_re & !reg_error;
+ assign alert_class_shadowed_38_we = addr_hit[194] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_38_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_39_re = addr_hit[195] & reg_re & !reg_error;
+ assign alert_class_shadowed_39_we = addr_hit[195] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_39_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_40_re = addr_hit[196] & reg_re & !reg_error;
+ assign alert_class_shadowed_40_we = addr_hit[196] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_40_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_41_re = addr_hit[197] & reg_re & !reg_error;
+ assign alert_class_shadowed_41_we = addr_hit[197] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_41_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_42_re = addr_hit[198] & reg_re & !reg_error;
+ assign alert_class_shadowed_42_we = addr_hit[198] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_42_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_43_re = addr_hit[199] & reg_re & !reg_error;
+ assign alert_class_shadowed_43_we = addr_hit[199] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_43_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_44_re = addr_hit[200] & reg_re & !reg_error;
+ assign alert_class_shadowed_44_we = addr_hit[200] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_44_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_45_re = addr_hit[201] & reg_re & !reg_error;
+ assign alert_class_shadowed_45_we = addr_hit[201] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_45_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_46_re = addr_hit[202] & reg_re & !reg_error;
+ assign alert_class_shadowed_46_we = addr_hit[202] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_46_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_47_re = addr_hit[203] & reg_re & !reg_error;
+ assign alert_class_shadowed_47_we = addr_hit[203] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_47_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_48_re = addr_hit[204] & reg_re & !reg_error;
+ assign alert_class_shadowed_48_we = addr_hit[204] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_48_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_49_re = addr_hit[205] & reg_re & !reg_error;
+ assign alert_class_shadowed_49_we = addr_hit[205] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_49_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_50_re = addr_hit[206] & reg_re & !reg_error;
+ assign alert_class_shadowed_50_we = addr_hit[206] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_50_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_51_re = addr_hit[207] & reg_re & !reg_error;
+ assign alert_class_shadowed_51_we = addr_hit[207] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_51_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_52_re = addr_hit[208] & reg_re & !reg_error;
+ assign alert_class_shadowed_52_we = addr_hit[208] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_52_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_53_re = addr_hit[209] & reg_re & !reg_error;
+ assign alert_class_shadowed_53_we = addr_hit[209] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_53_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_54_re = addr_hit[210] & reg_re & !reg_error;
+ assign alert_class_shadowed_54_we = addr_hit[210] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_54_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_55_re = addr_hit[211] & reg_re & !reg_error;
+ assign alert_class_shadowed_55_we = addr_hit[211] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_55_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_56_re = addr_hit[212] & reg_re & !reg_error;
+ assign alert_class_shadowed_56_we = addr_hit[212] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_56_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_57_re = addr_hit[213] & reg_re & !reg_error;
+ assign alert_class_shadowed_57_we = addr_hit[213] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_57_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_58_re = addr_hit[214] & reg_re & !reg_error;
+ assign alert_class_shadowed_58_we = addr_hit[214] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_58_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_59_re = addr_hit[215] & reg_re & !reg_error;
+ assign alert_class_shadowed_59_we = addr_hit[215] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_59_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_60_re = addr_hit[216] & reg_re & !reg_error;
+ assign alert_class_shadowed_60_we = addr_hit[216] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_60_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_61_re = addr_hit[217] & reg_re & !reg_error;
+ assign alert_class_shadowed_61_we = addr_hit[217] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_61_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_62_re = addr_hit[218] & reg_re & !reg_error;
+ assign alert_class_shadowed_62_we = addr_hit[218] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_62_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_63_re = addr_hit[219] & reg_re & !reg_error;
+ assign alert_class_shadowed_63_we = addr_hit[219] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_63_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_64_re = addr_hit[220] & reg_re & !reg_error;
+ assign alert_class_shadowed_64_we = addr_hit[220] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_64_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_65_re = addr_hit[221] & reg_re & !reg_error;
+ assign alert_class_shadowed_65_we = addr_hit[221] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_65_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_66_re = addr_hit[222] & reg_re & !reg_error;
+ assign alert_class_shadowed_66_we = addr_hit[222] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_66_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_67_re = addr_hit[223] & reg_re & !reg_error;
+ assign alert_class_shadowed_67_we = addr_hit[223] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_67_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_68_re = addr_hit[224] & reg_re & !reg_error;
+ assign alert_class_shadowed_68_we = addr_hit[224] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_68_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_69_re = addr_hit[225] & reg_re & !reg_error;
+ assign alert_class_shadowed_69_we = addr_hit[225] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_69_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_70_re = addr_hit[226] & reg_re & !reg_error;
+ assign alert_class_shadowed_70_we = addr_hit[226] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_70_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_71_re = addr_hit[227] & reg_re & !reg_error;
+ assign alert_class_shadowed_71_we = addr_hit[227] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_71_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_72_re = addr_hit[228] & reg_re & !reg_error;
+ assign alert_class_shadowed_72_we = addr_hit[228] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_72_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_73_re = addr_hit[229] & reg_re & !reg_error;
+ assign alert_class_shadowed_73_we = addr_hit[229] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_73_wd = reg_wdata[1:0];
+ assign alert_class_shadowed_74_re = addr_hit[230] & reg_re & !reg_error;
+ assign alert_class_shadowed_74_we = addr_hit[230] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_74_wd = reg_wdata[1:0];
+ assign alert_cause_0_we = addr_hit[231] & reg_we & !reg_error;
+
+ assign alert_cause_0_wd = reg_wdata[0];
+ assign alert_cause_1_we = addr_hit[232] & reg_we & !reg_error;
+
+ assign alert_cause_1_wd = reg_wdata[0];
+ assign alert_cause_2_we = addr_hit[233] & reg_we & !reg_error;
+
+ assign alert_cause_2_wd = reg_wdata[0];
+ assign alert_cause_3_we = addr_hit[234] & reg_we & !reg_error;
+
+ assign alert_cause_3_wd = reg_wdata[0];
+ assign alert_cause_4_we = addr_hit[235] & reg_we & !reg_error;
+
+ assign alert_cause_4_wd = reg_wdata[0];
+ assign alert_cause_5_we = addr_hit[236] & reg_we & !reg_error;
+
+ assign alert_cause_5_wd = reg_wdata[0];
+ assign alert_cause_6_we = addr_hit[237] & reg_we & !reg_error;
+
+ assign alert_cause_6_wd = reg_wdata[0];
+ assign alert_cause_7_we = addr_hit[238] & reg_we & !reg_error;
+
+ assign alert_cause_7_wd = reg_wdata[0];
+ assign alert_cause_8_we = addr_hit[239] & reg_we & !reg_error;
+
+ assign alert_cause_8_wd = reg_wdata[0];
+ assign alert_cause_9_we = addr_hit[240] & reg_we & !reg_error;
+
+ assign alert_cause_9_wd = reg_wdata[0];
+ assign alert_cause_10_we = addr_hit[241] & reg_we & !reg_error;
+
+ assign alert_cause_10_wd = reg_wdata[0];
+ assign alert_cause_11_we = addr_hit[242] & reg_we & !reg_error;
+
+ assign alert_cause_11_wd = reg_wdata[0];
+ assign alert_cause_12_we = addr_hit[243] & reg_we & !reg_error;
+
+ assign alert_cause_12_wd = reg_wdata[0];
+ assign alert_cause_13_we = addr_hit[244] & reg_we & !reg_error;
+
+ assign alert_cause_13_wd = reg_wdata[0];
+ assign alert_cause_14_we = addr_hit[245] & reg_we & !reg_error;
+
+ assign alert_cause_14_wd = reg_wdata[0];
+ assign alert_cause_15_we = addr_hit[246] & reg_we & !reg_error;
+
+ assign alert_cause_15_wd = reg_wdata[0];
+ assign alert_cause_16_we = addr_hit[247] & reg_we & !reg_error;
+
+ assign alert_cause_16_wd = reg_wdata[0];
+ assign alert_cause_17_we = addr_hit[248] & reg_we & !reg_error;
+
+ assign alert_cause_17_wd = reg_wdata[0];
+ assign alert_cause_18_we = addr_hit[249] & reg_we & !reg_error;
+
+ assign alert_cause_18_wd = reg_wdata[0];
+ assign alert_cause_19_we = addr_hit[250] & reg_we & !reg_error;
+
+ assign alert_cause_19_wd = reg_wdata[0];
+ assign alert_cause_20_we = addr_hit[251] & reg_we & !reg_error;
+
+ assign alert_cause_20_wd = reg_wdata[0];
+ assign alert_cause_21_we = addr_hit[252] & reg_we & !reg_error;
+
+ assign alert_cause_21_wd = reg_wdata[0];
+ assign alert_cause_22_we = addr_hit[253] & reg_we & !reg_error;
+
+ assign alert_cause_22_wd = reg_wdata[0];
+ assign alert_cause_23_we = addr_hit[254] & reg_we & !reg_error;
+
+ assign alert_cause_23_wd = reg_wdata[0];
+ assign alert_cause_24_we = addr_hit[255] & reg_we & !reg_error;
+
+ assign alert_cause_24_wd = reg_wdata[0];
+ assign alert_cause_25_we = addr_hit[256] & reg_we & !reg_error;
+
+ assign alert_cause_25_wd = reg_wdata[0];
+ assign alert_cause_26_we = addr_hit[257] & reg_we & !reg_error;
+
+ assign alert_cause_26_wd = reg_wdata[0];
+ assign alert_cause_27_we = addr_hit[258] & reg_we & !reg_error;
+
+ assign alert_cause_27_wd = reg_wdata[0];
+ assign alert_cause_28_we = addr_hit[259] & reg_we & !reg_error;
+
+ assign alert_cause_28_wd = reg_wdata[0];
+ assign alert_cause_29_we = addr_hit[260] & reg_we & !reg_error;
+
+ assign alert_cause_29_wd = reg_wdata[0];
+ assign alert_cause_30_we = addr_hit[261] & reg_we & !reg_error;
+
+ assign alert_cause_30_wd = reg_wdata[0];
+ assign alert_cause_31_we = addr_hit[262] & reg_we & !reg_error;
+
+ assign alert_cause_31_wd = reg_wdata[0];
+ assign alert_cause_32_we = addr_hit[263] & reg_we & !reg_error;
+
+ assign alert_cause_32_wd = reg_wdata[0];
+ assign alert_cause_33_we = addr_hit[264] & reg_we & !reg_error;
+
+ assign alert_cause_33_wd = reg_wdata[0];
+ assign alert_cause_34_we = addr_hit[265] & reg_we & !reg_error;
+
+ assign alert_cause_34_wd = reg_wdata[0];
+ assign alert_cause_35_we = addr_hit[266] & reg_we & !reg_error;
+
+ assign alert_cause_35_wd = reg_wdata[0];
+ assign alert_cause_36_we = addr_hit[267] & reg_we & !reg_error;
+
+ assign alert_cause_36_wd = reg_wdata[0];
+ assign alert_cause_37_we = addr_hit[268] & reg_we & !reg_error;
+
+ assign alert_cause_37_wd = reg_wdata[0];
+ assign alert_cause_38_we = addr_hit[269] & reg_we & !reg_error;
+
+ assign alert_cause_38_wd = reg_wdata[0];
+ assign alert_cause_39_we = addr_hit[270] & reg_we & !reg_error;
+
+ assign alert_cause_39_wd = reg_wdata[0];
+ assign alert_cause_40_we = addr_hit[271] & reg_we & !reg_error;
+
+ assign alert_cause_40_wd = reg_wdata[0];
+ assign alert_cause_41_we = addr_hit[272] & reg_we & !reg_error;
+
+ assign alert_cause_41_wd = reg_wdata[0];
+ assign alert_cause_42_we = addr_hit[273] & reg_we & !reg_error;
+
+ assign alert_cause_42_wd = reg_wdata[0];
+ assign alert_cause_43_we = addr_hit[274] & reg_we & !reg_error;
+
+ assign alert_cause_43_wd = reg_wdata[0];
+ assign alert_cause_44_we = addr_hit[275] & reg_we & !reg_error;
+
+ assign alert_cause_44_wd = reg_wdata[0];
+ assign alert_cause_45_we = addr_hit[276] & reg_we & !reg_error;
+
+ assign alert_cause_45_wd = reg_wdata[0];
+ assign alert_cause_46_we = addr_hit[277] & reg_we & !reg_error;
+
+ assign alert_cause_46_wd = reg_wdata[0];
+ assign alert_cause_47_we = addr_hit[278] & reg_we & !reg_error;
+
+ assign alert_cause_47_wd = reg_wdata[0];
+ assign alert_cause_48_we = addr_hit[279] & reg_we & !reg_error;
+
+ assign alert_cause_48_wd = reg_wdata[0];
+ assign alert_cause_49_we = addr_hit[280] & reg_we & !reg_error;
+
+ assign alert_cause_49_wd = reg_wdata[0];
+ assign alert_cause_50_we = addr_hit[281] & reg_we & !reg_error;
+
+ assign alert_cause_50_wd = reg_wdata[0];
+ assign alert_cause_51_we = addr_hit[282] & reg_we & !reg_error;
+
+ assign alert_cause_51_wd = reg_wdata[0];
+ assign alert_cause_52_we = addr_hit[283] & reg_we & !reg_error;
+
+ assign alert_cause_52_wd = reg_wdata[0];
+ assign alert_cause_53_we = addr_hit[284] & reg_we & !reg_error;
+
+ assign alert_cause_53_wd = reg_wdata[0];
+ assign alert_cause_54_we = addr_hit[285] & reg_we & !reg_error;
+
+ assign alert_cause_54_wd = reg_wdata[0];
+ assign alert_cause_55_we = addr_hit[286] & reg_we & !reg_error;
+
+ assign alert_cause_55_wd = reg_wdata[0];
+ assign alert_cause_56_we = addr_hit[287] & reg_we & !reg_error;
+
+ assign alert_cause_56_wd = reg_wdata[0];
+ assign alert_cause_57_we = addr_hit[288] & reg_we & !reg_error;
+
+ assign alert_cause_57_wd = reg_wdata[0];
+ assign alert_cause_58_we = addr_hit[289] & reg_we & !reg_error;
+
+ assign alert_cause_58_wd = reg_wdata[0];
+ assign alert_cause_59_we = addr_hit[290] & reg_we & !reg_error;
+
+ assign alert_cause_59_wd = reg_wdata[0];
+ assign alert_cause_60_we = addr_hit[291] & reg_we & !reg_error;
+
+ assign alert_cause_60_wd = reg_wdata[0];
+ assign alert_cause_61_we = addr_hit[292] & reg_we & !reg_error;
+
+ assign alert_cause_61_wd = reg_wdata[0];
+ assign alert_cause_62_we = addr_hit[293] & reg_we & !reg_error;
+
+ assign alert_cause_62_wd = reg_wdata[0];
+ assign alert_cause_63_we = addr_hit[294] & reg_we & !reg_error;
+
+ assign alert_cause_63_wd = reg_wdata[0];
+ assign alert_cause_64_we = addr_hit[295] & reg_we & !reg_error;
+
+ assign alert_cause_64_wd = reg_wdata[0];
+ assign alert_cause_65_we = addr_hit[296] & reg_we & !reg_error;
+
+ assign alert_cause_65_wd = reg_wdata[0];
+ assign alert_cause_66_we = addr_hit[297] & reg_we & !reg_error;
+
+ assign alert_cause_66_wd = reg_wdata[0];
+ assign alert_cause_67_we = addr_hit[298] & reg_we & !reg_error;
+
+ assign alert_cause_67_wd = reg_wdata[0];
+ assign alert_cause_68_we = addr_hit[299] & reg_we & !reg_error;
+
+ assign alert_cause_68_wd = reg_wdata[0];
+ assign alert_cause_69_we = addr_hit[300] & reg_we & !reg_error;
+
+ assign alert_cause_69_wd = reg_wdata[0];
+ assign alert_cause_70_we = addr_hit[301] & reg_we & !reg_error;
+
+ assign alert_cause_70_wd = reg_wdata[0];
+ assign alert_cause_71_we = addr_hit[302] & reg_we & !reg_error;
+
+ assign alert_cause_71_wd = reg_wdata[0];
+ assign alert_cause_72_we = addr_hit[303] & reg_we & !reg_error;
+
+ assign alert_cause_72_wd = reg_wdata[0];
+ assign alert_cause_73_we = addr_hit[304] & reg_we & !reg_error;
+
+ assign alert_cause_73_wd = reg_wdata[0];
+ assign alert_cause_74_we = addr_hit[305] & reg_we & !reg_error;
+
+ assign alert_cause_74_wd = reg_wdata[0];
+ assign loc_alert_regwen_0_we = addr_hit[306] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_0_wd = reg_wdata[0];
+ assign loc_alert_regwen_1_we = addr_hit[307] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_1_wd = reg_wdata[0];
+ assign loc_alert_regwen_2_we = addr_hit[308] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_2_wd = reg_wdata[0];
+ assign loc_alert_regwen_3_we = addr_hit[309] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_3_wd = reg_wdata[0];
+ assign loc_alert_regwen_4_we = addr_hit[310] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_4_wd = reg_wdata[0];
+ assign loc_alert_regwen_5_we = addr_hit[311] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_5_wd = reg_wdata[0];
+ assign loc_alert_regwen_6_we = addr_hit[312] & reg_we & !reg_error;
+
+ assign loc_alert_regwen_6_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_0_re = addr_hit[313] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_0_we = addr_hit[313] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_1_re = addr_hit[314] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_1_we = addr_hit[314] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_2_re = addr_hit[315] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_2_we = addr_hit[315] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_3_re = addr_hit[316] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_3_we = addr_hit[316] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_4_re = addr_hit[317] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_4_we = addr_hit[317] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_5_re = addr_hit[318] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_5_we = addr_hit[318] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
+ assign loc_alert_en_shadowed_6_re = addr_hit[319] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_6_we = addr_hit[319] & reg_we & !reg_error;
+
+ assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
+ assign loc_alert_class_shadowed_0_re = addr_hit[320] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_0_we = addr_hit[320] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_1_re = addr_hit[321] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_1_we = addr_hit[321] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_2_re = addr_hit[322] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_2_we = addr_hit[322] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_3_re = addr_hit[323] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_3_we = addr_hit[323] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_4_re = addr_hit[324] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_4_we = addr_hit[324] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_5_re = addr_hit[325] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_5_we = addr_hit[325] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
+ assign loc_alert_class_shadowed_6_re = addr_hit[326] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_6_we = addr_hit[326] & reg_we & !reg_error;
+
+ assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
+ assign loc_alert_cause_0_we = addr_hit[327] & reg_we & !reg_error;
+
+ assign loc_alert_cause_0_wd = reg_wdata[0];
+ assign loc_alert_cause_1_we = addr_hit[328] & reg_we & !reg_error;
+
+ assign loc_alert_cause_1_wd = reg_wdata[0];
+ assign loc_alert_cause_2_we = addr_hit[329] & reg_we & !reg_error;
+
+ assign loc_alert_cause_2_wd = reg_wdata[0];
+ assign loc_alert_cause_3_we = addr_hit[330] & reg_we & !reg_error;
+
+ assign loc_alert_cause_3_wd = reg_wdata[0];
+ assign loc_alert_cause_4_we = addr_hit[331] & reg_we & !reg_error;
+
+ assign loc_alert_cause_4_wd = reg_wdata[0];
+ assign loc_alert_cause_5_we = addr_hit[332] & reg_we & !reg_error;
+
+ assign loc_alert_cause_5_wd = reg_wdata[0];
+ assign loc_alert_cause_6_we = addr_hit[333] & reg_we & !reg_error;
+
+ assign loc_alert_cause_6_wd = reg_wdata[0];
+ assign classa_regwen_we = addr_hit[334] & reg_we & !reg_error;
+
+ assign classa_regwen_wd = reg_wdata[0];
+ assign classa_ctrl_shadowed_re = addr_hit[335] & reg_re & !reg_error;
+ assign classa_ctrl_shadowed_we = addr_hit[335] & reg_we & !reg_error;
+
+ assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
+
+ assign classa_ctrl_shadowed_lock_wd = reg_wdata[1];
+
+ assign classa_ctrl_shadowed_en_e0_wd = reg_wdata[2];
+
+ assign classa_ctrl_shadowed_en_e1_wd = reg_wdata[3];
+
+ assign classa_ctrl_shadowed_en_e2_wd = reg_wdata[4];
+
+ assign classa_ctrl_shadowed_en_e3_wd = reg_wdata[5];
+
+ assign classa_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
+
+ assign classa_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
+
+ assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
+
+ assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
+ assign classa_clr_regwen_we = addr_hit[336] & reg_we & !reg_error;
+
+ assign classa_clr_regwen_wd = reg_wdata[0];
+ assign classa_clr_shadowed_re = addr_hit[337] & reg_re & !reg_error;
+ assign classa_clr_shadowed_we = addr_hit[337] & reg_we & !reg_error;
+
+ assign classa_clr_shadowed_wd = reg_wdata[0];
+ assign classa_accum_cnt_re = addr_hit[338] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_re = addr_hit[339] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_we = addr_hit[339] & reg_we & !reg_error;
+
+ assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
+ assign classa_timeout_cyc_shadowed_re = addr_hit[340] & reg_re & !reg_error;
+ assign classa_timeout_cyc_shadowed_we = addr_hit[340] & reg_we & !reg_error;
+
+ assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classa_crashdump_trigger_shadowed_re = addr_hit[341] & reg_re & !reg_error;
+ assign classa_crashdump_trigger_shadowed_we = addr_hit[341] & reg_we & !reg_error;
+
+ assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
+ assign classa_phase0_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error;
+ assign classa_phase0_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error;
+
+ assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classa_phase1_cyc_shadowed_re = addr_hit[343] & reg_re & !reg_error;
+ assign classa_phase1_cyc_shadowed_we = addr_hit[343] & reg_we & !reg_error;
+
+ assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classa_phase2_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error;
+ assign classa_phase2_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error;
+
+ assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classa_phase3_cyc_shadowed_re = addr_hit[345] & reg_re & !reg_error;
+ assign classa_phase3_cyc_shadowed_we = addr_hit[345] & reg_we & !reg_error;
+
+ assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classa_esc_cnt_re = addr_hit[346] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[347] & reg_re & !reg_error;
+ assign classb_regwen_we = addr_hit[348] & reg_we & !reg_error;
+
+ assign classb_regwen_wd = reg_wdata[0];
+ assign classb_ctrl_shadowed_re = addr_hit[349] & reg_re & !reg_error;
+ assign classb_ctrl_shadowed_we = addr_hit[349] & reg_we & !reg_error;
+
+ assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
+
+ assign classb_ctrl_shadowed_lock_wd = reg_wdata[1];
+
+ assign classb_ctrl_shadowed_en_e0_wd = reg_wdata[2];
+
+ assign classb_ctrl_shadowed_en_e1_wd = reg_wdata[3];
+
+ assign classb_ctrl_shadowed_en_e2_wd = reg_wdata[4];
+
+ assign classb_ctrl_shadowed_en_e3_wd = reg_wdata[5];
+
+ assign classb_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
+
+ assign classb_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
+
+ assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
+
+ assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
+ assign classb_clr_regwen_we = addr_hit[350] & reg_we & !reg_error;
+
+ assign classb_clr_regwen_wd = reg_wdata[0];
+ assign classb_clr_shadowed_re = addr_hit[351] & reg_re & !reg_error;
+ assign classb_clr_shadowed_we = addr_hit[351] & reg_we & !reg_error;
+
+ assign classb_clr_shadowed_wd = reg_wdata[0];
+ assign classb_accum_cnt_re = addr_hit[352] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_re = addr_hit[353] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_we = addr_hit[353] & reg_we & !reg_error;
+
+ assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
+ assign classb_timeout_cyc_shadowed_re = addr_hit[354] & reg_re & !reg_error;
+ assign classb_timeout_cyc_shadowed_we = addr_hit[354] & reg_we & !reg_error;
+
+ assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classb_crashdump_trigger_shadowed_re = addr_hit[355] & reg_re & !reg_error;
+ assign classb_crashdump_trigger_shadowed_we = addr_hit[355] & reg_we & !reg_error;
+
+ assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
+ assign classb_phase0_cyc_shadowed_re = addr_hit[356] & reg_re & !reg_error;
+ assign classb_phase0_cyc_shadowed_we = addr_hit[356] & reg_we & !reg_error;
+
+ assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classb_phase1_cyc_shadowed_re = addr_hit[357] & reg_re & !reg_error;
+ assign classb_phase1_cyc_shadowed_we = addr_hit[357] & reg_we & !reg_error;
+
+ assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classb_phase2_cyc_shadowed_re = addr_hit[358] & reg_re & !reg_error;
+ assign classb_phase2_cyc_shadowed_we = addr_hit[358] & reg_we & !reg_error;
+
+ assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classb_phase3_cyc_shadowed_re = addr_hit[359] & reg_re & !reg_error;
+ assign classb_phase3_cyc_shadowed_we = addr_hit[359] & reg_we & !reg_error;
+
+ assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classb_esc_cnt_re = addr_hit[360] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[361] & reg_re & !reg_error;
+ assign classc_regwen_we = addr_hit[362] & reg_we & !reg_error;
+
+ assign classc_regwen_wd = reg_wdata[0];
+ assign classc_ctrl_shadowed_re = addr_hit[363] & reg_re & !reg_error;
+ assign classc_ctrl_shadowed_we = addr_hit[363] & reg_we & !reg_error;
+
+ assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
+
+ assign classc_ctrl_shadowed_lock_wd = reg_wdata[1];
+
+ assign classc_ctrl_shadowed_en_e0_wd = reg_wdata[2];
+
+ assign classc_ctrl_shadowed_en_e1_wd = reg_wdata[3];
+
+ assign classc_ctrl_shadowed_en_e2_wd = reg_wdata[4];
+
+ assign classc_ctrl_shadowed_en_e3_wd = reg_wdata[5];
+
+ assign classc_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
+
+ assign classc_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
+
+ assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
+
+ assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
+ assign classc_clr_regwen_we = addr_hit[364] & reg_we & !reg_error;
+
+ assign classc_clr_regwen_wd = reg_wdata[0];
+ assign classc_clr_shadowed_re = addr_hit[365] & reg_re & !reg_error;
+ assign classc_clr_shadowed_we = addr_hit[365] & reg_we & !reg_error;
+
+ assign classc_clr_shadowed_wd = reg_wdata[0];
+ assign classc_accum_cnt_re = addr_hit[366] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_re = addr_hit[367] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_we = addr_hit[367] & reg_we & !reg_error;
+
+ assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
+ assign classc_timeout_cyc_shadowed_re = addr_hit[368] & reg_re & !reg_error;
+ assign classc_timeout_cyc_shadowed_we = addr_hit[368] & reg_we & !reg_error;
+
+ assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classc_crashdump_trigger_shadowed_re = addr_hit[369] & reg_re & !reg_error;
+ assign classc_crashdump_trigger_shadowed_we = addr_hit[369] & reg_we & !reg_error;
+
+ assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
+ assign classc_phase0_cyc_shadowed_re = addr_hit[370] & reg_re & !reg_error;
+ assign classc_phase0_cyc_shadowed_we = addr_hit[370] & reg_we & !reg_error;
+
+ assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classc_phase1_cyc_shadowed_re = addr_hit[371] & reg_re & !reg_error;
+ assign classc_phase1_cyc_shadowed_we = addr_hit[371] & reg_we & !reg_error;
+
+ assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classc_phase2_cyc_shadowed_re = addr_hit[372] & reg_re & !reg_error;
+ assign classc_phase2_cyc_shadowed_we = addr_hit[372] & reg_we & !reg_error;
+
+ assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classc_phase3_cyc_shadowed_re = addr_hit[373] & reg_re & !reg_error;
+ assign classc_phase3_cyc_shadowed_we = addr_hit[373] & reg_we & !reg_error;
+
+ assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classc_esc_cnt_re = addr_hit[374] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[375] & reg_re & !reg_error;
+ assign classd_regwen_we = addr_hit[376] & reg_we & !reg_error;
+
+ assign classd_regwen_wd = reg_wdata[0];
+ assign classd_ctrl_shadowed_re = addr_hit[377] & reg_re & !reg_error;
+ assign classd_ctrl_shadowed_we = addr_hit[377] & reg_we & !reg_error;
+
+ assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
+
+ assign classd_ctrl_shadowed_lock_wd = reg_wdata[1];
+
+ assign classd_ctrl_shadowed_en_e0_wd = reg_wdata[2];
+
+ assign classd_ctrl_shadowed_en_e1_wd = reg_wdata[3];
+
+ assign classd_ctrl_shadowed_en_e2_wd = reg_wdata[4];
+
+ assign classd_ctrl_shadowed_en_e3_wd = reg_wdata[5];
+
+ assign classd_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
+
+ assign classd_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
+
+ assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
+
+ assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
+ assign classd_clr_regwen_we = addr_hit[378] & reg_we & !reg_error;
+
+ assign classd_clr_regwen_wd = reg_wdata[0];
+ assign classd_clr_shadowed_re = addr_hit[379] & reg_re & !reg_error;
+ assign classd_clr_shadowed_we = addr_hit[379] & reg_we & !reg_error;
+
+ assign classd_clr_shadowed_wd = reg_wdata[0];
+ assign classd_accum_cnt_re = addr_hit[380] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_re = addr_hit[381] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_we = addr_hit[381] & reg_we & !reg_error;
+
+ assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
+ assign classd_timeout_cyc_shadowed_re = addr_hit[382] & reg_re & !reg_error;
+ assign classd_timeout_cyc_shadowed_we = addr_hit[382] & reg_we & !reg_error;
+
+ assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classd_crashdump_trigger_shadowed_re = addr_hit[383] & reg_re & !reg_error;
+ assign classd_crashdump_trigger_shadowed_we = addr_hit[383] & reg_we & !reg_error;
+
+ assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
+ assign classd_phase0_cyc_shadowed_re = addr_hit[384] & reg_re & !reg_error;
+ assign classd_phase0_cyc_shadowed_we = addr_hit[384] & reg_we & !reg_error;
+
+ assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classd_phase1_cyc_shadowed_re = addr_hit[385] & reg_re & !reg_error;
+ assign classd_phase1_cyc_shadowed_we = addr_hit[385] & reg_we & !reg_error;
+
+ assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classd_phase2_cyc_shadowed_re = addr_hit[386] & reg_re & !reg_error;
+ assign classd_phase2_cyc_shadowed_we = addr_hit[386] & reg_we & !reg_error;
+
+ assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classd_phase3_cyc_shadowed_re = addr_hit[387] & reg_re & !reg_error;
+ assign classd_phase3_cyc_shadowed_we = addr_hit[387] & reg_we & !reg_error;
+
+ assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
+ assign classd_esc_cnt_re = addr_hit[388] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[389] & reg_re & !reg_error;
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = intr_state_we;
+ reg_we_check[1] = intr_enable_we;
+ reg_we_check[2] = intr_test_we;
+ reg_we_check[3] = ping_timer_regwen_we;
+ reg_we_check[4] = ping_timeout_cyc_shadowed_gated_we;
+ reg_we_check[5] = ping_timer_en_shadowed_gated_we;
+ reg_we_check[6] = alert_regwen_0_we;
+ reg_we_check[7] = alert_regwen_1_we;
+ reg_we_check[8] = alert_regwen_2_we;
+ reg_we_check[9] = alert_regwen_3_we;
+ reg_we_check[10] = alert_regwen_4_we;
+ reg_we_check[11] = alert_regwen_5_we;
+ reg_we_check[12] = alert_regwen_6_we;
+ reg_we_check[13] = alert_regwen_7_we;
+ reg_we_check[14] = alert_regwen_8_we;
+ reg_we_check[15] = alert_regwen_9_we;
+ reg_we_check[16] = alert_regwen_10_we;
+ reg_we_check[17] = alert_regwen_11_we;
+ reg_we_check[18] = alert_regwen_12_we;
+ reg_we_check[19] = alert_regwen_13_we;
+ reg_we_check[20] = alert_regwen_14_we;
+ reg_we_check[21] = alert_regwen_15_we;
+ reg_we_check[22] = alert_regwen_16_we;
+ reg_we_check[23] = alert_regwen_17_we;
+ reg_we_check[24] = alert_regwen_18_we;
+ reg_we_check[25] = alert_regwen_19_we;
+ reg_we_check[26] = alert_regwen_20_we;
+ reg_we_check[27] = alert_regwen_21_we;
+ reg_we_check[28] = alert_regwen_22_we;
+ reg_we_check[29] = alert_regwen_23_we;
+ reg_we_check[30] = alert_regwen_24_we;
+ reg_we_check[31] = alert_regwen_25_we;
+ reg_we_check[32] = alert_regwen_26_we;
+ reg_we_check[33] = alert_regwen_27_we;
+ reg_we_check[34] = alert_regwen_28_we;
+ reg_we_check[35] = alert_regwen_29_we;
+ reg_we_check[36] = alert_regwen_30_we;
+ reg_we_check[37] = alert_regwen_31_we;
+ reg_we_check[38] = alert_regwen_32_we;
+ reg_we_check[39] = alert_regwen_33_we;
+ reg_we_check[40] = alert_regwen_34_we;
+ reg_we_check[41] = alert_regwen_35_we;
+ reg_we_check[42] = alert_regwen_36_we;
+ reg_we_check[43] = alert_regwen_37_we;
+ reg_we_check[44] = alert_regwen_38_we;
+ reg_we_check[45] = alert_regwen_39_we;
+ reg_we_check[46] = alert_regwen_40_we;
+ reg_we_check[47] = alert_regwen_41_we;
+ reg_we_check[48] = alert_regwen_42_we;
+ reg_we_check[49] = alert_regwen_43_we;
+ reg_we_check[50] = alert_regwen_44_we;
+ reg_we_check[51] = alert_regwen_45_we;
+ reg_we_check[52] = alert_regwen_46_we;
+ reg_we_check[53] = alert_regwen_47_we;
+ reg_we_check[54] = alert_regwen_48_we;
+ reg_we_check[55] = alert_regwen_49_we;
+ reg_we_check[56] = alert_regwen_50_we;
+ reg_we_check[57] = alert_regwen_51_we;
+ reg_we_check[58] = alert_regwen_52_we;
+ reg_we_check[59] = alert_regwen_53_we;
+ reg_we_check[60] = alert_regwen_54_we;
+ reg_we_check[61] = alert_regwen_55_we;
+ reg_we_check[62] = alert_regwen_56_we;
+ reg_we_check[63] = alert_regwen_57_we;
+ reg_we_check[64] = alert_regwen_58_we;
+ reg_we_check[65] = alert_regwen_59_we;
+ reg_we_check[66] = alert_regwen_60_we;
+ reg_we_check[67] = alert_regwen_61_we;
+ reg_we_check[68] = alert_regwen_62_we;
+ reg_we_check[69] = alert_regwen_63_we;
+ reg_we_check[70] = alert_regwen_64_we;
+ reg_we_check[71] = alert_regwen_65_we;
+ reg_we_check[72] = alert_regwen_66_we;
+ reg_we_check[73] = alert_regwen_67_we;
+ reg_we_check[74] = alert_regwen_68_we;
+ reg_we_check[75] = alert_regwen_69_we;
+ reg_we_check[76] = alert_regwen_70_we;
+ reg_we_check[77] = alert_regwen_71_we;
+ reg_we_check[78] = alert_regwen_72_we;
+ reg_we_check[79] = alert_regwen_73_we;
+ reg_we_check[80] = alert_regwen_74_we;
+ reg_we_check[81] = alert_en_shadowed_0_gated_we;
+ reg_we_check[82] = alert_en_shadowed_1_gated_we;
+ reg_we_check[83] = alert_en_shadowed_2_gated_we;
+ reg_we_check[84] = alert_en_shadowed_3_gated_we;
+ reg_we_check[85] = alert_en_shadowed_4_gated_we;
+ reg_we_check[86] = alert_en_shadowed_5_gated_we;
+ reg_we_check[87] = alert_en_shadowed_6_gated_we;
+ reg_we_check[88] = alert_en_shadowed_7_gated_we;
+ reg_we_check[89] = alert_en_shadowed_8_gated_we;
+ reg_we_check[90] = alert_en_shadowed_9_gated_we;
+ reg_we_check[91] = alert_en_shadowed_10_gated_we;
+ reg_we_check[92] = alert_en_shadowed_11_gated_we;
+ reg_we_check[93] = alert_en_shadowed_12_gated_we;
+ reg_we_check[94] = alert_en_shadowed_13_gated_we;
+ reg_we_check[95] = alert_en_shadowed_14_gated_we;
+ reg_we_check[96] = alert_en_shadowed_15_gated_we;
+ reg_we_check[97] = alert_en_shadowed_16_gated_we;
+ reg_we_check[98] = alert_en_shadowed_17_gated_we;
+ reg_we_check[99] = alert_en_shadowed_18_gated_we;
+ reg_we_check[100] = alert_en_shadowed_19_gated_we;
+ reg_we_check[101] = alert_en_shadowed_20_gated_we;
+ reg_we_check[102] = alert_en_shadowed_21_gated_we;
+ reg_we_check[103] = alert_en_shadowed_22_gated_we;
+ reg_we_check[104] = alert_en_shadowed_23_gated_we;
+ reg_we_check[105] = alert_en_shadowed_24_gated_we;
+ reg_we_check[106] = alert_en_shadowed_25_gated_we;
+ reg_we_check[107] = alert_en_shadowed_26_gated_we;
+ reg_we_check[108] = alert_en_shadowed_27_gated_we;
+ reg_we_check[109] = alert_en_shadowed_28_gated_we;
+ reg_we_check[110] = alert_en_shadowed_29_gated_we;
+ reg_we_check[111] = alert_en_shadowed_30_gated_we;
+ reg_we_check[112] = alert_en_shadowed_31_gated_we;
+ reg_we_check[113] = alert_en_shadowed_32_gated_we;
+ reg_we_check[114] = alert_en_shadowed_33_gated_we;
+ reg_we_check[115] = alert_en_shadowed_34_gated_we;
+ reg_we_check[116] = alert_en_shadowed_35_gated_we;
+ reg_we_check[117] = alert_en_shadowed_36_gated_we;
+ reg_we_check[118] = alert_en_shadowed_37_gated_we;
+ reg_we_check[119] = alert_en_shadowed_38_gated_we;
+ reg_we_check[120] = alert_en_shadowed_39_gated_we;
+ reg_we_check[121] = alert_en_shadowed_40_gated_we;
+ reg_we_check[122] = alert_en_shadowed_41_gated_we;
+ reg_we_check[123] = alert_en_shadowed_42_gated_we;
+ reg_we_check[124] = alert_en_shadowed_43_gated_we;
+ reg_we_check[125] = alert_en_shadowed_44_gated_we;
+ reg_we_check[126] = alert_en_shadowed_45_gated_we;
+ reg_we_check[127] = alert_en_shadowed_46_gated_we;
+ reg_we_check[128] = alert_en_shadowed_47_gated_we;
+ reg_we_check[129] = alert_en_shadowed_48_gated_we;
+ reg_we_check[130] = alert_en_shadowed_49_gated_we;
+ reg_we_check[131] = alert_en_shadowed_50_gated_we;
+ reg_we_check[132] = alert_en_shadowed_51_gated_we;
+ reg_we_check[133] = alert_en_shadowed_52_gated_we;
+ reg_we_check[134] = alert_en_shadowed_53_gated_we;
+ reg_we_check[135] = alert_en_shadowed_54_gated_we;
+ reg_we_check[136] = alert_en_shadowed_55_gated_we;
+ reg_we_check[137] = alert_en_shadowed_56_gated_we;
+ reg_we_check[138] = alert_en_shadowed_57_gated_we;
+ reg_we_check[139] = alert_en_shadowed_58_gated_we;
+ reg_we_check[140] = alert_en_shadowed_59_gated_we;
+ reg_we_check[141] = alert_en_shadowed_60_gated_we;
+ reg_we_check[142] = alert_en_shadowed_61_gated_we;
+ reg_we_check[143] = alert_en_shadowed_62_gated_we;
+ reg_we_check[144] = alert_en_shadowed_63_gated_we;
+ reg_we_check[145] = alert_en_shadowed_64_gated_we;
+ reg_we_check[146] = alert_en_shadowed_65_gated_we;
+ reg_we_check[147] = alert_en_shadowed_66_gated_we;
+ reg_we_check[148] = alert_en_shadowed_67_gated_we;
+ reg_we_check[149] = alert_en_shadowed_68_gated_we;
+ reg_we_check[150] = alert_en_shadowed_69_gated_we;
+ reg_we_check[151] = alert_en_shadowed_70_gated_we;
+ reg_we_check[152] = alert_en_shadowed_71_gated_we;
+ reg_we_check[153] = alert_en_shadowed_72_gated_we;
+ reg_we_check[154] = alert_en_shadowed_73_gated_we;
+ reg_we_check[155] = alert_en_shadowed_74_gated_we;
+ reg_we_check[156] = alert_class_shadowed_0_gated_we;
+ reg_we_check[157] = alert_class_shadowed_1_gated_we;
+ reg_we_check[158] = alert_class_shadowed_2_gated_we;
+ reg_we_check[159] = alert_class_shadowed_3_gated_we;
+ reg_we_check[160] = alert_class_shadowed_4_gated_we;
+ reg_we_check[161] = alert_class_shadowed_5_gated_we;
+ reg_we_check[162] = alert_class_shadowed_6_gated_we;
+ reg_we_check[163] = alert_class_shadowed_7_gated_we;
+ reg_we_check[164] = alert_class_shadowed_8_gated_we;
+ reg_we_check[165] = alert_class_shadowed_9_gated_we;
+ reg_we_check[166] = alert_class_shadowed_10_gated_we;
+ reg_we_check[167] = alert_class_shadowed_11_gated_we;
+ reg_we_check[168] = alert_class_shadowed_12_gated_we;
+ reg_we_check[169] = alert_class_shadowed_13_gated_we;
+ reg_we_check[170] = alert_class_shadowed_14_gated_we;
+ reg_we_check[171] = alert_class_shadowed_15_gated_we;
+ reg_we_check[172] = alert_class_shadowed_16_gated_we;
+ reg_we_check[173] = alert_class_shadowed_17_gated_we;
+ reg_we_check[174] = alert_class_shadowed_18_gated_we;
+ reg_we_check[175] = alert_class_shadowed_19_gated_we;
+ reg_we_check[176] = alert_class_shadowed_20_gated_we;
+ reg_we_check[177] = alert_class_shadowed_21_gated_we;
+ reg_we_check[178] = alert_class_shadowed_22_gated_we;
+ reg_we_check[179] = alert_class_shadowed_23_gated_we;
+ reg_we_check[180] = alert_class_shadowed_24_gated_we;
+ reg_we_check[181] = alert_class_shadowed_25_gated_we;
+ reg_we_check[182] = alert_class_shadowed_26_gated_we;
+ reg_we_check[183] = alert_class_shadowed_27_gated_we;
+ reg_we_check[184] = alert_class_shadowed_28_gated_we;
+ reg_we_check[185] = alert_class_shadowed_29_gated_we;
+ reg_we_check[186] = alert_class_shadowed_30_gated_we;
+ reg_we_check[187] = alert_class_shadowed_31_gated_we;
+ reg_we_check[188] = alert_class_shadowed_32_gated_we;
+ reg_we_check[189] = alert_class_shadowed_33_gated_we;
+ reg_we_check[190] = alert_class_shadowed_34_gated_we;
+ reg_we_check[191] = alert_class_shadowed_35_gated_we;
+ reg_we_check[192] = alert_class_shadowed_36_gated_we;
+ reg_we_check[193] = alert_class_shadowed_37_gated_we;
+ reg_we_check[194] = alert_class_shadowed_38_gated_we;
+ reg_we_check[195] = alert_class_shadowed_39_gated_we;
+ reg_we_check[196] = alert_class_shadowed_40_gated_we;
+ reg_we_check[197] = alert_class_shadowed_41_gated_we;
+ reg_we_check[198] = alert_class_shadowed_42_gated_we;
+ reg_we_check[199] = alert_class_shadowed_43_gated_we;
+ reg_we_check[200] = alert_class_shadowed_44_gated_we;
+ reg_we_check[201] = alert_class_shadowed_45_gated_we;
+ reg_we_check[202] = alert_class_shadowed_46_gated_we;
+ reg_we_check[203] = alert_class_shadowed_47_gated_we;
+ reg_we_check[204] = alert_class_shadowed_48_gated_we;
+ reg_we_check[205] = alert_class_shadowed_49_gated_we;
+ reg_we_check[206] = alert_class_shadowed_50_gated_we;
+ reg_we_check[207] = alert_class_shadowed_51_gated_we;
+ reg_we_check[208] = alert_class_shadowed_52_gated_we;
+ reg_we_check[209] = alert_class_shadowed_53_gated_we;
+ reg_we_check[210] = alert_class_shadowed_54_gated_we;
+ reg_we_check[211] = alert_class_shadowed_55_gated_we;
+ reg_we_check[212] = alert_class_shadowed_56_gated_we;
+ reg_we_check[213] = alert_class_shadowed_57_gated_we;
+ reg_we_check[214] = alert_class_shadowed_58_gated_we;
+ reg_we_check[215] = alert_class_shadowed_59_gated_we;
+ reg_we_check[216] = alert_class_shadowed_60_gated_we;
+ reg_we_check[217] = alert_class_shadowed_61_gated_we;
+ reg_we_check[218] = alert_class_shadowed_62_gated_we;
+ reg_we_check[219] = alert_class_shadowed_63_gated_we;
+ reg_we_check[220] = alert_class_shadowed_64_gated_we;
+ reg_we_check[221] = alert_class_shadowed_65_gated_we;
+ reg_we_check[222] = alert_class_shadowed_66_gated_we;
+ reg_we_check[223] = alert_class_shadowed_67_gated_we;
+ reg_we_check[224] = alert_class_shadowed_68_gated_we;
+ reg_we_check[225] = alert_class_shadowed_69_gated_we;
+ reg_we_check[226] = alert_class_shadowed_70_gated_we;
+ reg_we_check[227] = alert_class_shadowed_71_gated_we;
+ reg_we_check[228] = alert_class_shadowed_72_gated_we;
+ reg_we_check[229] = alert_class_shadowed_73_gated_we;
+ reg_we_check[230] = alert_class_shadowed_74_gated_we;
+ reg_we_check[231] = alert_cause_0_we;
+ reg_we_check[232] = alert_cause_1_we;
+ reg_we_check[233] = alert_cause_2_we;
+ reg_we_check[234] = alert_cause_3_we;
+ reg_we_check[235] = alert_cause_4_we;
+ reg_we_check[236] = alert_cause_5_we;
+ reg_we_check[237] = alert_cause_6_we;
+ reg_we_check[238] = alert_cause_7_we;
+ reg_we_check[239] = alert_cause_8_we;
+ reg_we_check[240] = alert_cause_9_we;
+ reg_we_check[241] = alert_cause_10_we;
+ reg_we_check[242] = alert_cause_11_we;
+ reg_we_check[243] = alert_cause_12_we;
+ reg_we_check[244] = alert_cause_13_we;
+ reg_we_check[245] = alert_cause_14_we;
+ reg_we_check[246] = alert_cause_15_we;
+ reg_we_check[247] = alert_cause_16_we;
+ reg_we_check[248] = alert_cause_17_we;
+ reg_we_check[249] = alert_cause_18_we;
+ reg_we_check[250] = alert_cause_19_we;
+ reg_we_check[251] = alert_cause_20_we;
+ reg_we_check[252] = alert_cause_21_we;
+ reg_we_check[253] = alert_cause_22_we;
+ reg_we_check[254] = alert_cause_23_we;
+ reg_we_check[255] = alert_cause_24_we;
+ reg_we_check[256] = alert_cause_25_we;
+ reg_we_check[257] = alert_cause_26_we;
+ reg_we_check[258] = alert_cause_27_we;
+ reg_we_check[259] = alert_cause_28_we;
+ reg_we_check[260] = alert_cause_29_we;
+ reg_we_check[261] = alert_cause_30_we;
+ reg_we_check[262] = alert_cause_31_we;
+ reg_we_check[263] = alert_cause_32_we;
+ reg_we_check[264] = alert_cause_33_we;
+ reg_we_check[265] = alert_cause_34_we;
+ reg_we_check[266] = alert_cause_35_we;
+ reg_we_check[267] = alert_cause_36_we;
+ reg_we_check[268] = alert_cause_37_we;
+ reg_we_check[269] = alert_cause_38_we;
+ reg_we_check[270] = alert_cause_39_we;
+ reg_we_check[271] = alert_cause_40_we;
+ reg_we_check[272] = alert_cause_41_we;
+ reg_we_check[273] = alert_cause_42_we;
+ reg_we_check[274] = alert_cause_43_we;
+ reg_we_check[275] = alert_cause_44_we;
+ reg_we_check[276] = alert_cause_45_we;
+ reg_we_check[277] = alert_cause_46_we;
+ reg_we_check[278] = alert_cause_47_we;
+ reg_we_check[279] = alert_cause_48_we;
+ reg_we_check[280] = alert_cause_49_we;
+ reg_we_check[281] = alert_cause_50_we;
+ reg_we_check[282] = alert_cause_51_we;
+ reg_we_check[283] = alert_cause_52_we;
+ reg_we_check[284] = alert_cause_53_we;
+ reg_we_check[285] = alert_cause_54_we;
+ reg_we_check[286] = alert_cause_55_we;
+ reg_we_check[287] = alert_cause_56_we;
+ reg_we_check[288] = alert_cause_57_we;
+ reg_we_check[289] = alert_cause_58_we;
+ reg_we_check[290] = alert_cause_59_we;
+ reg_we_check[291] = alert_cause_60_we;
+ reg_we_check[292] = alert_cause_61_we;
+ reg_we_check[293] = alert_cause_62_we;
+ reg_we_check[294] = alert_cause_63_we;
+ reg_we_check[295] = alert_cause_64_we;
+ reg_we_check[296] = alert_cause_65_we;
+ reg_we_check[297] = alert_cause_66_we;
+ reg_we_check[298] = alert_cause_67_we;
+ reg_we_check[299] = alert_cause_68_we;
+ reg_we_check[300] = alert_cause_69_we;
+ reg_we_check[301] = alert_cause_70_we;
+ reg_we_check[302] = alert_cause_71_we;
+ reg_we_check[303] = alert_cause_72_we;
+ reg_we_check[304] = alert_cause_73_we;
+ reg_we_check[305] = alert_cause_74_we;
+ reg_we_check[306] = loc_alert_regwen_0_we;
+ reg_we_check[307] = loc_alert_regwen_1_we;
+ reg_we_check[308] = loc_alert_regwen_2_we;
+ reg_we_check[309] = loc_alert_regwen_3_we;
+ reg_we_check[310] = loc_alert_regwen_4_we;
+ reg_we_check[311] = loc_alert_regwen_5_we;
+ reg_we_check[312] = loc_alert_regwen_6_we;
+ reg_we_check[313] = loc_alert_en_shadowed_0_gated_we;
+ reg_we_check[314] = loc_alert_en_shadowed_1_gated_we;
+ reg_we_check[315] = loc_alert_en_shadowed_2_gated_we;
+ reg_we_check[316] = loc_alert_en_shadowed_3_gated_we;
+ reg_we_check[317] = loc_alert_en_shadowed_4_gated_we;
+ reg_we_check[318] = loc_alert_en_shadowed_5_gated_we;
+ reg_we_check[319] = loc_alert_en_shadowed_6_gated_we;
+ reg_we_check[320] = loc_alert_class_shadowed_0_gated_we;
+ reg_we_check[321] = loc_alert_class_shadowed_1_gated_we;
+ reg_we_check[322] = loc_alert_class_shadowed_2_gated_we;
+ reg_we_check[323] = loc_alert_class_shadowed_3_gated_we;
+ reg_we_check[324] = loc_alert_class_shadowed_4_gated_we;
+ reg_we_check[325] = loc_alert_class_shadowed_5_gated_we;
+ reg_we_check[326] = loc_alert_class_shadowed_6_gated_we;
+ reg_we_check[327] = loc_alert_cause_0_we;
+ reg_we_check[328] = loc_alert_cause_1_we;
+ reg_we_check[329] = loc_alert_cause_2_we;
+ reg_we_check[330] = loc_alert_cause_3_we;
+ reg_we_check[331] = loc_alert_cause_4_we;
+ reg_we_check[332] = loc_alert_cause_5_we;
+ reg_we_check[333] = loc_alert_cause_6_we;
+ reg_we_check[334] = classa_regwen_we;
+ reg_we_check[335] = classa_ctrl_shadowed_gated_we;
+ reg_we_check[336] = classa_clr_regwen_we;
+ reg_we_check[337] = classa_clr_shadowed_gated_we;
+ reg_we_check[338] = 1'b0;
+ reg_we_check[339] = classa_accum_thresh_shadowed_gated_we;
+ reg_we_check[340] = classa_timeout_cyc_shadowed_gated_we;
+ reg_we_check[341] = classa_crashdump_trigger_shadowed_gated_we;
+ reg_we_check[342] = classa_phase0_cyc_shadowed_gated_we;
+ reg_we_check[343] = classa_phase1_cyc_shadowed_gated_we;
+ reg_we_check[344] = classa_phase2_cyc_shadowed_gated_we;
+ reg_we_check[345] = classa_phase3_cyc_shadowed_gated_we;
+ reg_we_check[346] = 1'b0;
+ reg_we_check[347] = 1'b0;
+ reg_we_check[348] = classb_regwen_we;
+ reg_we_check[349] = classb_ctrl_shadowed_gated_we;
+ reg_we_check[350] = classb_clr_regwen_we;
+ reg_we_check[351] = classb_clr_shadowed_gated_we;
+ reg_we_check[352] = 1'b0;
+ reg_we_check[353] = classb_accum_thresh_shadowed_gated_we;
+ reg_we_check[354] = classb_timeout_cyc_shadowed_gated_we;
+ reg_we_check[355] = classb_crashdump_trigger_shadowed_gated_we;
+ reg_we_check[356] = classb_phase0_cyc_shadowed_gated_we;
+ reg_we_check[357] = classb_phase1_cyc_shadowed_gated_we;
+ reg_we_check[358] = classb_phase2_cyc_shadowed_gated_we;
+ reg_we_check[359] = classb_phase3_cyc_shadowed_gated_we;
+ reg_we_check[360] = 1'b0;
+ reg_we_check[361] = 1'b0;
+ reg_we_check[362] = classc_regwen_we;
+ reg_we_check[363] = classc_ctrl_shadowed_gated_we;
+ reg_we_check[364] = classc_clr_regwen_we;
+ reg_we_check[365] = classc_clr_shadowed_gated_we;
+ reg_we_check[366] = 1'b0;
+ reg_we_check[367] = classc_accum_thresh_shadowed_gated_we;
+ reg_we_check[368] = classc_timeout_cyc_shadowed_gated_we;
+ reg_we_check[369] = classc_crashdump_trigger_shadowed_gated_we;
+ reg_we_check[370] = classc_phase0_cyc_shadowed_gated_we;
+ reg_we_check[371] = classc_phase1_cyc_shadowed_gated_we;
+ reg_we_check[372] = classc_phase2_cyc_shadowed_gated_we;
+ reg_we_check[373] = classc_phase3_cyc_shadowed_gated_we;
+ reg_we_check[374] = 1'b0;
+ reg_we_check[375] = 1'b0;
+ reg_we_check[376] = classd_regwen_we;
+ reg_we_check[377] = classd_ctrl_shadowed_gated_we;
+ reg_we_check[378] = classd_clr_regwen_we;
+ reg_we_check[379] = classd_clr_shadowed_gated_we;
+ reg_we_check[380] = 1'b0;
+ reg_we_check[381] = classd_accum_thresh_shadowed_gated_we;
+ reg_we_check[382] = classd_timeout_cyc_shadowed_gated_we;
+ reg_we_check[383] = classd_crashdump_trigger_shadowed_gated_we;
+ reg_we_check[384] = classd_phase0_cyc_shadowed_gated_we;
+ reg_we_check[385] = classd_phase1_cyc_shadowed_gated_we;
+ reg_we_check[386] = classd_phase2_cyc_shadowed_gated_we;
+ reg_we_check[387] = classd_phase3_cyc_shadowed_gated_we;
+ reg_we_check[388] = 1'b0;
+ reg_we_check[389] = 1'b0;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_classa_qs;
+ reg_rdata_next[1] = intr_state_classb_qs;
+ reg_rdata_next[2] = intr_state_classc_qs;
+ reg_rdata_next[3] = intr_state_classd_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_classa_qs;
+ reg_rdata_next[1] = intr_enable_classb_qs;
+ reg_rdata_next[2] = intr_enable_classc_qs;
+ reg_rdata_next[3] = intr_enable_classd_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = ping_timer_regwen_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[15:0] = ping_timeout_cyc_shadowed_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = ping_timer_en_shadowed_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[0] = alert_regwen_0_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = alert_regwen_1_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = alert_regwen_2_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[0] = alert_regwen_3_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = alert_regwen_4_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = alert_regwen_5_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = alert_regwen_6_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = alert_regwen_7_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[0] = alert_regwen_8_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[0] = alert_regwen_9_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[0] = alert_regwen_10_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[0] = alert_regwen_11_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[0] = alert_regwen_12_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[0] = alert_regwen_13_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[0] = alert_regwen_14_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[0] = alert_regwen_15_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[0] = alert_regwen_16_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[0] = alert_regwen_17_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[0] = alert_regwen_18_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[0] = alert_regwen_19_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[0] = alert_regwen_20_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[0] = alert_regwen_21_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[0] = alert_regwen_22_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[0] = alert_regwen_23_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[0] = alert_regwen_24_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[0] = alert_regwen_25_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[0] = alert_regwen_26_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[0] = alert_regwen_27_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[0] = alert_regwen_28_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[0] = alert_regwen_29_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[0] = alert_regwen_30_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = alert_regwen_31_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[0] = alert_regwen_32_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[0] = alert_regwen_33_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[0] = alert_regwen_34_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[0] = alert_regwen_35_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[0] = alert_regwen_36_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[0] = alert_regwen_37_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[0] = alert_regwen_38_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[0] = alert_regwen_39_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[0] = alert_regwen_40_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[0] = alert_regwen_41_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[0] = alert_regwen_42_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[0] = alert_regwen_43_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[0] = alert_regwen_44_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[0] = alert_regwen_45_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[0] = alert_regwen_46_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[0] = alert_regwen_47_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[0] = alert_regwen_48_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[0] = alert_regwen_49_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[0] = alert_regwen_50_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[0] = alert_regwen_51_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[0] = alert_regwen_52_qs;
+ end
+
+ addr_hit[59]: begin
+ reg_rdata_next[0] = alert_regwen_53_qs;
+ end
+
+ addr_hit[60]: begin
+ reg_rdata_next[0] = alert_regwen_54_qs;
+ end
+
+ addr_hit[61]: begin
+ reg_rdata_next[0] = alert_regwen_55_qs;
+ end
+
+ addr_hit[62]: begin
+ reg_rdata_next[0] = alert_regwen_56_qs;
+ end
+
+ addr_hit[63]: begin
+ reg_rdata_next[0] = alert_regwen_57_qs;
+ end
+
+ addr_hit[64]: begin
+ reg_rdata_next[0] = alert_regwen_58_qs;
+ end
+
+ addr_hit[65]: begin
+ reg_rdata_next[0] = alert_regwen_59_qs;
+ end
+
+ addr_hit[66]: begin
+ reg_rdata_next[0] = alert_regwen_60_qs;
+ end
+
+ addr_hit[67]: begin
+ reg_rdata_next[0] = alert_regwen_61_qs;
+ end
+
+ addr_hit[68]: begin
+ reg_rdata_next[0] = alert_regwen_62_qs;
+ end
+
+ addr_hit[69]: begin
+ reg_rdata_next[0] = alert_regwen_63_qs;
+ end
+
+ addr_hit[70]: begin
+ reg_rdata_next[0] = alert_regwen_64_qs;
+ end
+
+ addr_hit[71]: begin
+ reg_rdata_next[0] = alert_regwen_65_qs;
+ end
+
+ addr_hit[72]: begin
+ reg_rdata_next[0] = alert_regwen_66_qs;
+ end
+
+ addr_hit[73]: begin
+ reg_rdata_next[0] = alert_regwen_67_qs;
+ end
+
+ addr_hit[74]: begin
+ reg_rdata_next[0] = alert_regwen_68_qs;
+ end
+
+ addr_hit[75]: begin
+ reg_rdata_next[0] = alert_regwen_69_qs;
+ end
+
+ addr_hit[76]: begin
+ reg_rdata_next[0] = alert_regwen_70_qs;
+ end
+
+ addr_hit[77]: begin
+ reg_rdata_next[0] = alert_regwen_71_qs;
+ end
+
+ addr_hit[78]: begin
+ reg_rdata_next[0] = alert_regwen_72_qs;
+ end
+
+ addr_hit[79]: begin
+ reg_rdata_next[0] = alert_regwen_73_qs;
+ end
+
+ addr_hit[80]: begin
+ reg_rdata_next[0] = alert_regwen_74_qs;
+ end
+
+ addr_hit[81]: begin
+ reg_rdata_next[0] = alert_en_shadowed_0_qs;
+ end
+
+ addr_hit[82]: begin
+ reg_rdata_next[0] = alert_en_shadowed_1_qs;
+ end
+
+ addr_hit[83]: begin
+ reg_rdata_next[0] = alert_en_shadowed_2_qs;
+ end
+
+ addr_hit[84]: begin
+ reg_rdata_next[0] = alert_en_shadowed_3_qs;
+ end
+
+ addr_hit[85]: begin
+ reg_rdata_next[0] = alert_en_shadowed_4_qs;
+ end
+
+ addr_hit[86]: begin
+ reg_rdata_next[0] = alert_en_shadowed_5_qs;
+ end
+
+ addr_hit[87]: begin
+ reg_rdata_next[0] = alert_en_shadowed_6_qs;
+ end
+
+ addr_hit[88]: begin
+ reg_rdata_next[0] = alert_en_shadowed_7_qs;
+ end
+
+ addr_hit[89]: begin
+ reg_rdata_next[0] = alert_en_shadowed_8_qs;
+ end
+
+ addr_hit[90]: begin
+ reg_rdata_next[0] = alert_en_shadowed_9_qs;
+ end
+
+ addr_hit[91]: begin
+ reg_rdata_next[0] = alert_en_shadowed_10_qs;
+ end
+
+ addr_hit[92]: begin
+ reg_rdata_next[0] = alert_en_shadowed_11_qs;
+ end
+
+ addr_hit[93]: begin
+ reg_rdata_next[0] = alert_en_shadowed_12_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[0] = alert_en_shadowed_13_qs;
+ end
+
+ addr_hit[95]: begin
+ reg_rdata_next[0] = alert_en_shadowed_14_qs;
+ end
+
+ addr_hit[96]: begin
+ reg_rdata_next[0] = alert_en_shadowed_15_qs;
+ end
+
+ addr_hit[97]: begin
+ reg_rdata_next[0] = alert_en_shadowed_16_qs;
+ end
+
+ addr_hit[98]: begin
+ reg_rdata_next[0] = alert_en_shadowed_17_qs;
+ end
+
+ addr_hit[99]: begin
+ reg_rdata_next[0] = alert_en_shadowed_18_qs;
+ end
+
+ addr_hit[100]: begin
+ reg_rdata_next[0] = alert_en_shadowed_19_qs;
+ end
+
+ addr_hit[101]: begin
+ reg_rdata_next[0] = alert_en_shadowed_20_qs;
+ end
+
+ addr_hit[102]: begin
+ reg_rdata_next[0] = alert_en_shadowed_21_qs;
+ end
+
+ addr_hit[103]: begin
+ reg_rdata_next[0] = alert_en_shadowed_22_qs;
+ end
+
+ addr_hit[104]: begin
+ reg_rdata_next[0] = alert_en_shadowed_23_qs;
+ end
+
+ addr_hit[105]: begin
+ reg_rdata_next[0] = alert_en_shadowed_24_qs;
+ end
+
+ addr_hit[106]: begin
+ reg_rdata_next[0] = alert_en_shadowed_25_qs;
+ end
+
+ addr_hit[107]: begin
+ reg_rdata_next[0] = alert_en_shadowed_26_qs;
+ end
+
+ addr_hit[108]: begin
+ reg_rdata_next[0] = alert_en_shadowed_27_qs;
+ end
+
+ addr_hit[109]: begin
+ reg_rdata_next[0] = alert_en_shadowed_28_qs;
+ end
+
+ addr_hit[110]: begin
+ reg_rdata_next[0] = alert_en_shadowed_29_qs;
+ end
+
+ addr_hit[111]: begin
+ reg_rdata_next[0] = alert_en_shadowed_30_qs;
+ end
+
+ addr_hit[112]: begin
+ reg_rdata_next[0] = alert_en_shadowed_31_qs;
+ end
+
+ addr_hit[113]: begin
+ reg_rdata_next[0] = alert_en_shadowed_32_qs;
+ end
+
+ addr_hit[114]: begin
+ reg_rdata_next[0] = alert_en_shadowed_33_qs;
+ end
+
+ addr_hit[115]: begin
+ reg_rdata_next[0] = alert_en_shadowed_34_qs;
+ end
+
+ addr_hit[116]: begin
+ reg_rdata_next[0] = alert_en_shadowed_35_qs;
+ end
+
+ addr_hit[117]: begin
+ reg_rdata_next[0] = alert_en_shadowed_36_qs;
+ end
+
+ addr_hit[118]: begin
+ reg_rdata_next[0] = alert_en_shadowed_37_qs;
+ end
+
+ addr_hit[119]: begin
+ reg_rdata_next[0] = alert_en_shadowed_38_qs;
+ end
+
+ addr_hit[120]: begin
+ reg_rdata_next[0] = alert_en_shadowed_39_qs;
+ end
+
+ addr_hit[121]: begin
+ reg_rdata_next[0] = alert_en_shadowed_40_qs;
+ end
+
+ addr_hit[122]: begin
+ reg_rdata_next[0] = alert_en_shadowed_41_qs;
+ end
+
+ addr_hit[123]: begin
+ reg_rdata_next[0] = alert_en_shadowed_42_qs;
+ end
+
+ addr_hit[124]: begin
+ reg_rdata_next[0] = alert_en_shadowed_43_qs;
+ end
+
+ addr_hit[125]: begin
+ reg_rdata_next[0] = alert_en_shadowed_44_qs;
+ end
+
+ addr_hit[126]: begin
+ reg_rdata_next[0] = alert_en_shadowed_45_qs;
+ end
+
+ addr_hit[127]: begin
+ reg_rdata_next[0] = alert_en_shadowed_46_qs;
+ end
+
+ addr_hit[128]: begin
+ reg_rdata_next[0] = alert_en_shadowed_47_qs;
+ end
+
+ addr_hit[129]: begin
+ reg_rdata_next[0] = alert_en_shadowed_48_qs;
+ end
+
+ addr_hit[130]: begin
+ reg_rdata_next[0] = alert_en_shadowed_49_qs;
+ end
+
+ addr_hit[131]: begin
+ reg_rdata_next[0] = alert_en_shadowed_50_qs;
+ end
+
+ addr_hit[132]: begin
+ reg_rdata_next[0] = alert_en_shadowed_51_qs;
+ end
+
+ addr_hit[133]: begin
+ reg_rdata_next[0] = alert_en_shadowed_52_qs;
+ end
+
+ addr_hit[134]: begin
+ reg_rdata_next[0] = alert_en_shadowed_53_qs;
+ end
+
+ addr_hit[135]: begin
+ reg_rdata_next[0] = alert_en_shadowed_54_qs;
+ end
+
+ addr_hit[136]: begin
+ reg_rdata_next[0] = alert_en_shadowed_55_qs;
+ end
+
+ addr_hit[137]: begin
+ reg_rdata_next[0] = alert_en_shadowed_56_qs;
+ end
+
+ addr_hit[138]: begin
+ reg_rdata_next[0] = alert_en_shadowed_57_qs;
+ end
+
+ addr_hit[139]: begin
+ reg_rdata_next[0] = alert_en_shadowed_58_qs;
+ end
+
+ addr_hit[140]: begin
+ reg_rdata_next[0] = alert_en_shadowed_59_qs;
+ end
+
+ addr_hit[141]: begin
+ reg_rdata_next[0] = alert_en_shadowed_60_qs;
+ end
+
+ addr_hit[142]: begin
+ reg_rdata_next[0] = alert_en_shadowed_61_qs;
+ end
+
+ addr_hit[143]: begin
+ reg_rdata_next[0] = alert_en_shadowed_62_qs;
+ end
+
+ addr_hit[144]: begin
+ reg_rdata_next[0] = alert_en_shadowed_63_qs;
+ end
+
+ addr_hit[145]: begin
+ reg_rdata_next[0] = alert_en_shadowed_64_qs;
+ end
+
+ addr_hit[146]: begin
+ reg_rdata_next[0] = alert_en_shadowed_65_qs;
+ end
+
+ addr_hit[147]: begin
+ reg_rdata_next[0] = alert_en_shadowed_66_qs;
+ end
+
+ addr_hit[148]: begin
+ reg_rdata_next[0] = alert_en_shadowed_67_qs;
+ end
+
+ addr_hit[149]: begin
+ reg_rdata_next[0] = alert_en_shadowed_68_qs;
+ end
+
+ addr_hit[150]: begin
+ reg_rdata_next[0] = alert_en_shadowed_69_qs;
+ end
+
+ addr_hit[151]: begin
+ reg_rdata_next[0] = alert_en_shadowed_70_qs;
+ end
+
+ addr_hit[152]: begin
+ reg_rdata_next[0] = alert_en_shadowed_71_qs;
+ end
+
+ addr_hit[153]: begin
+ reg_rdata_next[0] = alert_en_shadowed_72_qs;
+ end
+
+ addr_hit[154]: begin
+ reg_rdata_next[0] = alert_en_shadowed_73_qs;
+ end
+
+ addr_hit[155]: begin
+ reg_rdata_next[0] = alert_en_shadowed_74_qs;
+ end
+
+ addr_hit[156]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
+ end
+
+ addr_hit[157]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
+ end
+
+ addr_hit[158]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
+ end
+
+ addr_hit[159]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
+ end
+
+ addr_hit[160]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
+ end
+
+ addr_hit[161]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
+ end
+
+ addr_hit[162]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
+ end
+
+ addr_hit[163]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
+ end
+
+ addr_hit[164]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
+ end
+
+ addr_hit[165]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
+ end
+
+ addr_hit[166]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
+ end
+
+ addr_hit[167]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
+ end
+
+ addr_hit[168]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
+ end
+
+ addr_hit[169]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
+ end
+
+ addr_hit[170]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
+ end
+
+ addr_hit[171]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
+ end
+
+ addr_hit[172]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
+ end
+
+ addr_hit[173]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
+ end
+
+ addr_hit[174]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
+ end
+
+ addr_hit[175]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
+ end
+
+ addr_hit[176]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
+ end
+
+ addr_hit[177]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
+ end
+
+ addr_hit[178]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
+ end
+
+ addr_hit[179]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
+ end
+
+ addr_hit[180]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
+ end
+
+ addr_hit[181]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
+ end
+
+ addr_hit[182]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
+ end
+
+ addr_hit[183]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
+ end
+
+ addr_hit[184]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
+ end
+
+ addr_hit[185]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
+ end
+
+ addr_hit[186]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
+ end
+
+ addr_hit[187]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
+ end
+
+ addr_hit[188]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
+ end
+
+ addr_hit[189]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
+ end
+
+ addr_hit[190]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
+ end
+
+ addr_hit[191]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
+ end
+
+ addr_hit[192]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
+ end
+
+ addr_hit[193]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
+ end
+
+ addr_hit[194]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
+ end
+
+ addr_hit[195]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
+ end
+
+ addr_hit[196]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
+ end
+
+ addr_hit[197]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
+ end
+
+ addr_hit[198]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
+ end
+
+ addr_hit[199]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
+ end
+
+ addr_hit[200]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
+ end
+
+ addr_hit[201]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
+ end
+
+ addr_hit[202]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
+ end
+
+ addr_hit[203]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
+ end
+
+ addr_hit[204]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
+ end
+
+ addr_hit[205]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
+ end
+
+ addr_hit[206]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
+ end
+
+ addr_hit[207]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
+ end
+
+ addr_hit[208]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
+ end
+
+ addr_hit[209]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
+ end
+
+ addr_hit[210]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
+ end
+
+ addr_hit[211]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
+ end
+
+ addr_hit[212]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
+ end
+
+ addr_hit[213]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
+ end
+
+ addr_hit[214]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
+ end
+
+ addr_hit[215]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
+ end
+
+ addr_hit[216]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_60_qs;
+ end
+
+ addr_hit[217]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_61_qs;
+ end
+
+ addr_hit[218]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_62_qs;
+ end
+
+ addr_hit[219]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_63_qs;
+ end
+
+ addr_hit[220]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_64_qs;
+ end
+
+ addr_hit[221]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_65_qs;
+ end
+
+ addr_hit[222]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_66_qs;
+ end
+
+ addr_hit[223]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_67_qs;
+ end
+
+ addr_hit[224]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_68_qs;
+ end
+
+ addr_hit[225]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_69_qs;
+ end
+
+ addr_hit[226]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_70_qs;
+ end
+
+ addr_hit[227]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_71_qs;
+ end
+
+ addr_hit[228]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_72_qs;
+ end
+
+ addr_hit[229]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_73_qs;
+ end
+
+ addr_hit[230]: begin
+ reg_rdata_next[1:0] = alert_class_shadowed_74_qs;
+ end
+
+ addr_hit[231]: begin
+ reg_rdata_next[0] = alert_cause_0_qs;
+ end
+
+ addr_hit[232]: begin
+ reg_rdata_next[0] = alert_cause_1_qs;
+ end
+
+ addr_hit[233]: begin
+ reg_rdata_next[0] = alert_cause_2_qs;
+ end
+
+ addr_hit[234]: begin
+ reg_rdata_next[0] = alert_cause_3_qs;
+ end
+
+ addr_hit[235]: begin
+ reg_rdata_next[0] = alert_cause_4_qs;
+ end
+
+ addr_hit[236]: begin
+ reg_rdata_next[0] = alert_cause_5_qs;
+ end
+
+ addr_hit[237]: begin
+ reg_rdata_next[0] = alert_cause_6_qs;
+ end
+
+ addr_hit[238]: begin
+ reg_rdata_next[0] = alert_cause_7_qs;
+ end
+
+ addr_hit[239]: begin
+ reg_rdata_next[0] = alert_cause_8_qs;
+ end
+
+ addr_hit[240]: begin
+ reg_rdata_next[0] = alert_cause_9_qs;
+ end
+
+ addr_hit[241]: begin
+ reg_rdata_next[0] = alert_cause_10_qs;
+ end
+
+ addr_hit[242]: begin
+ reg_rdata_next[0] = alert_cause_11_qs;
+ end
+
+ addr_hit[243]: begin
+ reg_rdata_next[0] = alert_cause_12_qs;
+ end
+
+ addr_hit[244]: begin
+ reg_rdata_next[0] = alert_cause_13_qs;
+ end
+
+ addr_hit[245]: begin
+ reg_rdata_next[0] = alert_cause_14_qs;
+ end
+
+ addr_hit[246]: begin
+ reg_rdata_next[0] = alert_cause_15_qs;
+ end
+
+ addr_hit[247]: begin
+ reg_rdata_next[0] = alert_cause_16_qs;
+ end
+
+ addr_hit[248]: begin
+ reg_rdata_next[0] = alert_cause_17_qs;
+ end
+
+ addr_hit[249]: begin
+ reg_rdata_next[0] = alert_cause_18_qs;
+ end
+
+ addr_hit[250]: begin
+ reg_rdata_next[0] = alert_cause_19_qs;
+ end
+
+ addr_hit[251]: begin
+ reg_rdata_next[0] = alert_cause_20_qs;
+ end
+
+ addr_hit[252]: begin
+ reg_rdata_next[0] = alert_cause_21_qs;
+ end
+
+ addr_hit[253]: begin
+ reg_rdata_next[0] = alert_cause_22_qs;
+ end
+
+ addr_hit[254]: begin
+ reg_rdata_next[0] = alert_cause_23_qs;
+ end
+
+ addr_hit[255]: begin
+ reg_rdata_next[0] = alert_cause_24_qs;
+ end
+
+ addr_hit[256]: begin
+ reg_rdata_next[0] = alert_cause_25_qs;
+ end
+
+ addr_hit[257]: begin
+ reg_rdata_next[0] = alert_cause_26_qs;
+ end
+
+ addr_hit[258]: begin
+ reg_rdata_next[0] = alert_cause_27_qs;
+ end
+
+ addr_hit[259]: begin
+ reg_rdata_next[0] = alert_cause_28_qs;
+ end
+
+ addr_hit[260]: begin
+ reg_rdata_next[0] = alert_cause_29_qs;
+ end
+
+ addr_hit[261]: begin
+ reg_rdata_next[0] = alert_cause_30_qs;
+ end
+
+ addr_hit[262]: begin
+ reg_rdata_next[0] = alert_cause_31_qs;
+ end
+
+ addr_hit[263]: begin
+ reg_rdata_next[0] = alert_cause_32_qs;
+ end
+
+ addr_hit[264]: begin
+ reg_rdata_next[0] = alert_cause_33_qs;
+ end
+
+ addr_hit[265]: begin
+ reg_rdata_next[0] = alert_cause_34_qs;
+ end
+
+ addr_hit[266]: begin
+ reg_rdata_next[0] = alert_cause_35_qs;
+ end
+
+ addr_hit[267]: begin
+ reg_rdata_next[0] = alert_cause_36_qs;
+ end
+
+ addr_hit[268]: begin
+ reg_rdata_next[0] = alert_cause_37_qs;
+ end
+
+ addr_hit[269]: begin
+ reg_rdata_next[0] = alert_cause_38_qs;
+ end
+
+ addr_hit[270]: begin
+ reg_rdata_next[0] = alert_cause_39_qs;
+ end
+
+ addr_hit[271]: begin
+ reg_rdata_next[0] = alert_cause_40_qs;
+ end
+
+ addr_hit[272]: begin
+ reg_rdata_next[0] = alert_cause_41_qs;
+ end
+
+ addr_hit[273]: begin
+ reg_rdata_next[0] = alert_cause_42_qs;
+ end
+
+ addr_hit[274]: begin
+ reg_rdata_next[0] = alert_cause_43_qs;
+ end
+
+ addr_hit[275]: begin
+ reg_rdata_next[0] = alert_cause_44_qs;
+ end
+
+ addr_hit[276]: begin
+ reg_rdata_next[0] = alert_cause_45_qs;
+ end
+
+ addr_hit[277]: begin
+ reg_rdata_next[0] = alert_cause_46_qs;
+ end
+
+ addr_hit[278]: begin
+ reg_rdata_next[0] = alert_cause_47_qs;
+ end
+
+ addr_hit[279]: begin
+ reg_rdata_next[0] = alert_cause_48_qs;
+ end
+
+ addr_hit[280]: begin
+ reg_rdata_next[0] = alert_cause_49_qs;
+ end
+
+ addr_hit[281]: begin
+ reg_rdata_next[0] = alert_cause_50_qs;
+ end
+
+ addr_hit[282]: begin
+ reg_rdata_next[0] = alert_cause_51_qs;
+ end
+
+ addr_hit[283]: begin
+ reg_rdata_next[0] = alert_cause_52_qs;
+ end
+
+ addr_hit[284]: begin
+ reg_rdata_next[0] = alert_cause_53_qs;
+ end
+
+ addr_hit[285]: begin
+ reg_rdata_next[0] = alert_cause_54_qs;
+ end
+
+ addr_hit[286]: begin
+ reg_rdata_next[0] = alert_cause_55_qs;
+ end
+
+ addr_hit[287]: begin
+ reg_rdata_next[0] = alert_cause_56_qs;
+ end
+
+ addr_hit[288]: begin
+ reg_rdata_next[0] = alert_cause_57_qs;
+ end
+
+ addr_hit[289]: begin
+ reg_rdata_next[0] = alert_cause_58_qs;
+ end
+
+ addr_hit[290]: begin
+ reg_rdata_next[0] = alert_cause_59_qs;
+ end
+
+ addr_hit[291]: begin
+ reg_rdata_next[0] = alert_cause_60_qs;
+ end
+
+ addr_hit[292]: begin
+ reg_rdata_next[0] = alert_cause_61_qs;
+ end
+
+ addr_hit[293]: begin
+ reg_rdata_next[0] = alert_cause_62_qs;
+ end
+
+ addr_hit[294]: begin
+ reg_rdata_next[0] = alert_cause_63_qs;
+ end
+
+ addr_hit[295]: begin
+ reg_rdata_next[0] = alert_cause_64_qs;
+ end
+
+ addr_hit[296]: begin
+ reg_rdata_next[0] = alert_cause_65_qs;
+ end
+
+ addr_hit[297]: begin
+ reg_rdata_next[0] = alert_cause_66_qs;
+ end
+
+ addr_hit[298]: begin
+ reg_rdata_next[0] = alert_cause_67_qs;
+ end
+
+ addr_hit[299]: begin
+ reg_rdata_next[0] = alert_cause_68_qs;
+ end
+
+ addr_hit[300]: begin
+ reg_rdata_next[0] = alert_cause_69_qs;
+ end
+
+ addr_hit[301]: begin
+ reg_rdata_next[0] = alert_cause_70_qs;
+ end
+
+ addr_hit[302]: begin
+ reg_rdata_next[0] = alert_cause_71_qs;
+ end
+
+ addr_hit[303]: begin
+ reg_rdata_next[0] = alert_cause_72_qs;
+ end
+
+ addr_hit[304]: begin
+ reg_rdata_next[0] = alert_cause_73_qs;
+ end
+
+ addr_hit[305]: begin
+ reg_rdata_next[0] = alert_cause_74_qs;
+ end
+
+ addr_hit[306]: begin
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ end
+
+ addr_hit[307]: begin
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ end
+
+ addr_hit[308]: begin
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ end
+
+ addr_hit[309]: begin
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ end
+
+ addr_hit[310]: begin
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ end
+
+ addr_hit[311]: begin
+ reg_rdata_next[0] = loc_alert_regwen_5_qs;
+ end
+
+ addr_hit[312]: begin
+ reg_rdata_next[0] = loc_alert_regwen_6_qs;
+ end
+
+ addr_hit[313]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
+ end
+
+ addr_hit[314]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
+ end
+
+ addr_hit[315]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
+ end
+
+ addr_hit[316]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
+ end
+
+ addr_hit[317]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
+ end
+
+ addr_hit[318]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
+ end
+
+ addr_hit[319]: begin
+ reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
+ end
+
+ addr_hit[320]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
+ end
+
+ addr_hit[321]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
+ end
+
+ addr_hit[322]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
+ end
+
+ addr_hit[323]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
+ end
+
+ addr_hit[324]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
+ end
+
+ addr_hit[325]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
+ end
+
+ addr_hit[326]: begin
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
+ end
+
+ addr_hit[327]: begin
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
+ end
+
+ addr_hit[328]: begin
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
+ end
+
+ addr_hit[329]: begin
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
+ end
+
+ addr_hit[330]: begin
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
+ end
+
+ addr_hit[331]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[332]: begin
+ reg_rdata_next[0] = loc_alert_cause_5_qs;
+ end
+
+ addr_hit[333]: begin
+ reg_rdata_next[0] = loc_alert_cause_6_qs;
+ end
+
+ addr_hit[334]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[335]: begin
+ reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
+ reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
+ reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
+ reg_rdata_next[3] = classa_ctrl_shadowed_en_e1_qs;
+ reg_rdata_next[4] = classa_ctrl_shadowed_en_e2_qs;
+ reg_rdata_next[5] = classa_ctrl_shadowed_en_e3_qs;
+ reg_rdata_next[7:6] = classa_ctrl_shadowed_map_e0_qs;
+ reg_rdata_next[9:8] = classa_ctrl_shadowed_map_e1_qs;
+ reg_rdata_next[11:10] = classa_ctrl_shadowed_map_e2_qs;
+ reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
+ end
+
+ addr_hit[336]: begin
+ reg_rdata_next[0] = classa_clr_regwen_qs;
+ end
+
+ addr_hit[337]: begin
+ reg_rdata_next[0] = classa_clr_shadowed_qs;
+ end
+
+ addr_hit[338]: begin
+ reg_rdata_next[15:0] = classa_accum_cnt_qs;
+ end
+
+ addr_hit[339]: begin
+ reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
+ end
+
+ addr_hit[340]: begin
+ reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
+ end
+
+ addr_hit[341]: begin
+ reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
+ end
+
+ addr_hit[342]: begin
+ reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
+ end
+
+ addr_hit[343]: begin
+ reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
+ end
+
+ addr_hit[344]: begin
+ reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
+ end
+
+ addr_hit[345]: begin
+ reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
+ end
+
+ addr_hit[346]: begin
+ reg_rdata_next[31:0] = classa_esc_cnt_qs;
+ end
+
+ addr_hit[347]: begin
+ reg_rdata_next[2:0] = classa_state_qs;
+ end
+
+ addr_hit[348]: begin
+ reg_rdata_next[0] = classb_regwen_qs;
+ end
+
+ addr_hit[349]: begin
+ reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
+ reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
+ reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
+ reg_rdata_next[3] = classb_ctrl_shadowed_en_e1_qs;
+ reg_rdata_next[4] = classb_ctrl_shadowed_en_e2_qs;
+ reg_rdata_next[5] = classb_ctrl_shadowed_en_e3_qs;
+ reg_rdata_next[7:6] = classb_ctrl_shadowed_map_e0_qs;
+ reg_rdata_next[9:8] = classb_ctrl_shadowed_map_e1_qs;
+ reg_rdata_next[11:10] = classb_ctrl_shadowed_map_e2_qs;
+ reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
+ end
+
+ addr_hit[350]: begin
+ reg_rdata_next[0] = classb_clr_regwen_qs;
+ end
+
+ addr_hit[351]: begin
+ reg_rdata_next[0] = classb_clr_shadowed_qs;
+ end
+
+ addr_hit[352]: begin
+ reg_rdata_next[15:0] = classb_accum_cnt_qs;
+ end
+
+ addr_hit[353]: begin
+ reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
+ end
+
+ addr_hit[354]: begin
+ reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
+ end
+
+ addr_hit[355]: begin
+ reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
+ end
+
+ addr_hit[356]: begin
+ reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
+ end
+
+ addr_hit[357]: begin
+ reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
+ end
+
+ addr_hit[358]: begin
+ reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
+ end
+
+ addr_hit[359]: begin
+ reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
+ end
+
+ addr_hit[360]: begin
+ reg_rdata_next[31:0] = classb_esc_cnt_qs;
+ end
+
+ addr_hit[361]: begin
+ reg_rdata_next[2:0] = classb_state_qs;
+ end
+
+ addr_hit[362]: begin
+ reg_rdata_next[0] = classc_regwen_qs;
+ end
+
+ addr_hit[363]: begin
+ reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
+ reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
+ reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
+ reg_rdata_next[3] = classc_ctrl_shadowed_en_e1_qs;
+ reg_rdata_next[4] = classc_ctrl_shadowed_en_e2_qs;
+ reg_rdata_next[5] = classc_ctrl_shadowed_en_e3_qs;
+ reg_rdata_next[7:6] = classc_ctrl_shadowed_map_e0_qs;
+ reg_rdata_next[9:8] = classc_ctrl_shadowed_map_e1_qs;
+ reg_rdata_next[11:10] = classc_ctrl_shadowed_map_e2_qs;
+ reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
+ end
+
+ addr_hit[364]: begin
+ reg_rdata_next[0] = classc_clr_regwen_qs;
+ end
+
+ addr_hit[365]: begin
+ reg_rdata_next[0] = classc_clr_shadowed_qs;
+ end
+
+ addr_hit[366]: begin
+ reg_rdata_next[15:0] = classc_accum_cnt_qs;
+ end
+
+ addr_hit[367]: begin
+ reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
+ end
+
+ addr_hit[368]: begin
+ reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
+ end
+
+ addr_hit[369]: begin
+ reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
+ end
+
+ addr_hit[370]: begin
+ reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
+ end
+
+ addr_hit[371]: begin
+ reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
+ end
+
+ addr_hit[372]: begin
+ reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
+ end
+
+ addr_hit[373]: begin
+ reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
+ end
+
+ addr_hit[374]: begin
+ reg_rdata_next[31:0] = classc_esc_cnt_qs;
+ end
+
+ addr_hit[375]: begin
+ reg_rdata_next[2:0] = classc_state_qs;
+ end
+
+ addr_hit[376]: begin
+ reg_rdata_next[0] = classd_regwen_qs;
+ end
+
+ addr_hit[377]: begin
+ reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
+ reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
+ reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
+ reg_rdata_next[3] = classd_ctrl_shadowed_en_e1_qs;
+ reg_rdata_next[4] = classd_ctrl_shadowed_en_e2_qs;
+ reg_rdata_next[5] = classd_ctrl_shadowed_en_e3_qs;
+ reg_rdata_next[7:6] = classd_ctrl_shadowed_map_e0_qs;
+ reg_rdata_next[9:8] = classd_ctrl_shadowed_map_e1_qs;
+ reg_rdata_next[11:10] = classd_ctrl_shadowed_map_e2_qs;
+ reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
+ end
+
+ addr_hit[378]: begin
+ reg_rdata_next[0] = classd_clr_regwen_qs;
+ end
+
+ addr_hit[379]: begin
+ reg_rdata_next[0] = classd_clr_shadowed_qs;
+ end
+
+ addr_hit[380]: begin
+ reg_rdata_next[15:0] = classd_accum_cnt_qs;
+ end
+
+ addr_hit[381]: begin
+ reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
+ end
+
+ addr_hit[382]: begin
+ reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
+ end
+
+ addr_hit[383]: begin
+ reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
+ end
+
+ addr_hit[384]: begin
+ reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
+ end
+
+ addr_hit[385]: begin
+ reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
+ end
+
+ addr_hit[386]: begin
+ reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
+ end
+
+ addr_hit[387]: begin
+ reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
+ end
+
+ addr_hit[388]: begin
+ reg_rdata_next[31:0] = classd_esc_cnt_qs;
+ end
+
+ addr_hit[389]: begin
+ reg_rdata_next[2:0] = classd_state_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ logic rst_done;
+ logic shadow_rst_done;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rst_done <= '0;
+ end else begin
+ rst_done <= 1'b1;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
+ if (!rst_shadowed_ni) begin
+ shadow_rst_done <= '0;
+ end else begin
+ shadow_rst_done <= 1'b1;
+ end
+ end
+
+ // both shadow and normal resets have been released
+ assign shadow_busy = ~(rst_done & shadow_rst_done);
+
+ // Collect up storage and update errors
+ assign shadowed_storage_err_o = |{
+ ping_timeout_cyc_shadowed_storage_err,
+ ping_timer_en_shadowed_storage_err,
+ alert_en_shadowed_0_storage_err,
+ alert_en_shadowed_1_storage_err,
+ alert_en_shadowed_2_storage_err,
+ alert_en_shadowed_3_storage_err,
+ alert_en_shadowed_4_storage_err,
+ alert_en_shadowed_5_storage_err,
+ alert_en_shadowed_6_storage_err,
+ alert_en_shadowed_7_storage_err,
+ alert_en_shadowed_8_storage_err,
+ alert_en_shadowed_9_storage_err,
+ alert_en_shadowed_10_storage_err,
+ alert_en_shadowed_11_storage_err,
+ alert_en_shadowed_12_storage_err,
+ alert_en_shadowed_13_storage_err,
+ alert_en_shadowed_14_storage_err,
+ alert_en_shadowed_15_storage_err,
+ alert_en_shadowed_16_storage_err,
+ alert_en_shadowed_17_storage_err,
+ alert_en_shadowed_18_storage_err,
+ alert_en_shadowed_19_storage_err,
+ alert_en_shadowed_20_storage_err,
+ alert_en_shadowed_21_storage_err,
+ alert_en_shadowed_22_storage_err,
+ alert_en_shadowed_23_storage_err,
+ alert_en_shadowed_24_storage_err,
+ alert_en_shadowed_25_storage_err,
+ alert_en_shadowed_26_storage_err,
+ alert_en_shadowed_27_storage_err,
+ alert_en_shadowed_28_storage_err,
+ alert_en_shadowed_29_storage_err,
+ alert_en_shadowed_30_storage_err,
+ alert_en_shadowed_31_storage_err,
+ alert_en_shadowed_32_storage_err,
+ alert_en_shadowed_33_storage_err,
+ alert_en_shadowed_34_storage_err,
+ alert_en_shadowed_35_storage_err,
+ alert_en_shadowed_36_storage_err,
+ alert_en_shadowed_37_storage_err,
+ alert_en_shadowed_38_storage_err,
+ alert_en_shadowed_39_storage_err,
+ alert_en_shadowed_40_storage_err,
+ alert_en_shadowed_41_storage_err,
+ alert_en_shadowed_42_storage_err,
+ alert_en_shadowed_43_storage_err,
+ alert_en_shadowed_44_storage_err,
+ alert_en_shadowed_45_storage_err,
+ alert_en_shadowed_46_storage_err,
+ alert_en_shadowed_47_storage_err,
+ alert_en_shadowed_48_storage_err,
+ alert_en_shadowed_49_storage_err,
+ alert_en_shadowed_50_storage_err,
+ alert_en_shadowed_51_storage_err,
+ alert_en_shadowed_52_storage_err,
+ alert_en_shadowed_53_storage_err,
+ alert_en_shadowed_54_storage_err,
+ alert_en_shadowed_55_storage_err,
+ alert_en_shadowed_56_storage_err,
+ alert_en_shadowed_57_storage_err,
+ alert_en_shadowed_58_storage_err,
+ alert_en_shadowed_59_storage_err,
+ alert_en_shadowed_60_storage_err,
+ alert_en_shadowed_61_storage_err,
+ alert_en_shadowed_62_storage_err,
+ alert_en_shadowed_63_storage_err,
+ alert_en_shadowed_64_storage_err,
+ alert_en_shadowed_65_storage_err,
+ alert_en_shadowed_66_storage_err,
+ alert_en_shadowed_67_storage_err,
+ alert_en_shadowed_68_storage_err,
+ alert_en_shadowed_69_storage_err,
+ alert_en_shadowed_70_storage_err,
+ alert_en_shadowed_71_storage_err,
+ alert_en_shadowed_72_storage_err,
+ alert_en_shadowed_73_storage_err,
+ alert_en_shadowed_74_storage_err,
+ alert_class_shadowed_0_storage_err,
+ alert_class_shadowed_1_storage_err,
+ alert_class_shadowed_2_storage_err,
+ alert_class_shadowed_3_storage_err,
+ alert_class_shadowed_4_storage_err,
+ alert_class_shadowed_5_storage_err,
+ alert_class_shadowed_6_storage_err,
+ alert_class_shadowed_7_storage_err,
+ alert_class_shadowed_8_storage_err,
+ alert_class_shadowed_9_storage_err,
+ alert_class_shadowed_10_storage_err,
+ alert_class_shadowed_11_storage_err,
+ alert_class_shadowed_12_storage_err,
+ alert_class_shadowed_13_storage_err,
+ alert_class_shadowed_14_storage_err,
+ alert_class_shadowed_15_storage_err,
+ alert_class_shadowed_16_storage_err,
+ alert_class_shadowed_17_storage_err,
+ alert_class_shadowed_18_storage_err,
+ alert_class_shadowed_19_storage_err,
+ alert_class_shadowed_20_storage_err,
+ alert_class_shadowed_21_storage_err,
+ alert_class_shadowed_22_storage_err,
+ alert_class_shadowed_23_storage_err,
+ alert_class_shadowed_24_storage_err,
+ alert_class_shadowed_25_storage_err,
+ alert_class_shadowed_26_storage_err,
+ alert_class_shadowed_27_storage_err,
+ alert_class_shadowed_28_storage_err,
+ alert_class_shadowed_29_storage_err,
+ alert_class_shadowed_30_storage_err,
+ alert_class_shadowed_31_storage_err,
+ alert_class_shadowed_32_storage_err,
+ alert_class_shadowed_33_storage_err,
+ alert_class_shadowed_34_storage_err,
+ alert_class_shadowed_35_storage_err,
+ alert_class_shadowed_36_storage_err,
+ alert_class_shadowed_37_storage_err,
+ alert_class_shadowed_38_storage_err,
+ alert_class_shadowed_39_storage_err,
+ alert_class_shadowed_40_storage_err,
+ alert_class_shadowed_41_storage_err,
+ alert_class_shadowed_42_storage_err,
+ alert_class_shadowed_43_storage_err,
+ alert_class_shadowed_44_storage_err,
+ alert_class_shadowed_45_storage_err,
+ alert_class_shadowed_46_storage_err,
+ alert_class_shadowed_47_storage_err,
+ alert_class_shadowed_48_storage_err,
+ alert_class_shadowed_49_storage_err,
+ alert_class_shadowed_50_storage_err,
+ alert_class_shadowed_51_storage_err,
+ alert_class_shadowed_52_storage_err,
+ alert_class_shadowed_53_storage_err,
+ alert_class_shadowed_54_storage_err,
+ alert_class_shadowed_55_storage_err,
+ alert_class_shadowed_56_storage_err,
+ alert_class_shadowed_57_storage_err,
+ alert_class_shadowed_58_storage_err,
+ alert_class_shadowed_59_storage_err,
+ alert_class_shadowed_60_storage_err,
+ alert_class_shadowed_61_storage_err,
+ alert_class_shadowed_62_storage_err,
+ alert_class_shadowed_63_storage_err,
+ alert_class_shadowed_64_storage_err,
+ alert_class_shadowed_65_storage_err,
+ alert_class_shadowed_66_storage_err,
+ alert_class_shadowed_67_storage_err,
+ alert_class_shadowed_68_storage_err,
+ alert_class_shadowed_69_storage_err,
+ alert_class_shadowed_70_storage_err,
+ alert_class_shadowed_71_storage_err,
+ alert_class_shadowed_72_storage_err,
+ alert_class_shadowed_73_storage_err,
+ alert_class_shadowed_74_storage_err,
+ loc_alert_en_shadowed_0_storage_err,
+ loc_alert_en_shadowed_1_storage_err,
+ loc_alert_en_shadowed_2_storage_err,
+ loc_alert_en_shadowed_3_storage_err,
+ loc_alert_en_shadowed_4_storage_err,
+ loc_alert_en_shadowed_5_storage_err,
+ loc_alert_en_shadowed_6_storage_err,
+ loc_alert_class_shadowed_0_storage_err,
+ loc_alert_class_shadowed_1_storage_err,
+ loc_alert_class_shadowed_2_storage_err,
+ loc_alert_class_shadowed_3_storage_err,
+ loc_alert_class_shadowed_4_storage_err,
+ loc_alert_class_shadowed_5_storage_err,
+ loc_alert_class_shadowed_6_storage_err,
+ classa_ctrl_shadowed_en_storage_err,
+ classa_ctrl_shadowed_lock_storage_err,
+ classa_ctrl_shadowed_en_e0_storage_err,
+ classa_ctrl_shadowed_en_e1_storage_err,
+ classa_ctrl_shadowed_en_e2_storage_err,
+ classa_ctrl_shadowed_en_e3_storage_err,
+ classa_ctrl_shadowed_map_e0_storage_err,
+ classa_ctrl_shadowed_map_e1_storage_err,
+ classa_ctrl_shadowed_map_e2_storage_err,
+ classa_ctrl_shadowed_map_e3_storage_err,
+ classa_clr_shadowed_storage_err,
+ classa_accum_thresh_shadowed_storage_err,
+ classa_timeout_cyc_shadowed_storage_err,
+ classa_crashdump_trigger_shadowed_storage_err,
+ classa_phase0_cyc_shadowed_storage_err,
+ classa_phase1_cyc_shadowed_storage_err,
+ classa_phase2_cyc_shadowed_storage_err,
+ classa_phase3_cyc_shadowed_storage_err,
+ classb_ctrl_shadowed_en_storage_err,
+ classb_ctrl_shadowed_lock_storage_err,
+ classb_ctrl_shadowed_en_e0_storage_err,
+ classb_ctrl_shadowed_en_e1_storage_err,
+ classb_ctrl_shadowed_en_e2_storage_err,
+ classb_ctrl_shadowed_en_e3_storage_err,
+ classb_ctrl_shadowed_map_e0_storage_err,
+ classb_ctrl_shadowed_map_e1_storage_err,
+ classb_ctrl_shadowed_map_e2_storage_err,
+ classb_ctrl_shadowed_map_e3_storage_err,
+ classb_clr_shadowed_storage_err,
+ classb_accum_thresh_shadowed_storage_err,
+ classb_timeout_cyc_shadowed_storage_err,
+ classb_crashdump_trigger_shadowed_storage_err,
+ classb_phase0_cyc_shadowed_storage_err,
+ classb_phase1_cyc_shadowed_storage_err,
+ classb_phase2_cyc_shadowed_storage_err,
+ classb_phase3_cyc_shadowed_storage_err,
+ classc_ctrl_shadowed_en_storage_err,
+ classc_ctrl_shadowed_lock_storage_err,
+ classc_ctrl_shadowed_en_e0_storage_err,
+ classc_ctrl_shadowed_en_e1_storage_err,
+ classc_ctrl_shadowed_en_e2_storage_err,
+ classc_ctrl_shadowed_en_e3_storage_err,
+ classc_ctrl_shadowed_map_e0_storage_err,
+ classc_ctrl_shadowed_map_e1_storage_err,
+ classc_ctrl_shadowed_map_e2_storage_err,
+ classc_ctrl_shadowed_map_e3_storage_err,
+ classc_clr_shadowed_storage_err,
+ classc_accum_thresh_shadowed_storage_err,
+ classc_timeout_cyc_shadowed_storage_err,
+ classc_crashdump_trigger_shadowed_storage_err,
+ classc_phase0_cyc_shadowed_storage_err,
+ classc_phase1_cyc_shadowed_storage_err,
+ classc_phase2_cyc_shadowed_storage_err,
+ classc_phase3_cyc_shadowed_storage_err,
+ classd_ctrl_shadowed_en_storage_err,
+ classd_ctrl_shadowed_lock_storage_err,
+ classd_ctrl_shadowed_en_e0_storage_err,
+ classd_ctrl_shadowed_en_e1_storage_err,
+ classd_ctrl_shadowed_en_e2_storage_err,
+ classd_ctrl_shadowed_en_e3_storage_err,
+ classd_ctrl_shadowed_map_e0_storage_err,
+ classd_ctrl_shadowed_map_e1_storage_err,
+ classd_ctrl_shadowed_map_e2_storage_err,
+ classd_ctrl_shadowed_map_e3_storage_err,
+ classd_clr_shadowed_storage_err,
+ classd_accum_thresh_shadowed_storage_err,
+ classd_timeout_cyc_shadowed_storage_err,
+ classd_crashdump_trigger_shadowed_storage_err,
+ classd_phase0_cyc_shadowed_storage_err,
+ classd_phase1_cyc_shadowed_storage_err,
+ classd_phase2_cyc_shadowed_storage_err,
+ classd_phase3_cyc_shadowed_storage_err
+ };
+ assign shadowed_update_err_o = |{
+ ping_timeout_cyc_shadowed_update_err,
+ ping_timer_en_shadowed_update_err,
+ alert_en_shadowed_0_update_err,
+ alert_en_shadowed_1_update_err,
+ alert_en_shadowed_2_update_err,
+ alert_en_shadowed_3_update_err,
+ alert_en_shadowed_4_update_err,
+ alert_en_shadowed_5_update_err,
+ alert_en_shadowed_6_update_err,
+ alert_en_shadowed_7_update_err,
+ alert_en_shadowed_8_update_err,
+ alert_en_shadowed_9_update_err,
+ alert_en_shadowed_10_update_err,
+ alert_en_shadowed_11_update_err,
+ alert_en_shadowed_12_update_err,
+ alert_en_shadowed_13_update_err,
+ alert_en_shadowed_14_update_err,
+ alert_en_shadowed_15_update_err,
+ alert_en_shadowed_16_update_err,
+ alert_en_shadowed_17_update_err,
+ alert_en_shadowed_18_update_err,
+ alert_en_shadowed_19_update_err,
+ alert_en_shadowed_20_update_err,
+ alert_en_shadowed_21_update_err,
+ alert_en_shadowed_22_update_err,
+ alert_en_shadowed_23_update_err,
+ alert_en_shadowed_24_update_err,
+ alert_en_shadowed_25_update_err,
+ alert_en_shadowed_26_update_err,
+ alert_en_shadowed_27_update_err,
+ alert_en_shadowed_28_update_err,
+ alert_en_shadowed_29_update_err,
+ alert_en_shadowed_30_update_err,
+ alert_en_shadowed_31_update_err,
+ alert_en_shadowed_32_update_err,
+ alert_en_shadowed_33_update_err,
+ alert_en_shadowed_34_update_err,
+ alert_en_shadowed_35_update_err,
+ alert_en_shadowed_36_update_err,
+ alert_en_shadowed_37_update_err,
+ alert_en_shadowed_38_update_err,
+ alert_en_shadowed_39_update_err,
+ alert_en_shadowed_40_update_err,
+ alert_en_shadowed_41_update_err,
+ alert_en_shadowed_42_update_err,
+ alert_en_shadowed_43_update_err,
+ alert_en_shadowed_44_update_err,
+ alert_en_shadowed_45_update_err,
+ alert_en_shadowed_46_update_err,
+ alert_en_shadowed_47_update_err,
+ alert_en_shadowed_48_update_err,
+ alert_en_shadowed_49_update_err,
+ alert_en_shadowed_50_update_err,
+ alert_en_shadowed_51_update_err,
+ alert_en_shadowed_52_update_err,
+ alert_en_shadowed_53_update_err,
+ alert_en_shadowed_54_update_err,
+ alert_en_shadowed_55_update_err,
+ alert_en_shadowed_56_update_err,
+ alert_en_shadowed_57_update_err,
+ alert_en_shadowed_58_update_err,
+ alert_en_shadowed_59_update_err,
+ alert_en_shadowed_60_update_err,
+ alert_en_shadowed_61_update_err,
+ alert_en_shadowed_62_update_err,
+ alert_en_shadowed_63_update_err,
+ alert_en_shadowed_64_update_err,
+ alert_en_shadowed_65_update_err,
+ alert_en_shadowed_66_update_err,
+ alert_en_shadowed_67_update_err,
+ alert_en_shadowed_68_update_err,
+ alert_en_shadowed_69_update_err,
+ alert_en_shadowed_70_update_err,
+ alert_en_shadowed_71_update_err,
+ alert_en_shadowed_72_update_err,
+ alert_en_shadowed_73_update_err,
+ alert_en_shadowed_74_update_err,
+ alert_class_shadowed_0_update_err,
+ alert_class_shadowed_1_update_err,
+ alert_class_shadowed_2_update_err,
+ alert_class_shadowed_3_update_err,
+ alert_class_shadowed_4_update_err,
+ alert_class_shadowed_5_update_err,
+ alert_class_shadowed_6_update_err,
+ alert_class_shadowed_7_update_err,
+ alert_class_shadowed_8_update_err,
+ alert_class_shadowed_9_update_err,
+ alert_class_shadowed_10_update_err,
+ alert_class_shadowed_11_update_err,
+ alert_class_shadowed_12_update_err,
+ alert_class_shadowed_13_update_err,
+ alert_class_shadowed_14_update_err,
+ alert_class_shadowed_15_update_err,
+ alert_class_shadowed_16_update_err,
+ alert_class_shadowed_17_update_err,
+ alert_class_shadowed_18_update_err,
+ alert_class_shadowed_19_update_err,
+ alert_class_shadowed_20_update_err,
+ alert_class_shadowed_21_update_err,
+ alert_class_shadowed_22_update_err,
+ alert_class_shadowed_23_update_err,
+ alert_class_shadowed_24_update_err,
+ alert_class_shadowed_25_update_err,
+ alert_class_shadowed_26_update_err,
+ alert_class_shadowed_27_update_err,
+ alert_class_shadowed_28_update_err,
+ alert_class_shadowed_29_update_err,
+ alert_class_shadowed_30_update_err,
+ alert_class_shadowed_31_update_err,
+ alert_class_shadowed_32_update_err,
+ alert_class_shadowed_33_update_err,
+ alert_class_shadowed_34_update_err,
+ alert_class_shadowed_35_update_err,
+ alert_class_shadowed_36_update_err,
+ alert_class_shadowed_37_update_err,
+ alert_class_shadowed_38_update_err,
+ alert_class_shadowed_39_update_err,
+ alert_class_shadowed_40_update_err,
+ alert_class_shadowed_41_update_err,
+ alert_class_shadowed_42_update_err,
+ alert_class_shadowed_43_update_err,
+ alert_class_shadowed_44_update_err,
+ alert_class_shadowed_45_update_err,
+ alert_class_shadowed_46_update_err,
+ alert_class_shadowed_47_update_err,
+ alert_class_shadowed_48_update_err,
+ alert_class_shadowed_49_update_err,
+ alert_class_shadowed_50_update_err,
+ alert_class_shadowed_51_update_err,
+ alert_class_shadowed_52_update_err,
+ alert_class_shadowed_53_update_err,
+ alert_class_shadowed_54_update_err,
+ alert_class_shadowed_55_update_err,
+ alert_class_shadowed_56_update_err,
+ alert_class_shadowed_57_update_err,
+ alert_class_shadowed_58_update_err,
+ alert_class_shadowed_59_update_err,
+ alert_class_shadowed_60_update_err,
+ alert_class_shadowed_61_update_err,
+ alert_class_shadowed_62_update_err,
+ alert_class_shadowed_63_update_err,
+ alert_class_shadowed_64_update_err,
+ alert_class_shadowed_65_update_err,
+ alert_class_shadowed_66_update_err,
+ alert_class_shadowed_67_update_err,
+ alert_class_shadowed_68_update_err,
+ alert_class_shadowed_69_update_err,
+ alert_class_shadowed_70_update_err,
+ alert_class_shadowed_71_update_err,
+ alert_class_shadowed_72_update_err,
+ alert_class_shadowed_73_update_err,
+ alert_class_shadowed_74_update_err,
+ loc_alert_en_shadowed_0_update_err,
+ loc_alert_en_shadowed_1_update_err,
+ loc_alert_en_shadowed_2_update_err,
+ loc_alert_en_shadowed_3_update_err,
+ loc_alert_en_shadowed_4_update_err,
+ loc_alert_en_shadowed_5_update_err,
+ loc_alert_en_shadowed_6_update_err,
+ loc_alert_class_shadowed_0_update_err,
+ loc_alert_class_shadowed_1_update_err,
+ loc_alert_class_shadowed_2_update_err,
+ loc_alert_class_shadowed_3_update_err,
+ loc_alert_class_shadowed_4_update_err,
+ loc_alert_class_shadowed_5_update_err,
+ loc_alert_class_shadowed_6_update_err,
+ classa_ctrl_shadowed_en_update_err,
+ classa_ctrl_shadowed_lock_update_err,
+ classa_ctrl_shadowed_en_e0_update_err,
+ classa_ctrl_shadowed_en_e1_update_err,
+ classa_ctrl_shadowed_en_e2_update_err,
+ classa_ctrl_shadowed_en_e3_update_err,
+ classa_ctrl_shadowed_map_e0_update_err,
+ classa_ctrl_shadowed_map_e1_update_err,
+ classa_ctrl_shadowed_map_e2_update_err,
+ classa_ctrl_shadowed_map_e3_update_err,
+ classa_clr_shadowed_update_err,
+ classa_accum_thresh_shadowed_update_err,
+ classa_timeout_cyc_shadowed_update_err,
+ classa_crashdump_trigger_shadowed_update_err,
+ classa_phase0_cyc_shadowed_update_err,
+ classa_phase1_cyc_shadowed_update_err,
+ classa_phase2_cyc_shadowed_update_err,
+ classa_phase3_cyc_shadowed_update_err,
+ classb_ctrl_shadowed_en_update_err,
+ classb_ctrl_shadowed_lock_update_err,
+ classb_ctrl_shadowed_en_e0_update_err,
+ classb_ctrl_shadowed_en_e1_update_err,
+ classb_ctrl_shadowed_en_e2_update_err,
+ classb_ctrl_shadowed_en_e3_update_err,
+ classb_ctrl_shadowed_map_e0_update_err,
+ classb_ctrl_shadowed_map_e1_update_err,
+ classb_ctrl_shadowed_map_e2_update_err,
+ classb_ctrl_shadowed_map_e3_update_err,
+ classb_clr_shadowed_update_err,
+ classb_accum_thresh_shadowed_update_err,
+ classb_timeout_cyc_shadowed_update_err,
+ classb_crashdump_trigger_shadowed_update_err,
+ classb_phase0_cyc_shadowed_update_err,
+ classb_phase1_cyc_shadowed_update_err,
+ classb_phase2_cyc_shadowed_update_err,
+ classb_phase3_cyc_shadowed_update_err,
+ classc_ctrl_shadowed_en_update_err,
+ classc_ctrl_shadowed_lock_update_err,
+ classc_ctrl_shadowed_en_e0_update_err,
+ classc_ctrl_shadowed_en_e1_update_err,
+ classc_ctrl_shadowed_en_e2_update_err,
+ classc_ctrl_shadowed_en_e3_update_err,
+ classc_ctrl_shadowed_map_e0_update_err,
+ classc_ctrl_shadowed_map_e1_update_err,
+ classc_ctrl_shadowed_map_e2_update_err,
+ classc_ctrl_shadowed_map_e3_update_err,
+ classc_clr_shadowed_update_err,
+ classc_accum_thresh_shadowed_update_err,
+ classc_timeout_cyc_shadowed_update_err,
+ classc_crashdump_trigger_shadowed_update_err,
+ classc_phase0_cyc_shadowed_update_err,
+ classc_phase1_cyc_shadowed_update_err,
+ classc_phase2_cyc_shadowed_update_err,
+ classc_phase3_cyc_shadowed_update_err,
+ classd_ctrl_shadowed_en_update_err,
+ classd_ctrl_shadowed_lock_update_err,
+ classd_ctrl_shadowed_en_e0_update_err,
+ classd_ctrl_shadowed_en_e1_update_err,
+ classd_ctrl_shadowed_en_e2_update_err,
+ classd_ctrl_shadowed_en_e3_update_err,
+ classd_ctrl_shadowed_map_e0_update_err,
+ classd_ctrl_shadowed_map_e1_update_err,
+ classd_ctrl_shadowed_map_e2_update_err,
+ classd_ctrl_shadowed_map_e3_update_err,
+ classd_clr_shadowed_update_err,
+ classd_accum_thresh_shadowed_update_err,
+ classd_timeout_cyc_shadowed_update_err,
+ classd_crashdump_trigger_shadowed_update_err,
+ classd_phase0_cyc_shadowed_update_err,
+ classd_phase1_cyc_shadowed_update_err,
+ classd_phase2_cyc_shadowed_update_err,
+ classd_phase3_cyc_shadowed_update_err
+ };
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv
new file mode 100644
index 0000000..cdef649
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv
@@ -0,0 +1,361 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Breakout / remapping wrapper for register file.
+
+module alert_handler_reg_wrap import alert_pkg::*; (
+ input clk_i,
+ input rst_ni,
+ input rst_shadowed_ni,
+ // Bus Interface (device)
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // interrupt
+ output logic [N_CLASSES-1:0] irq_o,
+ // State information for HW crashdump
+ input [N_CLASSES-1:0] latch_crashdump_i,
+ output alert_crashdump_t crashdump_o,
+ // hw2reg
+ input hw2reg_wrap_t hw2reg_wrap,
+ // reg2hw
+ output reg2hw_wrap_t reg2hw_wrap,
+ // bus integrity alert
+ output logic fatal_integ_alert_o
+);
+
+
+ //////////////////
+ // reg instance //
+ //////////////////
+
+ logic [N_CLASSES-1:0] class_autolock_en;
+ alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw;
+ alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg;
+
+ alert_handler_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+ .rst_shadowed_ni,
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg,
+ .shadowed_storage_err_o(reg2hw_wrap.shadowed_err_storage),
+ .shadowed_update_err_o(reg2hw_wrap.shadowed_err_update),
+ .intg_err_o(fatal_integ_alert_o),
+ .devmode_i(1'b1)
+ );
+
+ ////////////////
+ // interrupts //
+ ////////////////
+
+ prim_intr_hw #(
+ .Width(1)
+ ) u_irq_classa (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i ( hw2reg_wrap.class_trig[0] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ),
+ .intr_o ( irq_o[0] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) u_irq_classb (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i ( hw2reg_wrap.class_trig[1] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ),
+ .intr_o ( irq_o[1] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) u_irq_classc (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i ( hw2reg_wrap.class_trig[2] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ),
+ .intr_o ( irq_o[2] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) u_irq_classd (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i ( hw2reg_wrap.class_trig[3] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ),
+ .intr_o ( irq_o[3] )
+ );
+
+ /////////////////////
+ // hw2reg mappings //
+ /////////////////////
+
+ // if an alert is enabled and it fires,
+ // we have to set the corresponding cause bit
+ for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause
+ assign hw2reg.alert_cause[k].d = 1'b1;
+ assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q |
+ hw2reg_wrap.alert_cause[k];
+ end
+
+ // if a local alert is enabled and it fires,
+ // we have to set the corresponding cause bit
+ for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause
+ assign hw2reg.loc_alert_cause[k].d = 1'b1;
+ assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q |
+ hw2reg_wrap.loc_alert_cause[k];
+ end
+
+ // ping timeout in cycles
+ // autolock can clear these regs automatically upon entering escalation
+ // note: the class must be activated for this to occur
+ assign { hw2reg.classd_clr_regwen.d,
+ hw2reg.classc_clr_regwen.d,
+ hw2reg.classb_clr_regwen.d,
+ hw2reg.classa_clr_regwen.d } = '0;
+
+ assign { hw2reg.classd_clr_regwen.de,
+ hw2reg.classc_clr_regwen.de,
+ hw2reg.classb_clr_regwen.de,
+ hw2reg.classa_clr_regwen.de } = hw2reg_wrap.class_esc_trig &
+ class_autolock_en &
+ reg2hw_wrap.class_en;
+
+ // current accumulator counts
+ assign { hw2reg.classd_accum_cnt.d,
+ hw2reg.classc_accum_cnt.d,
+ hw2reg.classb_accum_cnt.d,
+ hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt;
+
+ // current accumulator counts
+ assign { hw2reg.classd_esc_cnt.d,
+ hw2reg.classc_esc_cnt.d,
+ hw2reg.classb_esc_cnt.d,
+ hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt;
+
+ // current accumulator counts
+ assign { hw2reg.classd_state.d,
+ hw2reg.classc_state.d,
+ hw2reg.classb_state.d,
+ hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state;
+
+ /////////////////////
+ // reg2hw mappings //
+ /////////////////////
+
+ // config register lock
+ assign reg2hw_wrap.ping_enable = reg2hw.ping_timer_en_shadowed.q;
+
+ // alert enable and class assignments
+ for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_en_class
+ // we only ping enabled alerts that are locked
+ assign reg2hw_wrap.alert_ping_en[k] = reg2hw.alert_en_shadowed[k].q &
+ ~reg2hw.alert_regwen[k].q;
+ assign reg2hw_wrap.alert_en[k] = reg2hw.alert_en_shadowed[k].q;
+ assign reg2hw_wrap.alert_class[k] = reg2hw.alert_class_shadowed[k].q;
+ end
+
+ // local alert enable and class assignments
+ for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_en_class
+ assign reg2hw_wrap.loc_alert_en[k] = reg2hw.loc_alert_en_shadowed[k].q;
+ assign reg2hw_wrap.loc_alert_class[k] = reg2hw.loc_alert_class_shadowed[k].q;
+ end
+
+ assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc_shadowed.q;
+
+ // class enable
+ // we require that at least one of the enable signals is
+ // set for a class to be enabled
+ assign reg2hw_wrap.class_en = {
+ reg2hw.classd_ctrl_shadowed.en.q & ( reg2hw.classd_ctrl_shadowed.en_e3.q |
+ reg2hw.classd_ctrl_shadowed.en_e2.q |
+ reg2hw.classd_ctrl_shadowed.en_e1.q |
+ reg2hw.classd_ctrl_shadowed.en_e0.q ),
+ //
+ reg2hw.classc_ctrl_shadowed.en.q & ( reg2hw.classc_ctrl_shadowed.en_e3.q |
+ reg2hw.classc_ctrl_shadowed.en_e2.q |
+ reg2hw.classc_ctrl_shadowed.en_e1.q |
+ reg2hw.classc_ctrl_shadowed.en_e0.q ),
+ //
+ reg2hw.classb_ctrl_shadowed.en.q & ( reg2hw.classb_ctrl_shadowed.en_e3.q |
+ reg2hw.classb_ctrl_shadowed.en_e2.q |
+ reg2hw.classb_ctrl_shadowed.en_e1.q |
+ reg2hw.classb_ctrl_shadowed.en_e0.q ),
+ //
+ reg2hw.classa_ctrl_shadowed.en.q & ( reg2hw.classa_ctrl_shadowed.en_e3.q |
+ reg2hw.classa_ctrl_shadowed.en_e2.q |
+ reg2hw.classa_ctrl_shadowed.en_e1.q |
+ reg2hw.classa_ctrl_shadowed.en_e0.q )
+ };
+
+
+ // autolock enable
+ assign class_autolock_en = { reg2hw.classd_ctrl_shadowed.lock.q,
+ reg2hw.classc_ctrl_shadowed.lock.q,
+ reg2hw.classb_ctrl_shadowed.lock.q,
+ reg2hw.classa_ctrl_shadowed.lock.q };
+
+ // escalation signal enable
+ assign reg2hw_wrap.class_esc_en = { reg2hw.classd_ctrl_shadowed.en_e3.q,
+ reg2hw.classd_ctrl_shadowed.en_e2.q,
+ reg2hw.classd_ctrl_shadowed.en_e1.q,
+ reg2hw.classd_ctrl_shadowed.en_e0.q,
+ //
+ reg2hw.classc_ctrl_shadowed.en_e3.q,
+ reg2hw.classc_ctrl_shadowed.en_e2.q,
+ reg2hw.classc_ctrl_shadowed.en_e1.q,
+ reg2hw.classc_ctrl_shadowed.en_e0.q,
+ //
+ reg2hw.classb_ctrl_shadowed.en_e3.q,
+ reg2hw.classb_ctrl_shadowed.en_e2.q,
+ reg2hw.classb_ctrl_shadowed.en_e1.q,
+ reg2hw.classb_ctrl_shadowed.en_e0.q,
+ //
+ reg2hw.classa_ctrl_shadowed.en_e3.q,
+ reg2hw.classa_ctrl_shadowed.en_e2.q,
+ reg2hw.classa_ctrl_shadowed.en_e1.q,
+ reg2hw.classa_ctrl_shadowed.en_e0.q };
+
+
+ // escalation phase to escalation signal mapping
+ assign reg2hw_wrap.class_esc_map = { reg2hw.classd_ctrl_shadowed.map_e3.q,
+ reg2hw.classd_ctrl_shadowed.map_e2.q,
+ reg2hw.classd_ctrl_shadowed.map_e1.q,
+ reg2hw.classd_ctrl_shadowed.map_e0.q,
+ //
+ reg2hw.classc_ctrl_shadowed.map_e3.q,
+ reg2hw.classc_ctrl_shadowed.map_e2.q,
+ reg2hw.classc_ctrl_shadowed.map_e1.q,
+ reg2hw.classc_ctrl_shadowed.map_e0.q,
+ //
+ reg2hw.classb_ctrl_shadowed.map_e3.q,
+ reg2hw.classb_ctrl_shadowed.map_e2.q,
+ reg2hw.classb_ctrl_shadowed.map_e1.q,
+ reg2hw.classb_ctrl_shadowed.map_e0.q,
+ //
+ reg2hw.classa_ctrl_shadowed.map_e3.q,
+ reg2hw.classa_ctrl_shadowed.map_e2.q,
+ reg2hw.classa_ctrl_shadowed.map_e1.q,
+ reg2hw.classa_ctrl_shadowed.map_e0.q };
+
+ // Determines in which phase to latch the crashdump.
+ assign reg2hw_wrap.class_crashdump_phase = { reg2hw.classd_crashdump_trigger_shadowed.q,
+ reg2hw.classc_crashdump_trigger_shadowed.q,
+ reg2hw.classb_crashdump_trigger_shadowed.q,
+ reg2hw.classa_crashdump_trigger_shadowed.q };
+
+ // writing 1b1 to a class clr register clears the accumulator and
+ // escalation state if autolock is not asserted
+ assign reg2hw_wrap.class_clr = { reg2hw.classd_clr_shadowed.q & reg2hw.classd_clr_shadowed.qe,
+ reg2hw.classc_clr_shadowed.q & reg2hw.classc_clr_shadowed.qe,
+ reg2hw.classb_clr_shadowed.q & reg2hw.classb_clr_shadowed.qe,
+ reg2hw.classa_clr_shadowed.q & reg2hw.classa_clr_shadowed.qe };
+
+
+ // accumulator thresholds
+ assign reg2hw_wrap.class_accum_thresh = { reg2hw.classd_accum_thresh_shadowed.q,
+ reg2hw.classc_accum_thresh_shadowed.q,
+ reg2hw.classb_accum_thresh_shadowed.q,
+ reg2hw.classa_accum_thresh_shadowed.q };
+
+ // interrupt timeout lengths
+ assign reg2hw_wrap.class_timeout_cyc = { reg2hw.classd_timeout_cyc_shadowed.q,
+ reg2hw.classc_timeout_cyc_shadowed.q,
+ reg2hw.classb_timeout_cyc_shadowed.q,
+ reg2hw.classa_timeout_cyc_shadowed.q };
+ // escalation phase lengths
+ assign reg2hw_wrap.class_phase_cyc = { reg2hw.classd_phase3_cyc_shadowed.q,
+ reg2hw.classd_phase2_cyc_shadowed.q,
+ reg2hw.classd_phase1_cyc_shadowed.q,
+ reg2hw.classd_phase0_cyc_shadowed.q,
+ //
+ reg2hw.classc_phase3_cyc_shadowed.q,
+ reg2hw.classc_phase2_cyc_shadowed.q,
+ reg2hw.classc_phase1_cyc_shadowed.q,
+ reg2hw.classc_phase0_cyc_shadowed.q,
+ //
+ reg2hw.classb_phase3_cyc_shadowed.q,
+ reg2hw.classb_phase2_cyc_shadowed.q,
+ reg2hw.classb_phase1_cyc_shadowed.q,
+ reg2hw.classb_phase0_cyc_shadowed.q,
+ //
+ reg2hw.classa_phase3_cyc_shadowed.q,
+ reg2hw.classa_phase2_cyc_shadowed.q,
+ reg2hw.classa_phase1_cyc_shadowed.q,
+ reg2hw.classa_phase0_cyc_shadowed.q};
+
+ //////////////////////
+ // crashdump output //
+ //////////////////////
+
+ logic [N_CLASSES-1:0] crashdump_latched_q;
+ alert_crashdump_t crashdump_d, crashdump_q;
+
+ // alert cause output
+ for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump
+ assign crashdump_d.alert_cause[k] = reg2hw.alert_cause[k].q;
+ end
+
+ // local alert cause register output
+ for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause_dump
+ assign crashdump_d.loc_alert_cause[k] = reg2hw.loc_alert_cause[k].q;
+ end
+
+ assign crashdump_d.class_accum_cnt = hw2reg_wrap.class_accum_cnt;
+ assign crashdump_d.class_esc_cnt = hw2reg_wrap.class_esc_cnt;
+ assign crashdump_d.class_esc_state = hw2reg_wrap.class_esc_state;
+
+ // We latch the crashdump upon triggering any of the escalation protocols. The reason for this is
+ // that during escalation, certain alert senders may start to trigger due to FSMs being moved
+ // into escalation mode - thereby masking the actual alert reasons exposed in the cause
+ // registers.
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_crashdump
+ if (!rst_ni) begin
+ crashdump_latched_q <= '0;
+ crashdump_q <= '0;
+ end else begin
+ // We track which class has been escalated so that the crashdump latching mechanism cannot be
+ // re-armed by clearing another class that has not escalated yet. This also implies that if
+ // an unclearable class has escalated, the crashdump latching mechanism cannot be re-armed.
+ crashdump_latched_q <= (crashdump_latched_q & ~reg2hw_wrap.class_clr) | latch_crashdump_i;
+
+ // The alert handler only captures the first escalation event that asserts a latch_crashdump_i
+ // signal, unless all classes are cleared, in which case the crashdump latching mechanism is
+ // re-armed. In other words, we latch the crashdump if any of the latch_crashdump_i bits is
+ // asserted, and no crashdump has been latched yet.
+ if (|latch_crashdump_i && !(|crashdump_latched_q)) begin
+ crashdump_q <= crashdump_d;
+ end
+ end
+ end
+
+ // As long as the crashdump has not been latched yet, we output the current alert handler state.
+ // Once any of the classes has triggered the latching, we switch to the latched snapshot.
+ assign crashdump_o = (|crashdump_latched_q) ? crashdump_q : crashdump_d;
+
+endmodule : alert_handler_reg_wrap
diff --git a/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_pkg.sv b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_pkg.sv
new file mode 100644
index 0000000..ad102cb
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/alert_handler/rtl/alert_pkg.sv
@@ -0,0 +1,103 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package alert_pkg;
+
+ // these localparams are generated based on the system top-level configuration
+ localparam int unsigned NAlerts = alert_handler_reg_pkg::NAlerts; // maximum 252
+ localparam int unsigned EscCntDw = alert_handler_reg_pkg::EscCntDw; // maximum 32
+ localparam int unsigned AccuCntDw = alert_handler_reg_pkg::AccuCntDw; // maximum 32
+ localparam int unsigned NLpg = alert_handler_reg_pkg::NLpg;
+ localparam int unsigned NLpgWidth = alert_handler_reg_pkg::NLpgWidth;
+ localparam logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = alert_handler_reg_pkg::LpgMap;
+ // enable async transitions for specific RX/TX pairs
+ localparam bit [NAlerts-1:0] AsyncOn = alert_handler_reg_pkg::AsyncOn;
+
+ // common constants, do not change
+ localparam int unsigned N_CLASSES = alert_handler_reg_pkg::N_CLASSES;
+ localparam int unsigned N_ESC_SEV = alert_handler_reg_pkg::N_ESC_SEV;
+ localparam int unsigned N_PHASES = alert_handler_reg_pkg::N_PHASES;
+ localparam int unsigned N_LOC_ALERT = alert_handler_reg_pkg::N_LOC_ALERT;
+
+ localparam int unsigned PING_CNT_DW = alert_handler_reg_pkg::PING_CNT_DW;
+ localparam int unsigned PHASE_DW = alert_handler_reg_pkg::PHASE_DW;
+ localparam int unsigned CLASS_DW = alert_handler_reg_pkg::CLASS_DW;
+
+ // do not change the phase encoding
+ typedef enum logic [2:0] {Idle = 3'b000, Timeout = 3'b001, Terminal = 3'b011,
+ Phase0 = 3'b100, Phase1 = 3'b101, Phase2 = 3'b110,
+ Phase3 = 3'b111, FsmError = 3'b010} cstate_e;
+
+ // These LFSR parameters have been generated with
+ // $ util/design/gen-lfsr-seed.py --width 32 --seed 2700182644
+ localparam int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ localparam lfsr_seed_t RndCnstLfsrSeedDefault = 32'he96064e5;
+ localparam lfsr_perm_t RndCnstLfsrPermDefault =
+ 160'hebd1e5d4a1cee5afdb866a9c7a0278b899020d31;
+
+ // struct containing the current alert handler state
+ // can be used to gather crashdump information in HW
+ typedef struct packed {
+ // alerts
+ logic [NAlerts-1:0] alert_cause; // alert cause bits
+ logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits
+ // class state
+ logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value
+ logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value
+ cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state
+ } alert_crashdump_t;
+
+ // Default for dangling connection
+ parameter alert_crashdump_t ALERT_CRASHDUMP_DEFAULT = '{
+ alert_cause: '0,
+ loc_alert_cause: '0,
+ class_accum_cnt: '0,
+ class_esc_cnt: '0,
+ class_esc_state: {N_CLASSES{Idle}}
+ };
+
+ // breakout wrapper structs
+ typedef struct packed {
+ // alerts
+ logic [NAlerts-1:0] alert_cause; // alert cause bits
+ logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits
+ // class state
+ logic [N_CLASSES-1:0] class_trig; // class trigger
+ logic [N_CLASSES-1:0] class_esc_trig; // escalation trigger
+ logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value
+ logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value
+ cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state
+ } hw2reg_wrap_t;
+
+ typedef struct packed {
+ // aggregated shadow reg errors (trigger internal alerts)
+ logic shadowed_err_update;
+ logic shadowed_err_storage;
+ // ping config
+ logic ping_enable; // ping timer enable
+ logic [PING_CNT_DW-1:0] ping_timeout_cyc; // ping timeout config
+ logic [NAlerts-1:0] alert_ping_en; // ping enable for alerts
+ // alert config
+ logic [N_LOC_ALERT-1:0] loc_alert_en; // alert enable
+ logic [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class; // alert class config
+ logic [NAlerts-1:0] alert_en; // alert enable
+ logic [NAlerts-1:0][CLASS_DW-1:0] alert_class; // alert class config
+ // class config
+ logic [N_CLASSES-1:0] class_en; // enables esc mechanisms
+ logic [N_CLASSES-1:0] class_clr; // clears esc/accu
+ logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_thresh; // accum esc threshold
+ logic [N_CLASSES-1:0][EscCntDw-1:0] class_timeout_cyc; // interrupt timeout
+ logic [N_CLASSES-1:0][N_PHASES-1:0][EscCntDw-1:0] class_phase_cyc; // length of phases 0..3
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_en; // esc signal enables
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0][PHASE_DW-1:0] class_esc_map; // esc signal/phase map
+ // determines when to latch the crashdump output.
+ logic [N_CLASSES-1:0][PHASE_DW-1:0] class_crashdump_phase;
+ } reg2hw_wrap_t;
+
+endpackage : alert_pkg
+
+
diff --git a/hw/top_sencha/ip_autogen/rv_plic/README.md b/hw/top_sencha/ip_autogen/rv_plic/README.md
new file mode 100644
index 0000000..d642009
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/README.md
@@ -0,0 +1,247 @@
+# Interrupt Controller Technical Specification
+
+# Overview
+
+This document specifies the Interrupt Controller (RV_PLIC) functionality. This
+module conforms to the
+[Comportable guideline for peripheral functionality](../../../doc/contributing/hw/comportability/README.md).
+See that document for integration overview within the broader top level system.
+
+
+## Features
+
+- RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller
+- Support arbitrary number of interrupt vectors (up to 255) and targets
+- Support interrupt enable, interrupt status registers
+- Memory-mapped MSIP register per HART for software interrupt control.
+
+## Description
+
+The RV_PLIC module is designed to manage various interrupt sources from the
+peripherals. It receives interrupt events as either edge or level of the
+incoming interrupt signals (``intr_src_i``) and can notify multiple targets.
+
+## Compatibility
+
+The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
+
+# Theory of Operations
+
+## Block Diagram
+
+
+
+## Hardware Interfaces
+
+* [Interface Tables](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
+
+## Design Details
+
+### Identifier
+
+Each interrupt source has a unique ID assigned based upon its bit position
+within the input `intr_src_i`. ID ranges from 0 to N, the number of interrupt
+sources. ID 0 is reserved and represents no interrupt. The bit 0 of
+`intr_src_i` shall be tied to 0 from the outside of RV_PLIC. The
+`intr_src_i[i]` bit has an ID of `i`. This ID is used when targets "claim" the
+interrupt and to "complete" the interrupt event.
+
+### Priority and Threshold
+
+Interrupt sources have configurable priority values. The maximum value of the
+priority is configurable through the localparam `MAX_PRIO` in the rv_plic
+top-level module. For each target there is a threshold value ([`THRESHOLD0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#threshold0) for
+target 0). RV_PLIC notifies a target of an interrupt only if it's priority is
+strictly greater than the target's threshold. Note this means an interrupt with
+a priority is 0 is effectively prevented from causing an interrupt at any target
+and a target can suppress all interrupts by setting it's threshold to the max
+priority value.
+
+`MAX_PRIO` parameter is most area contributing option in RV_PLIC. If `MAX_PRIO`
+is big, then finding the highest priority in Process module may consume a lot of
+logic gates.
+
+### Interrupt Gateways
+
+The Gateway observes incoming interrupt sources and converts them to a common
+interrupt format used internally by RV_PLIC. It can be parameterized to detect
+interrupts events on an edge (when the signal changes from **0** to **1**) or
+level basis (where the signal remains at **1**).
+The choice is a system-integration decision and can be configured via the design parameter `LevelEdgeTrig` for each interrupt request.
+
+When the gateway detects an interrupt event it raises the interrupt pending bit
+([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the
+relevant bit of [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) will not be reasserted until the
+target signals completion of the interrupt. Any new interrupt event between a
+bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular
+this means that for edge triggered interrupts if a new edge is seen after the
+source's [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored
+(counting missed edges as discussed in the RISC-V PLIC specification is not
+supported).
+
+Note that there is no ability for a level triggered interrupt to be cancelled.
+If the interrupt drops after the gateway has set a bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip), the bit will
+remain set until the interrupt is completed. The SW handler should be conscious
+of this and check the interrupt still requires handling in the handler if this
+behaviour is possible.
+
+### Interrupt Enables
+
+Each target has a set of Interrupt Enable ([`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) for target 0) registers. Each
+bit in the [`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an
+interrupt source is disabled for a target, then interrupt events from that
+source won't trigger an interrupt at the target. RV_PLIC doesn't have a global
+interrupt disable feature.
+
+### Interrupt Claims
+
+"Claiming" an interrupt is done by a target reading the associated
+Claim/Completion register for the target ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The return value
+of the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the
+highest priority. If two or more pending interrupts have the same priority,
+RV_PLIC chooses the one with lowest ID. Only interrupts that that are enabled
+for the target can be claimed. The target priority threshold doesn't matter
+(this only factors into whether an interrupt is signalled to the target) so
+lower priority interrupt IDs can be returned on a read from [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0). If no
+interrupt is pending (or all pending interrupts are disabled for the target) a
+read of [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) returns an ID of 0.
+
+### Interrupt Completion
+
+After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) is
+cleared, regardless of the status of the `intr_src_i` input value. Until a
+target "completes" the interrupt, it won't be re-asserted if a new event for the
+interrupt occurs. A target completes the interrupt by writing the ID of the
+interrupt to the Claim/Complete register ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The write event
+is forwarded to the Gateway logic, which resets the interrupt status to accept a
+new interrupt event. The assumption is that the processor has cleaned up the
+originating interrupt event during the time between claim and complete such that
+`intr_src_i[ID]` will have de-asserted (unless a new interrupt has occurred).
+
+```wavejson
+{ signal: [
+ { name: 'clk', wave: 'p...........' },
+ { name: 'intr_src_i[i]', wave: '01....0.1...', node:'.a....e.f...'},
+ { name: 'irq_o', wave: '0.1.0......1', node:'..b.d......h'},
+ { name: 'irq_id_o', wave: '=.=.=......=',
+ data: ["0","i","0","i"] },
+ { name: 'claim', wave: '0..10.......', node:'...c........'},
+ { name: 'complete', wave: '0.........10', node:'..........g.'},
+ ],
+ head:{
+ text: 'Interrupt Flow',
+ tick: 0,
+ },
+}
+```
+
+In the example above an interrupt for source ID `i` is configured as a level
+interrupt and is raised at a, this results in the target being notified of the
+interrupt at b. The target claims the interrupt at c (reading `i` from it's
+Claim/Complete register) so `irq_o` deasserts though `intr_src_i[i]` remains
+raised. The SW handles the interrupt and it drops at e. However a new interrupt
+quickly occurs at f. As complete hasn't been signaled yet `irq_o` isn't
+asserted. At g the interrupt is completed (by writing `i` to it's
+Claim/Complete register) so at h `irq_o` is asserted due to the new interrupt.
+
+
+# Programmers Guide
+
+## Initialization
+
+After reset, RV_PLIC doesn't generate any interrupts to any targets even if
+interrupt sources are set, as all priorities and thresholds are 0 by default and
+all ``IE`` values are 0. Software should configure the above three registers.
+
+[`PRIO0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio0) .. [`PRIO31`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio1) registers are unique. So, only one of the targets
+shall configure them.
+
+```c
+// Pseudo-code below
+void plic_init() {
+ // Configure priority
+ // Note that PRIO0 register doesn't affect as intr_src_i[0] is tied to 0.
+ for (int i = 0; i < N_SOURCE; ++i) {
+ *(PRIO + i) = value(i);
+ }
+}
+
+void plic_threshold(tid, threshold) {
+ *(THRESHOLD + tid) = threshold;
+}
+
+void plic_enable(tid, iid) {
+ // iid: 0-based ID
+ int offset = ceil(N_SOURCE / 32) * tid + (iid >> 5);
+
+ *(IE + offset) = *(IE + offset) | (1 << (iid % 32));
+}
+```
+
+## Handling Interrupt Request Events
+
+If software receives an interrupt request, it is recommended to follow the steps
+shown below (assuming target 0 which uses [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for claim/complete).
+
+1. Claim the interrupts right after entering to the interrupt service routine
+ by reading the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
+2. Determine which interrupt should be serviced based on the values read from
+ the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
+3. Execute ISR, clearing the originating peripheral interrupt.
+4. Write Interrupt ID to [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0)
+5. Repeat as necessary for other pending interrupts.
+
+It is possible to have multiple interrupt events claimed. If software claims one
+interrupt request, then the process module advertises any pending interrupts
+with lower priority unless new higher priority interrupt events occur. If a
+higher interrupt event occurs after previous interrupt is claimed, the RV_PLIC
+IP advertises the higher priority interrupt. Software may utilize an event
+manager inside a loop so that interrupt claiming and completion can be
+separated.
+
+~~~~c
+void interrupt_service() {
+ uint32_t tid = /* ... */;
+ uint32_t iid = *(CC + tid);
+ if (iid == 0) {
+ // Interrupt is claimed by one of other targets.
+ return;
+ }
+
+ do {
+ // Process interrupts...
+ // ...
+
+ // Finish.
+ *(CC + tid) = iid;
+ iid = *(CC + tid);
+ } while (iid != 0);
+}
+~~~~
+
+As a reference, default interrupt service routines are auto-generated for each
+IP, and are documented [here](/sw/apis/isr__testutils_8h.html).
+
+## Device Interface Functions (DIFs)
+
+- [Device Interface Functions](../../../sw/device/lib/dif/dif_rv_plic.h)
+
+## Registers
+
+The RV_PLIC in the top level is generated by topgen tool so that the number of
+interrupt sources may be different.
+
+- IE: CEILING(N_SOURCE / DW) X N_TARGET
+ Each bit enables corresponding interrupt source. Each target has IE set.
+- PRIO: N_SOURCE
+ Universal set across all targets. Lower n bits are valid. n is determined by
+ MAX_PRIO parameter
+- THRESHOLD: N_TARGET
+ Priority threshold per target. Only priority of the interrupt greater than
+ threshold can raise interrupt notification to the target.
+- IP: CEILING(N_SOURCE / DW)
+ Pending bits right after the gateways. Read-only
+- CC: N_TARGET
+ Claim by read, complete by write
+
+* [Register Table](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
diff --git a/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic.hjson
new file mode 100644
index 0000000..52bbf26
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic.hjson
@@ -0,0 +1,1744 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# RV_PLIC register template
+#
+# Parameter (given by Python tool)
+# - src: Number of Interrupt Sources
+# - target: Number of Targets that handle interrupt requests
+# - prio: Max value of interrupt priorities
+# - module_instance_name: Module instance name.
+{
+ name: "rv_plic",
+ design_spec: "../doc",
+ dv_doc: "../doc/dv",
+ hw_checklist: "../doc/checklist",
+ sw_checklist: "/sw/device/lib/dif/dif_rv_plic",
+ revisions: [
+ {
+ version: "1.0",
+ life_stage: "L1",
+ design_stage: "D3",
+ verification_stage: "V2",
+ dif_stage: "S2",
+ commit_id: "",
+ notes: "Use FPV to perform block level verification.",
+ }
+ ],
+ clocking: [{clock: "clk_i", reset: "rst_ni"}],
+ bus_interfaces: [
+ { protocol: "tlul", direction: "device" }
+ ],
+
+ param_list: [
+ { name: "NumSrc",
+ desc: "Number of interrupt sources",
+ type: "int",
+ default: "190",
+ local: "true"
+ },
+ { name: "NumTarget",
+ desc: "Number of Targets (Harts)",
+ type: "int",
+ default: "2",
+ local: "true",
+ },
+ { name: "PrioWidth",
+ desc: "Width of priority signals",
+ type: "int",
+ default: "2",
+ local: "true",
+ },
+ ],
+
+ // In order to not disturb the PLIC address map, we place the alert test
+ // register manually at a safe offset after the main CSRs.
+ no_auto_alert_regs: "True",
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ '''
+ }
+ ],
+
+ inter_signal_list: [
+ { struct: "logic",
+ type: "uni",
+ name: "irq",
+ act: "req",
+ package: "",
+ width: "2"
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "irq_id",
+ act: "req",
+ package: "",
+ },
+
+ { struct: "logic",
+ type: "uni",
+ name: "msip",
+ act: "req",
+ package: "",
+ width: "2"
+ },
+ ]
+
+ countermeasures: [
+ { name: "BUS.INTEGRITY",
+ desc: "End-to-end bus integrity scheme."
+ }
+ ]
+
+ regwidth: "32",
+ registers: [
+ { name: "PRIO0",
+ desc: "Interrupt Source 0 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO1",
+ desc: "Interrupt Source 1 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO2",
+ desc: "Interrupt Source 2 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO3",
+ desc: "Interrupt Source 3 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO4",
+ desc: "Interrupt Source 4 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO5",
+ desc: "Interrupt Source 5 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO6",
+ desc: "Interrupt Source 6 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO7",
+ desc: "Interrupt Source 7 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO8",
+ desc: "Interrupt Source 8 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO9",
+ desc: "Interrupt Source 9 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO10",
+ desc: "Interrupt Source 10 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO11",
+ desc: "Interrupt Source 11 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO12",
+ desc: "Interrupt Source 12 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO13",
+ desc: "Interrupt Source 13 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO14",
+ desc: "Interrupt Source 14 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO15",
+ desc: "Interrupt Source 15 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO16",
+ desc: "Interrupt Source 16 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO17",
+ desc: "Interrupt Source 17 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO18",
+ desc: "Interrupt Source 18 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO19",
+ desc: "Interrupt Source 19 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO20",
+ desc: "Interrupt Source 20 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO21",
+ desc: "Interrupt Source 21 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO22",
+ desc: "Interrupt Source 22 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO23",
+ desc: "Interrupt Source 23 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO24",
+ desc: "Interrupt Source 24 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO25",
+ desc: "Interrupt Source 25 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO26",
+ desc: "Interrupt Source 26 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO27",
+ desc: "Interrupt Source 27 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO28",
+ desc: "Interrupt Source 28 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO29",
+ desc: "Interrupt Source 29 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO30",
+ desc: "Interrupt Source 30 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO31",
+ desc: "Interrupt Source 31 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO32",
+ desc: "Interrupt Source 32 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO33",
+ desc: "Interrupt Source 33 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO34",
+ desc: "Interrupt Source 34 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO35",
+ desc: "Interrupt Source 35 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO36",
+ desc: "Interrupt Source 36 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO37",
+ desc: "Interrupt Source 37 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO38",
+ desc: "Interrupt Source 38 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO39",
+ desc: "Interrupt Source 39 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO40",
+ desc: "Interrupt Source 40 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO41",
+ desc: "Interrupt Source 41 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO42",
+ desc: "Interrupt Source 42 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO43",
+ desc: "Interrupt Source 43 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO44",
+ desc: "Interrupt Source 44 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO45",
+ desc: "Interrupt Source 45 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO46",
+ desc: "Interrupt Source 46 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO47",
+ desc: "Interrupt Source 47 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO48",
+ desc: "Interrupt Source 48 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO49",
+ desc: "Interrupt Source 49 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO50",
+ desc: "Interrupt Source 50 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO51",
+ desc: "Interrupt Source 51 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO52",
+ desc: "Interrupt Source 52 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO53",
+ desc: "Interrupt Source 53 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO54",
+ desc: "Interrupt Source 54 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO55",
+ desc: "Interrupt Source 55 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO56",
+ desc: "Interrupt Source 56 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO57",
+ desc: "Interrupt Source 57 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO58",
+ desc: "Interrupt Source 58 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO59",
+ desc: "Interrupt Source 59 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO60",
+ desc: "Interrupt Source 60 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO61",
+ desc: "Interrupt Source 61 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO62",
+ desc: "Interrupt Source 62 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO63",
+ desc: "Interrupt Source 63 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO64",
+ desc: "Interrupt Source 64 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO65",
+ desc: "Interrupt Source 65 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO66",
+ desc: "Interrupt Source 66 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO67",
+ desc: "Interrupt Source 67 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO68",
+ desc: "Interrupt Source 68 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO69",
+ desc: "Interrupt Source 69 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO70",
+ desc: "Interrupt Source 70 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO71",
+ desc: "Interrupt Source 71 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO72",
+ desc: "Interrupt Source 72 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO73",
+ desc: "Interrupt Source 73 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO74",
+ desc: "Interrupt Source 74 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO75",
+ desc: "Interrupt Source 75 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO76",
+ desc: "Interrupt Source 76 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO77",
+ desc: "Interrupt Source 77 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO78",
+ desc: "Interrupt Source 78 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO79",
+ desc: "Interrupt Source 79 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO80",
+ desc: "Interrupt Source 80 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO81",
+ desc: "Interrupt Source 81 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO82",
+ desc: "Interrupt Source 82 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO83",
+ desc: "Interrupt Source 83 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO84",
+ desc: "Interrupt Source 84 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO85",
+ desc: "Interrupt Source 85 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO86",
+ desc: "Interrupt Source 86 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO87",
+ desc: "Interrupt Source 87 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO88",
+ desc: "Interrupt Source 88 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO89",
+ desc: "Interrupt Source 89 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO90",
+ desc: "Interrupt Source 90 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO91",
+ desc: "Interrupt Source 91 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO92",
+ desc: "Interrupt Source 92 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO93",
+ desc: "Interrupt Source 93 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO94",
+ desc: "Interrupt Source 94 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO95",
+ desc: "Interrupt Source 95 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO96",
+ desc: "Interrupt Source 96 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO97",
+ desc: "Interrupt Source 97 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO98",
+ desc: "Interrupt Source 98 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO99",
+ desc: "Interrupt Source 99 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO100",
+ desc: "Interrupt Source 100 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO101",
+ desc: "Interrupt Source 101 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO102",
+ desc: "Interrupt Source 102 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO103",
+ desc: "Interrupt Source 103 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO104",
+ desc: "Interrupt Source 104 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO105",
+ desc: "Interrupt Source 105 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO106",
+ desc: "Interrupt Source 106 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO107",
+ desc: "Interrupt Source 107 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO108",
+ desc: "Interrupt Source 108 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO109",
+ desc: "Interrupt Source 109 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO110",
+ desc: "Interrupt Source 110 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO111",
+ desc: "Interrupt Source 111 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO112",
+ desc: "Interrupt Source 112 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO113",
+ desc: "Interrupt Source 113 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO114",
+ desc: "Interrupt Source 114 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO115",
+ desc: "Interrupt Source 115 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO116",
+ desc: "Interrupt Source 116 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO117",
+ desc: "Interrupt Source 117 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO118",
+ desc: "Interrupt Source 118 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO119",
+ desc: "Interrupt Source 119 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO120",
+ desc: "Interrupt Source 120 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO121",
+ desc: "Interrupt Source 121 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO122",
+ desc: "Interrupt Source 122 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO123",
+ desc: "Interrupt Source 123 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO124",
+ desc: "Interrupt Source 124 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO125",
+ desc: "Interrupt Source 125 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO126",
+ desc: "Interrupt Source 126 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO127",
+ desc: "Interrupt Source 127 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO128",
+ desc: "Interrupt Source 128 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO129",
+ desc: "Interrupt Source 129 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO130",
+ desc: "Interrupt Source 130 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO131",
+ desc: "Interrupt Source 131 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO132",
+ desc: "Interrupt Source 132 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO133",
+ desc: "Interrupt Source 133 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO134",
+ desc: "Interrupt Source 134 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO135",
+ desc: "Interrupt Source 135 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO136",
+ desc: "Interrupt Source 136 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO137",
+ desc: "Interrupt Source 137 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO138",
+ desc: "Interrupt Source 138 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO139",
+ desc: "Interrupt Source 139 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO140",
+ desc: "Interrupt Source 140 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO141",
+ desc: "Interrupt Source 141 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO142",
+ desc: "Interrupt Source 142 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO143",
+ desc: "Interrupt Source 143 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO144",
+ desc: "Interrupt Source 144 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO145",
+ desc: "Interrupt Source 145 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO146",
+ desc: "Interrupt Source 146 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO147",
+ desc: "Interrupt Source 147 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO148",
+ desc: "Interrupt Source 148 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO149",
+ desc: "Interrupt Source 149 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO150",
+ desc: "Interrupt Source 150 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO151",
+ desc: "Interrupt Source 151 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO152",
+ desc: "Interrupt Source 152 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO153",
+ desc: "Interrupt Source 153 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO154",
+ desc: "Interrupt Source 154 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO155",
+ desc: "Interrupt Source 155 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO156",
+ desc: "Interrupt Source 156 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO157",
+ desc: "Interrupt Source 157 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO158",
+ desc: "Interrupt Source 158 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO159",
+ desc: "Interrupt Source 159 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO160",
+ desc: "Interrupt Source 160 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO161",
+ desc: "Interrupt Source 161 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO162",
+ desc: "Interrupt Source 162 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO163",
+ desc: "Interrupt Source 163 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO164",
+ desc: "Interrupt Source 164 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO165",
+ desc: "Interrupt Source 165 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO166",
+ desc: "Interrupt Source 166 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO167",
+ desc: "Interrupt Source 167 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO168",
+ desc: "Interrupt Source 168 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO169",
+ desc: "Interrupt Source 169 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO170",
+ desc: "Interrupt Source 170 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO171",
+ desc: "Interrupt Source 171 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO172",
+ desc: "Interrupt Source 172 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO173",
+ desc: "Interrupt Source 173 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO174",
+ desc: "Interrupt Source 174 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO175",
+ desc: "Interrupt Source 175 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO176",
+ desc: "Interrupt Source 176 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO177",
+ desc: "Interrupt Source 177 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO178",
+ desc: "Interrupt Source 178 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO179",
+ desc: "Interrupt Source 179 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO180",
+ desc: "Interrupt Source 180 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO181",
+ desc: "Interrupt Source 181 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO182",
+ desc: "Interrupt Source 182 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO183",
+ desc: "Interrupt Source 183 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO184",
+ desc: "Interrupt Source 184 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO185",
+ desc: "Interrupt Source 185 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO186",
+ desc: "Interrupt Source 186 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO187",
+ desc: "Interrupt Source 187 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO188",
+ desc: "Interrupt Source 188 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO189",
+ desc: "Interrupt Source 189 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { skipto: "0x00001000" }
+ { multireg: {
+ name: "IP",
+ desc: "Interrupt Pending",
+ count: "NumSrc",
+ cname: "RV_PLIC",
+ swaccess: "ro",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "P", desc: "Interrupt Pending of Source" }
+ ],
+ tags: [// IP is driven by intr_src, cannot auto-predict
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ }
+ },
+ { skipto: "0x2000" }
+ { multireg: {
+ name: "IE0",
+ desc: "Interrupt Enable for Target 0",
+ count: "NumSrc",
+ cname: "RV_PLIC",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0", name: "E", desc: "Interrupt Enable of Source" }
+ ],
+ }
+ }
+ { skipto: "0x2100" }
+ { multireg: {
+ name: "IE1",
+ desc: "Interrupt Enable for Target 1",
+ count: "NumSrc",
+ cname: "RV_PLIC",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0", name: "E", desc: "Interrupt Enable of Source" }
+ ],
+ }
+ }
+ { skipto: "0x200000" }
+ { name: "THRESHOLD0",
+ desc: "Threshold of priority for Target 0",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "CC0",
+ desc: '''Claim interrupt by read, complete interrupt by write for Target 0.
+ Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ hwre: "true",
+ fields: [
+ { bits: "7:0" }
+ ],
+ tags: [// CC register value is related to IP
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ }
+ { skipto: "0x201000" }
+ { name: "THRESHOLD1",
+ desc: "Threshold of priority for Target 1",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "CC1",
+ desc: '''Claim interrupt by read, complete interrupt by write for Target 1.
+ Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''',
+ swaccess: "rw",
+ hwaccess: "hrw",
+ hwext: "true",
+ hwqe: "true",
+ hwre: "true",
+ fields: [
+ { bits: "7:0" }
+ ],
+ tags: [// CC register value is related to IP
+ "excl:CsrNonInitTests:CsrExclCheck"],
+ }
+ { skipto: "0x4000000" }
+ { name: "MSIP0",
+ desc: '''msip for Hart 0.
+ Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ desc: "Software Interrupt Pending register",
+ }
+ ],
+ }
+ { name: "MSIP1",
+ desc: '''msip for Hart 1.
+ Write 1 to here asserts software interrupt for Hart msip_o[1], write 0 to clear.''',
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ desc: "Software Interrupt Pending register",
+ }
+ ],
+ }
+ { skipto: "0x4004000" }
+ { name: "ALERT_TEST",
+ desc: '''Alert Test Register.''',
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "True",
+ hwext: "True",
+ fields: [
+ { bits: "0",
+ name: "fatal_fault",
+ desc: "'Write 1 to trigger one alert event of this kind.'",
+ }
+ ],
+ }
+ ],
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson
new file mode 100644
index 0000000..1e1d2d2
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson
@@ -0,0 +1,88 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "rv_plic"
+ import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"]
+ testpoints: [
+ {
+ name: LevelTriggeredIp_A
+ desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+ level triggered (`le=0`), then in the prvious clock cycle, the interrupt source
+ (`intr_src_i) should be set to 1.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: EdgeTriggeredIp_A
+ desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+ edge triggered (`le=1`), then in the prvious clock cycle, the interrupt source
+ (`intr_src_i) should be at the rising edge.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: LevelTriggeredIpWithClaim_A
+ desc: '''If `intr_src_i` is set to 1, level indicator is set to level triggered, and claim
+ signal is not set, then at the next clock cycle `ip` will be triggered.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: EdgeTriggeredIpWithClaim_A
+ desc: '''If `intr_src_i` is at the rising edge, level indicator is set to edge triggered, and claim
+ signal is not set, then at the next clock cycle `ip` will be triggered.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: IpStableAfterTriggered_A
+ desc: "Once `ip` is set, it stays stable until is being claimed."
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: IpClearAfterClaim_A
+ desc: "Once `ip` is set and being claimed, its value is cleared to 0."
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: IpStableAfterClaimed_A
+ desc: '''Once `ip` is cleared to 0, it stays stable until completed and being triggered
+ again.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: TriggerIrqForwardCheck_A
+ desc: '''If interrupt is enabled (`ie=1`), interrupt pending is set (`ip=1`), interrupt
+ input has the highest priority among the rest of the inputs, and its priority is
+ above the threshold. Then in the next clock clcye, the `irq_o` should be triggered,
+ and the `irq_id_o` will reflect the input ID.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ {
+ name: TriggerIrqBackwardCheck_A
+ desc: '''If `irq_o` is set to 1, then in the previous clock cycle, the corresponding
+ `ip` should be set, `ie` should be enabled, and the interrupt source should above the
+ threshold and have the highest priority.'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+
+ }
+ {
+ name: IdChangeWithIrq_A
+ desc: '''If `irq_id_o` signal is changed and the signal does not change to 0 (value 0 does
+ not represent any interrupt source ID). Then either of the two condition should have
+ happened:
+ - `irq_o` is triggered
+ - No interrupt triggered, `ip` is set and `ie` is enabled, interrupt source priority is the
+ largest among the rest of the interrupt, but the interrupt source
+ priority is smaller than the threshold'''
+ stage: V2
+ tests: ["rv_plic_assert"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson
new file mode 100644
index 0000000..bdee6a1
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../rv_plic/data/rv_plic.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../rv_plic/data/rv_plic_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic/data/top_sencha_rv_plic.ipconfig.hjson b/hw/top_sencha/ip_autogen/rv_plic/data/top_sencha_rv_plic.ipconfig.hjson
new file mode 100644
index 0000000..1905c7f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/data/top_sencha_rv_plic.ipconfig.hjson
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ instance_name: top_sencha_rv_plic
+ param_values:
+ {
+ prio: 3
+ src: 190
+ target: 2
+ }
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson b/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson
new file mode 100644
index 0000000..0a6a12b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+ unreachable:
+ [
+ rv_plic_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1
+ rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1
+ rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_fpv.core b/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_fpv.core
new file mode 100644
index 0000000..67b9e4e
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/fpv/rv_plic_fpv.core
@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_rv_plic_fpv:0.1
+description: "FPV for RISC-V PLIC"
+
+filesets:
+ files_formal:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:opentitan:top_sencha_rv_plic
+ - lowrisc:fpv:csr_assert_gen
+ files:
+ - tb/rv_plic_bind_fpv.sv
+ - tb/rv_plic_tb.sv
+ - vip/rv_plic_assert_fpv.sv
+ file_type: systemVerilogSource
+
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../data/rv_plic.hjson
+ depend: lowrisc:opentitan:top_sencha_rv_plic
+
+targets:
+ default: &default_target
+ # note, this setting is just used
+ # to generate a file list for jg
+ default_tool: icarus
+ filesets:
+ - files_formal
+ generate:
+ - csr_assert_gen
+ toplevel: rv_plic_tb
+
+ formal:
+ <<: *default_target
+
+ lint:
+ <<: *default_target
diff --git a/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv b/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv
new file mode 100644
index 0000000..ab3d149
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv
@@ -0,0 +1,47 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module rv_plic_bind_fpv;
+
+ import rv_plic_reg_pkg::*;
+
+ bind rv_plic rv_plic_assert_fpv #(
+ .NumSrc(rv_plic_reg_pkg::NumSrc),
+ .NumTarget(rv_plic_reg_pkg::NumTarget),
+ .NumAlerts(rv_plic_reg_pkg::NumAlerts),
+ .PRIOW(rv_plic_reg_pkg::PrioWidth)
+ ) rv_plic_assert_fpv(
+ .clk_i,
+ .rst_ni,
+ .intr_src_i,
+ .alert_rx_i,
+ .alert_tx_o,
+ .irq_o,
+ .irq_id_o,
+ .msip_o,
+ .ip,
+ .ie,
+ .claim,
+ .complete,
+ .prio,
+ .threshold
+ );
+
+ bind rv_plic tlul_assert #(
+ .EndpointType("Device")
+ ) tlul_assert_device (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+ bind rv_plic rv_plic_csr_assert_fpv rv_plic_csr_assert_fpv (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+endmodule : rv_plic_bind_fpv
diff --git a/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv b/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
new file mode 100644
index 0000000..37ebbf1
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
@@ -0,0 +1,40 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Testbench module for rv_plic. Intended to use with a formal tool.
+
+module rv_plic_tb import rv_plic_reg_pkg::*; #(
+ // test all implementations
+ localparam int unsigned NumInstances = 1
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
+ output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
+ input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
+ input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
+ output [NumInstances-1:0][NumTarget-1:0] irq_o,
+ output [$clog2(NumSrc)-1:0] irq_id_o [NumInstances][NumTarget],
+ output logic [NumInstances-1:0][NumTarget-1:0] msip_o
+);
+
+ // TODO: once the PLIC is fully parameterizable in RTL, generate
+ // several instances with different NumSrc and NumTarget configs here
+ // (in a similar way as this has been done in prim_lfsr_fpv)
+ // for (genvar k = 0; k < NumInstances; k++) begin : geNumInstances
+ rv_plic dut (
+ .clk_i ,
+ .rst_ni ,
+ .tl_i (tl_i[0]),
+ .tl_o (tl_o[0]),
+ .intr_src_i (intr_src_i[0]),
+ .alert_rx_i (alert_rx_i[0]),
+ .alert_tx_o (alert_tx_o[0]),
+ .irq_o (irq_o[0]),
+ .irq_id_o (irq_id_o[0]),
+ .msip_o (msip_o[0])
+ );
+
+endmodule : rv_plic_tb
diff --git a/hw/top_sencha/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv b/hw/top_sencha/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv
new file mode 100644
index 0000000..f7c4392
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv
@@ -0,0 +1,104 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+// Testbench module for rv_plic. Intended to use with a formal tool.
+
+`include "prim_assert.sv"
+
+module rv_plic_assert_fpv #(parameter int NumSrc = 1,
+ parameter int NumTarget = 1,
+ parameter int NumAlerts = 1,
+ parameter int PRIOW = $clog2(7+1)
+) (
+ input clk_i,
+ input rst_ni,
+ input [NumSrc-1:0] intr_src_i,
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ input prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+ input [NumTarget-1:0] irq_o,
+ input [$clog2(NumSrc)-1:0] irq_id_o [NumTarget],
+ input [NumTarget-1:0] msip_o,
+ // probe design signals
+ input [NumSrc-1:0] ip,
+ input [NumSrc-1:0] ie [NumTarget],
+ input [NumSrc-1:0] claim,
+ input [NumSrc-1:0] complete,
+ input [NumSrc-1:0][PRIOW-1:0] prio,
+ input [PRIOW-1:0] threshold [NumTarget]
+);
+
+ logic claim_reg, claimed;
+ logic max_priority;
+ logic irq;
+ logic [$clog2(NumSrc)-1:0] i_high_prio;
+
+ // symbolic variables
+ int unsigned src_sel;
+ int unsigned tgt_sel;
+
+ `ASSUME_FPV(IsrcRange_M, src_sel > 0 && src_sel < NumSrc, clk_i, !rst_ni)
+ `ASSUME_FPV(ItgtRange_M, tgt_sel >= 0 && tgt_sel < NumTarget, clk_i, !rst_ni)
+ `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni)
+ `ASSUME_FPV(ItgtStable_M, ##1 $stable(tgt_sel), clk_i, !rst_ni)
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ claim_reg <= 1'b0;
+ end else if (claim[src_sel]) begin
+ claim_reg <= 1'b1;
+ end else if (complete[src_sel]) begin
+ claim_reg <= 1'b0;
+ end
+ end
+
+ assign claimed = claim_reg || claim[src_sel];
+
+ always_comb begin
+ max_priority = 1'b1;
+ for (int i = 0; i < NumSrc; i++) begin
+ // conditions that if src_sel has the highest priority with the lowest ID
+ if (i != src_sel && ip[i] && ie[tgt_sel][i] &&
+ (prio[i] > prio[src_sel] || (prio[i] == prio[src_sel] && i < src_sel))) begin
+ max_priority = 1'b0;
+ break;
+ end
+ end
+ end
+
+ always_comb begin
+ automatic logic [31:0] max_prio = 0;
+ for (int i = NumSrc-1; i >= 0; i--) begin
+ if (ip[i] && ie[tgt_sel][i] && prio[i] >= max_prio) begin
+ max_prio = prio[i];
+ i_high_prio = i; // i is the smallest id if have IPs with the same priority
+ end
+ end
+ if (max_prio > threshold[tgt_sel]) irq = 1'b1;
+ else irq = 1'b0;
+ end
+
+ // when IP is set, previous cycle should follow edge or level triggered criteria
+ `ASSERT(LevelTriggeredIp_A, ##3 $rose(ip[src_sel]) |-> $past(intr_src_i[src_sel], 3))
+
+ // when interrupt is trigger, and nothing claimed yet, then next cycle should assert IP.
+ `ASSERT(LevelTriggeredIpWithClaim_A, ##2 $past(intr_src_i[src_sel], 2) &&
+ !claimed |=> ip[src_sel])
+
+ // ip stays stable until claimed, reset to 0 after claimed, and stays 0 until complete
+ `ASSERT(IpStableAfterTriggered_A, ip[src_sel] && !claimed |=> ip[src_sel])
+ `ASSERT(IpClearAfterClaim_A, ip[src_sel] && claim[src_sel] |=> !ip[src_sel])
+ `ASSERT(IpStableAfterClaimed_A, claimed |=> !ip[src_sel])
+
+ // when ip is set and priority is the largest and above threshold, and interrupt enable is set,
+ // assertion irq_o at next cycle
+ `ASSERT(TriggerIrqForwardCheck_A, ip[src_sel] && prio[src_sel] > threshold[tgt_sel] &&
+ max_priority && ie[tgt_sel][src_sel] |=> irq_o[tgt_sel])
+
+ `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[tgt_sel]) |->
+ $past(irq) && (irq_id_o[tgt_sel] == $past(i_high_prio)))
+
+ // when irq ID changed, but not to ID=0, irq_o should be high, or irq represents the largest prio
+ // but smaller than the threshold
+ `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[tgt_sel]) && irq_id_o[tgt_sel] != 0 |->
+ irq_o[tgt_sel] || ((irq_id_o[tgt_sel]) == $past(i_high_prio) && !$past(irq)))
+endmodule : rv_plic_assert_fpv
diff --git a/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.vlt b/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.vlt
new file mode 100644
index 0000000..6ea47cd
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.vlt
@@ -0,0 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for rv_plic
+
+`verilator_config
diff --git a/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.waiver b/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.waiver
new file mode 100644
index 0000000..424a64a
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/lint/rv_plic.waiver
@@ -0,0 +1,22 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for Platform-Level Interrupt Controller
+
+waive -rules ONE_BIT_MEM_WIDTH -location {rv_plic.sv} -regexp {Memory '(claim_re|complete_we)' has} \
+ -comment "N_TARGET can be 1."
+
+waive -rules VAR_INDEX_RANGE -location {rv_plic.sv} -regexp {(claim_id|complete_id).* (maximum|minimum) value} \
+ -comment "Claim ID is guarded inside target module, complete ID has undeterministic behavior if FW writes OOR value"
+
+waive -rules HIER_NET_NOT_READ -location {rv_plic.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \
+ -comment "Register interface doesn't use upper address and param, user filed"
+
+waive -rules EXPLICIT_BITLEN -location {rv_plic_target.sv} -regexp {Bit length .* '1'} \
+ -comment "i + 1 is assumed as constant and guarded by SRCW"
+waive -rules INTEGER -location {rv_plic_target.sv} -regexp {'i' of type int used as} \
+ -comment "int i is static and only assigned to irq_id_next when it hits condition"
+
+waive -rules TWOS_COMP -location {rv_plic_target.sv} -regexp {Explicit two's complement with terms} \
+ -comment "This is permissible in this context"
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic.sv
new file mode 100644
index 0000000..d8c00a1
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic.sv
@@ -0,0 +1,449 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Controller compliant INTC
+//
+// Current version doesn't support MSI interrupt but it is easy to add
+// the feature. Create one external register and connect qe signal to the
+// gateway module (as edge-triggered)
+//
+// Consider to set MAX_PRIO as small number as possible. It is main factor
+// of area increase if edge-triggered counter isn't implemented.
+//
+// Verilog parameter
+// MAX_PRIO: Maximum value of interrupt priority
+
+module rv_plic import rv_plic_reg_pkg::*; #(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+ // OpenTitan IP standardizes on level triggered interrupts,
+ // hence LevelEdgeTrig is set to all-zeroes by default.
+ // Note that in case of edge-triggered interrupts, CDC handling is not
+ // fully implemented yet (this would require instantiating pulse syncs
+ // and routing the source clocks / resets to the PLIC).
+ parameter logic [NumSrc-1:0] LevelEdgeTrig = '0, // 0: level, 1: edge
+ // derived parameter
+ localparam int SRCW = $clog2(NumSrc)
+) (
+ input clk_i,
+ input rst_ni,
+
+ // Bus Interface (device)
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Interrupt Sources
+ input [NumSrc-1:0] intr_src_i,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // Interrupt notification to targets
+ output [NumTarget-1:0] irq_o,
+ output [SRCW-1:0] irq_id_o [NumTarget],
+
+ output logic [NumTarget-1:0] msip_o
+);
+
+ rv_plic_reg2hw_t reg2hw;
+ rv_plic_hw2reg_t hw2reg;
+
+ localparam int MAX_PRIO = 3;
+ localparam int PRIOW = $clog2(MAX_PRIO+1);
+
+ logic [NumSrc-1:0] ip;
+
+ logic [NumSrc-1:0] ie [NumTarget];
+
+ logic [NumTarget-1:0] claim_re; // Target read indicator
+ logic [SRCW-1:0] claim_id [NumTarget];
+ logic [NumSrc-1:0] claim; // Converted from claim_re/claim_id
+
+ logic [NumTarget-1:0] complete_we; // Target write indicator
+ logic [SRCW-1:0] complete_id [NumTarget];
+ logic [NumSrc-1:0] complete; // Converted from complete_re/complete_id
+
+ logic [SRCW-1:0] cc_id [NumTarget]; // Write ID
+
+ logic [NumSrc-1:0][PRIOW-1:0] prio;
+
+ logic [PRIOW-1:0] threshold [NumTarget];
+
+ // Glue logic between rv_plic_reg_top and others
+ assign cc_id = irq_id_o;
+
+ always_comb begin
+ claim = '0;
+ for (int i = 0 ; i < NumTarget ; i++) begin
+ if (claim_re[i]) claim[claim_id[i]] = 1'b1;
+ end
+ end
+ always_comb begin
+ complete = '0;
+ for (int i = 0 ; i < NumTarget ; i++) begin
+ if (complete_we[i]) complete[complete_id[i]] = 1'b1;
+ end
+ end
+
+ //`ASSERT_PULSE(claimPulse, claim_re[i])
+ //`ASSERT_PULSE(completePulse, complete_we[i])
+
+ `ASSERT(onehot0Claim, $onehot0(claim_re))
+
+ `ASSERT(onehot0Complete, $onehot0(complete_we))
+
+ //////////////
+ // Priority //
+ //////////////
+ assign prio[0] = reg2hw.prio0.q;
+ assign prio[1] = reg2hw.prio1.q;
+ assign prio[2] = reg2hw.prio2.q;
+ assign prio[3] = reg2hw.prio3.q;
+ assign prio[4] = reg2hw.prio4.q;
+ assign prio[5] = reg2hw.prio5.q;
+ assign prio[6] = reg2hw.prio6.q;
+ assign prio[7] = reg2hw.prio7.q;
+ assign prio[8] = reg2hw.prio8.q;
+ assign prio[9] = reg2hw.prio9.q;
+ assign prio[10] = reg2hw.prio10.q;
+ assign prio[11] = reg2hw.prio11.q;
+ assign prio[12] = reg2hw.prio12.q;
+ assign prio[13] = reg2hw.prio13.q;
+ assign prio[14] = reg2hw.prio14.q;
+ assign prio[15] = reg2hw.prio15.q;
+ assign prio[16] = reg2hw.prio16.q;
+ assign prio[17] = reg2hw.prio17.q;
+ assign prio[18] = reg2hw.prio18.q;
+ assign prio[19] = reg2hw.prio19.q;
+ assign prio[20] = reg2hw.prio20.q;
+ assign prio[21] = reg2hw.prio21.q;
+ assign prio[22] = reg2hw.prio22.q;
+ assign prio[23] = reg2hw.prio23.q;
+ assign prio[24] = reg2hw.prio24.q;
+ assign prio[25] = reg2hw.prio25.q;
+ assign prio[26] = reg2hw.prio26.q;
+ assign prio[27] = reg2hw.prio27.q;
+ assign prio[28] = reg2hw.prio28.q;
+ assign prio[29] = reg2hw.prio29.q;
+ assign prio[30] = reg2hw.prio30.q;
+ assign prio[31] = reg2hw.prio31.q;
+ assign prio[32] = reg2hw.prio32.q;
+ assign prio[33] = reg2hw.prio33.q;
+ assign prio[34] = reg2hw.prio34.q;
+ assign prio[35] = reg2hw.prio35.q;
+ assign prio[36] = reg2hw.prio36.q;
+ assign prio[37] = reg2hw.prio37.q;
+ assign prio[38] = reg2hw.prio38.q;
+ assign prio[39] = reg2hw.prio39.q;
+ assign prio[40] = reg2hw.prio40.q;
+ assign prio[41] = reg2hw.prio41.q;
+ assign prio[42] = reg2hw.prio42.q;
+ assign prio[43] = reg2hw.prio43.q;
+ assign prio[44] = reg2hw.prio44.q;
+ assign prio[45] = reg2hw.prio45.q;
+ assign prio[46] = reg2hw.prio46.q;
+ assign prio[47] = reg2hw.prio47.q;
+ assign prio[48] = reg2hw.prio48.q;
+ assign prio[49] = reg2hw.prio49.q;
+ assign prio[50] = reg2hw.prio50.q;
+ assign prio[51] = reg2hw.prio51.q;
+ assign prio[52] = reg2hw.prio52.q;
+ assign prio[53] = reg2hw.prio53.q;
+ assign prio[54] = reg2hw.prio54.q;
+ assign prio[55] = reg2hw.prio55.q;
+ assign prio[56] = reg2hw.prio56.q;
+ assign prio[57] = reg2hw.prio57.q;
+ assign prio[58] = reg2hw.prio58.q;
+ assign prio[59] = reg2hw.prio59.q;
+ assign prio[60] = reg2hw.prio60.q;
+ assign prio[61] = reg2hw.prio61.q;
+ assign prio[62] = reg2hw.prio62.q;
+ assign prio[63] = reg2hw.prio63.q;
+ assign prio[64] = reg2hw.prio64.q;
+ assign prio[65] = reg2hw.prio65.q;
+ assign prio[66] = reg2hw.prio66.q;
+ assign prio[67] = reg2hw.prio67.q;
+ assign prio[68] = reg2hw.prio68.q;
+ assign prio[69] = reg2hw.prio69.q;
+ assign prio[70] = reg2hw.prio70.q;
+ assign prio[71] = reg2hw.prio71.q;
+ assign prio[72] = reg2hw.prio72.q;
+ assign prio[73] = reg2hw.prio73.q;
+ assign prio[74] = reg2hw.prio74.q;
+ assign prio[75] = reg2hw.prio75.q;
+ assign prio[76] = reg2hw.prio76.q;
+ assign prio[77] = reg2hw.prio77.q;
+ assign prio[78] = reg2hw.prio78.q;
+ assign prio[79] = reg2hw.prio79.q;
+ assign prio[80] = reg2hw.prio80.q;
+ assign prio[81] = reg2hw.prio81.q;
+ assign prio[82] = reg2hw.prio82.q;
+ assign prio[83] = reg2hw.prio83.q;
+ assign prio[84] = reg2hw.prio84.q;
+ assign prio[85] = reg2hw.prio85.q;
+ assign prio[86] = reg2hw.prio86.q;
+ assign prio[87] = reg2hw.prio87.q;
+ assign prio[88] = reg2hw.prio88.q;
+ assign prio[89] = reg2hw.prio89.q;
+ assign prio[90] = reg2hw.prio90.q;
+ assign prio[91] = reg2hw.prio91.q;
+ assign prio[92] = reg2hw.prio92.q;
+ assign prio[93] = reg2hw.prio93.q;
+ assign prio[94] = reg2hw.prio94.q;
+ assign prio[95] = reg2hw.prio95.q;
+ assign prio[96] = reg2hw.prio96.q;
+ assign prio[97] = reg2hw.prio97.q;
+ assign prio[98] = reg2hw.prio98.q;
+ assign prio[99] = reg2hw.prio99.q;
+ assign prio[100] = reg2hw.prio100.q;
+ assign prio[101] = reg2hw.prio101.q;
+ assign prio[102] = reg2hw.prio102.q;
+ assign prio[103] = reg2hw.prio103.q;
+ assign prio[104] = reg2hw.prio104.q;
+ assign prio[105] = reg2hw.prio105.q;
+ assign prio[106] = reg2hw.prio106.q;
+ assign prio[107] = reg2hw.prio107.q;
+ assign prio[108] = reg2hw.prio108.q;
+ assign prio[109] = reg2hw.prio109.q;
+ assign prio[110] = reg2hw.prio110.q;
+ assign prio[111] = reg2hw.prio111.q;
+ assign prio[112] = reg2hw.prio112.q;
+ assign prio[113] = reg2hw.prio113.q;
+ assign prio[114] = reg2hw.prio114.q;
+ assign prio[115] = reg2hw.prio115.q;
+ assign prio[116] = reg2hw.prio116.q;
+ assign prio[117] = reg2hw.prio117.q;
+ assign prio[118] = reg2hw.prio118.q;
+ assign prio[119] = reg2hw.prio119.q;
+ assign prio[120] = reg2hw.prio120.q;
+ assign prio[121] = reg2hw.prio121.q;
+ assign prio[122] = reg2hw.prio122.q;
+ assign prio[123] = reg2hw.prio123.q;
+ assign prio[124] = reg2hw.prio124.q;
+ assign prio[125] = reg2hw.prio125.q;
+ assign prio[126] = reg2hw.prio126.q;
+ assign prio[127] = reg2hw.prio127.q;
+ assign prio[128] = reg2hw.prio128.q;
+ assign prio[129] = reg2hw.prio129.q;
+ assign prio[130] = reg2hw.prio130.q;
+ assign prio[131] = reg2hw.prio131.q;
+ assign prio[132] = reg2hw.prio132.q;
+ assign prio[133] = reg2hw.prio133.q;
+ assign prio[134] = reg2hw.prio134.q;
+ assign prio[135] = reg2hw.prio135.q;
+ assign prio[136] = reg2hw.prio136.q;
+ assign prio[137] = reg2hw.prio137.q;
+ assign prio[138] = reg2hw.prio138.q;
+ assign prio[139] = reg2hw.prio139.q;
+ assign prio[140] = reg2hw.prio140.q;
+ assign prio[141] = reg2hw.prio141.q;
+ assign prio[142] = reg2hw.prio142.q;
+ assign prio[143] = reg2hw.prio143.q;
+ assign prio[144] = reg2hw.prio144.q;
+ assign prio[145] = reg2hw.prio145.q;
+ assign prio[146] = reg2hw.prio146.q;
+ assign prio[147] = reg2hw.prio147.q;
+ assign prio[148] = reg2hw.prio148.q;
+ assign prio[149] = reg2hw.prio149.q;
+ assign prio[150] = reg2hw.prio150.q;
+ assign prio[151] = reg2hw.prio151.q;
+ assign prio[152] = reg2hw.prio152.q;
+ assign prio[153] = reg2hw.prio153.q;
+ assign prio[154] = reg2hw.prio154.q;
+ assign prio[155] = reg2hw.prio155.q;
+ assign prio[156] = reg2hw.prio156.q;
+ assign prio[157] = reg2hw.prio157.q;
+ assign prio[158] = reg2hw.prio158.q;
+ assign prio[159] = reg2hw.prio159.q;
+ assign prio[160] = reg2hw.prio160.q;
+ assign prio[161] = reg2hw.prio161.q;
+ assign prio[162] = reg2hw.prio162.q;
+ assign prio[163] = reg2hw.prio163.q;
+ assign prio[164] = reg2hw.prio164.q;
+ assign prio[165] = reg2hw.prio165.q;
+ assign prio[166] = reg2hw.prio166.q;
+ assign prio[167] = reg2hw.prio167.q;
+ assign prio[168] = reg2hw.prio168.q;
+ assign prio[169] = reg2hw.prio169.q;
+ assign prio[170] = reg2hw.prio170.q;
+ assign prio[171] = reg2hw.prio171.q;
+ assign prio[172] = reg2hw.prio172.q;
+ assign prio[173] = reg2hw.prio173.q;
+ assign prio[174] = reg2hw.prio174.q;
+ assign prio[175] = reg2hw.prio175.q;
+ assign prio[176] = reg2hw.prio176.q;
+ assign prio[177] = reg2hw.prio177.q;
+ assign prio[178] = reg2hw.prio178.q;
+ assign prio[179] = reg2hw.prio179.q;
+ assign prio[180] = reg2hw.prio180.q;
+ assign prio[181] = reg2hw.prio181.q;
+ assign prio[182] = reg2hw.prio182.q;
+ assign prio[183] = reg2hw.prio183.q;
+ assign prio[184] = reg2hw.prio184.q;
+ assign prio[185] = reg2hw.prio185.q;
+ assign prio[186] = reg2hw.prio186.q;
+ assign prio[187] = reg2hw.prio187.q;
+ assign prio[188] = reg2hw.prio188.q;
+ assign prio[189] = reg2hw.prio189.q;
+
+ //////////////////////
+ // Interrupt Enable //
+ //////////////////////
+ for (genvar s = 0; s < 190; s++) begin : gen_ie0
+ assign ie[0][s] = reg2hw.ie0[s].q;
+ end
+ for (genvar s = 0; s < 190; s++) begin : gen_ie1
+ assign ie[1][s] = reg2hw.ie1[s].q;
+ end
+
+ ////////////////////////
+ // THRESHOLD register //
+ ////////////////////////
+ assign threshold[0] = reg2hw.threshold0.q;
+ assign threshold[1] = reg2hw.threshold1.q;
+
+ /////////////////
+ // CC register //
+ /////////////////
+ assign claim_re[0] = reg2hw.cc0.re;
+ assign claim_id[0] = irq_id_o[0];
+ assign complete_we[0] = reg2hw.cc0.qe;
+ assign complete_id[0] = reg2hw.cc0.q;
+ assign hw2reg.cc0.d = cc_id[0];
+ assign claim_re[1] = reg2hw.cc1.re;
+ assign claim_id[1] = irq_id_o[1];
+ assign complete_we[1] = reg2hw.cc1.qe;
+ assign complete_id[1] = reg2hw.cc1.q;
+ assign hw2reg.cc1.d = cc_id[1];
+
+ ///////////////////
+ // MSIP register //
+ ///////////////////
+ assign msip_o[0] = reg2hw.msip0.q;
+ assign msip_o[1] = reg2hw.msip1.q;
+
+ ////////
+ // IP //
+ ////////
+ for (genvar s = 0; s < 190; s++) begin : gen_ip
+ assign hw2reg.ip[s].de = 1'b1; // Always write
+ assign hw2reg.ip[s].d = ip[s];
+ end
+
+ //////////////
+ // Gateways //
+ //////////////
+
+ // Synchronize all incoming interrupt requests.
+ logic [NumSrc-1:0] intr_src_synced;
+ prim_flop_2sync #(
+ .Width(NumSrc)
+ ) u_prim_flop_2sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(intr_src_i),
+ .q_o(intr_src_synced)
+ );
+
+ rv_plic_gateway #(
+ .N_SOURCE (NumSrc)
+ ) u_gateway (
+ .clk_i,
+ .rst_ni,
+
+ .src_i (intr_src_synced),
+ .le_i (LevelEdgeTrig),
+
+ .claim_i (claim),
+ .complete_i (complete),
+
+ .ip_o (ip)
+ );
+
+ ///////////////////////////////////
+ // Target interrupt notification //
+ ///////////////////////////////////
+ for (genvar i = 0 ; i < NumTarget ; i++) begin : gen_target
+ rv_plic_target #(
+ .N_SOURCE (NumSrc),
+ .MAX_PRIO (MAX_PRIO)
+ ) u_target (
+ .clk_i,
+ .rst_ni,
+
+ .ip_i (ip),
+ .ie_i (ie[i]),
+
+ .prio_i (prio),
+ .threshold_i (threshold[i]),
+
+ .irq_o (irq_o[i]),
+ .irq_id_o (irq_id_o[i])
+
+ );
+ end
+
+ ////////////
+ // Alerts //
+ ////////////
+
+ logic [NumAlerts-1:0] alert_test, alerts;
+
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ ////////////////////////
+ // Register interface //
+ ////////////////////////
+ // Limitation of register tool prevents the module from having flexibility to parameters
+ // So, signals are manually tied at the top.
+ rv_plic_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .reg2hw,
+ .hw2reg,
+
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o(alerts[0]),
+
+ .devmode_i (1'b1)
+ );
+
+ // Assertions
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(IrqKnownO_A, irq_o)
+ `ASSERT_KNOWN(MsipKnownO_A, msip_o)
+ for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known
+ `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
+ end
+
+ // Assume
+ `ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv
new file mode 100644
index 0000000..c81810b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Gateways module
+
+module rv_plic_gateway #(
+ parameter int N_SOURCE = 32
+) (
+ input clk_i,
+ input rst_ni,
+
+ input [N_SOURCE-1:0] src_i,
+ input [N_SOURCE-1:0] le_i, // Level0 Edge1
+
+ input [N_SOURCE-1:0] claim_i, // $onehot0(claim_i)
+ input [N_SOURCE-1:0] complete_i, // $onehot0(complete_i)
+
+ output logic [N_SOURCE-1:0] ip_o
+);
+
+ logic [N_SOURCE-1:0] ia; // Interrupt Active
+
+ logic [N_SOURCE-1:0] set; // Set: (le_i) ? src_i & ~src_q : src_i ;
+ logic [N_SOURCE-1:0] src_q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) src_q <= '0;
+ else src_q <= src_i;
+ end
+
+ always_comb begin
+ for (int i = 0 ; i < N_SOURCE; i++) begin
+ set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
+ end
+ end
+
+ // Interrupt pending is set by source (depends on le_i), cleared by claim_i.
+ // Until interrupt is claimed, set doesn't affect ip_o.
+ // RISC-V PLIC spec mentioned it can have counter for edge triggered
+ // But skipped the feature as counter consumes substantial logic size.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ip_o <= '0;
+ end else begin
+ ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
+ end
+ end
+
+ // Interrupt active is to control ip_o. If ip_o is set then until completed
+ // by target, ip_o shouldn't be set by source even claim_i can clear ip_o.
+ // ia can be cleared only when ia was set. If `set` and `complete_i` happen
+ // at the same time, always `set` wins.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ia <= '0;
+ end else begin
+ ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
+ end
+ end
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv
new file mode 100644
index 0000000..370e055
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv
@@ -0,0 +1,1706 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package rv_plic_reg_pkg;
+
+ // Param list
+ parameter int NumSrc = 190;
+ parameter int NumTarget = 2;
+ parameter int PrioWidth = 2;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 27;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio0_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio1_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio2_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio3_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio4_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio5_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio6_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio7_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio8_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio9_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio10_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio11_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio12_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio13_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio14_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio15_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio16_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio17_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio18_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio19_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio20_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio21_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio22_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio23_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio24_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio25_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio26_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio27_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio28_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio29_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio30_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio31_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio32_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio33_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio34_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio35_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio36_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio37_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio38_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio39_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio40_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio41_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio42_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio43_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio44_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio45_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio46_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio47_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio48_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio49_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio50_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio51_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio52_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio53_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio54_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio55_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio56_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio57_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio58_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio59_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio60_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio61_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio62_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio63_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio64_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio65_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio66_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio67_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio68_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio69_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio70_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio71_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio72_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio73_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio74_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio75_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio76_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio77_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio78_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio79_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio80_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio81_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio82_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio83_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio84_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio85_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio86_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio87_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio88_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio89_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio90_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio91_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio92_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio93_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio94_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio95_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio96_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio97_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio98_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio99_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio100_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio101_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio102_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio103_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio104_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio105_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio106_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio107_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio108_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio109_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio110_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio111_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio112_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio113_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio114_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio115_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio116_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio117_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio118_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio119_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio120_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio121_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio122_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio123_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio124_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio125_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio126_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio127_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio128_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio129_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio130_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio131_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio132_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio133_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio134_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio135_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio136_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio137_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio138_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio139_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio140_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio141_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio142_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio143_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio144_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio145_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio146_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio147_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio148_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio149_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio150_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio151_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio152_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio153_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio154_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio155_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio156_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio157_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio158_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio159_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio160_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio161_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio162_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio163_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio164_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio165_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio166_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio167_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio168_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio169_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio170_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio171_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio172_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio173_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio174_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio175_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio176_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio177_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio178_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio179_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio180_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio181_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio182_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio183_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio184_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio185_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio186_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio187_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio188_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio189_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_reg2hw_ie0_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_reg2hw_ie1_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_threshold0_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ logic qe;
+ logic re;
+ } rv_plic_reg2hw_cc0_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_threshold1_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ logic qe;
+ logic re;
+ } rv_plic_reg2hw_cc1_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_reg2hw_msip0_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_reg2hw_msip1_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } rv_plic_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } rv_plic_hw2reg_ip_mreg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ } rv_plic_hw2reg_cc0_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ } rv_plic_hw2reg_cc1_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ rv_plic_reg2hw_prio0_reg_t prio0; // [787:786]
+ rv_plic_reg2hw_prio1_reg_t prio1; // [785:784]
+ rv_plic_reg2hw_prio2_reg_t prio2; // [783:782]
+ rv_plic_reg2hw_prio3_reg_t prio3; // [781:780]
+ rv_plic_reg2hw_prio4_reg_t prio4; // [779:778]
+ rv_plic_reg2hw_prio5_reg_t prio5; // [777:776]
+ rv_plic_reg2hw_prio6_reg_t prio6; // [775:774]
+ rv_plic_reg2hw_prio7_reg_t prio7; // [773:772]
+ rv_plic_reg2hw_prio8_reg_t prio8; // [771:770]
+ rv_plic_reg2hw_prio9_reg_t prio9; // [769:768]
+ rv_plic_reg2hw_prio10_reg_t prio10; // [767:766]
+ rv_plic_reg2hw_prio11_reg_t prio11; // [765:764]
+ rv_plic_reg2hw_prio12_reg_t prio12; // [763:762]
+ rv_plic_reg2hw_prio13_reg_t prio13; // [761:760]
+ rv_plic_reg2hw_prio14_reg_t prio14; // [759:758]
+ rv_plic_reg2hw_prio15_reg_t prio15; // [757:756]
+ rv_plic_reg2hw_prio16_reg_t prio16; // [755:754]
+ rv_plic_reg2hw_prio17_reg_t prio17; // [753:752]
+ rv_plic_reg2hw_prio18_reg_t prio18; // [751:750]
+ rv_plic_reg2hw_prio19_reg_t prio19; // [749:748]
+ rv_plic_reg2hw_prio20_reg_t prio20; // [747:746]
+ rv_plic_reg2hw_prio21_reg_t prio21; // [745:744]
+ rv_plic_reg2hw_prio22_reg_t prio22; // [743:742]
+ rv_plic_reg2hw_prio23_reg_t prio23; // [741:740]
+ rv_plic_reg2hw_prio24_reg_t prio24; // [739:738]
+ rv_plic_reg2hw_prio25_reg_t prio25; // [737:736]
+ rv_plic_reg2hw_prio26_reg_t prio26; // [735:734]
+ rv_plic_reg2hw_prio27_reg_t prio27; // [733:732]
+ rv_plic_reg2hw_prio28_reg_t prio28; // [731:730]
+ rv_plic_reg2hw_prio29_reg_t prio29; // [729:728]
+ rv_plic_reg2hw_prio30_reg_t prio30; // [727:726]
+ rv_plic_reg2hw_prio31_reg_t prio31; // [725:724]
+ rv_plic_reg2hw_prio32_reg_t prio32; // [723:722]
+ rv_plic_reg2hw_prio33_reg_t prio33; // [721:720]
+ rv_plic_reg2hw_prio34_reg_t prio34; // [719:718]
+ rv_plic_reg2hw_prio35_reg_t prio35; // [717:716]
+ rv_plic_reg2hw_prio36_reg_t prio36; // [715:714]
+ rv_plic_reg2hw_prio37_reg_t prio37; // [713:712]
+ rv_plic_reg2hw_prio38_reg_t prio38; // [711:710]
+ rv_plic_reg2hw_prio39_reg_t prio39; // [709:708]
+ rv_plic_reg2hw_prio40_reg_t prio40; // [707:706]
+ rv_plic_reg2hw_prio41_reg_t prio41; // [705:704]
+ rv_plic_reg2hw_prio42_reg_t prio42; // [703:702]
+ rv_plic_reg2hw_prio43_reg_t prio43; // [701:700]
+ rv_plic_reg2hw_prio44_reg_t prio44; // [699:698]
+ rv_plic_reg2hw_prio45_reg_t prio45; // [697:696]
+ rv_plic_reg2hw_prio46_reg_t prio46; // [695:694]
+ rv_plic_reg2hw_prio47_reg_t prio47; // [693:692]
+ rv_plic_reg2hw_prio48_reg_t prio48; // [691:690]
+ rv_plic_reg2hw_prio49_reg_t prio49; // [689:688]
+ rv_plic_reg2hw_prio50_reg_t prio50; // [687:686]
+ rv_plic_reg2hw_prio51_reg_t prio51; // [685:684]
+ rv_plic_reg2hw_prio52_reg_t prio52; // [683:682]
+ rv_plic_reg2hw_prio53_reg_t prio53; // [681:680]
+ rv_plic_reg2hw_prio54_reg_t prio54; // [679:678]
+ rv_plic_reg2hw_prio55_reg_t prio55; // [677:676]
+ rv_plic_reg2hw_prio56_reg_t prio56; // [675:674]
+ rv_plic_reg2hw_prio57_reg_t prio57; // [673:672]
+ rv_plic_reg2hw_prio58_reg_t prio58; // [671:670]
+ rv_plic_reg2hw_prio59_reg_t prio59; // [669:668]
+ rv_plic_reg2hw_prio60_reg_t prio60; // [667:666]
+ rv_plic_reg2hw_prio61_reg_t prio61; // [665:664]
+ rv_plic_reg2hw_prio62_reg_t prio62; // [663:662]
+ rv_plic_reg2hw_prio63_reg_t prio63; // [661:660]
+ rv_plic_reg2hw_prio64_reg_t prio64; // [659:658]
+ rv_plic_reg2hw_prio65_reg_t prio65; // [657:656]
+ rv_plic_reg2hw_prio66_reg_t prio66; // [655:654]
+ rv_plic_reg2hw_prio67_reg_t prio67; // [653:652]
+ rv_plic_reg2hw_prio68_reg_t prio68; // [651:650]
+ rv_plic_reg2hw_prio69_reg_t prio69; // [649:648]
+ rv_plic_reg2hw_prio70_reg_t prio70; // [647:646]
+ rv_plic_reg2hw_prio71_reg_t prio71; // [645:644]
+ rv_plic_reg2hw_prio72_reg_t prio72; // [643:642]
+ rv_plic_reg2hw_prio73_reg_t prio73; // [641:640]
+ rv_plic_reg2hw_prio74_reg_t prio74; // [639:638]
+ rv_plic_reg2hw_prio75_reg_t prio75; // [637:636]
+ rv_plic_reg2hw_prio76_reg_t prio76; // [635:634]
+ rv_plic_reg2hw_prio77_reg_t prio77; // [633:632]
+ rv_plic_reg2hw_prio78_reg_t prio78; // [631:630]
+ rv_plic_reg2hw_prio79_reg_t prio79; // [629:628]
+ rv_plic_reg2hw_prio80_reg_t prio80; // [627:626]
+ rv_plic_reg2hw_prio81_reg_t prio81; // [625:624]
+ rv_plic_reg2hw_prio82_reg_t prio82; // [623:622]
+ rv_plic_reg2hw_prio83_reg_t prio83; // [621:620]
+ rv_plic_reg2hw_prio84_reg_t prio84; // [619:618]
+ rv_plic_reg2hw_prio85_reg_t prio85; // [617:616]
+ rv_plic_reg2hw_prio86_reg_t prio86; // [615:614]
+ rv_plic_reg2hw_prio87_reg_t prio87; // [613:612]
+ rv_plic_reg2hw_prio88_reg_t prio88; // [611:610]
+ rv_plic_reg2hw_prio89_reg_t prio89; // [609:608]
+ rv_plic_reg2hw_prio90_reg_t prio90; // [607:606]
+ rv_plic_reg2hw_prio91_reg_t prio91; // [605:604]
+ rv_plic_reg2hw_prio92_reg_t prio92; // [603:602]
+ rv_plic_reg2hw_prio93_reg_t prio93; // [601:600]
+ rv_plic_reg2hw_prio94_reg_t prio94; // [599:598]
+ rv_plic_reg2hw_prio95_reg_t prio95; // [597:596]
+ rv_plic_reg2hw_prio96_reg_t prio96; // [595:594]
+ rv_plic_reg2hw_prio97_reg_t prio97; // [593:592]
+ rv_plic_reg2hw_prio98_reg_t prio98; // [591:590]
+ rv_plic_reg2hw_prio99_reg_t prio99; // [589:588]
+ rv_plic_reg2hw_prio100_reg_t prio100; // [587:586]
+ rv_plic_reg2hw_prio101_reg_t prio101; // [585:584]
+ rv_plic_reg2hw_prio102_reg_t prio102; // [583:582]
+ rv_plic_reg2hw_prio103_reg_t prio103; // [581:580]
+ rv_plic_reg2hw_prio104_reg_t prio104; // [579:578]
+ rv_plic_reg2hw_prio105_reg_t prio105; // [577:576]
+ rv_plic_reg2hw_prio106_reg_t prio106; // [575:574]
+ rv_plic_reg2hw_prio107_reg_t prio107; // [573:572]
+ rv_plic_reg2hw_prio108_reg_t prio108; // [571:570]
+ rv_plic_reg2hw_prio109_reg_t prio109; // [569:568]
+ rv_plic_reg2hw_prio110_reg_t prio110; // [567:566]
+ rv_plic_reg2hw_prio111_reg_t prio111; // [565:564]
+ rv_plic_reg2hw_prio112_reg_t prio112; // [563:562]
+ rv_plic_reg2hw_prio113_reg_t prio113; // [561:560]
+ rv_plic_reg2hw_prio114_reg_t prio114; // [559:558]
+ rv_plic_reg2hw_prio115_reg_t prio115; // [557:556]
+ rv_plic_reg2hw_prio116_reg_t prio116; // [555:554]
+ rv_plic_reg2hw_prio117_reg_t prio117; // [553:552]
+ rv_plic_reg2hw_prio118_reg_t prio118; // [551:550]
+ rv_plic_reg2hw_prio119_reg_t prio119; // [549:548]
+ rv_plic_reg2hw_prio120_reg_t prio120; // [547:546]
+ rv_plic_reg2hw_prio121_reg_t prio121; // [545:544]
+ rv_plic_reg2hw_prio122_reg_t prio122; // [543:542]
+ rv_plic_reg2hw_prio123_reg_t prio123; // [541:540]
+ rv_plic_reg2hw_prio124_reg_t prio124; // [539:538]
+ rv_plic_reg2hw_prio125_reg_t prio125; // [537:536]
+ rv_plic_reg2hw_prio126_reg_t prio126; // [535:534]
+ rv_plic_reg2hw_prio127_reg_t prio127; // [533:532]
+ rv_plic_reg2hw_prio128_reg_t prio128; // [531:530]
+ rv_plic_reg2hw_prio129_reg_t prio129; // [529:528]
+ rv_plic_reg2hw_prio130_reg_t prio130; // [527:526]
+ rv_plic_reg2hw_prio131_reg_t prio131; // [525:524]
+ rv_plic_reg2hw_prio132_reg_t prio132; // [523:522]
+ rv_plic_reg2hw_prio133_reg_t prio133; // [521:520]
+ rv_plic_reg2hw_prio134_reg_t prio134; // [519:518]
+ rv_plic_reg2hw_prio135_reg_t prio135; // [517:516]
+ rv_plic_reg2hw_prio136_reg_t prio136; // [515:514]
+ rv_plic_reg2hw_prio137_reg_t prio137; // [513:512]
+ rv_plic_reg2hw_prio138_reg_t prio138; // [511:510]
+ rv_plic_reg2hw_prio139_reg_t prio139; // [509:508]
+ rv_plic_reg2hw_prio140_reg_t prio140; // [507:506]
+ rv_plic_reg2hw_prio141_reg_t prio141; // [505:504]
+ rv_plic_reg2hw_prio142_reg_t prio142; // [503:502]
+ rv_plic_reg2hw_prio143_reg_t prio143; // [501:500]
+ rv_plic_reg2hw_prio144_reg_t prio144; // [499:498]
+ rv_plic_reg2hw_prio145_reg_t prio145; // [497:496]
+ rv_plic_reg2hw_prio146_reg_t prio146; // [495:494]
+ rv_plic_reg2hw_prio147_reg_t prio147; // [493:492]
+ rv_plic_reg2hw_prio148_reg_t prio148; // [491:490]
+ rv_plic_reg2hw_prio149_reg_t prio149; // [489:488]
+ rv_plic_reg2hw_prio150_reg_t prio150; // [487:486]
+ rv_plic_reg2hw_prio151_reg_t prio151; // [485:484]
+ rv_plic_reg2hw_prio152_reg_t prio152; // [483:482]
+ rv_plic_reg2hw_prio153_reg_t prio153; // [481:480]
+ rv_plic_reg2hw_prio154_reg_t prio154; // [479:478]
+ rv_plic_reg2hw_prio155_reg_t prio155; // [477:476]
+ rv_plic_reg2hw_prio156_reg_t prio156; // [475:474]
+ rv_plic_reg2hw_prio157_reg_t prio157; // [473:472]
+ rv_plic_reg2hw_prio158_reg_t prio158; // [471:470]
+ rv_plic_reg2hw_prio159_reg_t prio159; // [469:468]
+ rv_plic_reg2hw_prio160_reg_t prio160; // [467:466]
+ rv_plic_reg2hw_prio161_reg_t prio161; // [465:464]
+ rv_plic_reg2hw_prio162_reg_t prio162; // [463:462]
+ rv_plic_reg2hw_prio163_reg_t prio163; // [461:460]
+ rv_plic_reg2hw_prio164_reg_t prio164; // [459:458]
+ rv_plic_reg2hw_prio165_reg_t prio165; // [457:456]
+ rv_plic_reg2hw_prio166_reg_t prio166; // [455:454]
+ rv_plic_reg2hw_prio167_reg_t prio167; // [453:452]
+ rv_plic_reg2hw_prio168_reg_t prio168; // [451:450]
+ rv_plic_reg2hw_prio169_reg_t prio169; // [449:448]
+ rv_plic_reg2hw_prio170_reg_t prio170; // [447:446]
+ rv_plic_reg2hw_prio171_reg_t prio171; // [445:444]
+ rv_plic_reg2hw_prio172_reg_t prio172; // [443:442]
+ rv_plic_reg2hw_prio173_reg_t prio173; // [441:440]
+ rv_plic_reg2hw_prio174_reg_t prio174; // [439:438]
+ rv_plic_reg2hw_prio175_reg_t prio175; // [437:436]
+ rv_plic_reg2hw_prio176_reg_t prio176; // [435:434]
+ rv_plic_reg2hw_prio177_reg_t prio177; // [433:432]
+ rv_plic_reg2hw_prio178_reg_t prio178; // [431:430]
+ rv_plic_reg2hw_prio179_reg_t prio179; // [429:428]
+ rv_plic_reg2hw_prio180_reg_t prio180; // [427:426]
+ rv_plic_reg2hw_prio181_reg_t prio181; // [425:424]
+ rv_plic_reg2hw_prio182_reg_t prio182; // [423:422]
+ rv_plic_reg2hw_prio183_reg_t prio183; // [421:420]
+ rv_plic_reg2hw_prio184_reg_t prio184; // [419:418]
+ rv_plic_reg2hw_prio185_reg_t prio185; // [417:416]
+ rv_plic_reg2hw_prio186_reg_t prio186; // [415:414]
+ rv_plic_reg2hw_prio187_reg_t prio187; // [413:412]
+ rv_plic_reg2hw_prio188_reg_t prio188; // [411:410]
+ rv_plic_reg2hw_prio189_reg_t prio189; // [409:408]
+ rv_plic_reg2hw_ie0_mreg_t [189:0] ie0; // [407:218]
+ rv_plic_reg2hw_ie1_mreg_t [189:0] ie1; // [217:28]
+ rv_plic_reg2hw_threshold0_reg_t threshold0; // [27:26]
+ rv_plic_reg2hw_cc0_reg_t cc0; // [25:16]
+ rv_plic_reg2hw_threshold1_reg_t threshold1; // [15:14]
+ rv_plic_reg2hw_cc1_reg_t cc1; // [13:4]
+ rv_plic_reg2hw_msip0_reg_t msip0; // [3:3]
+ rv_plic_reg2hw_msip1_reg_t msip1; // [2:2]
+ rv_plic_reg2hw_alert_test_reg_t alert_test; // [1:0]
+ } rv_plic_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ rv_plic_hw2reg_ip_mreg_t [189:0] ip; // [395:16]
+ rv_plic_hw2reg_cc0_reg_t cc0; // [15:8]
+ rv_plic_hw2reg_cc1_reg_t cc1; // [7:0]
+ } rv_plic_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO0_OFFSET = 27'h 0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO1_OFFSET = 27'h 4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO2_OFFSET = 27'h 8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO3_OFFSET = 27'h c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO4_OFFSET = 27'h 10;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO5_OFFSET = 27'h 14;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO6_OFFSET = 27'h 18;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO7_OFFSET = 27'h 1c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO8_OFFSET = 27'h 20;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO9_OFFSET = 27'h 24;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO10_OFFSET = 27'h 28;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO11_OFFSET = 27'h 2c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO12_OFFSET = 27'h 30;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO13_OFFSET = 27'h 34;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO14_OFFSET = 27'h 38;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO15_OFFSET = 27'h 3c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO16_OFFSET = 27'h 40;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO17_OFFSET = 27'h 44;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO18_OFFSET = 27'h 48;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO19_OFFSET = 27'h 4c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO20_OFFSET = 27'h 50;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO21_OFFSET = 27'h 54;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO22_OFFSET = 27'h 58;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO23_OFFSET = 27'h 5c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO24_OFFSET = 27'h 60;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO25_OFFSET = 27'h 64;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO26_OFFSET = 27'h 68;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO27_OFFSET = 27'h 6c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO28_OFFSET = 27'h 70;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO29_OFFSET = 27'h 74;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO30_OFFSET = 27'h 78;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO31_OFFSET = 27'h 7c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO32_OFFSET = 27'h 80;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO33_OFFSET = 27'h 84;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO34_OFFSET = 27'h 88;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO35_OFFSET = 27'h 8c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO36_OFFSET = 27'h 90;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO37_OFFSET = 27'h 94;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO38_OFFSET = 27'h 98;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO39_OFFSET = 27'h 9c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO40_OFFSET = 27'h a0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO41_OFFSET = 27'h a4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO42_OFFSET = 27'h a8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO43_OFFSET = 27'h ac;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO44_OFFSET = 27'h b0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO45_OFFSET = 27'h b4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO46_OFFSET = 27'h b8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO47_OFFSET = 27'h bc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO48_OFFSET = 27'h c0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO49_OFFSET = 27'h c4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO50_OFFSET = 27'h c8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO51_OFFSET = 27'h cc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO52_OFFSET = 27'h d0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO53_OFFSET = 27'h d4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO54_OFFSET = 27'h d8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO55_OFFSET = 27'h dc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO56_OFFSET = 27'h e0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO57_OFFSET = 27'h e4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO58_OFFSET = 27'h e8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO59_OFFSET = 27'h ec;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO60_OFFSET = 27'h f0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO61_OFFSET = 27'h f4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO62_OFFSET = 27'h f8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO63_OFFSET = 27'h fc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO64_OFFSET = 27'h 100;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO65_OFFSET = 27'h 104;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO66_OFFSET = 27'h 108;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO67_OFFSET = 27'h 10c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO68_OFFSET = 27'h 110;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO69_OFFSET = 27'h 114;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO70_OFFSET = 27'h 118;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO71_OFFSET = 27'h 11c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO72_OFFSET = 27'h 120;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO73_OFFSET = 27'h 124;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO74_OFFSET = 27'h 128;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO75_OFFSET = 27'h 12c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO76_OFFSET = 27'h 130;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO77_OFFSET = 27'h 134;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO78_OFFSET = 27'h 138;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO79_OFFSET = 27'h 13c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO80_OFFSET = 27'h 140;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO81_OFFSET = 27'h 144;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO82_OFFSET = 27'h 148;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO83_OFFSET = 27'h 14c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO84_OFFSET = 27'h 150;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO85_OFFSET = 27'h 154;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO86_OFFSET = 27'h 158;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO87_OFFSET = 27'h 15c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO88_OFFSET = 27'h 160;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO89_OFFSET = 27'h 164;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO90_OFFSET = 27'h 168;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO91_OFFSET = 27'h 16c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO92_OFFSET = 27'h 170;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO93_OFFSET = 27'h 174;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO94_OFFSET = 27'h 178;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO95_OFFSET = 27'h 17c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO96_OFFSET = 27'h 180;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO97_OFFSET = 27'h 184;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO98_OFFSET = 27'h 188;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO99_OFFSET = 27'h 18c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO100_OFFSET = 27'h 190;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO101_OFFSET = 27'h 194;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO102_OFFSET = 27'h 198;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO103_OFFSET = 27'h 19c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO104_OFFSET = 27'h 1a0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO105_OFFSET = 27'h 1a4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO106_OFFSET = 27'h 1a8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO107_OFFSET = 27'h 1ac;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO108_OFFSET = 27'h 1b0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO109_OFFSET = 27'h 1b4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO110_OFFSET = 27'h 1b8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO111_OFFSET = 27'h 1bc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO112_OFFSET = 27'h 1c0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO113_OFFSET = 27'h 1c4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO114_OFFSET = 27'h 1c8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO115_OFFSET = 27'h 1cc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO116_OFFSET = 27'h 1d0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO117_OFFSET = 27'h 1d4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO118_OFFSET = 27'h 1d8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO119_OFFSET = 27'h 1dc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO120_OFFSET = 27'h 1e0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO121_OFFSET = 27'h 1e4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO122_OFFSET = 27'h 1e8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO123_OFFSET = 27'h 1ec;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO124_OFFSET = 27'h 1f0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO125_OFFSET = 27'h 1f4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO126_OFFSET = 27'h 1f8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO127_OFFSET = 27'h 1fc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO128_OFFSET = 27'h 200;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO129_OFFSET = 27'h 204;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO130_OFFSET = 27'h 208;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO131_OFFSET = 27'h 20c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO132_OFFSET = 27'h 210;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO133_OFFSET = 27'h 214;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO134_OFFSET = 27'h 218;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO135_OFFSET = 27'h 21c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO136_OFFSET = 27'h 220;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO137_OFFSET = 27'h 224;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO138_OFFSET = 27'h 228;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO139_OFFSET = 27'h 22c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO140_OFFSET = 27'h 230;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO141_OFFSET = 27'h 234;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO142_OFFSET = 27'h 238;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO143_OFFSET = 27'h 23c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO144_OFFSET = 27'h 240;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO145_OFFSET = 27'h 244;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO146_OFFSET = 27'h 248;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO147_OFFSET = 27'h 24c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO148_OFFSET = 27'h 250;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO149_OFFSET = 27'h 254;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO150_OFFSET = 27'h 258;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO151_OFFSET = 27'h 25c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO152_OFFSET = 27'h 260;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO153_OFFSET = 27'h 264;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO154_OFFSET = 27'h 268;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO155_OFFSET = 27'h 26c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO156_OFFSET = 27'h 270;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO157_OFFSET = 27'h 274;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO158_OFFSET = 27'h 278;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO159_OFFSET = 27'h 27c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO160_OFFSET = 27'h 280;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO161_OFFSET = 27'h 284;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO162_OFFSET = 27'h 288;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO163_OFFSET = 27'h 28c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO164_OFFSET = 27'h 290;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO165_OFFSET = 27'h 294;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO166_OFFSET = 27'h 298;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO167_OFFSET = 27'h 29c;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO168_OFFSET = 27'h 2a0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO169_OFFSET = 27'h 2a4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO170_OFFSET = 27'h 2a8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO171_OFFSET = 27'h 2ac;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO172_OFFSET = 27'h 2b0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO173_OFFSET = 27'h 2b4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO174_OFFSET = 27'h 2b8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO175_OFFSET = 27'h 2bc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO176_OFFSET = 27'h 2c0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO177_OFFSET = 27'h 2c4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO178_OFFSET = 27'h 2c8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO179_OFFSET = 27'h 2cc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO180_OFFSET = 27'h 2d0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO181_OFFSET = 27'h 2d4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO182_OFFSET = 27'h 2d8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO183_OFFSET = 27'h 2dc;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO184_OFFSET = 27'h 2e0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO185_OFFSET = 27'h 2e4;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO186_OFFSET = 27'h 2e8;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO187_OFFSET = 27'h 2ec;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO188_OFFSET = 27'h 2f0;
+ parameter logic [BlockAw-1:0] RV_PLIC_PRIO189_OFFSET = 27'h 2f4;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_3_OFFSET = 27'h 100c;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_4_OFFSET = 27'h 1010;
+ parameter logic [BlockAw-1:0] RV_PLIC_IP_5_OFFSET = 27'h 1014;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 27'h 2000;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 27'h 2004;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 27'h 2008;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 27'h 200c;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_4_OFFSET = 27'h 2010;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE0_5_OFFSET = 27'h 2014;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_0_OFFSET = 27'h 2100;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_1_OFFSET = 27'h 2104;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_2_OFFSET = 27'h 2108;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_3_OFFSET = 27'h 210c;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_4_OFFSET = 27'h 2110;
+ parameter logic [BlockAw-1:0] RV_PLIC_IE1_5_OFFSET = 27'h 2114;
+ parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 27'h 200000;
+ parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 27'h 200004;
+ parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD1_OFFSET = 27'h 201000;
+ parameter logic [BlockAw-1:0] RV_PLIC_CC1_OFFSET = 27'h 201004;
+ parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 27'h 4000000;
+ parameter logic [BlockAw-1:0] RV_PLIC_MSIP1_OFFSET = 27'h 4000004;
+ parameter logic [BlockAw-1:0] RV_PLIC_ALERT_TEST_OFFSET = 27'h 4004000;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [7:0] RV_PLIC_CC0_RESVAL = 8'h 0;
+ parameter logic [7:0] RV_PLIC_CC1_RESVAL = 8'h 0;
+ parameter logic [0:0] RV_PLIC_ALERT_TEST_RESVAL = 1'h 0;
+
+ // Register index
+ typedef enum int {
+ RV_PLIC_PRIO0,
+ RV_PLIC_PRIO1,
+ RV_PLIC_PRIO2,
+ RV_PLIC_PRIO3,
+ RV_PLIC_PRIO4,
+ RV_PLIC_PRIO5,
+ RV_PLIC_PRIO6,
+ RV_PLIC_PRIO7,
+ RV_PLIC_PRIO8,
+ RV_PLIC_PRIO9,
+ RV_PLIC_PRIO10,
+ RV_PLIC_PRIO11,
+ RV_PLIC_PRIO12,
+ RV_PLIC_PRIO13,
+ RV_PLIC_PRIO14,
+ RV_PLIC_PRIO15,
+ RV_PLIC_PRIO16,
+ RV_PLIC_PRIO17,
+ RV_PLIC_PRIO18,
+ RV_PLIC_PRIO19,
+ RV_PLIC_PRIO20,
+ RV_PLIC_PRIO21,
+ RV_PLIC_PRIO22,
+ RV_PLIC_PRIO23,
+ RV_PLIC_PRIO24,
+ RV_PLIC_PRIO25,
+ RV_PLIC_PRIO26,
+ RV_PLIC_PRIO27,
+ RV_PLIC_PRIO28,
+ RV_PLIC_PRIO29,
+ RV_PLIC_PRIO30,
+ RV_PLIC_PRIO31,
+ RV_PLIC_PRIO32,
+ RV_PLIC_PRIO33,
+ RV_PLIC_PRIO34,
+ RV_PLIC_PRIO35,
+ RV_PLIC_PRIO36,
+ RV_PLIC_PRIO37,
+ RV_PLIC_PRIO38,
+ RV_PLIC_PRIO39,
+ RV_PLIC_PRIO40,
+ RV_PLIC_PRIO41,
+ RV_PLIC_PRIO42,
+ RV_PLIC_PRIO43,
+ RV_PLIC_PRIO44,
+ RV_PLIC_PRIO45,
+ RV_PLIC_PRIO46,
+ RV_PLIC_PRIO47,
+ RV_PLIC_PRIO48,
+ RV_PLIC_PRIO49,
+ RV_PLIC_PRIO50,
+ RV_PLIC_PRIO51,
+ RV_PLIC_PRIO52,
+ RV_PLIC_PRIO53,
+ RV_PLIC_PRIO54,
+ RV_PLIC_PRIO55,
+ RV_PLIC_PRIO56,
+ RV_PLIC_PRIO57,
+ RV_PLIC_PRIO58,
+ RV_PLIC_PRIO59,
+ RV_PLIC_PRIO60,
+ RV_PLIC_PRIO61,
+ RV_PLIC_PRIO62,
+ RV_PLIC_PRIO63,
+ RV_PLIC_PRIO64,
+ RV_PLIC_PRIO65,
+ RV_PLIC_PRIO66,
+ RV_PLIC_PRIO67,
+ RV_PLIC_PRIO68,
+ RV_PLIC_PRIO69,
+ RV_PLIC_PRIO70,
+ RV_PLIC_PRIO71,
+ RV_PLIC_PRIO72,
+ RV_PLIC_PRIO73,
+ RV_PLIC_PRIO74,
+ RV_PLIC_PRIO75,
+ RV_PLIC_PRIO76,
+ RV_PLIC_PRIO77,
+ RV_PLIC_PRIO78,
+ RV_PLIC_PRIO79,
+ RV_PLIC_PRIO80,
+ RV_PLIC_PRIO81,
+ RV_PLIC_PRIO82,
+ RV_PLIC_PRIO83,
+ RV_PLIC_PRIO84,
+ RV_PLIC_PRIO85,
+ RV_PLIC_PRIO86,
+ RV_PLIC_PRIO87,
+ RV_PLIC_PRIO88,
+ RV_PLIC_PRIO89,
+ RV_PLIC_PRIO90,
+ RV_PLIC_PRIO91,
+ RV_PLIC_PRIO92,
+ RV_PLIC_PRIO93,
+ RV_PLIC_PRIO94,
+ RV_PLIC_PRIO95,
+ RV_PLIC_PRIO96,
+ RV_PLIC_PRIO97,
+ RV_PLIC_PRIO98,
+ RV_PLIC_PRIO99,
+ RV_PLIC_PRIO100,
+ RV_PLIC_PRIO101,
+ RV_PLIC_PRIO102,
+ RV_PLIC_PRIO103,
+ RV_PLIC_PRIO104,
+ RV_PLIC_PRIO105,
+ RV_PLIC_PRIO106,
+ RV_PLIC_PRIO107,
+ RV_PLIC_PRIO108,
+ RV_PLIC_PRIO109,
+ RV_PLIC_PRIO110,
+ RV_PLIC_PRIO111,
+ RV_PLIC_PRIO112,
+ RV_PLIC_PRIO113,
+ RV_PLIC_PRIO114,
+ RV_PLIC_PRIO115,
+ RV_PLIC_PRIO116,
+ RV_PLIC_PRIO117,
+ RV_PLIC_PRIO118,
+ RV_PLIC_PRIO119,
+ RV_PLIC_PRIO120,
+ RV_PLIC_PRIO121,
+ RV_PLIC_PRIO122,
+ RV_PLIC_PRIO123,
+ RV_PLIC_PRIO124,
+ RV_PLIC_PRIO125,
+ RV_PLIC_PRIO126,
+ RV_PLIC_PRIO127,
+ RV_PLIC_PRIO128,
+ RV_PLIC_PRIO129,
+ RV_PLIC_PRIO130,
+ RV_PLIC_PRIO131,
+ RV_PLIC_PRIO132,
+ RV_PLIC_PRIO133,
+ RV_PLIC_PRIO134,
+ RV_PLIC_PRIO135,
+ RV_PLIC_PRIO136,
+ RV_PLIC_PRIO137,
+ RV_PLIC_PRIO138,
+ RV_PLIC_PRIO139,
+ RV_PLIC_PRIO140,
+ RV_PLIC_PRIO141,
+ RV_PLIC_PRIO142,
+ RV_PLIC_PRIO143,
+ RV_PLIC_PRIO144,
+ RV_PLIC_PRIO145,
+ RV_PLIC_PRIO146,
+ RV_PLIC_PRIO147,
+ RV_PLIC_PRIO148,
+ RV_PLIC_PRIO149,
+ RV_PLIC_PRIO150,
+ RV_PLIC_PRIO151,
+ RV_PLIC_PRIO152,
+ RV_PLIC_PRIO153,
+ RV_PLIC_PRIO154,
+ RV_PLIC_PRIO155,
+ RV_PLIC_PRIO156,
+ RV_PLIC_PRIO157,
+ RV_PLIC_PRIO158,
+ RV_PLIC_PRIO159,
+ RV_PLIC_PRIO160,
+ RV_PLIC_PRIO161,
+ RV_PLIC_PRIO162,
+ RV_PLIC_PRIO163,
+ RV_PLIC_PRIO164,
+ RV_PLIC_PRIO165,
+ RV_PLIC_PRIO166,
+ RV_PLIC_PRIO167,
+ RV_PLIC_PRIO168,
+ RV_PLIC_PRIO169,
+ RV_PLIC_PRIO170,
+ RV_PLIC_PRIO171,
+ RV_PLIC_PRIO172,
+ RV_PLIC_PRIO173,
+ RV_PLIC_PRIO174,
+ RV_PLIC_PRIO175,
+ RV_PLIC_PRIO176,
+ RV_PLIC_PRIO177,
+ RV_PLIC_PRIO178,
+ RV_PLIC_PRIO179,
+ RV_PLIC_PRIO180,
+ RV_PLIC_PRIO181,
+ RV_PLIC_PRIO182,
+ RV_PLIC_PRIO183,
+ RV_PLIC_PRIO184,
+ RV_PLIC_PRIO185,
+ RV_PLIC_PRIO186,
+ RV_PLIC_PRIO187,
+ RV_PLIC_PRIO188,
+ RV_PLIC_PRIO189,
+ RV_PLIC_IP_0,
+ RV_PLIC_IP_1,
+ RV_PLIC_IP_2,
+ RV_PLIC_IP_3,
+ RV_PLIC_IP_4,
+ RV_PLIC_IP_5,
+ RV_PLIC_IE0_0,
+ RV_PLIC_IE0_1,
+ RV_PLIC_IE0_2,
+ RV_PLIC_IE0_3,
+ RV_PLIC_IE0_4,
+ RV_PLIC_IE0_5,
+ RV_PLIC_IE1_0,
+ RV_PLIC_IE1_1,
+ RV_PLIC_IE1_2,
+ RV_PLIC_IE1_3,
+ RV_PLIC_IE1_4,
+ RV_PLIC_IE1_5,
+ RV_PLIC_THRESHOLD0,
+ RV_PLIC_CC0,
+ RV_PLIC_THRESHOLD1,
+ RV_PLIC_CC1,
+ RV_PLIC_MSIP0,
+ RV_PLIC_MSIP1,
+ RV_PLIC_ALERT_TEST
+ } rv_plic_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] RV_PLIC_PERMIT [215] = '{
+ 4'b 0001, // index[ 0] RV_PLIC_PRIO0
+ 4'b 0001, // index[ 1] RV_PLIC_PRIO1
+ 4'b 0001, // index[ 2] RV_PLIC_PRIO2
+ 4'b 0001, // index[ 3] RV_PLIC_PRIO3
+ 4'b 0001, // index[ 4] RV_PLIC_PRIO4
+ 4'b 0001, // index[ 5] RV_PLIC_PRIO5
+ 4'b 0001, // index[ 6] RV_PLIC_PRIO6
+ 4'b 0001, // index[ 7] RV_PLIC_PRIO7
+ 4'b 0001, // index[ 8] RV_PLIC_PRIO8
+ 4'b 0001, // index[ 9] RV_PLIC_PRIO9
+ 4'b 0001, // index[ 10] RV_PLIC_PRIO10
+ 4'b 0001, // index[ 11] RV_PLIC_PRIO11
+ 4'b 0001, // index[ 12] RV_PLIC_PRIO12
+ 4'b 0001, // index[ 13] RV_PLIC_PRIO13
+ 4'b 0001, // index[ 14] RV_PLIC_PRIO14
+ 4'b 0001, // index[ 15] RV_PLIC_PRIO15
+ 4'b 0001, // index[ 16] RV_PLIC_PRIO16
+ 4'b 0001, // index[ 17] RV_PLIC_PRIO17
+ 4'b 0001, // index[ 18] RV_PLIC_PRIO18
+ 4'b 0001, // index[ 19] RV_PLIC_PRIO19
+ 4'b 0001, // index[ 20] RV_PLIC_PRIO20
+ 4'b 0001, // index[ 21] RV_PLIC_PRIO21
+ 4'b 0001, // index[ 22] RV_PLIC_PRIO22
+ 4'b 0001, // index[ 23] RV_PLIC_PRIO23
+ 4'b 0001, // index[ 24] RV_PLIC_PRIO24
+ 4'b 0001, // index[ 25] RV_PLIC_PRIO25
+ 4'b 0001, // index[ 26] RV_PLIC_PRIO26
+ 4'b 0001, // index[ 27] RV_PLIC_PRIO27
+ 4'b 0001, // index[ 28] RV_PLIC_PRIO28
+ 4'b 0001, // index[ 29] RV_PLIC_PRIO29
+ 4'b 0001, // index[ 30] RV_PLIC_PRIO30
+ 4'b 0001, // index[ 31] RV_PLIC_PRIO31
+ 4'b 0001, // index[ 32] RV_PLIC_PRIO32
+ 4'b 0001, // index[ 33] RV_PLIC_PRIO33
+ 4'b 0001, // index[ 34] RV_PLIC_PRIO34
+ 4'b 0001, // index[ 35] RV_PLIC_PRIO35
+ 4'b 0001, // index[ 36] RV_PLIC_PRIO36
+ 4'b 0001, // index[ 37] RV_PLIC_PRIO37
+ 4'b 0001, // index[ 38] RV_PLIC_PRIO38
+ 4'b 0001, // index[ 39] RV_PLIC_PRIO39
+ 4'b 0001, // index[ 40] RV_PLIC_PRIO40
+ 4'b 0001, // index[ 41] RV_PLIC_PRIO41
+ 4'b 0001, // index[ 42] RV_PLIC_PRIO42
+ 4'b 0001, // index[ 43] RV_PLIC_PRIO43
+ 4'b 0001, // index[ 44] RV_PLIC_PRIO44
+ 4'b 0001, // index[ 45] RV_PLIC_PRIO45
+ 4'b 0001, // index[ 46] RV_PLIC_PRIO46
+ 4'b 0001, // index[ 47] RV_PLIC_PRIO47
+ 4'b 0001, // index[ 48] RV_PLIC_PRIO48
+ 4'b 0001, // index[ 49] RV_PLIC_PRIO49
+ 4'b 0001, // index[ 50] RV_PLIC_PRIO50
+ 4'b 0001, // index[ 51] RV_PLIC_PRIO51
+ 4'b 0001, // index[ 52] RV_PLIC_PRIO52
+ 4'b 0001, // index[ 53] RV_PLIC_PRIO53
+ 4'b 0001, // index[ 54] RV_PLIC_PRIO54
+ 4'b 0001, // index[ 55] RV_PLIC_PRIO55
+ 4'b 0001, // index[ 56] RV_PLIC_PRIO56
+ 4'b 0001, // index[ 57] RV_PLIC_PRIO57
+ 4'b 0001, // index[ 58] RV_PLIC_PRIO58
+ 4'b 0001, // index[ 59] RV_PLIC_PRIO59
+ 4'b 0001, // index[ 60] RV_PLIC_PRIO60
+ 4'b 0001, // index[ 61] RV_PLIC_PRIO61
+ 4'b 0001, // index[ 62] RV_PLIC_PRIO62
+ 4'b 0001, // index[ 63] RV_PLIC_PRIO63
+ 4'b 0001, // index[ 64] RV_PLIC_PRIO64
+ 4'b 0001, // index[ 65] RV_PLIC_PRIO65
+ 4'b 0001, // index[ 66] RV_PLIC_PRIO66
+ 4'b 0001, // index[ 67] RV_PLIC_PRIO67
+ 4'b 0001, // index[ 68] RV_PLIC_PRIO68
+ 4'b 0001, // index[ 69] RV_PLIC_PRIO69
+ 4'b 0001, // index[ 70] RV_PLIC_PRIO70
+ 4'b 0001, // index[ 71] RV_PLIC_PRIO71
+ 4'b 0001, // index[ 72] RV_PLIC_PRIO72
+ 4'b 0001, // index[ 73] RV_PLIC_PRIO73
+ 4'b 0001, // index[ 74] RV_PLIC_PRIO74
+ 4'b 0001, // index[ 75] RV_PLIC_PRIO75
+ 4'b 0001, // index[ 76] RV_PLIC_PRIO76
+ 4'b 0001, // index[ 77] RV_PLIC_PRIO77
+ 4'b 0001, // index[ 78] RV_PLIC_PRIO78
+ 4'b 0001, // index[ 79] RV_PLIC_PRIO79
+ 4'b 0001, // index[ 80] RV_PLIC_PRIO80
+ 4'b 0001, // index[ 81] RV_PLIC_PRIO81
+ 4'b 0001, // index[ 82] RV_PLIC_PRIO82
+ 4'b 0001, // index[ 83] RV_PLIC_PRIO83
+ 4'b 0001, // index[ 84] RV_PLIC_PRIO84
+ 4'b 0001, // index[ 85] RV_PLIC_PRIO85
+ 4'b 0001, // index[ 86] RV_PLIC_PRIO86
+ 4'b 0001, // index[ 87] RV_PLIC_PRIO87
+ 4'b 0001, // index[ 88] RV_PLIC_PRIO88
+ 4'b 0001, // index[ 89] RV_PLIC_PRIO89
+ 4'b 0001, // index[ 90] RV_PLIC_PRIO90
+ 4'b 0001, // index[ 91] RV_PLIC_PRIO91
+ 4'b 0001, // index[ 92] RV_PLIC_PRIO92
+ 4'b 0001, // index[ 93] RV_PLIC_PRIO93
+ 4'b 0001, // index[ 94] RV_PLIC_PRIO94
+ 4'b 0001, // index[ 95] RV_PLIC_PRIO95
+ 4'b 0001, // index[ 96] RV_PLIC_PRIO96
+ 4'b 0001, // index[ 97] RV_PLIC_PRIO97
+ 4'b 0001, // index[ 98] RV_PLIC_PRIO98
+ 4'b 0001, // index[ 99] RV_PLIC_PRIO99
+ 4'b 0001, // index[100] RV_PLIC_PRIO100
+ 4'b 0001, // index[101] RV_PLIC_PRIO101
+ 4'b 0001, // index[102] RV_PLIC_PRIO102
+ 4'b 0001, // index[103] RV_PLIC_PRIO103
+ 4'b 0001, // index[104] RV_PLIC_PRIO104
+ 4'b 0001, // index[105] RV_PLIC_PRIO105
+ 4'b 0001, // index[106] RV_PLIC_PRIO106
+ 4'b 0001, // index[107] RV_PLIC_PRIO107
+ 4'b 0001, // index[108] RV_PLIC_PRIO108
+ 4'b 0001, // index[109] RV_PLIC_PRIO109
+ 4'b 0001, // index[110] RV_PLIC_PRIO110
+ 4'b 0001, // index[111] RV_PLIC_PRIO111
+ 4'b 0001, // index[112] RV_PLIC_PRIO112
+ 4'b 0001, // index[113] RV_PLIC_PRIO113
+ 4'b 0001, // index[114] RV_PLIC_PRIO114
+ 4'b 0001, // index[115] RV_PLIC_PRIO115
+ 4'b 0001, // index[116] RV_PLIC_PRIO116
+ 4'b 0001, // index[117] RV_PLIC_PRIO117
+ 4'b 0001, // index[118] RV_PLIC_PRIO118
+ 4'b 0001, // index[119] RV_PLIC_PRIO119
+ 4'b 0001, // index[120] RV_PLIC_PRIO120
+ 4'b 0001, // index[121] RV_PLIC_PRIO121
+ 4'b 0001, // index[122] RV_PLIC_PRIO122
+ 4'b 0001, // index[123] RV_PLIC_PRIO123
+ 4'b 0001, // index[124] RV_PLIC_PRIO124
+ 4'b 0001, // index[125] RV_PLIC_PRIO125
+ 4'b 0001, // index[126] RV_PLIC_PRIO126
+ 4'b 0001, // index[127] RV_PLIC_PRIO127
+ 4'b 0001, // index[128] RV_PLIC_PRIO128
+ 4'b 0001, // index[129] RV_PLIC_PRIO129
+ 4'b 0001, // index[130] RV_PLIC_PRIO130
+ 4'b 0001, // index[131] RV_PLIC_PRIO131
+ 4'b 0001, // index[132] RV_PLIC_PRIO132
+ 4'b 0001, // index[133] RV_PLIC_PRIO133
+ 4'b 0001, // index[134] RV_PLIC_PRIO134
+ 4'b 0001, // index[135] RV_PLIC_PRIO135
+ 4'b 0001, // index[136] RV_PLIC_PRIO136
+ 4'b 0001, // index[137] RV_PLIC_PRIO137
+ 4'b 0001, // index[138] RV_PLIC_PRIO138
+ 4'b 0001, // index[139] RV_PLIC_PRIO139
+ 4'b 0001, // index[140] RV_PLIC_PRIO140
+ 4'b 0001, // index[141] RV_PLIC_PRIO141
+ 4'b 0001, // index[142] RV_PLIC_PRIO142
+ 4'b 0001, // index[143] RV_PLIC_PRIO143
+ 4'b 0001, // index[144] RV_PLIC_PRIO144
+ 4'b 0001, // index[145] RV_PLIC_PRIO145
+ 4'b 0001, // index[146] RV_PLIC_PRIO146
+ 4'b 0001, // index[147] RV_PLIC_PRIO147
+ 4'b 0001, // index[148] RV_PLIC_PRIO148
+ 4'b 0001, // index[149] RV_PLIC_PRIO149
+ 4'b 0001, // index[150] RV_PLIC_PRIO150
+ 4'b 0001, // index[151] RV_PLIC_PRIO151
+ 4'b 0001, // index[152] RV_PLIC_PRIO152
+ 4'b 0001, // index[153] RV_PLIC_PRIO153
+ 4'b 0001, // index[154] RV_PLIC_PRIO154
+ 4'b 0001, // index[155] RV_PLIC_PRIO155
+ 4'b 0001, // index[156] RV_PLIC_PRIO156
+ 4'b 0001, // index[157] RV_PLIC_PRIO157
+ 4'b 0001, // index[158] RV_PLIC_PRIO158
+ 4'b 0001, // index[159] RV_PLIC_PRIO159
+ 4'b 0001, // index[160] RV_PLIC_PRIO160
+ 4'b 0001, // index[161] RV_PLIC_PRIO161
+ 4'b 0001, // index[162] RV_PLIC_PRIO162
+ 4'b 0001, // index[163] RV_PLIC_PRIO163
+ 4'b 0001, // index[164] RV_PLIC_PRIO164
+ 4'b 0001, // index[165] RV_PLIC_PRIO165
+ 4'b 0001, // index[166] RV_PLIC_PRIO166
+ 4'b 0001, // index[167] RV_PLIC_PRIO167
+ 4'b 0001, // index[168] RV_PLIC_PRIO168
+ 4'b 0001, // index[169] RV_PLIC_PRIO169
+ 4'b 0001, // index[170] RV_PLIC_PRIO170
+ 4'b 0001, // index[171] RV_PLIC_PRIO171
+ 4'b 0001, // index[172] RV_PLIC_PRIO172
+ 4'b 0001, // index[173] RV_PLIC_PRIO173
+ 4'b 0001, // index[174] RV_PLIC_PRIO174
+ 4'b 0001, // index[175] RV_PLIC_PRIO175
+ 4'b 0001, // index[176] RV_PLIC_PRIO176
+ 4'b 0001, // index[177] RV_PLIC_PRIO177
+ 4'b 0001, // index[178] RV_PLIC_PRIO178
+ 4'b 0001, // index[179] RV_PLIC_PRIO179
+ 4'b 0001, // index[180] RV_PLIC_PRIO180
+ 4'b 0001, // index[181] RV_PLIC_PRIO181
+ 4'b 0001, // index[182] RV_PLIC_PRIO182
+ 4'b 0001, // index[183] RV_PLIC_PRIO183
+ 4'b 0001, // index[184] RV_PLIC_PRIO184
+ 4'b 0001, // index[185] RV_PLIC_PRIO185
+ 4'b 0001, // index[186] RV_PLIC_PRIO186
+ 4'b 0001, // index[187] RV_PLIC_PRIO187
+ 4'b 0001, // index[188] RV_PLIC_PRIO188
+ 4'b 0001, // index[189] RV_PLIC_PRIO189
+ 4'b 1111, // index[190] RV_PLIC_IP_0
+ 4'b 1111, // index[191] RV_PLIC_IP_1
+ 4'b 1111, // index[192] RV_PLIC_IP_2
+ 4'b 1111, // index[193] RV_PLIC_IP_3
+ 4'b 1111, // index[194] RV_PLIC_IP_4
+ 4'b 1111, // index[195] RV_PLIC_IP_5
+ 4'b 1111, // index[196] RV_PLIC_IE0_0
+ 4'b 1111, // index[197] RV_PLIC_IE0_1
+ 4'b 1111, // index[198] RV_PLIC_IE0_2
+ 4'b 1111, // index[199] RV_PLIC_IE0_3
+ 4'b 1111, // index[200] RV_PLIC_IE0_4
+ 4'b 1111, // index[201] RV_PLIC_IE0_5
+ 4'b 1111, // index[202] RV_PLIC_IE1_0
+ 4'b 1111, // index[203] RV_PLIC_IE1_1
+ 4'b 1111, // index[204] RV_PLIC_IE1_2
+ 4'b 1111, // index[205] RV_PLIC_IE1_3
+ 4'b 1111, // index[206] RV_PLIC_IE1_4
+ 4'b 1111, // index[207] RV_PLIC_IE1_5
+ 4'b 0001, // index[208] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[209] RV_PLIC_CC0
+ 4'b 0001, // index[210] RV_PLIC_THRESHOLD1
+ 4'b 0001, // index[211] RV_PLIC_CC1
+ 4'b 0001, // index[212] RV_PLIC_MSIP0
+ 4'b 0001, // index[213] RV_PLIC_MSIP1
+ 4'b 0001 // index[214] RV_PLIC_ALERT_TEST
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv
new file mode 100644
index 0000000..cf901ae
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv
@@ -0,0 +1,25335 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module rv_plic_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
+ input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import rv_plic_reg_pkg::* ;
+
+ localparam int AW = 27;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [214:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(215)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic prio0_we;
+ logic [1:0] prio0_qs;
+ logic [1:0] prio0_wd;
+ logic prio1_we;
+ logic [1:0] prio1_qs;
+ logic [1:0] prio1_wd;
+ logic prio2_we;
+ logic [1:0] prio2_qs;
+ logic [1:0] prio2_wd;
+ logic prio3_we;
+ logic [1:0] prio3_qs;
+ logic [1:0] prio3_wd;
+ logic prio4_we;
+ logic [1:0] prio4_qs;
+ logic [1:0] prio4_wd;
+ logic prio5_we;
+ logic [1:0] prio5_qs;
+ logic [1:0] prio5_wd;
+ logic prio6_we;
+ logic [1:0] prio6_qs;
+ logic [1:0] prio6_wd;
+ logic prio7_we;
+ logic [1:0] prio7_qs;
+ logic [1:0] prio7_wd;
+ logic prio8_we;
+ logic [1:0] prio8_qs;
+ logic [1:0] prio8_wd;
+ logic prio9_we;
+ logic [1:0] prio9_qs;
+ logic [1:0] prio9_wd;
+ logic prio10_we;
+ logic [1:0] prio10_qs;
+ logic [1:0] prio10_wd;
+ logic prio11_we;
+ logic [1:0] prio11_qs;
+ logic [1:0] prio11_wd;
+ logic prio12_we;
+ logic [1:0] prio12_qs;
+ logic [1:0] prio12_wd;
+ logic prio13_we;
+ logic [1:0] prio13_qs;
+ logic [1:0] prio13_wd;
+ logic prio14_we;
+ logic [1:0] prio14_qs;
+ logic [1:0] prio14_wd;
+ logic prio15_we;
+ logic [1:0] prio15_qs;
+ logic [1:0] prio15_wd;
+ logic prio16_we;
+ logic [1:0] prio16_qs;
+ logic [1:0] prio16_wd;
+ logic prio17_we;
+ logic [1:0] prio17_qs;
+ logic [1:0] prio17_wd;
+ logic prio18_we;
+ logic [1:0] prio18_qs;
+ logic [1:0] prio18_wd;
+ logic prio19_we;
+ logic [1:0] prio19_qs;
+ logic [1:0] prio19_wd;
+ logic prio20_we;
+ logic [1:0] prio20_qs;
+ logic [1:0] prio20_wd;
+ logic prio21_we;
+ logic [1:0] prio21_qs;
+ logic [1:0] prio21_wd;
+ logic prio22_we;
+ logic [1:0] prio22_qs;
+ logic [1:0] prio22_wd;
+ logic prio23_we;
+ logic [1:0] prio23_qs;
+ logic [1:0] prio23_wd;
+ logic prio24_we;
+ logic [1:0] prio24_qs;
+ logic [1:0] prio24_wd;
+ logic prio25_we;
+ logic [1:0] prio25_qs;
+ logic [1:0] prio25_wd;
+ logic prio26_we;
+ logic [1:0] prio26_qs;
+ logic [1:0] prio26_wd;
+ logic prio27_we;
+ logic [1:0] prio27_qs;
+ logic [1:0] prio27_wd;
+ logic prio28_we;
+ logic [1:0] prio28_qs;
+ logic [1:0] prio28_wd;
+ logic prio29_we;
+ logic [1:0] prio29_qs;
+ logic [1:0] prio29_wd;
+ logic prio30_we;
+ logic [1:0] prio30_qs;
+ logic [1:0] prio30_wd;
+ logic prio31_we;
+ logic [1:0] prio31_qs;
+ logic [1:0] prio31_wd;
+ logic prio32_we;
+ logic [1:0] prio32_qs;
+ logic [1:0] prio32_wd;
+ logic prio33_we;
+ logic [1:0] prio33_qs;
+ logic [1:0] prio33_wd;
+ logic prio34_we;
+ logic [1:0] prio34_qs;
+ logic [1:0] prio34_wd;
+ logic prio35_we;
+ logic [1:0] prio35_qs;
+ logic [1:0] prio35_wd;
+ logic prio36_we;
+ logic [1:0] prio36_qs;
+ logic [1:0] prio36_wd;
+ logic prio37_we;
+ logic [1:0] prio37_qs;
+ logic [1:0] prio37_wd;
+ logic prio38_we;
+ logic [1:0] prio38_qs;
+ logic [1:0] prio38_wd;
+ logic prio39_we;
+ logic [1:0] prio39_qs;
+ logic [1:0] prio39_wd;
+ logic prio40_we;
+ logic [1:0] prio40_qs;
+ logic [1:0] prio40_wd;
+ logic prio41_we;
+ logic [1:0] prio41_qs;
+ logic [1:0] prio41_wd;
+ logic prio42_we;
+ logic [1:0] prio42_qs;
+ logic [1:0] prio42_wd;
+ logic prio43_we;
+ logic [1:0] prio43_qs;
+ logic [1:0] prio43_wd;
+ logic prio44_we;
+ logic [1:0] prio44_qs;
+ logic [1:0] prio44_wd;
+ logic prio45_we;
+ logic [1:0] prio45_qs;
+ logic [1:0] prio45_wd;
+ logic prio46_we;
+ logic [1:0] prio46_qs;
+ logic [1:0] prio46_wd;
+ logic prio47_we;
+ logic [1:0] prio47_qs;
+ logic [1:0] prio47_wd;
+ logic prio48_we;
+ logic [1:0] prio48_qs;
+ logic [1:0] prio48_wd;
+ logic prio49_we;
+ logic [1:0] prio49_qs;
+ logic [1:0] prio49_wd;
+ logic prio50_we;
+ logic [1:0] prio50_qs;
+ logic [1:0] prio50_wd;
+ logic prio51_we;
+ logic [1:0] prio51_qs;
+ logic [1:0] prio51_wd;
+ logic prio52_we;
+ logic [1:0] prio52_qs;
+ logic [1:0] prio52_wd;
+ logic prio53_we;
+ logic [1:0] prio53_qs;
+ logic [1:0] prio53_wd;
+ logic prio54_we;
+ logic [1:0] prio54_qs;
+ logic [1:0] prio54_wd;
+ logic prio55_we;
+ logic [1:0] prio55_qs;
+ logic [1:0] prio55_wd;
+ logic prio56_we;
+ logic [1:0] prio56_qs;
+ logic [1:0] prio56_wd;
+ logic prio57_we;
+ logic [1:0] prio57_qs;
+ logic [1:0] prio57_wd;
+ logic prio58_we;
+ logic [1:0] prio58_qs;
+ logic [1:0] prio58_wd;
+ logic prio59_we;
+ logic [1:0] prio59_qs;
+ logic [1:0] prio59_wd;
+ logic prio60_we;
+ logic [1:0] prio60_qs;
+ logic [1:0] prio60_wd;
+ logic prio61_we;
+ logic [1:0] prio61_qs;
+ logic [1:0] prio61_wd;
+ logic prio62_we;
+ logic [1:0] prio62_qs;
+ logic [1:0] prio62_wd;
+ logic prio63_we;
+ logic [1:0] prio63_qs;
+ logic [1:0] prio63_wd;
+ logic prio64_we;
+ logic [1:0] prio64_qs;
+ logic [1:0] prio64_wd;
+ logic prio65_we;
+ logic [1:0] prio65_qs;
+ logic [1:0] prio65_wd;
+ logic prio66_we;
+ logic [1:0] prio66_qs;
+ logic [1:0] prio66_wd;
+ logic prio67_we;
+ logic [1:0] prio67_qs;
+ logic [1:0] prio67_wd;
+ logic prio68_we;
+ logic [1:0] prio68_qs;
+ logic [1:0] prio68_wd;
+ logic prio69_we;
+ logic [1:0] prio69_qs;
+ logic [1:0] prio69_wd;
+ logic prio70_we;
+ logic [1:0] prio70_qs;
+ logic [1:0] prio70_wd;
+ logic prio71_we;
+ logic [1:0] prio71_qs;
+ logic [1:0] prio71_wd;
+ logic prio72_we;
+ logic [1:0] prio72_qs;
+ logic [1:0] prio72_wd;
+ logic prio73_we;
+ logic [1:0] prio73_qs;
+ logic [1:0] prio73_wd;
+ logic prio74_we;
+ logic [1:0] prio74_qs;
+ logic [1:0] prio74_wd;
+ logic prio75_we;
+ logic [1:0] prio75_qs;
+ logic [1:0] prio75_wd;
+ logic prio76_we;
+ logic [1:0] prio76_qs;
+ logic [1:0] prio76_wd;
+ logic prio77_we;
+ logic [1:0] prio77_qs;
+ logic [1:0] prio77_wd;
+ logic prio78_we;
+ logic [1:0] prio78_qs;
+ logic [1:0] prio78_wd;
+ logic prio79_we;
+ logic [1:0] prio79_qs;
+ logic [1:0] prio79_wd;
+ logic prio80_we;
+ logic [1:0] prio80_qs;
+ logic [1:0] prio80_wd;
+ logic prio81_we;
+ logic [1:0] prio81_qs;
+ logic [1:0] prio81_wd;
+ logic prio82_we;
+ logic [1:0] prio82_qs;
+ logic [1:0] prio82_wd;
+ logic prio83_we;
+ logic [1:0] prio83_qs;
+ logic [1:0] prio83_wd;
+ logic prio84_we;
+ logic [1:0] prio84_qs;
+ logic [1:0] prio84_wd;
+ logic prio85_we;
+ logic [1:0] prio85_qs;
+ logic [1:0] prio85_wd;
+ logic prio86_we;
+ logic [1:0] prio86_qs;
+ logic [1:0] prio86_wd;
+ logic prio87_we;
+ logic [1:0] prio87_qs;
+ logic [1:0] prio87_wd;
+ logic prio88_we;
+ logic [1:0] prio88_qs;
+ logic [1:0] prio88_wd;
+ logic prio89_we;
+ logic [1:0] prio89_qs;
+ logic [1:0] prio89_wd;
+ logic prio90_we;
+ logic [1:0] prio90_qs;
+ logic [1:0] prio90_wd;
+ logic prio91_we;
+ logic [1:0] prio91_qs;
+ logic [1:0] prio91_wd;
+ logic prio92_we;
+ logic [1:0] prio92_qs;
+ logic [1:0] prio92_wd;
+ logic prio93_we;
+ logic [1:0] prio93_qs;
+ logic [1:0] prio93_wd;
+ logic prio94_we;
+ logic [1:0] prio94_qs;
+ logic [1:0] prio94_wd;
+ logic prio95_we;
+ logic [1:0] prio95_qs;
+ logic [1:0] prio95_wd;
+ logic prio96_we;
+ logic [1:0] prio96_qs;
+ logic [1:0] prio96_wd;
+ logic prio97_we;
+ logic [1:0] prio97_qs;
+ logic [1:0] prio97_wd;
+ logic prio98_we;
+ logic [1:0] prio98_qs;
+ logic [1:0] prio98_wd;
+ logic prio99_we;
+ logic [1:0] prio99_qs;
+ logic [1:0] prio99_wd;
+ logic prio100_we;
+ logic [1:0] prio100_qs;
+ logic [1:0] prio100_wd;
+ logic prio101_we;
+ logic [1:0] prio101_qs;
+ logic [1:0] prio101_wd;
+ logic prio102_we;
+ logic [1:0] prio102_qs;
+ logic [1:0] prio102_wd;
+ logic prio103_we;
+ logic [1:0] prio103_qs;
+ logic [1:0] prio103_wd;
+ logic prio104_we;
+ logic [1:0] prio104_qs;
+ logic [1:0] prio104_wd;
+ logic prio105_we;
+ logic [1:0] prio105_qs;
+ logic [1:0] prio105_wd;
+ logic prio106_we;
+ logic [1:0] prio106_qs;
+ logic [1:0] prio106_wd;
+ logic prio107_we;
+ logic [1:0] prio107_qs;
+ logic [1:0] prio107_wd;
+ logic prio108_we;
+ logic [1:0] prio108_qs;
+ logic [1:0] prio108_wd;
+ logic prio109_we;
+ logic [1:0] prio109_qs;
+ logic [1:0] prio109_wd;
+ logic prio110_we;
+ logic [1:0] prio110_qs;
+ logic [1:0] prio110_wd;
+ logic prio111_we;
+ logic [1:0] prio111_qs;
+ logic [1:0] prio111_wd;
+ logic prio112_we;
+ logic [1:0] prio112_qs;
+ logic [1:0] prio112_wd;
+ logic prio113_we;
+ logic [1:0] prio113_qs;
+ logic [1:0] prio113_wd;
+ logic prio114_we;
+ logic [1:0] prio114_qs;
+ logic [1:0] prio114_wd;
+ logic prio115_we;
+ logic [1:0] prio115_qs;
+ logic [1:0] prio115_wd;
+ logic prio116_we;
+ logic [1:0] prio116_qs;
+ logic [1:0] prio116_wd;
+ logic prio117_we;
+ logic [1:0] prio117_qs;
+ logic [1:0] prio117_wd;
+ logic prio118_we;
+ logic [1:0] prio118_qs;
+ logic [1:0] prio118_wd;
+ logic prio119_we;
+ logic [1:0] prio119_qs;
+ logic [1:0] prio119_wd;
+ logic prio120_we;
+ logic [1:0] prio120_qs;
+ logic [1:0] prio120_wd;
+ logic prio121_we;
+ logic [1:0] prio121_qs;
+ logic [1:0] prio121_wd;
+ logic prio122_we;
+ logic [1:0] prio122_qs;
+ logic [1:0] prio122_wd;
+ logic prio123_we;
+ logic [1:0] prio123_qs;
+ logic [1:0] prio123_wd;
+ logic prio124_we;
+ logic [1:0] prio124_qs;
+ logic [1:0] prio124_wd;
+ logic prio125_we;
+ logic [1:0] prio125_qs;
+ logic [1:0] prio125_wd;
+ logic prio126_we;
+ logic [1:0] prio126_qs;
+ logic [1:0] prio126_wd;
+ logic prio127_we;
+ logic [1:0] prio127_qs;
+ logic [1:0] prio127_wd;
+ logic prio128_we;
+ logic [1:0] prio128_qs;
+ logic [1:0] prio128_wd;
+ logic prio129_we;
+ logic [1:0] prio129_qs;
+ logic [1:0] prio129_wd;
+ logic prio130_we;
+ logic [1:0] prio130_qs;
+ logic [1:0] prio130_wd;
+ logic prio131_we;
+ logic [1:0] prio131_qs;
+ logic [1:0] prio131_wd;
+ logic prio132_we;
+ logic [1:0] prio132_qs;
+ logic [1:0] prio132_wd;
+ logic prio133_we;
+ logic [1:0] prio133_qs;
+ logic [1:0] prio133_wd;
+ logic prio134_we;
+ logic [1:0] prio134_qs;
+ logic [1:0] prio134_wd;
+ logic prio135_we;
+ logic [1:0] prio135_qs;
+ logic [1:0] prio135_wd;
+ logic prio136_we;
+ logic [1:0] prio136_qs;
+ logic [1:0] prio136_wd;
+ logic prio137_we;
+ logic [1:0] prio137_qs;
+ logic [1:0] prio137_wd;
+ logic prio138_we;
+ logic [1:0] prio138_qs;
+ logic [1:0] prio138_wd;
+ logic prio139_we;
+ logic [1:0] prio139_qs;
+ logic [1:0] prio139_wd;
+ logic prio140_we;
+ logic [1:0] prio140_qs;
+ logic [1:0] prio140_wd;
+ logic prio141_we;
+ logic [1:0] prio141_qs;
+ logic [1:0] prio141_wd;
+ logic prio142_we;
+ logic [1:0] prio142_qs;
+ logic [1:0] prio142_wd;
+ logic prio143_we;
+ logic [1:0] prio143_qs;
+ logic [1:0] prio143_wd;
+ logic prio144_we;
+ logic [1:0] prio144_qs;
+ logic [1:0] prio144_wd;
+ logic prio145_we;
+ logic [1:0] prio145_qs;
+ logic [1:0] prio145_wd;
+ logic prio146_we;
+ logic [1:0] prio146_qs;
+ logic [1:0] prio146_wd;
+ logic prio147_we;
+ logic [1:0] prio147_qs;
+ logic [1:0] prio147_wd;
+ logic prio148_we;
+ logic [1:0] prio148_qs;
+ logic [1:0] prio148_wd;
+ logic prio149_we;
+ logic [1:0] prio149_qs;
+ logic [1:0] prio149_wd;
+ logic prio150_we;
+ logic [1:0] prio150_qs;
+ logic [1:0] prio150_wd;
+ logic prio151_we;
+ logic [1:0] prio151_qs;
+ logic [1:0] prio151_wd;
+ logic prio152_we;
+ logic [1:0] prio152_qs;
+ logic [1:0] prio152_wd;
+ logic prio153_we;
+ logic [1:0] prio153_qs;
+ logic [1:0] prio153_wd;
+ logic prio154_we;
+ logic [1:0] prio154_qs;
+ logic [1:0] prio154_wd;
+ logic prio155_we;
+ logic [1:0] prio155_qs;
+ logic [1:0] prio155_wd;
+ logic prio156_we;
+ logic [1:0] prio156_qs;
+ logic [1:0] prio156_wd;
+ logic prio157_we;
+ logic [1:0] prio157_qs;
+ logic [1:0] prio157_wd;
+ logic prio158_we;
+ logic [1:0] prio158_qs;
+ logic [1:0] prio158_wd;
+ logic prio159_we;
+ logic [1:0] prio159_qs;
+ logic [1:0] prio159_wd;
+ logic prio160_we;
+ logic [1:0] prio160_qs;
+ logic [1:0] prio160_wd;
+ logic prio161_we;
+ logic [1:0] prio161_qs;
+ logic [1:0] prio161_wd;
+ logic prio162_we;
+ logic [1:0] prio162_qs;
+ logic [1:0] prio162_wd;
+ logic prio163_we;
+ logic [1:0] prio163_qs;
+ logic [1:0] prio163_wd;
+ logic prio164_we;
+ logic [1:0] prio164_qs;
+ logic [1:0] prio164_wd;
+ logic prio165_we;
+ logic [1:0] prio165_qs;
+ logic [1:0] prio165_wd;
+ logic prio166_we;
+ logic [1:0] prio166_qs;
+ logic [1:0] prio166_wd;
+ logic prio167_we;
+ logic [1:0] prio167_qs;
+ logic [1:0] prio167_wd;
+ logic prio168_we;
+ logic [1:0] prio168_qs;
+ logic [1:0] prio168_wd;
+ logic prio169_we;
+ logic [1:0] prio169_qs;
+ logic [1:0] prio169_wd;
+ logic prio170_we;
+ logic [1:0] prio170_qs;
+ logic [1:0] prio170_wd;
+ logic prio171_we;
+ logic [1:0] prio171_qs;
+ logic [1:0] prio171_wd;
+ logic prio172_we;
+ logic [1:0] prio172_qs;
+ logic [1:0] prio172_wd;
+ logic prio173_we;
+ logic [1:0] prio173_qs;
+ logic [1:0] prio173_wd;
+ logic prio174_we;
+ logic [1:0] prio174_qs;
+ logic [1:0] prio174_wd;
+ logic prio175_we;
+ logic [1:0] prio175_qs;
+ logic [1:0] prio175_wd;
+ logic prio176_we;
+ logic [1:0] prio176_qs;
+ logic [1:0] prio176_wd;
+ logic prio177_we;
+ logic [1:0] prio177_qs;
+ logic [1:0] prio177_wd;
+ logic prio178_we;
+ logic [1:0] prio178_qs;
+ logic [1:0] prio178_wd;
+ logic prio179_we;
+ logic [1:0] prio179_qs;
+ logic [1:0] prio179_wd;
+ logic prio180_we;
+ logic [1:0] prio180_qs;
+ logic [1:0] prio180_wd;
+ logic prio181_we;
+ logic [1:0] prio181_qs;
+ logic [1:0] prio181_wd;
+ logic prio182_we;
+ logic [1:0] prio182_qs;
+ logic [1:0] prio182_wd;
+ logic prio183_we;
+ logic [1:0] prio183_qs;
+ logic [1:0] prio183_wd;
+ logic prio184_we;
+ logic [1:0] prio184_qs;
+ logic [1:0] prio184_wd;
+ logic prio185_we;
+ logic [1:0] prio185_qs;
+ logic [1:0] prio185_wd;
+ logic prio186_we;
+ logic [1:0] prio186_qs;
+ logic [1:0] prio186_wd;
+ logic prio187_we;
+ logic [1:0] prio187_qs;
+ logic [1:0] prio187_wd;
+ logic prio188_we;
+ logic [1:0] prio188_qs;
+ logic [1:0] prio188_wd;
+ logic prio189_we;
+ logic [1:0] prio189_qs;
+ logic [1:0] prio189_wd;
+ logic ip_0_p_0_qs;
+ logic ip_0_p_1_qs;
+ logic ip_0_p_2_qs;
+ logic ip_0_p_3_qs;
+ logic ip_0_p_4_qs;
+ logic ip_0_p_5_qs;
+ logic ip_0_p_6_qs;
+ logic ip_0_p_7_qs;
+ logic ip_0_p_8_qs;
+ logic ip_0_p_9_qs;
+ logic ip_0_p_10_qs;
+ logic ip_0_p_11_qs;
+ logic ip_0_p_12_qs;
+ logic ip_0_p_13_qs;
+ logic ip_0_p_14_qs;
+ logic ip_0_p_15_qs;
+ logic ip_0_p_16_qs;
+ logic ip_0_p_17_qs;
+ logic ip_0_p_18_qs;
+ logic ip_0_p_19_qs;
+ logic ip_0_p_20_qs;
+ logic ip_0_p_21_qs;
+ logic ip_0_p_22_qs;
+ logic ip_0_p_23_qs;
+ logic ip_0_p_24_qs;
+ logic ip_0_p_25_qs;
+ logic ip_0_p_26_qs;
+ logic ip_0_p_27_qs;
+ logic ip_0_p_28_qs;
+ logic ip_0_p_29_qs;
+ logic ip_0_p_30_qs;
+ logic ip_0_p_31_qs;
+ logic ip_1_p_32_qs;
+ logic ip_1_p_33_qs;
+ logic ip_1_p_34_qs;
+ logic ip_1_p_35_qs;
+ logic ip_1_p_36_qs;
+ logic ip_1_p_37_qs;
+ logic ip_1_p_38_qs;
+ logic ip_1_p_39_qs;
+ logic ip_1_p_40_qs;
+ logic ip_1_p_41_qs;
+ logic ip_1_p_42_qs;
+ logic ip_1_p_43_qs;
+ logic ip_1_p_44_qs;
+ logic ip_1_p_45_qs;
+ logic ip_1_p_46_qs;
+ logic ip_1_p_47_qs;
+ logic ip_1_p_48_qs;
+ logic ip_1_p_49_qs;
+ logic ip_1_p_50_qs;
+ logic ip_1_p_51_qs;
+ logic ip_1_p_52_qs;
+ logic ip_1_p_53_qs;
+ logic ip_1_p_54_qs;
+ logic ip_1_p_55_qs;
+ logic ip_1_p_56_qs;
+ logic ip_1_p_57_qs;
+ logic ip_1_p_58_qs;
+ logic ip_1_p_59_qs;
+ logic ip_1_p_60_qs;
+ logic ip_1_p_61_qs;
+ logic ip_1_p_62_qs;
+ logic ip_1_p_63_qs;
+ logic ip_2_p_64_qs;
+ logic ip_2_p_65_qs;
+ logic ip_2_p_66_qs;
+ logic ip_2_p_67_qs;
+ logic ip_2_p_68_qs;
+ logic ip_2_p_69_qs;
+ logic ip_2_p_70_qs;
+ logic ip_2_p_71_qs;
+ logic ip_2_p_72_qs;
+ logic ip_2_p_73_qs;
+ logic ip_2_p_74_qs;
+ logic ip_2_p_75_qs;
+ logic ip_2_p_76_qs;
+ logic ip_2_p_77_qs;
+ logic ip_2_p_78_qs;
+ logic ip_2_p_79_qs;
+ logic ip_2_p_80_qs;
+ logic ip_2_p_81_qs;
+ logic ip_2_p_82_qs;
+ logic ip_2_p_83_qs;
+ logic ip_2_p_84_qs;
+ logic ip_2_p_85_qs;
+ logic ip_2_p_86_qs;
+ logic ip_2_p_87_qs;
+ logic ip_2_p_88_qs;
+ logic ip_2_p_89_qs;
+ logic ip_2_p_90_qs;
+ logic ip_2_p_91_qs;
+ logic ip_2_p_92_qs;
+ logic ip_2_p_93_qs;
+ logic ip_2_p_94_qs;
+ logic ip_2_p_95_qs;
+ logic ip_3_p_96_qs;
+ logic ip_3_p_97_qs;
+ logic ip_3_p_98_qs;
+ logic ip_3_p_99_qs;
+ logic ip_3_p_100_qs;
+ logic ip_3_p_101_qs;
+ logic ip_3_p_102_qs;
+ logic ip_3_p_103_qs;
+ logic ip_3_p_104_qs;
+ logic ip_3_p_105_qs;
+ logic ip_3_p_106_qs;
+ logic ip_3_p_107_qs;
+ logic ip_3_p_108_qs;
+ logic ip_3_p_109_qs;
+ logic ip_3_p_110_qs;
+ logic ip_3_p_111_qs;
+ logic ip_3_p_112_qs;
+ logic ip_3_p_113_qs;
+ logic ip_3_p_114_qs;
+ logic ip_3_p_115_qs;
+ logic ip_3_p_116_qs;
+ logic ip_3_p_117_qs;
+ logic ip_3_p_118_qs;
+ logic ip_3_p_119_qs;
+ logic ip_3_p_120_qs;
+ logic ip_3_p_121_qs;
+ logic ip_3_p_122_qs;
+ logic ip_3_p_123_qs;
+ logic ip_3_p_124_qs;
+ logic ip_3_p_125_qs;
+ logic ip_3_p_126_qs;
+ logic ip_3_p_127_qs;
+ logic ip_4_p_128_qs;
+ logic ip_4_p_129_qs;
+ logic ip_4_p_130_qs;
+ logic ip_4_p_131_qs;
+ logic ip_4_p_132_qs;
+ logic ip_4_p_133_qs;
+ logic ip_4_p_134_qs;
+ logic ip_4_p_135_qs;
+ logic ip_4_p_136_qs;
+ logic ip_4_p_137_qs;
+ logic ip_4_p_138_qs;
+ logic ip_4_p_139_qs;
+ logic ip_4_p_140_qs;
+ logic ip_4_p_141_qs;
+ logic ip_4_p_142_qs;
+ logic ip_4_p_143_qs;
+ logic ip_4_p_144_qs;
+ logic ip_4_p_145_qs;
+ logic ip_4_p_146_qs;
+ logic ip_4_p_147_qs;
+ logic ip_4_p_148_qs;
+ logic ip_4_p_149_qs;
+ logic ip_4_p_150_qs;
+ logic ip_4_p_151_qs;
+ logic ip_4_p_152_qs;
+ logic ip_4_p_153_qs;
+ logic ip_4_p_154_qs;
+ logic ip_4_p_155_qs;
+ logic ip_4_p_156_qs;
+ logic ip_4_p_157_qs;
+ logic ip_4_p_158_qs;
+ logic ip_4_p_159_qs;
+ logic ip_5_p_160_qs;
+ logic ip_5_p_161_qs;
+ logic ip_5_p_162_qs;
+ logic ip_5_p_163_qs;
+ logic ip_5_p_164_qs;
+ logic ip_5_p_165_qs;
+ logic ip_5_p_166_qs;
+ logic ip_5_p_167_qs;
+ logic ip_5_p_168_qs;
+ logic ip_5_p_169_qs;
+ logic ip_5_p_170_qs;
+ logic ip_5_p_171_qs;
+ logic ip_5_p_172_qs;
+ logic ip_5_p_173_qs;
+ logic ip_5_p_174_qs;
+ logic ip_5_p_175_qs;
+ logic ip_5_p_176_qs;
+ logic ip_5_p_177_qs;
+ logic ip_5_p_178_qs;
+ logic ip_5_p_179_qs;
+ logic ip_5_p_180_qs;
+ logic ip_5_p_181_qs;
+ logic ip_5_p_182_qs;
+ logic ip_5_p_183_qs;
+ logic ip_5_p_184_qs;
+ logic ip_5_p_185_qs;
+ logic ip_5_p_186_qs;
+ logic ip_5_p_187_qs;
+ logic ip_5_p_188_qs;
+ logic ip_5_p_189_qs;
+ logic ie0_0_we;
+ logic ie0_0_e_0_qs;
+ logic ie0_0_e_0_wd;
+ logic ie0_0_e_1_qs;
+ logic ie0_0_e_1_wd;
+ logic ie0_0_e_2_qs;
+ logic ie0_0_e_2_wd;
+ logic ie0_0_e_3_qs;
+ logic ie0_0_e_3_wd;
+ logic ie0_0_e_4_qs;
+ logic ie0_0_e_4_wd;
+ logic ie0_0_e_5_qs;
+ logic ie0_0_e_5_wd;
+ logic ie0_0_e_6_qs;
+ logic ie0_0_e_6_wd;
+ logic ie0_0_e_7_qs;
+ logic ie0_0_e_7_wd;
+ logic ie0_0_e_8_qs;
+ logic ie0_0_e_8_wd;
+ logic ie0_0_e_9_qs;
+ logic ie0_0_e_9_wd;
+ logic ie0_0_e_10_qs;
+ logic ie0_0_e_10_wd;
+ logic ie0_0_e_11_qs;
+ logic ie0_0_e_11_wd;
+ logic ie0_0_e_12_qs;
+ logic ie0_0_e_12_wd;
+ logic ie0_0_e_13_qs;
+ logic ie0_0_e_13_wd;
+ logic ie0_0_e_14_qs;
+ logic ie0_0_e_14_wd;
+ logic ie0_0_e_15_qs;
+ logic ie0_0_e_15_wd;
+ logic ie0_0_e_16_qs;
+ logic ie0_0_e_16_wd;
+ logic ie0_0_e_17_qs;
+ logic ie0_0_e_17_wd;
+ logic ie0_0_e_18_qs;
+ logic ie0_0_e_18_wd;
+ logic ie0_0_e_19_qs;
+ logic ie0_0_e_19_wd;
+ logic ie0_0_e_20_qs;
+ logic ie0_0_e_20_wd;
+ logic ie0_0_e_21_qs;
+ logic ie0_0_e_21_wd;
+ logic ie0_0_e_22_qs;
+ logic ie0_0_e_22_wd;
+ logic ie0_0_e_23_qs;
+ logic ie0_0_e_23_wd;
+ logic ie0_0_e_24_qs;
+ logic ie0_0_e_24_wd;
+ logic ie0_0_e_25_qs;
+ logic ie0_0_e_25_wd;
+ logic ie0_0_e_26_qs;
+ logic ie0_0_e_26_wd;
+ logic ie0_0_e_27_qs;
+ logic ie0_0_e_27_wd;
+ logic ie0_0_e_28_qs;
+ logic ie0_0_e_28_wd;
+ logic ie0_0_e_29_qs;
+ logic ie0_0_e_29_wd;
+ logic ie0_0_e_30_qs;
+ logic ie0_0_e_30_wd;
+ logic ie0_0_e_31_qs;
+ logic ie0_0_e_31_wd;
+ logic ie0_1_we;
+ logic ie0_1_e_32_qs;
+ logic ie0_1_e_32_wd;
+ logic ie0_1_e_33_qs;
+ logic ie0_1_e_33_wd;
+ logic ie0_1_e_34_qs;
+ logic ie0_1_e_34_wd;
+ logic ie0_1_e_35_qs;
+ logic ie0_1_e_35_wd;
+ logic ie0_1_e_36_qs;
+ logic ie0_1_e_36_wd;
+ logic ie0_1_e_37_qs;
+ logic ie0_1_e_37_wd;
+ logic ie0_1_e_38_qs;
+ logic ie0_1_e_38_wd;
+ logic ie0_1_e_39_qs;
+ logic ie0_1_e_39_wd;
+ logic ie0_1_e_40_qs;
+ logic ie0_1_e_40_wd;
+ logic ie0_1_e_41_qs;
+ logic ie0_1_e_41_wd;
+ logic ie0_1_e_42_qs;
+ logic ie0_1_e_42_wd;
+ logic ie0_1_e_43_qs;
+ logic ie0_1_e_43_wd;
+ logic ie0_1_e_44_qs;
+ logic ie0_1_e_44_wd;
+ logic ie0_1_e_45_qs;
+ logic ie0_1_e_45_wd;
+ logic ie0_1_e_46_qs;
+ logic ie0_1_e_46_wd;
+ logic ie0_1_e_47_qs;
+ logic ie0_1_e_47_wd;
+ logic ie0_1_e_48_qs;
+ logic ie0_1_e_48_wd;
+ logic ie0_1_e_49_qs;
+ logic ie0_1_e_49_wd;
+ logic ie0_1_e_50_qs;
+ logic ie0_1_e_50_wd;
+ logic ie0_1_e_51_qs;
+ logic ie0_1_e_51_wd;
+ logic ie0_1_e_52_qs;
+ logic ie0_1_e_52_wd;
+ logic ie0_1_e_53_qs;
+ logic ie0_1_e_53_wd;
+ logic ie0_1_e_54_qs;
+ logic ie0_1_e_54_wd;
+ logic ie0_1_e_55_qs;
+ logic ie0_1_e_55_wd;
+ logic ie0_1_e_56_qs;
+ logic ie0_1_e_56_wd;
+ logic ie0_1_e_57_qs;
+ logic ie0_1_e_57_wd;
+ logic ie0_1_e_58_qs;
+ logic ie0_1_e_58_wd;
+ logic ie0_1_e_59_qs;
+ logic ie0_1_e_59_wd;
+ logic ie0_1_e_60_qs;
+ logic ie0_1_e_60_wd;
+ logic ie0_1_e_61_qs;
+ logic ie0_1_e_61_wd;
+ logic ie0_1_e_62_qs;
+ logic ie0_1_e_62_wd;
+ logic ie0_1_e_63_qs;
+ logic ie0_1_e_63_wd;
+ logic ie0_2_we;
+ logic ie0_2_e_64_qs;
+ logic ie0_2_e_64_wd;
+ logic ie0_2_e_65_qs;
+ logic ie0_2_e_65_wd;
+ logic ie0_2_e_66_qs;
+ logic ie0_2_e_66_wd;
+ logic ie0_2_e_67_qs;
+ logic ie0_2_e_67_wd;
+ logic ie0_2_e_68_qs;
+ logic ie0_2_e_68_wd;
+ logic ie0_2_e_69_qs;
+ logic ie0_2_e_69_wd;
+ logic ie0_2_e_70_qs;
+ logic ie0_2_e_70_wd;
+ logic ie0_2_e_71_qs;
+ logic ie0_2_e_71_wd;
+ logic ie0_2_e_72_qs;
+ logic ie0_2_e_72_wd;
+ logic ie0_2_e_73_qs;
+ logic ie0_2_e_73_wd;
+ logic ie0_2_e_74_qs;
+ logic ie0_2_e_74_wd;
+ logic ie0_2_e_75_qs;
+ logic ie0_2_e_75_wd;
+ logic ie0_2_e_76_qs;
+ logic ie0_2_e_76_wd;
+ logic ie0_2_e_77_qs;
+ logic ie0_2_e_77_wd;
+ logic ie0_2_e_78_qs;
+ logic ie0_2_e_78_wd;
+ logic ie0_2_e_79_qs;
+ logic ie0_2_e_79_wd;
+ logic ie0_2_e_80_qs;
+ logic ie0_2_e_80_wd;
+ logic ie0_2_e_81_qs;
+ logic ie0_2_e_81_wd;
+ logic ie0_2_e_82_qs;
+ logic ie0_2_e_82_wd;
+ logic ie0_2_e_83_qs;
+ logic ie0_2_e_83_wd;
+ logic ie0_2_e_84_qs;
+ logic ie0_2_e_84_wd;
+ logic ie0_2_e_85_qs;
+ logic ie0_2_e_85_wd;
+ logic ie0_2_e_86_qs;
+ logic ie0_2_e_86_wd;
+ logic ie0_2_e_87_qs;
+ logic ie0_2_e_87_wd;
+ logic ie0_2_e_88_qs;
+ logic ie0_2_e_88_wd;
+ logic ie0_2_e_89_qs;
+ logic ie0_2_e_89_wd;
+ logic ie0_2_e_90_qs;
+ logic ie0_2_e_90_wd;
+ logic ie0_2_e_91_qs;
+ logic ie0_2_e_91_wd;
+ logic ie0_2_e_92_qs;
+ logic ie0_2_e_92_wd;
+ logic ie0_2_e_93_qs;
+ logic ie0_2_e_93_wd;
+ logic ie0_2_e_94_qs;
+ logic ie0_2_e_94_wd;
+ logic ie0_2_e_95_qs;
+ logic ie0_2_e_95_wd;
+ logic ie0_3_we;
+ logic ie0_3_e_96_qs;
+ logic ie0_3_e_96_wd;
+ logic ie0_3_e_97_qs;
+ logic ie0_3_e_97_wd;
+ logic ie0_3_e_98_qs;
+ logic ie0_3_e_98_wd;
+ logic ie0_3_e_99_qs;
+ logic ie0_3_e_99_wd;
+ logic ie0_3_e_100_qs;
+ logic ie0_3_e_100_wd;
+ logic ie0_3_e_101_qs;
+ logic ie0_3_e_101_wd;
+ logic ie0_3_e_102_qs;
+ logic ie0_3_e_102_wd;
+ logic ie0_3_e_103_qs;
+ logic ie0_3_e_103_wd;
+ logic ie0_3_e_104_qs;
+ logic ie0_3_e_104_wd;
+ logic ie0_3_e_105_qs;
+ logic ie0_3_e_105_wd;
+ logic ie0_3_e_106_qs;
+ logic ie0_3_e_106_wd;
+ logic ie0_3_e_107_qs;
+ logic ie0_3_e_107_wd;
+ logic ie0_3_e_108_qs;
+ logic ie0_3_e_108_wd;
+ logic ie0_3_e_109_qs;
+ logic ie0_3_e_109_wd;
+ logic ie0_3_e_110_qs;
+ logic ie0_3_e_110_wd;
+ logic ie0_3_e_111_qs;
+ logic ie0_3_e_111_wd;
+ logic ie0_3_e_112_qs;
+ logic ie0_3_e_112_wd;
+ logic ie0_3_e_113_qs;
+ logic ie0_3_e_113_wd;
+ logic ie0_3_e_114_qs;
+ logic ie0_3_e_114_wd;
+ logic ie0_3_e_115_qs;
+ logic ie0_3_e_115_wd;
+ logic ie0_3_e_116_qs;
+ logic ie0_3_e_116_wd;
+ logic ie0_3_e_117_qs;
+ logic ie0_3_e_117_wd;
+ logic ie0_3_e_118_qs;
+ logic ie0_3_e_118_wd;
+ logic ie0_3_e_119_qs;
+ logic ie0_3_e_119_wd;
+ logic ie0_3_e_120_qs;
+ logic ie0_3_e_120_wd;
+ logic ie0_3_e_121_qs;
+ logic ie0_3_e_121_wd;
+ logic ie0_3_e_122_qs;
+ logic ie0_3_e_122_wd;
+ logic ie0_3_e_123_qs;
+ logic ie0_3_e_123_wd;
+ logic ie0_3_e_124_qs;
+ logic ie0_3_e_124_wd;
+ logic ie0_3_e_125_qs;
+ logic ie0_3_e_125_wd;
+ logic ie0_3_e_126_qs;
+ logic ie0_3_e_126_wd;
+ logic ie0_3_e_127_qs;
+ logic ie0_3_e_127_wd;
+ logic ie0_4_we;
+ logic ie0_4_e_128_qs;
+ logic ie0_4_e_128_wd;
+ logic ie0_4_e_129_qs;
+ logic ie0_4_e_129_wd;
+ logic ie0_4_e_130_qs;
+ logic ie0_4_e_130_wd;
+ logic ie0_4_e_131_qs;
+ logic ie0_4_e_131_wd;
+ logic ie0_4_e_132_qs;
+ logic ie0_4_e_132_wd;
+ logic ie0_4_e_133_qs;
+ logic ie0_4_e_133_wd;
+ logic ie0_4_e_134_qs;
+ logic ie0_4_e_134_wd;
+ logic ie0_4_e_135_qs;
+ logic ie0_4_e_135_wd;
+ logic ie0_4_e_136_qs;
+ logic ie0_4_e_136_wd;
+ logic ie0_4_e_137_qs;
+ logic ie0_4_e_137_wd;
+ logic ie0_4_e_138_qs;
+ logic ie0_4_e_138_wd;
+ logic ie0_4_e_139_qs;
+ logic ie0_4_e_139_wd;
+ logic ie0_4_e_140_qs;
+ logic ie0_4_e_140_wd;
+ logic ie0_4_e_141_qs;
+ logic ie0_4_e_141_wd;
+ logic ie0_4_e_142_qs;
+ logic ie0_4_e_142_wd;
+ logic ie0_4_e_143_qs;
+ logic ie0_4_e_143_wd;
+ logic ie0_4_e_144_qs;
+ logic ie0_4_e_144_wd;
+ logic ie0_4_e_145_qs;
+ logic ie0_4_e_145_wd;
+ logic ie0_4_e_146_qs;
+ logic ie0_4_e_146_wd;
+ logic ie0_4_e_147_qs;
+ logic ie0_4_e_147_wd;
+ logic ie0_4_e_148_qs;
+ logic ie0_4_e_148_wd;
+ logic ie0_4_e_149_qs;
+ logic ie0_4_e_149_wd;
+ logic ie0_4_e_150_qs;
+ logic ie0_4_e_150_wd;
+ logic ie0_4_e_151_qs;
+ logic ie0_4_e_151_wd;
+ logic ie0_4_e_152_qs;
+ logic ie0_4_e_152_wd;
+ logic ie0_4_e_153_qs;
+ logic ie0_4_e_153_wd;
+ logic ie0_4_e_154_qs;
+ logic ie0_4_e_154_wd;
+ logic ie0_4_e_155_qs;
+ logic ie0_4_e_155_wd;
+ logic ie0_4_e_156_qs;
+ logic ie0_4_e_156_wd;
+ logic ie0_4_e_157_qs;
+ logic ie0_4_e_157_wd;
+ logic ie0_4_e_158_qs;
+ logic ie0_4_e_158_wd;
+ logic ie0_4_e_159_qs;
+ logic ie0_4_e_159_wd;
+ logic ie0_5_we;
+ logic ie0_5_e_160_qs;
+ logic ie0_5_e_160_wd;
+ logic ie0_5_e_161_qs;
+ logic ie0_5_e_161_wd;
+ logic ie0_5_e_162_qs;
+ logic ie0_5_e_162_wd;
+ logic ie0_5_e_163_qs;
+ logic ie0_5_e_163_wd;
+ logic ie0_5_e_164_qs;
+ logic ie0_5_e_164_wd;
+ logic ie0_5_e_165_qs;
+ logic ie0_5_e_165_wd;
+ logic ie0_5_e_166_qs;
+ logic ie0_5_e_166_wd;
+ logic ie0_5_e_167_qs;
+ logic ie0_5_e_167_wd;
+ logic ie0_5_e_168_qs;
+ logic ie0_5_e_168_wd;
+ logic ie0_5_e_169_qs;
+ logic ie0_5_e_169_wd;
+ logic ie0_5_e_170_qs;
+ logic ie0_5_e_170_wd;
+ logic ie0_5_e_171_qs;
+ logic ie0_5_e_171_wd;
+ logic ie0_5_e_172_qs;
+ logic ie0_5_e_172_wd;
+ logic ie0_5_e_173_qs;
+ logic ie0_5_e_173_wd;
+ logic ie0_5_e_174_qs;
+ logic ie0_5_e_174_wd;
+ logic ie0_5_e_175_qs;
+ logic ie0_5_e_175_wd;
+ logic ie0_5_e_176_qs;
+ logic ie0_5_e_176_wd;
+ logic ie0_5_e_177_qs;
+ logic ie0_5_e_177_wd;
+ logic ie0_5_e_178_qs;
+ logic ie0_5_e_178_wd;
+ logic ie0_5_e_179_qs;
+ logic ie0_5_e_179_wd;
+ logic ie0_5_e_180_qs;
+ logic ie0_5_e_180_wd;
+ logic ie0_5_e_181_qs;
+ logic ie0_5_e_181_wd;
+ logic ie0_5_e_182_qs;
+ logic ie0_5_e_182_wd;
+ logic ie0_5_e_183_qs;
+ logic ie0_5_e_183_wd;
+ logic ie0_5_e_184_qs;
+ logic ie0_5_e_184_wd;
+ logic ie0_5_e_185_qs;
+ logic ie0_5_e_185_wd;
+ logic ie0_5_e_186_qs;
+ logic ie0_5_e_186_wd;
+ logic ie0_5_e_187_qs;
+ logic ie0_5_e_187_wd;
+ logic ie0_5_e_188_qs;
+ logic ie0_5_e_188_wd;
+ logic ie0_5_e_189_qs;
+ logic ie0_5_e_189_wd;
+ logic ie1_0_we;
+ logic ie1_0_e_0_qs;
+ logic ie1_0_e_0_wd;
+ logic ie1_0_e_1_qs;
+ logic ie1_0_e_1_wd;
+ logic ie1_0_e_2_qs;
+ logic ie1_0_e_2_wd;
+ logic ie1_0_e_3_qs;
+ logic ie1_0_e_3_wd;
+ logic ie1_0_e_4_qs;
+ logic ie1_0_e_4_wd;
+ logic ie1_0_e_5_qs;
+ logic ie1_0_e_5_wd;
+ logic ie1_0_e_6_qs;
+ logic ie1_0_e_6_wd;
+ logic ie1_0_e_7_qs;
+ logic ie1_0_e_7_wd;
+ logic ie1_0_e_8_qs;
+ logic ie1_0_e_8_wd;
+ logic ie1_0_e_9_qs;
+ logic ie1_0_e_9_wd;
+ logic ie1_0_e_10_qs;
+ logic ie1_0_e_10_wd;
+ logic ie1_0_e_11_qs;
+ logic ie1_0_e_11_wd;
+ logic ie1_0_e_12_qs;
+ logic ie1_0_e_12_wd;
+ logic ie1_0_e_13_qs;
+ logic ie1_0_e_13_wd;
+ logic ie1_0_e_14_qs;
+ logic ie1_0_e_14_wd;
+ logic ie1_0_e_15_qs;
+ logic ie1_0_e_15_wd;
+ logic ie1_0_e_16_qs;
+ logic ie1_0_e_16_wd;
+ logic ie1_0_e_17_qs;
+ logic ie1_0_e_17_wd;
+ logic ie1_0_e_18_qs;
+ logic ie1_0_e_18_wd;
+ logic ie1_0_e_19_qs;
+ logic ie1_0_e_19_wd;
+ logic ie1_0_e_20_qs;
+ logic ie1_0_e_20_wd;
+ logic ie1_0_e_21_qs;
+ logic ie1_0_e_21_wd;
+ logic ie1_0_e_22_qs;
+ logic ie1_0_e_22_wd;
+ logic ie1_0_e_23_qs;
+ logic ie1_0_e_23_wd;
+ logic ie1_0_e_24_qs;
+ logic ie1_0_e_24_wd;
+ logic ie1_0_e_25_qs;
+ logic ie1_0_e_25_wd;
+ logic ie1_0_e_26_qs;
+ logic ie1_0_e_26_wd;
+ logic ie1_0_e_27_qs;
+ logic ie1_0_e_27_wd;
+ logic ie1_0_e_28_qs;
+ logic ie1_0_e_28_wd;
+ logic ie1_0_e_29_qs;
+ logic ie1_0_e_29_wd;
+ logic ie1_0_e_30_qs;
+ logic ie1_0_e_30_wd;
+ logic ie1_0_e_31_qs;
+ logic ie1_0_e_31_wd;
+ logic ie1_1_we;
+ logic ie1_1_e_32_qs;
+ logic ie1_1_e_32_wd;
+ logic ie1_1_e_33_qs;
+ logic ie1_1_e_33_wd;
+ logic ie1_1_e_34_qs;
+ logic ie1_1_e_34_wd;
+ logic ie1_1_e_35_qs;
+ logic ie1_1_e_35_wd;
+ logic ie1_1_e_36_qs;
+ logic ie1_1_e_36_wd;
+ logic ie1_1_e_37_qs;
+ logic ie1_1_e_37_wd;
+ logic ie1_1_e_38_qs;
+ logic ie1_1_e_38_wd;
+ logic ie1_1_e_39_qs;
+ logic ie1_1_e_39_wd;
+ logic ie1_1_e_40_qs;
+ logic ie1_1_e_40_wd;
+ logic ie1_1_e_41_qs;
+ logic ie1_1_e_41_wd;
+ logic ie1_1_e_42_qs;
+ logic ie1_1_e_42_wd;
+ logic ie1_1_e_43_qs;
+ logic ie1_1_e_43_wd;
+ logic ie1_1_e_44_qs;
+ logic ie1_1_e_44_wd;
+ logic ie1_1_e_45_qs;
+ logic ie1_1_e_45_wd;
+ logic ie1_1_e_46_qs;
+ logic ie1_1_e_46_wd;
+ logic ie1_1_e_47_qs;
+ logic ie1_1_e_47_wd;
+ logic ie1_1_e_48_qs;
+ logic ie1_1_e_48_wd;
+ logic ie1_1_e_49_qs;
+ logic ie1_1_e_49_wd;
+ logic ie1_1_e_50_qs;
+ logic ie1_1_e_50_wd;
+ logic ie1_1_e_51_qs;
+ logic ie1_1_e_51_wd;
+ logic ie1_1_e_52_qs;
+ logic ie1_1_e_52_wd;
+ logic ie1_1_e_53_qs;
+ logic ie1_1_e_53_wd;
+ logic ie1_1_e_54_qs;
+ logic ie1_1_e_54_wd;
+ logic ie1_1_e_55_qs;
+ logic ie1_1_e_55_wd;
+ logic ie1_1_e_56_qs;
+ logic ie1_1_e_56_wd;
+ logic ie1_1_e_57_qs;
+ logic ie1_1_e_57_wd;
+ logic ie1_1_e_58_qs;
+ logic ie1_1_e_58_wd;
+ logic ie1_1_e_59_qs;
+ logic ie1_1_e_59_wd;
+ logic ie1_1_e_60_qs;
+ logic ie1_1_e_60_wd;
+ logic ie1_1_e_61_qs;
+ logic ie1_1_e_61_wd;
+ logic ie1_1_e_62_qs;
+ logic ie1_1_e_62_wd;
+ logic ie1_1_e_63_qs;
+ logic ie1_1_e_63_wd;
+ logic ie1_2_we;
+ logic ie1_2_e_64_qs;
+ logic ie1_2_e_64_wd;
+ logic ie1_2_e_65_qs;
+ logic ie1_2_e_65_wd;
+ logic ie1_2_e_66_qs;
+ logic ie1_2_e_66_wd;
+ logic ie1_2_e_67_qs;
+ logic ie1_2_e_67_wd;
+ logic ie1_2_e_68_qs;
+ logic ie1_2_e_68_wd;
+ logic ie1_2_e_69_qs;
+ logic ie1_2_e_69_wd;
+ logic ie1_2_e_70_qs;
+ logic ie1_2_e_70_wd;
+ logic ie1_2_e_71_qs;
+ logic ie1_2_e_71_wd;
+ logic ie1_2_e_72_qs;
+ logic ie1_2_e_72_wd;
+ logic ie1_2_e_73_qs;
+ logic ie1_2_e_73_wd;
+ logic ie1_2_e_74_qs;
+ logic ie1_2_e_74_wd;
+ logic ie1_2_e_75_qs;
+ logic ie1_2_e_75_wd;
+ logic ie1_2_e_76_qs;
+ logic ie1_2_e_76_wd;
+ logic ie1_2_e_77_qs;
+ logic ie1_2_e_77_wd;
+ logic ie1_2_e_78_qs;
+ logic ie1_2_e_78_wd;
+ logic ie1_2_e_79_qs;
+ logic ie1_2_e_79_wd;
+ logic ie1_2_e_80_qs;
+ logic ie1_2_e_80_wd;
+ logic ie1_2_e_81_qs;
+ logic ie1_2_e_81_wd;
+ logic ie1_2_e_82_qs;
+ logic ie1_2_e_82_wd;
+ logic ie1_2_e_83_qs;
+ logic ie1_2_e_83_wd;
+ logic ie1_2_e_84_qs;
+ logic ie1_2_e_84_wd;
+ logic ie1_2_e_85_qs;
+ logic ie1_2_e_85_wd;
+ logic ie1_2_e_86_qs;
+ logic ie1_2_e_86_wd;
+ logic ie1_2_e_87_qs;
+ logic ie1_2_e_87_wd;
+ logic ie1_2_e_88_qs;
+ logic ie1_2_e_88_wd;
+ logic ie1_2_e_89_qs;
+ logic ie1_2_e_89_wd;
+ logic ie1_2_e_90_qs;
+ logic ie1_2_e_90_wd;
+ logic ie1_2_e_91_qs;
+ logic ie1_2_e_91_wd;
+ logic ie1_2_e_92_qs;
+ logic ie1_2_e_92_wd;
+ logic ie1_2_e_93_qs;
+ logic ie1_2_e_93_wd;
+ logic ie1_2_e_94_qs;
+ logic ie1_2_e_94_wd;
+ logic ie1_2_e_95_qs;
+ logic ie1_2_e_95_wd;
+ logic ie1_3_we;
+ logic ie1_3_e_96_qs;
+ logic ie1_3_e_96_wd;
+ logic ie1_3_e_97_qs;
+ logic ie1_3_e_97_wd;
+ logic ie1_3_e_98_qs;
+ logic ie1_3_e_98_wd;
+ logic ie1_3_e_99_qs;
+ logic ie1_3_e_99_wd;
+ logic ie1_3_e_100_qs;
+ logic ie1_3_e_100_wd;
+ logic ie1_3_e_101_qs;
+ logic ie1_3_e_101_wd;
+ logic ie1_3_e_102_qs;
+ logic ie1_3_e_102_wd;
+ logic ie1_3_e_103_qs;
+ logic ie1_3_e_103_wd;
+ logic ie1_3_e_104_qs;
+ logic ie1_3_e_104_wd;
+ logic ie1_3_e_105_qs;
+ logic ie1_3_e_105_wd;
+ logic ie1_3_e_106_qs;
+ logic ie1_3_e_106_wd;
+ logic ie1_3_e_107_qs;
+ logic ie1_3_e_107_wd;
+ logic ie1_3_e_108_qs;
+ logic ie1_3_e_108_wd;
+ logic ie1_3_e_109_qs;
+ logic ie1_3_e_109_wd;
+ logic ie1_3_e_110_qs;
+ logic ie1_3_e_110_wd;
+ logic ie1_3_e_111_qs;
+ logic ie1_3_e_111_wd;
+ logic ie1_3_e_112_qs;
+ logic ie1_3_e_112_wd;
+ logic ie1_3_e_113_qs;
+ logic ie1_3_e_113_wd;
+ logic ie1_3_e_114_qs;
+ logic ie1_3_e_114_wd;
+ logic ie1_3_e_115_qs;
+ logic ie1_3_e_115_wd;
+ logic ie1_3_e_116_qs;
+ logic ie1_3_e_116_wd;
+ logic ie1_3_e_117_qs;
+ logic ie1_3_e_117_wd;
+ logic ie1_3_e_118_qs;
+ logic ie1_3_e_118_wd;
+ logic ie1_3_e_119_qs;
+ logic ie1_3_e_119_wd;
+ logic ie1_3_e_120_qs;
+ logic ie1_3_e_120_wd;
+ logic ie1_3_e_121_qs;
+ logic ie1_3_e_121_wd;
+ logic ie1_3_e_122_qs;
+ logic ie1_3_e_122_wd;
+ logic ie1_3_e_123_qs;
+ logic ie1_3_e_123_wd;
+ logic ie1_3_e_124_qs;
+ logic ie1_3_e_124_wd;
+ logic ie1_3_e_125_qs;
+ logic ie1_3_e_125_wd;
+ logic ie1_3_e_126_qs;
+ logic ie1_3_e_126_wd;
+ logic ie1_3_e_127_qs;
+ logic ie1_3_e_127_wd;
+ logic ie1_4_we;
+ logic ie1_4_e_128_qs;
+ logic ie1_4_e_128_wd;
+ logic ie1_4_e_129_qs;
+ logic ie1_4_e_129_wd;
+ logic ie1_4_e_130_qs;
+ logic ie1_4_e_130_wd;
+ logic ie1_4_e_131_qs;
+ logic ie1_4_e_131_wd;
+ logic ie1_4_e_132_qs;
+ logic ie1_4_e_132_wd;
+ logic ie1_4_e_133_qs;
+ logic ie1_4_e_133_wd;
+ logic ie1_4_e_134_qs;
+ logic ie1_4_e_134_wd;
+ logic ie1_4_e_135_qs;
+ logic ie1_4_e_135_wd;
+ logic ie1_4_e_136_qs;
+ logic ie1_4_e_136_wd;
+ logic ie1_4_e_137_qs;
+ logic ie1_4_e_137_wd;
+ logic ie1_4_e_138_qs;
+ logic ie1_4_e_138_wd;
+ logic ie1_4_e_139_qs;
+ logic ie1_4_e_139_wd;
+ logic ie1_4_e_140_qs;
+ logic ie1_4_e_140_wd;
+ logic ie1_4_e_141_qs;
+ logic ie1_4_e_141_wd;
+ logic ie1_4_e_142_qs;
+ logic ie1_4_e_142_wd;
+ logic ie1_4_e_143_qs;
+ logic ie1_4_e_143_wd;
+ logic ie1_4_e_144_qs;
+ logic ie1_4_e_144_wd;
+ logic ie1_4_e_145_qs;
+ logic ie1_4_e_145_wd;
+ logic ie1_4_e_146_qs;
+ logic ie1_4_e_146_wd;
+ logic ie1_4_e_147_qs;
+ logic ie1_4_e_147_wd;
+ logic ie1_4_e_148_qs;
+ logic ie1_4_e_148_wd;
+ logic ie1_4_e_149_qs;
+ logic ie1_4_e_149_wd;
+ logic ie1_4_e_150_qs;
+ logic ie1_4_e_150_wd;
+ logic ie1_4_e_151_qs;
+ logic ie1_4_e_151_wd;
+ logic ie1_4_e_152_qs;
+ logic ie1_4_e_152_wd;
+ logic ie1_4_e_153_qs;
+ logic ie1_4_e_153_wd;
+ logic ie1_4_e_154_qs;
+ logic ie1_4_e_154_wd;
+ logic ie1_4_e_155_qs;
+ logic ie1_4_e_155_wd;
+ logic ie1_4_e_156_qs;
+ logic ie1_4_e_156_wd;
+ logic ie1_4_e_157_qs;
+ logic ie1_4_e_157_wd;
+ logic ie1_4_e_158_qs;
+ logic ie1_4_e_158_wd;
+ logic ie1_4_e_159_qs;
+ logic ie1_4_e_159_wd;
+ logic ie1_5_we;
+ logic ie1_5_e_160_qs;
+ logic ie1_5_e_160_wd;
+ logic ie1_5_e_161_qs;
+ logic ie1_5_e_161_wd;
+ logic ie1_5_e_162_qs;
+ logic ie1_5_e_162_wd;
+ logic ie1_5_e_163_qs;
+ logic ie1_5_e_163_wd;
+ logic ie1_5_e_164_qs;
+ logic ie1_5_e_164_wd;
+ logic ie1_5_e_165_qs;
+ logic ie1_5_e_165_wd;
+ logic ie1_5_e_166_qs;
+ logic ie1_5_e_166_wd;
+ logic ie1_5_e_167_qs;
+ logic ie1_5_e_167_wd;
+ logic ie1_5_e_168_qs;
+ logic ie1_5_e_168_wd;
+ logic ie1_5_e_169_qs;
+ logic ie1_5_e_169_wd;
+ logic ie1_5_e_170_qs;
+ logic ie1_5_e_170_wd;
+ logic ie1_5_e_171_qs;
+ logic ie1_5_e_171_wd;
+ logic ie1_5_e_172_qs;
+ logic ie1_5_e_172_wd;
+ logic ie1_5_e_173_qs;
+ logic ie1_5_e_173_wd;
+ logic ie1_5_e_174_qs;
+ logic ie1_5_e_174_wd;
+ logic ie1_5_e_175_qs;
+ logic ie1_5_e_175_wd;
+ logic ie1_5_e_176_qs;
+ logic ie1_5_e_176_wd;
+ logic ie1_5_e_177_qs;
+ logic ie1_5_e_177_wd;
+ logic ie1_5_e_178_qs;
+ logic ie1_5_e_178_wd;
+ logic ie1_5_e_179_qs;
+ logic ie1_5_e_179_wd;
+ logic ie1_5_e_180_qs;
+ logic ie1_5_e_180_wd;
+ logic ie1_5_e_181_qs;
+ logic ie1_5_e_181_wd;
+ logic ie1_5_e_182_qs;
+ logic ie1_5_e_182_wd;
+ logic ie1_5_e_183_qs;
+ logic ie1_5_e_183_wd;
+ logic ie1_5_e_184_qs;
+ logic ie1_5_e_184_wd;
+ logic ie1_5_e_185_qs;
+ logic ie1_5_e_185_wd;
+ logic ie1_5_e_186_qs;
+ logic ie1_5_e_186_wd;
+ logic ie1_5_e_187_qs;
+ logic ie1_5_e_187_wd;
+ logic ie1_5_e_188_qs;
+ logic ie1_5_e_188_wd;
+ logic ie1_5_e_189_qs;
+ logic ie1_5_e_189_wd;
+ logic threshold0_we;
+ logic [1:0] threshold0_qs;
+ logic [1:0] threshold0_wd;
+ logic cc0_re;
+ logic cc0_we;
+ logic [7:0] cc0_qs;
+ logic [7:0] cc0_wd;
+ logic threshold1_we;
+ logic [1:0] threshold1_qs;
+ logic [1:0] threshold1_wd;
+ logic cc1_re;
+ logic cc1_we;
+ logic [7:0] cc1_qs;
+ logic [7:0] cc1_wd;
+ logic msip0_we;
+ logic msip0_qs;
+ logic msip0_wd;
+ logic msip1_we;
+ logic msip1_qs;
+ logic msip1_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+
+ // Register instances
+ // R[prio0]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio0_we),
+ .wd (prio0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio0_qs)
+ );
+
+
+ // R[prio1]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio1_we),
+ .wd (prio1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio1_qs)
+ );
+
+
+ // R[prio2]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio2_we),
+ .wd (prio2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio2_qs)
+ );
+
+
+ // R[prio3]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio3_we),
+ .wd (prio3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio3_qs)
+ );
+
+
+ // R[prio4]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio4_we),
+ .wd (prio4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio4_qs)
+ );
+
+
+ // R[prio5]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio5_we),
+ .wd (prio5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio5_qs)
+ );
+
+
+ // R[prio6]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio6_we),
+ .wd (prio6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio6_qs)
+ );
+
+
+ // R[prio7]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio7_we),
+ .wd (prio7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio7_qs)
+ );
+
+
+ // R[prio8]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio8_we),
+ .wd (prio8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio8_qs)
+ );
+
+
+ // R[prio9]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio9_we),
+ .wd (prio9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio9.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio9_qs)
+ );
+
+
+ // R[prio10]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio10_we),
+ .wd (prio10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio10.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio10_qs)
+ );
+
+
+ // R[prio11]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio11_we),
+ .wd (prio11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio11.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio11_qs)
+ );
+
+
+ // R[prio12]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio12_we),
+ .wd (prio12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio12.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio12_qs)
+ );
+
+
+ // R[prio13]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio13_we),
+ .wd (prio13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio13.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio13_qs)
+ );
+
+
+ // R[prio14]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio14_we),
+ .wd (prio14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio14.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio14_qs)
+ );
+
+
+ // R[prio15]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio15_we),
+ .wd (prio15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio15.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio15_qs)
+ );
+
+
+ // R[prio16]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio16_we),
+ .wd (prio16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio16.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio16_qs)
+ );
+
+
+ // R[prio17]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio17_we),
+ .wd (prio17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio17.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio17_qs)
+ );
+
+
+ // R[prio18]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio18_we),
+ .wd (prio18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio18.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio18_qs)
+ );
+
+
+ // R[prio19]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio19_we),
+ .wd (prio19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio19.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio19_qs)
+ );
+
+
+ // R[prio20]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio20_we),
+ .wd (prio20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio20.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio20_qs)
+ );
+
+
+ // R[prio21]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio21_we),
+ .wd (prio21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio21.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio21_qs)
+ );
+
+
+ // R[prio22]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio22_we),
+ .wd (prio22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio22.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio22_qs)
+ );
+
+
+ // R[prio23]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio23_we),
+ .wd (prio23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio23.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio23_qs)
+ );
+
+
+ // R[prio24]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio24_we),
+ .wd (prio24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio24.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio24_qs)
+ );
+
+
+ // R[prio25]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio25_we),
+ .wd (prio25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio25.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio25_qs)
+ );
+
+
+ // R[prio26]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio26_we),
+ .wd (prio26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio26.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio26_qs)
+ );
+
+
+ // R[prio27]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio27_we),
+ .wd (prio27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio27.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio27_qs)
+ );
+
+
+ // R[prio28]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio28_we),
+ .wd (prio28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio28.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio28_qs)
+ );
+
+
+ // R[prio29]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio29_we),
+ .wd (prio29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio29.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio29_qs)
+ );
+
+
+ // R[prio30]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio30_we),
+ .wd (prio30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio30.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio30_qs)
+ );
+
+
+ // R[prio31]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio31_we),
+ .wd (prio31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio31.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio31_qs)
+ );
+
+
+ // R[prio32]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio32_we),
+ .wd (prio32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio32.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio32_qs)
+ );
+
+
+ // R[prio33]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio33_we),
+ .wd (prio33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio33.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio33_qs)
+ );
+
+
+ // R[prio34]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio34_we),
+ .wd (prio34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio34.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio34_qs)
+ );
+
+
+ // R[prio35]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio35_we),
+ .wd (prio35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio35.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio35_qs)
+ );
+
+
+ // R[prio36]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio36_we),
+ .wd (prio36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio36.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio36_qs)
+ );
+
+
+ // R[prio37]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio37_we),
+ .wd (prio37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio37.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio37_qs)
+ );
+
+
+ // R[prio38]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio38_we),
+ .wd (prio38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio38.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio38_qs)
+ );
+
+
+ // R[prio39]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio39_we),
+ .wd (prio39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio39.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio39_qs)
+ );
+
+
+ // R[prio40]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio40_we),
+ .wd (prio40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio40.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio40_qs)
+ );
+
+
+ // R[prio41]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio41_we),
+ .wd (prio41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio41.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio41_qs)
+ );
+
+
+ // R[prio42]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio42_we),
+ .wd (prio42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio42.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio42_qs)
+ );
+
+
+ // R[prio43]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio43_we),
+ .wd (prio43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio43.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio43_qs)
+ );
+
+
+ // R[prio44]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio44_we),
+ .wd (prio44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio44.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio44_qs)
+ );
+
+
+ // R[prio45]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio45_we),
+ .wd (prio45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio45.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio45_qs)
+ );
+
+
+ // R[prio46]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio46_we),
+ .wd (prio46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio46.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio46_qs)
+ );
+
+
+ // R[prio47]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio47_we),
+ .wd (prio47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio47.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio47_qs)
+ );
+
+
+ // R[prio48]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio48_we),
+ .wd (prio48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio48.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio48_qs)
+ );
+
+
+ // R[prio49]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio49_we),
+ .wd (prio49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio49.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio49_qs)
+ );
+
+
+ // R[prio50]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio50_we),
+ .wd (prio50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio50.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio50_qs)
+ );
+
+
+ // R[prio51]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio51_we),
+ .wd (prio51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio51.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio51_qs)
+ );
+
+
+ // R[prio52]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio52_we),
+ .wd (prio52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio52.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio52_qs)
+ );
+
+
+ // R[prio53]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio53_we),
+ .wd (prio53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio53.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio53_qs)
+ );
+
+
+ // R[prio54]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio54_we),
+ .wd (prio54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio54.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio54_qs)
+ );
+
+
+ // R[prio55]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio55_we),
+ .wd (prio55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio55.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio55_qs)
+ );
+
+
+ // R[prio56]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio56_we),
+ .wd (prio56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio56.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio56_qs)
+ );
+
+
+ // R[prio57]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio57_we),
+ .wd (prio57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio57.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio57_qs)
+ );
+
+
+ // R[prio58]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio58_we),
+ .wd (prio58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio58.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio58_qs)
+ );
+
+
+ // R[prio59]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio59_we),
+ .wd (prio59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio59.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio59_qs)
+ );
+
+
+ // R[prio60]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio60_we),
+ .wd (prio60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio60.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio60_qs)
+ );
+
+
+ // R[prio61]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio61_we),
+ .wd (prio61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio61.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio61_qs)
+ );
+
+
+ // R[prio62]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio62_we),
+ .wd (prio62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio62.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio62_qs)
+ );
+
+
+ // R[prio63]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio63_we),
+ .wd (prio63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio63.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio63_qs)
+ );
+
+
+ // R[prio64]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio64_we),
+ .wd (prio64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio64.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio64_qs)
+ );
+
+
+ // R[prio65]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio65_we),
+ .wd (prio65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio65.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio65_qs)
+ );
+
+
+ // R[prio66]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio66_we),
+ .wd (prio66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio66.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio66_qs)
+ );
+
+
+ // R[prio67]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio67_we),
+ .wd (prio67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio67.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio67_qs)
+ );
+
+
+ // R[prio68]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio68_we),
+ .wd (prio68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio68.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio68_qs)
+ );
+
+
+ // R[prio69]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio69_we),
+ .wd (prio69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio69.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio69_qs)
+ );
+
+
+ // R[prio70]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio70_we),
+ .wd (prio70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio70.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio70_qs)
+ );
+
+
+ // R[prio71]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio71_we),
+ .wd (prio71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio71.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio71_qs)
+ );
+
+
+ // R[prio72]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio72_we),
+ .wd (prio72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio72.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio72_qs)
+ );
+
+
+ // R[prio73]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio73_we),
+ .wd (prio73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio73.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio73_qs)
+ );
+
+
+ // R[prio74]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio74_we),
+ .wd (prio74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio74.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio74_qs)
+ );
+
+
+ // R[prio75]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio75_we),
+ .wd (prio75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio75.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio75_qs)
+ );
+
+
+ // R[prio76]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio76 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio76_we),
+ .wd (prio76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio76.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio76_qs)
+ );
+
+
+ // R[prio77]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio77 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio77_we),
+ .wd (prio77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio77.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio77_qs)
+ );
+
+
+ // R[prio78]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio78 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio78_we),
+ .wd (prio78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio78.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio78_qs)
+ );
+
+
+ // R[prio79]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio79 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio79_we),
+ .wd (prio79_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio79.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio79_qs)
+ );
+
+
+ // R[prio80]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio80 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio80_we),
+ .wd (prio80_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio80.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio80_qs)
+ );
+
+
+ // R[prio81]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio81 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio81_we),
+ .wd (prio81_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio81.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio81_qs)
+ );
+
+
+ // R[prio82]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio82 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio82_we),
+ .wd (prio82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio82.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio82_qs)
+ );
+
+
+ // R[prio83]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio83 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio83_we),
+ .wd (prio83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio83.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio83_qs)
+ );
+
+
+ // R[prio84]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio84 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio84_we),
+ .wd (prio84_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio84.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio84_qs)
+ );
+
+
+ // R[prio85]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio85 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio85_we),
+ .wd (prio85_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio85.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio85_qs)
+ );
+
+
+ // R[prio86]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio86 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio86_we),
+ .wd (prio86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio86.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio86_qs)
+ );
+
+
+ // R[prio87]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio87 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio87_we),
+ .wd (prio87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio87.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio87_qs)
+ );
+
+
+ // R[prio88]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio88 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio88_we),
+ .wd (prio88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio88.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio88_qs)
+ );
+
+
+ // R[prio89]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio89 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio89_we),
+ .wd (prio89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio89.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio89_qs)
+ );
+
+
+ // R[prio90]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio90 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio90_we),
+ .wd (prio90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio90.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio90_qs)
+ );
+
+
+ // R[prio91]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio91 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio91_we),
+ .wd (prio91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio91.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio91_qs)
+ );
+
+
+ // R[prio92]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio92 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio92_we),
+ .wd (prio92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio92.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio92_qs)
+ );
+
+
+ // R[prio93]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio93 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio93_we),
+ .wd (prio93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio93.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio93_qs)
+ );
+
+
+ // R[prio94]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio94 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio94_we),
+ .wd (prio94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio94.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio94_qs)
+ );
+
+
+ // R[prio95]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio95 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio95_we),
+ .wd (prio95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio95.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio95_qs)
+ );
+
+
+ // R[prio96]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio96 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio96_we),
+ .wd (prio96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio96.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio96_qs)
+ );
+
+
+ // R[prio97]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio97 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio97_we),
+ .wd (prio97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio97.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio97_qs)
+ );
+
+
+ // R[prio98]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio98 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio98_we),
+ .wd (prio98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio98.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio98_qs)
+ );
+
+
+ // R[prio99]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio99 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio99_we),
+ .wd (prio99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio99.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio99_qs)
+ );
+
+
+ // R[prio100]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio100 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio100_we),
+ .wd (prio100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio100.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio100_qs)
+ );
+
+
+ // R[prio101]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio101 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio101_we),
+ .wd (prio101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio101.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio101_qs)
+ );
+
+
+ // R[prio102]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio102 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio102_we),
+ .wd (prio102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio102.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio102_qs)
+ );
+
+
+ // R[prio103]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio103 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio103_we),
+ .wd (prio103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio103.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio103_qs)
+ );
+
+
+ // R[prio104]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio104 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio104_we),
+ .wd (prio104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio104.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio104_qs)
+ );
+
+
+ // R[prio105]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio105 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio105_we),
+ .wd (prio105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio105.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio105_qs)
+ );
+
+
+ // R[prio106]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio106 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio106_we),
+ .wd (prio106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio106.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio106_qs)
+ );
+
+
+ // R[prio107]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio107 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio107_we),
+ .wd (prio107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio107.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio107_qs)
+ );
+
+
+ // R[prio108]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio108 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio108_we),
+ .wd (prio108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio108.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio108_qs)
+ );
+
+
+ // R[prio109]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio109 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio109_we),
+ .wd (prio109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio109.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio109_qs)
+ );
+
+
+ // R[prio110]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio110 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio110_we),
+ .wd (prio110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio110.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio110_qs)
+ );
+
+
+ // R[prio111]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio111 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio111_we),
+ .wd (prio111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio111.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio111_qs)
+ );
+
+
+ // R[prio112]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio112 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio112_we),
+ .wd (prio112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio112.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio112_qs)
+ );
+
+
+ // R[prio113]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio113 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio113_we),
+ .wd (prio113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio113.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio113_qs)
+ );
+
+
+ // R[prio114]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio114 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio114_we),
+ .wd (prio114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio114.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio114_qs)
+ );
+
+
+ // R[prio115]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio115 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio115_we),
+ .wd (prio115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio115.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio115_qs)
+ );
+
+
+ // R[prio116]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio116 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio116_we),
+ .wd (prio116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio116.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio116_qs)
+ );
+
+
+ // R[prio117]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio117 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio117_we),
+ .wd (prio117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio117.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio117_qs)
+ );
+
+
+ // R[prio118]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio118 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio118_we),
+ .wd (prio118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio118.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio118_qs)
+ );
+
+
+ // R[prio119]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio119 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio119_we),
+ .wd (prio119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio119.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio119_qs)
+ );
+
+
+ // R[prio120]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio120 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio120_we),
+ .wd (prio120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio120.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio120_qs)
+ );
+
+
+ // R[prio121]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio121 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio121_we),
+ .wd (prio121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio121.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio121_qs)
+ );
+
+
+ // R[prio122]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio122 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio122_we),
+ .wd (prio122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio122.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio122_qs)
+ );
+
+
+ // R[prio123]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio123 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio123_we),
+ .wd (prio123_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio123.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio123_qs)
+ );
+
+
+ // R[prio124]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio124 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio124_we),
+ .wd (prio124_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio124.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio124_qs)
+ );
+
+
+ // R[prio125]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio125 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio125_we),
+ .wd (prio125_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio125.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio125_qs)
+ );
+
+
+ // R[prio126]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio126 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio126_we),
+ .wd (prio126_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio126.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio126_qs)
+ );
+
+
+ // R[prio127]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio127 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio127_we),
+ .wd (prio127_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio127.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio127_qs)
+ );
+
+
+ // R[prio128]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio128 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio128_we),
+ .wd (prio128_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio128.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio128_qs)
+ );
+
+
+ // R[prio129]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio129 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio129_we),
+ .wd (prio129_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio129.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio129_qs)
+ );
+
+
+ // R[prio130]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio130 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio130_we),
+ .wd (prio130_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio130.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio130_qs)
+ );
+
+
+ // R[prio131]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio131 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio131_we),
+ .wd (prio131_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio131.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio131_qs)
+ );
+
+
+ // R[prio132]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio132 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio132_we),
+ .wd (prio132_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio132.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio132_qs)
+ );
+
+
+ // R[prio133]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio133 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio133_we),
+ .wd (prio133_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio133.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio133_qs)
+ );
+
+
+ // R[prio134]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio134 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio134_we),
+ .wd (prio134_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio134.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio134_qs)
+ );
+
+
+ // R[prio135]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio135 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio135_we),
+ .wd (prio135_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio135.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio135_qs)
+ );
+
+
+ // R[prio136]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio136 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio136_we),
+ .wd (prio136_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio136.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio136_qs)
+ );
+
+
+ // R[prio137]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio137 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio137_we),
+ .wd (prio137_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio137.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio137_qs)
+ );
+
+
+ // R[prio138]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio138 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio138_we),
+ .wd (prio138_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio138.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio138_qs)
+ );
+
+
+ // R[prio139]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio139 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio139_we),
+ .wd (prio139_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio139.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio139_qs)
+ );
+
+
+ // R[prio140]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio140 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio140_we),
+ .wd (prio140_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio140.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio140_qs)
+ );
+
+
+ // R[prio141]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio141 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio141_we),
+ .wd (prio141_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio141.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio141_qs)
+ );
+
+
+ // R[prio142]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio142 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio142_we),
+ .wd (prio142_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio142.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio142_qs)
+ );
+
+
+ // R[prio143]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio143 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio143_we),
+ .wd (prio143_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio143.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio143_qs)
+ );
+
+
+ // R[prio144]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio144 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio144_we),
+ .wd (prio144_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio144.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio144_qs)
+ );
+
+
+ // R[prio145]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio145 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio145_we),
+ .wd (prio145_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio145.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio145_qs)
+ );
+
+
+ // R[prio146]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio146 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio146_we),
+ .wd (prio146_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio146.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio146_qs)
+ );
+
+
+ // R[prio147]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio147 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio147_we),
+ .wd (prio147_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio147.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio147_qs)
+ );
+
+
+ // R[prio148]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio148 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio148_we),
+ .wd (prio148_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio148.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio148_qs)
+ );
+
+
+ // R[prio149]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio149 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio149_we),
+ .wd (prio149_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio149.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio149_qs)
+ );
+
+
+ // R[prio150]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio150 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio150_we),
+ .wd (prio150_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio150.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio150_qs)
+ );
+
+
+ // R[prio151]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio151 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio151_we),
+ .wd (prio151_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio151.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio151_qs)
+ );
+
+
+ // R[prio152]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio152 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio152_we),
+ .wd (prio152_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio152.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio152_qs)
+ );
+
+
+ // R[prio153]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio153 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio153_we),
+ .wd (prio153_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio153.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio153_qs)
+ );
+
+
+ // R[prio154]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio154 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio154_we),
+ .wd (prio154_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio154.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio154_qs)
+ );
+
+
+ // R[prio155]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio155 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio155_we),
+ .wd (prio155_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio155.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio155_qs)
+ );
+
+
+ // R[prio156]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio156 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio156_we),
+ .wd (prio156_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio156.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio156_qs)
+ );
+
+
+ // R[prio157]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio157 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio157_we),
+ .wd (prio157_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio157.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio157_qs)
+ );
+
+
+ // R[prio158]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio158 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio158_we),
+ .wd (prio158_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio158.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio158_qs)
+ );
+
+
+ // R[prio159]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio159 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio159_we),
+ .wd (prio159_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio159.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio159_qs)
+ );
+
+
+ // R[prio160]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio160 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio160_we),
+ .wd (prio160_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio160.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio160_qs)
+ );
+
+
+ // R[prio161]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio161 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio161_we),
+ .wd (prio161_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio161.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio161_qs)
+ );
+
+
+ // R[prio162]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio162 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio162_we),
+ .wd (prio162_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio162.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio162_qs)
+ );
+
+
+ // R[prio163]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio163 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio163_we),
+ .wd (prio163_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio163.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio163_qs)
+ );
+
+
+ // R[prio164]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio164 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio164_we),
+ .wd (prio164_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio164.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio164_qs)
+ );
+
+
+ // R[prio165]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio165 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio165_we),
+ .wd (prio165_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio165.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio165_qs)
+ );
+
+
+ // R[prio166]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio166 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio166_we),
+ .wd (prio166_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio166.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio166_qs)
+ );
+
+
+ // R[prio167]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio167 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio167_we),
+ .wd (prio167_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio167.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio167_qs)
+ );
+
+
+ // R[prio168]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio168 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio168_we),
+ .wd (prio168_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio168.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio168_qs)
+ );
+
+
+ // R[prio169]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio169 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio169_we),
+ .wd (prio169_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio169.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio169_qs)
+ );
+
+
+ // R[prio170]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio170 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio170_we),
+ .wd (prio170_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio170.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio170_qs)
+ );
+
+
+ // R[prio171]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio171 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio171_we),
+ .wd (prio171_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio171.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio171_qs)
+ );
+
+
+ // R[prio172]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio172 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio172_we),
+ .wd (prio172_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio172.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio172_qs)
+ );
+
+
+ // R[prio173]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio173 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio173_we),
+ .wd (prio173_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio173.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio173_qs)
+ );
+
+
+ // R[prio174]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio174 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio174_we),
+ .wd (prio174_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio174.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio174_qs)
+ );
+
+
+ // R[prio175]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio175 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio175_we),
+ .wd (prio175_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio175.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio175_qs)
+ );
+
+
+ // R[prio176]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio176 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio176_we),
+ .wd (prio176_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio176.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio176_qs)
+ );
+
+
+ // R[prio177]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio177 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio177_we),
+ .wd (prio177_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio177.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio177_qs)
+ );
+
+
+ // R[prio178]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio178 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio178_we),
+ .wd (prio178_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio178.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio178_qs)
+ );
+
+
+ // R[prio179]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio179 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio179_we),
+ .wd (prio179_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio179.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio179_qs)
+ );
+
+
+ // R[prio180]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio180 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio180_we),
+ .wd (prio180_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio180.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio180_qs)
+ );
+
+
+ // R[prio181]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio181 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio181_we),
+ .wd (prio181_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio181.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio181_qs)
+ );
+
+
+ // R[prio182]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio182 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio182_we),
+ .wd (prio182_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio182.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio182_qs)
+ );
+
+
+ // R[prio183]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio183 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio183_we),
+ .wd (prio183_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio183.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio183_qs)
+ );
+
+
+ // R[prio184]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio184 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio184_we),
+ .wd (prio184_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio184.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio184_qs)
+ );
+
+
+ // R[prio185]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio185 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio185_we),
+ .wd (prio185_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio185.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio185_qs)
+ );
+
+
+ // R[prio186]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio186 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio186_we),
+ .wd (prio186_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio186.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio186_qs)
+ );
+
+
+ // R[prio187]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio187 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio187_we),
+ .wd (prio187_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio187.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio187_qs)
+ );
+
+
+ // R[prio188]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio188 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio188_we),
+ .wd (prio188_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio188.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio188_qs)
+ );
+
+
+ // R[prio189]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio189 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio189_we),
+ .wd (prio189_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio189.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio189_qs)
+ );
+
+
+ // Subregister 0 of Multireg ip
+ // R[ip_0]: V(False)
+ // F[p_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[0].de),
+ .d (hw2reg.ip[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_0_qs)
+ );
+
+ // F[p_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[1].de),
+ .d (hw2reg.ip[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_1_qs)
+ );
+
+ // F[p_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[2].de),
+ .d (hw2reg.ip[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_2_qs)
+ );
+
+ // F[p_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[3].de),
+ .d (hw2reg.ip[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_3_qs)
+ );
+
+ // F[p_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[4].de),
+ .d (hw2reg.ip[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_4_qs)
+ );
+
+ // F[p_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[5].de),
+ .d (hw2reg.ip[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_5_qs)
+ );
+
+ // F[p_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[6].de),
+ .d (hw2reg.ip[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_6_qs)
+ );
+
+ // F[p_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[7].de),
+ .d (hw2reg.ip[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_7_qs)
+ );
+
+ // F[p_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[8].de),
+ .d (hw2reg.ip[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_8_qs)
+ );
+
+ // F[p_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[9].de),
+ .d (hw2reg.ip[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_9_qs)
+ );
+
+ // F[p_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[10].de),
+ .d (hw2reg.ip[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_10_qs)
+ );
+
+ // F[p_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[11].de),
+ .d (hw2reg.ip[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_11_qs)
+ );
+
+ // F[p_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[12].de),
+ .d (hw2reg.ip[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_12_qs)
+ );
+
+ // F[p_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[13].de),
+ .d (hw2reg.ip[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_13_qs)
+ );
+
+ // F[p_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[14].de),
+ .d (hw2reg.ip[14].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_14_qs)
+ );
+
+ // F[p_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[15].de),
+ .d (hw2reg.ip[15].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_15_qs)
+ );
+
+ // F[p_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[16].de),
+ .d (hw2reg.ip[16].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_16_qs)
+ );
+
+ // F[p_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[17].de),
+ .d (hw2reg.ip[17].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_17_qs)
+ );
+
+ // F[p_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[18].de),
+ .d (hw2reg.ip[18].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_18_qs)
+ );
+
+ // F[p_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[19].de),
+ .d (hw2reg.ip[19].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_19_qs)
+ );
+
+ // F[p_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[20].de),
+ .d (hw2reg.ip[20].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_20_qs)
+ );
+
+ // F[p_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[21].de),
+ .d (hw2reg.ip[21].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_21_qs)
+ );
+
+ // F[p_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[22].de),
+ .d (hw2reg.ip[22].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_22_qs)
+ );
+
+ // F[p_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[23].de),
+ .d (hw2reg.ip[23].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_23_qs)
+ );
+
+ // F[p_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[24].de),
+ .d (hw2reg.ip[24].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_24_qs)
+ );
+
+ // F[p_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[25].de),
+ .d (hw2reg.ip[25].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_25_qs)
+ );
+
+ // F[p_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[26].de),
+ .d (hw2reg.ip[26].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_26_qs)
+ );
+
+ // F[p_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[27].de),
+ .d (hw2reg.ip[27].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_27_qs)
+ );
+
+ // F[p_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[28].de),
+ .d (hw2reg.ip[28].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_28_qs)
+ );
+
+ // F[p_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[29].de),
+ .d (hw2reg.ip[29].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_29_qs)
+ );
+
+ // F[p_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[30].de),
+ .d (hw2reg.ip[30].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_30_qs)
+ );
+
+ // F[p_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[31].de),
+ .d (hw2reg.ip[31].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg ip
+ // R[ip_1]: V(False)
+ // F[p_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[32].de),
+ .d (hw2reg.ip[32].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_32_qs)
+ );
+
+ // F[p_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[33].de),
+ .d (hw2reg.ip[33].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_33_qs)
+ );
+
+ // F[p_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[34].de),
+ .d (hw2reg.ip[34].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_34_qs)
+ );
+
+ // F[p_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[35].de),
+ .d (hw2reg.ip[35].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_35_qs)
+ );
+
+ // F[p_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[36].de),
+ .d (hw2reg.ip[36].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_36_qs)
+ );
+
+ // F[p_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[37].de),
+ .d (hw2reg.ip[37].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_37_qs)
+ );
+
+ // F[p_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[38].de),
+ .d (hw2reg.ip[38].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_38_qs)
+ );
+
+ // F[p_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[39].de),
+ .d (hw2reg.ip[39].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_39_qs)
+ );
+
+ // F[p_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[40].de),
+ .d (hw2reg.ip[40].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_40_qs)
+ );
+
+ // F[p_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[41].de),
+ .d (hw2reg.ip[41].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_41_qs)
+ );
+
+ // F[p_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[42].de),
+ .d (hw2reg.ip[42].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_42_qs)
+ );
+
+ // F[p_43]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[43].de),
+ .d (hw2reg.ip[43].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_43_qs)
+ );
+
+ // F[p_44]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[44].de),
+ .d (hw2reg.ip[44].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_44_qs)
+ );
+
+ // F[p_45]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[45].de),
+ .d (hw2reg.ip[45].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_45_qs)
+ );
+
+ // F[p_46]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[46].de),
+ .d (hw2reg.ip[46].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_46_qs)
+ );
+
+ // F[p_47]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[47].de),
+ .d (hw2reg.ip[47].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_47_qs)
+ );
+
+ // F[p_48]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[48].de),
+ .d (hw2reg.ip[48].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_48_qs)
+ );
+
+ // F[p_49]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[49].de),
+ .d (hw2reg.ip[49].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_49_qs)
+ );
+
+ // F[p_50]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[50].de),
+ .d (hw2reg.ip[50].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_50_qs)
+ );
+
+ // F[p_51]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[51].de),
+ .d (hw2reg.ip[51].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_51_qs)
+ );
+
+ // F[p_52]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[52].de),
+ .d (hw2reg.ip[52].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_52_qs)
+ );
+
+ // F[p_53]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[53].de),
+ .d (hw2reg.ip[53].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_53_qs)
+ );
+
+ // F[p_54]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[54].de),
+ .d (hw2reg.ip[54].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_54_qs)
+ );
+
+ // F[p_55]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[55].de),
+ .d (hw2reg.ip[55].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_55_qs)
+ );
+
+ // F[p_56]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[56].de),
+ .d (hw2reg.ip[56].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_56_qs)
+ );
+
+ // F[p_57]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[57].de),
+ .d (hw2reg.ip[57].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_57_qs)
+ );
+
+ // F[p_58]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[58].de),
+ .d (hw2reg.ip[58].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_58_qs)
+ );
+
+ // F[p_59]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[59].de),
+ .d (hw2reg.ip[59].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_59_qs)
+ );
+
+ // F[p_60]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[60].de),
+ .d (hw2reg.ip[60].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_60_qs)
+ );
+
+ // F[p_61]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[61].de),
+ .d (hw2reg.ip[61].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_61_qs)
+ );
+
+ // F[p_62]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[62].de),
+ .d (hw2reg.ip[62].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_62_qs)
+ );
+
+ // F[p_63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[63].de),
+ .d (hw2reg.ip[63].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_63_qs)
+ );
+
+
+ // Subregister 2 of Multireg ip
+ // R[ip_2]: V(False)
+ // F[p_64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[64].de),
+ .d (hw2reg.ip[64].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_64_qs)
+ );
+
+ // F[p_65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[65].de),
+ .d (hw2reg.ip[65].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_65_qs)
+ );
+
+ // F[p_66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[66].de),
+ .d (hw2reg.ip[66].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_66_qs)
+ );
+
+ // F[p_67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[67].de),
+ .d (hw2reg.ip[67].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_67_qs)
+ );
+
+ // F[p_68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[68].de),
+ .d (hw2reg.ip[68].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_68_qs)
+ );
+
+ // F[p_69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[69].de),
+ .d (hw2reg.ip[69].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_69_qs)
+ );
+
+ // F[p_70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[70].de),
+ .d (hw2reg.ip[70].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_70_qs)
+ );
+
+ // F[p_71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[71].de),
+ .d (hw2reg.ip[71].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_71_qs)
+ );
+
+ // F[p_72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[72].de),
+ .d (hw2reg.ip[72].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_72_qs)
+ );
+
+ // F[p_73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[73].de),
+ .d (hw2reg.ip[73].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_73_qs)
+ );
+
+ // F[p_74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[74].de),
+ .d (hw2reg.ip[74].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_74_qs)
+ );
+
+ // F[p_75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[75].de),
+ .d (hw2reg.ip[75].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_75_qs)
+ );
+
+ // F[p_76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_76 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[76].de),
+ .d (hw2reg.ip[76].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_76_qs)
+ );
+
+ // F[p_77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_77 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[77].de),
+ .d (hw2reg.ip[77].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_77_qs)
+ );
+
+ // F[p_78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_78 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[78].de),
+ .d (hw2reg.ip[78].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_78_qs)
+ );
+
+ // F[p_79]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_79 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[79].de),
+ .d (hw2reg.ip[79].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_79_qs)
+ );
+
+ // F[p_80]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_80 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[80].de),
+ .d (hw2reg.ip[80].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_80_qs)
+ );
+
+ // F[p_81]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_81 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[81].de),
+ .d (hw2reg.ip[81].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_81_qs)
+ );
+
+ // F[p_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_82 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[82].de),
+ .d (hw2reg.ip[82].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_82_qs)
+ );
+
+ // F[p_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_83 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[83].de),
+ .d (hw2reg.ip[83].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_83_qs)
+ );
+
+ // F[p_84]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_84 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[84].de),
+ .d (hw2reg.ip[84].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_84_qs)
+ );
+
+ // F[p_85]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_85 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[85].de),
+ .d (hw2reg.ip[85].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_85_qs)
+ );
+
+ // F[p_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_86 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[86].de),
+ .d (hw2reg.ip[86].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_86_qs)
+ );
+
+ // F[p_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_87 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[87].de),
+ .d (hw2reg.ip[87].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_87_qs)
+ );
+
+ // F[p_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_88 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[88].de),
+ .d (hw2reg.ip[88].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_88_qs)
+ );
+
+ // F[p_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_89 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[89].de),
+ .d (hw2reg.ip[89].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_89_qs)
+ );
+
+ // F[p_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_90 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[90].de),
+ .d (hw2reg.ip[90].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_90_qs)
+ );
+
+ // F[p_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_91 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[91].de),
+ .d (hw2reg.ip[91].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_91_qs)
+ );
+
+ // F[p_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_92 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[92].de),
+ .d (hw2reg.ip[92].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_92_qs)
+ );
+
+ // F[p_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_93 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[93].de),
+ .d (hw2reg.ip[93].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_93_qs)
+ );
+
+ // F[p_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_94 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[94].de),
+ .d (hw2reg.ip[94].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_94_qs)
+ );
+
+ // F[p_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_95 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[95].de),
+ .d (hw2reg.ip[95].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_2_p_95_qs)
+ );
+
+
+ // Subregister 3 of Multireg ip
+ // R[ip_3]: V(False)
+ // F[p_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_96 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[96].de),
+ .d (hw2reg.ip[96].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_96_qs)
+ );
+
+ // F[p_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_97 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[97].de),
+ .d (hw2reg.ip[97].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_97_qs)
+ );
+
+ // F[p_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_98 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[98].de),
+ .d (hw2reg.ip[98].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_98_qs)
+ );
+
+ // F[p_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_99 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[99].de),
+ .d (hw2reg.ip[99].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_99_qs)
+ );
+
+ // F[p_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_100 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[100].de),
+ .d (hw2reg.ip[100].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_100_qs)
+ );
+
+ // F[p_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_101 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[101].de),
+ .d (hw2reg.ip[101].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_101_qs)
+ );
+
+ // F[p_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_102 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[102].de),
+ .d (hw2reg.ip[102].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_102_qs)
+ );
+
+ // F[p_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_103 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[103].de),
+ .d (hw2reg.ip[103].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_103_qs)
+ );
+
+ // F[p_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_104 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[104].de),
+ .d (hw2reg.ip[104].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_104_qs)
+ );
+
+ // F[p_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_105 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[105].de),
+ .d (hw2reg.ip[105].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_105_qs)
+ );
+
+ // F[p_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_106 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[106].de),
+ .d (hw2reg.ip[106].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_106_qs)
+ );
+
+ // F[p_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_107 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[107].de),
+ .d (hw2reg.ip[107].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_107_qs)
+ );
+
+ // F[p_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_108 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[108].de),
+ .d (hw2reg.ip[108].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_108_qs)
+ );
+
+ // F[p_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_109 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[109].de),
+ .d (hw2reg.ip[109].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_109_qs)
+ );
+
+ // F[p_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_110 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[110].de),
+ .d (hw2reg.ip[110].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_110_qs)
+ );
+
+ // F[p_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_111 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[111].de),
+ .d (hw2reg.ip[111].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_111_qs)
+ );
+
+ // F[p_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_112 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[112].de),
+ .d (hw2reg.ip[112].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_112_qs)
+ );
+
+ // F[p_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_113 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[113].de),
+ .d (hw2reg.ip[113].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_113_qs)
+ );
+
+ // F[p_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_114 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[114].de),
+ .d (hw2reg.ip[114].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_114_qs)
+ );
+
+ // F[p_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_115 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[115].de),
+ .d (hw2reg.ip[115].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_115_qs)
+ );
+
+ // F[p_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_116 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[116].de),
+ .d (hw2reg.ip[116].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_116_qs)
+ );
+
+ // F[p_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_117 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[117].de),
+ .d (hw2reg.ip[117].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_117_qs)
+ );
+
+ // F[p_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_118 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[118].de),
+ .d (hw2reg.ip[118].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_118_qs)
+ );
+
+ // F[p_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_119 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[119].de),
+ .d (hw2reg.ip[119].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_119_qs)
+ );
+
+ // F[p_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_120 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[120].de),
+ .d (hw2reg.ip[120].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_120_qs)
+ );
+
+ // F[p_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_121 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[121].de),
+ .d (hw2reg.ip[121].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_121_qs)
+ );
+
+ // F[p_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_122 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[122].de),
+ .d (hw2reg.ip[122].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_122_qs)
+ );
+
+ // F[p_123]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_123 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[123].de),
+ .d (hw2reg.ip[123].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_123_qs)
+ );
+
+ // F[p_124]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_124 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[124].de),
+ .d (hw2reg.ip[124].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_124_qs)
+ );
+
+ // F[p_125]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_125 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[125].de),
+ .d (hw2reg.ip[125].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_125_qs)
+ );
+
+ // F[p_126]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_126 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[126].de),
+ .d (hw2reg.ip[126].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_126_qs)
+ );
+
+ // F[p_127]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_3_p_127 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[127].de),
+ .d (hw2reg.ip[127].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_3_p_127_qs)
+ );
+
+
+ // Subregister 4 of Multireg ip
+ // R[ip_4]: V(False)
+ // F[p_128]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_128 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[128].de),
+ .d (hw2reg.ip[128].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_128_qs)
+ );
+
+ // F[p_129]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_129 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[129].de),
+ .d (hw2reg.ip[129].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_129_qs)
+ );
+
+ // F[p_130]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_130 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[130].de),
+ .d (hw2reg.ip[130].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_130_qs)
+ );
+
+ // F[p_131]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_131 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[131].de),
+ .d (hw2reg.ip[131].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_131_qs)
+ );
+
+ // F[p_132]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_132 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[132].de),
+ .d (hw2reg.ip[132].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_132_qs)
+ );
+
+ // F[p_133]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_133 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[133].de),
+ .d (hw2reg.ip[133].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_133_qs)
+ );
+
+ // F[p_134]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_134 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[134].de),
+ .d (hw2reg.ip[134].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_134_qs)
+ );
+
+ // F[p_135]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_135 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[135].de),
+ .d (hw2reg.ip[135].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_135_qs)
+ );
+
+ // F[p_136]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_136 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[136].de),
+ .d (hw2reg.ip[136].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_136_qs)
+ );
+
+ // F[p_137]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_137 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[137].de),
+ .d (hw2reg.ip[137].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_137_qs)
+ );
+
+ // F[p_138]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_138 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[138].de),
+ .d (hw2reg.ip[138].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_138_qs)
+ );
+
+ // F[p_139]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_139 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[139].de),
+ .d (hw2reg.ip[139].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_139_qs)
+ );
+
+ // F[p_140]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_140 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[140].de),
+ .d (hw2reg.ip[140].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_140_qs)
+ );
+
+ // F[p_141]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_141 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[141].de),
+ .d (hw2reg.ip[141].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_141_qs)
+ );
+
+ // F[p_142]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_142 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[142].de),
+ .d (hw2reg.ip[142].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_142_qs)
+ );
+
+ // F[p_143]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_143 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[143].de),
+ .d (hw2reg.ip[143].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_143_qs)
+ );
+
+ // F[p_144]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_144 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[144].de),
+ .d (hw2reg.ip[144].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_144_qs)
+ );
+
+ // F[p_145]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_145 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[145].de),
+ .d (hw2reg.ip[145].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_145_qs)
+ );
+
+ // F[p_146]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_146 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[146].de),
+ .d (hw2reg.ip[146].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_146_qs)
+ );
+
+ // F[p_147]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_147 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[147].de),
+ .d (hw2reg.ip[147].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_147_qs)
+ );
+
+ // F[p_148]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_148 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[148].de),
+ .d (hw2reg.ip[148].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_148_qs)
+ );
+
+ // F[p_149]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_149 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[149].de),
+ .d (hw2reg.ip[149].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_149_qs)
+ );
+
+ // F[p_150]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_150 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[150].de),
+ .d (hw2reg.ip[150].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_150_qs)
+ );
+
+ // F[p_151]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_151 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[151].de),
+ .d (hw2reg.ip[151].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_151_qs)
+ );
+
+ // F[p_152]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_152 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[152].de),
+ .d (hw2reg.ip[152].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_152_qs)
+ );
+
+ // F[p_153]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_153 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[153].de),
+ .d (hw2reg.ip[153].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_153_qs)
+ );
+
+ // F[p_154]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_154 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[154].de),
+ .d (hw2reg.ip[154].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_154_qs)
+ );
+
+ // F[p_155]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_155 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[155].de),
+ .d (hw2reg.ip[155].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_155_qs)
+ );
+
+ // F[p_156]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_156 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[156].de),
+ .d (hw2reg.ip[156].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_156_qs)
+ );
+
+ // F[p_157]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_157 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[157].de),
+ .d (hw2reg.ip[157].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_157_qs)
+ );
+
+ // F[p_158]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_158 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[158].de),
+ .d (hw2reg.ip[158].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_158_qs)
+ );
+
+ // F[p_159]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_4_p_159 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[159].de),
+ .d (hw2reg.ip[159].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_4_p_159_qs)
+ );
+
+
+ // Subregister 5 of Multireg ip
+ // R[ip_5]: V(False)
+ // F[p_160]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_160 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[160].de),
+ .d (hw2reg.ip[160].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_160_qs)
+ );
+
+ // F[p_161]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_161 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[161].de),
+ .d (hw2reg.ip[161].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_161_qs)
+ );
+
+ // F[p_162]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_162 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[162].de),
+ .d (hw2reg.ip[162].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_162_qs)
+ );
+
+ // F[p_163]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_163 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[163].de),
+ .d (hw2reg.ip[163].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_163_qs)
+ );
+
+ // F[p_164]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_164 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[164].de),
+ .d (hw2reg.ip[164].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_164_qs)
+ );
+
+ // F[p_165]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_165 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[165].de),
+ .d (hw2reg.ip[165].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_165_qs)
+ );
+
+ // F[p_166]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_166 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[166].de),
+ .d (hw2reg.ip[166].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_166_qs)
+ );
+
+ // F[p_167]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_167 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[167].de),
+ .d (hw2reg.ip[167].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_167_qs)
+ );
+
+ // F[p_168]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_168 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[168].de),
+ .d (hw2reg.ip[168].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_168_qs)
+ );
+
+ // F[p_169]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_169 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[169].de),
+ .d (hw2reg.ip[169].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_169_qs)
+ );
+
+ // F[p_170]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_170 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[170].de),
+ .d (hw2reg.ip[170].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_170_qs)
+ );
+
+ // F[p_171]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_171 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[171].de),
+ .d (hw2reg.ip[171].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_171_qs)
+ );
+
+ // F[p_172]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_172 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[172].de),
+ .d (hw2reg.ip[172].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_172_qs)
+ );
+
+ // F[p_173]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_173 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[173].de),
+ .d (hw2reg.ip[173].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_173_qs)
+ );
+
+ // F[p_174]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_174 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[174].de),
+ .d (hw2reg.ip[174].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_174_qs)
+ );
+
+ // F[p_175]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_175 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[175].de),
+ .d (hw2reg.ip[175].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_175_qs)
+ );
+
+ // F[p_176]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_176 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[176].de),
+ .d (hw2reg.ip[176].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_176_qs)
+ );
+
+ // F[p_177]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_177 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[177].de),
+ .d (hw2reg.ip[177].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_177_qs)
+ );
+
+ // F[p_178]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_178 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[178].de),
+ .d (hw2reg.ip[178].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_178_qs)
+ );
+
+ // F[p_179]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_179 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[179].de),
+ .d (hw2reg.ip[179].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_179_qs)
+ );
+
+ // F[p_180]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_180 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[180].de),
+ .d (hw2reg.ip[180].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_180_qs)
+ );
+
+ // F[p_181]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_181 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[181].de),
+ .d (hw2reg.ip[181].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_181_qs)
+ );
+
+ // F[p_182]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_182 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[182].de),
+ .d (hw2reg.ip[182].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_182_qs)
+ );
+
+ // F[p_183]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_183 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[183].de),
+ .d (hw2reg.ip[183].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_183_qs)
+ );
+
+ // F[p_184]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_184 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[184].de),
+ .d (hw2reg.ip[184].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_184_qs)
+ );
+
+ // F[p_185]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_185 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[185].de),
+ .d (hw2reg.ip[185].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_185_qs)
+ );
+
+ // F[p_186]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_186 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[186].de),
+ .d (hw2reg.ip[186].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_186_qs)
+ );
+
+ // F[p_187]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_187 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[187].de),
+ .d (hw2reg.ip[187].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_187_qs)
+ );
+
+ // F[p_188]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_188 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[188].de),
+ .d (hw2reg.ip[188].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_188_qs)
+ );
+
+ // F[p_189]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_5_p_189 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[189].de),
+ .d (hw2reg.ip[189].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_5_p_189_qs)
+ );
+
+
+ // Subregister 0 of Multireg ie0
+ // R[ie0_0]: V(False)
+ // F[e_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_0_qs)
+ );
+
+ // F[e_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_1_qs)
+ );
+
+ // F[e_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_2_qs)
+ );
+
+ // F[e_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_3_qs)
+ );
+
+ // F[e_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_4_qs)
+ );
+
+ // F[e_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_5_qs)
+ );
+
+ // F[e_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_6_qs)
+ );
+
+ // F[e_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_7_qs)
+ );
+
+ // F[e_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_8_qs)
+ );
+
+ // F[e_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_9_qs)
+ );
+
+ // F[e_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_10_qs)
+ );
+
+ // F[e_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_11_qs)
+ );
+
+ // F[e_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_12_qs)
+ );
+
+ // F[e_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_13_qs)
+ );
+
+ // F[e_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_14_qs)
+ );
+
+ // F[e_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_15_qs)
+ );
+
+ // F[e_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_16_qs)
+ );
+
+ // F[e_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_17_qs)
+ );
+
+ // F[e_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_18_qs)
+ );
+
+ // F[e_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_19_qs)
+ );
+
+ // F[e_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_20_qs)
+ );
+
+ // F[e_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_21_qs)
+ );
+
+ // F[e_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_22_qs)
+ );
+
+ // F[e_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_23_qs)
+ );
+
+ // F[e_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_24_qs)
+ );
+
+ // F[e_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_25_qs)
+ );
+
+ // F[e_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_26_qs)
+ );
+
+ // F[e_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_27_qs)
+ );
+
+ // F[e_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_28_qs)
+ );
+
+ // F[e_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_29_qs)
+ );
+
+ // F[e_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_30_qs)
+ );
+
+ // F[e_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg ie0
+ // R[ie0_1]: V(False)
+ // F[e_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_32_qs)
+ );
+
+ // F[e_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_33_qs)
+ );
+
+ // F[e_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_34_qs)
+ );
+
+ // F[e_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_35_qs)
+ );
+
+ // F[e_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_36_qs)
+ );
+
+ // F[e_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_37_qs)
+ );
+
+ // F[e_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_38_qs)
+ );
+
+ // F[e_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_39_qs)
+ );
+
+ // F[e_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_40_qs)
+ );
+
+ // F[e_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_41_qs)
+ );
+
+ // F[e_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_42_qs)
+ );
+
+ // F[e_43]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_43_qs)
+ );
+
+ // F[e_44]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_44_qs)
+ );
+
+ // F[e_45]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_45_qs)
+ );
+
+ // F[e_46]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_46_qs)
+ );
+
+ // F[e_47]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_47_qs)
+ );
+
+ // F[e_48]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_48_qs)
+ );
+
+ // F[e_49]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_49_qs)
+ );
+
+ // F[e_50]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_50_qs)
+ );
+
+ // F[e_51]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_51_qs)
+ );
+
+ // F[e_52]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_52_qs)
+ );
+
+ // F[e_53]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_53_qs)
+ );
+
+ // F[e_54]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_54_qs)
+ );
+
+ // F[e_55]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_55_qs)
+ );
+
+ // F[e_56]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_56_qs)
+ );
+
+ // F[e_57]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_57_qs)
+ );
+
+ // F[e_58]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_58_qs)
+ );
+
+ // F[e_59]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_59_qs)
+ );
+
+ // F[e_60]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_60_qs)
+ );
+
+ // F[e_61]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_61_qs)
+ );
+
+ // F[e_62]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_62_qs)
+ );
+
+ // F[e_63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_63_qs)
+ );
+
+
+ // Subregister 2 of Multireg ie0
+ // R[ie0_2]: V(False)
+ // F[e_64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_64_qs)
+ );
+
+ // F[e_65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_65_qs)
+ );
+
+ // F[e_66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_66_qs)
+ );
+
+ // F[e_67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_67_qs)
+ );
+
+ // F[e_68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_68_qs)
+ );
+
+ // F[e_69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_69_qs)
+ );
+
+ // F[e_70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_70_qs)
+ );
+
+ // F[e_71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_71_qs)
+ );
+
+ // F[e_72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_72_qs)
+ );
+
+ // F[e_73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_73_qs)
+ );
+
+ // F[e_74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_74_qs)
+ );
+
+ // F[e_75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[75].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_75_qs)
+ );
+
+ // F[e_76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_76 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[76].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_76_qs)
+ );
+
+ // F[e_77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_77 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[77].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_77_qs)
+ );
+
+ // F[e_78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_78 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[78].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_78_qs)
+ );
+
+ // F[e_79]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_79 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_79_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[79].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_79_qs)
+ );
+
+ // F[e_80]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_80 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_80_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[80].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_80_qs)
+ );
+
+ // F[e_81]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_81 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_81_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[81].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_81_qs)
+ );
+
+ // F[e_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_82 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[82].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_82_qs)
+ );
+
+ // F[e_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_83 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[83].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_83_qs)
+ );
+
+ // F[e_84]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_84 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_84_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[84].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_84_qs)
+ );
+
+ // F[e_85]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_85 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_85_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[85].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_85_qs)
+ );
+
+ // F[e_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_86 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[86].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_86_qs)
+ );
+
+ // F[e_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_87 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[87].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_87_qs)
+ );
+
+ // F[e_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_88 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[88].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_88_qs)
+ );
+
+ // F[e_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_89 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[89].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_89_qs)
+ );
+
+ // F[e_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_90 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[90].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_90_qs)
+ );
+
+ // F[e_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_91 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[91].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_91_qs)
+ );
+
+ // F[e_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_92 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[92].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_92_qs)
+ );
+
+ // F[e_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_93 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[93].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_93_qs)
+ );
+
+ // F[e_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_94 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[94].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_94_qs)
+ );
+
+ // F[e_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_95 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_2_we),
+ .wd (ie0_2_e_95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[95].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_2_e_95_qs)
+ );
+
+
+ // Subregister 3 of Multireg ie0
+ // R[ie0_3]: V(False)
+ // F[e_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_96 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[96].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_96_qs)
+ );
+
+ // F[e_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_97 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[97].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_97_qs)
+ );
+
+ // F[e_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_98 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[98].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_98_qs)
+ );
+
+ // F[e_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_99 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[99].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_99_qs)
+ );
+
+ // F[e_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_100 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[100].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_100_qs)
+ );
+
+ // F[e_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_101 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[101].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_101_qs)
+ );
+
+ // F[e_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_102 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[102].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_102_qs)
+ );
+
+ // F[e_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_103 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[103].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_103_qs)
+ );
+
+ // F[e_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_104 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[104].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_104_qs)
+ );
+
+ // F[e_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_105 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[105].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_105_qs)
+ );
+
+ // F[e_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_106 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[106].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_106_qs)
+ );
+
+ // F[e_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_107 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[107].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_107_qs)
+ );
+
+ // F[e_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_108 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[108].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_108_qs)
+ );
+
+ // F[e_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_109 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[109].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_109_qs)
+ );
+
+ // F[e_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_110 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[110].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_110_qs)
+ );
+
+ // F[e_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_111 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[111].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_111_qs)
+ );
+
+ // F[e_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_112 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[112].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_112_qs)
+ );
+
+ // F[e_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_113 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[113].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_113_qs)
+ );
+
+ // F[e_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_114 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[114].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_114_qs)
+ );
+
+ // F[e_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_115 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[115].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_115_qs)
+ );
+
+ // F[e_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_116 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[116].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_116_qs)
+ );
+
+ // F[e_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_117 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[117].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_117_qs)
+ );
+
+ // F[e_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_118 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[118].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_118_qs)
+ );
+
+ // F[e_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_119 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[119].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_119_qs)
+ );
+
+ // F[e_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_120 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[120].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_120_qs)
+ );
+
+ // F[e_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_121 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[121].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_121_qs)
+ );
+
+ // F[e_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_122 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[122].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_122_qs)
+ );
+
+ // F[e_123]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_123 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_123_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[123].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_123_qs)
+ );
+
+ // F[e_124]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_124 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_124_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[124].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_124_qs)
+ );
+
+ // F[e_125]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_125 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_125_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[125].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_125_qs)
+ );
+
+ // F[e_126]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_126 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_126_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[126].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_126_qs)
+ );
+
+ // F[e_127]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_3_e_127 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_3_we),
+ .wd (ie0_3_e_127_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[127].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_3_e_127_qs)
+ );
+
+
+ // Subregister 4 of Multireg ie0
+ // R[ie0_4]: V(False)
+ // F[e_128]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_128 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_128_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[128].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_128_qs)
+ );
+
+ // F[e_129]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_129 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_129_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[129].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_129_qs)
+ );
+
+ // F[e_130]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_130 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_130_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[130].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_130_qs)
+ );
+
+ // F[e_131]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_131 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_131_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[131].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_131_qs)
+ );
+
+ // F[e_132]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_132 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_132_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[132].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_132_qs)
+ );
+
+ // F[e_133]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_133 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_133_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[133].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_133_qs)
+ );
+
+ // F[e_134]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_134 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_134_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[134].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_134_qs)
+ );
+
+ // F[e_135]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_135 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_135_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[135].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_135_qs)
+ );
+
+ // F[e_136]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_136 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_136_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[136].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_136_qs)
+ );
+
+ // F[e_137]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_137 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_137_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[137].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_137_qs)
+ );
+
+ // F[e_138]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_138 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_138_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[138].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_138_qs)
+ );
+
+ // F[e_139]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_139 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_139_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[139].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_139_qs)
+ );
+
+ // F[e_140]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_140 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_140_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[140].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_140_qs)
+ );
+
+ // F[e_141]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_141 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_141_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[141].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_141_qs)
+ );
+
+ // F[e_142]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_142 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_142_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[142].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_142_qs)
+ );
+
+ // F[e_143]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_143 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_143_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[143].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_143_qs)
+ );
+
+ // F[e_144]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_144 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_144_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[144].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_144_qs)
+ );
+
+ // F[e_145]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_145 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_145_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[145].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_145_qs)
+ );
+
+ // F[e_146]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_146 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_146_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[146].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_146_qs)
+ );
+
+ // F[e_147]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_147 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_147_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[147].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_147_qs)
+ );
+
+ // F[e_148]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_148 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_148_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[148].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_148_qs)
+ );
+
+ // F[e_149]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_149 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_149_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[149].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_149_qs)
+ );
+
+ // F[e_150]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_150 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_150_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[150].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_150_qs)
+ );
+
+ // F[e_151]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_151 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_151_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[151].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_151_qs)
+ );
+
+ // F[e_152]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_152 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_152_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[152].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_152_qs)
+ );
+
+ // F[e_153]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_153 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_153_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[153].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_153_qs)
+ );
+
+ // F[e_154]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_154 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_154_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[154].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_154_qs)
+ );
+
+ // F[e_155]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_155 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_155_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[155].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_155_qs)
+ );
+
+ // F[e_156]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_156 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_156_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[156].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_156_qs)
+ );
+
+ // F[e_157]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_157 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_157_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[157].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_157_qs)
+ );
+
+ // F[e_158]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_158 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_158_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[158].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_158_qs)
+ );
+
+ // F[e_159]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_4_e_159 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_4_we),
+ .wd (ie0_4_e_159_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[159].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_4_e_159_qs)
+ );
+
+
+ // Subregister 5 of Multireg ie0
+ // R[ie0_5]: V(False)
+ // F[e_160]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_160 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_160_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[160].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_160_qs)
+ );
+
+ // F[e_161]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_161 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_161_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[161].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_161_qs)
+ );
+
+ // F[e_162]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_162 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_162_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[162].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_162_qs)
+ );
+
+ // F[e_163]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_163 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_163_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[163].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_163_qs)
+ );
+
+ // F[e_164]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_164 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_164_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[164].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_164_qs)
+ );
+
+ // F[e_165]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_165 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_165_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[165].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_165_qs)
+ );
+
+ // F[e_166]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_166 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_166_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[166].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_166_qs)
+ );
+
+ // F[e_167]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_167 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_167_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[167].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_167_qs)
+ );
+
+ // F[e_168]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_168 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_168_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[168].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_168_qs)
+ );
+
+ // F[e_169]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_169 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_169_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[169].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_169_qs)
+ );
+
+ // F[e_170]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_170 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_170_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[170].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_170_qs)
+ );
+
+ // F[e_171]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_171 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_171_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[171].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_171_qs)
+ );
+
+ // F[e_172]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_172 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_172_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[172].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_172_qs)
+ );
+
+ // F[e_173]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_173 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_173_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[173].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_173_qs)
+ );
+
+ // F[e_174]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_174 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_174_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[174].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_174_qs)
+ );
+
+ // F[e_175]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_175 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_175_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[175].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_175_qs)
+ );
+
+ // F[e_176]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_176 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_176_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[176].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_176_qs)
+ );
+
+ // F[e_177]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_177 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_177_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[177].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_177_qs)
+ );
+
+ // F[e_178]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_178 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_178_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[178].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_178_qs)
+ );
+
+ // F[e_179]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_179 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_179_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[179].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_179_qs)
+ );
+
+ // F[e_180]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_180 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_180_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[180].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_180_qs)
+ );
+
+ // F[e_181]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_181 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_181_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[181].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_181_qs)
+ );
+
+ // F[e_182]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_182 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_182_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[182].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_182_qs)
+ );
+
+ // F[e_183]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_183 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_183_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[183].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_183_qs)
+ );
+
+ // F[e_184]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_184 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_184_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[184].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_184_qs)
+ );
+
+ // F[e_185]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_185 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_185_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[185].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_185_qs)
+ );
+
+ // F[e_186]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_186 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_186_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[186].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_186_qs)
+ );
+
+ // F[e_187]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_187 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_187_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[187].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_187_qs)
+ );
+
+ // F[e_188]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_188 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_188_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[188].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_188_qs)
+ );
+
+ // F[e_189]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_5_e_189 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_5_we),
+ .wd (ie0_5_e_189_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[189].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_5_e_189_qs)
+ );
+
+
+ // Subregister 0 of Multireg ie1
+ // R[ie1_0]: V(False)
+ // F[e_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_0_qs)
+ );
+
+ // F[e_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_1_qs)
+ );
+
+ // F[e_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_2_qs)
+ );
+
+ // F[e_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_3_qs)
+ );
+
+ // F[e_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_4_qs)
+ );
+
+ // F[e_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_5_qs)
+ );
+
+ // F[e_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_6_qs)
+ );
+
+ // F[e_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_7_qs)
+ );
+
+ // F[e_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_8_qs)
+ );
+
+ // F[e_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_9_qs)
+ );
+
+ // F[e_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_10_qs)
+ );
+
+ // F[e_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_11_qs)
+ );
+
+ // F[e_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_12_qs)
+ );
+
+ // F[e_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_13_qs)
+ );
+
+ // F[e_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_14_qs)
+ );
+
+ // F[e_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_15_qs)
+ );
+
+ // F[e_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_16_qs)
+ );
+
+ // F[e_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_17_qs)
+ );
+
+ // F[e_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_18_qs)
+ );
+
+ // F[e_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_19_qs)
+ );
+
+ // F[e_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_20_qs)
+ );
+
+ // F[e_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_21_qs)
+ );
+
+ // F[e_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_22_qs)
+ );
+
+ // F[e_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_23_qs)
+ );
+
+ // F[e_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_24_qs)
+ );
+
+ // F[e_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_25_qs)
+ );
+
+ // F[e_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_26_qs)
+ );
+
+ // F[e_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_27_qs)
+ );
+
+ // F[e_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_28_qs)
+ );
+
+ // F[e_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_29_qs)
+ );
+
+ // F[e_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_30_qs)
+ );
+
+ // F[e_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_0_e_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_0_we),
+ .wd (ie1_0_e_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_0_e_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg ie1
+ // R[ie1_1]: V(False)
+ // F[e_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_32_qs)
+ );
+
+ // F[e_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_33_qs)
+ );
+
+ // F[e_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_34_qs)
+ );
+
+ // F[e_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_35_qs)
+ );
+
+ // F[e_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_36_qs)
+ );
+
+ // F[e_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_37_qs)
+ );
+
+ // F[e_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_38_qs)
+ );
+
+ // F[e_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_39_qs)
+ );
+
+ // F[e_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_40_qs)
+ );
+
+ // F[e_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_41_qs)
+ );
+
+ // F[e_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_42_qs)
+ );
+
+ // F[e_43]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[43].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_43_qs)
+ );
+
+ // F[e_44]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_44 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_44_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[44].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_44_qs)
+ );
+
+ // F[e_45]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_45 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_45_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[45].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_45_qs)
+ );
+
+ // F[e_46]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_46 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_46_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[46].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_46_qs)
+ );
+
+ // F[e_47]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_47 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_47_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[47].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_47_qs)
+ );
+
+ // F[e_48]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_48 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_48_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[48].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_48_qs)
+ );
+
+ // F[e_49]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_49 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_49_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[49].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_49_qs)
+ );
+
+ // F[e_50]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_50 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_50_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[50].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_50_qs)
+ );
+
+ // F[e_51]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_51 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_51_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[51].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_51_qs)
+ );
+
+ // F[e_52]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_52 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_52_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[52].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_52_qs)
+ );
+
+ // F[e_53]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_53 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_53_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[53].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_53_qs)
+ );
+
+ // F[e_54]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_54 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_54_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[54].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_54_qs)
+ );
+
+ // F[e_55]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_55 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_55_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[55].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_55_qs)
+ );
+
+ // F[e_56]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_56 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_56_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[56].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_56_qs)
+ );
+
+ // F[e_57]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_57 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_57_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[57].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_57_qs)
+ );
+
+ // F[e_58]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[58].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_58_qs)
+ );
+
+ // F[e_59]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_59 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_59_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[59].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_59_qs)
+ );
+
+ // F[e_60]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_60 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_60_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[60].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_60_qs)
+ );
+
+ // F[e_61]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_61 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_61_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[61].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_61_qs)
+ );
+
+ // F[e_62]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_62 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_62_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[62].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_62_qs)
+ );
+
+ // F[e_63]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_1_e_63 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_1_we),
+ .wd (ie1_1_e_63_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[63].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_1_e_63_qs)
+ );
+
+
+ // Subregister 2 of Multireg ie1
+ // R[ie1_2]: V(False)
+ // F[e_64]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_64 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_64_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[64].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_64_qs)
+ );
+
+ // F[e_65]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_65 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_65_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[65].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_65_qs)
+ );
+
+ // F[e_66]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_66 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_66_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[66].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_66_qs)
+ );
+
+ // F[e_67]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_67 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_67_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[67].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_67_qs)
+ );
+
+ // F[e_68]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_68 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_68_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[68].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_68_qs)
+ );
+
+ // F[e_69]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_69 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_69_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[69].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_69_qs)
+ );
+
+ // F[e_70]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_70 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_70_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[70].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_70_qs)
+ );
+
+ // F[e_71]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_71 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_71_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[71].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_71_qs)
+ );
+
+ // F[e_72]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_72 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_72_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[72].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_72_qs)
+ );
+
+ // F[e_73]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_73 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_73_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[73].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_73_qs)
+ );
+
+ // F[e_74]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_74 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_74_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[74].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_74_qs)
+ );
+
+ // F[e_75]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_75 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_75_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[75].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_75_qs)
+ );
+
+ // F[e_76]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_76 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_76_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[76].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_76_qs)
+ );
+
+ // F[e_77]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_77 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_77_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[77].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_77_qs)
+ );
+
+ // F[e_78]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_78 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_78_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[78].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_78_qs)
+ );
+
+ // F[e_79]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_79 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_79_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[79].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_79_qs)
+ );
+
+ // F[e_80]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_80 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_80_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[80].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_80_qs)
+ );
+
+ // F[e_81]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_81 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_81_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[81].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_81_qs)
+ );
+
+ // F[e_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_82 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[82].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_82_qs)
+ );
+
+ // F[e_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_83 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[83].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_83_qs)
+ );
+
+ // F[e_84]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_84 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_84_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[84].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_84_qs)
+ );
+
+ // F[e_85]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_85 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_85_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[85].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_85_qs)
+ );
+
+ // F[e_86]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_86 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_86_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[86].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_86_qs)
+ );
+
+ // F[e_87]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_87 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_87_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[87].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_87_qs)
+ );
+
+ // F[e_88]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_88 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_88_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[88].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_88_qs)
+ );
+
+ // F[e_89]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_89 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_89_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[89].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_89_qs)
+ );
+
+ // F[e_90]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_90 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_90_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[90].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_90_qs)
+ );
+
+ // F[e_91]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_91 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_91_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[91].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_91_qs)
+ );
+
+ // F[e_92]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_92 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_92_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[92].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_92_qs)
+ );
+
+ // F[e_93]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_93 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_93_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[93].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_93_qs)
+ );
+
+ // F[e_94]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_94 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_94_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[94].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_94_qs)
+ );
+
+ // F[e_95]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_2_e_95 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_2_we),
+ .wd (ie1_2_e_95_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[95].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_2_e_95_qs)
+ );
+
+
+ // Subregister 3 of Multireg ie1
+ // R[ie1_3]: V(False)
+ // F[e_96]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_96 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_96_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[96].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_96_qs)
+ );
+
+ // F[e_97]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_97 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_97_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[97].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_97_qs)
+ );
+
+ // F[e_98]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_98 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_98_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[98].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_98_qs)
+ );
+
+ // F[e_99]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_99 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_99_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[99].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_99_qs)
+ );
+
+ // F[e_100]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_100 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_100_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[100].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_100_qs)
+ );
+
+ // F[e_101]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_101 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_101_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[101].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_101_qs)
+ );
+
+ // F[e_102]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_102 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_102_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[102].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_102_qs)
+ );
+
+ // F[e_103]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_103 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_103_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[103].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_103_qs)
+ );
+
+ // F[e_104]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_104 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_104_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[104].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_104_qs)
+ );
+
+ // F[e_105]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_105 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_105_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[105].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_105_qs)
+ );
+
+ // F[e_106]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_106 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_106_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[106].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_106_qs)
+ );
+
+ // F[e_107]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_107 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_107_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[107].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_107_qs)
+ );
+
+ // F[e_108]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_108 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_108_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[108].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_108_qs)
+ );
+
+ // F[e_109]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_109 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_109_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[109].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_109_qs)
+ );
+
+ // F[e_110]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_110 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_110_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[110].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_110_qs)
+ );
+
+ // F[e_111]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_111 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_111_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[111].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_111_qs)
+ );
+
+ // F[e_112]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_112 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_112_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[112].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_112_qs)
+ );
+
+ // F[e_113]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_113 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_113_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[113].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_113_qs)
+ );
+
+ // F[e_114]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_114 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_114_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[114].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_114_qs)
+ );
+
+ // F[e_115]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_115 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_115_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[115].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_115_qs)
+ );
+
+ // F[e_116]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_116 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_116_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[116].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_116_qs)
+ );
+
+ // F[e_117]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_117 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_117_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[117].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_117_qs)
+ );
+
+ // F[e_118]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_118 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_118_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[118].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_118_qs)
+ );
+
+ // F[e_119]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_119 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_119_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[119].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_119_qs)
+ );
+
+ // F[e_120]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_120 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_120_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[120].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_120_qs)
+ );
+
+ // F[e_121]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_121 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_121_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[121].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_121_qs)
+ );
+
+ // F[e_122]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_122 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_122_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[122].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_122_qs)
+ );
+
+ // F[e_123]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_123 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_123_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[123].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_123_qs)
+ );
+
+ // F[e_124]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_124 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_124_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[124].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_124_qs)
+ );
+
+ // F[e_125]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_125 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_125_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[125].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_125_qs)
+ );
+
+ // F[e_126]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_126 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_126_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[126].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_126_qs)
+ );
+
+ // F[e_127]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_3_e_127 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_3_we),
+ .wd (ie1_3_e_127_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[127].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_3_e_127_qs)
+ );
+
+
+ // Subregister 4 of Multireg ie1
+ // R[ie1_4]: V(False)
+ // F[e_128]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_128 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_128_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[128].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_128_qs)
+ );
+
+ // F[e_129]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_129 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_129_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[129].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_129_qs)
+ );
+
+ // F[e_130]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_130 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_130_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[130].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_130_qs)
+ );
+
+ // F[e_131]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_131 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_131_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[131].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_131_qs)
+ );
+
+ // F[e_132]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_132 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_132_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[132].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_132_qs)
+ );
+
+ // F[e_133]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_133 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_133_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[133].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_133_qs)
+ );
+
+ // F[e_134]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_134 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_134_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[134].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_134_qs)
+ );
+
+ // F[e_135]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_135 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_135_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[135].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_135_qs)
+ );
+
+ // F[e_136]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_136 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_136_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[136].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_136_qs)
+ );
+
+ // F[e_137]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_137 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_137_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[137].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_137_qs)
+ );
+
+ // F[e_138]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_138 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_138_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[138].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_138_qs)
+ );
+
+ // F[e_139]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_139 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_139_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[139].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_139_qs)
+ );
+
+ // F[e_140]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_140 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_140_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[140].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_140_qs)
+ );
+
+ // F[e_141]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_141 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_141_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[141].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_141_qs)
+ );
+
+ // F[e_142]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_142 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_142_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[142].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_142_qs)
+ );
+
+ // F[e_143]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_143 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_143_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[143].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_143_qs)
+ );
+
+ // F[e_144]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_144 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_144_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[144].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_144_qs)
+ );
+
+ // F[e_145]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_145 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_145_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[145].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_145_qs)
+ );
+
+ // F[e_146]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_146 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_146_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[146].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_146_qs)
+ );
+
+ // F[e_147]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_147 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_147_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[147].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_147_qs)
+ );
+
+ // F[e_148]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_148 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_148_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[148].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_148_qs)
+ );
+
+ // F[e_149]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_149 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_149_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[149].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_149_qs)
+ );
+
+ // F[e_150]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_150 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_150_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[150].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_150_qs)
+ );
+
+ // F[e_151]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_151 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_151_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[151].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_151_qs)
+ );
+
+ // F[e_152]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_152 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_152_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[152].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_152_qs)
+ );
+
+ // F[e_153]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_153 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_153_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[153].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_153_qs)
+ );
+
+ // F[e_154]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_154 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_154_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[154].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_154_qs)
+ );
+
+ // F[e_155]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_155 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_155_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[155].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_155_qs)
+ );
+
+ // F[e_156]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_156 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_156_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[156].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_156_qs)
+ );
+
+ // F[e_157]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_157 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_157_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[157].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_157_qs)
+ );
+
+ // F[e_158]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_158 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_158_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[158].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_158_qs)
+ );
+
+ // F[e_159]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_4_e_159 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_4_we),
+ .wd (ie1_4_e_159_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[159].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_4_e_159_qs)
+ );
+
+
+ // Subregister 5 of Multireg ie1
+ // R[ie1_5]: V(False)
+ // F[e_160]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_160 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_160_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[160].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_160_qs)
+ );
+
+ // F[e_161]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_161 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_161_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[161].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_161_qs)
+ );
+
+ // F[e_162]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_162 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_162_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[162].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_162_qs)
+ );
+
+ // F[e_163]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_163 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_163_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[163].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_163_qs)
+ );
+
+ // F[e_164]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_164 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_164_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[164].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_164_qs)
+ );
+
+ // F[e_165]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_165 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_165_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[165].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_165_qs)
+ );
+
+ // F[e_166]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_166 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_166_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[166].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_166_qs)
+ );
+
+ // F[e_167]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_167 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_167_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[167].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_167_qs)
+ );
+
+ // F[e_168]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_168 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_168_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[168].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_168_qs)
+ );
+
+ // F[e_169]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_169 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_169_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[169].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_169_qs)
+ );
+
+ // F[e_170]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_170 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_170_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[170].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_170_qs)
+ );
+
+ // F[e_171]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_171 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_171_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[171].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_171_qs)
+ );
+
+ // F[e_172]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_172 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_172_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[172].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_172_qs)
+ );
+
+ // F[e_173]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_173 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_173_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[173].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_173_qs)
+ );
+
+ // F[e_174]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_174 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_174_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[174].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_174_qs)
+ );
+
+ // F[e_175]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_175 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_175_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[175].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_175_qs)
+ );
+
+ // F[e_176]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_176 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_176_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[176].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_176_qs)
+ );
+
+ // F[e_177]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_177 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_177_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[177].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_177_qs)
+ );
+
+ // F[e_178]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_178 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_178_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[178].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_178_qs)
+ );
+
+ // F[e_179]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_179 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_179_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[179].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_179_qs)
+ );
+
+ // F[e_180]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_180 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_180_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[180].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_180_qs)
+ );
+
+ // F[e_181]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_181 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_181_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[181].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_181_qs)
+ );
+
+ // F[e_182]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_182 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_182_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[182].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_182_qs)
+ );
+
+ // F[e_183]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_183 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_183_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[183].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_183_qs)
+ );
+
+ // F[e_184]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_184 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_184_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[184].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_184_qs)
+ );
+
+ // F[e_185]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_185 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_185_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[185].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_185_qs)
+ );
+
+ // F[e_186]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_186 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_186_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[186].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_186_qs)
+ );
+
+ // F[e_187]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_187 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_187_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[187].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_187_qs)
+ );
+
+ // F[e_188]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_188 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_188_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[188].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_188_qs)
+ );
+
+ // F[e_189]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie1_5_e_189 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie1_5_we),
+ .wd (ie1_5_e_189_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie1[189].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie1_5_e_189_qs)
+ );
+
+
+ // R[threshold0]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_threshold0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (threshold0_we),
+ .wd (threshold0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.threshold0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (threshold0_qs)
+ );
+
+
+ // R[cc0]: V(True)
+ logic cc0_qe;
+ logic [0:0] cc0_flds_we;
+ assign cc0_qe = &cc0_flds_we;
+ prim_subreg_ext #(
+ .DW (8)
+ ) u_cc0 (
+ .re (cc0_re),
+ .we (cc0_we),
+ .wd (cc0_wd),
+ .d (hw2reg.cc0.d),
+ .qre (reg2hw.cc0.re),
+ .qe (cc0_flds_we[0]),
+ .q (reg2hw.cc0.q),
+ .ds (),
+ .qs (cc0_qs)
+ );
+ assign reg2hw.cc0.qe = cc0_qe;
+
+
+ // R[threshold1]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_threshold1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (threshold1_we),
+ .wd (threshold1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.threshold1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (threshold1_qs)
+ );
+
+
+ // R[cc1]: V(True)
+ logic cc1_qe;
+ logic [0:0] cc1_flds_we;
+ assign cc1_qe = &cc1_flds_we;
+ prim_subreg_ext #(
+ .DW (8)
+ ) u_cc1 (
+ .re (cc1_re),
+ .we (cc1_we),
+ .wd (cc1_wd),
+ .d (hw2reg.cc1.d),
+ .qre (reg2hw.cc1.re),
+ .qe (cc1_flds_we[0]),
+ .q (reg2hw.cc1.q),
+ .ds (),
+ .qs (cc1_qs)
+ );
+ assign reg2hw.cc1.qe = cc1_qe;
+
+
+ // R[msip0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_msip0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (msip0_we),
+ .wd (msip0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.msip0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (msip0_qs)
+ );
+
+
+ // R[msip1]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_msip1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (msip1_we),
+ .wd (msip1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.msip1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (msip1_qs)
+ );
+
+
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [0:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.qe = alert_test_qe;
+
+
+
+ logic [214:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+ addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
+ addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
+ addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
+ addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
+ addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
+ addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
+ addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
+ addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
+ addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
+ addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
+ addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
+ addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
+ addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
+ addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
+ addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
+ addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
+ addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
+ addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
+ addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
+ addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
+ addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
+ addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
+ addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
+ addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
+ addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
+ addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
+ addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
+ addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
+ addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
+ addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
+ addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
+ addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
+ addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
+ addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
+ addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
+ addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
+ addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
+ addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
+ addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
+ addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
+ addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
+ addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
+ addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
+ addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
+ addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
+ addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
+ addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
+ addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
+ addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
+ addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
+ addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
+ addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
+ addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
+ addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
+ addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
+ addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
+ addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
+ addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
+ addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
+ addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
+ addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
+ addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
+ addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
+ addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
+ addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
+ addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
+ addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
+ addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
+ addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
+ addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
+ addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
+ addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
+ addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO81_OFFSET);
+ addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO82_OFFSET);
+ addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO83_OFFSET);
+ addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO84_OFFSET);
+ addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO85_OFFSET);
+ addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO86_OFFSET);
+ addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO87_OFFSET);
+ addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO88_OFFSET);
+ addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO89_OFFSET);
+ addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO90_OFFSET);
+ addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO91_OFFSET);
+ addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO92_OFFSET);
+ addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO93_OFFSET);
+ addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO94_OFFSET);
+ addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO95_OFFSET);
+ addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO96_OFFSET);
+ addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO97_OFFSET);
+ addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO98_OFFSET);
+ addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO99_OFFSET);
+ addr_hit[100] = (reg_addr == RV_PLIC_PRIO100_OFFSET);
+ addr_hit[101] = (reg_addr == RV_PLIC_PRIO101_OFFSET);
+ addr_hit[102] = (reg_addr == RV_PLIC_PRIO102_OFFSET);
+ addr_hit[103] = (reg_addr == RV_PLIC_PRIO103_OFFSET);
+ addr_hit[104] = (reg_addr == RV_PLIC_PRIO104_OFFSET);
+ addr_hit[105] = (reg_addr == RV_PLIC_PRIO105_OFFSET);
+ addr_hit[106] = (reg_addr == RV_PLIC_PRIO106_OFFSET);
+ addr_hit[107] = (reg_addr == RV_PLIC_PRIO107_OFFSET);
+ addr_hit[108] = (reg_addr == RV_PLIC_PRIO108_OFFSET);
+ addr_hit[109] = (reg_addr == RV_PLIC_PRIO109_OFFSET);
+ addr_hit[110] = (reg_addr == RV_PLIC_PRIO110_OFFSET);
+ addr_hit[111] = (reg_addr == RV_PLIC_PRIO111_OFFSET);
+ addr_hit[112] = (reg_addr == RV_PLIC_PRIO112_OFFSET);
+ addr_hit[113] = (reg_addr == RV_PLIC_PRIO113_OFFSET);
+ addr_hit[114] = (reg_addr == RV_PLIC_PRIO114_OFFSET);
+ addr_hit[115] = (reg_addr == RV_PLIC_PRIO115_OFFSET);
+ addr_hit[116] = (reg_addr == RV_PLIC_PRIO116_OFFSET);
+ addr_hit[117] = (reg_addr == RV_PLIC_PRIO117_OFFSET);
+ addr_hit[118] = (reg_addr == RV_PLIC_PRIO118_OFFSET);
+ addr_hit[119] = (reg_addr == RV_PLIC_PRIO119_OFFSET);
+ addr_hit[120] = (reg_addr == RV_PLIC_PRIO120_OFFSET);
+ addr_hit[121] = (reg_addr == RV_PLIC_PRIO121_OFFSET);
+ addr_hit[122] = (reg_addr == RV_PLIC_PRIO122_OFFSET);
+ addr_hit[123] = (reg_addr == RV_PLIC_PRIO123_OFFSET);
+ addr_hit[124] = (reg_addr == RV_PLIC_PRIO124_OFFSET);
+ addr_hit[125] = (reg_addr == RV_PLIC_PRIO125_OFFSET);
+ addr_hit[126] = (reg_addr == RV_PLIC_PRIO126_OFFSET);
+ addr_hit[127] = (reg_addr == RV_PLIC_PRIO127_OFFSET);
+ addr_hit[128] = (reg_addr == RV_PLIC_PRIO128_OFFSET);
+ addr_hit[129] = (reg_addr == RV_PLIC_PRIO129_OFFSET);
+ addr_hit[130] = (reg_addr == RV_PLIC_PRIO130_OFFSET);
+ addr_hit[131] = (reg_addr == RV_PLIC_PRIO131_OFFSET);
+ addr_hit[132] = (reg_addr == RV_PLIC_PRIO132_OFFSET);
+ addr_hit[133] = (reg_addr == RV_PLIC_PRIO133_OFFSET);
+ addr_hit[134] = (reg_addr == RV_PLIC_PRIO134_OFFSET);
+ addr_hit[135] = (reg_addr == RV_PLIC_PRIO135_OFFSET);
+ addr_hit[136] = (reg_addr == RV_PLIC_PRIO136_OFFSET);
+ addr_hit[137] = (reg_addr == RV_PLIC_PRIO137_OFFSET);
+ addr_hit[138] = (reg_addr == RV_PLIC_PRIO138_OFFSET);
+ addr_hit[139] = (reg_addr == RV_PLIC_PRIO139_OFFSET);
+ addr_hit[140] = (reg_addr == RV_PLIC_PRIO140_OFFSET);
+ addr_hit[141] = (reg_addr == RV_PLIC_PRIO141_OFFSET);
+ addr_hit[142] = (reg_addr == RV_PLIC_PRIO142_OFFSET);
+ addr_hit[143] = (reg_addr == RV_PLIC_PRIO143_OFFSET);
+ addr_hit[144] = (reg_addr == RV_PLIC_PRIO144_OFFSET);
+ addr_hit[145] = (reg_addr == RV_PLIC_PRIO145_OFFSET);
+ addr_hit[146] = (reg_addr == RV_PLIC_PRIO146_OFFSET);
+ addr_hit[147] = (reg_addr == RV_PLIC_PRIO147_OFFSET);
+ addr_hit[148] = (reg_addr == RV_PLIC_PRIO148_OFFSET);
+ addr_hit[149] = (reg_addr == RV_PLIC_PRIO149_OFFSET);
+ addr_hit[150] = (reg_addr == RV_PLIC_PRIO150_OFFSET);
+ addr_hit[151] = (reg_addr == RV_PLIC_PRIO151_OFFSET);
+ addr_hit[152] = (reg_addr == RV_PLIC_PRIO152_OFFSET);
+ addr_hit[153] = (reg_addr == RV_PLIC_PRIO153_OFFSET);
+ addr_hit[154] = (reg_addr == RV_PLIC_PRIO154_OFFSET);
+ addr_hit[155] = (reg_addr == RV_PLIC_PRIO155_OFFSET);
+ addr_hit[156] = (reg_addr == RV_PLIC_PRIO156_OFFSET);
+ addr_hit[157] = (reg_addr == RV_PLIC_PRIO157_OFFSET);
+ addr_hit[158] = (reg_addr == RV_PLIC_PRIO158_OFFSET);
+ addr_hit[159] = (reg_addr == RV_PLIC_PRIO159_OFFSET);
+ addr_hit[160] = (reg_addr == RV_PLIC_PRIO160_OFFSET);
+ addr_hit[161] = (reg_addr == RV_PLIC_PRIO161_OFFSET);
+ addr_hit[162] = (reg_addr == RV_PLIC_PRIO162_OFFSET);
+ addr_hit[163] = (reg_addr == RV_PLIC_PRIO163_OFFSET);
+ addr_hit[164] = (reg_addr == RV_PLIC_PRIO164_OFFSET);
+ addr_hit[165] = (reg_addr == RV_PLIC_PRIO165_OFFSET);
+ addr_hit[166] = (reg_addr == RV_PLIC_PRIO166_OFFSET);
+ addr_hit[167] = (reg_addr == RV_PLIC_PRIO167_OFFSET);
+ addr_hit[168] = (reg_addr == RV_PLIC_PRIO168_OFFSET);
+ addr_hit[169] = (reg_addr == RV_PLIC_PRIO169_OFFSET);
+ addr_hit[170] = (reg_addr == RV_PLIC_PRIO170_OFFSET);
+ addr_hit[171] = (reg_addr == RV_PLIC_PRIO171_OFFSET);
+ addr_hit[172] = (reg_addr == RV_PLIC_PRIO172_OFFSET);
+ addr_hit[173] = (reg_addr == RV_PLIC_PRIO173_OFFSET);
+ addr_hit[174] = (reg_addr == RV_PLIC_PRIO174_OFFSET);
+ addr_hit[175] = (reg_addr == RV_PLIC_PRIO175_OFFSET);
+ addr_hit[176] = (reg_addr == RV_PLIC_PRIO176_OFFSET);
+ addr_hit[177] = (reg_addr == RV_PLIC_PRIO177_OFFSET);
+ addr_hit[178] = (reg_addr == RV_PLIC_PRIO178_OFFSET);
+ addr_hit[179] = (reg_addr == RV_PLIC_PRIO179_OFFSET);
+ addr_hit[180] = (reg_addr == RV_PLIC_PRIO180_OFFSET);
+ addr_hit[181] = (reg_addr == RV_PLIC_PRIO181_OFFSET);
+ addr_hit[182] = (reg_addr == RV_PLIC_PRIO182_OFFSET);
+ addr_hit[183] = (reg_addr == RV_PLIC_PRIO183_OFFSET);
+ addr_hit[184] = (reg_addr == RV_PLIC_PRIO184_OFFSET);
+ addr_hit[185] = (reg_addr == RV_PLIC_PRIO185_OFFSET);
+ addr_hit[186] = (reg_addr == RV_PLIC_PRIO186_OFFSET);
+ addr_hit[187] = (reg_addr == RV_PLIC_PRIO187_OFFSET);
+ addr_hit[188] = (reg_addr == RV_PLIC_PRIO188_OFFSET);
+ addr_hit[189] = (reg_addr == RV_PLIC_PRIO189_OFFSET);
+ addr_hit[190] = (reg_addr == RV_PLIC_IP_0_OFFSET);
+ addr_hit[191] = (reg_addr == RV_PLIC_IP_1_OFFSET);
+ addr_hit[192] = (reg_addr == RV_PLIC_IP_2_OFFSET);
+ addr_hit[193] = (reg_addr == RV_PLIC_IP_3_OFFSET);
+ addr_hit[194] = (reg_addr == RV_PLIC_IP_4_OFFSET);
+ addr_hit[195] = (reg_addr == RV_PLIC_IP_5_OFFSET);
+ addr_hit[196] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+ addr_hit[197] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+ addr_hit[198] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
+ addr_hit[199] = (reg_addr == RV_PLIC_IE0_3_OFFSET);
+ addr_hit[200] = (reg_addr == RV_PLIC_IE0_4_OFFSET);
+ addr_hit[201] = (reg_addr == RV_PLIC_IE0_5_OFFSET);
+ addr_hit[202] = (reg_addr == RV_PLIC_IE1_0_OFFSET);
+ addr_hit[203] = (reg_addr == RV_PLIC_IE1_1_OFFSET);
+ addr_hit[204] = (reg_addr == RV_PLIC_IE1_2_OFFSET);
+ addr_hit[205] = (reg_addr == RV_PLIC_IE1_3_OFFSET);
+ addr_hit[206] = (reg_addr == RV_PLIC_IE1_4_OFFSET);
+ addr_hit[207] = (reg_addr == RV_PLIC_IE1_5_OFFSET);
+ addr_hit[208] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[209] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[210] = (reg_addr == RV_PLIC_THRESHOLD1_OFFSET);
+ addr_hit[211] = (reg_addr == RV_PLIC_CC1_OFFSET);
+ addr_hit[212] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[213] = (reg_addr == RV_PLIC_MSIP1_OFFSET);
+ addr_hit[214] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(RV_PLIC_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(RV_PLIC_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(RV_PLIC_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(RV_PLIC_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(RV_PLIC_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(RV_PLIC_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(RV_PLIC_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(RV_PLIC_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(RV_PLIC_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(RV_PLIC_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[ 10] & (|(RV_PLIC_PERMIT[ 10] & ~reg_be))) |
+ (addr_hit[ 11] & (|(RV_PLIC_PERMIT[ 11] & ~reg_be))) |
+ (addr_hit[ 12] & (|(RV_PLIC_PERMIT[ 12] & ~reg_be))) |
+ (addr_hit[ 13] & (|(RV_PLIC_PERMIT[ 13] & ~reg_be))) |
+ (addr_hit[ 14] & (|(RV_PLIC_PERMIT[ 14] & ~reg_be))) |
+ (addr_hit[ 15] & (|(RV_PLIC_PERMIT[ 15] & ~reg_be))) |
+ (addr_hit[ 16] & (|(RV_PLIC_PERMIT[ 16] & ~reg_be))) |
+ (addr_hit[ 17] & (|(RV_PLIC_PERMIT[ 17] & ~reg_be))) |
+ (addr_hit[ 18] & (|(RV_PLIC_PERMIT[ 18] & ~reg_be))) |
+ (addr_hit[ 19] & (|(RV_PLIC_PERMIT[ 19] & ~reg_be))) |
+ (addr_hit[ 20] & (|(RV_PLIC_PERMIT[ 20] & ~reg_be))) |
+ (addr_hit[ 21] & (|(RV_PLIC_PERMIT[ 21] & ~reg_be))) |
+ (addr_hit[ 22] & (|(RV_PLIC_PERMIT[ 22] & ~reg_be))) |
+ (addr_hit[ 23] & (|(RV_PLIC_PERMIT[ 23] & ~reg_be))) |
+ (addr_hit[ 24] & (|(RV_PLIC_PERMIT[ 24] & ~reg_be))) |
+ (addr_hit[ 25] & (|(RV_PLIC_PERMIT[ 25] & ~reg_be))) |
+ (addr_hit[ 26] & (|(RV_PLIC_PERMIT[ 26] & ~reg_be))) |
+ (addr_hit[ 27] & (|(RV_PLIC_PERMIT[ 27] & ~reg_be))) |
+ (addr_hit[ 28] & (|(RV_PLIC_PERMIT[ 28] & ~reg_be))) |
+ (addr_hit[ 29] & (|(RV_PLIC_PERMIT[ 29] & ~reg_be))) |
+ (addr_hit[ 30] & (|(RV_PLIC_PERMIT[ 30] & ~reg_be))) |
+ (addr_hit[ 31] & (|(RV_PLIC_PERMIT[ 31] & ~reg_be))) |
+ (addr_hit[ 32] & (|(RV_PLIC_PERMIT[ 32] & ~reg_be))) |
+ (addr_hit[ 33] & (|(RV_PLIC_PERMIT[ 33] & ~reg_be))) |
+ (addr_hit[ 34] & (|(RV_PLIC_PERMIT[ 34] & ~reg_be))) |
+ (addr_hit[ 35] & (|(RV_PLIC_PERMIT[ 35] & ~reg_be))) |
+ (addr_hit[ 36] & (|(RV_PLIC_PERMIT[ 36] & ~reg_be))) |
+ (addr_hit[ 37] & (|(RV_PLIC_PERMIT[ 37] & ~reg_be))) |
+ (addr_hit[ 38] & (|(RV_PLIC_PERMIT[ 38] & ~reg_be))) |
+ (addr_hit[ 39] & (|(RV_PLIC_PERMIT[ 39] & ~reg_be))) |
+ (addr_hit[ 40] & (|(RV_PLIC_PERMIT[ 40] & ~reg_be))) |
+ (addr_hit[ 41] & (|(RV_PLIC_PERMIT[ 41] & ~reg_be))) |
+ (addr_hit[ 42] & (|(RV_PLIC_PERMIT[ 42] & ~reg_be))) |
+ (addr_hit[ 43] & (|(RV_PLIC_PERMIT[ 43] & ~reg_be))) |
+ (addr_hit[ 44] & (|(RV_PLIC_PERMIT[ 44] & ~reg_be))) |
+ (addr_hit[ 45] & (|(RV_PLIC_PERMIT[ 45] & ~reg_be))) |
+ (addr_hit[ 46] & (|(RV_PLIC_PERMIT[ 46] & ~reg_be))) |
+ (addr_hit[ 47] & (|(RV_PLIC_PERMIT[ 47] & ~reg_be))) |
+ (addr_hit[ 48] & (|(RV_PLIC_PERMIT[ 48] & ~reg_be))) |
+ (addr_hit[ 49] & (|(RV_PLIC_PERMIT[ 49] & ~reg_be))) |
+ (addr_hit[ 50] & (|(RV_PLIC_PERMIT[ 50] & ~reg_be))) |
+ (addr_hit[ 51] & (|(RV_PLIC_PERMIT[ 51] & ~reg_be))) |
+ (addr_hit[ 52] & (|(RV_PLIC_PERMIT[ 52] & ~reg_be))) |
+ (addr_hit[ 53] & (|(RV_PLIC_PERMIT[ 53] & ~reg_be))) |
+ (addr_hit[ 54] & (|(RV_PLIC_PERMIT[ 54] & ~reg_be))) |
+ (addr_hit[ 55] & (|(RV_PLIC_PERMIT[ 55] & ~reg_be))) |
+ (addr_hit[ 56] & (|(RV_PLIC_PERMIT[ 56] & ~reg_be))) |
+ (addr_hit[ 57] & (|(RV_PLIC_PERMIT[ 57] & ~reg_be))) |
+ (addr_hit[ 58] & (|(RV_PLIC_PERMIT[ 58] & ~reg_be))) |
+ (addr_hit[ 59] & (|(RV_PLIC_PERMIT[ 59] & ~reg_be))) |
+ (addr_hit[ 60] & (|(RV_PLIC_PERMIT[ 60] & ~reg_be))) |
+ (addr_hit[ 61] & (|(RV_PLIC_PERMIT[ 61] & ~reg_be))) |
+ (addr_hit[ 62] & (|(RV_PLIC_PERMIT[ 62] & ~reg_be))) |
+ (addr_hit[ 63] & (|(RV_PLIC_PERMIT[ 63] & ~reg_be))) |
+ (addr_hit[ 64] & (|(RV_PLIC_PERMIT[ 64] & ~reg_be))) |
+ (addr_hit[ 65] & (|(RV_PLIC_PERMIT[ 65] & ~reg_be))) |
+ (addr_hit[ 66] & (|(RV_PLIC_PERMIT[ 66] & ~reg_be))) |
+ (addr_hit[ 67] & (|(RV_PLIC_PERMIT[ 67] & ~reg_be))) |
+ (addr_hit[ 68] & (|(RV_PLIC_PERMIT[ 68] & ~reg_be))) |
+ (addr_hit[ 69] & (|(RV_PLIC_PERMIT[ 69] & ~reg_be))) |
+ (addr_hit[ 70] & (|(RV_PLIC_PERMIT[ 70] & ~reg_be))) |
+ (addr_hit[ 71] & (|(RV_PLIC_PERMIT[ 71] & ~reg_be))) |
+ (addr_hit[ 72] & (|(RV_PLIC_PERMIT[ 72] & ~reg_be))) |
+ (addr_hit[ 73] & (|(RV_PLIC_PERMIT[ 73] & ~reg_be))) |
+ (addr_hit[ 74] & (|(RV_PLIC_PERMIT[ 74] & ~reg_be))) |
+ (addr_hit[ 75] & (|(RV_PLIC_PERMIT[ 75] & ~reg_be))) |
+ (addr_hit[ 76] & (|(RV_PLIC_PERMIT[ 76] & ~reg_be))) |
+ (addr_hit[ 77] & (|(RV_PLIC_PERMIT[ 77] & ~reg_be))) |
+ (addr_hit[ 78] & (|(RV_PLIC_PERMIT[ 78] & ~reg_be))) |
+ (addr_hit[ 79] & (|(RV_PLIC_PERMIT[ 79] & ~reg_be))) |
+ (addr_hit[ 80] & (|(RV_PLIC_PERMIT[ 80] & ~reg_be))) |
+ (addr_hit[ 81] & (|(RV_PLIC_PERMIT[ 81] & ~reg_be))) |
+ (addr_hit[ 82] & (|(RV_PLIC_PERMIT[ 82] & ~reg_be))) |
+ (addr_hit[ 83] & (|(RV_PLIC_PERMIT[ 83] & ~reg_be))) |
+ (addr_hit[ 84] & (|(RV_PLIC_PERMIT[ 84] & ~reg_be))) |
+ (addr_hit[ 85] & (|(RV_PLIC_PERMIT[ 85] & ~reg_be))) |
+ (addr_hit[ 86] & (|(RV_PLIC_PERMIT[ 86] & ~reg_be))) |
+ (addr_hit[ 87] & (|(RV_PLIC_PERMIT[ 87] & ~reg_be))) |
+ (addr_hit[ 88] & (|(RV_PLIC_PERMIT[ 88] & ~reg_be))) |
+ (addr_hit[ 89] & (|(RV_PLIC_PERMIT[ 89] & ~reg_be))) |
+ (addr_hit[ 90] & (|(RV_PLIC_PERMIT[ 90] & ~reg_be))) |
+ (addr_hit[ 91] & (|(RV_PLIC_PERMIT[ 91] & ~reg_be))) |
+ (addr_hit[ 92] & (|(RV_PLIC_PERMIT[ 92] & ~reg_be))) |
+ (addr_hit[ 93] & (|(RV_PLIC_PERMIT[ 93] & ~reg_be))) |
+ (addr_hit[ 94] & (|(RV_PLIC_PERMIT[ 94] & ~reg_be))) |
+ (addr_hit[ 95] & (|(RV_PLIC_PERMIT[ 95] & ~reg_be))) |
+ (addr_hit[ 96] & (|(RV_PLIC_PERMIT[ 96] & ~reg_be))) |
+ (addr_hit[ 97] & (|(RV_PLIC_PERMIT[ 97] & ~reg_be))) |
+ (addr_hit[ 98] & (|(RV_PLIC_PERMIT[ 98] & ~reg_be))) |
+ (addr_hit[ 99] & (|(RV_PLIC_PERMIT[ 99] & ~reg_be))) |
+ (addr_hit[100] & (|(RV_PLIC_PERMIT[100] & ~reg_be))) |
+ (addr_hit[101] & (|(RV_PLIC_PERMIT[101] & ~reg_be))) |
+ (addr_hit[102] & (|(RV_PLIC_PERMIT[102] & ~reg_be))) |
+ (addr_hit[103] & (|(RV_PLIC_PERMIT[103] & ~reg_be))) |
+ (addr_hit[104] & (|(RV_PLIC_PERMIT[104] & ~reg_be))) |
+ (addr_hit[105] & (|(RV_PLIC_PERMIT[105] & ~reg_be))) |
+ (addr_hit[106] & (|(RV_PLIC_PERMIT[106] & ~reg_be))) |
+ (addr_hit[107] & (|(RV_PLIC_PERMIT[107] & ~reg_be))) |
+ (addr_hit[108] & (|(RV_PLIC_PERMIT[108] & ~reg_be))) |
+ (addr_hit[109] & (|(RV_PLIC_PERMIT[109] & ~reg_be))) |
+ (addr_hit[110] & (|(RV_PLIC_PERMIT[110] & ~reg_be))) |
+ (addr_hit[111] & (|(RV_PLIC_PERMIT[111] & ~reg_be))) |
+ (addr_hit[112] & (|(RV_PLIC_PERMIT[112] & ~reg_be))) |
+ (addr_hit[113] & (|(RV_PLIC_PERMIT[113] & ~reg_be))) |
+ (addr_hit[114] & (|(RV_PLIC_PERMIT[114] & ~reg_be))) |
+ (addr_hit[115] & (|(RV_PLIC_PERMIT[115] & ~reg_be))) |
+ (addr_hit[116] & (|(RV_PLIC_PERMIT[116] & ~reg_be))) |
+ (addr_hit[117] & (|(RV_PLIC_PERMIT[117] & ~reg_be))) |
+ (addr_hit[118] & (|(RV_PLIC_PERMIT[118] & ~reg_be))) |
+ (addr_hit[119] & (|(RV_PLIC_PERMIT[119] & ~reg_be))) |
+ (addr_hit[120] & (|(RV_PLIC_PERMIT[120] & ~reg_be))) |
+ (addr_hit[121] & (|(RV_PLIC_PERMIT[121] & ~reg_be))) |
+ (addr_hit[122] & (|(RV_PLIC_PERMIT[122] & ~reg_be))) |
+ (addr_hit[123] & (|(RV_PLIC_PERMIT[123] & ~reg_be))) |
+ (addr_hit[124] & (|(RV_PLIC_PERMIT[124] & ~reg_be))) |
+ (addr_hit[125] & (|(RV_PLIC_PERMIT[125] & ~reg_be))) |
+ (addr_hit[126] & (|(RV_PLIC_PERMIT[126] & ~reg_be))) |
+ (addr_hit[127] & (|(RV_PLIC_PERMIT[127] & ~reg_be))) |
+ (addr_hit[128] & (|(RV_PLIC_PERMIT[128] & ~reg_be))) |
+ (addr_hit[129] & (|(RV_PLIC_PERMIT[129] & ~reg_be))) |
+ (addr_hit[130] & (|(RV_PLIC_PERMIT[130] & ~reg_be))) |
+ (addr_hit[131] & (|(RV_PLIC_PERMIT[131] & ~reg_be))) |
+ (addr_hit[132] & (|(RV_PLIC_PERMIT[132] & ~reg_be))) |
+ (addr_hit[133] & (|(RV_PLIC_PERMIT[133] & ~reg_be))) |
+ (addr_hit[134] & (|(RV_PLIC_PERMIT[134] & ~reg_be))) |
+ (addr_hit[135] & (|(RV_PLIC_PERMIT[135] & ~reg_be))) |
+ (addr_hit[136] & (|(RV_PLIC_PERMIT[136] & ~reg_be))) |
+ (addr_hit[137] & (|(RV_PLIC_PERMIT[137] & ~reg_be))) |
+ (addr_hit[138] & (|(RV_PLIC_PERMIT[138] & ~reg_be))) |
+ (addr_hit[139] & (|(RV_PLIC_PERMIT[139] & ~reg_be))) |
+ (addr_hit[140] & (|(RV_PLIC_PERMIT[140] & ~reg_be))) |
+ (addr_hit[141] & (|(RV_PLIC_PERMIT[141] & ~reg_be))) |
+ (addr_hit[142] & (|(RV_PLIC_PERMIT[142] & ~reg_be))) |
+ (addr_hit[143] & (|(RV_PLIC_PERMIT[143] & ~reg_be))) |
+ (addr_hit[144] & (|(RV_PLIC_PERMIT[144] & ~reg_be))) |
+ (addr_hit[145] & (|(RV_PLIC_PERMIT[145] & ~reg_be))) |
+ (addr_hit[146] & (|(RV_PLIC_PERMIT[146] & ~reg_be))) |
+ (addr_hit[147] & (|(RV_PLIC_PERMIT[147] & ~reg_be))) |
+ (addr_hit[148] & (|(RV_PLIC_PERMIT[148] & ~reg_be))) |
+ (addr_hit[149] & (|(RV_PLIC_PERMIT[149] & ~reg_be))) |
+ (addr_hit[150] & (|(RV_PLIC_PERMIT[150] & ~reg_be))) |
+ (addr_hit[151] & (|(RV_PLIC_PERMIT[151] & ~reg_be))) |
+ (addr_hit[152] & (|(RV_PLIC_PERMIT[152] & ~reg_be))) |
+ (addr_hit[153] & (|(RV_PLIC_PERMIT[153] & ~reg_be))) |
+ (addr_hit[154] & (|(RV_PLIC_PERMIT[154] & ~reg_be))) |
+ (addr_hit[155] & (|(RV_PLIC_PERMIT[155] & ~reg_be))) |
+ (addr_hit[156] & (|(RV_PLIC_PERMIT[156] & ~reg_be))) |
+ (addr_hit[157] & (|(RV_PLIC_PERMIT[157] & ~reg_be))) |
+ (addr_hit[158] & (|(RV_PLIC_PERMIT[158] & ~reg_be))) |
+ (addr_hit[159] & (|(RV_PLIC_PERMIT[159] & ~reg_be))) |
+ (addr_hit[160] & (|(RV_PLIC_PERMIT[160] & ~reg_be))) |
+ (addr_hit[161] & (|(RV_PLIC_PERMIT[161] & ~reg_be))) |
+ (addr_hit[162] & (|(RV_PLIC_PERMIT[162] & ~reg_be))) |
+ (addr_hit[163] & (|(RV_PLIC_PERMIT[163] & ~reg_be))) |
+ (addr_hit[164] & (|(RV_PLIC_PERMIT[164] & ~reg_be))) |
+ (addr_hit[165] & (|(RV_PLIC_PERMIT[165] & ~reg_be))) |
+ (addr_hit[166] & (|(RV_PLIC_PERMIT[166] & ~reg_be))) |
+ (addr_hit[167] & (|(RV_PLIC_PERMIT[167] & ~reg_be))) |
+ (addr_hit[168] & (|(RV_PLIC_PERMIT[168] & ~reg_be))) |
+ (addr_hit[169] & (|(RV_PLIC_PERMIT[169] & ~reg_be))) |
+ (addr_hit[170] & (|(RV_PLIC_PERMIT[170] & ~reg_be))) |
+ (addr_hit[171] & (|(RV_PLIC_PERMIT[171] & ~reg_be))) |
+ (addr_hit[172] & (|(RV_PLIC_PERMIT[172] & ~reg_be))) |
+ (addr_hit[173] & (|(RV_PLIC_PERMIT[173] & ~reg_be))) |
+ (addr_hit[174] & (|(RV_PLIC_PERMIT[174] & ~reg_be))) |
+ (addr_hit[175] & (|(RV_PLIC_PERMIT[175] & ~reg_be))) |
+ (addr_hit[176] & (|(RV_PLIC_PERMIT[176] & ~reg_be))) |
+ (addr_hit[177] & (|(RV_PLIC_PERMIT[177] & ~reg_be))) |
+ (addr_hit[178] & (|(RV_PLIC_PERMIT[178] & ~reg_be))) |
+ (addr_hit[179] & (|(RV_PLIC_PERMIT[179] & ~reg_be))) |
+ (addr_hit[180] & (|(RV_PLIC_PERMIT[180] & ~reg_be))) |
+ (addr_hit[181] & (|(RV_PLIC_PERMIT[181] & ~reg_be))) |
+ (addr_hit[182] & (|(RV_PLIC_PERMIT[182] & ~reg_be))) |
+ (addr_hit[183] & (|(RV_PLIC_PERMIT[183] & ~reg_be))) |
+ (addr_hit[184] & (|(RV_PLIC_PERMIT[184] & ~reg_be))) |
+ (addr_hit[185] & (|(RV_PLIC_PERMIT[185] & ~reg_be))) |
+ (addr_hit[186] & (|(RV_PLIC_PERMIT[186] & ~reg_be))) |
+ (addr_hit[187] & (|(RV_PLIC_PERMIT[187] & ~reg_be))) |
+ (addr_hit[188] & (|(RV_PLIC_PERMIT[188] & ~reg_be))) |
+ (addr_hit[189] & (|(RV_PLIC_PERMIT[189] & ~reg_be))) |
+ (addr_hit[190] & (|(RV_PLIC_PERMIT[190] & ~reg_be))) |
+ (addr_hit[191] & (|(RV_PLIC_PERMIT[191] & ~reg_be))) |
+ (addr_hit[192] & (|(RV_PLIC_PERMIT[192] & ~reg_be))) |
+ (addr_hit[193] & (|(RV_PLIC_PERMIT[193] & ~reg_be))) |
+ (addr_hit[194] & (|(RV_PLIC_PERMIT[194] & ~reg_be))) |
+ (addr_hit[195] & (|(RV_PLIC_PERMIT[195] & ~reg_be))) |
+ (addr_hit[196] & (|(RV_PLIC_PERMIT[196] & ~reg_be))) |
+ (addr_hit[197] & (|(RV_PLIC_PERMIT[197] & ~reg_be))) |
+ (addr_hit[198] & (|(RV_PLIC_PERMIT[198] & ~reg_be))) |
+ (addr_hit[199] & (|(RV_PLIC_PERMIT[199] & ~reg_be))) |
+ (addr_hit[200] & (|(RV_PLIC_PERMIT[200] & ~reg_be))) |
+ (addr_hit[201] & (|(RV_PLIC_PERMIT[201] & ~reg_be))) |
+ (addr_hit[202] & (|(RV_PLIC_PERMIT[202] & ~reg_be))) |
+ (addr_hit[203] & (|(RV_PLIC_PERMIT[203] & ~reg_be))) |
+ (addr_hit[204] & (|(RV_PLIC_PERMIT[204] & ~reg_be))) |
+ (addr_hit[205] & (|(RV_PLIC_PERMIT[205] & ~reg_be))) |
+ (addr_hit[206] & (|(RV_PLIC_PERMIT[206] & ~reg_be))) |
+ (addr_hit[207] & (|(RV_PLIC_PERMIT[207] & ~reg_be))) |
+ (addr_hit[208] & (|(RV_PLIC_PERMIT[208] & ~reg_be))) |
+ (addr_hit[209] & (|(RV_PLIC_PERMIT[209] & ~reg_be))) |
+ (addr_hit[210] & (|(RV_PLIC_PERMIT[210] & ~reg_be))) |
+ (addr_hit[211] & (|(RV_PLIC_PERMIT[211] & ~reg_be))) |
+ (addr_hit[212] & (|(RV_PLIC_PERMIT[212] & ~reg_be))) |
+ (addr_hit[213] & (|(RV_PLIC_PERMIT[213] & ~reg_be))) |
+ (addr_hit[214] & (|(RV_PLIC_PERMIT[214] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign prio0_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign prio0_wd = reg_wdata[1:0];
+ assign prio1_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign prio1_wd = reg_wdata[1:0];
+ assign prio2_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign prio2_wd = reg_wdata[1:0];
+ assign prio3_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign prio3_wd = reg_wdata[1:0];
+ assign prio4_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign prio4_wd = reg_wdata[1:0];
+ assign prio5_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign prio5_wd = reg_wdata[1:0];
+ assign prio6_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign prio6_wd = reg_wdata[1:0];
+ assign prio7_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign prio7_wd = reg_wdata[1:0];
+ assign prio8_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign prio8_wd = reg_wdata[1:0];
+ assign prio9_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign prio9_wd = reg_wdata[1:0];
+ assign prio10_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign prio10_wd = reg_wdata[1:0];
+ assign prio11_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign prio11_wd = reg_wdata[1:0];
+ assign prio12_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign prio12_wd = reg_wdata[1:0];
+ assign prio13_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign prio13_wd = reg_wdata[1:0];
+ assign prio14_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign prio14_wd = reg_wdata[1:0];
+ assign prio15_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign prio15_wd = reg_wdata[1:0];
+ assign prio16_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign prio16_wd = reg_wdata[1:0];
+ assign prio17_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign prio17_wd = reg_wdata[1:0];
+ assign prio18_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign prio18_wd = reg_wdata[1:0];
+ assign prio19_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign prio19_wd = reg_wdata[1:0];
+ assign prio20_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign prio20_wd = reg_wdata[1:0];
+ assign prio21_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign prio21_wd = reg_wdata[1:0];
+ assign prio22_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign prio22_wd = reg_wdata[1:0];
+ assign prio23_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign prio23_wd = reg_wdata[1:0];
+ assign prio24_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign prio24_wd = reg_wdata[1:0];
+ assign prio25_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign prio25_wd = reg_wdata[1:0];
+ assign prio26_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign prio26_wd = reg_wdata[1:0];
+ assign prio27_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign prio27_wd = reg_wdata[1:0];
+ assign prio28_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign prio28_wd = reg_wdata[1:0];
+ assign prio29_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign prio29_wd = reg_wdata[1:0];
+ assign prio30_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign prio30_wd = reg_wdata[1:0];
+ assign prio31_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign prio31_wd = reg_wdata[1:0];
+ assign prio32_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign prio32_wd = reg_wdata[1:0];
+ assign prio33_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign prio33_wd = reg_wdata[1:0];
+ assign prio34_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign prio34_wd = reg_wdata[1:0];
+ assign prio35_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign prio35_wd = reg_wdata[1:0];
+ assign prio36_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign prio36_wd = reg_wdata[1:0];
+ assign prio37_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign prio37_wd = reg_wdata[1:0];
+ assign prio38_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign prio38_wd = reg_wdata[1:0];
+ assign prio39_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign prio39_wd = reg_wdata[1:0];
+ assign prio40_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign prio40_wd = reg_wdata[1:0];
+ assign prio41_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign prio41_wd = reg_wdata[1:0];
+ assign prio42_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign prio42_wd = reg_wdata[1:0];
+ assign prio43_we = addr_hit[43] & reg_we & !reg_error;
+
+ assign prio43_wd = reg_wdata[1:0];
+ assign prio44_we = addr_hit[44] & reg_we & !reg_error;
+
+ assign prio44_wd = reg_wdata[1:0];
+ assign prio45_we = addr_hit[45] & reg_we & !reg_error;
+
+ assign prio45_wd = reg_wdata[1:0];
+ assign prio46_we = addr_hit[46] & reg_we & !reg_error;
+
+ assign prio46_wd = reg_wdata[1:0];
+ assign prio47_we = addr_hit[47] & reg_we & !reg_error;
+
+ assign prio47_wd = reg_wdata[1:0];
+ assign prio48_we = addr_hit[48] & reg_we & !reg_error;
+
+ assign prio48_wd = reg_wdata[1:0];
+ assign prio49_we = addr_hit[49] & reg_we & !reg_error;
+
+ assign prio49_wd = reg_wdata[1:0];
+ assign prio50_we = addr_hit[50] & reg_we & !reg_error;
+
+ assign prio50_wd = reg_wdata[1:0];
+ assign prio51_we = addr_hit[51] & reg_we & !reg_error;
+
+ assign prio51_wd = reg_wdata[1:0];
+ assign prio52_we = addr_hit[52] & reg_we & !reg_error;
+
+ assign prio52_wd = reg_wdata[1:0];
+ assign prio53_we = addr_hit[53] & reg_we & !reg_error;
+
+ assign prio53_wd = reg_wdata[1:0];
+ assign prio54_we = addr_hit[54] & reg_we & !reg_error;
+
+ assign prio54_wd = reg_wdata[1:0];
+ assign prio55_we = addr_hit[55] & reg_we & !reg_error;
+
+ assign prio55_wd = reg_wdata[1:0];
+ assign prio56_we = addr_hit[56] & reg_we & !reg_error;
+
+ assign prio56_wd = reg_wdata[1:0];
+ assign prio57_we = addr_hit[57] & reg_we & !reg_error;
+
+ assign prio57_wd = reg_wdata[1:0];
+ assign prio58_we = addr_hit[58] & reg_we & !reg_error;
+
+ assign prio58_wd = reg_wdata[1:0];
+ assign prio59_we = addr_hit[59] & reg_we & !reg_error;
+
+ assign prio59_wd = reg_wdata[1:0];
+ assign prio60_we = addr_hit[60] & reg_we & !reg_error;
+
+ assign prio60_wd = reg_wdata[1:0];
+ assign prio61_we = addr_hit[61] & reg_we & !reg_error;
+
+ assign prio61_wd = reg_wdata[1:0];
+ assign prio62_we = addr_hit[62] & reg_we & !reg_error;
+
+ assign prio62_wd = reg_wdata[1:0];
+ assign prio63_we = addr_hit[63] & reg_we & !reg_error;
+
+ assign prio63_wd = reg_wdata[1:0];
+ assign prio64_we = addr_hit[64] & reg_we & !reg_error;
+
+ assign prio64_wd = reg_wdata[1:0];
+ assign prio65_we = addr_hit[65] & reg_we & !reg_error;
+
+ assign prio65_wd = reg_wdata[1:0];
+ assign prio66_we = addr_hit[66] & reg_we & !reg_error;
+
+ assign prio66_wd = reg_wdata[1:0];
+ assign prio67_we = addr_hit[67] & reg_we & !reg_error;
+
+ assign prio67_wd = reg_wdata[1:0];
+ assign prio68_we = addr_hit[68] & reg_we & !reg_error;
+
+ assign prio68_wd = reg_wdata[1:0];
+ assign prio69_we = addr_hit[69] & reg_we & !reg_error;
+
+ assign prio69_wd = reg_wdata[1:0];
+ assign prio70_we = addr_hit[70] & reg_we & !reg_error;
+
+ assign prio70_wd = reg_wdata[1:0];
+ assign prio71_we = addr_hit[71] & reg_we & !reg_error;
+
+ assign prio71_wd = reg_wdata[1:0];
+ assign prio72_we = addr_hit[72] & reg_we & !reg_error;
+
+ assign prio72_wd = reg_wdata[1:0];
+ assign prio73_we = addr_hit[73] & reg_we & !reg_error;
+
+ assign prio73_wd = reg_wdata[1:0];
+ assign prio74_we = addr_hit[74] & reg_we & !reg_error;
+
+ assign prio74_wd = reg_wdata[1:0];
+ assign prio75_we = addr_hit[75] & reg_we & !reg_error;
+
+ assign prio75_wd = reg_wdata[1:0];
+ assign prio76_we = addr_hit[76] & reg_we & !reg_error;
+
+ assign prio76_wd = reg_wdata[1:0];
+ assign prio77_we = addr_hit[77] & reg_we & !reg_error;
+
+ assign prio77_wd = reg_wdata[1:0];
+ assign prio78_we = addr_hit[78] & reg_we & !reg_error;
+
+ assign prio78_wd = reg_wdata[1:0];
+ assign prio79_we = addr_hit[79] & reg_we & !reg_error;
+
+ assign prio79_wd = reg_wdata[1:0];
+ assign prio80_we = addr_hit[80] & reg_we & !reg_error;
+
+ assign prio80_wd = reg_wdata[1:0];
+ assign prio81_we = addr_hit[81] & reg_we & !reg_error;
+
+ assign prio81_wd = reg_wdata[1:0];
+ assign prio82_we = addr_hit[82] & reg_we & !reg_error;
+
+ assign prio82_wd = reg_wdata[1:0];
+ assign prio83_we = addr_hit[83] & reg_we & !reg_error;
+
+ assign prio83_wd = reg_wdata[1:0];
+ assign prio84_we = addr_hit[84] & reg_we & !reg_error;
+
+ assign prio84_wd = reg_wdata[1:0];
+ assign prio85_we = addr_hit[85] & reg_we & !reg_error;
+
+ assign prio85_wd = reg_wdata[1:0];
+ assign prio86_we = addr_hit[86] & reg_we & !reg_error;
+
+ assign prio86_wd = reg_wdata[1:0];
+ assign prio87_we = addr_hit[87] & reg_we & !reg_error;
+
+ assign prio87_wd = reg_wdata[1:0];
+ assign prio88_we = addr_hit[88] & reg_we & !reg_error;
+
+ assign prio88_wd = reg_wdata[1:0];
+ assign prio89_we = addr_hit[89] & reg_we & !reg_error;
+
+ assign prio89_wd = reg_wdata[1:0];
+ assign prio90_we = addr_hit[90] & reg_we & !reg_error;
+
+ assign prio90_wd = reg_wdata[1:0];
+ assign prio91_we = addr_hit[91] & reg_we & !reg_error;
+
+ assign prio91_wd = reg_wdata[1:0];
+ assign prio92_we = addr_hit[92] & reg_we & !reg_error;
+
+ assign prio92_wd = reg_wdata[1:0];
+ assign prio93_we = addr_hit[93] & reg_we & !reg_error;
+
+ assign prio93_wd = reg_wdata[1:0];
+ assign prio94_we = addr_hit[94] & reg_we & !reg_error;
+
+ assign prio94_wd = reg_wdata[1:0];
+ assign prio95_we = addr_hit[95] & reg_we & !reg_error;
+
+ assign prio95_wd = reg_wdata[1:0];
+ assign prio96_we = addr_hit[96] & reg_we & !reg_error;
+
+ assign prio96_wd = reg_wdata[1:0];
+ assign prio97_we = addr_hit[97] & reg_we & !reg_error;
+
+ assign prio97_wd = reg_wdata[1:0];
+ assign prio98_we = addr_hit[98] & reg_we & !reg_error;
+
+ assign prio98_wd = reg_wdata[1:0];
+ assign prio99_we = addr_hit[99] & reg_we & !reg_error;
+
+ assign prio99_wd = reg_wdata[1:0];
+ assign prio100_we = addr_hit[100] & reg_we & !reg_error;
+
+ assign prio100_wd = reg_wdata[1:0];
+ assign prio101_we = addr_hit[101] & reg_we & !reg_error;
+
+ assign prio101_wd = reg_wdata[1:0];
+ assign prio102_we = addr_hit[102] & reg_we & !reg_error;
+
+ assign prio102_wd = reg_wdata[1:0];
+ assign prio103_we = addr_hit[103] & reg_we & !reg_error;
+
+ assign prio103_wd = reg_wdata[1:0];
+ assign prio104_we = addr_hit[104] & reg_we & !reg_error;
+
+ assign prio104_wd = reg_wdata[1:0];
+ assign prio105_we = addr_hit[105] & reg_we & !reg_error;
+
+ assign prio105_wd = reg_wdata[1:0];
+ assign prio106_we = addr_hit[106] & reg_we & !reg_error;
+
+ assign prio106_wd = reg_wdata[1:0];
+ assign prio107_we = addr_hit[107] & reg_we & !reg_error;
+
+ assign prio107_wd = reg_wdata[1:0];
+ assign prio108_we = addr_hit[108] & reg_we & !reg_error;
+
+ assign prio108_wd = reg_wdata[1:0];
+ assign prio109_we = addr_hit[109] & reg_we & !reg_error;
+
+ assign prio109_wd = reg_wdata[1:0];
+ assign prio110_we = addr_hit[110] & reg_we & !reg_error;
+
+ assign prio110_wd = reg_wdata[1:0];
+ assign prio111_we = addr_hit[111] & reg_we & !reg_error;
+
+ assign prio111_wd = reg_wdata[1:0];
+ assign prio112_we = addr_hit[112] & reg_we & !reg_error;
+
+ assign prio112_wd = reg_wdata[1:0];
+ assign prio113_we = addr_hit[113] & reg_we & !reg_error;
+
+ assign prio113_wd = reg_wdata[1:0];
+ assign prio114_we = addr_hit[114] & reg_we & !reg_error;
+
+ assign prio114_wd = reg_wdata[1:0];
+ assign prio115_we = addr_hit[115] & reg_we & !reg_error;
+
+ assign prio115_wd = reg_wdata[1:0];
+ assign prio116_we = addr_hit[116] & reg_we & !reg_error;
+
+ assign prio116_wd = reg_wdata[1:0];
+ assign prio117_we = addr_hit[117] & reg_we & !reg_error;
+
+ assign prio117_wd = reg_wdata[1:0];
+ assign prio118_we = addr_hit[118] & reg_we & !reg_error;
+
+ assign prio118_wd = reg_wdata[1:0];
+ assign prio119_we = addr_hit[119] & reg_we & !reg_error;
+
+ assign prio119_wd = reg_wdata[1:0];
+ assign prio120_we = addr_hit[120] & reg_we & !reg_error;
+
+ assign prio120_wd = reg_wdata[1:0];
+ assign prio121_we = addr_hit[121] & reg_we & !reg_error;
+
+ assign prio121_wd = reg_wdata[1:0];
+ assign prio122_we = addr_hit[122] & reg_we & !reg_error;
+
+ assign prio122_wd = reg_wdata[1:0];
+ assign prio123_we = addr_hit[123] & reg_we & !reg_error;
+
+ assign prio123_wd = reg_wdata[1:0];
+ assign prio124_we = addr_hit[124] & reg_we & !reg_error;
+
+ assign prio124_wd = reg_wdata[1:0];
+ assign prio125_we = addr_hit[125] & reg_we & !reg_error;
+
+ assign prio125_wd = reg_wdata[1:0];
+ assign prio126_we = addr_hit[126] & reg_we & !reg_error;
+
+ assign prio126_wd = reg_wdata[1:0];
+ assign prio127_we = addr_hit[127] & reg_we & !reg_error;
+
+ assign prio127_wd = reg_wdata[1:0];
+ assign prio128_we = addr_hit[128] & reg_we & !reg_error;
+
+ assign prio128_wd = reg_wdata[1:0];
+ assign prio129_we = addr_hit[129] & reg_we & !reg_error;
+
+ assign prio129_wd = reg_wdata[1:0];
+ assign prio130_we = addr_hit[130] & reg_we & !reg_error;
+
+ assign prio130_wd = reg_wdata[1:0];
+ assign prio131_we = addr_hit[131] & reg_we & !reg_error;
+
+ assign prio131_wd = reg_wdata[1:0];
+ assign prio132_we = addr_hit[132] & reg_we & !reg_error;
+
+ assign prio132_wd = reg_wdata[1:0];
+ assign prio133_we = addr_hit[133] & reg_we & !reg_error;
+
+ assign prio133_wd = reg_wdata[1:0];
+ assign prio134_we = addr_hit[134] & reg_we & !reg_error;
+
+ assign prio134_wd = reg_wdata[1:0];
+ assign prio135_we = addr_hit[135] & reg_we & !reg_error;
+
+ assign prio135_wd = reg_wdata[1:0];
+ assign prio136_we = addr_hit[136] & reg_we & !reg_error;
+
+ assign prio136_wd = reg_wdata[1:0];
+ assign prio137_we = addr_hit[137] & reg_we & !reg_error;
+
+ assign prio137_wd = reg_wdata[1:0];
+ assign prio138_we = addr_hit[138] & reg_we & !reg_error;
+
+ assign prio138_wd = reg_wdata[1:0];
+ assign prio139_we = addr_hit[139] & reg_we & !reg_error;
+
+ assign prio139_wd = reg_wdata[1:0];
+ assign prio140_we = addr_hit[140] & reg_we & !reg_error;
+
+ assign prio140_wd = reg_wdata[1:0];
+ assign prio141_we = addr_hit[141] & reg_we & !reg_error;
+
+ assign prio141_wd = reg_wdata[1:0];
+ assign prio142_we = addr_hit[142] & reg_we & !reg_error;
+
+ assign prio142_wd = reg_wdata[1:0];
+ assign prio143_we = addr_hit[143] & reg_we & !reg_error;
+
+ assign prio143_wd = reg_wdata[1:0];
+ assign prio144_we = addr_hit[144] & reg_we & !reg_error;
+
+ assign prio144_wd = reg_wdata[1:0];
+ assign prio145_we = addr_hit[145] & reg_we & !reg_error;
+
+ assign prio145_wd = reg_wdata[1:0];
+ assign prio146_we = addr_hit[146] & reg_we & !reg_error;
+
+ assign prio146_wd = reg_wdata[1:0];
+ assign prio147_we = addr_hit[147] & reg_we & !reg_error;
+
+ assign prio147_wd = reg_wdata[1:0];
+ assign prio148_we = addr_hit[148] & reg_we & !reg_error;
+
+ assign prio148_wd = reg_wdata[1:0];
+ assign prio149_we = addr_hit[149] & reg_we & !reg_error;
+
+ assign prio149_wd = reg_wdata[1:0];
+ assign prio150_we = addr_hit[150] & reg_we & !reg_error;
+
+ assign prio150_wd = reg_wdata[1:0];
+ assign prio151_we = addr_hit[151] & reg_we & !reg_error;
+
+ assign prio151_wd = reg_wdata[1:0];
+ assign prio152_we = addr_hit[152] & reg_we & !reg_error;
+
+ assign prio152_wd = reg_wdata[1:0];
+ assign prio153_we = addr_hit[153] & reg_we & !reg_error;
+
+ assign prio153_wd = reg_wdata[1:0];
+ assign prio154_we = addr_hit[154] & reg_we & !reg_error;
+
+ assign prio154_wd = reg_wdata[1:0];
+ assign prio155_we = addr_hit[155] & reg_we & !reg_error;
+
+ assign prio155_wd = reg_wdata[1:0];
+ assign prio156_we = addr_hit[156] & reg_we & !reg_error;
+
+ assign prio156_wd = reg_wdata[1:0];
+ assign prio157_we = addr_hit[157] & reg_we & !reg_error;
+
+ assign prio157_wd = reg_wdata[1:0];
+ assign prio158_we = addr_hit[158] & reg_we & !reg_error;
+
+ assign prio158_wd = reg_wdata[1:0];
+ assign prio159_we = addr_hit[159] & reg_we & !reg_error;
+
+ assign prio159_wd = reg_wdata[1:0];
+ assign prio160_we = addr_hit[160] & reg_we & !reg_error;
+
+ assign prio160_wd = reg_wdata[1:0];
+ assign prio161_we = addr_hit[161] & reg_we & !reg_error;
+
+ assign prio161_wd = reg_wdata[1:0];
+ assign prio162_we = addr_hit[162] & reg_we & !reg_error;
+
+ assign prio162_wd = reg_wdata[1:0];
+ assign prio163_we = addr_hit[163] & reg_we & !reg_error;
+
+ assign prio163_wd = reg_wdata[1:0];
+ assign prio164_we = addr_hit[164] & reg_we & !reg_error;
+
+ assign prio164_wd = reg_wdata[1:0];
+ assign prio165_we = addr_hit[165] & reg_we & !reg_error;
+
+ assign prio165_wd = reg_wdata[1:0];
+ assign prio166_we = addr_hit[166] & reg_we & !reg_error;
+
+ assign prio166_wd = reg_wdata[1:0];
+ assign prio167_we = addr_hit[167] & reg_we & !reg_error;
+
+ assign prio167_wd = reg_wdata[1:0];
+ assign prio168_we = addr_hit[168] & reg_we & !reg_error;
+
+ assign prio168_wd = reg_wdata[1:0];
+ assign prio169_we = addr_hit[169] & reg_we & !reg_error;
+
+ assign prio169_wd = reg_wdata[1:0];
+ assign prio170_we = addr_hit[170] & reg_we & !reg_error;
+
+ assign prio170_wd = reg_wdata[1:0];
+ assign prio171_we = addr_hit[171] & reg_we & !reg_error;
+
+ assign prio171_wd = reg_wdata[1:0];
+ assign prio172_we = addr_hit[172] & reg_we & !reg_error;
+
+ assign prio172_wd = reg_wdata[1:0];
+ assign prio173_we = addr_hit[173] & reg_we & !reg_error;
+
+ assign prio173_wd = reg_wdata[1:0];
+ assign prio174_we = addr_hit[174] & reg_we & !reg_error;
+
+ assign prio174_wd = reg_wdata[1:0];
+ assign prio175_we = addr_hit[175] & reg_we & !reg_error;
+
+ assign prio175_wd = reg_wdata[1:0];
+ assign prio176_we = addr_hit[176] & reg_we & !reg_error;
+
+ assign prio176_wd = reg_wdata[1:0];
+ assign prio177_we = addr_hit[177] & reg_we & !reg_error;
+
+ assign prio177_wd = reg_wdata[1:0];
+ assign prio178_we = addr_hit[178] & reg_we & !reg_error;
+
+ assign prio178_wd = reg_wdata[1:0];
+ assign prio179_we = addr_hit[179] & reg_we & !reg_error;
+
+ assign prio179_wd = reg_wdata[1:0];
+ assign prio180_we = addr_hit[180] & reg_we & !reg_error;
+
+ assign prio180_wd = reg_wdata[1:0];
+ assign prio181_we = addr_hit[181] & reg_we & !reg_error;
+
+ assign prio181_wd = reg_wdata[1:0];
+ assign prio182_we = addr_hit[182] & reg_we & !reg_error;
+
+ assign prio182_wd = reg_wdata[1:0];
+ assign prio183_we = addr_hit[183] & reg_we & !reg_error;
+
+ assign prio183_wd = reg_wdata[1:0];
+ assign prio184_we = addr_hit[184] & reg_we & !reg_error;
+
+ assign prio184_wd = reg_wdata[1:0];
+ assign prio185_we = addr_hit[185] & reg_we & !reg_error;
+
+ assign prio185_wd = reg_wdata[1:0];
+ assign prio186_we = addr_hit[186] & reg_we & !reg_error;
+
+ assign prio186_wd = reg_wdata[1:0];
+ assign prio187_we = addr_hit[187] & reg_we & !reg_error;
+
+ assign prio187_wd = reg_wdata[1:0];
+ assign prio188_we = addr_hit[188] & reg_we & !reg_error;
+
+ assign prio188_wd = reg_wdata[1:0];
+ assign prio189_we = addr_hit[189] & reg_we & !reg_error;
+
+ assign prio189_wd = reg_wdata[1:0];
+ assign ie0_0_we = addr_hit[196] & reg_we & !reg_error;
+
+ assign ie0_0_e_0_wd = reg_wdata[0];
+
+ assign ie0_0_e_1_wd = reg_wdata[1];
+
+ assign ie0_0_e_2_wd = reg_wdata[2];
+
+ assign ie0_0_e_3_wd = reg_wdata[3];
+
+ assign ie0_0_e_4_wd = reg_wdata[4];
+
+ assign ie0_0_e_5_wd = reg_wdata[5];
+
+ assign ie0_0_e_6_wd = reg_wdata[6];
+
+ assign ie0_0_e_7_wd = reg_wdata[7];
+
+ assign ie0_0_e_8_wd = reg_wdata[8];
+
+ assign ie0_0_e_9_wd = reg_wdata[9];
+
+ assign ie0_0_e_10_wd = reg_wdata[10];
+
+ assign ie0_0_e_11_wd = reg_wdata[11];
+
+ assign ie0_0_e_12_wd = reg_wdata[12];
+
+ assign ie0_0_e_13_wd = reg_wdata[13];
+
+ assign ie0_0_e_14_wd = reg_wdata[14];
+
+ assign ie0_0_e_15_wd = reg_wdata[15];
+
+ assign ie0_0_e_16_wd = reg_wdata[16];
+
+ assign ie0_0_e_17_wd = reg_wdata[17];
+
+ assign ie0_0_e_18_wd = reg_wdata[18];
+
+ assign ie0_0_e_19_wd = reg_wdata[19];
+
+ assign ie0_0_e_20_wd = reg_wdata[20];
+
+ assign ie0_0_e_21_wd = reg_wdata[21];
+
+ assign ie0_0_e_22_wd = reg_wdata[22];
+
+ assign ie0_0_e_23_wd = reg_wdata[23];
+
+ assign ie0_0_e_24_wd = reg_wdata[24];
+
+ assign ie0_0_e_25_wd = reg_wdata[25];
+
+ assign ie0_0_e_26_wd = reg_wdata[26];
+
+ assign ie0_0_e_27_wd = reg_wdata[27];
+
+ assign ie0_0_e_28_wd = reg_wdata[28];
+
+ assign ie0_0_e_29_wd = reg_wdata[29];
+
+ assign ie0_0_e_30_wd = reg_wdata[30];
+
+ assign ie0_0_e_31_wd = reg_wdata[31];
+ assign ie0_1_we = addr_hit[197] & reg_we & !reg_error;
+
+ assign ie0_1_e_32_wd = reg_wdata[0];
+
+ assign ie0_1_e_33_wd = reg_wdata[1];
+
+ assign ie0_1_e_34_wd = reg_wdata[2];
+
+ assign ie0_1_e_35_wd = reg_wdata[3];
+
+ assign ie0_1_e_36_wd = reg_wdata[4];
+
+ assign ie0_1_e_37_wd = reg_wdata[5];
+
+ assign ie0_1_e_38_wd = reg_wdata[6];
+
+ assign ie0_1_e_39_wd = reg_wdata[7];
+
+ assign ie0_1_e_40_wd = reg_wdata[8];
+
+ assign ie0_1_e_41_wd = reg_wdata[9];
+
+ assign ie0_1_e_42_wd = reg_wdata[10];
+
+ assign ie0_1_e_43_wd = reg_wdata[11];
+
+ assign ie0_1_e_44_wd = reg_wdata[12];
+
+ assign ie0_1_e_45_wd = reg_wdata[13];
+
+ assign ie0_1_e_46_wd = reg_wdata[14];
+
+ assign ie0_1_e_47_wd = reg_wdata[15];
+
+ assign ie0_1_e_48_wd = reg_wdata[16];
+
+ assign ie0_1_e_49_wd = reg_wdata[17];
+
+ assign ie0_1_e_50_wd = reg_wdata[18];
+
+ assign ie0_1_e_51_wd = reg_wdata[19];
+
+ assign ie0_1_e_52_wd = reg_wdata[20];
+
+ assign ie0_1_e_53_wd = reg_wdata[21];
+
+ assign ie0_1_e_54_wd = reg_wdata[22];
+
+ assign ie0_1_e_55_wd = reg_wdata[23];
+
+ assign ie0_1_e_56_wd = reg_wdata[24];
+
+ assign ie0_1_e_57_wd = reg_wdata[25];
+
+ assign ie0_1_e_58_wd = reg_wdata[26];
+
+ assign ie0_1_e_59_wd = reg_wdata[27];
+
+ assign ie0_1_e_60_wd = reg_wdata[28];
+
+ assign ie0_1_e_61_wd = reg_wdata[29];
+
+ assign ie0_1_e_62_wd = reg_wdata[30];
+
+ assign ie0_1_e_63_wd = reg_wdata[31];
+ assign ie0_2_we = addr_hit[198] & reg_we & !reg_error;
+
+ assign ie0_2_e_64_wd = reg_wdata[0];
+
+ assign ie0_2_e_65_wd = reg_wdata[1];
+
+ assign ie0_2_e_66_wd = reg_wdata[2];
+
+ assign ie0_2_e_67_wd = reg_wdata[3];
+
+ assign ie0_2_e_68_wd = reg_wdata[4];
+
+ assign ie0_2_e_69_wd = reg_wdata[5];
+
+ assign ie0_2_e_70_wd = reg_wdata[6];
+
+ assign ie0_2_e_71_wd = reg_wdata[7];
+
+ assign ie0_2_e_72_wd = reg_wdata[8];
+
+ assign ie0_2_e_73_wd = reg_wdata[9];
+
+ assign ie0_2_e_74_wd = reg_wdata[10];
+
+ assign ie0_2_e_75_wd = reg_wdata[11];
+
+ assign ie0_2_e_76_wd = reg_wdata[12];
+
+ assign ie0_2_e_77_wd = reg_wdata[13];
+
+ assign ie0_2_e_78_wd = reg_wdata[14];
+
+ assign ie0_2_e_79_wd = reg_wdata[15];
+
+ assign ie0_2_e_80_wd = reg_wdata[16];
+
+ assign ie0_2_e_81_wd = reg_wdata[17];
+
+ assign ie0_2_e_82_wd = reg_wdata[18];
+
+ assign ie0_2_e_83_wd = reg_wdata[19];
+
+ assign ie0_2_e_84_wd = reg_wdata[20];
+
+ assign ie0_2_e_85_wd = reg_wdata[21];
+
+ assign ie0_2_e_86_wd = reg_wdata[22];
+
+ assign ie0_2_e_87_wd = reg_wdata[23];
+
+ assign ie0_2_e_88_wd = reg_wdata[24];
+
+ assign ie0_2_e_89_wd = reg_wdata[25];
+
+ assign ie0_2_e_90_wd = reg_wdata[26];
+
+ assign ie0_2_e_91_wd = reg_wdata[27];
+
+ assign ie0_2_e_92_wd = reg_wdata[28];
+
+ assign ie0_2_e_93_wd = reg_wdata[29];
+
+ assign ie0_2_e_94_wd = reg_wdata[30];
+
+ assign ie0_2_e_95_wd = reg_wdata[31];
+ assign ie0_3_we = addr_hit[199] & reg_we & !reg_error;
+
+ assign ie0_3_e_96_wd = reg_wdata[0];
+
+ assign ie0_3_e_97_wd = reg_wdata[1];
+
+ assign ie0_3_e_98_wd = reg_wdata[2];
+
+ assign ie0_3_e_99_wd = reg_wdata[3];
+
+ assign ie0_3_e_100_wd = reg_wdata[4];
+
+ assign ie0_3_e_101_wd = reg_wdata[5];
+
+ assign ie0_3_e_102_wd = reg_wdata[6];
+
+ assign ie0_3_e_103_wd = reg_wdata[7];
+
+ assign ie0_3_e_104_wd = reg_wdata[8];
+
+ assign ie0_3_e_105_wd = reg_wdata[9];
+
+ assign ie0_3_e_106_wd = reg_wdata[10];
+
+ assign ie0_3_e_107_wd = reg_wdata[11];
+
+ assign ie0_3_e_108_wd = reg_wdata[12];
+
+ assign ie0_3_e_109_wd = reg_wdata[13];
+
+ assign ie0_3_e_110_wd = reg_wdata[14];
+
+ assign ie0_3_e_111_wd = reg_wdata[15];
+
+ assign ie0_3_e_112_wd = reg_wdata[16];
+
+ assign ie0_3_e_113_wd = reg_wdata[17];
+
+ assign ie0_3_e_114_wd = reg_wdata[18];
+
+ assign ie0_3_e_115_wd = reg_wdata[19];
+
+ assign ie0_3_e_116_wd = reg_wdata[20];
+
+ assign ie0_3_e_117_wd = reg_wdata[21];
+
+ assign ie0_3_e_118_wd = reg_wdata[22];
+
+ assign ie0_3_e_119_wd = reg_wdata[23];
+
+ assign ie0_3_e_120_wd = reg_wdata[24];
+
+ assign ie0_3_e_121_wd = reg_wdata[25];
+
+ assign ie0_3_e_122_wd = reg_wdata[26];
+
+ assign ie0_3_e_123_wd = reg_wdata[27];
+
+ assign ie0_3_e_124_wd = reg_wdata[28];
+
+ assign ie0_3_e_125_wd = reg_wdata[29];
+
+ assign ie0_3_e_126_wd = reg_wdata[30];
+
+ assign ie0_3_e_127_wd = reg_wdata[31];
+ assign ie0_4_we = addr_hit[200] & reg_we & !reg_error;
+
+ assign ie0_4_e_128_wd = reg_wdata[0];
+
+ assign ie0_4_e_129_wd = reg_wdata[1];
+
+ assign ie0_4_e_130_wd = reg_wdata[2];
+
+ assign ie0_4_e_131_wd = reg_wdata[3];
+
+ assign ie0_4_e_132_wd = reg_wdata[4];
+
+ assign ie0_4_e_133_wd = reg_wdata[5];
+
+ assign ie0_4_e_134_wd = reg_wdata[6];
+
+ assign ie0_4_e_135_wd = reg_wdata[7];
+
+ assign ie0_4_e_136_wd = reg_wdata[8];
+
+ assign ie0_4_e_137_wd = reg_wdata[9];
+
+ assign ie0_4_e_138_wd = reg_wdata[10];
+
+ assign ie0_4_e_139_wd = reg_wdata[11];
+
+ assign ie0_4_e_140_wd = reg_wdata[12];
+
+ assign ie0_4_e_141_wd = reg_wdata[13];
+
+ assign ie0_4_e_142_wd = reg_wdata[14];
+
+ assign ie0_4_e_143_wd = reg_wdata[15];
+
+ assign ie0_4_e_144_wd = reg_wdata[16];
+
+ assign ie0_4_e_145_wd = reg_wdata[17];
+
+ assign ie0_4_e_146_wd = reg_wdata[18];
+
+ assign ie0_4_e_147_wd = reg_wdata[19];
+
+ assign ie0_4_e_148_wd = reg_wdata[20];
+
+ assign ie0_4_e_149_wd = reg_wdata[21];
+
+ assign ie0_4_e_150_wd = reg_wdata[22];
+
+ assign ie0_4_e_151_wd = reg_wdata[23];
+
+ assign ie0_4_e_152_wd = reg_wdata[24];
+
+ assign ie0_4_e_153_wd = reg_wdata[25];
+
+ assign ie0_4_e_154_wd = reg_wdata[26];
+
+ assign ie0_4_e_155_wd = reg_wdata[27];
+
+ assign ie0_4_e_156_wd = reg_wdata[28];
+
+ assign ie0_4_e_157_wd = reg_wdata[29];
+
+ assign ie0_4_e_158_wd = reg_wdata[30];
+
+ assign ie0_4_e_159_wd = reg_wdata[31];
+ assign ie0_5_we = addr_hit[201] & reg_we & !reg_error;
+
+ assign ie0_5_e_160_wd = reg_wdata[0];
+
+ assign ie0_5_e_161_wd = reg_wdata[1];
+
+ assign ie0_5_e_162_wd = reg_wdata[2];
+
+ assign ie0_5_e_163_wd = reg_wdata[3];
+
+ assign ie0_5_e_164_wd = reg_wdata[4];
+
+ assign ie0_5_e_165_wd = reg_wdata[5];
+
+ assign ie0_5_e_166_wd = reg_wdata[6];
+
+ assign ie0_5_e_167_wd = reg_wdata[7];
+
+ assign ie0_5_e_168_wd = reg_wdata[8];
+
+ assign ie0_5_e_169_wd = reg_wdata[9];
+
+ assign ie0_5_e_170_wd = reg_wdata[10];
+
+ assign ie0_5_e_171_wd = reg_wdata[11];
+
+ assign ie0_5_e_172_wd = reg_wdata[12];
+
+ assign ie0_5_e_173_wd = reg_wdata[13];
+
+ assign ie0_5_e_174_wd = reg_wdata[14];
+
+ assign ie0_5_e_175_wd = reg_wdata[15];
+
+ assign ie0_5_e_176_wd = reg_wdata[16];
+
+ assign ie0_5_e_177_wd = reg_wdata[17];
+
+ assign ie0_5_e_178_wd = reg_wdata[18];
+
+ assign ie0_5_e_179_wd = reg_wdata[19];
+
+ assign ie0_5_e_180_wd = reg_wdata[20];
+
+ assign ie0_5_e_181_wd = reg_wdata[21];
+
+ assign ie0_5_e_182_wd = reg_wdata[22];
+
+ assign ie0_5_e_183_wd = reg_wdata[23];
+
+ assign ie0_5_e_184_wd = reg_wdata[24];
+
+ assign ie0_5_e_185_wd = reg_wdata[25];
+
+ assign ie0_5_e_186_wd = reg_wdata[26];
+
+ assign ie0_5_e_187_wd = reg_wdata[27];
+
+ assign ie0_5_e_188_wd = reg_wdata[28];
+
+ assign ie0_5_e_189_wd = reg_wdata[29];
+ assign ie1_0_we = addr_hit[202] & reg_we & !reg_error;
+
+ assign ie1_0_e_0_wd = reg_wdata[0];
+
+ assign ie1_0_e_1_wd = reg_wdata[1];
+
+ assign ie1_0_e_2_wd = reg_wdata[2];
+
+ assign ie1_0_e_3_wd = reg_wdata[3];
+
+ assign ie1_0_e_4_wd = reg_wdata[4];
+
+ assign ie1_0_e_5_wd = reg_wdata[5];
+
+ assign ie1_0_e_6_wd = reg_wdata[6];
+
+ assign ie1_0_e_7_wd = reg_wdata[7];
+
+ assign ie1_0_e_8_wd = reg_wdata[8];
+
+ assign ie1_0_e_9_wd = reg_wdata[9];
+
+ assign ie1_0_e_10_wd = reg_wdata[10];
+
+ assign ie1_0_e_11_wd = reg_wdata[11];
+
+ assign ie1_0_e_12_wd = reg_wdata[12];
+
+ assign ie1_0_e_13_wd = reg_wdata[13];
+
+ assign ie1_0_e_14_wd = reg_wdata[14];
+
+ assign ie1_0_e_15_wd = reg_wdata[15];
+
+ assign ie1_0_e_16_wd = reg_wdata[16];
+
+ assign ie1_0_e_17_wd = reg_wdata[17];
+
+ assign ie1_0_e_18_wd = reg_wdata[18];
+
+ assign ie1_0_e_19_wd = reg_wdata[19];
+
+ assign ie1_0_e_20_wd = reg_wdata[20];
+
+ assign ie1_0_e_21_wd = reg_wdata[21];
+
+ assign ie1_0_e_22_wd = reg_wdata[22];
+
+ assign ie1_0_e_23_wd = reg_wdata[23];
+
+ assign ie1_0_e_24_wd = reg_wdata[24];
+
+ assign ie1_0_e_25_wd = reg_wdata[25];
+
+ assign ie1_0_e_26_wd = reg_wdata[26];
+
+ assign ie1_0_e_27_wd = reg_wdata[27];
+
+ assign ie1_0_e_28_wd = reg_wdata[28];
+
+ assign ie1_0_e_29_wd = reg_wdata[29];
+
+ assign ie1_0_e_30_wd = reg_wdata[30];
+
+ assign ie1_0_e_31_wd = reg_wdata[31];
+ assign ie1_1_we = addr_hit[203] & reg_we & !reg_error;
+
+ assign ie1_1_e_32_wd = reg_wdata[0];
+
+ assign ie1_1_e_33_wd = reg_wdata[1];
+
+ assign ie1_1_e_34_wd = reg_wdata[2];
+
+ assign ie1_1_e_35_wd = reg_wdata[3];
+
+ assign ie1_1_e_36_wd = reg_wdata[4];
+
+ assign ie1_1_e_37_wd = reg_wdata[5];
+
+ assign ie1_1_e_38_wd = reg_wdata[6];
+
+ assign ie1_1_e_39_wd = reg_wdata[7];
+
+ assign ie1_1_e_40_wd = reg_wdata[8];
+
+ assign ie1_1_e_41_wd = reg_wdata[9];
+
+ assign ie1_1_e_42_wd = reg_wdata[10];
+
+ assign ie1_1_e_43_wd = reg_wdata[11];
+
+ assign ie1_1_e_44_wd = reg_wdata[12];
+
+ assign ie1_1_e_45_wd = reg_wdata[13];
+
+ assign ie1_1_e_46_wd = reg_wdata[14];
+
+ assign ie1_1_e_47_wd = reg_wdata[15];
+
+ assign ie1_1_e_48_wd = reg_wdata[16];
+
+ assign ie1_1_e_49_wd = reg_wdata[17];
+
+ assign ie1_1_e_50_wd = reg_wdata[18];
+
+ assign ie1_1_e_51_wd = reg_wdata[19];
+
+ assign ie1_1_e_52_wd = reg_wdata[20];
+
+ assign ie1_1_e_53_wd = reg_wdata[21];
+
+ assign ie1_1_e_54_wd = reg_wdata[22];
+
+ assign ie1_1_e_55_wd = reg_wdata[23];
+
+ assign ie1_1_e_56_wd = reg_wdata[24];
+
+ assign ie1_1_e_57_wd = reg_wdata[25];
+
+ assign ie1_1_e_58_wd = reg_wdata[26];
+
+ assign ie1_1_e_59_wd = reg_wdata[27];
+
+ assign ie1_1_e_60_wd = reg_wdata[28];
+
+ assign ie1_1_e_61_wd = reg_wdata[29];
+
+ assign ie1_1_e_62_wd = reg_wdata[30];
+
+ assign ie1_1_e_63_wd = reg_wdata[31];
+ assign ie1_2_we = addr_hit[204] & reg_we & !reg_error;
+
+ assign ie1_2_e_64_wd = reg_wdata[0];
+
+ assign ie1_2_e_65_wd = reg_wdata[1];
+
+ assign ie1_2_e_66_wd = reg_wdata[2];
+
+ assign ie1_2_e_67_wd = reg_wdata[3];
+
+ assign ie1_2_e_68_wd = reg_wdata[4];
+
+ assign ie1_2_e_69_wd = reg_wdata[5];
+
+ assign ie1_2_e_70_wd = reg_wdata[6];
+
+ assign ie1_2_e_71_wd = reg_wdata[7];
+
+ assign ie1_2_e_72_wd = reg_wdata[8];
+
+ assign ie1_2_e_73_wd = reg_wdata[9];
+
+ assign ie1_2_e_74_wd = reg_wdata[10];
+
+ assign ie1_2_e_75_wd = reg_wdata[11];
+
+ assign ie1_2_e_76_wd = reg_wdata[12];
+
+ assign ie1_2_e_77_wd = reg_wdata[13];
+
+ assign ie1_2_e_78_wd = reg_wdata[14];
+
+ assign ie1_2_e_79_wd = reg_wdata[15];
+
+ assign ie1_2_e_80_wd = reg_wdata[16];
+
+ assign ie1_2_e_81_wd = reg_wdata[17];
+
+ assign ie1_2_e_82_wd = reg_wdata[18];
+
+ assign ie1_2_e_83_wd = reg_wdata[19];
+
+ assign ie1_2_e_84_wd = reg_wdata[20];
+
+ assign ie1_2_e_85_wd = reg_wdata[21];
+
+ assign ie1_2_e_86_wd = reg_wdata[22];
+
+ assign ie1_2_e_87_wd = reg_wdata[23];
+
+ assign ie1_2_e_88_wd = reg_wdata[24];
+
+ assign ie1_2_e_89_wd = reg_wdata[25];
+
+ assign ie1_2_e_90_wd = reg_wdata[26];
+
+ assign ie1_2_e_91_wd = reg_wdata[27];
+
+ assign ie1_2_e_92_wd = reg_wdata[28];
+
+ assign ie1_2_e_93_wd = reg_wdata[29];
+
+ assign ie1_2_e_94_wd = reg_wdata[30];
+
+ assign ie1_2_e_95_wd = reg_wdata[31];
+ assign ie1_3_we = addr_hit[205] & reg_we & !reg_error;
+
+ assign ie1_3_e_96_wd = reg_wdata[0];
+
+ assign ie1_3_e_97_wd = reg_wdata[1];
+
+ assign ie1_3_e_98_wd = reg_wdata[2];
+
+ assign ie1_3_e_99_wd = reg_wdata[3];
+
+ assign ie1_3_e_100_wd = reg_wdata[4];
+
+ assign ie1_3_e_101_wd = reg_wdata[5];
+
+ assign ie1_3_e_102_wd = reg_wdata[6];
+
+ assign ie1_3_e_103_wd = reg_wdata[7];
+
+ assign ie1_3_e_104_wd = reg_wdata[8];
+
+ assign ie1_3_e_105_wd = reg_wdata[9];
+
+ assign ie1_3_e_106_wd = reg_wdata[10];
+
+ assign ie1_3_e_107_wd = reg_wdata[11];
+
+ assign ie1_3_e_108_wd = reg_wdata[12];
+
+ assign ie1_3_e_109_wd = reg_wdata[13];
+
+ assign ie1_3_e_110_wd = reg_wdata[14];
+
+ assign ie1_3_e_111_wd = reg_wdata[15];
+
+ assign ie1_3_e_112_wd = reg_wdata[16];
+
+ assign ie1_3_e_113_wd = reg_wdata[17];
+
+ assign ie1_3_e_114_wd = reg_wdata[18];
+
+ assign ie1_3_e_115_wd = reg_wdata[19];
+
+ assign ie1_3_e_116_wd = reg_wdata[20];
+
+ assign ie1_3_e_117_wd = reg_wdata[21];
+
+ assign ie1_3_e_118_wd = reg_wdata[22];
+
+ assign ie1_3_e_119_wd = reg_wdata[23];
+
+ assign ie1_3_e_120_wd = reg_wdata[24];
+
+ assign ie1_3_e_121_wd = reg_wdata[25];
+
+ assign ie1_3_e_122_wd = reg_wdata[26];
+
+ assign ie1_3_e_123_wd = reg_wdata[27];
+
+ assign ie1_3_e_124_wd = reg_wdata[28];
+
+ assign ie1_3_e_125_wd = reg_wdata[29];
+
+ assign ie1_3_e_126_wd = reg_wdata[30];
+
+ assign ie1_3_e_127_wd = reg_wdata[31];
+ assign ie1_4_we = addr_hit[206] & reg_we & !reg_error;
+
+ assign ie1_4_e_128_wd = reg_wdata[0];
+
+ assign ie1_4_e_129_wd = reg_wdata[1];
+
+ assign ie1_4_e_130_wd = reg_wdata[2];
+
+ assign ie1_4_e_131_wd = reg_wdata[3];
+
+ assign ie1_4_e_132_wd = reg_wdata[4];
+
+ assign ie1_4_e_133_wd = reg_wdata[5];
+
+ assign ie1_4_e_134_wd = reg_wdata[6];
+
+ assign ie1_4_e_135_wd = reg_wdata[7];
+
+ assign ie1_4_e_136_wd = reg_wdata[8];
+
+ assign ie1_4_e_137_wd = reg_wdata[9];
+
+ assign ie1_4_e_138_wd = reg_wdata[10];
+
+ assign ie1_4_e_139_wd = reg_wdata[11];
+
+ assign ie1_4_e_140_wd = reg_wdata[12];
+
+ assign ie1_4_e_141_wd = reg_wdata[13];
+
+ assign ie1_4_e_142_wd = reg_wdata[14];
+
+ assign ie1_4_e_143_wd = reg_wdata[15];
+
+ assign ie1_4_e_144_wd = reg_wdata[16];
+
+ assign ie1_4_e_145_wd = reg_wdata[17];
+
+ assign ie1_4_e_146_wd = reg_wdata[18];
+
+ assign ie1_4_e_147_wd = reg_wdata[19];
+
+ assign ie1_4_e_148_wd = reg_wdata[20];
+
+ assign ie1_4_e_149_wd = reg_wdata[21];
+
+ assign ie1_4_e_150_wd = reg_wdata[22];
+
+ assign ie1_4_e_151_wd = reg_wdata[23];
+
+ assign ie1_4_e_152_wd = reg_wdata[24];
+
+ assign ie1_4_e_153_wd = reg_wdata[25];
+
+ assign ie1_4_e_154_wd = reg_wdata[26];
+
+ assign ie1_4_e_155_wd = reg_wdata[27];
+
+ assign ie1_4_e_156_wd = reg_wdata[28];
+
+ assign ie1_4_e_157_wd = reg_wdata[29];
+
+ assign ie1_4_e_158_wd = reg_wdata[30];
+
+ assign ie1_4_e_159_wd = reg_wdata[31];
+ assign ie1_5_we = addr_hit[207] & reg_we & !reg_error;
+
+ assign ie1_5_e_160_wd = reg_wdata[0];
+
+ assign ie1_5_e_161_wd = reg_wdata[1];
+
+ assign ie1_5_e_162_wd = reg_wdata[2];
+
+ assign ie1_5_e_163_wd = reg_wdata[3];
+
+ assign ie1_5_e_164_wd = reg_wdata[4];
+
+ assign ie1_5_e_165_wd = reg_wdata[5];
+
+ assign ie1_5_e_166_wd = reg_wdata[6];
+
+ assign ie1_5_e_167_wd = reg_wdata[7];
+
+ assign ie1_5_e_168_wd = reg_wdata[8];
+
+ assign ie1_5_e_169_wd = reg_wdata[9];
+
+ assign ie1_5_e_170_wd = reg_wdata[10];
+
+ assign ie1_5_e_171_wd = reg_wdata[11];
+
+ assign ie1_5_e_172_wd = reg_wdata[12];
+
+ assign ie1_5_e_173_wd = reg_wdata[13];
+
+ assign ie1_5_e_174_wd = reg_wdata[14];
+
+ assign ie1_5_e_175_wd = reg_wdata[15];
+
+ assign ie1_5_e_176_wd = reg_wdata[16];
+
+ assign ie1_5_e_177_wd = reg_wdata[17];
+
+ assign ie1_5_e_178_wd = reg_wdata[18];
+
+ assign ie1_5_e_179_wd = reg_wdata[19];
+
+ assign ie1_5_e_180_wd = reg_wdata[20];
+
+ assign ie1_5_e_181_wd = reg_wdata[21];
+
+ assign ie1_5_e_182_wd = reg_wdata[22];
+
+ assign ie1_5_e_183_wd = reg_wdata[23];
+
+ assign ie1_5_e_184_wd = reg_wdata[24];
+
+ assign ie1_5_e_185_wd = reg_wdata[25];
+
+ assign ie1_5_e_186_wd = reg_wdata[26];
+
+ assign ie1_5_e_187_wd = reg_wdata[27];
+
+ assign ie1_5_e_188_wd = reg_wdata[28];
+
+ assign ie1_5_e_189_wd = reg_wdata[29];
+ assign threshold0_we = addr_hit[208] & reg_we & !reg_error;
+
+ assign threshold0_wd = reg_wdata[1:0];
+ assign cc0_re = addr_hit[209] & reg_re & !reg_error;
+ assign cc0_we = addr_hit[209] & reg_we & !reg_error;
+
+ assign cc0_wd = reg_wdata[7:0];
+ assign threshold1_we = addr_hit[210] & reg_we & !reg_error;
+
+ assign threshold1_wd = reg_wdata[1:0];
+ assign cc1_re = addr_hit[211] & reg_re & !reg_error;
+ assign cc1_we = addr_hit[211] & reg_we & !reg_error;
+
+ assign cc1_wd = reg_wdata[7:0];
+ assign msip0_we = addr_hit[212] & reg_we & !reg_error;
+
+ assign msip0_wd = reg_wdata[0];
+ assign msip1_we = addr_hit[213] & reg_we & !reg_error;
+
+ assign msip1_wd = reg_wdata[0];
+ assign alert_test_we = addr_hit[214] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = prio0_we;
+ reg_we_check[1] = prio1_we;
+ reg_we_check[2] = prio2_we;
+ reg_we_check[3] = prio3_we;
+ reg_we_check[4] = prio4_we;
+ reg_we_check[5] = prio5_we;
+ reg_we_check[6] = prio6_we;
+ reg_we_check[7] = prio7_we;
+ reg_we_check[8] = prio8_we;
+ reg_we_check[9] = prio9_we;
+ reg_we_check[10] = prio10_we;
+ reg_we_check[11] = prio11_we;
+ reg_we_check[12] = prio12_we;
+ reg_we_check[13] = prio13_we;
+ reg_we_check[14] = prio14_we;
+ reg_we_check[15] = prio15_we;
+ reg_we_check[16] = prio16_we;
+ reg_we_check[17] = prio17_we;
+ reg_we_check[18] = prio18_we;
+ reg_we_check[19] = prio19_we;
+ reg_we_check[20] = prio20_we;
+ reg_we_check[21] = prio21_we;
+ reg_we_check[22] = prio22_we;
+ reg_we_check[23] = prio23_we;
+ reg_we_check[24] = prio24_we;
+ reg_we_check[25] = prio25_we;
+ reg_we_check[26] = prio26_we;
+ reg_we_check[27] = prio27_we;
+ reg_we_check[28] = prio28_we;
+ reg_we_check[29] = prio29_we;
+ reg_we_check[30] = prio30_we;
+ reg_we_check[31] = prio31_we;
+ reg_we_check[32] = prio32_we;
+ reg_we_check[33] = prio33_we;
+ reg_we_check[34] = prio34_we;
+ reg_we_check[35] = prio35_we;
+ reg_we_check[36] = prio36_we;
+ reg_we_check[37] = prio37_we;
+ reg_we_check[38] = prio38_we;
+ reg_we_check[39] = prio39_we;
+ reg_we_check[40] = prio40_we;
+ reg_we_check[41] = prio41_we;
+ reg_we_check[42] = prio42_we;
+ reg_we_check[43] = prio43_we;
+ reg_we_check[44] = prio44_we;
+ reg_we_check[45] = prio45_we;
+ reg_we_check[46] = prio46_we;
+ reg_we_check[47] = prio47_we;
+ reg_we_check[48] = prio48_we;
+ reg_we_check[49] = prio49_we;
+ reg_we_check[50] = prio50_we;
+ reg_we_check[51] = prio51_we;
+ reg_we_check[52] = prio52_we;
+ reg_we_check[53] = prio53_we;
+ reg_we_check[54] = prio54_we;
+ reg_we_check[55] = prio55_we;
+ reg_we_check[56] = prio56_we;
+ reg_we_check[57] = prio57_we;
+ reg_we_check[58] = prio58_we;
+ reg_we_check[59] = prio59_we;
+ reg_we_check[60] = prio60_we;
+ reg_we_check[61] = prio61_we;
+ reg_we_check[62] = prio62_we;
+ reg_we_check[63] = prio63_we;
+ reg_we_check[64] = prio64_we;
+ reg_we_check[65] = prio65_we;
+ reg_we_check[66] = prio66_we;
+ reg_we_check[67] = prio67_we;
+ reg_we_check[68] = prio68_we;
+ reg_we_check[69] = prio69_we;
+ reg_we_check[70] = prio70_we;
+ reg_we_check[71] = prio71_we;
+ reg_we_check[72] = prio72_we;
+ reg_we_check[73] = prio73_we;
+ reg_we_check[74] = prio74_we;
+ reg_we_check[75] = prio75_we;
+ reg_we_check[76] = prio76_we;
+ reg_we_check[77] = prio77_we;
+ reg_we_check[78] = prio78_we;
+ reg_we_check[79] = prio79_we;
+ reg_we_check[80] = prio80_we;
+ reg_we_check[81] = prio81_we;
+ reg_we_check[82] = prio82_we;
+ reg_we_check[83] = prio83_we;
+ reg_we_check[84] = prio84_we;
+ reg_we_check[85] = prio85_we;
+ reg_we_check[86] = prio86_we;
+ reg_we_check[87] = prio87_we;
+ reg_we_check[88] = prio88_we;
+ reg_we_check[89] = prio89_we;
+ reg_we_check[90] = prio90_we;
+ reg_we_check[91] = prio91_we;
+ reg_we_check[92] = prio92_we;
+ reg_we_check[93] = prio93_we;
+ reg_we_check[94] = prio94_we;
+ reg_we_check[95] = prio95_we;
+ reg_we_check[96] = prio96_we;
+ reg_we_check[97] = prio97_we;
+ reg_we_check[98] = prio98_we;
+ reg_we_check[99] = prio99_we;
+ reg_we_check[100] = prio100_we;
+ reg_we_check[101] = prio101_we;
+ reg_we_check[102] = prio102_we;
+ reg_we_check[103] = prio103_we;
+ reg_we_check[104] = prio104_we;
+ reg_we_check[105] = prio105_we;
+ reg_we_check[106] = prio106_we;
+ reg_we_check[107] = prio107_we;
+ reg_we_check[108] = prio108_we;
+ reg_we_check[109] = prio109_we;
+ reg_we_check[110] = prio110_we;
+ reg_we_check[111] = prio111_we;
+ reg_we_check[112] = prio112_we;
+ reg_we_check[113] = prio113_we;
+ reg_we_check[114] = prio114_we;
+ reg_we_check[115] = prio115_we;
+ reg_we_check[116] = prio116_we;
+ reg_we_check[117] = prio117_we;
+ reg_we_check[118] = prio118_we;
+ reg_we_check[119] = prio119_we;
+ reg_we_check[120] = prio120_we;
+ reg_we_check[121] = prio121_we;
+ reg_we_check[122] = prio122_we;
+ reg_we_check[123] = prio123_we;
+ reg_we_check[124] = prio124_we;
+ reg_we_check[125] = prio125_we;
+ reg_we_check[126] = prio126_we;
+ reg_we_check[127] = prio127_we;
+ reg_we_check[128] = prio128_we;
+ reg_we_check[129] = prio129_we;
+ reg_we_check[130] = prio130_we;
+ reg_we_check[131] = prio131_we;
+ reg_we_check[132] = prio132_we;
+ reg_we_check[133] = prio133_we;
+ reg_we_check[134] = prio134_we;
+ reg_we_check[135] = prio135_we;
+ reg_we_check[136] = prio136_we;
+ reg_we_check[137] = prio137_we;
+ reg_we_check[138] = prio138_we;
+ reg_we_check[139] = prio139_we;
+ reg_we_check[140] = prio140_we;
+ reg_we_check[141] = prio141_we;
+ reg_we_check[142] = prio142_we;
+ reg_we_check[143] = prio143_we;
+ reg_we_check[144] = prio144_we;
+ reg_we_check[145] = prio145_we;
+ reg_we_check[146] = prio146_we;
+ reg_we_check[147] = prio147_we;
+ reg_we_check[148] = prio148_we;
+ reg_we_check[149] = prio149_we;
+ reg_we_check[150] = prio150_we;
+ reg_we_check[151] = prio151_we;
+ reg_we_check[152] = prio152_we;
+ reg_we_check[153] = prio153_we;
+ reg_we_check[154] = prio154_we;
+ reg_we_check[155] = prio155_we;
+ reg_we_check[156] = prio156_we;
+ reg_we_check[157] = prio157_we;
+ reg_we_check[158] = prio158_we;
+ reg_we_check[159] = prio159_we;
+ reg_we_check[160] = prio160_we;
+ reg_we_check[161] = prio161_we;
+ reg_we_check[162] = prio162_we;
+ reg_we_check[163] = prio163_we;
+ reg_we_check[164] = prio164_we;
+ reg_we_check[165] = prio165_we;
+ reg_we_check[166] = prio166_we;
+ reg_we_check[167] = prio167_we;
+ reg_we_check[168] = prio168_we;
+ reg_we_check[169] = prio169_we;
+ reg_we_check[170] = prio170_we;
+ reg_we_check[171] = prio171_we;
+ reg_we_check[172] = prio172_we;
+ reg_we_check[173] = prio173_we;
+ reg_we_check[174] = prio174_we;
+ reg_we_check[175] = prio175_we;
+ reg_we_check[176] = prio176_we;
+ reg_we_check[177] = prio177_we;
+ reg_we_check[178] = prio178_we;
+ reg_we_check[179] = prio179_we;
+ reg_we_check[180] = prio180_we;
+ reg_we_check[181] = prio181_we;
+ reg_we_check[182] = prio182_we;
+ reg_we_check[183] = prio183_we;
+ reg_we_check[184] = prio184_we;
+ reg_we_check[185] = prio185_we;
+ reg_we_check[186] = prio186_we;
+ reg_we_check[187] = prio187_we;
+ reg_we_check[188] = prio188_we;
+ reg_we_check[189] = prio189_we;
+ reg_we_check[190] = 1'b0;
+ reg_we_check[191] = 1'b0;
+ reg_we_check[192] = 1'b0;
+ reg_we_check[193] = 1'b0;
+ reg_we_check[194] = 1'b0;
+ reg_we_check[195] = 1'b0;
+ reg_we_check[196] = ie0_0_we;
+ reg_we_check[197] = ie0_1_we;
+ reg_we_check[198] = ie0_2_we;
+ reg_we_check[199] = ie0_3_we;
+ reg_we_check[200] = ie0_4_we;
+ reg_we_check[201] = ie0_5_we;
+ reg_we_check[202] = ie1_0_we;
+ reg_we_check[203] = ie1_1_we;
+ reg_we_check[204] = ie1_2_we;
+ reg_we_check[205] = ie1_3_we;
+ reg_we_check[206] = ie1_4_we;
+ reg_we_check[207] = ie1_5_we;
+ reg_we_check[208] = threshold0_we;
+ reg_we_check[209] = cc0_we;
+ reg_we_check[210] = threshold1_we;
+ reg_we_check[211] = cc1_we;
+ reg_we_check[212] = msip0_we;
+ reg_we_check[213] = msip1_we;
+ reg_we_check[214] = alert_test_we;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[1:0] = prio0_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[1:0] = prio1_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[1:0] = prio2_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[1:0] = prio3_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[1:0] = prio4_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[1:0] = prio5_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[1:0] = prio6_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[1:0] = prio7_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[1:0] = prio8_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[1:0] = prio9_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[1:0] = prio10_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[1:0] = prio11_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[1:0] = prio12_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[1:0] = prio13_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[1:0] = prio14_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[1:0] = prio15_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[1:0] = prio16_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[1:0] = prio17_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[1:0] = prio18_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[1:0] = prio19_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[1:0] = prio20_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[1:0] = prio21_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[1:0] = prio22_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[1:0] = prio23_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[1:0] = prio24_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[1:0] = prio25_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[1:0] = prio26_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[1:0] = prio27_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[1:0] = prio28_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[1:0] = prio29_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[1:0] = prio30_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[1:0] = prio31_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[1:0] = prio32_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[1:0] = prio33_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[1:0] = prio34_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[1:0] = prio35_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[1:0] = prio36_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[1:0] = prio37_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[1:0] = prio38_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[1:0] = prio39_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[1:0] = prio40_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[1:0] = prio41_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[1:0] = prio42_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[1:0] = prio43_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[1:0] = prio44_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[1:0] = prio45_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[1:0] = prio46_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[1:0] = prio47_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[1:0] = prio48_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[1:0] = prio49_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[1:0] = prio50_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[1:0] = prio51_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[1:0] = prio52_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[1:0] = prio53_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[1:0] = prio54_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[1:0] = prio55_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[1:0] = prio56_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[1:0] = prio57_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[1:0] = prio58_qs;
+ end
+
+ addr_hit[59]: begin
+ reg_rdata_next[1:0] = prio59_qs;
+ end
+
+ addr_hit[60]: begin
+ reg_rdata_next[1:0] = prio60_qs;
+ end
+
+ addr_hit[61]: begin
+ reg_rdata_next[1:0] = prio61_qs;
+ end
+
+ addr_hit[62]: begin
+ reg_rdata_next[1:0] = prio62_qs;
+ end
+
+ addr_hit[63]: begin
+ reg_rdata_next[1:0] = prio63_qs;
+ end
+
+ addr_hit[64]: begin
+ reg_rdata_next[1:0] = prio64_qs;
+ end
+
+ addr_hit[65]: begin
+ reg_rdata_next[1:0] = prio65_qs;
+ end
+
+ addr_hit[66]: begin
+ reg_rdata_next[1:0] = prio66_qs;
+ end
+
+ addr_hit[67]: begin
+ reg_rdata_next[1:0] = prio67_qs;
+ end
+
+ addr_hit[68]: begin
+ reg_rdata_next[1:0] = prio68_qs;
+ end
+
+ addr_hit[69]: begin
+ reg_rdata_next[1:0] = prio69_qs;
+ end
+
+ addr_hit[70]: begin
+ reg_rdata_next[1:0] = prio70_qs;
+ end
+
+ addr_hit[71]: begin
+ reg_rdata_next[1:0] = prio71_qs;
+ end
+
+ addr_hit[72]: begin
+ reg_rdata_next[1:0] = prio72_qs;
+ end
+
+ addr_hit[73]: begin
+ reg_rdata_next[1:0] = prio73_qs;
+ end
+
+ addr_hit[74]: begin
+ reg_rdata_next[1:0] = prio74_qs;
+ end
+
+ addr_hit[75]: begin
+ reg_rdata_next[1:0] = prio75_qs;
+ end
+
+ addr_hit[76]: begin
+ reg_rdata_next[1:0] = prio76_qs;
+ end
+
+ addr_hit[77]: begin
+ reg_rdata_next[1:0] = prio77_qs;
+ end
+
+ addr_hit[78]: begin
+ reg_rdata_next[1:0] = prio78_qs;
+ end
+
+ addr_hit[79]: begin
+ reg_rdata_next[1:0] = prio79_qs;
+ end
+
+ addr_hit[80]: begin
+ reg_rdata_next[1:0] = prio80_qs;
+ end
+
+ addr_hit[81]: begin
+ reg_rdata_next[1:0] = prio81_qs;
+ end
+
+ addr_hit[82]: begin
+ reg_rdata_next[1:0] = prio82_qs;
+ end
+
+ addr_hit[83]: begin
+ reg_rdata_next[1:0] = prio83_qs;
+ end
+
+ addr_hit[84]: begin
+ reg_rdata_next[1:0] = prio84_qs;
+ end
+
+ addr_hit[85]: begin
+ reg_rdata_next[1:0] = prio85_qs;
+ end
+
+ addr_hit[86]: begin
+ reg_rdata_next[1:0] = prio86_qs;
+ end
+
+ addr_hit[87]: begin
+ reg_rdata_next[1:0] = prio87_qs;
+ end
+
+ addr_hit[88]: begin
+ reg_rdata_next[1:0] = prio88_qs;
+ end
+
+ addr_hit[89]: begin
+ reg_rdata_next[1:0] = prio89_qs;
+ end
+
+ addr_hit[90]: begin
+ reg_rdata_next[1:0] = prio90_qs;
+ end
+
+ addr_hit[91]: begin
+ reg_rdata_next[1:0] = prio91_qs;
+ end
+
+ addr_hit[92]: begin
+ reg_rdata_next[1:0] = prio92_qs;
+ end
+
+ addr_hit[93]: begin
+ reg_rdata_next[1:0] = prio93_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[1:0] = prio94_qs;
+ end
+
+ addr_hit[95]: begin
+ reg_rdata_next[1:0] = prio95_qs;
+ end
+
+ addr_hit[96]: begin
+ reg_rdata_next[1:0] = prio96_qs;
+ end
+
+ addr_hit[97]: begin
+ reg_rdata_next[1:0] = prio97_qs;
+ end
+
+ addr_hit[98]: begin
+ reg_rdata_next[1:0] = prio98_qs;
+ end
+
+ addr_hit[99]: begin
+ reg_rdata_next[1:0] = prio99_qs;
+ end
+
+ addr_hit[100]: begin
+ reg_rdata_next[1:0] = prio100_qs;
+ end
+
+ addr_hit[101]: begin
+ reg_rdata_next[1:0] = prio101_qs;
+ end
+
+ addr_hit[102]: begin
+ reg_rdata_next[1:0] = prio102_qs;
+ end
+
+ addr_hit[103]: begin
+ reg_rdata_next[1:0] = prio103_qs;
+ end
+
+ addr_hit[104]: begin
+ reg_rdata_next[1:0] = prio104_qs;
+ end
+
+ addr_hit[105]: begin
+ reg_rdata_next[1:0] = prio105_qs;
+ end
+
+ addr_hit[106]: begin
+ reg_rdata_next[1:0] = prio106_qs;
+ end
+
+ addr_hit[107]: begin
+ reg_rdata_next[1:0] = prio107_qs;
+ end
+
+ addr_hit[108]: begin
+ reg_rdata_next[1:0] = prio108_qs;
+ end
+
+ addr_hit[109]: begin
+ reg_rdata_next[1:0] = prio109_qs;
+ end
+
+ addr_hit[110]: begin
+ reg_rdata_next[1:0] = prio110_qs;
+ end
+
+ addr_hit[111]: begin
+ reg_rdata_next[1:0] = prio111_qs;
+ end
+
+ addr_hit[112]: begin
+ reg_rdata_next[1:0] = prio112_qs;
+ end
+
+ addr_hit[113]: begin
+ reg_rdata_next[1:0] = prio113_qs;
+ end
+
+ addr_hit[114]: begin
+ reg_rdata_next[1:0] = prio114_qs;
+ end
+
+ addr_hit[115]: begin
+ reg_rdata_next[1:0] = prio115_qs;
+ end
+
+ addr_hit[116]: begin
+ reg_rdata_next[1:0] = prio116_qs;
+ end
+
+ addr_hit[117]: begin
+ reg_rdata_next[1:0] = prio117_qs;
+ end
+
+ addr_hit[118]: begin
+ reg_rdata_next[1:0] = prio118_qs;
+ end
+
+ addr_hit[119]: begin
+ reg_rdata_next[1:0] = prio119_qs;
+ end
+
+ addr_hit[120]: begin
+ reg_rdata_next[1:0] = prio120_qs;
+ end
+
+ addr_hit[121]: begin
+ reg_rdata_next[1:0] = prio121_qs;
+ end
+
+ addr_hit[122]: begin
+ reg_rdata_next[1:0] = prio122_qs;
+ end
+
+ addr_hit[123]: begin
+ reg_rdata_next[1:0] = prio123_qs;
+ end
+
+ addr_hit[124]: begin
+ reg_rdata_next[1:0] = prio124_qs;
+ end
+
+ addr_hit[125]: begin
+ reg_rdata_next[1:0] = prio125_qs;
+ end
+
+ addr_hit[126]: begin
+ reg_rdata_next[1:0] = prio126_qs;
+ end
+
+ addr_hit[127]: begin
+ reg_rdata_next[1:0] = prio127_qs;
+ end
+
+ addr_hit[128]: begin
+ reg_rdata_next[1:0] = prio128_qs;
+ end
+
+ addr_hit[129]: begin
+ reg_rdata_next[1:0] = prio129_qs;
+ end
+
+ addr_hit[130]: begin
+ reg_rdata_next[1:0] = prio130_qs;
+ end
+
+ addr_hit[131]: begin
+ reg_rdata_next[1:0] = prio131_qs;
+ end
+
+ addr_hit[132]: begin
+ reg_rdata_next[1:0] = prio132_qs;
+ end
+
+ addr_hit[133]: begin
+ reg_rdata_next[1:0] = prio133_qs;
+ end
+
+ addr_hit[134]: begin
+ reg_rdata_next[1:0] = prio134_qs;
+ end
+
+ addr_hit[135]: begin
+ reg_rdata_next[1:0] = prio135_qs;
+ end
+
+ addr_hit[136]: begin
+ reg_rdata_next[1:0] = prio136_qs;
+ end
+
+ addr_hit[137]: begin
+ reg_rdata_next[1:0] = prio137_qs;
+ end
+
+ addr_hit[138]: begin
+ reg_rdata_next[1:0] = prio138_qs;
+ end
+
+ addr_hit[139]: begin
+ reg_rdata_next[1:0] = prio139_qs;
+ end
+
+ addr_hit[140]: begin
+ reg_rdata_next[1:0] = prio140_qs;
+ end
+
+ addr_hit[141]: begin
+ reg_rdata_next[1:0] = prio141_qs;
+ end
+
+ addr_hit[142]: begin
+ reg_rdata_next[1:0] = prio142_qs;
+ end
+
+ addr_hit[143]: begin
+ reg_rdata_next[1:0] = prio143_qs;
+ end
+
+ addr_hit[144]: begin
+ reg_rdata_next[1:0] = prio144_qs;
+ end
+
+ addr_hit[145]: begin
+ reg_rdata_next[1:0] = prio145_qs;
+ end
+
+ addr_hit[146]: begin
+ reg_rdata_next[1:0] = prio146_qs;
+ end
+
+ addr_hit[147]: begin
+ reg_rdata_next[1:0] = prio147_qs;
+ end
+
+ addr_hit[148]: begin
+ reg_rdata_next[1:0] = prio148_qs;
+ end
+
+ addr_hit[149]: begin
+ reg_rdata_next[1:0] = prio149_qs;
+ end
+
+ addr_hit[150]: begin
+ reg_rdata_next[1:0] = prio150_qs;
+ end
+
+ addr_hit[151]: begin
+ reg_rdata_next[1:0] = prio151_qs;
+ end
+
+ addr_hit[152]: begin
+ reg_rdata_next[1:0] = prio152_qs;
+ end
+
+ addr_hit[153]: begin
+ reg_rdata_next[1:0] = prio153_qs;
+ end
+
+ addr_hit[154]: begin
+ reg_rdata_next[1:0] = prio154_qs;
+ end
+
+ addr_hit[155]: begin
+ reg_rdata_next[1:0] = prio155_qs;
+ end
+
+ addr_hit[156]: begin
+ reg_rdata_next[1:0] = prio156_qs;
+ end
+
+ addr_hit[157]: begin
+ reg_rdata_next[1:0] = prio157_qs;
+ end
+
+ addr_hit[158]: begin
+ reg_rdata_next[1:0] = prio158_qs;
+ end
+
+ addr_hit[159]: begin
+ reg_rdata_next[1:0] = prio159_qs;
+ end
+
+ addr_hit[160]: begin
+ reg_rdata_next[1:0] = prio160_qs;
+ end
+
+ addr_hit[161]: begin
+ reg_rdata_next[1:0] = prio161_qs;
+ end
+
+ addr_hit[162]: begin
+ reg_rdata_next[1:0] = prio162_qs;
+ end
+
+ addr_hit[163]: begin
+ reg_rdata_next[1:0] = prio163_qs;
+ end
+
+ addr_hit[164]: begin
+ reg_rdata_next[1:0] = prio164_qs;
+ end
+
+ addr_hit[165]: begin
+ reg_rdata_next[1:0] = prio165_qs;
+ end
+
+ addr_hit[166]: begin
+ reg_rdata_next[1:0] = prio166_qs;
+ end
+
+ addr_hit[167]: begin
+ reg_rdata_next[1:0] = prio167_qs;
+ end
+
+ addr_hit[168]: begin
+ reg_rdata_next[1:0] = prio168_qs;
+ end
+
+ addr_hit[169]: begin
+ reg_rdata_next[1:0] = prio169_qs;
+ end
+
+ addr_hit[170]: begin
+ reg_rdata_next[1:0] = prio170_qs;
+ end
+
+ addr_hit[171]: begin
+ reg_rdata_next[1:0] = prio171_qs;
+ end
+
+ addr_hit[172]: begin
+ reg_rdata_next[1:0] = prio172_qs;
+ end
+
+ addr_hit[173]: begin
+ reg_rdata_next[1:0] = prio173_qs;
+ end
+
+ addr_hit[174]: begin
+ reg_rdata_next[1:0] = prio174_qs;
+ end
+
+ addr_hit[175]: begin
+ reg_rdata_next[1:0] = prio175_qs;
+ end
+
+ addr_hit[176]: begin
+ reg_rdata_next[1:0] = prio176_qs;
+ end
+
+ addr_hit[177]: begin
+ reg_rdata_next[1:0] = prio177_qs;
+ end
+
+ addr_hit[178]: begin
+ reg_rdata_next[1:0] = prio178_qs;
+ end
+
+ addr_hit[179]: begin
+ reg_rdata_next[1:0] = prio179_qs;
+ end
+
+ addr_hit[180]: begin
+ reg_rdata_next[1:0] = prio180_qs;
+ end
+
+ addr_hit[181]: begin
+ reg_rdata_next[1:0] = prio181_qs;
+ end
+
+ addr_hit[182]: begin
+ reg_rdata_next[1:0] = prio182_qs;
+ end
+
+ addr_hit[183]: begin
+ reg_rdata_next[1:0] = prio183_qs;
+ end
+
+ addr_hit[184]: begin
+ reg_rdata_next[1:0] = prio184_qs;
+ end
+
+ addr_hit[185]: begin
+ reg_rdata_next[1:0] = prio185_qs;
+ end
+
+ addr_hit[186]: begin
+ reg_rdata_next[1:0] = prio186_qs;
+ end
+
+ addr_hit[187]: begin
+ reg_rdata_next[1:0] = prio187_qs;
+ end
+
+ addr_hit[188]: begin
+ reg_rdata_next[1:0] = prio188_qs;
+ end
+
+ addr_hit[189]: begin
+ reg_rdata_next[1:0] = prio189_qs;
+ end
+
+ addr_hit[190]: begin
+ reg_rdata_next[0] = ip_0_p_0_qs;
+ reg_rdata_next[1] = ip_0_p_1_qs;
+ reg_rdata_next[2] = ip_0_p_2_qs;
+ reg_rdata_next[3] = ip_0_p_3_qs;
+ reg_rdata_next[4] = ip_0_p_4_qs;
+ reg_rdata_next[5] = ip_0_p_5_qs;
+ reg_rdata_next[6] = ip_0_p_6_qs;
+ reg_rdata_next[7] = ip_0_p_7_qs;
+ reg_rdata_next[8] = ip_0_p_8_qs;
+ reg_rdata_next[9] = ip_0_p_9_qs;
+ reg_rdata_next[10] = ip_0_p_10_qs;
+ reg_rdata_next[11] = ip_0_p_11_qs;
+ reg_rdata_next[12] = ip_0_p_12_qs;
+ reg_rdata_next[13] = ip_0_p_13_qs;
+ reg_rdata_next[14] = ip_0_p_14_qs;
+ reg_rdata_next[15] = ip_0_p_15_qs;
+ reg_rdata_next[16] = ip_0_p_16_qs;
+ reg_rdata_next[17] = ip_0_p_17_qs;
+ reg_rdata_next[18] = ip_0_p_18_qs;
+ reg_rdata_next[19] = ip_0_p_19_qs;
+ reg_rdata_next[20] = ip_0_p_20_qs;
+ reg_rdata_next[21] = ip_0_p_21_qs;
+ reg_rdata_next[22] = ip_0_p_22_qs;
+ reg_rdata_next[23] = ip_0_p_23_qs;
+ reg_rdata_next[24] = ip_0_p_24_qs;
+ reg_rdata_next[25] = ip_0_p_25_qs;
+ reg_rdata_next[26] = ip_0_p_26_qs;
+ reg_rdata_next[27] = ip_0_p_27_qs;
+ reg_rdata_next[28] = ip_0_p_28_qs;
+ reg_rdata_next[29] = ip_0_p_29_qs;
+ reg_rdata_next[30] = ip_0_p_30_qs;
+ reg_rdata_next[31] = ip_0_p_31_qs;
+ end
+
+ addr_hit[191]: begin
+ reg_rdata_next[0] = ip_1_p_32_qs;
+ reg_rdata_next[1] = ip_1_p_33_qs;
+ reg_rdata_next[2] = ip_1_p_34_qs;
+ reg_rdata_next[3] = ip_1_p_35_qs;
+ reg_rdata_next[4] = ip_1_p_36_qs;
+ reg_rdata_next[5] = ip_1_p_37_qs;
+ reg_rdata_next[6] = ip_1_p_38_qs;
+ reg_rdata_next[7] = ip_1_p_39_qs;
+ reg_rdata_next[8] = ip_1_p_40_qs;
+ reg_rdata_next[9] = ip_1_p_41_qs;
+ reg_rdata_next[10] = ip_1_p_42_qs;
+ reg_rdata_next[11] = ip_1_p_43_qs;
+ reg_rdata_next[12] = ip_1_p_44_qs;
+ reg_rdata_next[13] = ip_1_p_45_qs;
+ reg_rdata_next[14] = ip_1_p_46_qs;
+ reg_rdata_next[15] = ip_1_p_47_qs;
+ reg_rdata_next[16] = ip_1_p_48_qs;
+ reg_rdata_next[17] = ip_1_p_49_qs;
+ reg_rdata_next[18] = ip_1_p_50_qs;
+ reg_rdata_next[19] = ip_1_p_51_qs;
+ reg_rdata_next[20] = ip_1_p_52_qs;
+ reg_rdata_next[21] = ip_1_p_53_qs;
+ reg_rdata_next[22] = ip_1_p_54_qs;
+ reg_rdata_next[23] = ip_1_p_55_qs;
+ reg_rdata_next[24] = ip_1_p_56_qs;
+ reg_rdata_next[25] = ip_1_p_57_qs;
+ reg_rdata_next[26] = ip_1_p_58_qs;
+ reg_rdata_next[27] = ip_1_p_59_qs;
+ reg_rdata_next[28] = ip_1_p_60_qs;
+ reg_rdata_next[29] = ip_1_p_61_qs;
+ reg_rdata_next[30] = ip_1_p_62_qs;
+ reg_rdata_next[31] = ip_1_p_63_qs;
+ end
+
+ addr_hit[192]: begin
+ reg_rdata_next[0] = ip_2_p_64_qs;
+ reg_rdata_next[1] = ip_2_p_65_qs;
+ reg_rdata_next[2] = ip_2_p_66_qs;
+ reg_rdata_next[3] = ip_2_p_67_qs;
+ reg_rdata_next[4] = ip_2_p_68_qs;
+ reg_rdata_next[5] = ip_2_p_69_qs;
+ reg_rdata_next[6] = ip_2_p_70_qs;
+ reg_rdata_next[7] = ip_2_p_71_qs;
+ reg_rdata_next[8] = ip_2_p_72_qs;
+ reg_rdata_next[9] = ip_2_p_73_qs;
+ reg_rdata_next[10] = ip_2_p_74_qs;
+ reg_rdata_next[11] = ip_2_p_75_qs;
+ reg_rdata_next[12] = ip_2_p_76_qs;
+ reg_rdata_next[13] = ip_2_p_77_qs;
+ reg_rdata_next[14] = ip_2_p_78_qs;
+ reg_rdata_next[15] = ip_2_p_79_qs;
+ reg_rdata_next[16] = ip_2_p_80_qs;
+ reg_rdata_next[17] = ip_2_p_81_qs;
+ reg_rdata_next[18] = ip_2_p_82_qs;
+ reg_rdata_next[19] = ip_2_p_83_qs;
+ reg_rdata_next[20] = ip_2_p_84_qs;
+ reg_rdata_next[21] = ip_2_p_85_qs;
+ reg_rdata_next[22] = ip_2_p_86_qs;
+ reg_rdata_next[23] = ip_2_p_87_qs;
+ reg_rdata_next[24] = ip_2_p_88_qs;
+ reg_rdata_next[25] = ip_2_p_89_qs;
+ reg_rdata_next[26] = ip_2_p_90_qs;
+ reg_rdata_next[27] = ip_2_p_91_qs;
+ reg_rdata_next[28] = ip_2_p_92_qs;
+ reg_rdata_next[29] = ip_2_p_93_qs;
+ reg_rdata_next[30] = ip_2_p_94_qs;
+ reg_rdata_next[31] = ip_2_p_95_qs;
+ end
+
+ addr_hit[193]: begin
+ reg_rdata_next[0] = ip_3_p_96_qs;
+ reg_rdata_next[1] = ip_3_p_97_qs;
+ reg_rdata_next[2] = ip_3_p_98_qs;
+ reg_rdata_next[3] = ip_3_p_99_qs;
+ reg_rdata_next[4] = ip_3_p_100_qs;
+ reg_rdata_next[5] = ip_3_p_101_qs;
+ reg_rdata_next[6] = ip_3_p_102_qs;
+ reg_rdata_next[7] = ip_3_p_103_qs;
+ reg_rdata_next[8] = ip_3_p_104_qs;
+ reg_rdata_next[9] = ip_3_p_105_qs;
+ reg_rdata_next[10] = ip_3_p_106_qs;
+ reg_rdata_next[11] = ip_3_p_107_qs;
+ reg_rdata_next[12] = ip_3_p_108_qs;
+ reg_rdata_next[13] = ip_3_p_109_qs;
+ reg_rdata_next[14] = ip_3_p_110_qs;
+ reg_rdata_next[15] = ip_3_p_111_qs;
+ reg_rdata_next[16] = ip_3_p_112_qs;
+ reg_rdata_next[17] = ip_3_p_113_qs;
+ reg_rdata_next[18] = ip_3_p_114_qs;
+ reg_rdata_next[19] = ip_3_p_115_qs;
+ reg_rdata_next[20] = ip_3_p_116_qs;
+ reg_rdata_next[21] = ip_3_p_117_qs;
+ reg_rdata_next[22] = ip_3_p_118_qs;
+ reg_rdata_next[23] = ip_3_p_119_qs;
+ reg_rdata_next[24] = ip_3_p_120_qs;
+ reg_rdata_next[25] = ip_3_p_121_qs;
+ reg_rdata_next[26] = ip_3_p_122_qs;
+ reg_rdata_next[27] = ip_3_p_123_qs;
+ reg_rdata_next[28] = ip_3_p_124_qs;
+ reg_rdata_next[29] = ip_3_p_125_qs;
+ reg_rdata_next[30] = ip_3_p_126_qs;
+ reg_rdata_next[31] = ip_3_p_127_qs;
+ end
+
+ addr_hit[194]: begin
+ reg_rdata_next[0] = ip_4_p_128_qs;
+ reg_rdata_next[1] = ip_4_p_129_qs;
+ reg_rdata_next[2] = ip_4_p_130_qs;
+ reg_rdata_next[3] = ip_4_p_131_qs;
+ reg_rdata_next[4] = ip_4_p_132_qs;
+ reg_rdata_next[5] = ip_4_p_133_qs;
+ reg_rdata_next[6] = ip_4_p_134_qs;
+ reg_rdata_next[7] = ip_4_p_135_qs;
+ reg_rdata_next[8] = ip_4_p_136_qs;
+ reg_rdata_next[9] = ip_4_p_137_qs;
+ reg_rdata_next[10] = ip_4_p_138_qs;
+ reg_rdata_next[11] = ip_4_p_139_qs;
+ reg_rdata_next[12] = ip_4_p_140_qs;
+ reg_rdata_next[13] = ip_4_p_141_qs;
+ reg_rdata_next[14] = ip_4_p_142_qs;
+ reg_rdata_next[15] = ip_4_p_143_qs;
+ reg_rdata_next[16] = ip_4_p_144_qs;
+ reg_rdata_next[17] = ip_4_p_145_qs;
+ reg_rdata_next[18] = ip_4_p_146_qs;
+ reg_rdata_next[19] = ip_4_p_147_qs;
+ reg_rdata_next[20] = ip_4_p_148_qs;
+ reg_rdata_next[21] = ip_4_p_149_qs;
+ reg_rdata_next[22] = ip_4_p_150_qs;
+ reg_rdata_next[23] = ip_4_p_151_qs;
+ reg_rdata_next[24] = ip_4_p_152_qs;
+ reg_rdata_next[25] = ip_4_p_153_qs;
+ reg_rdata_next[26] = ip_4_p_154_qs;
+ reg_rdata_next[27] = ip_4_p_155_qs;
+ reg_rdata_next[28] = ip_4_p_156_qs;
+ reg_rdata_next[29] = ip_4_p_157_qs;
+ reg_rdata_next[30] = ip_4_p_158_qs;
+ reg_rdata_next[31] = ip_4_p_159_qs;
+ end
+
+ addr_hit[195]: begin
+ reg_rdata_next[0] = ip_5_p_160_qs;
+ reg_rdata_next[1] = ip_5_p_161_qs;
+ reg_rdata_next[2] = ip_5_p_162_qs;
+ reg_rdata_next[3] = ip_5_p_163_qs;
+ reg_rdata_next[4] = ip_5_p_164_qs;
+ reg_rdata_next[5] = ip_5_p_165_qs;
+ reg_rdata_next[6] = ip_5_p_166_qs;
+ reg_rdata_next[7] = ip_5_p_167_qs;
+ reg_rdata_next[8] = ip_5_p_168_qs;
+ reg_rdata_next[9] = ip_5_p_169_qs;
+ reg_rdata_next[10] = ip_5_p_170_qs;
+ reg_rdata_next[11] = ip_5_p_171_qs;
+ reg_rdata_next[12] = ip_5_p_172_qs;
+ reg_rdata_next[13] = ip_5_p_173_qs;
+ reg_rdata_next[14] = ip_5_p_174_qs;
+ reg_rdata_next[15] = ip_5_p_175_qs;
+ reg_rdata_next[16] = ip_5_p_176_qs;
+ reg_rdata_next[17] = ip_5_p_177_qs;
+ reg_rdata_next[18] = ip_5_p_178_qs;
+ reg_rdata_next[19] = ip_5_p_179_qs;
+ reg_rdata_next[20] = ip_5_p_180_qs;
+ reg_rdata_next[21] = ip_5_p_181_qs;
+ reg_rdata_next[22] = ip_5_p_182_qs;
+ reg_rdata_next[23] = ip_5_p_183_qs;
+ reg_rdata_next[24] = ip_5_p_184_qs;
+ reg_rdata_next[25] = ip_5_p_185_qs;
+ reg_rdata_next[26] = ip_5_p_186_qs;
+ reg_rdata_next[27] = ip_5_p_187_qs;
+ reg_rdata_next[28] = ip_5_p_188_qs;
+ reg_rdata_next[29] = ip_5_p_189_qs;
+ end
+
+ addr_hit[196]: begin
+ reg_rdata_next[0] = ie0_0_e_0_qs;
+ reg_rdata_next[1] = ie0_0_e_1_qs;
+ reg_rdata_next[2] = ie0_0_e_2_qs;
+ reg_rdata_next[3] = ie0_0_e_3_qs;
+ reg_rdata_next[4] = ie0_0_e_4_qs;
+ reg_rdata_next[5] = ie0_0_e_5_qs;
+ reg_rdata_next[6] = ie0_0_e_6_qs;
+ reg_rdata_next[7] = ie0_0_e_7_qs;
+ reg_rdata_next[8] = ie0_0_e_8_qs;
+ reg_rdata_next[9] = ie0_0_e_9_qs;
+ reg_rdata_next[10] = ie0_0_e_10_qs;
+ reg_rdata_next[11] = ie0_0_e_11_qs;
+ reg_rdata_next[12] = ie0_0_e_12_qs;
+ reg_rdata_next[13] = ie0_0_e_13_qs;
+ reg_rdata_next[14] = ie0_0_e_14_qs;
+ reg_rdata_next[15] = ie0_0_e_15_qs;
+ reg_rdata_next[16] = ie0_0_e_16_qs;
+ reg_rdata_next[17] = ie0_0_e_17_qs;
+ reg_rdata_next[18] = ie0_0_e_18_qs;
+ reg_rdata_next[19] = ie0_0_e_19_qs;
+ reg_rdata_next[20] = ie0_0_e_20_qs;
+ reg_rdata_next[21] = ie0_0_e_21_qs;
+ reg_rdata_next[22] = ie0_0_e_22_qs;
+ reg_rdata_next[23] = ie0_0_e_23_qs;
+ reg_rdata_next[24] = ie0_0_e_24_qs;
+ reg_rdata_next[25] = ie0_0_e_25_qs;
+ reg_rdata_next[26] = ie0_0_e_26_qs;
+ reg_rdata_next[27] = ie0_0_e_27_qs;
+ reg_rdata_next[28] = ie0_0_e_28_qs;
+ reg_rdata_next[29] = ie0_0_e_29_qs;
+ reg_rdata_next[30] = ie0_0_e_30_qs;
+ reg_rdata_next[31] = ie0_0_e_31_qs;
+ end
+
+ addr_hit[197]: begin
+ reg_rdata_next[0] = ie0_1_e_32_qs;
+ reg_rdata_next[1] = ie0_1_e_33_qs;
+ reg_rdata_next[2] = ie0_1_e_34_qs;
+ reg_rdata_next[3] = ie0_1_e_35_qs;
+ reg_rdata_next[4] = ie0_1_e_36_qs;
+ reg_rdata_next[5] = ie0_1_e_37_qs;
+ reg_rdata_next[6] = ie0_1_e_38_qs;
+ reg_rdata_next[7] = ie0_1_e_39_qs;
+ reg_rdata_next[8] = ie0_1_e_40_qs;
+ reg_rdata_next[9] = ie0_1_e_41_qs;
+ reg_rdata_next[10] = ie0_1_e_42_qs;
+ reg_rdata_next[11] = ie0_1_e_43_qs;
+ reg_rdata_next[12] = ie0_1_e_44_qs;
+ reg_rdata_next[13] = ie0_1_e_45_qs;
+ reg_rdata_next[14] = ie0_1_e_46_qs;
+ reg_rdata_next[15] = ie0_1_e_47_qs;
+ reg_rdata_next[16] = ie0_1_e_48_qs;
+ reg_rdata_next[17] = ie0_1_e_49_qs;
+ reg_rdata_next[18] = ie0_1_e_50_qs;
+ reg_rdata_next[19] = ie0_1_e_51_qs;
+ reg_rdata_next[20] = ie0_1_e_52_qs;
+ reg_rdata_next[21] = ie0_1_e_53_qs;
+ reg_rdata_next[22] = ie0_1_e_54_qs;
+ reg_rdata_next[23] = ie0_1_e_55_qs;
+ reg_rdata_next[24] = ie0_1_e_56_qs;
+ reg_rdata_next[25] = ie0_1_e_57_qs;
+ reg_rdata_next[26] = ie0_1_e_58_qs;
+ reg_rdata_next[27] = ie0_1_e_59_qs;
+ reg_rdata_next[28] = ie0_1_e_60_qs;
+ reg_rdata_next[29] = ie0_1_e_61_qs;
+ reg_rdata_next[30] = ie0_1_e_62_qs;
+ reg_rdata_next[31] = ie0_1_e_63_qs;
+ end
+
+ addr_hit[198]: begin
+ reg_rdata_next[0] = ie0_2_e_64_qs;
+ reg_rdata_next[1] = ie0_2_e_65_qs;
+ reg_rdata_next[2] = ie0_2_e_66_qs;
+ reg_rdata_next[3] = ie0_2_e_67_qs;
+ reg_rdata_next[4] = ie0_2_e_68_qs;
+ reg_rdata_next[5] = ie0_2_e_69_qs;
+ reg_rdata_next[6] = ie0_2_e_70_qs;
+ reg_rdata_next[7] = ie0_2_e_71_qs;
+ reg_rdata_next[8] = ie0_2_e_72_qs;
+ reg_rdata_next[9] = ie0_2_e_73_qs;
+ reg_rdata_next[10] = ie0_2_e_74_qs;
+ reg_rdata_next[11] = ie0_2_e_75_qs;
+ reg_rdata_next[12] = ie0_2_e_76_qs;
+ reg_rdata_next[13] = ie0_2_e_77_qs;
+ reg_rdata_next[14] = ie0_2_e_78_qs;
+ reg_rdata_next[15] = ie0_2_e_79_qs;
+ reg_rdata_next[16] = ie0_2_e_80_qs;
+ reg_rdata_next[17] = ie0_2_e_81_qs;
+ reg_rdata_next[18] = ie0_2_e_82_qs;
+ reg_rdata_next[19] = ie0_2_e_83_qs;
+ reg_rdata_next[20] = ie0_2_e_84_qs;
+ reg_rdata_next[21] = ie0_2_e_85_qs;
+ reg_rdata_next[22] = ie0_2_e_86_qs;
+ reg_rdata_next[23] = ie0_2_e_87_qs;
+ reg_rdata_next[24] = ie0_2_e_88_qs;
+ reg_rdata_next[25] = ie0_2_e_89_qs;
+ reg_rdata_next[26] = ie0_2_e_90_qs;
+ reg_rdata_next[27] = ie0_2_e_91_qs;
+ reg_rdata_next[28] = ie0_2_e_92_qs;
+ reg_rdata_next[29] = ie0_2_e_93_qs;
+ reg_rdata_next[30] = ie0_2_e_94_qs;
+ reg_rdata_next[31] = ie0_2_e_95_qs;
+ end
+
+ addr_hit[199]: begin
+ reg_rdata_next[0] = ie0_3_e_96_qs;
+ reg_rdata_next[1] = ie0_3_e_97_qs;
+ reg_rdata_next[2] = ie0_3_e_98_qs;
+ reg_rdata_next[3] = ie0_3_e_99_qs;
+ reg_rdata_next[4] = ie0_3_e_100_qs;
+ reg_rdata_next[5] = ie0_3_e_101_qs;
+ reg_rdata_next[6] = ie0_3_e_102_qs;
+ reg_rdata_next[7] = ie0_3_e_103_qs;
+ reg_rdata_next[8] = ie0_3_e_104_qs;
+ reg_rdata_next[9] = ie0_3_e_105_qs;
+ reg_rdata_next[10] = ie0_3_e_106_qs;
+ reg_rdata_next[11] = ie0_3_e_107_qs;
+ reg_rdata_next[12] = ie0_3_e_108_qs;
+ reg_rdata_next[13] = ie0_3_e_109_qs;
+ reg_rdata_next[14] = ie0_3_e_110_qs;
+ reg_rdata_next[15] = ie0_3_e_111_qs;
+ reg_rdata_next[16] = ie0_3_e_112_qs;
+ reg_rdata_next[17] = ie0_3_e_113_qs;
+ reg_rdata_next[18] = ie0_3_e_114_qs;
+ reg_rdata_next[19] = ie0_3_e_115_qs;
+ reg_rdata_next[20] = ie0_3_e_116_qs;
+ reg_rdata_next[21] = ie0_3_e_117_qs;
+ reg_rdata_next[22] = ie0_3_e_118_qs;
+ reg_rdata_next[23] = ie0_3_e_119_qs;
+ reg_rdata_next[24] = ie0_3_e_120_qs;
+ reg_rdata_next[25] = ie0_3_e_121_qs;
+ reg_rdata_next[26] = ie0_3_e_122_qs;
+ reg_rdata_next[27] = ie0_3_e_123_qs;
+ reg_rdata_next[28] = ie0_3_e_124_qs;
+ reg_rdata_next[29] = ie0_3_e_125_qs;
+ reg_rdata_next[30] = ie0_3_e_126_qs;
+ reg_rdata_next[31] = ie0_3_e_127_qs;
+ end
+
+ addr_hit[200]: begin
+ reg_rdata_next[0] = ie0_4_e_128_qs;
+ reg_rdata_next[1] = ie0_4_e_129_qs;
+ reg_rdata_next[2] = ie0_4_e_130_qs;
+ reg_rdata_next[3] = ie0_4_e_131_qs;
+ reg_rdata_next[4] = ie0_4_e_132_qs;
+ reg_rdata_next[5] = ie0_4_e_133_qs;
+ reg_rdata_next[6] = ie0_4_e_134_qs;
+ reg_rdata_next[7] = ie0_4_e_135_qs;
+ reg_rdata_next[8] = ie0_4_e_136_qs;
+ reg_rdata_next[9] = ie0_4_e_137_qs;
+ reg_rdata_next[10] = ie0_4_e_138_qs;
+ reg_rdata_next[11] = ie0_4_e_139_qs;
+ reg_rdata_next[12] = ie0_4_e_140_qs;
+ reg_rdata_next[13] = ie0_4_e_141_qs;
+ reg_rdata_next[14] = ie0_4_e_142_qs;
+ reg_rdata_next[15] = ie0_4_e_143_qs;
+ reg_rdata_next[16] = ie0_4_e_144_qs;
+ reg_rdata_next[17] = ie0_4_e_145_qs;
+ reg_rdata_next[18] = ie0_4_e_146_qs;
+ reg_rdata_next[19] = ie0_4_e_147_qs;
+ reg_rdata_next[20] = ie0_4_e_148_qs;
+ reg_rdata_next[21] = ie0_4_e_149_qs;
+ reg_rdata_next[22] = ie0_4_e_150_qs;
+ reg_rdata_next[23] = ie0_4_e_151_qs;
+ reg_rdata_next[24] = ie0_4_e_152_qs;
+ reg_rdata_next[25] = ie0_4_e_153_qs;
+ reg_rdata_next[26] = ie0_4_e_154_qs;
+ reg_rdata_next[27] = ie0_4_e_155_qs;
+ reg_rdata_next[28] = ie0_4_e_156_qs;
+ reg_rdata_next[29] = ie0_4_e_157_qs;
+ reg_rdata_next[30] = ie0_4_e_158_qs;
+ reg_rdata_next[31] = ie0_4_e_159_qs;
+ end
+
+ addr_hit[201]: begin
+ reg_rdata_next[0] = ie0_5_e_160_qs;
+ reg_rdata_next[1] = ie0_5_e_161_qs;
+ reg_rdata_next[2] = ie0_5_e_162_qs;
+ reg_rdata_next[3] = ie0_5_e_163_qs;
+ reg_rdata_next[4] = ie0_5_e_164_qs;
+ reg_rdata_next[5] = ie0_5_e_165_qs;
+ reg_rdata_next[6] = ie0_5_e_166_qs;
+ reg_rdata_next[7] = ie0_5_e_167_qs;
+ reg_rdata_next[8] = ie0_5_e_168_qs;
+ reg_rdata_next[9] = ie0_5_e_169_qs;
+ reg_rdata_next[10] = ie0_5_e_170_qs;
+ reg_rdata_next[11] = ie0_5_e_171_qs;
+ reg_rdata_next[12] = ie0_5_e_172_qs;
+ reg_rdata_next[13] = ie0_5_e_173_qs;
+ reg_rdata_next[14] = ie0_5_e_174_qs;
+ reg_rdata_next[15] = ie0_5_e_175_qs;
+ reg_rdata_next[16] = ie0_5_e_176_qs;
+ reg_rdata_next[17] = ie0_5_e_177_qs;
+ reg_rdata_next[18] = ie0_5_e_178_qs;
+ reg_rdata_next[19] = ie0_5_e_179_qs;
+ reg_rdata_next[20] = ie0_5_e_180_qs;
+ reg_rdata_next[21] = ie0_5_e_181_qs;
+ reg_rdata_next[22] = ie0_5_e_182_qs;
+ reg_rdata_next[23] = ie0_5_e_183_qs;
+ reg_rdata_next[24] = ie0_5_e_184_qs;
+ reg_rdata_next[25] = ie0_5_e_185_qs;
+ reg_rdata_next[26] = ie0_5_e_186_qs;
+ reg_rdata_next[27] = ie0_5_e_187_qs;
+ reg_rdata_next[28] = ie0_5_e_188_qs;
+ reg_rdata_next[29] = ie0_5_e_189_qs;
+ end
+
+ addr_hit[202]: begin
+ reg_rdata_next[0] = ie1_0_e_0_qs;
+ reg_rdata_next[1] = ie1_0_e_1_qs;
+ reg_rdata_next[2] = ie1_0_e_2_qs;
+ reg_rdata_next[3] = ie1_0_e_3_qs;
+ reg_rdata_next[4] = ie1_0_e_4_qs;
+ reg_rdata_next[5] = ie1_0_e_5_qs;
+ reg_rdata_next[6] = ie1_0_e_6_qs;
+ reg_rdata_next[7] = ie1_0_e_7_qs;
+ reg_rdata_next[8] = ie1_0_e_8_qs;
+ reg_rdata_next[9] = ie1_0_e_9_qs;
+ reg_rdata_next[10] = ie1_0_e_10_qs;
+ reg_rdata_next[11] = ie1_0_e_11_qs;
+ reg_rdata_next[12] = ie1_0_e_12_qs;
+ reg_rdata_next[13] = ie1_0_e_13_qs;
+ reg_rdata_next[14] = ie1_0_e_14_qs;
+ reg_rdata_next[15] = ie1_0_e_15_qs;
+ reg_rdata_next[16] = ie1_0_e_16_qs;
+ reg_rdata_next[17] = ie1_0_e_17_qs;
+ reg_rdata_next[18] = ie1_0_e_18_qs;
+ reg_rdata_next[19] = ie1_0_e_19_qs;
+ reg_rdata_next[20] = ie1_0_e_20_qs;
+ reg_rdata_next[21] = ie1_0_e_21_qs;
+ reg_rdata_next[22] = ie1_0_e_22_qs;
+ reg_rdata_next[23] = ie1_0_e_23_qs;
+ reg_rdata_next[24] = ie1_0_e_24_qs;
+ reg_rdata_next[25] = ie1_0_e_25_qs;
+ reg_rdata_next[26] = ie1_0_e_26_qs;
+ reg_rdata_next[27] = ie1_0_e_27_qs;
+ reg_rdata_next[28] = ie1_0_e_28_qs;
+ reg_rdata_next[29] = ie1_0_e_29_qs;
+ reg_rdata_next[30] = ie1_0_e_30_qs;
+ reg_rdata_next[31] = ie1_0_e_31_qs;
+ end
+
+ addr_hit[203]: begin
+ reg_rdata_next[0] = ie1_1_e_32_qs;
+ reg_rdata_next[1] = ie1_1_e_33_qs;
+ reg_rdata_next[2] = ie1_1_e_34_qs;
+ reg_rdata_next[3] = ie1_1_e_35_qs;
+ reg_rdata_next[4] = ie1_1_e_36_qs;
+ reg_rdata_next[5] = ie1_1_e_37_qs;
+ reg_rdata_next[6] = ie1_1_e_38_qs;
+ reg_rdata_next[7] = ie1_1_e_39_qs;
+ reg_rdata_next[8] = ie1_1_e_40_qs;
+ reg_rdata_next[9] = ie1_1_e_41_qs;
+ reg_rdata_next[10] = ie1_1_e_42_qs;
+ reg_rdata_next[11] = ie1_1_e_43_qs;
+ reg_rdata_next[12] = ie1_1_e_44_qs;
+ reg_rdata_next[13] = ie1_1_e_45_qs;
+ reg_rdata_next[14] = ie1_1_e_46_qs;
+ reg_rdata_next[15] = ie1_1_e_47_qs;
+ reg_rdata_next[16] = ie1_1_e_48_qs;
+ reg_rdata_next[17] = ie1_1_e_49_qs;
+ reg_rdata_next[18] = ie1_1_e_50_qs;
+ reg_rdata_next[19] = ie1_1_e_51_qs;
+ reg_rdata_next[20] = ie1_1_e_52_qs;
+ reg_rdata_next[21] = ie1_1_e_53_qs;
+ reg_rdata_next[22] = ie1_1_e_54_qs;
+ reg_rdata_next[23] = ie1_1_e_55_qs;
+ reg_rdata_next[24] = ie1_1_e_56_qs;
+ reg_rdata_next[25] = ie1_1_e_57_qs;
+ reg_rdata_next[26] = ie1_1_e_58_qs;
+ reg_rdata_next[27] = ie1_1_e_59_qs;
+ reg_rdata_next[28] = ie1_1_e_60_qs;
+ reg_rdata_next[29] = ie1_1_e_61_qs;
+ reg_rdata_next[30] = ie1_1_e_62_qs;
+ reg_rdata_next[31] = ie1_1_e_63_qs;
+ end
+
+ addr_hit[204]: begin
+ reg_rdata_next[0] = ie1_2_e_64_qs;
+ reg_rdata_next[1] = ie1_2_e_65_qs;
+ reg_rdata_next[2] = ie1_2_e_66_qs;
+ reg_rdata_next[3] = ie1_2_e_67_qs;
+ reg_rdata_next[4] = ie1_2_e_68_qs;
+ reg_rdata_next[5] = ie1_2_e_69_qs;
+ reg_rdata_next[6] = ie1_2_e_70_qs;
+ reg_rdata_next[7] = ie1_2_e_71_qs;
+ reg_rdata_next[8] = ie1_2_e_72_qs;
+ reg_rdata_next[9] = ie1_2_e_73_qs;
+ reg_rdata_next[10] = ie1_2_e_74_qs;
+ reg_rdata_next[11] = ie1_2_e_75_qs;
+ reg_rdata_next[12] = ie1_2_e_76_qs;
+ reg_rdata_next[13] = ie1_2_e_77_qs;
+ reg_rdata_next[14] = ie1_2_e_78_qs;
+ reg_rdata_next[15] = ie1_2_e_79_qs;
+ reg_rdata_next[16] = ie1_2_e_80_qs;
+ reg_rdata_next[17] = ie1_2_e_81_qs;
+ reg_rdata_next[18] = ie1_2_e_82_qs;
+ reg_rdata_next[19] = ie1_2_e_83_qs;
+ reg_rdata_next[20] = ie1_2_e_84_qs;
+ reg_rdata_next[21] = ie1_2_e_85_qs;
+ reg_rdata_next[22] = ie1_2_e_86_qs;
+ reg_rdata_next[23] = ie1_2_e_87_qs;
+ reg_rdata_next[24] = ie1_2_e_88_qs;
+ reg_rdata_next[25] = ie1_2_e_89_qs;
+ reg_rdata_next[26] = ie1_2_e_90_qs;
+ reg_rdata_next[27] = ie1_2_e_91_qs;
+ reg_rdata_next[28] = ie1_2_e_92_qs;
+ reg_rdata_next[29] = ie1_2_e_93_qs;
+ reg_rdata_next[30] = ie1_2_e_94_qs;
+ reg_rdata_next[31] = ie1_2_e_95_qs;
+ end
+
+ addr_hit[205]: begin
+ reg_rdata_next[0] = ie1_3_e_96_qs;
+ reg_rdata_next[1] = ie1_3_e_97_qs;
+ reg_rdata_next[2] = ie1_3_e_98_qs;
+ reg_rdata_next[3] = ie1_3_e_99_qs;
+ reg_rdata_next[4] = ie1_3_e_100_qs;
+ reg_rdata_next[5] = ie1_3_e_101_qs;
+ reg_rdata_next[6] = ie1_3_e_102_qs;
+ reg_rdata_next[7] = ie1_3_e_103_qs;
+ reg_rdata_next[8] = ie1_3_e_104_qs;
+ reg_rdata_next[9] = ie1_3_e_105_qs;
+ reg_rdata_next[10] = ie1_3_e_106_qs;
+ reg_rdata_next[11] = ie1_3_e_107_qs;
+ reg_rdata_next[12] = ie1_3_e_108_qs;
+ reg_rdata_next[13] = ie1_3_e_109_qs;
+ reg_rdata_next[14] = ie1_3_e_110_qs;
+ reg_rdata_next[15] = ie1_3_e_111_qs;
+ reg_rdata_next[16] = ie1_3_e_112_qs;
+ reg_rdata_next[17] = ie1_3_e_113_qs;
+ reg_rdata_next[18] = ie1_3_e_114_qs;
+ reg_rdata_next[19] = ie1_3_e_115_qs;
+ reg_rdata_next[20] = ie1_3_e_116_qs;
+ reg_rdata_next[21] = ie1_3_e_117_qs;
+ reg_rdata_next[22] = ie1_3_e_118_qs;
+ reg_rdata_next[23] = ie1_3_e_119_qs;
+ reg_rdata_next[24] = ie1_3_e_120_qs;
+ reg_rdata_next[25] = ie1_3_e_121_qs;
+ reg_rdata_next[26] = ie1_3_e_122_qs;
+ reg_rdata_next[27] = ie1_3_e_123_qs;
+ reg_rdata_next[28] = ie1_3_e_124_qs;
+ reg_rdata_next[29] = ie1_3_e_125_qs;
+ reg_rdata_next[30] = ie1_3_e_126_qs;
+ reg_rdata_next[31] = ie1_3_e_127_qs;
+ end
+
+ addr_hit[206]: begin
+ reg_rdata_next[0] = ie1_4_e_128_qs;
+ reg_rdata_next[1] = ie1_4_e_129_qs;
+ reg_rdata_next[2] = ie1_4_e_130_qs;
+ reg_rdata_next[3] = ie1_4_e_131_qs;
+ reg_rdata_next[4] = ie1_4_e_132_qs;
+ reg_rdata_next[5] = ie1_4_e_133_qs;
+ reg_rdata_next[6] = ie1_4_e_134_qs;
+ reg_rdata_next[7] = ie1_4_e_135_qs;
+ reg_rdata_next[8] = ie1_4_e_136_qs;
+ reg_rdata_next[9] = ie1_4_e_137_qs;
+ reg_rdata_next[10] = ie1_4_e_138_qs;
+ reg_rdata_next[11] = ie1_4_e_139_qs;
+ reg_rdata_next[12] = ie1_4_e_140_qs;
+ reg_rdata_next[13] = ie1_4_e_141_qs;
+ reg_rdata_next[14] = ie1_4_e_142_qs;
+ reg_rdata_next[15] = ie1_4_e_143_qs;
+ reg_rdata_next[16] = ie1_4_e_144_qs;
+ reg_rdata_next[17] = ie1_4_e_145_qs;
+ reg_rdata_next[18] = ie1_4_e_146_qs;
+ reg_rdata_next[19] = ie1_4_e_147_qs;
+ reg_rdata_next[20] = ie1_4_e_148_qs;
+ reg_rdata_next[21] = ie1_4_e_149_qs;
+ reg_rdata_next[22] = ie1_4_e_150_qs;
+ reg_rdata_next[23] = ie1_4_e_151_qs;
+ reg_rdata_next[24] = ie1_4_e_152_qs;
+ reg_rdata_next[25] = ie1_4_e_153_qs;
+ reg_rdata_next[26] = ie1_4_e_154_qs;
+ reg_rdata_next[27] = ie1_4_e_155_qs;
+ reg_rdata_next[28] = ie1_4_e_156_qs;
+ reg_rdata_next[29] = ie1_4_e_157_qs;
+ reg_rdata_next[30] = ie1_4_e_158_qs;
+ reg_rdata_next[31] = ie1_4_e_159_qs;
+ end
+
+ addr_hit[207]: begin
+ reg_rdata_next[0] = ie1_5_e_160_qs;
+ reg_rdata_next[1] = ie1_5_e_161_qs;
+ reg_rdata_next[2] = ie1_5_e_162_qs;
+ reg_rdata_next[3] = ie1_5_e_163_qs;
+ reg_rdata_next[4] = ie1_5_e_164_qs;
+ reg_rdata_next[5] = ie1_5_e_165_qs;
+ reg_rdata_next[6] = ie1_5_e_166_qs;
+ reg_rdata_next[7] = ie1_5_e_167_qs;
+ reg_rdata_next[8] = ie1_5_e_168_qs;
+ reg_rdata_next[9] = ie1_5_e_169_qs;
+ reg_rdata_next[10] = ie1_5_e_170_qs;
+ reg_rdata_next[11] = ie1_5_e_171_qs;
+ reg_rdata_next[12] = ie1_5_e_172_qs;
+ reg_rdata_next[13] = ie1_5_e_173_qs;
+ reg_rdata_next[14] = ie1_5_e_174_qs;
+ reg_rdata_next[15] = ie1_5_e_175_qs;
+ reg_rdata_next[16] = ie1_5_e_176_qs;
+ reg_rdata_next[17] = ie1_5_e_177_qs;
+ reg_rdata_next[18] = ie1_5_e_178_qs;
+ reg_rdata_next[19] = ie1_5_e_179_qs;
+ reg_rdata_next[20] = ie1_5_e_180_qs;
+ reg_rdata_next[21] = ie1_5_e_181_qs;
+ reg_rdata_next[22] = ie1_5_e_182_qs;
+ reg_rdata_next[23] = ie1_5_e_183_qs;
+ reg_rdata_next[24] = ie1_5_e_184_qs;
+ reg_rdata_next[25] = ie1_5_e_185_qs;
+ reg_rdata_next[26] = ie1_5_e_186_qs;
+ reg_rdata_next[27] = ie1_5_e_187_qs;
+ reg_rdata_next[28] = ie1_5_e_188_qs;
+ reg_rdata_next[29] = ie1_5_e_189_qs;
+ end
+
+ addr_hit[208]: begin
+ reg_rdata_next[1:0] = threshold0_qs;
+ end
+
+ addr_hit[209]: begin
+ reg_rdata_next[7:0] = cc0_qs;
+ end
+
+ addr_hit[210]: begin
+ reg_rdata_next[1:0] = threshold1_qs;
+ end
+
+ addr_hit[211]: begin
+ reg_rdata_next[7:0] = cc1_qs;
+ end
+
+ addr_hit[212]: begin
+ reg_rdata_next[0] = msip0_qs;
+ end
+
+ addr_hit[213]: begin
+ reg_rdata_next[0] = msip1_qs;
+ end
+
+ addr_hit[214]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_target.sv b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_target.sv
new file mode 100644
index 0000000..c0c247f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rtl/rv_plic_target.sv
@@ -0,0 +1,74 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Generator for Target
+//
+// This module basically doing IE & IP based on priority and threshold_i.
+// Keep in mind that increasing MAX_PRIO affects logic size a lot.
+//
+// The module implements a binary tree to find the maximal entry. the solution
+// has O(N) area and O(log(N)) delay complexity, and thus scales well with
+// many input sources.
+//
+
+`include "prim_assert.sv"
+
+module rv_plic_target #(
+ parameter int N_SOURCE = 32,
+ parameter int MAX_PRIO = 7,
+
+ // Local param (Do not change this through parameter
+ localparam int SrcWidth = $clog2(N_SOURCE), // derived parameter
+ localparam int PrioWidth = $clog2(MAX_PRIO+1) // derived parameter
+) (
+ input clk_i,
+ input rst_ni,
+
+ input [N_SOURCE-1:0] ip_i,
+ input [N_SOURCE-1:0] ie_i,
+
+ input [N_SOURCE-1:0][PrioWidth-1:0] prio_i,
+ input [PrioWidth-1:0] threshold_i,
+
+ output logic irq_o,
+ output logic [SrcWidth-1:0] irq_id_o
+);
+
+ // Find maximum value and index using a binary tree implementation.
+ logic max_valid;
+ logic [PrioWidth-1:0] max_value;
+ logic [SrcWidth-1:0] max_idx;
+ prim_max_tree #(
+ .NumSrc(N_SOURCE),
+ .Width(PrioWidth)
+ ) u_prim_max_tree (
+ .clk_i,
+ .rst_ni,
+ .values_i(prio_i),
+ .valid_i(ip_i & ie_i),
+ .max_value_o(max_value),
+ .max_idx_o(max_idx),
+ .max_valid_o(max_valid)
+ );
+
+ logic irq_d, irq_q;
+ logic [SrcWidth-1:0] irq_id_d, irq_id_q;
+
+ assign irq_d = (max_value > threshold_i) ? max_valid : 1'b0;
+ assign irq_id_d = (max_valid) ? max_idx : '0;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : gen_regs
+ if (!rst_ni) begin
+ irq_q <= 1'b0;
+ irq_id_q <= '0;
+ end else begin
+ irq_q <= irq_d;
+ irq_id_q <= irq_id_d;
+ end
+ end
+
+ assign irq_o = irq_q;
+ assign irq_id_o = irq_id_q;
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rv_plic.core b/hw/top_sencha/ip_autogen/rv_plic/rv_plic.core
new file mode 100644
index 0000000..de2e954
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rv_plic.core
@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_rv_plic
+description: "RISC-V Platform Interrupt Controller (PLIC)"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:rv_plic_component
+ - lowrisc:ip:tlul
+ - lowrisc:prim:subreg
+ files:
+ - rtl/rv_plic_reg_pkg.sv
+ - rtl/rv_plic_reg_top.sv
+ - rtl/rv_plic.sv
+ file_type: systemVerilogSource
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: rv_plic
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip_autogen/rv_plic/rv_plic_component.core b/hw/top_sencha/ip_autogen/rv_plic/rv_plic_component.core
new file mode 100644
index 0000000..8eee97f
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic/rv_plic_component.core
@@ -0,0 +1,51 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:rv_plic_component:0.1"
+description: "RISC-V Platform Interrupt Controller (PLIC)"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:alert
+ - lowrisc:prim:max_tree
+ - lowrisc:prim:flop_2sync
+ - lowrisc:prim:reg_we_check
+ files:
+ - rtl/rv_plic_gateway.sv
+ - rtl/rv_plic_target.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/rv_plic.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/rv_plic.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/README.md b/hw/top_sencha/ip_autogen/rv_plic_smc/README.md
new file mode 100644
index 0000000..d642009
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/README.md
@@ -0,0 +1,247 @@
+# Interrupt Controller Technical Specification
+
+# Overview
+
+This document specifies the Interrupt Controller (RV_PLIC) functionality. This
+module conforms to the
+[Comportable guideline for peripheral functionality](../../../doc/contributing/hw/comportability/README.md).
+See that document for integration overview within the broader top level system.
+
+
+## Features
+
+- RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller
+- Support arbitrary number of interrupt vectors (up to 255) and targets
+- Support interrupt enable, interrupt status registers
+- Memory-mapped MSIP register per HART for software interrupt control.
+
+## Description
+
+The RV_PLIC module is designed to manage various interrupt sources from the
+peripherals. It receives interrupt events as either edge or level of the
+incoming interrupt signals (``intr_src_i``) and can notify multiple targets.
+
+## Compatibility
+
+The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
+
+# Theory of Operations
+
+## Block Diagram
+
+
+
+## Hardware Interfaces
+
+* [Interface Tables](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
+
+## Design Details
+
+### Identifier
+
+Each interrupt source has a unique ID assigned based upon its bit position
+within the input `intr_src_i`. ID ranges from 0 to N, the number of interrupt
+sources. ID 0 is reserved and represents no interrupt. The bit 0 of
+`intr_src_i` shall be tied to 0 from the outside of RV_PLIC. The
+`intr_src_i[i]` bit has an ID of `i`. This ID is used when targets "claim" the
+interrupt and to "complete" the interrupt event.
+
+### Priority and Threshold
+
+Interrupt sources have configurable priority values. The maximum value of the
+priority is configurable through the localparam `MAX_PRIO` in the rv_plic
+top-level module. For each target there is a threshold value ([`THRESHOLD0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#threshold0) for
+target 0). RV_PLIC notifies a target of an interrupt only if it's priority is
+strictly greater than the target's threshold. Note this means an interrupt with
+a priority is 0 is effectively prevented from causing an interrupt at any target
+and a target can suppress all interrupts by setting it's threshold to the max
+priority value.
+
+`MAX_PRIO` parameter is most area contributing option in RV_PLIC. If `MAX_PRIO`
+is big, then finding the highest priority in Process module may consume a lot of
+logic gates.
+
+### Interrupt Gateways
+
+The Gateway observes incoming interrupt sources and converts them to a common
+interrupt format used internally by RV_PLIC. It can be parameterized to detect
+interrupts events on an edge (when the signal changes from **0** to **1**) or
+level basis (where the signal remains at **1**).
+The choice is a system-integration decision and can be configured via the design parameter `LevelEdgeTrig` for each interrupt request.
+
+When the gateway detects an interrupt event it raises the interrupt pending bit
+([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the
+relevant bit of [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) will not be reasserted until the
+target signals completion of the interrupt. Any new interrupt event between a
+bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular
+this means that for edge triggered interrupts if a new edge is seen after the
+source's [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored
+(counting missed edges as discussed in the RISC-V PLIC specification is not
+supported).
+
+Note that there is no ability for a level triggered interrupt to be cancelled.
+If the interrupt drops after the gateway has set a bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip), the bit will
+remain set until the interrupt is completed. The SW handler should be conscious
+of this and check the interrupt still requires handling in the handler if this
+behaviour is possible.
+
+### Interrupt Enables
+
+Each target has a set of Interrupt Enable ([`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) for target 0) registers. Each
+bit in the [`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an
+interrupt source is disabled for a target, then interrupt events from that
+source won't trigger an interrupt at the target. RV_PLIC doesn't have a global
+interrupt disable feature.
+
+### Interrupt Claims
+
+"Claiming" an interrupt is done by a target reading the associated
+Claim/Completion register for the target ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The return value
+of the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the
+highest priority. If two or more pending interrupts have the same priority,
+RV_PLIC chooses the one with lowest ID. Only interrupts that that are enabled
+for the target can be claimed. The target priority threshold doesn't matter
+(this only factors into whether an interrupt is signalled to the target) so
+lower priority interrupt IDs can be returned on a read from [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0). If no
+interrupt is pending (or all pending interrupts are disabled for the target) a
+read of [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) returns an ID of 0.
+
+### Interrupt Completion
+
+After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) is
+cleared, regardless of the status of the `intr_src_i` input value. Until a
+target "completes" the interrupt, it won't be re-asserted if a new event for the
+interrupt occurs. A target completes the interrupt by writing the ID of the
+interrupt to the Claim/Complete register ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The write event
+is forwarded to the Gateway logic, which resets the interrupt status to accept a
+new interrupt event. The assumption is that the processor has cleaned up the
+originating interrupt event during the time between claim and complete such that
+`intr_src_i[ID]` will have de-asserted (unless a new interrupt has occurred).
+
+```wavejson
+{ signal: [
+ { name: 'clk', wave: 'p...........' },
+ { name: 'intr_src_i[i]', wave: '01....0.1...', node:'.a....e.f...'},
+ { name: 'irq_o', wave: '0.1.0......1', node:'..b.d......h'},
+ { name: 'irq_id_o', wave: '=.=.=......=',
+ data: ["0","i","0","i"] },
+ { name: 'claim', wave: '0..10.......', node:'...c........'},
+ { name: 'complete', wave: '0.........10', node:'..........g.'},
+ ],
+ head:{
+ text: 'Interrupt Flow',
+ tick: 0,
+ },
+}
+```
+
+In the example above an interrupt for source ID `i` is configured as a level
+interrupt and is raised at a, this results in the target being notified of the
+interrupt at b. The target claims the interrupt at c (reading `i` from it's
+Claim/Complete register) so `irq_o` deasserts though `intr_src_i[i]` remains
+raised. The SW handles the interrupt and it drops at e. However a new interrupt
+quickly occurs at f. As complete hasn't been signaled yet `irq_o` isn't
+asserted. At g the interrupt is completed (by writing `i` to it's
+Claim/Complete register) so at h `irq_o` is asserted due to the new interrupt.
+
+
+# Programmers Guide
+
+## Initialization
+
+After reset, RV_PLIC doesn't generate any interrupts to any targets even if
+interrupt sources are set, as all priorities and thresholds are 0 by default and
+all ``IE`` values are 0. Software should configure the above three registers.
+
+[`PRIO0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio0) .. [`PRIO31`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio1) registers are unique. So, only one of the targets
+shall configure them.
+
+```c
+// Pseudo-code below
+void plic_init() {
+ // Configure priority
+ // Note that PRIO0 register doesn't affect as intr_src_i[0] is tied to 0.
+ for (int i = 0; i < N_SOURCE; ++i) {
+ *(PRIO + i) = value(i);
+ }
+}
+
+void plic_threshold(tid, threshold) {
+ *(THRESHOLD + tid) = threshold;
+}
+
+void plic_enable(tid, iid) {
+ // iid: 0-based ID
+ int offset = ceil(N_SOURCE / 32) * tid + (iid >> 5);
+
+ *(IE + offset) = *(IE + offset) | (1 << (iid % 32));
+}
+```
+
+## Handling Interrupt Request Events
+
+If software receives an interrupt request, it is recommended to follow the steps
+shown below (assuming target 0 which uses [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for claim/complete).
+
+1. Claim the interrupts right after entering to the interrupt service routine
+ by reading the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
+2. Determine which interrupt should be serviced based on the values read from
+ the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
+3. Execute ISR, clearing the originating peripheral interrupt.
+4. Write Interrupt ID to [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0)
+5. Repeat as necessary for other pending interrupts.
+
+It is possible to have multiple interrupt events claimed. If software claims one
+interrupt request, then the process module advertises any pending interrupts
+with lower priority unless new higher priority interrupt events occur. If a
+higher interrupt event occurs after previous interrupt is claimed, the RV_PLIC
+IP advertises the higher priority interrupt. Software may utilize an event
+manager inside a loop so that interrupt claiming and completion can be
+separated.
+
+~~~~c
+void interrupt_service() {
+ uint32_t tid = /* ... */;
+ uint32_t iid = *(CC + tid);
+ if (iid == 0) {
+ // Interrupt is claimed by one of other targets.
+ return;
+ }
+
+ do {
+ // Process interrupts...
+ // ...
+
+ // Finish.
+ *(CC + tid) = iid;
+ iid = *(CC + tid);
+ } while (iid != 0);
+}
+~~~~
+
+As a reference, default interrupt service routines are auto-generated for each
+IP, and are documented [here](/sw/apis/isr__testutils_8h.html).
+
+## Device Interface Functions (DIFs)
+
+- [Device Interface Functions](../../../sw/device/lib/dif/dif_rv_plic.h)
+
+## Registers
+
+The RV_PLIC in the top level is generated by topgen tool so that the number of
+interrupt sources may be different.
+
+- IE: CEILING(N_SOURCE / DW) X N_TARGET
+ Each bit enables corresponding interrupt source. Each target has IE set.
+- PRIO: N_SOURCE
+ Universal set across all targets. Lower n bits are valid. n is determined by
+ MAX_PRIO parameter
+- THRESHOLD: N_TARGET
+ Priority threshold per target. Only priority of the interrupt greater than
+ threshold can raise interrupt notification to the target.
+- IP: CEILING(N_SOURCE / DW)
+ Pending bits right after the gateways. Read-only
+- CC: N_TARGET
+ Claim by read, complete by write
+
+* [Register Table](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_sec_cm_testplan.hjson b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_sec_cm_testplan.hjson
new file mode 100644
index 0000000..bdee6a1
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_sec_cm_testplan.hjson
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Security countermeasures testplan extracted from the IP Hjson using reggen.
+//
+// This testplan is auto-generated only the first time it is created. This is
+// because this testplan needs to be hand-editable. It is possible that these
+// testpoints can go out of date if the spec is updated with new
+// countermeasures. When `reggen` is invoked when this testplan already exists,
+// It checks if the list of testpoints is up-to-date and enforces the user to
+// make further manual updates.
+//
+// These countermeasures and their descriptions can be found here:
+// .../rv_plic/data/rv_plic.hjson
+//
+// It is possible that the testing of some of these countermeasures may already
+// be covered as a testpoint in a different testplan. This duplication is ok -
+// the test would have likely already been developed. We simply map those tests
+// to the testpoints below using the `tests` key.
+//
+// Please ensure that this testplan is imported in:
+// .../rv_plic/data/rv_plic_testplan.hjson
+{
+ testpoints: [
+ {
+ name: sec_cm_bus_integrity
+ desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ stage: V2S
+ tests: []
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc_fpv_testplan.hjson b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc_fpv_testplan.hjson
new file mode 100644
index 0000000..65efab3
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/data/rv_plic_smc_fpv_testplan.hjson
@@ -0,0 +1,88 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "rv_plic_smc"
+ import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"]
+ testpoints: [
+ {
+ name: LevelTriggeredIp_A
+ desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+ level triggered (`le=0`), then in the prvious clock cycle, the interrupt source
+ (`intr_src_i) should be set to 1.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: EdgeTriggeredIp_A
+ desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to
+ edge triggered (`le=1`), then in the prvious clock cycle, the interrupt source
+ (`intr_src_i) should be at the rising edge.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: LevelTriggeredIpWithClaim_A
+ desc: '''If `intr_src_i` is set to 1, level indicator is set to level triggered, and claim
+ signal is not set, then at the next clock cycle `ip` will be triggered.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: EdgeTriggeredIpWithClaim_A
+ desc: '''If `intr_src_i` is at the rising edge, level indicator is set to edge triggered, and claim
+ signal is not set, then at the next clock cycle `ip` will be triggered.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: IpStableAfterTriggered_A
+ desc: "Once `ip` is set, it stays stable until is being claimed."
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: IpClearAfterClaim_A
+ desc: "Once `ip` is set and being claimed, its value is cleared to 0."
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: IpStableAfterClaimed_A
+ desc: '''Once `ip` is cleared to 0, it stays stable until completed and being triggered
+ again.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: TriggerIrqForwardCheck_A
+ desc: '''If interrupt is enabled (`ie=1`), interrupt pending is set (`ip=1`), interrupt
+ input has the highest priority among the rest of the inputs, and its priority is
+ above the threshold. Then in the next clock clcye, the `irq_o` should be triggered,
+ and the `irq_id_o` will reflect the input ID.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ {
+ name: TriggerIrqBackwardCheck_A
+ desc: '''If `irq_o` is set to 1, then in the previous clock cycle, the corresponding
+ `ip` should be set, `ie` should be enabled, and the interrupt source should above the
+ threshold and have the highest priority.'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+
+ }
+ {
+ name: IdChangeWithIrq_A
+ desc: '''If `irq_id_o` signal is changed and the signal does not change to 0 (value 0 does
+ not represent any interrupt source ID). Then either of the two condition should have
+ happened:
+ - `irq_o` is triggered
+ - No interrupt triggered, `ip` is set and `ie` is enabled, interrupt source priority is the
+ largest among the rest of the interrupt, but the interrupt source
+ priority is smaller than the threshold'''
+ stage: V2
+ tests: ["rv_plic_smc_assert"]
+ }
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/data/top_sencha_rv_plic_smc.ipconfig.hjson b/hw/top_sencha/ip_autogen/rv_plic_smc/data/top_sencha_rv_plic_smc.ipconfig.hjson
new file mode 100644
index 0000000..0927011
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/data/top_sencha_rv_plic_smc.ipconfig.hjson
@@ -0,0 +1,13 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ instance_name: top_sencha_rv_plic_smc
+ param_values:
+ {
+ prio: 3
+ src: 43
+ target: 1
+ module_instance_name: rv_plic_smc
+ }
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/doc/block_diagram.svg b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/block_diagram.svg
new file mode 100644
index 0000000..ac02b67
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/block_diagram.svg
@@ -0,0 +1 @@
+<svg version="1.1" viewBox="0.0 0.0 639.0524934383202 509.3490813648294" fill="none" stroke="none" stroke-linecap="square" stroke-miterlimit="10" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><clipPath id="p.0"><path d="m0 0l639.0525 0l0 509.3491l-639.0525 0l0 -509.3491z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="#000000" fill-opacity="0.0" d="m0 0l639.0525 0l0 509.3491l-639.0525 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m150.07086 22.257217l338.17322 0l0 463.55908l-338.17322 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="4.0,3.0" d="m150.07086 22.257217l338.17322 0l0 463.55908l-338.17322 0z" fill-rule="evenodd"/><path fill="#ffffff" d="m313.13385 46.70341l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m313.13385 46.70341l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m378.6731 193.18349q0 0.359375 -0.0625 0.703125q-0.046875 0.328125 -0.171875 0.625q-0.125 0.28125 -0.328125 0.53125q-0.1875 0.234375 -0.484375 0.40625q-0.28125 0.15625 -0.671875 0.25q-0.375 0.09375 -0.875 0.09375l-1.09375 0l0 -5.109375l1.328125 0q1.1875 0 1.765625 0.625q0.59375 0.609375 0.59375 1.875zm-0.71875 0.046875q0 -0.546875 -0.109375 -0.921875q-0.09375 -0.375 -0.3125 -0.59375q-0.203125 -0.234375 -0.515625 -0.328125q-0.3125 -0.109375 -0.734375 -0.109375l-0.59375 0l0 3.90625l0.515625 0q1.75 0 1.75 -1.953125zm5.3671875 2.5625l-0.75 0l-0.359375 -1.109375l-2.125 0l-0.359375 1.109375l-0.71875 0l1.6875 -5.109375l0.953125 0l1.671875 5.109375zm-1.3125 -1.734375l-0.859375 -2.734375l-0.859375 2.734375l1.71875 0zm5.4140625 -2.78125l-1.515625 0l0 4.515625l-0.703125 0l0 -4.515625l-1.5 0l0 -0.59375l3.71875 0l0 0.59375zm4.6953125 4.515625l-0.75 0l-0.359375 -1.109375l-2.125 0l-0.359375 1.109375l-0.71875 0l1.6875 -5.109375l0.953125 0l1.671875 5.109375zm-1.3125 -1.734375l-0.859375 -2.734375l-0.859375 2.734375l1.71875 0zm5.7578125 3.34375l-4.40625 0l0 -0.5625l4.40625 0l0 0.5625zm4.1796875 -4.203125q0 0.6875 -0.171875 1.1875q-0.15625 0.5 -0.4375 0.828125q-0.265625 0.328125 -0.640625 0.5q-0.359375 0.15625 -0.78125 0.15625q-0.484375 0 -0.859375 -0.171875q-0.359375 -0.1875 -0.609375 -0.515625q-0.234375 -0.34375 -0.359375 -0.828125q-0.109375 -0.484375 -0.109375 -1.09375q0 -0.671875 0.15625 -1.171875q0.171875 -0.5 0.4375 -0.828125q0.28125 -0.328125 0.640625 -0.484375q0.375 -0.15625 0.78125 -0.15625q0.5 0 0.859375 0.1875q0.375 0.171875 0.609375 0.5q0.25 0.328125 0.359375 0.8125q0.125 0.484375 0.125 1.078125zm-0.71875 0.0625q0 -0.453125 -0.078125 -0.828125q-0.0625 -0.375 -0.21875 -0.640625q-0.15625 -0.265625 -0.390625 -0.40625q-0.234375 -0.15625 -0.578125 -0.15625q-0.328125 0 -0.5625 0.15625q-0.234375 0.15625 -0.390625 0.4375q-0.15625 0.265625 -0.234375 0.625q-0.0625 0.359375 -0.0625 0.78125q0 0.453125 0.0625 0.828125q0.078125 0.359375 0.21875 0.640625q0.15625 0.265625 0.390625 0.421875q0.234375 0.140625 0.578125 0.140625q0.328125 0 0.5625 -0.15625q0.234375 -0.171875 0.390625 -0.4375q0.15625 -0.265625 0.234375 -0.625q0.078125 -0.375 0.078125 -0.78125zm4.9140625 0.75q0 0.421875 -0.125 0.765625q-0.125 0.34375 -0.359375 0.59375q-0.21875 0.234375 -0.5625 0.375q-0.328125 0.125 -0.765625 0.125q-0.46875 0 -0.8125 -0.125q-0.328125 -0.140625 -0.53125 -0.359375q-0.203125 -0.234375 -0.3125 -0.546875q-0.09375 -0.328125 -0.09375 -0.71875l0 -3.4375l0.703125 0l0 3.375q0 0.3125 0.046875 0.546875q0.0625 0.21875 0.1875 0.375q0.140625 0.140625 0.34375 0.21875q0.203125 0.078125 0.5 0.078125q0.546875 0 0.8125 -0.3125q0.265625 -0.328125 0.265625 -0.90625l0 -3.375l0.703125 0l0 3.328125zm4.4765625 -2.734375l-1.515625 0l0 4.515625l-0.703125 0l0 -4.515625l-1.5 0l0 -0.59375l3.71875 0l0 0.59375z" fill-rule="nonzero"/><path fill="#ffffff" d="m305.78217 38.732285l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m305.78217 38.732285l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m371.3214 185.21236q0 0.359375 -0.0625 0.703125q-0.046875 0.328125 -0.171875 0.625q-0.125 0.28125 -0.328125 0.53125q-0.1875 0.234375 -0.484375 0.40625q-0.28125 0.15625 -0.671875 0.25q-0.375 0.09375 -0.875 0.09375l-1.09375 0l0 -5.109375l1.328125 0q1.1875 0 1.765625 0.625q0.59375 0.609375 0.59375 1.875zm-0.71875 0.046875q0 -0.546875 -0.109375 -0.921875q-0.09375 -0.375 -0.3125 -0.59375q-0.203125 -0.234375 -0.515625 -0.328125q-0.3125 -0.109375 -0.734375 -0.109375l-0.59375 0l0 3.90625l0.515625 0q1.75 0 1.75 -1.953125zm5.3671875 2.5625l-0.75 0l-0.359375 -1.109375l-2.125 0l-0.359375 1.109375l-0.71875 0l1.6875 -5.109375l0.953125 0l1.671875 5.109375zm-1.3125 -1.734375l-0.859375 -2.734375l-0.859375 2.734375l1.71875 0zm5.4140625 -2.78125l-1.515625 0l0 4.515625l-0.703125 0l0 -4.515625l-1.5 0l0 -0.59375l3.71875 0l0 0.59375zm4.6953125 4.515625l-0.75 0l-0.359375 -1.109375l-2.125 0l-0.359375 1.109375l-0.71875 0l1.6875 -5.109375l0.953125 0l1.671875 5.109375zm-1.3125 -1.734375l-0.859375 -2.734375l-0.859375 2.734375l1.71875 0zm5.7578125 3.34375l-4.40625 0l0 -0.5625l4.40625 0l0 0.5625zm4.1796875 -4.203125q0 0.6875 -0.171875 1.1875q-0.15625 0.5 -0.4375 0.828125q-0.265625 0.328125 -0.640625 0.5q-0.359375 0.15625 -0.78125 0.15625q-0.484375 0 -0.859375 -0.171875q-0.359375 -0.1875 -0.609375 -0.515625q-0.234375 -0.34375 -0.359375 -0.828125q-0.109375 -0.484375 -0.109375 -1.09375q0 -0.671875 0.15625 -1.171875q0.171875 -0.5 0.4375 -0.828125q0.28125 -0.328125 0.640625 -0.484375q0.375 -0.15625 0.78125 -0.15625q0.5 0 0.859375 0.1875q0.375 0.171875 0.609375 0.5q0.25 0.328125 0.359375 0.8125q0.125 0.484375 0.125 1.078125zm-0.71875 0.0625q0 -0.453125 -0.078125 -0.828125q-0.0625 -0.375 -0.21875 -0.640625q-0.15625 -0.265625 -0.390625 -0.40625q-0.234375 -0.15625 -0.578125 -0.15625q-0.328125 0 -0.5625 0.15625q-0.234375 0.15625 -0.390625 0.4375q-0.15625 0.265625 -0.234375 0.625q-0.0625 0.359375 -0.0625 0.78125q0 0.453125 0.0625 0.828125q0.078125 0.359375 0.21875 0.640625q0.15625 0.265625 0.390625 0.421875q0.234375 0.140625 0.578125 0.140625q0.328125 0 0.5625 -0.15625q0.234375 -0.171875 0.390625 -0.4375q0.15625 -0.265625 0.234375 -0.625q0.078125 -0.375 0.078125 -0.78125zm4.9140625 0.75q0 0.421875 -0.125 0.765625q-0.125 0.34375 -0.359375 0.59375q-0.21875 0.234375 -0.5625 0.375q-0.328125 0.125 -0.765625 0.125q-0.46875 0 -0.8125 -0.125q-0.328125 -0.140625 -0.53125 -0.359375q-0.203125 -0.234375 -0.3125 -0.546875q-0.09375 -0.328125 -0.09375 -0.71875l0 -3.4375l0.703125 0l0 3.375q0 0.3125 0.046875 0.546875q0.0625 0.21875 0.1875 0.375q0.140625 0.140625 0.34375 0.21875q0.203125 0.078125 0.5 0.078125q0.546875 0 0.8125 -0.3125q0.265625 -0.328125 0.265625 -0.90625l0 -3.375l0.703125 0l0 3.328125zm4.4765625 -2.734375l-1.515625 0l0 4.515625l-0.703125 0l0 -4.515625l-1.5 0l0 -0.59375l3.71875 0l0 0.59375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m101.055115 104.0l74.92914 0l0 35.779526l-74.92914 0z" fill-rule="evenodd"/><path fill="#000000" d="m115.1577 118.038124l-1.34375 0l0 -0.65625l2.15625 0l0 3.921875l1.359375 0l0 0.65625l-3.671875 0l0 -0.65625l1.5 0l0 -3.265625zm0.28125 -2.5625q0.140625 0 0.25 0.046875q0.109375 0.046875 0.1875 0.140625q0.09375 0.078125 0.140625 0.1875q0.046875 0.109375 0.046875 0.25q0 0.125 -0.046875 0.234375q-0.046875 0.109375 -0.140625 0.203125q-0.078125 0.078125 -0.1875 0.125q-0.109375 0.046875 -0.25 0.046875q-0.125 0 -0.25 -0.046875q-0.109375 -0.046875 -0.203125 -0.125q-0.078125 -0.09375 -0.125 -0.203125q-0.046875 -0.109375 -0.046875 -0.234375q0 -0.140625 0.046875 -0.25q0.046875 -0.109375 0.125 -0.1875q0.09375 -0.09375 0.203125 -0.140625q0.125 -0.046875 0.25 -0.046875zm3.3005219 1.90625l0.703125 0l0.03125 0.75q0.203125 -0.25 0.390625 -0.40625q0.1875 -0.15625 0.359375 -0.25q0.1875 -0.09375 0.375 -0.125q0.1875 -0.046875 0.375 -0.046875q0.71875 0 1.078125 0.421875q0.359375 0.40625 0.359375 1.25l0 2.984375l-0.796875 0l0 -2.921875q0 -0.53125 -0.203125 -0.78125q-0.1875 -0.265625 -0.59375 -0.265625q-0.140625 0 -0.28125 0.046875q-0.140625 0.03125 -0.296875 0.140625q-0.140625 0.109375 -0.328125 0.296875q-0.171875 0.171875 -0.390625 0.453125l0 3.03125l-0.78125 0l0 -4.578125zm8.800522 4.515625q-0.265625 0.0625 -0.546875 0.09375q-0.28125 0.03125 -0.578125 0.03125q-0.875 0 -1.296875 -0.390625q-0.421875 -0.390625 -0.421875 -1.1875l0 -2.390625l-1.28125 0l0 -0.671875l1.28125 0l0 -1.25l0.796875 -0.203125l0 1.453125l2.046875 0l0 0.671875l-2.046875 0l0 2.328125q0 0.484375 0.265625 0.734375q0.265625 0.234375 0.765625 0.234375q0.21875 0 0.46875 -0.03125q0.265625 -0.03125 0.546875 -0.109375l0 0.6875zm1.6442719 -4.515625l0.71875 0l0.015625 0.84375q0.40625 -0.484375 0.796875 -0.703125q0.40625 -0.21875 0.796875 -0.21875q0.71875 0 1.078125 0.46875q0.375 0.453125 0.34375 1.359375l-0.796875 0q0.015625 -0.609375 -0.1875 -0.875q-0.1875 -0.265625 -0.546875 -0.265625q-0.15625 0 -0.328125 0.0625q-0.15625 0.046875 -0.328125 0.171875q-0.171875 0.125 -0.359375 0.328125q-0.1875 0.1875 -0.40625 0.46875l0 2.9375l-0.796875 0l0 -4.578125zm9.331772 6.453125l-5.125 0l0 -0.65625l5.125 0l0 0.65625zm4.347397 -3.125q0 0.25 -0.078125 0.4375q-0.078125 0.1875 -0.21875 0.34375q-0.140625 0.140625 -0.328125 0.25q-0.1875 0.09375 -0.40625 0.171875q-0.203125 0.0625 -0.4375 0.09375q-0.21875 0.03125 -0.421875 0.03125q-0.46875 0 -0.859375 -0.046875q-0.390625 -0.03125 -0.765625 -0.125l0 -0.71875q0.40625 0.109375 0.796875 0.171875q0.390625 0.046875 0.78125 0.046875q0.578125 0 0.84375 -0.140625q0.28125 -0.15625 0.28125 -0.453125q0 -0.125 -0.046875 -0.21875q-0.046875 -0.09375 -0.15625 -0.1875q-0.109375 -0.09375 -0.359375 -0.1875q-0.234375 -0.09375 -0.640625 -0.21875q-0.3125 -0.09375 -0.578125 -0.203125q-0.265625 -0.109375 -0.453125 -0.265625q-0.1875 -0.171875 -0.296875 -0.375q-0.109375 -0.21875 -0.109375 -0.515625q0 -0.1875 0.078125 -0.40625q0.09375 -0.234375 0.3125 -0.421875q0.21875 -0.203125 0.578125 -0.328125q0.359375 -0.140625 0.90625 -0.140625q0.265625 0 0.59375 0.03125q0.328125 0.03125 0.6875 0.109375l0 0.703125q-0.375 -0.09375 -0.71875 -0.140625q-0.328125 -0.046875 -0.5625 -0.046875q-0.296875 0 -0.5 0.046875q-0.203125 0.046875 -0.328125 0.125q-0.125 0.078125 -0.1875 0.1875q-0.046875 0.109375 -0.046875 0.234375q0 0.125 0.046875 0.234375q0.046875 0.09375 0.171875 0.1875q0.125 0.09375 0.359375 0.1875q0.234375 0.09375 0.609375 0.203125q0.40625 0.109375 0.6875 0.25q0.28125 0.125 0.453125 0.28125q0.171875 0.15625 0.234375 0.359375q0.078125 0.203125 0.078125 0.453125zm1.7067719 -3.328125l0.71875 0l0.015625 0.84375q0.40625 -0.484375 0.796875 -0.703125q0.40625 -0.21875 0.796875 -0.21875q0.71875 0 1.078125 0.46875q0.375 0.453125 0.34375 1.359375l-0.796875 0q0.015625 -0.609375 -0.1875 -0.875q-0.1875 -0.265625 -0.546875 -0.265625q-0.15625 0 -0.328125 0.0625q-0.15625 0.046875 -0.328125 0.171875q-0.171875 0.125 -0.359375 0.328125q-0.1875 0.1875 -0.40625 0.46875l0 2.9375l-0.796875 0l0 -4.578125zm8.488022 4.40625q-0.3125 0.125 -0.640625 0.171875q-0.3125 0.0625 -0.671875 0.0625q-1.078125 0 -1.671875 -0.578125q-0.578125 -0.59375 -0.578125 -1.71875q0 -0.546875 0.171875 -0.984375q0.171875 -0.453125 0.46875 -0.765625q0.3125 -0.3125 0.734375 -0.484375q0.421875 -0.171875 0.9375 -0.171875q0.34375 0 0.65625 0.0625q0.3125 0.046875 0.59375 0.15625l0 0.75q-0.296875 -0.15625 -0.609375 -0.21875q-0.296875 -0.078125 -0.625 -0.078125q-0.3125 0 -0.578125 0.125q-0.265625 0.109375 -0.484375 0.328125q-0.203125 0.21875 -0.328125 0.53125q-0.109375 0.3125 -0.109375 0.71875q0 0.828125 0.40625 1.25q0.40625 0.40625 1.109375 0.40625q0.328125 0 0.625 -0.078125q0.3125 -0.078125 0.59375 -0.21875l0 0.734375zm5.972397 2.046875l-5.125 0l0 -0.65625l5.125 0l0 0.65625zm2.2848969 -5.796875l-1.34375 0l0 -0.65625l2.15625 0l0 3.921875l1.359375 0l0 0.65625l-3.671875 0l0 -0.65625l1.5 0l0 -3.265625zm0.28125 -2.5625q0.140625 0 0.25 0.046875q0.109375 0.046875 0.1875 0.140625q0.09375 0.078125 0.140625 0.1875q0.046875 0.109375 0.046875 0.25q0 0.125 -0.046875 0.234375q-0.046875 0.109375 -0.140625 0.203125q-0.078125 0.078125 -0.1875 0.125q-0.109375 0.046875 -0.25 0.046875q-0.125 0 -0.25 -0.046875q-0.109375 -0.046875 -0.203125 -0.125q-0.078125 -0.09375 -0.125 -0.203125q-0.046875 -0.109375 -0.046875 -0.234375q0 -0.140625 0.046875 -0.25q0.046875 -0.109375 0.125 -0.1875q0.09375 -0.09375 0.203125 -0.140625q0.125 -0.046875 0.25 -0.046875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m177.4672 32.0l59.307083 0l0 307.90552l-59.307083 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m177.4672 32.0l59.307083 0l0 307.90552l-59.307083 0z" fill-rule="evenodd"/><path fill="#000000" d="m195.6637 44.445625q-0.296875 -0.15625 -0.59375 -0.234375q-0.296875 -0.078125 -0.65625 -0.078125q-0.40625 0 -0.71875 0.140625q-0.3125 0.140625 -0.53125 0.40625q-0.21875 0.265625 -0.34375 0.640625q-0.109375 0.359375 -0.109375 0.8125q0 0.46875 0.09375 0.84375q0.09375 0.375 0.296875 0.640625q0.203125 0.25 0.5 0.390625q0.3125 0.125 0.75 0.125q0.078125 0 0.15625 0q0.09375 -0.015625 0.171875 -0.03125q0.09375 -0.015625 0.171875 -0.03125q0.078125 -0.015625 0.140625 -0.046875l0 -1.625l-1.046875 0l0 -0.5625l1.734375 0l0 2.609375q-0.15625 0.0625 -0.34375 0.125q-0.171875 0.0625 -0.359375 0.109375q-0.1875 0.03125 -0.375 0.046875q-0.171875 0.03125 -0.34375 0.03125q-0.53125 0 -0.953125 -0.171875q-0.40625 -0.171875 -0.703125 -0.484375q-0.296875 -0.328125 -0.453125 -0.796875q-0.15625 -0.484375 -0.15625 -1.125q0 -0.625 0.171875 -1.125q0.171875 -0.5 0.484375 -0.84375q0.328125 -0.34375 0.765625 -0.515625q0.453125 -0.1875 1.0 -0.1875q0.34375 0 0.640625 0.0625q0.3125 0.046875 0.609375 0.1875l0 0.6875zm3.6015625 4.234375l-0.015625 -0.53125q-0.3125 0.3125 -0.640625 0.46875q-0.328125 0.140625 -0.703125 0.140625q-0.328125 0 -0.578125 -0.09375q-0.234375 -0.09375 -0.390625 -0.234375q-0.140625 -0.15625 -0.21875 -0.359375q-0.078125 -0.203125 -0.078125 -0.4375q0 -0.59375 0.4375 -0.921875q0.453125 -0.34375 1.3125 -0.34375l0.8125 0l0 -0.34375q0 -0.34375 -0.234375 -0.546875q-0.21875 -0.21875 -0.671875 -0.21875q-0.328125 0 -0.65625 0.078125q-0.328125 0.078125 -0.671875 0.21875l0 -0.625q0.140625 -0.046875 0.296875 -0.078125q0.15625 -0.046875 0.328125 -0.078125q0.171875 -0.046875 0.359375 -0.0625q0.203125 -0.03125 0.390625 -0.03125q0.359375 0 0.640625 0.078125q0.296875 0.078125 0.484375 0.25q0.203125 0.15625 0.296875 0.40625q0.109375 0.234375 0.109375 0.5625l0 2.703125l-0.609375 0zm-0.0625 -1.78125l-0.875 0q-0.25 0 -0.4375 0.046875q-0.171875 0.046875 -0.296875 0.140625q-0.109375 0.09375 -0.171875 0.234375q-0.0625 0.125 -0.0625 0.28125q0 0.125 0.03125 0.234375q0.046875 0.09375 0.125 0.171875q0.078125 0.078125 0.203125 0.125q0.125 0.046875 0.296875 0.046875q0.234375 0 0.53125 -0.140625q0.3125 -0.140625 0.65625 -0.453125l0 -0.6875zm5.1015625 1.71875q-0.21875 0.0625 -0.46875 0.09375q-0.25 0.03125 -0.5 0.03125q-0.734375 0 -1.109375 -0.328125q-0.359375 -0.34375 -0.359375 -1.046875l0 -2.046875l-1.09375 0l0 -0.5625l1.09375 0l0 -1.078125l0.6875 -0.171875l0 1.25l1.75 0l0 0.5625l-1.75 0l0 2.0q0 0.421875 0.21875 0.640625q0.21875 0.203125 0.65625 0.203125q0.1875 0 0.40625 -0.03125q0.234375 -0.03125 0.46875 -0.09375l0 0.578125zm4.5546875 -2.109375q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0zm5.4296875 -1.65625l-0.578125 3.921875l-0.828125 0l-0.5625 -1.640625l-0.109375 -0.40625l-0.125 0.421875l-0.546875 1.625l-0.796875 0l-0.578125 -3.921875l0.671875 0l0.328125 2.65625l0.0625 0.59375l0.171875 -0.515625l0.578125 -1.765625l0.484375 0l0.609375 1.75l0.171875 0.515625l0.0625 -0.546875l0.3125 -2.6875l0.671875 0zm3.2734375 3.921875l-0.015625 -0.53125q-0.3125 0.3125 -0.640625 0.46875q-0.328125 0.140625 -0.703125 0.140625q-0.328125 0 -0.578125 -0.09375q-0.234375 -0.09375 -0.390625 -0.234375q-0.140625 -0.15625 -0.21875 -0.359375q-0.078125 -0.203125 -0.078125 -0.4375q0 -0.59375 0.4375 -0.921875q0.453125 -0.34375 1.3125 -0.34375l0.8125 0l0 -0.34375q0 -0.34375 -0.234375 -0.546875q-0.21875 -0.21875 -0.671875 -0.21875q-0.328125 0 -0.65625 0.078125q-0.328125 0.078125 -0.671875 0.21875l0 -0.625q0.140625 -0.046875 0.296875 -0.078125q0.15625 -0.046875 0.328125 -0.078125q0.171875 -0.046875 0.359375 -0.0625q0.203125 -0.03125 0.390625 -0.03125q0.359375 0 0.640625 0.078125q0.296875 0.078125 0.484375 0.25q0.203125 0.15625 0.296875 0.40625q0.109375 0.234375 0.109375 0.5625l0 2.703125l-0.609375 0zm-0.0625 -1.78125l-0.875 0q-0.25 0 -0.4375 0.046875q-0.171875 0.046875 -0.296875 0.140625q-0.109375 0.09375 -0.171875 0.234375q-0.0625 0.125 -0.0625 0.28125q0 0.125 0.03125 0.234375q0.046875 0.09375 0.125 0.171875q0.078125 0.078125 0.203125 0.125q0.125 0.046875 0.296875 0.046875q0.234375 0 0.53125 -0.140625q0.3125 -0.140625 0.65625 -0.453125l0 -0.6875zm5.4296875 -2.140625l-1.328125 3.5q-0.203125 0.546875 -0.4375 0.921875q-0.21875 0.390625 -0.484375 0.640625q-0.25 0.25 -0.5625 0.359375q-0.3125 0.125 -0.703125 0.125q-0.09375 0 -0.1875 0q-0.078125 0 -0.171875 -0.015625l0 -0.609375q0.078125 0 0.171875 0.015625q0.109375 0.015625 0.234375 0.015625q0.1875 0 0.34375 -0.0625q0.15625 -0.046875 0.296875 -0.171875q0.15625 -0.125 0.28125 -0.328125q0.140625 -0.1875 0.265625 -0.46875l-1.5625 -3.921875l0.765625 0l1.0 2.59375l0.1875 0.609375l0.234375 -0.625l0.921875 -2.578125l0.734375 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m262.74277 256.01312l0 151.59055" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m262.74277 256.01312l0 148.16348" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m262.74277 404.17657l-1.1245728 -1.1245728l1.1245728 3.0897827l1.1246033 -3.0897827z" fill-rule="evenodd"/><path fill="#ffffff" d="m299.04724 32.0l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m299.04724 32.0l158.04724 0l0 292.8189l-158.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m366.64508 45.133125q0 0.3125 -0.125 0.625q-0.109375 0.296875 -0.359375 0.546875q-0.234375 0.234375 -0.625 0.390625q-0.375 0.15625 -0.90625 0.15625l-0.640625 0l0 1.828125l-0.6875 0l0 -5.109375l1.4375 0q0.375 0 0.71875 0.09375q0.34375 0.078125 0.609375 0.265625q0.265625 0.1875 0.421875 0.484375q0.15625 0.296875 0.15625 0.71875zm-0.71875 0.03125q0 -0.484375 -0.328125 -0.75q-0.3125 -0.265625 -0.890625 -0.265625l-0.71875 0l0 2.109375l0.65625 0q0.609375 0 0.9375 -0.265625q0.34375 -0.28125 0.34375 -0.828125zm1.9296875 -0.40625l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm7.6640625 1.921875q0 0.46875 -0.140625 0.84375q-0.125 0.375 -0.375 0.65625q-0.234375 0.265625 -0.578125 0.421875q-0.34375 0.15625 -0.796875 0.15625q-0.421875 0 -0.75 -0.125q-0.328125 -0.140625 -0.5625 -0.390625q-0.234375 -0.265625 -0.359375 -0.640625q-0.125 -0.375 -0.125 -0.859375q0 -0.453125 0.125 -0.828125q0.140625 -0.390625 0.375 -0.65625q0.25 -0.265625 0.59375 -0.421875q0.34375 -0.15625 0.78125 -0.15625q0.421875 0 0.75 0.140625q0.34375 0.125 0.578125 0.375q0.234375 0.25 0.359375 0.625q0.125 0.375 0.125 0.859375zm-0.703125 0.03125q0 -0.359375 -0.078125 -0.625q-0.078125 -0.28125 -0.234375 -0.453125q-0.140625 -0.1875 -0.359375 -0.28125q-0.203125 -0.09375 -0.46875 -0.09375q-0.3125 0 -0.53125 0.125q-0.203125 0.125 -0.34375 0.328125q-0.140625 0.1875 -0.203125 0.453125q-0.0625 0.265625 -0.0625 0.546875q0 0.375 0.078125 0.65625q0.078125 0.265625 0.21875 0.453125q0.15625 0.171875 0.359375 0.265625q0.21875 0.09375 0.484375 0.09375q0.296875 0 0.515625 -0.125q0.21875 -0.125 0.359375 -0.3125q0.140625 -0.203125 0.203125 -0.46875q0.0625 -0.265625 0.0625 -0.5625zm4.7265625 1.828125q-0.265625 0.09375 -0.546875 0.140625q-0.28125 0.0625 -0.578125 0.0625q-0.921875 0 -1.421875 -0.5q-0.5 -0.515625 -0.5 -1.484375q0 -0.46875 0.140625 -0.84375q0.140625 -0.375 0.40625 -0.640625q0.265625 -0.28125 0.625 -0.421875q0.359375 -0.15625 0.796875 -0.15625q0.3125 0 0.578125 0.046875q0.265625 0.046875 0.5 0.140625l0 0.65625q-0.25 -0.140625 -0.515625 -0.203125q-0.265625 -0.0625 -0.546875 -0.0625q-0.265625 0 -0.5 0.109375q-0.21875 0.09375 -0.40625 0.28125q-0.171875 0.1875 -0.28125 0.46875q-0.09375 0.265625 -0.09375 0.59375q0 0.71875 0.34375 1.078125q0.34375 0.34375 0.96875 0.34375q0.265625 0 0.53125 -0.0625q0.265625 -0.0625 0.5 -0.1875l0 0.640625zm4.6640625 -2.03125q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0zm4.8984375 1.1875q0 0.21875 -0.078125 0.390625q-0.0625 0.15625 -0.1875 0.28125q-0.125 0.125 -0.28125 0.21875q-0.15625 0.078125 -0.34375 0.140625q-0.171875 0.0625 -0.375 0.09375q-0.1875 0.03125 -0.375 0.03125q-0.390625 0 -0.734375 -0.046875q-0.328125 -0.03125 -0.640625 -0.109375l0 -0.625q0.34375 0.09375 0.671875 0.15625q0.34375 0.046875 0.6875 0.046875q0.484375 0 0.71875 -0.125q0.234375 -0.140625 0.234375 -0.390625q0 -0.109375 -0.046875 -0.1875q-0.03125 -0.09375 -0.125 -0.15625q-0.09375 -0.078125 -0.3125 -0.15625q-0.203125 -0.09375 -0.546875 -0.203125q-0.265625 -0.078125 -0.5 -0.171875q-0.21875 -0.09375 -0.390625 -0.234375q-0.15625 -0.140625 -0.25 -0.3125q-0.09375 -0.1875 -0.09375 -0.4375q0 -0.171875 0.078125 -0.359375q0.078125 -0.203125 0.25 -0.359375q0.1875 -0.171875 0.5 -0.28125q0.3125 -0.125 0.78125 -0.125q0.234375 0 0.515625 0.03125q0.28125 0.03125 0.578125 0.09375l0 0.59375q-0.3125 -0.078125 -0.609375 -0.109375q-0.28125 -0.03125 -0.484375 -0.03125q-0.265625 0 -0.4375 0.046875q-0.171875 0.03125 -0.28125 0.09375q-0.109375 0.0625 -0.15625 0.15625q-0.046875 0.09375 -0.046875 0.203125q0 0.109375 0.046875 0.203125q0.046875 0.078125 0.15625 0.15625q0.109375 0.078125 0.296875 0.15625q0.203125 0.078125 0.53125 0.171875q0.34375 0.109375 0.578125 0.21875q0.25 0.109375 0.390625 0.25q0.15625 0.125 0.21875 0.296875q0.0625 0.171875 0.0625 0.390625zm4.3984375 0q0 0.21875 -0.078125 0.390625q-0.0625 0.15625 -0.1875 0.28125q-0.125 0.125 -0.28125 0.21875q-0.15625 0.078125 -0.34375 0.140625q-0.171875 0.0625 -0.375 0.09375q-0.1875 0.03125 -0.375 0.03125q-0.390625 0 -0.734375 -0.046875q-0.328125 -0.03125 -0.640625 -0.109375l0 -0.625q0.34375 0.09375 0.671875 0.15625q0.34375 0.046875 0.6875 0.046875q0.484375 0 0.71875 -0.125q0.234375 -0.140625 0.234375 -0.390625q0 -0.109375 -0.046875 -0.1875q-0.03125 -0.09375 -0.125 -0.15625q-0.09375 -0.078125 -0.3125 -0.15625q-0.203125 -0.09375 -0.546875 -0.203125q-0.265625 -0.078125 -0.5 -0.171875q-0.21875 -0.09375 -0.390625 -0.234375q-0.15625 -0.140625 -0.25 -0.3125q-0.09375 -0.1875 -0.09375 -0.4375q0 -0.171875 0.078125 -0.359375q0.078125 -0.203125 0.25 -0.359375q0.1875 -0.171875 0.5 -0.28125q0.3125 -0.125 0.78125 -0.125q0.234375 0 0.515625 0.03125q0.28125 0.03125 0.578125 0.09375l0 0.59375q-0.3125 -0.078125 -0.609375 -0.109375q-0.28125 -0.03125 -0.484375 -0.03125q-0.265625 0 -0.4375 0.046875q-0.171875 0.03125 -0.28125 0.09375q-0.109375 0.0625 -0.15625 0.15625q-0.046875 0.09375 -0.046875 0.203125q0 0.109375 0.046875 0.203125q0.046875 0.078125 0.15625 0.15625q0.109375 0.078125 0.296875 0.15625q0.203125 0.078125 0.53125 0.171875q0.34375 0.109375 0.578125 0.21875q0.25 0.109375 0.390625 0.25q0.15625 0.125 0.21875 0.296875q0.0625 0.171875 0.0625 0.390625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m236.77428 137.43176l88.85039 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m236.77428 137.43176l85.423325 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m322.19757 137.43176l-1.1245728 1.1245728l3.0897827 -1.1245728l-3.0897827 -1.124588z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m236.77428 255.99869l88.72441 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m236.77428 255.99869l85.29732 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m322.0716 255.99869l-1.1245728 1.1245728l3.0897522 -1.1245728l-3.0897522 -1.124588z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m236.77428 68.61155l88.94487 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m236.77428 68.61155l85.51781 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m322.29208 68.61155l-1.1246033 1.1245804l3.0897827 -1.1245804l-3.0897827 -1.124588z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m112.632545 100.83202l57.889763 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-57.889763 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m112.632545 100.83202l57.889763 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-57.889763 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m177.4672 408.0l293.10236 0l0 65.19684l-293.10236 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m177.4672 408.0l293.10236 0l0 65.19684l-293.10236 0z" fill-rule="evenodd"/><path fill="#000000" d="m422.76486 457.955l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm7.5546875 1.75q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0zm4.6171875 -1.109375q0.109375 0.140625 0.171875 0.328125q0.0625 0.171875 0.0625 0.390625q0 0.296875 -0.125 0.5625q-0.109375 0.25 -0.3125 0.4375q-0.203125 0.171875 -0.484375 0.265625q-0.28125 0.09375 -0.625 0.09375q-0.234375 0 -0.453125 -0.046875q-0.21875 -0.046875 -0.34375 -0.125q-0.078125 0.109375 -0.125 0.203125q-0.046875 0.09375 -0.046875 0.21875q0 0.140625 0.140625 0.25q0.140625 0.09375 0.375 0.09375l1.03125 0.046875q0.296875 0 0.546875 0.078125q0.25 0.0625 0.421875 0.1875q0.171875 0.125 0.265625 0.3125q0.109375 0.1875 0.109375 0.421875q0 0.265625 -0.109375 0.5q-0.109375 0.234375 -0.359375 0.40625q-0.234375 0.1875 -0.59375 0.28125q-0.359375 0.109375 -0.859375 0.109375q-0.484375 0 -0.8125 -0.078125q-0.328125 -0.078125 -0.546875 -0.21875q-0.21875 -0.125 -0.3125 -0.3125q-0.09375 -0.1875 -0.09375 -0.40625q0 -0.28125 0.125 -0.5q0.140625 -0.21875 0.40625 -0.421875q-0.09375 -0.046875 -0.171875 -0.109375q-0.078125 -0.078125 -0.125 -0.15625q-0.046875 -0.078125 -0.078125 -0.171875q-0.015625 -0.09375 -0.015625 -0.1875q0 -0.25 0.125 -0.453125q0.125 -0.21875 0.28125 -0.40625q-0.078125 -0.09375 -0.140625 -0.171875q-0.046875 -0.09375 -0.09375 -0.1875q-0.03125 -0.109375 -0.0625 -0.21875q-0.015625 -0.125 -0.015625 -0.265625q0 -0.3125 0.109375 -0.5625q0.109375 -0.25 0.3125 -0.421875q0.203125 -0.1875 0.484375 -0.28125q0.28125 -0.109375 0.625 -0.109375q0.15625 0 0.28125 0.03125q0.140625 0.015625 0.234375 0.046875l1.421875 0l0 0.546875l-0.625 0zm-2.359375 3.9375q0 0.28125 0.28125 0.40625q0.296875 0.125 0.8125 0.125q0.328125 0 0.546875 -0.0625q0.21875 -0.046875 0.34375 -0.140625q0.140625 -0.09375 0.203125 -0.21875q0.0625 -0.125 0.0625 -0.25q0 -0.25 -0.203125 -0.359375q-0.1875 -0.109375 -0.59375 -0.140625l-1.03125 -0.03125q-0.125 0.09375 -0.21875 0.171875q-0.078125 0.078125 -0.125 0.15625q-0.046875 0.09375 -0.0625 0.171875q-0.015625 0.09375 -0.015625 0.171875zm0.203125 -3.203125q0 0.1875 0.0625 0.34375q0.0625 0.15625 0.171875 0.265625q0.125 0.109375 0.265625 0.171875q0.15625 0.0625 0.34375 0.0625q0.203125 0 0.359375 -0.0625q0.171875 -0.078125 0.265625 -0.1875q0.109375 -0.125 0.171875 -0.28125q0.0625 -0.15625 0.0625 -0.3125q0 -0.1875 -0.0625 -0.34375q-0.0625 -0.15625 -0.1875 -0.265625q-0.109375 -0.109375 -0.265625 -0.171875q-0.15625 -0.0625 -0.34375 -0.0625q-0.203125 0 -0.359375 0.078125q-0.15625 0.0625 -0.265625 0.1875q-0.109375 0.109375 -0.171875 0.265625q-0.046875 0.140625 -0.046875 0.3125zm5.0703125 -0.71875l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm5.9296875 4.484375q0 0.21875 -0.078125 0.390625q-0.0625 0.15625 -0.1875 0.28125q-0.125 0.125 -0.28125 0.21875q-0.15625 0.078125 -0.34375 0.140625q-0.171875 0.0625 -0.375 0.09375q-0.1875 0.03125 -0.375 0.03125q-0.390625 0 -0.734375 -0.046875q-0.328125 -0.03125 -0.640625 -0.109375l0 -0.625q0.34375 0.09375 0.671875 0.15625q0.34375 0.046875 0.6875 0.046875q0.484375 0 0.71875 -0.125q0.234375 -0.140625 0.234375 -0.390625q0 -0.109375 -0.046875 -0.1875q-0.03125 -0.09375 -0.125 -0.15625q-0.09375 -0.078125 -0.3125 -0.15625q-0.203125 -0.09375 -0.546875 -0.203125q-0.265625 -0.078125 -0.5 -0.171875q-0.21875 -0.09375 -0.390625 -0.234375q-0.15625 -0.140625 -0.25 -0.3125q-0.09375 -0.1875 -0.09375 -0.4375q0 -0.171875 0.078125 -0.359375q0.078125 -0.203125 0.25 -0.359375q0.1875 -0.171875 0.5 -0.28125q0.3125 -0.125 0.78125 -0.125q0.234375 0 0.515625 0.03125q0.28125 0.03125 0.578125 0.09375l0 0.59375q-0.3125 -0.078125 -0.609375 -0.109375q-0.28125 -0.03125 -0.484375 -0.03125q-0.265625 0 -0.4375 0.046875q-0.171875 0.03125 -0.28125 0.09375q-0.109375 0.0625 -0.15625 0.15625q-0.046875 0.09375 -0.046875 0.203125q0 0.109375 0.046875 0.203125q0.046875 0.078125 0.15625 0.15625q0.109375 0.078125 0.296875 0.15625q0.203125 0.078125 0.53125 0.171875q0.34375 0.109375 0.578125 0.21875q0.25 0.109375 0.390625 0.25q0.15625 0.125 0.21875 0.296875q0.0625 0.171875 0.0625 0.390625zm4.4453125 1.015625q-0.21875 0.0625 -0.46875 0.09375q-0.25 0.03125 -0.5 0.03125q-0.734375 0 -1.109375 -0.328125q-0.359375 -0.34375 -0.359375 -1.046875l0 -2.046875l-1.09375 0l0 -0.5625l1.09375 0l0 -1.078125l0.6875 -0.171875l0 1.25l1.75 0l0 0.5625l-1.75 0l0 2.0q0 0.421875 0.21875 0.640625q0.21875 0.203125 0.65625 0.203125q0.1875 0 0.40625 -0.03125q0.234375 -0.03125 0.46875 -0.09375l0 0.578125zm4.5546875 -2.109375q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0zm1.9453125 -1.65625l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm7.3515625 2.84375q0 0.21875 -0.078125 0.390625q-0.0625 0.15625 -0.1875 0.28125q-0.125 0.125 -0.28125 0.21875q-0.15625 0.078125 -0.34375 0.140625q-0.171875 0.0625 -0.375 0.09375q-0.1875 0.03125 -0.375 0.03125q-0.390625 0 -0.734375 -0.046875q-0.328125 -0.03125 -0.640625 -0.109375l0 -0.625q0.34375 0.09375 0.671875 0.15625q0.34375 0.046875 0.6875 0.046875q0.484375 0 0.71875 -0.125q0.234375 -0.140625 0.234375 -0.390625q0 -0.109375 -0.046875 -0.1875q-0.03125 -0.09375 -0.125 -0.15625q-0.09375 -0.078125 -0.3125 -0.15625q-0.203125 -0.09375 -0.546875 -0.203125q-0.265625 -0.078125 -0.5 -0.171875q-0.21875 -0.09375 -0.390625 -0.234375q-0.15625 -0.140625 -0.25 -0.3125q-0.09375 -0.1875 -0.09375 -0.4375q0 -0.171875 0.078125 -0.359375q0.078125 -0.203125 0.25 -0.359375q0.1875 -0.171875 0.5 -0.28125q0.3125 -0.125 0.78125 -0.125q0.234375 0 0.515625 0.03125q0.28125 0.03125 0.578125 0.09375l0 0.59375q-0.3125 -0.078125 -0.609375 -0.109375q-0.28125 -0.03125 -0.484375 -0.03125q-0.265625 0 -0.4375 0.046875q-0.171875 0.03125 -0.28125 0.09375q-0.109375 0.0625 -0.15625 0.15625q-0.046875 0.09375 -0.046875 0.203125q0 0.109375 0.046875 0.203125q0.046875 0.078125 0.15625 0.15625q0.109375 0.078125 0.296875 0.15625q0.203125 0.078125 0.53125 0.171875q0.34375 0.109375 0.578125 0.21875q0.25 0.109375 0.390625 0.25q0.15625 0.125 0.21875 0.296875q0.0625 0.171875 0.0625 0.390625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m111.59055 429.99213l8.0 -8.0l0 4.0l49.889763 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-49.889763 0l0 4.0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m111.59055 429.99213l8.0 -8.0l0 4.0l49.889763 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-49.889763 0l0 4.0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m236.77428 33.372704l62.267715 0l0 34.015747l-62.267715 0z" fill-rule="evenodd"/><path fill="#000000" d="m265.47845 52.709076l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.1796875 3.53125q0 0.515625 -0.15625 0.90625q-0.140625 0.390625 -0.40625 0.65625q-0.25 0.25 -0.609375 0.390625q-0.34375 0.125 -0.75 0.125q-0.1875 0 -0.375 -0.015625q-0.1875 -0.015625 -0.375 -0.078125l0 1.65625l-0.6875 0l0 -5.53125l0.609375 0l0.046875 0.65625q0.28125 -0.40625 0.609375 -0.5625q0.34375 -0.171875 0.734375 -0.171875q0.328125 0 0.578125 0.140625q0.265625 0.140625 0.4375 0.40625q0.171875 0.25 0.25 0.609375q0.09375 0.359375 0.09375 0.8125zm-0.703125 0.03125q0 -0.3125 -0.046875 -0.5625q-0.046875 -0.265625 -0.140625 -0.4375q-0.09375 -0.1875 -0.25 -0.296875q-0.15625 -0.109375 -0.359375 -0.109375q-0.125 0 -0.265625 0.046875q-0.125 0.046875 -0.28125 0.140625q-0.140625 0.09375 -0.296875 0.25q-0.15625 0.15625 -0.328125 0.390625l0 1.90625q0.1875 0.078125 0.390625 0.125q0.203125 0.046875 0.40625 0.046875q0.546875 0 0.859375 -0.375q0.3125 -0.375 0.3125 -1.125z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m407.99738 409.98425l0 65.19684l-26.204712 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m392.27753 414.7655q-0.0625 -0.21875 -0.09375 -0.46875q-0.03125 -0.25 -0.03125 -0.5q0 -0.734375 0.328125 -1.109375q0.34375 -0.359375 1.046875 -0.359375l2.046875 0l0 -1.09375l0.5625 0l0 1.09375l1.078125 0l0.171875 0.6875l-1.25 0l0 1.75l-0.5625 0l0 -1.75l-2.0 0q-0.421875 0 -0.640625 0.21875q-0.203125 0.21875 -0.203125 0.65625q0 0.1875 0.03125 0.40625q0.03125 0.234375 0.09375 0.46875l-0.578125 0zm-0.0625 4.3984375l0 -0.6875l2.5 0q0.453125 0 0.671875 -0.171875q0.234375 -0.15625 0.234375 -0.484375q0 -0.125 -0.046875 -0.25q-0.03125 -0.125 -0.125 -0.25q-0.078125 -0.125 -0.234375 -0.28125q-0.15625 -0.15625 -0.390625 -0.34375l-2.609375 0l0 -0.6875l5.515625 0l0 0.6875l-1.59375 0l-0.609375 -0.03125q0.1875 0.15625 0.3125 0.3125q0.140625 0.15625 0.21875 0.3125q0.078125 0.15625 0.109375 0.3125q0.046875 0.15625 0.046875 0.328125q0 0.59375 -0.359375 0.90625q-0.359375 0.328125 -1.078125 0.328125l-2.5625 0zm3.921875 1.3984375l0 0.625l-0.71875 0.015625q0.421875 0.359375 0.609375 0.6875q0.1875 0.34375 0.1875 0.6875q0 0.609375 -0.40625 0.921875q-0.390625 0.3125 -1.171875 0.296875l0 -0.6875q0.515625 0 0.75 -0.15625q0.234375 -0.15625 0.234375 -0.46875q0 -0.140625 -0.046875 -0.28125q-0.046875 -0.140625 -0.15625 -0.296875q-0.109375 -0.140625 -0.28125 -0.3125q-0.15625 -0.15625 -0.40625 -0.34375l-2.515625 0l0 -0.6875l3.921875 0zm-1.75 7.5546875q-0.140625 0 -0.25 0q-0.09375 0 -0.171875 -0.015625l0 -2.75q-0.609375 0 -0.9375 0.328125q-0.3125 0.34375 -0.3125 0.96875q0 0.171875 0.015625 0.34375q0.015625 0.171875 0.03125 0.328125q0.03125 0.171875 0.046875 0.3125q0.03125 0.15625 0.078125 0.28125l-0.5625 0q-0.078125 -0.28125 -0.125 -0.640625q-0.0625 -0.34375 -0.0625 -0.71875q0 -0.5 0.140625 -0.875q0.140625 -0.359375 0.390625 -0.59375q0.265625 -0.21875 0.640625 -0.34375q0.390625 -0.109375 0.859375 -0.109375q0.421875 0 0.78125 0.125q0.375 0.125 0.65625 0.34375q0.28125 0.234375 0.4375 0.5625q0.171875 0.328125 0.171875 0.75q0 0.421875 -0.140625 0.734375q-0.125 0.3125 -0.359375 0.53125q-0.234375 0.21875 -0.578125 0.328125q-0.328125 0.109375 -0.75 0.109375zm0.09375 -0.703125q0.265625 0.015625 0.484375 -0.046875q0.21875 -0.0625 0.375 -0.203125q0.15625 -0.125 0.234375 -0.328125q0.09375 -0.1875 0.09375 -0.453125q0 -0.21875 -0.09375 -0.40625q-0.078125 -0.171875 -0.234375 -0.3125q-0.15625 -0.125 -0.375 -0.21875q-0.21875 -0.078125 -0.484375 -0.09375l0 2.0625zm-1.1875 4.8984375q-0.21875 0 -0.390625 -0.078125q-0.15625 -0.0625 -0.28125 -0.1875q-0.125 -0.125 -0.21875 -0.28125q-0.078125 -0.15625 -0.140625 -0.34375q-0.0625 -0.171875 -0.09375 -0.375q-0.03125 -0.1875 -0.03125 -0.375q0 -0.390625 0.046875 -0.734375q0.03125 -0.328125 0.109375 -0.640625l0.625 0q-0.09375 0.34375 -0.15625 0.671875q-0.046875 0.34375 -0.046875 0.6875q0 0.484375 0.125 0.71875q0.140625 0.234375 0.390625 0.234375q0.109375 0 0.1875 -0.046875q0.09375 -0.03125 0.15625 -0.125q0.078125 -0.09375 0.15625 -0.3125q0.09375 -0.203125 0.203125 -0.546875q0.078125 -0.265625 0.171875 -0.5q0.09375 -0.21875 0.234375 -0.390625q0.140625 -0.15625 0.3125 -0.25q0.1875 -0.09375 0.4375 -0.09375q0.171875 0 0.359375 0.078125q0.203125 0.078125 0.359375 0.25q0.171875 0.1875 0.28125 0.5q0.125 0.3125 0.125 0.78125q0 0.234375 -0.03125 0.515625q-0.03125 0.28125 -0.09375 0.578125l-0.59375 0q0.078125 -0.3125 0.109375 -0.609375q0.03125 -0.28125 0.03125 -0.484375q0 -0.265625 -0.046875 -0.4375q-0.03125 -0.171875 -0.09375 -0.28125q-0.0625 -0.109375 -0.15625 -0.15625q-0.09375 -0.046875 -0.203125 -0.046875q-0.109375 0 -0.203125 0.046875q-0.078125 0.046875 -0.15625 0.15625q-0.078125 0.109375 -0.15625 0.296875q-0.078125 0.203125 -0.171875 0.53125q-0.109375 0.34375 -0.21875 0.578125q-0.109375 0.25 -0.25 0.390625q-0.125 0.15625 -0.296875 0.21875q-0.171875 0.0625 -0.390625 0.0625zm-1.078125 4.4453125l0 -0.6875l2.5 0q0.453125 0 0.671875 -0.171875q0.234375 -0.15625 0.234375 -0.484375q0 -0.125 -0.046875 -0.25q-0.03125 -0.125 -0.125 -0.25q-0.078125 -0.125 -0.234375 -0.28125q-0.15625 -0.15625 -0.390625 -0.34375l-2.609375 0l0 -0.6875l5.515625 0l0 0.6875l-1.59375 0l-0.609375 -0.03125q0.1875 0.15625 0.3125 0.3125q0.140625 0.15625 0.21875 0.3125q0.078125 0.15625 0.109375 0.3125q0.046875 0.15625 0.046875 0.328125q0 0.59375 -0.359375 0.90625q-0.359375 0.328125 -1.078125 0.328125l-2.5625 0zm2.0 4.6640625q-0.46875 0 -0.84375 -0.140625q-0.375 -0.125 -0.65625 -0.375q-0.265625 -0.234375 -0.421875 -0.578125q-0.15625 -0.34375 -0.15625 -0.796875q0 -0.421875 0.125 -0.75q0.140625 -0.328125 0.390625 -0.5625q0.265625 -0.234375 0.640625 -0.359375q0.375 -0.125 0.859375 -0.125q0.453125 0 0.828125 0.125q0.390625 0.140625 0.65625 0.375q0.265625 0.25 0.421875 0.59375q0.15625 0.34375 0.15625 0.78125q0 0.421875 -0.140625 0.75q-0.125 0.34375 -0.375 0.578125q-0.25 0.234375 -0.625 0.359375q-0.375 0.125 -0.859375 0.125zm-0.03125 -0.703125q0.359375 0 0.625 -0.078125q0.28125 -0.078125 0.453125 -0.234375q0.1875 -0.140625 0.28125 -0.359375q0.09375 -0.203125 0.09375 -0.46875q0 -0.3125 -0.125 -0.53125q-0.125 -0.203125 -0.328125 -0.34375q-0.1875 -0.140625 -0.453125 -0.203125q-0.265625 -0.0625 -0.546875 -0.0625q-0.375 0 -0.65625 0.078125q-0.265625 0.078125 -0.453125 0.21875q-0.171875 0.15625 -0.265625 0.359375q-0.09375 0.21875 -0.09375 0.484375q0 0.296875 0.125 0.515625q0.125 0.21875 0.3125 0.359375q0.203125 0.140625 0.46875 0.203125q0.265625 0.0625 0.5625 0.0625zm3.0 3.0234375l0 -1.171875l0.546875 0l0 1.859375l-4.953125 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l4.40625 0zm-3.09375 2.8515625q0.5 0 0.890625 0.140625q0.390625 0.140625 0.65625 0.390625q0.265625 0.25 0.40625 0.59375q0.140625 0.359375 0.140625 0.796875q0 0.1875 -0.03125 0.359375q-0.015625 0.1875 -0.0625 0.375l1.640625 0l0 0.671875l-5.515625 0l0 -0.609375l0.75 -0.015625q-0.421875 -0.28125 -0.625 -0.625q-0.203125 -0.328125 -0.203125 -0.71875q0 -0.328125 0.140625 -0.59375q0.15625 -0.25 0.40625 -0.421875q0.25 -0.171875 0.609375 -0.265625q0.359375 -0.078125 0.796875 -0.078125zm0.046875 0.703125q-0.703125 0 -1.0625 0.203125q-0.34375 0.21875 -0.34375 0.59375q0 0.265625 0.21875 0.546875q0.234375 0.28125 0.6875 0.609375l1.828125 0q0.078125 -0.171875 0.109375 -0.375q0.046875 -0.203125 0.046875 -0.40625q0 -0.546875 -0.359375 -0.859375q-0.359375 -0.3125 -1.125 -0.3125z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m395.03674 408.08923l-0.28344727 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m395.03674 408.08923l-0.26940918 -65.6438" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m394.76733 342.44543l1.1292114 1.1199646l-1.1372681 -3.085144l-1.1118774 3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m381.79266 410.88452l0 65.19684l-26.204742 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m368.04153 415.8689q-0.515625 0 -0.90625 -0.15625q-0.390625 -0.140625 -0.65625 -0.40625q-0.25 -0.25 -0.390625 -0.609375q-0.125 -0.34375 -0.125 -0.75q0 -0.1875 0.015625 -0.375q0.015625 -0.1875 0.078125 -0.375l-1.65625 0l0 -0.6875l5.53125 0l0 0.609375l-0.65625 0.046875q0.40625 0.28125 0.5625 0.609375q0.171875 0.34375 0.171875 0.734375q0 0.328125 -0.140625 0.578125q-0.140625 0.265625 -0.40625 0.4375q-0.25 0.171875 -0.609375 0.25q-0.359375 0.09375 -0.8125 0.09375zm-0.03125 -0.703125q0.3125 0 0.5625 -0.046875q0.265625 -0.046875 0.4375 -0.140625q0.1875 -0.09375 0.296875 -0.25q0.109375 -0.15625 0.109375 -0.359375q0 -0.125 -0.046875 -0.265625q-0.046875 -0.125 -0.140625 -0.28125q-0.09375 -0.140625 -0.25 -0.296875q-0.15625 -0.15625 -0.390625 -0.328125l-1.90625 0q-0.078125 0.1875 -0.125 0.390625q-0.046875 0.203125 -0.046875 0.40625q0 0.546875 0.375 0.859375q0.375 0.3125 1.125 0.3125zm1.921875 1.8984375l0 0.625l-0.71875 0.015625q0.421875 0.359375 0.609375 0.6875q0.1875 0.34375 0.1875 0.6875q0 0.609375 -0.40625 0.921875q-0.390625 0.3125 -1.171875 0.296875l0 -0.6875q0.515625 0 0.75 -0.15625q0.234375 -0.15625 0.234375 -0.46875q0 -0.140625 -0.046875 -0.28125q-0.046875 -0.140625 -0.15625 -0.296875q-0.109375 -0.140625 -0.28125 -0.3125q-0.15625 -0.15625 -0.40625 -0.34375l-2.515625 0l0 -0.6875l3.921875 0zm-0.5625 5.5859375l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-3.5625 6.2421875q-0.46875 0 -0.84375 -0.140625q-0.375 -0.125 -0.65625 -0.375q-0.265625 -0.234375 -0.421875 -0.578125q-0.15625 -0.34375 -0.15625 -0.796875q0 -0.421875 0.125 -0.75q0.140625 -0.328125 0.390625 -0.5625q0.265625 -0.234375 0.640625 -0.359375q0.375 -0.125 0.859375 -0.125q0.453125 0 0.828125 0.125q0.390625 0.140625 0.65625 0.375q0.265625 0.25 0.421875 0.59375q0.15625 0.34375 0.15625 0.78125q0 0.421875 -0.140625 0.75q-0.125 0.34375 -0.375 0.578125q-0.25 0.234375 -0.625 0.359375q-0.375 0.125 -0.859375 0.125zm-0.03125 -0.703125q0.359375 0 0.625 -0.078125q0.28125 -0.078125 0.453125 -0.234375q0.1875 -0.140625 0.28125 -0.359375q0.09375 -0.203125 0.09375 -0.46875q0 -0.3125 -0.125 -0.53125q-0.125 -0.203125 -0.328125 -0.34375q-0.1875 -0.140625 -0.453125 -0.203125q-0.265625 -0.0625 -0.546875 -0.0625q-0.375 0 -0.65625 0.078125q-0.265625 0.078125 -0.453125 0.21875q-0.171875 0.15625 -0.265625 0.359375q-0.09375 0.21875 -0.09375 0.484375q0 0.296875 0.125 0.515625q0.125 0.21875 0.3125 0.359375q0.203125 0.140625 0.46875 0.203125q0.265625 0.0625 0.5625 0.0625zm1.953125 1.8359375l0 0.625l-0.71875 0.015625q0.421875 0.359375 0.609375 0.6875q0.1875 0.34375 0.1875 0.6875q0 0.609375 -0.40625 0.921875q-0.390625 0.3125 -1.171875 0.296875l0 -0.6875q0.515625 0 0.75 -0.15625q0.234375 -0.15625 0.234375 -0.46875q0 -0.140625 -0.046875 -0.28125q-0.046875 -0.140625 -0.15625 -0.296875q-0.109375 -0.140625 -0.28125 -0.3125q-0.15625 -0.15625 -0.40625 -0.34375l-2.515625 0l0 -0.6875l3.921875 0zm-0.5625 5.5859375l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-5.5 5.9765625q-0.0625 -0.21875 -0.09375 -0.46875q-0.03125 -0.25 -0.03125 -0.5q0 -0.734375 0.328125 -1.109375q0.34375 -0.359375 1.046875 -0.359375l2.046875 0l0 -1.09375l0.5625 0l0 1.09375l1.078125 0l0.171875 0.6875l-1.25 0l0 1.75l-0.5625 0l0 -1.75l-2.0 0q-0.421875 0 -0.640625 0.21875q-0.203125 0.21875 -0.203125 0.65625q0 0.1875 0.03125 0.40625q0.03125 0.234375 0.09375 0.46875l-0.578125 0zm3.859375 4.7265625l-3.5 -1.328125q-0.546875 -0.203125 -0.921875 -0.4375q-0.390625 -0.21875 -0.640625 -0.484375q-0.25 -0.25 -0.359375 -0.5625q-0.125 -0.3125 -0.125 -0.703125q0 -0.09375 0 -0.1875q0 -0.078125 0.015625 -0.171875l0.609375 0q0 0.078125 -0.015625 0.171875q-0.015625 0.109375 -0.015625 0.234375q0 0.1875 0.0625 0.34375q0.046875 0.15625 0.171875 0.296875q0.125 0.15625 0.328125 0.28125q0.1875 0.140625 0.46875 0.265625l3.921875 -1.5625l0 0.765625l-2.59375 1.0l-0.609375 0.1875l0.625 0.234375l2.578125 0.921875l0 0.734375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m368.83203 408.9895l-0.28347778 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m368.83203 408.9895l-0.26940918 -65.6438" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m368.56262 343.3457l1.1291809 1.1199341l-1.1372375 -3.0851135l-1.111908 3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m349.8504 410.88452l0 65.19684l-26.204742 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m337.4274 413.85327l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-3.390625 6.1328125q-0.140625 0 -0.25 0q-0.09375 0 -0.171875 -0.015625l0 -2.75q-0.609375 0 -0.9375 0.328125q-0.3125 0.34375 -0.3125 0.96875q0 0.171875 0.015625 0.34375q0.015625 0.171875 0.03125 0.328125q0.03125 0.171875 0.046875 0.3125q0.03125 0.15625 0.078125 0.28125l-0.5625 0q-0.078125 -0.28125 -0.125 -0.640625q-0.0625 -0.34375 -0.0625 -0.71875q0 -0.5 0.140625 -0.875q0.140625 -0.359375 0.390625 -0.59375q0.265625 -0.21875 0.640625 -0.34375q0.390625 -0.109375 0.859375 -0.109375q0.421875 0 0.78125 0.125q0.375 0.125 0.65625 0.34375q0.28125 0.234375 0.4375 0.5625q0.171875 0.328125 0.171875 0.75q0 0.421875 -0.140625 0.734375q-0.125 0.3125 -0.359375 0.53125q-0.234375 0.21875 -0.578125 0.328125q-0.328125 0.109375 -0.75 0.109375zm0.09375 -0.703125q0.265625 0.015625 0.484375 -0.046875q0.21875 -0.0625 0.375 -0.203125q0.15625 -0.125 0.234375 -0.328125q0.09375 -0.1875 0.09375 -0.453125q0 -0.21875 -0.09375 -0.40625q-0.078125 -0.171875 -0.234375 -0.3125q-0.15625 -0.125 -0.375 -0.21875q-0.21875 -0.078125 -0.484375 -0.09375l0 2.0625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m336.90552 406.97113l0 -67.811035" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m336.90552 406.97113l0 -64.38394" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m336.90552 342.5872l1.1245728 1.1245728l-1.1245728 -3.0897522l-1.1246033 3.0897522z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m445.84253 410.88452l0 65.19684l-26.204742 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m433.41953 413.85327l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-1.640625 2.9765625l0 0.625l-0.71875 0.015625q0.421875 0.359375 0.609375 0.6875q0.1875 0.34375 0.1875 0.6875q0 0.609375 -0.40625 0.921875q-0.390625 0.3125 -1.171875 0.296875l0 -0.6875q0.515625 0 0.75 -0.15625q0.234375 -0.15625 0.234375 -0.46875q0 -0.140625 -0.046875 -0.28125q-0.046875 -0.140625 -0.15625 -0.296875q-0.109375 -0.140625 -0.28125 -0.3125q-0.15625 -0.15625 -0.40625 -0.34375l-2.515625 0l0 -0.6875l3.921875 0zm-2.046875 4.0390625q0.421875 0 0.796875 0.109375q0.390625 0.125 0.671875 0.34375q0.296875 0.234375 0.453125 0.59375q0.171875 0.375 0.171875 0.875q0 0.203125 -0.03125 0.390625q-0.03125 0.203125 -0.09375 0.421875l0.15625 0.59375l-5.609375 0l0 -0.671875l1.484375 0l0.84375 0.03125q-0.796875 -0.5625 -0.796875 -1.328125q0 -0.34375 0.140625 -0.59375q0.15625 -0.25 0.40625 -0.421875q0.265625 -0.171875 0.625 -0.265625q0.359375 -0.078125 0.78125 -0.078125zm0.046875 0.703125q-0.328125 0 -0.59375 0.046875q-0.25 0.046875 -0.4375 0.140625q-0.1875 0.109375 -0.28125 0.25q-0.09375 0.15625 -0.09375 0.359375q0 0.265625 0.21875 0.546875q0.234375 0.28125 0.6875 0.609375l1.828125 0q0.078125 -0.15625 0.125 -0.359375q0.046875 -0.203125 0.046875 -0.421875q0 -0.578125 -0.390625 -0.875q-0.375 -0.296875 -1.109375 -0.296875zm-3.53125 7.6796875l0 -4.40625l0.5625 0l0 4.40625l-0.5625 0zm4.96875 1.9609375l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-3.6875 2.6171875q0.5 0 0.890625 0.140625q0.390625 0.140625 0.65625 0.390625q0.265625 0.25 0.40625 0.59375q0.140625 0.359375 0.140625 0.796875q0 0.1875 -0.03125 0.359375q-0.015625 0.1875 -0.0625 0.375l1.640625 0l0 0.671875l-5.515625 0l0 -0.609375l0.75 -0.015625q-0.421875 -0.28125 -0.625 -0.625q-0.203125 -0.328125 -0.203125 -0.71875q0 -0.328125 0.140625 -0.59375q0.15625 -0.25 0.40625 -0.421875q0.25 -0.171875 0.609375 -0.265625q0.359375 -0.078125 0.796875 -0.078125zm0.046875 0.703125q-0.703125 0 -1.0625 0.203125q-0.34375 0.21875 -0.34375 0.59375q0 0.265625 0.21875 0.546875q0.234375 0.28125 0.6875 0.609375l1.828125 0q0.078125 -0.171875 0.109375 -0.375q0.046875 -0.203125 0.046875 -0.40625q0 -0.546875 -0.359375 -0.859375q-0.359375 -0.3125 -1.125 -0.3125z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m432.8819 408.9895l-0.28347778 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m432.86783 405.56247l-0.26940918 -65.64383" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m432.86783 405.56244l-1.1291809 -1.1199646l1.1372375 3.085144l1.111908 -3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m207.6693 410.88452l0 65.19684l-26.204727 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m196.85568 413.85327l0 -1.171875l0.546875 0l0 1.859375l-4.953125 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l4.40625 0zm-2.796875 6.3671875q-0.140625 0 -0.25 0q-0.09375 0 -0.171875 -0.015625l0 -2.75q-0.609375 0 -0.9375 0.328125q-0.3125 0.34375 -0.3125 0.96875q0 0.171875 0.015625 0.34375q0.015625 0.171875 0.03125 0.328125q0.03125 0.171875 0.046875 0.3125q0.03125 0.15625 0.078125 0.28125l-0.5625 0q-0.078125 -0.28125 -0.125 -0.640625q-0.0625 -0.34375 -0.0625 -0.71875q0 -0.5 0.140625 -0.875q0.140625 -0.359375 0.390625 -0.59375q0.265625 -0.21875 0.640625 -0.34375q0.390625 -0.109375 0.859375 -0.109375q0.421875 0 0.78125 0.125q0.375 0.125 0.65625 0.34375q0.28125 0.234375 0.4375 0.5625q0.171875 0.328125 0.171875 0.75q0 0.421875 -0.140625 0.734375q-0.125 0.3125 -0.359375 0.53125q-0.234375 0.21875 -0.578125 0.328125q-0.328125 0.109375 -0.75 0.109375zm0.09375 -0.703125q0.265625 0.015625 0.484375 -0.046875q0.21875 -0.0625 0.375 -0.203125q0.15625 -0.125 0.234375 -0.328125q0.09375 -0.1875 0.09375 -0.453125q0 -0.21875 -0.09375 -0.40625q-0.078125 -0.171875 -0.234375 -0.3125q-0.15625 -0.125 -0.375 -0.21875q-0.21875 -0.078125 -0.484375 -0.09375l0 2.0625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m194.70866 408.9895l-0.28346252 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m194.70866 408.9895l-0.26939392 -65.6438" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m194.43925 343.3457l1.1291962 1.1199341l-1.1372528 -3.0851135l-1.1118927 3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m224.89764 410.88452l0 65.19684l-26.204727 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m209.2559 415.5564q-0.09375 -0.265625 -0.140625 -0.546875q-0.0625 -0.28125 -0.0625 -0.578125q0 -0.921875 0.5 -1.421875q0.515625 -0.5 1.484375 -0.5q0.46875 0 0.84375 0.140625q0.375 0.140625 0.640625 0.40625q0.28125 0.265625 0.421875 0.625q0.15625 0.359375 0.15625 0.796875q0 0.3125 -0.046875 0.578125q-0.046875 0.265625 -0.140625 0.5l-0.65625 0q0.140625 -0.25 0.203125 -0.515625q0.0625 -0.265625 0.0625 -0.546875q0 -0.265625 -0.109375 -0.5q-0.09375 -0.21875 -0.28125 -0.40625q-0.1875 -0.171875 -0.46875 -0.28125q-0.265625 -0.09375 -0.59375 -0.09375q-0.71875 0 -1.078125 0.34375q-0.34375 0.34375 -0.34375 0.96875q0 0.265625 0.0625 0.53125q0.0625 0.265625 0.1875 0.5l-0.640625 0zm4.828125 2.6953125l0 -1.171875l0.546875 0l0 1.859375l-4.953125 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l4.40625 0zm-4.96875 5.5703125l0.53125 -0.015625q-0.3125 -0.3125 -0.46875 -0.640625q-0.140625 -0.328125 -0.140625 -0.703125q0 -0.328125 0.09375 -0.578125q0.09375 -0.234375 0.234375 -0.390625q0.15625 -0.140625 0.359375 -0.21875q0.203125 -0.078125 0.4375 -0.078125q0.59375 0 0.921875 0.4375q0.34375 0.453125 0.34375 1.3125l0 0.8125l0.34375 0q0.34375 0 0.546875 -0.234375q0.21875 -0.21875 0.21875 -0.671875q0 -0.328125 -0.078125 -0.65625q-0.078125 -0.328125 -0.21875 -0.671875l0.625 0q0.046875 0.140625 0.078125 0.296875q0.046875 0.15625 0.078125 0.328125q0.046875 0.171875 0.0625 0.359375q0.03125 0.203125 0.03125 0.390625q0 0.359375 -0.078125 0.640625q-0.078125 0.296875 -0.25 0.484375q-0.15625 0.203125 -0.40625 0.296875q-0.234375 0.109375 -0.5625 0.109375l-2.703125 0l0 -0.609375zm1.78125 -0.0625l0 -0.875q0 -0.25 -0.046875 -0.4375q-0.046875 -0.171875 -0.140625 -0.296875q-0.09375 -0.109375 -0.234375 -0.171875q-0.125 -0.0625 -0.28125 -0.0625q-0.125 0 -0.234375 0.03125q-0.09375 0.046875 -0.171875 0.125q-0.078125 0.078125 -0.125 0.203125q-0.046875 0.125 -0.046875 0.296875q0 0.234375 0.140625 0.53125q0.140625 0.3125 0.453125 0.65625l0.6875 0zm1.578125 3.2890625l0 -1.171875l0.5625 0l0 1.859375l-3.359375 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l2.796875 0zm2.203125 0.234375q0 0.109375 -0.046875 0.203125q-0.03125 0.109375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.109375q-0.09375 0.046875 -0.203125 0.046875q-0.109375 0 -0.203125 -0.046875q-0.09375 -0.03125 -0.171875 -0.109375q-0.078125 -0.0625 -0.125 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.21875q0.046875 -0.09375 0.125 -0.171875q0.078125 -0.0625 0.171875 -0.109375q0.09375 -0.03125 0.203125 -0.03125q0.109375 0 0.203125 0.03125q0.109375 0.046875 0.171875 0.109375q0.078125 0.078125 0.109375 0.171875q0.046875 0.109375 0.046875 0.21875zm-5.5625 5.6171875l2.8125 0q0.1875 0 0.296875 -0.015625q0.125 -0.015625 0.1875 -0.046875q0.078125 -0.015625 0.09375 -0.0625q0.03125 -0.046875 0.03125 -0.109375q0 -0.078125 -0.046875 -0.15625q-0.046875 -0.0625 -0.15625 -0.140625q-0.09375 -0.078125 -0.265625 -0.171875q-0.171875 -0.078125 -0.4375 -0.203125l-2.515625 0l0 -0.625l2.75 0q0.203125 0 0.328125 -0.015625q0.140625 -0.015625 0.21875 -0.046875q0.078125 -0.03125 0.09375 -0.078125q0.03125 -0.046875 0.03125 -0.109375q0 -0.0625 -0.046875 -0.125q-0.03125 -0.0625 -0.140625 -0.140625q-0.09375 -0.078125 -0.265625 -0.171875q-0.171875 -0.09375 -0.453125 -0.21875l-2.515625 0l0 -0.625l3.921875 0l0 0.515625l-0.75 0.03125q0.234375 0.09375 0.390625 0.1875q0.15625 0.109375 0.25 0.203125q0.09375 0.109375 0.140625 0.21875q0.046875 0.109375 0.046875 0.25q0 0.328125 -0.21875 0.484375q-0.203125 0.171875 -0.640625 0.171875q0.203125 0.09375 0.359375 0.171875q0.171875 0.09375 0.265625 0.1875q0.109375 0.109375 0.171875 0.234375q0.0625 0.125 0.0625 0.296875q0 0.734375 -1.140625 0.734375l-2.859375 0l0 -0.625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m211.93701 408.9895l-0.28346252 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m211.93701 408.9895l-0.26940918 -65.6438" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m211.6676 343.3457l1.1291962 1.1199341l-1.1372528 -3.0851135l-1.1118927 3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m237.85826 410.88452l0 65.19684l-26.204712 0l0 -65.19684z" fill-rule="evenodd"/><path fill="#000000" d="m222.21654 415.5564q-0.09375 -0.265625 -0.140625 -0.546875q-0.0625 -0.28125 -0.0625 -0.578125q0 -0.921875 0.5 -1.421875q0.515625 -0.5 1.484375 -0.5q0.46875 0 0.84375 0.140625q0.375 0.140625 0.640625 0.40625q0.28125 0.265625 0.421875 0.625q0.15625 0.359375 0.15625 0.796875q0 0.3125 -0.046875 0.578125q-0.046875 0.265625 -0.140625 0.5l-0.65625 0q0.140625 -0.25 0.203125 -0.515625q0.0625 -0.265625 0.0625 -0.546875q0 -0.265625 -0.109375 -0.5q-0.09375 -0.21875 -0.28125 -0.40625q-0.1875 -0.171875 -0.46875 -0.28125q-0.265625 -0.09375 -0.59375 -0.09375q-0.71875 0 -1.078125 0.34375q-0.34375 0.34375 -0.34375 0.96875q0 0.265625 0.0625 0.53125q0.0625 0.265625 0.1875 0.5l-0.640625 0zm1.859375 4.7734375q-0.46875 0 -0.84375 -0.140625q-0.375 -0.125 -0.65625 -0.375q-0.265625 -0.234375 -0.421875 -0.578125q-0.15625 -0.34375 -0.15625 -0.796875q0 -0.421875 0.125 -0.75q0.140625 -0.328125 0.390625 -0.5625q0.265625 -0.234375 0.640625 -0.359375q0.375 -0.125 0.859375 -0.125q0.453125 0 0.828125 0.125q0.390625 0.140625 0.65625 0.375q0.265625 0.25 0.421875 0.59375q0.15625 0.34375 0.15625 0.78125q0 0.421875 -0.140625 0.75q-0.125 0.34375 -0.375 0.578125q-0.25 0.234375 -0.625 0.359375q-0.375 0.125 -0.859375 0.125zm-0.03125 -0.703125q0.359375 0 0.625 -0.078125q0.28125 -0.078125 0.453125 -0.234375q0.1875 -0.140625 0.28125 -0.359375q0.09375 -0.203125 0.09375 -0.46875q0 -0.3125 -0.125 -0.53125q-0.125 -0.203125 -0.328125 -0.34375q-0.1875 -0.140625 -0.453125 -0.203125q-0.265625 -0.0625 -0.546875 -0.0625q-0.375 0 -0.65625 0.078125q-0.265625 0.078125 -0.453125 0.21875q-0.171875 0.15625 -0.265625 0.359375q-0.09375 0.21875 -0.09375 0.484375q0 0.296875 0.125 0.515625q0.125 0.21875 0.3125 0.359375q0.203125 0.140625 0.46875 0.203125q0.265625 0.0625 0.5625 0.0625zm-1.96875 4.4765625l2.8125 0q0.1875 0 0.296875 -0.015625q0.125 -0.015625 0.1875 -0.046875q0.078125 -0.015625 0.09375 -0.0625q0.03125 -0.046875 0.03125 -0.109375q0 -0.078125 -0.046875 -0.15625q-0.046875 -0.0625 -0.15625 -0.140625q-0.09375 -0.078125 -0.265625 -0.171875q-0.171875 -0.078125 -0.4375 -0.203125l-2.515625 0l0 -0.625l2.75 0q0.203125 0 0.328125 -0.015625q0.140625 -0.015625 0.21875 -0.046875q0.078125 -0.03125 0.09375 -0.078125q0.03125 -0.046875 0.03125 -0.109375q0 -0.0625 -0.046875 -0.125q-0.03125 -0.0625 -0.140625 -0.140625q-0.09375 -0.078125 -0.265625 -0.171875q-0.171875 -0.09375 -0.453125 -0.21875l-2.515625 0l0 -0.625l3.921875 0l0 0.515625l-0.75 0.03125q0.234375 0.09375 0.390625 0.1875q0.15625 0.109375 0.25 0.203125q0.09375 0.109375 0.140625 0.21875q0.046875 0.109375 0.046875 0.25q0 0.328125 -0.21875 0.484375q-0.203125 0.171875 -0.640625 0.171875q0.203125 0.09375 0.359375 0.171875q0.171875 0.09375 0.265625 0.1875q0.109375 0.109375 0.171875 0.234375q0.0625 0.125 0.0625 0.296875q0 0.734375 -1.140625 0.734375l-2.859375 0l0 -0.625zm2.03125 4.9609375q-0.515625 0 -0.90625 -0.15625q-0.390625 -0.140625 -0.65625 -0.40625q-0.25 -0.25 -0.390625 -0.609375q-0.125 -0.34375 -0.125 -0.75q0 -0.1875 0.015625 -0.375q0.015625 -0.1875 0.078125 -0.375l-1.65625 0l0 -0.6875l5.53125 0l0 0.609375l-0.65625 0.046875q0.40625 0.28125 0.5625 0.609375q0.171875 0.34375 0.171875 0.734375q0 0.328125 -0.140625 0.578125q-0.140625 0.265625 -0.40625 0.4375q-0.25 0.171875 -0.609375 0.25q-0.359375 0.09375 -0.8125 0.09375zm-0.03125 -0.703125q0.3125 0 0.5625 -0.046875q0.265625 -0.046875 0.4375 -0.140625q0.1875 -0.09375 0.296875 -0.25q0.109375 -0.15625 0.109375 -0.359375q0 -0.125 -0.046875 -0.265625q-0.046875 -0.125 -0.140625 -0.28125q-0.09375 -0.140625 -0.25 -0.296875q-0.15625 -0.15625 -0.390625 -0.328125l-1.90625 0q-0.078125 0.1875 -0.125 0.390625q-0.046875 0.203125 -0.046875 0.40625q0 0.546875 0.375 0.859375q0.375 0.3125 1.125 0.3125zm2.96875 3.0859375l0 -1.171875l0.546875 0l0 1.859375l-4.953125 0l0 1.15625l-0.5625 0l0 -3.140625l0.5625 0l0 1.296875l4.40625 0zm-2.796875 6.3671875q-0.140625 0 -0.25 0q-0.09375 0 -0.171875 -0.015625l0 -2.75q-0.609375 0 -0.9375 0.328125q-0.3125 0.34375 -0.3125 0.96875q0 0.171875 0.015625 0.34375q0.015625 0.171875 0.03125 0.328125q0.03125 0.171875 0.046875 0.3125q0.03125 0.15625 0.078125 0.28125l-0.5625 0q-0.078125 -0.28125 -0.125 -0.640625q-0.0625 -0.34375 -0.0625 -0.71875q0 -0.5 0.140625 -0.875q0.140625 -0.359375 0.390625 -0.59375q0.265625 -0.21875 0.640625 -0.34375q0.390625 -0.109375 0.859375 -0.109375q0.421875 0 0.78125 0.125q0.375 0.125 0.65625 0.34375q0.28125 0.234375 0.4375 0.5625q0.171875 0.328125 0.171875 0.75q0 0.421875 -0.140625 0.734375q-0.125 0.3125 -0.359375 0.53125q-0.234375 0.21875 -0.578125 0.328125q-0.328125 0.109375 -0.75 0.109375zm0.09375 -0.703125q0.265625 0.015625 0.484375 -0.046875q0.21875 -0.0625 0.375 -0.203125q0.15625 -0.125 0.234375 -0.328125q0.09375 -0.1875 0.09375 -0.453125q0 -0.21875 -0.09375 -0.40625q-0.078125 -0.171875 -0.234375 -0.3125q-0.15625 -0.125 -0.375 -0.21875q-0.21875 -0.078125 -0.484375 -0.09375l0 2.0625zm-2.203125 4.9453125q-0.0625 -0.21875 -0.09375 -0.46875q-0.03125 -0.25 -0.03125 -0.5q0 -0.734375 0.328125 -1.109375q0.34375 -0.359375 1.046875 -0.359375l2.046875 0l0 -1.09375l0.5625 0l0 1.09375l1.078125 0l0.171875 0.6875l-1.25 0l0 1.75l-0.5625 0l0 -1.75l-2.0 0q-0.421875 0 -0.640625 0.21875q-0.203125 0.21875 -0.203125 0.65625q0 0.1875 0.03125 0.40625q0.03125 0.234375 0.09375 0.46875l-0.578125 0zm2.109375 4.5546875q-0.140625 0 -0.25 0q-0.09375 0 -0.171875 -0.015625l0 -2.75q-0.609375 0 -0.9375 0.328125q-0.3125 0.34375 -0.3125 0.96875q0 0.171875 0.015625 0.34375q0.015625 0.171875 0.03125 0.328125q0.03125 0.171875 0.046875 0.3125q0.03125 0.15625 0.078125 0.28125l-0.5625 0q-0.078125 -0.28125 -0.125 -0.640625q-0.0625 -0.34375 -0.0625 -0.71875q0 -0.5 0.140625 -0.875q0.140625 -0.359375 0.390625 -0.59375q0.265625 -0.21875 0.640625 -0.34375q0.390625 -0.109375 0.859375 -0.109375q0.421875 0 0.78125 0.125q0.375 0.125 0.65625 0.34375q0.28125 0.234375 0.4375 0.5625q0.171875 0.328125 0.171875 0.75q0 0.421875 -0.140625 0.734375q-0.125 0.3125 -0.359375 0.53125q-0.234375 0.21875 -0.578125 0.328125q-0.328125 0.109375 -0.75 0.109375zm0.09375 -0.703125q0.265625 0.015625 0.484375 -0.046875q0.21875 -0.0625 0.375 -0.203125q0.15625 -0.125 0.234375 -0.328125q0.09375 -0.1875 0.09375 -0.453125q0 -0.21875 -0.09375 -0.40625q-0.078125 -0.171875 -0.234375 -0.3125q-0.15625 -0.125 -0.375 -0.21875q-0.21875 -0.078125 -0.484375 -0.09375l0 2.0625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m224.89764 408.9895l-0.28347778 -69.07086" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m224.89764 408.9895l-0.26940918 -65.6438" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m224.62823 343.3457l1.1291962 1.1199341l-1.1372528 -3.0851135l-1.1118927 3.0943604z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m108.11286 425.59317l52.34646 0l0 35.77954l-52.34646 0z" fill-rule="evenodd"/><path fill="#000000" d="m126.198845 438.28754l-1.765625 0l0 5.265625l-0.8125 0l0 -5.265625l-1.765625 0l0 -0.6875l4.34375 0l0 0.6875zm4.8786545 5.265625l-3.4218826 0l0 -5.953125l0.8281326 0l0 5.265625l2.59375 0l0 0.6875zm4.566147 -2.109375l-2.71875 0l0 -0.75l2.71875 0l0 0.75zm5.847397 0.03125q0 0.5 -0.140625 0.90625q-0.140625 0.390625 -0.40625 0.671875q-0.265625 0.28125 -0.65625 0.4375q-0.390625 0.140625 -0.90625 0.140625q-0.546875 0 -0.9375 -0.140625q-0.390625 -0.140625 -0.640625 -0.40625q-0.234375 -0.28125 -0.34375 -0.640625q-0.109375 -0.375 -0.109375 -0.84375l0 -4.0l0.8125 0l0 3.9375q0 0.359375 0.0625 0.625q0.0625 0.25 0.203125 0.4375q0.15625 0.171875 0.390625 0.265625q0.25 0.09375 0.59375 0.09375q0.65625 0 0.953125 -0.375q0.3125 -0.375 0.3125 -1.046875l0 -3.9375l0.8125 0l0 3.875zm4.972397 2.078125l-3.421875 0l0 -5.953125l0.828125 0l0 5.265625l2.59375 0l0 0.6875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m488.24408 139.77953l62.26776 0l0 35.779526l-62.26776 0z" fill-rule="evenodd"/><path fill="#000000" d="m518.14984 153.81766l-1.34375 0l0 -0.65625l2.15625 0l0 3.921875l1.359375 0l0 0.65625l-3.671875 0l0 -0.65625l1.5 0l0 -3.265625zm0.28125 -2.5625q0.140625 0 0.25 0.046875q0.109375 0.046875 0.1875 0.140625q0.09375 0.078125 0.140625 0.1875q0.046875 0.109375 0.046875 0.25q0 0.125 -0.046875 0.234375q-0.046875 0.109375 -0.140625 0.203125q-0.078125 0.078125 -0.1875 0.125q-0.109375 0.046875 -0.25 0.046875q-0.125 0 -0.25 -0.046875q-0.109375 -0.046875 -0.203125 -0.125q-0.078125 -0.09375 -0.125 -0.203125q-0.046875 -0.109375 -0.046875 -0.234375q0 -0.140625 0.046875 -0.25q0.046875 -0.109375 0.125 -0.1875q0.09375 -0.09375 0.203125 -0.140625q0.125 -0.046875 0.25 -0.046875zm3.487976 1.90625l0.71875 0l0.015625 0.84375q0.40625 -0.484375 0.796875 -0.703125q0.40625 -0.21875 0.796875 -0.21875q0.71875 0 1.078125 0.46875q0.375 0.453125 0.34375 1.359375l-0.796875 0q0.015625 -0.609375 -0.1875 -0.875q-0.1875 -0.265625 -0.546875 -0.265625q-0.15625 0 -0.328125 0.0625q-0.15625 0.046875 -0.328125 0.171875q-0.171875 0.125 -0.359375 0.328125q-0.1875 0.1875 -0.40625 0.46875l0 2.9375l-0.796875 0l0 -4.578125zm4.706787 2.390625q0 -0.5 0.125 -0.9375q0.125 -0.4375 0.390625 -0.765625q0.28125 -0.34375 0.703125 -0.53125q0.421875 -0.203125 1.015625 -0.203125q0.234375 0 0.453125 0.03125q0.234375 0.03125 0.484375 0.109375l0.703125 -0.171875l0 6.53125l-0.796875 0l0 -1.734375l0.046875 -0.984375q-0.65625 0.921875 -1.546875 0.921875q-0.390625 0 -0.6875 -0.15625q-0.296875 -0.171875 -0.5 -0.46875q-0.203125 -0.296875 -0.296875 -0.71875q-0.09375 -0.421875 -0.09375 -0.921875zm0.8125 -0.046875q0 0.375 0.046875 0.6875q0.0625 0.296875 0.171875 0.515625q0.125 0.203125 0.296875 0.328125q0.171875 0.109375 0.40625 0.109375q0.3125 0 0.640625 -0.265625q0.34375 -0.28125 0.703125 -0.796875l0 -2.125q-0.1875 -0.09375 -0.421875 -0.140625q-0.21875 -0.0625 -0.484375 -0.0625q-0.65625 0 -1.015625 0.453125q-0.34375 0.4375 -0.34375 1.296875zm8.941162 4.109375l-5.125 0l0 -0.65625l5.125 0l0 0.65625zm4.706787 -4.203125q0 0.53125 -0.15625 0.984375q-0.140625 0.4375 -0.421875 0.765625q-0.28125 0.3125 -0.6875 0.484375q-0.40625 0.171875 -0.921875 0.171875q-0.484375 0 -0.875 -0.140625q-0.390625 -0.15625 -0.671875 -0.453125q-0.265625 -0.296875 -0.40625 -0.734375q-0.140625 -0.4375 -0.140625 -1.015625q0 -0.53125 0.140625 -0.96875q0.15625 -0.4375 0.4375 -0.75q0.28125 -0.3125 0.6875 -0.484375q0.40625 -0.1875 0.921875 -0.1875q0.5 0 0.875 0.15625q0.390625 0.15625 0.65625 0.453125q0.28125 0.28125 0.421875 0.71875q0.140625 0.4375 0.140625 1.0zm-0.796875 0.046875q0 -0.421875 -0.09375 -0.734375q-0.09375 -0.328125 -0.28125 -0.53125q-0.171875 -0.21875 -0.421875 -0.328125q-0.234375 -0.109375 -0.546875 -0.109375q-0.359375 0 -0.609375 0.140625q-0.25 0.140625 -0.421875 0.375q-0.15625 0.234375 -0.234375 0.546875q-0.0625 0.296875 -0.0625 0.640625q0 0.421875 0.09375 0.75q0.09375 0.3125 0.265625 0.53125q0.171875 0.203125 0.40625 0.3125q0.25 0.09375 0.5625 0.09375q0.359375 0 0.609375 -0.125q0.25 -0.140625 0.40625 -0.375q0.171875 -0.234375 0.25 -0.53125q0.078125 -0.3125 0.078125 -0.65625z" fill-rule="nonzero"/><path fill="#000000" d="m502.7639 164.81766l-1.34375 0l0 -0.65625l2.15625 0l0 3.921875l1.359375 0l0 0.65625l-3.671875 0l0 -0.65625l1.5 0l0 -3.265625zm0.28125 -2.5625q0.140625 0 0.25 0.046875q0.109375 0.046875 0.1875 0.140625q0.09375 0.078125 0.140625 0.1875q0.046875 0.109375 0.046875 0.25q0 0.125 -0.046875 0.234375q-0.046875 0.109375 -0.140625 0.203125q-0.078125 0.078125 -0.1875 0.125q-0.109375 0.046875 -0.25 0.046875q-0.125 0 -0.25 -0.046875q-0.109375 -0.046875 -0.203125 -0.125q-0.078125 -0.09375 -0.125 -0.203125q-0.046875 -0.109375 -0.046875 -0.234375q0 -0.140625 0.046875 -0.25q0.046875 -0.109375 0.125 -0.1875q0.09375 -0.09375 0.203125 -0.140625q0.125 -0.046875 0.25 -0.046875zm3.4880066 1.90625l0.71875 0l0.015625 0.84375q0.40625 -0.484375 0.796875 -0.703125q0.40625 -0.21875 0.796875 -0.21875q0.71875 0 1.078125 0.46875q0.375 0.453125 0.34375 1.359375l-0.796875 0q0.015625 -0.609375 -0.1875 -0.875q-0.1875 -0.265625 -0.546875 -0.265625q-0.15625 0 -0.328125 0.0625q-0.15625 0.046875 -0.328125 0.171875q-0.171875 0.125 -0.359375 0.328125q-0.1875 0.1875 -0.40625 0.46875l0 2.9375l-0.796875 0l0 -4.578125zm4.706787 2.390625q0 -0.5 0.125 -0.9375q0.125 -0.4375 0.390625 -0.765625q0.28125 -0.34375 0.703125 -0.53125q0.421875 -0.203125 1.015625 -0.203125q0.234375 0 0.453125 0.03125q0.234375 0.03125 0.484375 0.109375l0.703125 -0.171875l0 6.53125l-0.796875 0l0 -1.734375l0.046875 -0.984375q-0.65625 0.921875 -1.546875 0.921875q-0.390625 0 -0.6875 -0.15625q-0.296875 -0.171875 -0.5 -0.46875q-0.203125 -0.296875 -0.296875 -0.71875q-0.09375 -0.421875 -0.09375 -0.921875zm0.8125 -0.046875q0 0.375 0.046875 0.6875q0.0625 0.296875 0.171875 0.515625q0.125 0.203125 0.296875 0.328125q0.171875 0.109375 0.40625 0.109375q0.3125 0 0.640625 -0.265625q0.34375 -0.28125 0.703125 -0.796875l0 -2.125q-0.1875 -0.09375 -0.421875 -0.140625q-0.21875 -0.0625 -0.484375 -0.0625q-0.65625 0 -1.015625 0.453125q-0.34375 0.4375 -0.34375 1.296875zm8.941162 4.109375l-5.125 0l0 -0.65625l5.125 0l0 0.65625zm2.284851 -5.796875l-1.34375 0l0 -0.65625l2.15625 0l0 3.921875l1.359375 0l0 0.65625l-3.671875 0l0 -0.65625l1.5 0l0 -3.265625zm0.28125 -2.5625q0.140625 0 0.25 0.046875q0.109375 0.046875 0.1875 0.140625q0.09375 0.078125 0.140625 0.1875q0.046875 0.109375 0.046875 0.25q0 0.125 -0.046875 0.234375q-0.046875 0.109375 -0.140625 0.203125q-0.078125 0.078125 -0.1875 0.125q-0.109375 0.046875 -0.25 0.046875q-0.125 0 -0.25 -0.046875q-0.109375 -0.046875 -0.203125 -0.125q-0.078125 -0.09375 -0.125 -0.203125q-0.046875 -0.109375 -0.046875 -0.234375q0 -0.140625 0.046875 -0.25q0.046875 -0.109375 0.125 -0.1875q0.09375 -0.09375 0.203125 -0.140625q0.125 -0.046875 0.25 -0.046875zm3.066162 4.296875q0 -0.59375 0.15625 -1.046875q0.15625 -0.453125 0.453125 -0.75q0.296875 -0.3125 0.703125 -0.46875q0.421875 -0.171875 0.921875 -0.171875q0.21875 0 0.421875 0.03125q0.21875 0.015625 0.421875 0.078125l0 -1.921875l0.796875 0l0 6.4375l-0.703125 0l-0.03125 -0.859375q-0.328125 0.484375 -0.71875 0.71875q-0.390625 0.21875 -0.84375 0.21875q-0.390625 0 -0.6875 -0.15625q-0.296875 -0.171875 -0.5 -0.46875q-0.1875 -0.296875 -0.296875 -0.71875q-0.09375 -0.421875 -0.09375 -0.921875zm0.8125 -0.046875q0 0.828125 0.234375 1.234375q0.25 0.40625 0.6875 0.40625q0.3125 0 0.640625 -0.265625q0.34375 -0.28125 0.703125 -0.796875l0 -2.125q-0.1875 -0.09375 -0.4375 -0.140625q-0.234375 -0.046875 -0.46875 -0.046875q-0.640625 0 -1.0 0.421875q-0.359375 0.40625 -0.359375 1.3125zm8.941162 4.109375l-5.125 0l0 -0.65625l5.125 0l0 0.65625zm4.706787 -4.203125q0 0.53125 -0.15625 0.984375q-0.140625 0.4375 -0.421875 0.765625q-0.28125 0.3125 -0.6875 0.484375q-0.40625 0.171875 -0.921875 0.171875q-0.484375 0 -0.875 -0.140625q-0.390625 -0.15625 -0.671875 -0.453125q-0.265625 -0.296875 -0.40625 -0.734375q-0.140625 -0.4375 -0.140625 -1.015625q0 -0.53125 0.140625 -0.96875q0.15625 -0.4375 0.4375 -0.75q0.28125 -0.3125 0.6875 -0.484375q0.40625 -0.1875 0.921875 -0.1875q0.5 0 0.875 0.15625q0.390625 0.15625 0.65625 0.453125q0.28125 0.28125 0.421875 0.71875q0.140625 0.4375 0.140625 1.0zm-0.796875 0.046875q0 -0.421875 -0.09375 -0.734375q-0.09375 -0.328125 -0.28125 -0.53125q-0.171875 -0.21875 -0.421875 -0.328125q-0.234375 -0.109375 -0.546875 -0.109375q-0.359375 0 -0.609375 0.140625q-0.25 0.140625 -0.421875 0.375q-0.15625 0.234375 -0.234375 0.546875q-0.0625 0.296875 -0.0625 0.640625q0 0.421875 0.09375 0.75q0.09375 0.3125 0.265625 0.53125q0.171875 0.203125 0.40625 0.3125q0.25 0.09375 0.5625 0.09375q0.359375 0 0.609375 -0.125q0.25 -0.140625 0.40625 -0.375q0.171875 -0.234375 0.25 -0.53125q0.078125 -0.3125 0.078125 -0.65625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m471.4252 134.86613l71.99997 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-71.99997 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m471.4252 134.86613l71.99997 0l0 -4.0l8.0 8.0l-8.0 8.0l0 -4.0l-71.99997 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m325.8504 61.45669l17.574799 0l0 0c9.706299 0 17.574799 6.50774 17.574799 14.535435c0 8.027695 -7.8684998 14.535431 -17.574799 14.535431l-17.574799 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m325.8504 61.45669l17.574799 0l0 0c9.706299 0 17.574799 6.50774 17.574799 14.535435c0 8.027695 -7.8684998 14.535431 -17.574799 14.535431l-17.574799 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m345.937 99.461945l26.204712 0l0 10.740158l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m354.22687 105.85085q0 0.515625 -0.15625 0.90625q-0.140625 0.390625 -0.40625 0.65625q-0.25 0.25 -0.609375 0.390625q-0.34375 0.125 -0.75 0.125q-0.1875 0 -0.375 -0.015625q-0.1875 -0.015625 -0.375 -0.078125l0 1.65625l-0.6875 0l0 -5.53125l0.609375 0l0.046875 0.65625q0.28125 -0.40625 0.609375 -0.5625q0.34375 -0.171875 0.734375 -0.171875q0.328125 0 0.578125 0.140625q0.265625 0.140625 0.4375 0.40625q0.171875 0.25 0.25 0.609375q0.09375 0.359375 0.09375 0.8125zm-0.703125 0.03125q0 -0.3125 -0.046875 -0.5625q-0.046875 -0.265625 -0.140625 -0.4375q-0.09375 -0.1875 -0.25 -0.296875q-0.15625 -0.109375 -0.359375 -0.109375q-0.125 0 -0.265625 0.046875q-0.125 0.046875 -0.28125 0.140625q-0.140625 0.09375 -0.296875 0.25q-0.15625 0.15625 -0.328125 0.390625l0 1.90625q0.1875 0.078125 0.390625 0.125q0.203125 0.046875 0.40625 0.046875q0.546875 0 0.859375 -0.375q0.3125 -0.375 0.3125 -1.125zm1.8984375 -1.921875l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm5.5859375 0.5625l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.2421875 3.5625q0 0.46875 -0.140625 0.84375q-0.125 0.375 -0.375 0.65625q-0.234375 0.265625 -0.578125 0.421875q-0.34375 0.15625 -0.796875 0.15625q-0.421875 0 -0.75 -0.125q-0.328125 -0.140625 -0.5625 -0.390625q-0.234375 -0.265625 -0.359375 -0.640625q-0.125 -0.375 -0.125 -0.859375q0 -0.453125 0.125 -0.828125q0.140625 -0.390625 0.375 -0.65625q0.25 -0.265625 0.59375 -0.421875q0.34375 -0.15625 0.78125 -0.15625q0.421875 0 0.75 0.140625q0.34375 0.125 0.578125 0.375q0.234375 0.25 0.359375 0.625q0.125 0.375 0.125 0.859375zm-0.703125 0.03125q0 -0.359375 -0.078125 -0.625q-0.078125 -0.28125 -0.234375 -0.453125q-0.140625 -0.1875 -0.359375 -0.28125q-0.203125 -0.09375 -0.46875 -0.09375q-0.3125 0 -0.53125 0.125q-0.203125 0.125 -0.34375 0.328125q-0.140625 0.1875 -0.203125 0.453125q-0.0625 0.265625 -0.0625 0.546875q0 0.375 0.078125 0.65625q0.078125 0.265625 0.21875 0.453125q0.15625 0.171875 0.359375 0.265625q0.21875 0.09375 0.484375 0.09375q0.296875 0 0.515625 -0.125q0.21875 -0.125 0.359375 -0.3125q0.140625 -0.203125 0.203125 -0.46875q0.0625 -0.265625 0.0625 -0.5625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m299.04724 78.57218l22.771667 0l0 10.74015l-22.771667 0z" fill-rule="evenodd"/><path fill="#000000" d="m314.99078 83.63296l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.1328125 3.390625q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m372.14172 112.13911l0 -26.650917l16.07611 5.330185l0 15.990547z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m372.14172 112.13911l0 -26.650917l16.07611 5.330185l0 15.990547z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m372.21783 88.01837l16.0 0l0 22.897636l-16.0 0z" fill-rule="evenodd"/><path fill="#000000" d="m372.54596 94.31907q0 -1.015625 0.203125 -1.625q0.21875 -0.625 0.625 -0.953125q0.421875 -0.34375 1.046875 -0.34375q0.453125 0 0.796875 0.1875q0.359375 0.1875 0.578125 0.53125q0.234375 0.34375 0.359375 0.859375q0.125 0.5 0.125 1.34375q0 1.015625 -0.203125 1.640625q-0.203125 0.609375 -0.625 0.953125q-0.40625 0.328125 -1.03125 0.328125q-0.828125 0 -1.296875 -0.59375q-0.578125 -0.71875 -0.578125 -2.328125zm0.734375 0q0 1.40625 0.328125 1.875q0.328125 0.46875 0.8125 0.46875q0.484375 0 0.8125 -0.46875q0.328125 -0.46875 0.328125 -1.875q0 -1.40625 -0.328125 -1.875q-0.328125 -0.46875 -0.828125 -0.46875q-0.484375 0 -0.765625 0.40625q-0.359375 0.53125 -0.359375 1.9375z" fill-rule="nonzero"/><path fill="#000000" d="m375.2022 107.147194l-0.703125 0l0 -4.484375q-0.25 0.25 -0.671875 0.5q-0.40625 0.234375 -0.734375 0.34375l0 -0.671875q0.59375 -0.28125 1.03125 -0.671875q0.4375 -0.390625 0.625 -0.765625l0.453125 0l0 5.75z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m340.99738 88.11811l26.204712 0l0 10.740158l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m366.86615 93.991394q0 0.578125 -0.125 1.0625q-0.109375 0.484375 -0.359375 0.828125q-0.234375 0.34375 -0.59375 0.546875q-0.34375 0.1875 -0.828125 0.1875q-0.40625 0 -0.75 -0.15625q-0.328125 -0.15625 -0.5625 -0.46875q-0.234375 -0.328125 -0.375 -0.828125q-0.125 -0.5 -0.125 -1.171875q0 -0.59375 0.109375 -1.078125q0.125 -0.484375 0.359375 -0.828125q0.25 -0.34375 0.59375 -0.53125q0.359375 -0.1875 0.828125 -0.1875q0.421875 0 0.75 0.15625q0.34375 0.140625 0.578125 0.46875q0.234375 0.328125 0.359375 0.828125q0.140625 0.484375 0.140625 1.171875zm-0.6875 0.015625q0 -0.125 -0.015625 -0.25q-0.015625 -0.140625 -0.015625 -0.265625l-2.171875 1.609375q0.0625 0.203125 0.15625 0.375q0.09375 0.171875 0.21875 0.296875q0.125 0.109375 0.28125 0.1875q0.171875 0.0625 0.375 0.0625q0.265625 0 0.484375 -0.125q0.21875 -0.125 0.359375 -0.375q0.15625 -0.265625 0.234375 -0.640625q0.09375 -0.375 0.09375 -0.875zm-2.34375 -0.046875q0 0.125 0 0.25q0 0.109375 0.015625 0.234375l2.15625 -1.609375q-0.046875 -0.1875 -0.140625 -0.34375q-0.09375 -0.171875 -0.21875 -0.296875q-0.125 -0.125 -0.28125 -0.1875q-0.15625 -0.0625 -0.359375 -0.0625q-0.265625 0 -0.484375 0.125q-0.21875 0.125 -0.375 0.390625q-0.140625 0.25 -0.234375 0.625q-0.078125 0.375 -0.078125 0.875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m361.0 75.99213l18.614166 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m361.0 75.99213l18.614166 0" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m380.21783 75.67191l0 12.346458" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m380.21783 75.67191l0 12.346458" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m439.24408 86.04724l0 208.8504l-36.22046 0l0 -208.8504z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" stroke-dasharray="1.0,3.0" d="m439.24408 86.04724l0 208.8504l-36.22046 0l0 -208.8504z" fill-rule="evenodd"/><path fill="#000000" d="m417.39386 164.40762l7.625 0l0 5.140625l-0.890625 0l0 -4.125l-2.375 0l0 3.578125l-0.890625 0l0 -3.578125l-3.46875 0l0 -1.015625zm0 6.634262l7.625 0l0 1.0l-7.625 0l0 -1.0zm0 2.7731476l7.625 0l0 1.03125l-5.984375 4.015625l5.984375 0l0 0.96875l-7.625 0l0 -1.046875l6.0 -4.0l-6.0 0l0 -0.96875zm0 7.7112274l7.625 0l0 2.625q0 0.890625 -0.109375 1.359375q-0.140625 0.65625 -0.546875 1.109375q-0.5 0.609375 -1.296875 0.90625q-0.796875 0.296875 -1.8125 0.296875q-0.875 0 -1.546875 -0.203125q-0.671875 -0.203125 -1.109375 -0.515625q-0.4375 -0.3125 -0.6875 -0.703125q-0.25 -0.375 -0.390625 -0.90625q-0.125 -0.53125 -0.125 -1.21875l0 -2.75zm0.90625 1.0l0 1.625q0 0.765625 0.140625 1.1875q0.140625 0.4375 0.390625 0.6875q0.359375 0.359375 0.953125 0.5625q0.609375 0.203125 1.484375 0.203125q1.1875 0 1.828125 -0.40625q0.65625 -0.390625 0.875 -0.953125q0.15625 -0.40625 0.15625 -1.296875l0 -1.609375l-5.828125 0zm-3.03125 5.7112274l0.6875 0l0 6.203125l-0.6875 0l0 -6.203125zm2.125 6.8796234l7.625 0l0 1.515625l-5.390625 1.796875q-0.765625 0.25 -1.140625 0.375q0.421875 0.125 1.234375 0.40625l5.296875 1.828125l0 1.34375l-7.625 0l0 -0.96875l6.390625 0l-6.390625 -2.21875l0 -0.90625l6.5 -2.203125l-6.5 0l0 -0.96875zm0 8.0642395l7.625 2.921875l0 1.09375l-7.625 3.125l0 -1.15625l2.3125 -0.890625l0 -3.1875l-2.3125 -0.828125l0 -1.078125zm3.125 2.203125l0 2.578125l2.125 -0.796875q0.953125 -0.359375 1.578125 -0.53125q-0.734375 -0.15625 -1.453125 -0.421875l-2.25 -0.828125zm-3.125 4.9670105l3.96875 2.953125l3.65625 -2.609375l0 1.203125l-1.953125 1.390625q-0.609375 0.421875 -0.9375 0.609375q0.421875 0.25 0.875 0.609375l2.015625 1.53125l0 1.09375l-3.59375 -2.671875l-4.03125 2.890625l0 -1.25l2.71875 -1.921875q0.234375 -0.171875 0.515625 -0.34375q-0.421875 -0.25 -0.578125 -0.359375l-2.65625 -1.90625l0 -1.21875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m325.8504 127.333336l17.574799 0l0 0c9.706299 0 17.574799 6.5077286 17.574799 14.535423c0 8.02771 -7.8684998 14.535446 -17.574799 14.535446l-17.574799 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m325.8504 127.333336l17.574799 0l0 0c9.706299 0 17.574799 6.5077286 17.574799 14.535423c0 8.02771 -7.8684998 14.535446 -17.574799 14.535446l-17.574799 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m345.937 165.33858l26.204712 0l0 10.740158l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m354.22687 171.7275q0 0.515625 -0.15625 0.90625q-0.140625 0.390625 -0.40625 0.65625q-0.25 0.25 -0.609375 0.390625q-0.34375 0.125 -0.75 0.125q-0.1875 0 -0.375 -0.015625q-0.1875 -0.015625 -0.375 -0.078125l0 1.65625l-0.6875 0l0 -5.53125l0.609375 0l0.046875 0.65625q0.28125 -0.40625 0.609375 -0.5625q0.34375 -0.171875 0.734375 -0.171875q0.328125 0 0.578125 0.140625q0.265625 0.140625 0.4375 0.40625q0.171875 0.25 0.25 0.609375q0.09375 0.359375 0.09375 0.8125zm-0.703125 0.03125q0 -0.3125 -0.046875 -0.5625q-0.046875 -0.265625 -0.140625 -0.4375q-0.09375 -0.1875 -0.25 -0.296875q-0.15625 -0.109375 -0.359375 -0.109375q-0.125 0 -0.265625 0.046875q-0.125 0.046875 -0.28125 0.140625q-0.140625 0.09375 -0.296875 0.25q-0.15625 0.15625 -0.328125 0.390625l0 1.90625q0.1875 0.078125 0.390625 0.125q0.203125 0.046875 0.40625 0.046875q0.546875 0 0.859375 -0.375q0.3125 -0.375 0.3125 -1.125zm1.8984375 -1.921875l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm5.5859375 0.5625l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.2421875 3.5625q0 0.46875 -0.140625 0.84375q-0.125 0.375 -0.375 0.65625q-0.234375 0.265625 -0.578125 0.421875q-0.34375 0.15625 -0.796875 0.15625q-0.421875 0 -0.75 -0.125q-0.328125 -0.140625 -0.5625 -0.390625q-0.234375 -0.265625 -0.359375 -0.640625q-0.125 -0.375 -0.125 -0.859375q0 -0.453125 0.125 -0.828125q0.140625 -0.390625 0.375 -0.65625q0.25 -0.265625 0.59375 -0.421875q0.34375 -0.15625 0.78125 -0.15625q0.421875 0 0.75 0.140625q0.34375 0.125 0.578125 0.375q0.234375 0.25 0.359375 0.625q0.125 0.375 0.125 0.859375zm-0.703125 0.03125q0 -0.359375 -0.078125 -0.625q-0.078125 -0.28125 -0.234375 -0.453125q-0.140625 -0.1875 -0.359375 -0.28125q-0.203125 -0.09375 -0.46875 -0.09375q-0.3125 0 -0.53125 0.125q-0.203125 0.125 -0.34375 0.328125q-0.140625 0.1875 -0.203125 0.453125q-0.0625 0.265625 -0.0625 0.546875q0 0.375 0.078125 0.65625q0.078125 0.265625 0.21875 0.453125q0.15625 0.171875 0.359375 0.265625q0.21875 0.09375 0.484375 0.09375q0.296875 0 0.515625 -0.125q0.21875 -0.125 0.359375 -0.3125q0.140625 -0.203125 0.203125 -0.46875q0.0625 -0.265625 0.0625 -0.5625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m299.04724 144.44882l22.771667 0l0 10.740158l-22.771667 0z" fill-rule="evenodd"/><path fill="#000000" d="m314.99078 149.5096l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.1328125 3.390625q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m372.14172 178.01575l0 -26.650925l16.07611 5.330185l0 15.990555z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m372.14172 178.01575l0 -26.650925l16.07611 5.330185l0 15.990555z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m372.21783 153.89502l16.0 0l0 22.897629l-16.0 0z" fill-rule="evenodd"/><path fill="#000000" d="m372.54596 160.19571q0 -1.015625 0.203125 -1.625q0.21875 -0.625 0.625 -0.953125q0.421875 -0.34375 1.046875 -0.34375q0.453125 0 0.796875 0.1875q0.359375 0.1875 0.578125 0.53125q0.234375 0.34375 0.359375 0.859375q0.125 0.5 0.125 1.34375q0 1.015625 -0.203125 1.640625q-0.203125 0.609375 -0.625 0.953125q-0.40625 0.328125 -1.03125 0.328125q-0.828125 0 -1.296875 -0.59375q-0.578125 -0.71875 -0.578125 -2.328125zm0.734375 0q0 1.40625 0.328125 1.875q0.328125 0.46875 0.8125 0.46875q0.484375 0 0.8125 -0.46875q0.328125 -0.46875 0.328125 -1.875q0 -1.40625 -0.328125 -1.875q-0.328125 -0.46875 -0.828125 -0.46875q-0.484375 0 -0.765625 0.40625q-0.359375 0.53125 -0.359375 1.9375z" fill-rule="nonzero"/><path fill="#000000" d="m375.2022 173.02383l-0.703125 0l0 -4.484375q-0.25 0.25 -0.671875 0.5q-0.40625 0.234375 -0.734375 0.34375l0 -0.671875q0.59375 -0.28125 1.03125 -0.671875q0.4375 -0.390625 0.625 -0.765625l0.453125 0l0 5.75z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m340.99738 153.99475l26.204712 0l0 10.740158l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m366.86615 159.86803q0 0.578125 -0.125 1.0625q-0.109375 0.484375 -0.359375 0.828125q-0.234375 0.34375 -0.59375 0.546875q-0.34375 0.1875 -0.828125 0.1875q-0.40625 0 -0.75 -0.15625q-0.328125 -0.15625 -0.5625 -0.46875q-0.234375 -0.328125 -0.375 -0.828125q-0.125 -0.5 -0.125 -1.171875q0 -0.59375 0.109375 -1.078125q0.125 -0.484375 0.359375 -0.828125q0.25 -0.34375 0.59375 -0.53125q0.359375 -0.1875 0.828125 -0.1875q0.421875 0 0.75 0.15625q0.34375 0.140625 0.578125 0.46875q0.234375 0.328125 0.359375 0.828125q0.140625 0.484375 0.140625 1.171875zm-0.6875 0.015625q0 -0.125 -0.015625 -0.25q-0.015625 -0.140625 -0.015625 -0.265625l-2.171875 1.609375q0.0625 0.203125 0.15625 0.375q0.09375 0.171875 0.21875 0.296875q0.125 0.109375 0.28125 0.1875q0.171875 0.0625 0.375 0.0625q0.265625 0 0.484375 -0.125q0.21875 -0.125 0.359375 -0.375q0.15625 -0.265625 0.234375 -0.640625q0.09375 -0.375 0.09375 -0.875zm-2.34375 -0.046875q0 0.125 0 0.25q0 0.109375 0.015625 0.234375l2.15625 -1.609375q-0.046875 -0.1875 -0.140625 -0.34375q-0.09375 -0.171875 -0.21875 -0.296875q-0.125 -0.125 -0.28125 -0.1875q-0.15625 -0.0625 -0.359375 -0.0625q-0.265625 0 -0.484375 0.125q-0.21875 0.125 -0.375 0.390625q-0.140625 0.25 -0.234375 0.625q-0.078125 0.375 -0.078125 0.875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m361.0 141.86876l18.614166 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m361.0 141.86876l18.614166 0" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m380.21783 141.54855l0 12.346466" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m380.21783 141.54855l0 12.346466" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m325.8504 245.24672l17.574799 0l0 0c9.706299 0 17.574799 6.507736 17.574799 14.535446c0 8.027679 -7.8684998 14.535431 -17.574799 14.535431l-17.574799 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m325.8504 245.24672l17.574799 0l0 0c9.706299 0 17.574799 6.507736 17.574799 14.535446c0 8.027679 -7.8684998 14.535431 -17.574799 14.535431l-17.574799 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m345.937 283.25198l26.204712 0l0 10.740143l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m354.22687 289.64087q0 0.515625 -0.15625 0.90625q-0.140625 0.390625 -0.40625 0.65625q-0.25 0.25 -0.609375 0.390625q-0.34375 0.125 -0.75 0.125q-0.1875 0 -0.375 -0.015625q-0.1875 -0.015625 -0.375 -0.078125l0 1.65625l-0.6875 0l0 -5.53125l0.609375 0l0.046875 0.65625q0.28125 -0.40625 0.609375 -0.5625q0.34375 -0.171875 0.734375 -0.171875q0.328125 0 0.578125 0.140625q0.265625 0.140625 0.4375 0.40625q0.171875 0.25 0.25 0.609375q0.09375 0.359375 0.09375 0.8125zm-0.703125 0.03125q0 -0.3125 -0.046875 -0.5625q-0.046875 -0.265625 -0.140625 -0.4375q-0.09375 -0.1875 -0.25 -0.296875q-0.15625 -0.109375 -0.359375 -0.109375q-0.125 0 -0.265625 0.046875q-0.125 0.046875 -0.28125 0.140625q-0.140625 0.09375 -0.296875 0.25q-0.15625 0.15625 -0.328125 0.390625l0 1.90625q0.1875 0.078125 0.390625 0.125q0.203125 0.046875 0.40625 0.046875q0.546875 0 0.859375 -0.375q0.3125 -0.375 0.3125 -1.125zm1.8984375 -1.921875l0.625 0l0.015625 0.71875q0.359375 -0.421875 0.6875 -0.609375q0.34375 -0.1875 0.6875 -0.1875q0.609375 0 0.921875 0.40625q0.3125 0.390625 0.296875 1.171875l-0.6875 0q0 -0.515625 -0.15625 -0.75q-0.15625 -0.234375 -0.46875 -0.234375q-0.140625 0 -0.28125 0.046875q-0.140625 0.046875 -0.296875 0.15625q-0.140625 0.109375 -0.3125 0.28125q-0.15625 0.15625 -0.34375 0.40625l0 2.515625l-0.6875 0l0 -3.921875zm5.5859375 0.5625l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.2421875 3.5625q0 0.46875 -0.140625 0.84375q-0.125 0.375 -0.375 0.65625q-0.234375 0.265625 -0.578125 0.421875q-0.34375 0.15625 -0.796875 0.15625q-0.421875 0 -0.75 -0.125q-0.328125 -0.140625 -0.5625 -0.390625q-0.234375 -0.265625 -0.359375 -0.640625q-0.125 -0.375 -0.125 -0.859375q0 -0.453125 0.125 -0.828125q0.140625 -0.390625 0.375 -0.65625q0.25 -0.265625 0.59375 -0.421875q0.34375 -0.15625 0.78125 -0.15625q0.421875 0 0.75 0.140625q0.34375 0.125 0.578125 0.375q0.234375 0.25 0.359375 0.625q0.125 0.375 0.125 0.859375zm-0.703125 0.03125q0 -0.359375 -0.078125 -0.625q-0.078125 -0.28125 -0.234375 -0.453125q-0.140625 -0.1875 -0.359375 -0.28125q-0.203125 -0.09375 -0.46875 -0.09375q-0.3125 0 -0.53125 0.125q-0.203125 0.125 -0.34375 0.328125q-0.140625 0.1875 -0.203125 0.453125q-0.0625 0.265625 -0.0625 0.546875q0 0.375 0.078125 0.65625q0.078125 0.265625 0.21875 0.453125q0.15625 0.171875 0.359375 0.265625q0.21875 0.09375 0.484375 0.09375q0.296875 0 0.515625 -0.125q0.21875 -0.125 0.359375 -0.3125q0.140625 -0.203125 0.203125 -0.46875q0.0625 -0.265625 0.0625 -0.5625z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m299.04724 262.3622l22.771667 0l0 10.740143l-22.771667 0z" fill-rule="evenodd"/><path fill="#000000" d="m314.99078 267.42297l-1.171875 0l0 -0.5625l1.859375 0l0 3.359375l1.15625 0l0 0.5625l-3.140625 0l0 -0.5625l1.296875 0l0 -2.796875zm0.234375 -2.203125q0.109375 0 0.203125 0.046875q0.109375 0.03125 0.171875 0.109375q0.078125 0.0625 0.109375 0.171875q0.046875 0.09375 0.046875 0.203125q0 0.109375 -0.046875 0.203125q-0.03125 0.09375 -0.109375 0.171875q-0.0625 0.078125 -0.171875 0.125q-0.09375 0.03125 -0.203125 0.03125q-0.109375 0 -0.21875 -0.03125q-0.09375 -0.046875 -0.171875 -0.125q-0.0625 -0.078125 -0.109375 -0.171875q-0.03125 -0.09375 -0.03125 -0.203125q0 -0.109375 0.03125 -0.203125q0.046875 -0.109375 0.109375 -0.171875q0.078125 -0.078125 0.171875 -0.109375q0.109375 -0.046875 0.21875 -0.046875zm6.1328125 3.390625q0 0.140625 0 0.25q0 0.09375 -0.015625 0.171875l-2.75 0q0 0.609375 0.328125 0.9375q0.34375 0.3125 0.96875 0.3125q0.171875 0 0.34375 -0.015625q0.171875 -0.015625 0.328125 -0.03125q0.171875 -0.03125 0.3125 -0.046875q0.15625 -0.03125 0.28125 -0.078125l0 0.5625q-0.28125 0.078125 -0.640625 0.125q-0.34375 0.0625 -0.71875 0.0625q-0.5 0 -0.875 -0.140625q-0.359375 -0.140625 -0.59375 -0.390625q-0.21875 -0.265625 -0.34375 -0.640625q-0.109375 -0.390625 -0.109375 -0.859375q0 -0.421875 0.125 -0.78125q0.125 -0.375 0.34375 -0.65625q0.234375 -0.28125 0.5625 -0.4375q0.328125 -0.171875 0.75 -0.171875q0.421875 0 0.734375 0.140625q0.3125 0.125 0.53125 0.359375q0.21875 0.234375 0.328125 0.578125q0.109375 0.328125 0.109375 0.75zm-0.703125 -0.09375q0.015625 -0.265625 -0.046875 -0.484375q-0.0625 -0.21875 -0.203125 -0.375q-0.125 -0.15625 -0.328125 -0.234375q-0.1875 -0.09375 -0.453125 -0.09375q-0.21875 0 -0.40625 0.09375q-0.171875 0.078125 -0.3125 0.234375q-0.125 0.15625 -0.21875 0.375q-0.078125 0.21875 -0.09375 0.484375l2.0625 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m372.14172 295.92914l0 -26.65091l16.07611 5.3301697l0 15.99054z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m372.14172 295.92914l0 -26.65091l16.07611 5.3301697l0 15.99054z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m372.21783 271.8084l16.0 0l0 22.897614l-16.0 0z" fill-rule="evenodd"/><path fill="#000000" d="m372.54596 278.1091q0 -1.015625 0.203125 -1.625q0.21875 -0.625 0.625 -0.953125q0.421875 -0.34375 1.046875 -0.34375q0.453125 0 0.796875 0.1875q0.359375 0.1875 0.578125 0.53125q0.234375 0.34375 0.359375 0.859375q0.125 0.5 0.125 1.34375q0 1.015625 -0.203125 1.640625q-0.203125 0.609375 -0.625 0.953125q-0.40625 0.328125 -1.03125 0.328125q-0.828125 0 -1.296875 -0.59375q-0.578125 -0.71875 -0.578125 -2.328125zm0.734375 0q0 1.40625 0.328125 1.875q0.328125 0.46875 0.8125 0.46875q0.484375 0 0.8125 -0.46875q0.328125 -0.46875 0.328125 -1.875q0 -1.40625 -0.328125 -1.875q-0.328125 -0.46875 -0.828125 -0.46875q-0.484375 0 -0.765625 0.40625q-0.359375 0.53125 -0.359375 1.9375z" fill-rule="nonzero"/><path fill="#000000" d="m375.2022 290.93723l-0.703125 0l0 -4.484375q-0.25 0.25 -0.671875 0.5q-0.40625 0.234375 -0.734375 0.34375l0 -0.671875q0.59375 -0.28125 1.03125 -0.671875q0.4375 -0.390625 0.625 -0.765625l0.453125 0l0 5.75z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m340.99738 271.90814l26.204712 0l0 10.740143l-26.204712 0z" fill-rule="evenodd"/><path fill="#000000" d="m366.86615 277.78143q0 0.578125 -0.125 1.0625q-0.109375 0.484375 -0.359375 0.828125q-0.234375 0.34375 -0.59375 0.546875q-0.34375 0.1875 -0.828125 0.1875q-0.40625 0 -0.75 -0.15625q-0.328125 -0.15625 -0.5625 -0.46875q-0.234375 -0.328125 -0.375 -0.828125q-0.125 -0.5 -0.125 -1.171875q0 -0.59375 0.109375 -1.078125q0.125 -0.484375 0.359375 -0.828125q0.25 -0.34375 0.59375 -0.53125q0.359375 -0.1875 0.828125 -0.1875q0.421875 0 0.75 0.15625q0.34375 0.140625 0.578125 0.46875q0.234375 0.328125 0.359375 0.828125q0.140625 0.484375 0.140625 1.171875zm-0.6875 0.015625q0 -0.125 -0.015625 -0.25q-0.015625 -0.140625 -0.015625 -0.265625l-2.171875 1.609375q0.0625 0.203125 0.15625 0.375q0.09375 0.171875 0.21875 0.296875q0.125 0.109375 0.28125 0.1875q0.171875 0.0625 0.375 0.0625q0.265625 0 0.484375 -0.125q0.21875 -0.125 0.359375 -0.375q0.15625 -0.265625 0.234375 -0.640625q0.09375 -0.375 0.09375 -0.875zm-2.34375 -0.046875q0 0.125 0 0.25q0 0.109375 0.015625 0.234375l2.15625 -1.609375q-0.046875 -0.1875 -0.140625 -0.34375q-0.09375 -0.171875 -0.21875 -0.296875q-0.125 -0.125 -0.28125 -0.1875q-0.15625 -0.0625 -0.359375 -0.0625q-0.265625 0 -0.484375 0.125q-0.21875 0.125 -0.375 0.390625q-0.140625 0.25 -0.234375 0.625q-0.078125 0.375 -0.078125 0.875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m361.0 259.78217l18.614166 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m361.0 259.78217l18.614166 0" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m380.21783 259.46194l0 12.346466" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m380.21783 259.46194l0 12.346466" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m377.5223 166.54593l0 73.480316l-35.77954 0l0 -73.480316z" fill-rule="evenodd"/><path fill="#000000" d="m350.60233 197.19864l1.875 0l0 1.875l-1.875 0l0 -1.875zm0 5.183304l1.875 0l0 1.875l-1.875 0l0 -1.875zm0 5.183304l1.875 0l0 1.875l-1.875 0l0 -1.875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m285.79922 166.54593l0 73.480316l-35.77954 0l0 -73.480316z" fill-rule="evenodd"/><path fill="#000000" d="m258.8792 197.19864l1.875 0l0 1.875l-1.875 0l0 -1.875zm0 5.183304l1.875 0l0 1.875l-1.875 0l0 -1.875zm0 5.183304l1.875 0l0 1.875l-1.875 0l0 -1.875z" fill-rule="nonzero"/></g></svg>
\ No newline at end of file
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/doc/checklist.md b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/checklist.md
new file mode 100644
index 0000000..2095ed8
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/checklist.md
@@ -0,0 +1,266 @@
+# RV_PLIC Checklist
+
+This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [RV_PLIC peripheral](../README.md).
+All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md)
+
+## Design Checklist
+
+### D1
+
+Type | Item | Resolution | Note/Collaterals
+--------------|--------------------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][] | Done | [RV_PLIC Spec][]
+Documentation | [CSR_DEFINED][] | Done |
+RTL | [CLKRST_CONNECTED][] | Done |
+RTL | [IP_TOP][] | Done |
+RTL | [IP_INSTANTIABLE][] | Done |
+RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done |
+RTL | [FUNC_IMPLEMENTED][] | Done |
+RTL | [ASSERT_KNOWN_ADDED][] | Done |
+Code Quality | [LINT_SETUP][] | Done |
+
+[RV_PLIC Spec]: ../README.md
+
+[SPEC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#spec_complete
+[CSR_DEFINED]: ../../../../doc/project_governance/checklist/README.md#csr_defined
+[CLKRST_CONNECTED]: ../../../../doc/project_governance/checklist/README.md#clkrst_connected
+[IP_TOP]: ../../../../doc/project_governance/checklist/README.md#ip_top
+[IP_INSTANTIABLE]: ../../../../doc/project_governance/checklist/README.md#ip_instantiable
+[PHYSICAL_MACROS_DEFINED_80]: ../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
+[FUNC_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#func_implemented
+[ASSERT_KNOWN_ADDED]: ../../../../doc/project_governance/checklist/README.md#assert_known_added
+[LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#lint_setup
+
+### D2
+
+Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][] | N/A |
+Documentation | [BLOCK_DIAGRAM][] | Done |
+Documentation | [DOC_INTERFACE][] | Done |
+Documentation | [MISSING_FUNC][] | N/A |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [AREA_CHECK][] | Done |
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done | One TODO about Vivado Issue
+RTL | [STYLE_X][] | Done |
+Code Quality | [LINT_PASS][] | Done |
+Code Quality | [CDC_SETUP][] | N/A |
+Code Quality | [FPGA_TIMING][] | Done | Fmax @ 50MHz on NexysVideo
+Code Quality | [CDC_SYNCMACRO][] | N/A |
+Security | [SEC_CM_DOCUMENTED][] | N/A |
+Security | [SEC_RND_CNST][] | N/A |
+
+[NEW_FEATURES]: ../../../../doc/project_governance/checklist/README.md#new_features
+[BLOCK_DIAGRAM]: ../../../../doc/project_governance/checklist/README.md#block_diagram
+[DOC_INTERFACE]: ../../../../doc/project_governance/checklist/README.md#doc_interface
+[MISSING_FUNC]: ../../../../doc/project_governance/checklist/README.md#missing_func
+[FEATURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#feature_frozen
+[FEATURE_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#feature_complete
+[AREA_CHECK]: ../../../../doc/project_governance/checklist/README.md#area_check
+[PORT_FROZEN]: ../../../../doc/project_governance/checklist/README.md#port_frozen
+[ARCHITECTURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#architecture_frozen
+[REVIEW_TODO]: ../../../../doc/project_governance/checklist/README.md#review_todo
+[STYLE_X]: ../../../../doc/project_governance/checklist/README.md#style_x
+[LINT_PASS]: ../../../../doc/project_governance/checklist/README.md#lint_pass
+[CDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#cdc_setup
+[FPGA_TIMING]: ../../../../doc/project_governance/checklist/README.md#fpga_timing
+[CDC_SYNCMACRO]: ../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
+[SEC_CM_DOCUMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_documented
+[SEC_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_rnd_cnst
+
+### D2S
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|------------------------------|-------------|------------------
+Security | [SEC_CM_ASSETS_LISTED][] | Done |
+Security | [SEC_CM_IMPLEMENTED][] | Done |
+Security | [SEC_CM_RND_CNST][] | N/A |
+Security | [SEC_CM_NON_RESET_FLOPS][] | N/A |
+Security | [SEC_CM_SHADOW_REGS][] | N/A |
+Security | [SEC_CM_RTL_REVIEWED][] | N/A |
+Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM.
+
+[SEC_CM_ASSETS_LISTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
+[SEC_CM_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
+[SEC_CM_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
+[SEC_CM_NON_RESET_FLOPS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
+[SEC_CM_SHADOW_REGS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
+[SEC_CM_RTL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
+[SEC_CM_COUNCIL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
+
+### D3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][] | Done |
+RTL | [TODO_COMPLETE][] | Done |
+Code Quality | [LINT_COMPLETE][] | Done |
+Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff.
+Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff.
+Review | [REVIEW_RTL][] | Done |
+Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff.
+Review | [REVIEW_SW_CHANGE][] | Done |
+Review | [REVIEW_SW_ERRATA][] | Done |
+Review | Reviewer(s) | Done | eunchan@ gac@ chencindy@ ttrippel@
+Review | Signoff date | Done | 2022-07-25
+
+[NEW_FEATURES_D3]: ../../../../doc/project_governance/checklist/README.md#new_features_d3
+[TODO_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#todo_complete
+[LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#lint_complete
+[CDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#cdc_complete
+[RDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#rdc_complete
+[REVIEW_RTL]: ../../../../doc/project_governance/checklist/README.md#review_rtl
+[REVIEW_DELETED_FF]: ../../../../doc/project_governance/checklist/README.md#review_deleted_ff
+[REVIEW_SW_CHANGE]: ../../../../doc/project_governance/checklist/README.md#review_sw_change
+[REVIEW_SW_ERRATA]: ../../../../doc/project_governance/checklist/README.md#review_sw_errata
+
+## Verification Checklist
+
+### V1
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|---------------------------------------|-------------|------------------
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [rv_plic_fpv_plan](./dv/README.md)
+Documentation | [TESTPLAN_COMPLETED][] | Done |
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [SIM_TB_ENV_CREATED][] | N/A |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | N/A |
+Tests | [SIM_SMOKE_TEST_PASSING][] | N/A |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | N/A |
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Done |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A |
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | N/A |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | N/A |
+Regression | [FPV_REGRESSION_SETUP][] | Done |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | N/A |
+Code Quality | [TB_LINT_SETUP][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A |
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [TESTPLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A |
+Review | [V2_CHECKLIST_SCOPED][] | Done |
+
+[DV_DOC_DRAFT_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
+[TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#testplan_completed
+[TB_TOP_CREATED]: ../../../../doc/project_governance/checklist/README.md#tb_top_created
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
+[SIM_TB_ENV_CREATED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
+[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
+[CSR_CHECK_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
+[TB_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#tb_gen_automated
+[SIM_SMOKE_TEST_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
+[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
+[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
+[SIM_ALT_TOOL_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
+[SIM_SMOKE_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
+[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
+[FPV_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
+[SIM_COVERAGE_MODEL_ADDED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
+[TB_LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#tb_lint_setup
+[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
+[DESIGN_SPEC_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
+[TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#testplan_reviewed
+[STD_TEST_CATEGORIES_PLANNED]: ../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
+[V2_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
+
+### V2
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A |
+Documentation | [DV_DOC_COMPLETED][] | Done |
+Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | N/A |
+Testbench | [ALL_INTERFACES_EXERCISED][] | Done |
+Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done |
+Testbench | [SIM_TB_ENV_COMPLETED][] | N/A |
+Tests | [SIM_ALL_TESTS_PASSING][] | N/A |
+Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Done |
+Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Done |
+Tests | [SIM_FW_SIMULATED][] | N/A |
+Regression | [SIM_NIGHTLY_REGRESSION_V2][] | N/A |
+Coverage | [SIM_CODE_COVERAGE_V2][] | N/A |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | N/A |
+Coverage | [FPV_CODE_COVERAGE_V2][] | Done |
+Coverage | [FPV_COI_COVERAGE_V2][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A |
+Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done |
+Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done |
+Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started |
+Review | [V3_CHECKLIST_SCOPED][] | Done |
+
+[DESIGN_DELTAS_CAPTURED_V2]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
+[DV_DOC_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_completed
+[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
+[ALL_INTERFACES_EXERCISED]: ../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
+[ALL_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
+[SIM_TB_ENV_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
+[SIM_ALL_TESTS_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
+[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
+[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
+[SIM_FW_SIMULATED]: ../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
+[SIM_NIGHTLY_REGRESSION_V2]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
+[SIM_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
+[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
+[FPV_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
+[FPV_COI_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
+[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
+[DV_DOC_TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
+[V3_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
+
+### V2S
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started |
+Tests | [FPV_SEC_CM_VERIFIED][] | Not Started |
+Tests | [SIM_SEC_CM_VERIFIED][] | Not Started |
+Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started |
+Review | [SEC_CM_DV_REVIEWED][] | Not Started |
+
+[SEC_CM_TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
+[FPV_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
+[SIM_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
+[SIM_COVERAGE_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
+[SEC_CM_DV_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
+
+### V3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started |
+Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started |
+Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started |
+Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started |
+Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started |
+Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started |
+Code Quality | [ALL_TODOS_RESOLVED][] | Not Started |
+Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started |
+Code Quality | [TB_LINT_COMPLETE][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started |
+Issues | [NO_ISSUES_PENDING][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[DESIGN_DELTAS_CAPTURED_V3]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
+[X_PROP_ANALYSIS_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
+[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
+[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
+[SIM_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
+[FPV_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
+[FPV_COI_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
+[ALL_TODOS_RESOLVED]: ../../../../doc/project_governance/checklist/README.md#all_todos_resolved
+[NO_TOOL_WARNINGS_THROWN]: ../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
+[TB_LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#tb_lint_complete
+[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
+[NO_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_issues_pending
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/README.md b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/README.md
new file mode 100644
index 0000000..b672493
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/README.md
@@ -0,0 +1,48 @@
+# RV_PLIC DV document
+
+## Goals
+* DV:
+ * RV_PLIC is decided to verify in FPV only
+
+* FPV:
+ * Verify all the RV_PLIC outputs by writing assumptions and assertions with a
+ FPV based testbench
+ * Verify TileLink device protocol compliance with a FPV based testbench
+
+## Current status
+* [Design & verification stage](../../../../README.md)
+ * [HW development stages](../../../../../doc/project_governance/development_stages.md)
+* FPV dashboard (link TBD)
+
+## Design features
+For detailed information on RV_PLIC design features, please see the
+[RV_PLIC design specification](../../README.md).
+
+## Testbench architecture
+RV_PLIC FPV testbench has been constructed based on the [formal
+architecture](../../../../formal/README.md).
+
+### Block diagram
+
+
+#### TLUL assertions
+* The file `rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md)
+ to rv_plic to ensure TileLink interface protocol compliance.
+* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` also binds the `rv_plic_csr_assert_fpv`
+ under `fpv/vip/` to check if TileLink writes and reads correct
+ CSRs.
+
+#### RV_PLIC assertions
+The file `rv_plic_bind.sv` binds the `rv_plic_assert` under `rv_plic_assert.sv`.
+The assertion file ensures RV_PLIC's outputs (`irq_o` and `irq_id_o`) and important signals (`ip`) are being asserted.
+
+##### Symbolic variables
+Due to there are large number of input interrupt sources, the symbolic variable
+is used to reduce the number of repeated assertions code. In RV_PLIC, we
+declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for
+interrupt source and interrupt target.
+Detailed explanation is listed in the
+[Symbolic Variables](../../../../formal/README.md#symbolic-variables) section.
+
+## Testplan
+[Testplan](../data/rv_plic_fpv_testplan.hjson)
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/fpv.svg b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/fpv.svg
new file mode 100644
index 0000000..2f4cfe0
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/doc/dv/fpv.svg
@@ -0,0 +1 @@
+<svg version="1.1" viewBox="0.0 0.0 904.0472440944882 614.8503937007874" fill="none" stroke="none" stroke-linecap="square" stroke-miterlimit="10" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><clipPath id="p.0"><path d="m0 0l904.04724 0l0 614.8504l-904.04724 0l0 -614.8504z" clip-rule="nonzero"/></clipPath><g clip-path="url(#p.0)"><path fill="#ffffff" d="m0 0l904.04724 0l0 614.8504l-904.04724 0z" fill-rule="evenodd"/><path fill="#fce5cd" d="m151.53806 310.98425l105.60629 0l0 25.826782l-105.60629 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m151.53806 310.98425l105.60629 0l0 25.826782l-105.60629 0z" fill-rule="evenodd"/><path fill="#000000" d="m195.60326 326.19638l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm2.34375 2.78125l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm3.2873993 0l0 -10.484375l1.296875 0l0 5.96875l3.046875 -3.078125l1.671875 0l-2.90625 2.8125l3.1875 4.78125l-1.578125 0l-2.515625 -3.890625l-0.90625 0.875l0 3.015625l-1.296875 0zm6.140625 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338608 -11.921875l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0z" fill-rule="nonzero"/><path fill="#fce5cd" d="m668.3228 250.4672l146.04724 0l0 38.80316l-146.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m668.3228 250.4672l146.04724 0l0 38.80316l-146.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m692.99713 273.7925l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm1.2282104 1.15625l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm8.27179 0l0 -1.109375q-0.890625 1.28125 -2.421875 1.28125q-0.671875 0 -1.25 -0.25q-0.578125 -0.265625 -0.875 -0.65625q-0.28125 -0.390625 -0.390625 -0.953125q-0.078125 -0.375 -0.078125 -1.203125l0 -4.703125l1.28125 0l0 4.203125q0 1.015625 0.078125 1.359375q0.125 0.515625 0.515625 0.8125q0.40625 0.28125 0.984375 0.28125q0.578125 0 1.078125 -0.296875q0.515625 -0.296875 0.71875 -0.8125q0.21875 -0.515625 0.21875 -1.484375l0 -4.0625l1.28125 0l0 7.59375l-1.140625 0zm3.135437 0l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm2.0999146 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm14.291748 -3.84375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm2.791748 1.546875l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm7.328125 0l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm13.046875 -0.1875l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166687 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.7088013 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm3.7125854 4.234375q-1.0625 -1.34375 -1.796875 -3.140625q-0.734375 -1.8125 -0.734375 -3.734375q0 -1.703125 0.546875 -3.265625q0.640625 -1.8125 1.984375 -3.609375l0.921875 0q-0.859375 1.484375 -1.140625 2.125q-0.4375 0.984375 -0.6875 2.0625q-0.296875 1.34375 -0.296875 2.6875q0 3.453125 2.125 6.875l-0.921875 0zm2.4275513 -3.078125l0 -10.484375l1.28125 0l0 3.75q0.90625 -1.03125 2.28125 -1.03125q0.84375 0 1.46875 0.328125q0.625 0.328125 0.890625 0.921875q0.265625 0.578125 0.265625 1.703125l0 4.8125l-1.28125 0l0 -4.8125q0 -0.96875 -0.421875 -1.40625q-0.421875 -0.4375 -1.1875 -0.4375q-0.578125 0 -1.078125 0.296875q-0.5 0.296875 -0.71875 0.8125q-0.21875 0.5 -0.21875 1.390625l0 4.15625l-1.28125 0zm7.666687 -3.796875q0 -2.109375 1.171875 -3.125q0.984375 -0.84375 2.390625 -0.84375q1.578125 0 2.5625 1.03125q1.0 1.015625 1.0 2.828125q0 1.46875 -0.4375 2.3125q-0.4375 0.828125 -1.28125 1.296875q-0.84375 0.46875 -1.84375 0.46875q-1.59375 0 -2.578125 -1.015625q-0.984375 -1.03125 -0.984375 -2.953125zm1.328125 0q0 1.453125 0.625 2.1875q0.640625 0.71875 1.609375 0.71875q0.96875 0 1.59375 -0.71875q0.640625 -0.734375 0.640625 -2.234375q0 -1.40625 -0.640625 -2.125q-0.640625 -0.734375 -1.59375 -0.734375q-0.96875 0 -1.609375 0.71875q-0.625 0.71875 -0.625 2.1875zm6.791748 1.53125l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm10.65625 1.109375l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm2.1032104 4.234375l-0.921875 0q2.140625 -3.421875 2.140625 -6.875q0 -1.34375 -0.3125 -2.671875q-0.25 -1.0625 -0.671875 -2.046875q-0.28125 -0.65625 -1.15625 -2.15625l0.921875 0q1.34375 1.796875 1.984375 3.609375q0.546875 1.5625 0.546875 3.265625q0 1.921875 -0.734375 3.734375q-0.734375 1.796875 -1.796875 3.140625z" fill-rule="nonzero"/><path fill="#fce5cd" d="m151.53806 373.89502l105.60629 0l0 25.826752l-105.60629 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m151.53806 373.89502l105.60629 0l0 25.826752l-105.60629 0z" fill-rule="evenodd"/><path fill="#000000" d="m187.37477 391.8884l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm4.3806458 -2.265625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm10.65625 1.109375l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875zm0.07197571 4.0625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338608 -2.90625l0 -7.59375l1.15625 0l0 1.078125q0.84375 -1.25 2.421875 -1.25q0.6875 0 1.265625 0.25q0.578125 0.234375 0.859375 0.640625q0.28125 0.40625 0.40625 0.953125q0.0625 0.359375 0.0625 1.25l0 4.671875l-1.28125 0l0 -4.625q0 -0.78125 -0.15625 -1.171875q-0.15625 -0.390625 -0.546875 -0.625q-0.375 -0.234375 -0.890625 -0.234375q-0.8125 0 -1.421875 0.53125q-0.59375 0.515625 -0.59375 1.96875l0 4.15625l-1.28125 0zm8.151108 -9.015625l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0z" fill-rule="nonzero"/><path fill="#ffffff" d="m368.0 144.0l220.18896 0l0 356.7874l-220.18896 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m368.0 144.0l220.18896 0l0 356.7874l-220.18896 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m432.72702 147.20473l166.07877 0l0 38.803146l-166.07877 0z" fill-rule="evenodd"/><path fill="#000000" d="m442.94577 174.12473l0 -9.671875l1.46875 0l0 1.46875q0.5625 -1.03125 1.03125 -1.359375q0.484375 -0.328125 1.0625 -0.328125q0.828125 0 1.6875 0.53125l-0.5625 1.515625q-0.609375 -0.359375 -1.203125 -0.359375q-0.546875 0 -0.96875 0.328125q-0.421875 0.328125 -0.609375 0.890625q-0.28125 0.875 -0.28125 1.921875l0 5.0625l-1.625 0zm8.915802 0l-3.6875 -9.671875l1.734375 0l2.078125 5.796875q0.328125 0.9375 0.625 1.9375q0.203125 -0.765625 0.609375 -1.828125l2.140625 -5.90625l1.6875 0l-3.65625 9.671875l-1.53125 0zm5.125 3.703125l0 -1.1875l10.859375 0l0 1.1875l-10.859375 0zm11.891357 0l0 -13.375l1.484375 0l0 1.25q0.53125 -0.734375 1.1875 -1.09375q0.671875 -0.375 1.625 -0.375q1.234375 0 2.171875 0.640625q0.953125 0.625 1.4375 1.796875q0.484375 1.15625 0.484375 2.546875q0 1.484375 -0.53125 2.671875q-0.53125 1.1875 -1.546875 1.828125q-1.015625 0.625 -2.140625 0.625q-0.8125 0 -1.46875 -0.34375q-0.65625 -0.34375 -1.0625 -0.875l0 4.703125l-1.640625 0zm1.484375 -8.484375q0 1.859375 0.75 2.765625q0.765625 0.890625 1.828125 0.890625q1.09375 0 1.875 -0.921875q0.78125 -0.9375 0.78125 -2.875q0 -1.84375 -0.765625 -2.765625q-0.75 -0.921875 -1.8125 -0.921875q-1.046875 0 -1.859375 0.984375q-0.796875 0.96875 -0.796875 2.84375zm8.844452 4.78125l0 -13.359375l1.640625 0l0 13.359375l-1.640625 0zm4.1917114 -11.46875l0 -1.890625l1.640625 0l0 1.890625l-1.640625 0zm0 11.46875l0 -9.671875l1.640625 0l0 9.671875l-1.640625 0zm10.457306 -3.546875l1.609375 0.21875q-0.265625 1.65625 -1.359375 2.609375q-1.078125 0.9375 -2.671875 0.9375q-1.984375 0 -3.1875 -1.296875q-1.203125 -1.296875 -1.203125 -3.71875q0 -1.578125 0.515625 -2.75q0.515625 -1.171875 1.578125 -1.75q1.0625 -0.59375 2.3125 -0.59375q1.578125 0 2.578125 0.796875q1.0 0.796875 1.28125 2.265625l-1.59375 0.234375q-0.234375 -0.96875 -0.8125 -1.453125q-0.578125 -0.5 -1.390625 -0.5q-1.234375 0 -2.015625 0.890625q-0.78125 0.890625 -0.78125 2.8125q0 1.953125 0.75 2.84375q0.75 0.875 1.953125 0.875q0.96875 0 1.609375 -0.59375q0.65625 -0.59375 0.828125 -1.828125z" fill-rule="nonzero"/><path fill="#cfe2f3" d="m397.5223 197.6798l125.07089 0l0 144.37794l-125.07089 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m397.5223 197.6798l125.07089 0l0 144.37794l-125.07089 0z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m397.5223 197.6798l129.16537 0l0 61.354324l-129.16537 0z" fill-rule="evenodd"/><path fill="#000000" d="m407.56918 222.0398l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm11.015625 -2.671875l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.5703125 5.640625l1.375 0.203125q0.078125 0.640625 0.46875 0.921875q0.53125 0.390625 1.4375 0.390625q0.96875 0 1.5 -0.390625q0.53125 -0.390625 0.71875 -1.09375q0.109375 -0.421875 0.109375 -1.8125q-0.921875 1.09375 -2.296875 1.09375q-1.71875 0 -2.65625 -1.234375q-0.9375 -1.234375 -0.9375 -2.96875q0 -1.1875 0.421875 -2.1875q0.4375 -1.0 1.25 -1.546875q0.828125 -0.546875 1.921875 -0.546875q1.46875 0 2.421875 1.1875l0 -1.0l1.296875 0l0 7.171875q0 1.9375 -0.390625 2.75q-0.390625 0.8125 -1.25 1.28125q-0.859375 0.46875 -2.109375 0.46875q-1.484375 0 -2.40625 -0.671875q-0.90625 -0.671875 -0.875 -2.015625zm1.171875 -4.984375q0 1.625 0.640625 2.375q0.65625 0.75 1.625 0.75q0.96875 0 1.625 -0.734375q0.65625 -0.75 0.65625 -2.34375q0 -1.53125 -0.671875 -2.296875q-0.671875 -0.78125 -1.625 -0.78125q-0.9375 0 -1.59375 0.765625q-0.65625 0.765625 -0.65625 2.265625zm12.4375 -5.546875l0 -1.609375l1.40625 0l0 1.609375l-1.40625 0zm0 9.84375l0 -8.296875l1.40625 0l0 8.296875l-1.40625 0zm3.5546875 0l0 -8.296875l1.265625 0l0 1.171875q0.90625 -1.359375 2.640625 -1.359375q0.75 0 1.375 0.265625q0.625 0.265625 0.9375 0.703125q0.3125 0.4375 0.4375 1.046875q0.078125 0.390625 0.078125 1.359375l0 5.109375l-1.40625 0l0 -5.046875q0 -0.859375 -0.171875 -1.28125q-0.15625 -0.4375 -0.578125 -0.6875q-0.40625 -0.25 -0.96875 -0.25q-0.90625 0 -1.5625 0.578125q-0.640625 0.5625 -0.640625 2.15625l0 4.53125l-1.40625 0zm11.9609375 -1.265625l0.203125 1.25q-0.59375 0.125 -1.0625 0.125q-0.765625 0 -1.1875 -0.234375q-0.421875 -0.25 -0.59375 -0.640625q-0.171875 -0.40625 -0.171875 -1.671875l0 -4.765625l-1.03125 0l0 -1.09375l1.03125 0l0 -2.0625l1.40625 -0.84375l0 2.90625l1.40625 0l0 1.09375l-1.40625 0l0 4.84375q0 0.609375 0.0625 0.78125q0.078125 0.171875 0.25 0.28125q0.171875 0.09375 0.484375 0.09375q0.234375 0 0.609375 -0.0625zm7.0546875 -1.40625l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875zm7.8203125 4.953125l0 -8.296875l1.265625 0l0 1.25q0.484375 -0.875 0.890625 -1.15625q0.40625 -0.28125 0.90625 -0.28125q0.703125 0 1.4375 0.453125l-0.484375 1.296875q-0.515625 -0.296875 -1.03125 -0.296875q-0.453125 0 -0.828125 0.28125q-0.359375 0.265625 -0.515625 0.765625q-0.234375 0.75 -0.234375 1.640625l0 4.34375l-1.40625 0zm5.671875 0l0 -7.203125l-1.234375 0l0 -1.09375l1.234375 0l0 -0.890625q0 -0.828125 0.15625 -1.234375q0.203125 -0.546875 0.703125 -0.890625q0.515625 -0.34375 1.4375 -0.34375q0.59375 0 1.3125 0.140625l-0.203125 1.234375q-0.4375 -0.078125 -0.828125 -0.078125q-0.640625 0 -0.90625 0.28125q-0.265625 0.265625 -0.265625 1.015625l0 0.765625l1.609375 0l0 1.09375l-1.609375 0l0 7.203125l-1.40625 0zm9.5234375 -1.03125q-0.78125 0.671875 -1.5 0.953125q-0.71875 0.265625 -1.546875 0.265625q-1.375 0 -2.109375 -0.671875q-0.734375 -0.671875 -0.734375 -1.703125q0 -0.609375 0.28125 -1.109375q0.28125 -0.515625 0.71875 -0.8125q0.453125 -0.3125 1.015625 -0.46875q0.421875 -0.109375 1.25 -0.203125q1.703125 -0.203125 2.515625 -0.484375q0 -0.296875 0 -0.375q0 -0.859375 -0.390625 -1.203125q-0.546875 -0.484375 -1.609375 -0.484375q-0.984375 0 -1.46875 0.359375q-0.46875 0.34375 -0.6875 1.21875l-1.375 -0.1875q0.1875 -0.875 0.609375 -1.421875q0.4375 -0.546875 1.25 -0.828125q0.8125 -0.296875 1.875 -0.296875q1.0625 0 1.71875 0.25q0.671875 0.25 0.984375 0.625q0.3125 0.375 0.4375 0.953125q0.078125 0.359375 0.078125 1.296875l0 1.875q0 1.96875 0.078125 2.484375q0.09375 0.515625 0.359375 1.0l-1.46875 0q-0.21875 -0.4375 -0.28125 -1.03125zm-0.109375 -3.140625q-0.765625 0.3125 -2.296875 0.53125q-0.875 0.125 -1.234375 0.28125q-0.359375 0.15625 -0.5625 0.46875q-0.1875 0.296875 -0.1875 0.65625q0 0.5625 0.421875 0.9375q0.4375 0.375 1.25 0.375q0.8125 0 1.4375 -0.34375q0.640625 -0.359375 0.9375 -0.984375q0.234375 -0.46875 0.234375 -1.40625l0 -0.515625zm9.0078125 1.125l1.390625 0.1875q-0.234375 1.421875 -1.171875 2.234375q-0.921875 0.8125 -2.28125 0.8125q-1.703125 0 -2.75 -1.109375q-1.03125 -1.125 -1.03125 -3.203125q0 -1.34375 0.4375 -2.34375q0.453125 -1.015625 1.359375 -1.515625q0.921875 -0.5 1.984375 -0.5q1.359375 0 2.21875 0.6875q0.859375 0.671875 1.09375 1.9375l-1.359375 0.203125q-0.203125 -0.828125 -0.703125 -1.25q-0.484375 -0.421875 -1.1875 -0.421875q-1.0625 0 -1.734375 0.765625q-0.65625 0.75 -0.65625 2.40625q0 1.671875 0.640625 2.4375q0.640625 0.75 1.671875 0.75q0.828125 0 1.375 -0.5q0.5625 -0.515625 0.703125 -1.578125zm8.265625 0.375l1.453125 0.171875q-0.34375 1.28125 -1.28125 1.984375q-0.921875 0.703125 -2.359375 0.703125q-1.828125 0 -2.890625 -1.125q-1.0625 -1.125 -1.0625 -3.140625q0 -2.09375 1.078125 -3.25q1.078125 -1.15625 2.796875 -1.15625q1.65625 0 2.703125 1.140625q1.0625 1.125 1.0625 3.171875q0 0.125 0 0.375l-6.1875 0q0.078125 1.375 0.765625 2.109375q0.703125 0.71875 1.734375 0.71875q0.78125 0 1.328125 -0.40625q0.546875 -0.40625 0.859375 -1.296875zm-4.609375 -2.28125l4.625 0q-0.09375 -1.046875 -0.53125 -1.5625q-0.671875 -0.8125 -1.734375 -0.8125q-0.96875 0 -1.640625 0.65625q-0.65625 0.640625 -0.71875 1.71875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m522.5752 229.08836l48.188965 0.18896484" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m522.5752 229.08836l42.188965 0.16545105" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m564.7577 230.90552l4.5445557 -1.6339111l-4.531555 -1.6695251z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m570.2448 279.7787l-48.031494 0.09451294" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m570.2448 279.77872l-42.031494 0.08267212" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m528.21 278.20966l-4.534851 1.660675l4.541382 1.6427917z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m528.0 222.17323l66.64569 0l0 25.826767l-66.64569 0z" fill-rule="evenodd"/><path fill="#000000" d="m537.8594 243.97322l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.1883545 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.3031006 4.703125l1.140625 0.15625q0.078125 0.53125 0.40625 0.78125q0.4375 0.3125 1.1875 0.3125q0.8125 0 1.25 -0.328125q0.453125 -0.3125 0.609375 -0.90625q0.09375 -0.359375 0.078125 -1.5q-0.765625 0.90625 -1.90625 0.90625q-1.4375 0 -2.21875 -1.03125q-0.78125 -1.03125 -0.78125 -2.46875q0 -0.984375 0.359375 -1.8125q0.359375 -0.84375 1.03125 -1.296875q0.6875 -0.453125 1.609375 -0.453125q1.21875 0 2.015625 0.984375l0 -0.828125l1.078125 0l0 5.96875q0 1.609375 -0.328125 2.28125q-0.328125 0.6875 -1.046875 1.078125q-0.703125 0.390625 -1.75 0.390625q-1.234375 0 -2.0 -0.5625q-0.75 -0.5625 -0.734375 -1.671875zm0.984375 -4.15625q0 1.359375 0.53125 1.984375q0.546875 0.625 1.359375 0.625q0.796875 0 1.34375 -0.625q0.546875 -0.625 0.546875 -1.953125q0 -1.265625 -0.5625 -1.90625q-0.5625 -0.640625 -1.359375 -0.640625q-0.765625 0 -1.3125 0.640625q-0.546875 0.625 -0.546875 1.875zm12.474976 2.453125l0 1.125l-6.296875 0q-0.015625 -0.421875 0.140625 -0.8125q0.234375 -0.640625 0.765625 -1.265625q0.53125 -0.625 1.53125 -1.453125q1.5625 -1.265625 2.109375 -2.015625q0.546875 -0.75 0.546875 -1.40625q0 -0.703125 -0.5 -1.171875q-0.5 -0.484375 -1.296875 -0.484375q-0.859375 0 -1.375 0.515625q-0.5 0.5 -0.5 1.390625l-1.203125 -0.109375q0.125 -1.359375 0.921875 -2.0625q0.8125 -0.703125 2.171875 -0.703125q1.375 0 2.171875 0.765625q0.8125 0.75 0.8125 1.875q0 0.578125 -0.234375 1.140625q-0.234375 0.546875 -0.78125 1.15625q-0.546875 0.609375 -1.8125 1.671875q-1.046875 0.890625 -1.359375 1.21875q-0.296875 0.3125 -0.484375 0.625l4.671875 0zm1.5843506 1.125l0 -9.546875l1.171875 0l0 3.421875q0.828125 -0.9375 2.078125 -0.9375q0.765625 0 1.328125 0.296875q0.5625 0.296875 0.8125 0.84375q0.25 0.53125 0.25 1.546875l0 4.375l-1.171875 0l0 -4.375q0 -0.890625 -0.390625 -1.28125q-0.375 -0.40625 -1.078125 -0.40625q-0.515625 0 -0.984375 0.28125q-0.453125 0.265625 -0.65625 0.734375q-0.1875 0.453125 -0.1875 1.265625l0 3.78125l-1.171875 0zm8.693726 0l-2.125 -6.90625l1.21875 0l1.09375 3.984375l0.421875 1.484375q0.015625 -0.109375 0.359375 -1.421875l1.09375 -4.046875l1.203125 0l1.03125 4.0l0.34375 1.328125l0.40625 -1.34375l1.171875 -3.984375l1.140625 0l-2.15625 6.90625l-1.21875 0l-1.09375 -4.140625l-0.265625 -1.171875l-1.40625 5.3125l-1.21875 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m528.0 270.17322l66.64569 0l0 25.826782l-66.64569 0z" fill-rule="evenodd"/><path fill="#000000" d="m537.875 291.97324l0 -9.546875l1.171875 0l0 3.421875q0.828125 -0.9375 2.078125 -0.9375q0.765625 0 1.328125 0.296875q0.5625 0.296875 0.8125 0.84375q0.25 0.53125 0.25 1.546875l0 4.375l-1.171875 0l0 -4.375q0 -0.890625 -0.390625 -1.28125q-0.375 -0.40625 -1.078125 -0.40625q-0.515625 0 -0.984375 0.28125q-0.453125 0.265625 -0.65625 0.734375q-0.1875 0.453125 -0.1875 1.265625l0 3.78125l-1.171875 0zm8.693726 0l-2.125 -6.90625l1.21875 0l1.09375 3.984375l0.421875 1.484375q0.015625 -0.109375 0.359375 -1.421875l1.09375 -4.046875l1.203125 0l1.03125 4.0l0.34375 1.328125l0.40625 -1.34375l1.171875 -3.984375l1.140625 0l-2.15625 6.90625l-1.21875 0l-1.09375 -4.140625l-0.265625 -1.171875l-1.40625 5.3125l-1.21875 0zm14.171997 -1.125l0 1.125l-6.296875 0q-0.015625 -0.421875 0.140625 -0.8125q0.234375 -0.640625 0.765625 -1.265625q0.53125 -0.625 1.53125 -1.453125q1.5625 -1.265625 2.109375 -2.015625q0.546875 -0.75 0.546875 -1.40625q0 -0.703125 -0.5 -1.171875q-0.5 -0.484375 -1.296875 -0.484375q-0.859375 0 -1.375 0.515625q-0.5 0.5 -0.5 1.390625l-1.203125 -0.109375q0.125 -1.359375 0.921875 -2.0625q0.8125 -0.703125 2.171875 -0.703125q1.375 0 2.171875 0.765625q0.8125 0.75 0.8125 1.875q0 0.578125 -0.234375 1.140625q-0.234375 0.546875 -0.78125 1.15625q-0.546875 0.609375 -1.8125 1.671875q-1.046875 0.890625 -1.359375 1.21875q-0.296875 0.3125 -0.484375 0.625l4.671875 0zm1.5687256 1.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.188416 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.3031006 4.703125l1.140625 0.15625q0.078125 0.53125 0.40625 0.78125q0.4375 0.3125 1.1875 0.3125q0.8125 0 1.25 -0.328125q0.453125 -0.3125 0.609375 -0.90625q0.09375 -0.359375 0.078125 -1.5q-0.765625 0.90625 -1.90625 0.90625q-1.4375 0 -2.21875 -1.03125q-0.78125 -1.03125 -0.78125 -2.46875q0 -0.984375 0.359375 -1.8125q0.359375 -0.84375 1.03125 -1.296875q0.6875 -0.453125 1.609375 -0.453125q1.21875 0 2.015625 0.984375l0 -0.828125l1.078125 0l0 5.96875q0 1.609375 -0.328125 2.28125q-0.328125 0.6875 -1.046875 1.078125q-0.703125 0.390625 -1.75 0.390625q-1.234375 0 -2.0 -0.5625q-0.75 -0.5625 -0.734375 -1.671875zm0.984375 -4.15625q0 1.359375 0.53125 1.984375q0.546875 0.625 1.359375 0.625q0.796875 0 1.34375 -0.625q0.546875 -0.625 0.546875 -1.953125q0 -1.265625 -0.5625 -1.90625q-0.5625 -0.640625 -1.359375 -0.640625q-0.765625 0 -1.3125 0.640625q-0.546875 0.625 -0.546875 1.875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m595.59845 283.51443l72.724365 0l0 40.22046l-72.724365 0z" fill-rule="evenodd"/><path fill="#000000" d="m608.0516 305.31442l0 -8.421875l-3.140625 0l0 -1.125l7.5625 0l0 1.125l-3.15625 0l0 8.421875l-1.265625 0zm5.6569824 0l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0zm13.724976 -9.546875l1.265625 0l0 5.515625q0 1.4375 -0.328125 2.296875q-0.3125 0.84375 -1.171875 1.375q-0.84375 0.515625 -2.21875 0.515625q-1.34375 0 -2.203125 -0.453125q-0.84375 -0.46875 -1.21875 -1.34375q-0.359375 -0.875 -0.359375 -2.390625l0 -5.515625l1.265625 0l0 5.515625q0 1.234375 0.21875 1.828125q0.234375 0.59375 0.796875 0.921875q0.5625 0.3125 1.390625 0.3125q1.390625 0 1.96875 -0.625q0.59375 -0.640625 0.59375 -2.4375l0 -5.515625zm3.312622 9.546875l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0z" fill-rule="nonzero"/><path fill="#000000" d="m609.9578 321.31442l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm11.365601 1.234375l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm8.443726 4.125l-2.625 -6.90625l1.234375 0l1.484375 4.140625q0.234375 0.65625 0.4375 1.390625q0.15625 -0.546875 0.4375 -1.3125l1.53125 -4.21875l1.21875 0l-2.625 6.90625l-1.09375 0zm4.7578125 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm7.4610596 -2.53125l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm6.8828125 0.3125l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m258.11023 322.3937l109.88977 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m258.11023 322.3937l103.88977 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m362.0 324.04544l4.538086 -1.6517334l-4.538086 -1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m257.14435 386.8084l109.88977 0" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m257.14435 386.8084l103.88977 0" fill-rule="evenodd"/><path fill="#000000" stroke="#000000" stroke-width="1.0" stroke-linecap="butt" d="m361.03412 388.46014l4.538086 -1.6517334l-4.538086 -1.6517334z" fill-rule="evenodd"/><path fill="#000000" fill-opacity="0.0" d="m296.20078 318.09842l66.64569 0l0 25.826782l-66.64569 0z" fill-rule="evenodd"/><path fill="#000000" d="m310.5914 337.3672l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm2.1328125 2.53125l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm2.539215 -3.453125q0 -1.921875 1.078125 -2.84375q0.890625 -0.765625 2.171875 -0.765625q1.421875 0 2.328125 0.9375q0.90625 0.921875 0.90625 2.578125q0 1.328125 -0.40625 2.09375q-0.390625 0.765625 -1.15625 1.1875q-0.765625 0.421875 -1.671875 0.421875q-1.453125 0 -2.359375 -0.921875q-0.890625 -0.9375 -0.890625 -2.6875zm1.203125 0q0 1.328125 0.578125 1.984375q0.59375 0.65625 1.46875 0.65625q0.875 0 1.453125 -0.65625q0.578125 -0.671875 0.578125 -2.03125q0 -1.28125 -0.59375 -1.9375q-0.578125 -0.65625 -1.4375 -0.65625q-0.875 0 -1.46875 0.65625q-0.578125 0.65625 -0.578125 1.984375zm11.162476 0.921875l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm2.1640625 2.53125l0 -9.546875l1.171875 0l0 5.453125l2.765625 -2.8125l1.515625 0l-2.640625 2.5625l2.90625 4.34375l-1.4375 0l-2.28125 -3.53125l-0.828125 0.796875l0 2.734375l-1.171875 0z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m296.2021 380.8609l89.543304 0l0 25.826752l-89.543304 0z" fill-rule="evenodd"/><path fill="#000000" d="m306.06146 402.6609l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.188385 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.0531006 2.0625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625zm11.8671875 -0.15625l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm9.084351 3.078125l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875z" fill-rule="nonzero"/><path fill="#ffffff" d="m587.22363 268.10236l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m587.22363 268.10236l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path fill="#fce5cd" d="m668.3307 360.20996l146.04724 0l0 38.80316l-146.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m668.3307 360.20996l146.04724 0l0 38.80316l-146.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m697.10065 384.69156l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.0056763 0l-2.890625 -7.59375l1.359375 0l1.625 4.546875q0.265625 0.734375 0.5 1.53125q0.15625 -0.609375 0.46875 -1.453125l1.6875 -4.625l1.328125 0l-2.875 7.59375l-1.203125 0zm4.03125 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338562 0l0 -10.5l1.171875 0l0 0.984375q0.421875 -0.578125 0.9375 -0.859375q0.515625 -0.296875 1.265625 -0.296875q0.96875 0 1.71875 0.5q0.75 0.5 1.125 1.421875q0.375 0.90625 0.375 1.984375q0 1.171875 -0.421875 2.109375q-0.40625 0.921875 -1.21875 1.421875q-0.796875 0.5 -1.671875 0.5q-0.640625 0 -1.15625 -0.265625q-0.515625 -0.28125 -0.84375 -0.6875l0 3.6875l-1.28125 0zm1.15625 -6.65625q0 1.453125 0.59375 2.15625q0.609375 0.703125 1.453125 0.703125q0.859375 0 1.46875 -0.71875q0.609375 -0.734375 0.609375 -2.25q0 -1.453125 -0.609375 -2.171875q-0.59375 -0.734375 -1.421875 -0.734375q-0.8125 0 -1.453125 0.78125q-0.640625 0.765625 -0.640625 2.234375zm6.963623 3.75l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm3.2874146 -9.015625l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm8.20929 -2.78125l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm1.1875 5.6875l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm14.291687 -3.84375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm2.791748 1.546875l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm7.328125 0l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm13.046875 -0.1875l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.70874 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m591.8963 391.05905l72.72443 0l0 40.22049l-72.72443 0z" fill-rule="evenodd"/><path fill="#000000" d="m601.7557 412.85904l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm6.3759155 0l-2.625 -6.90625l1.234375 0l1.484375 4.140625q0.234375 0.65625 0.4375 1.390625q0.15625 -0.546875 0.4375 -1.3125l1.53125 -4.21875l1.21875 0l-2.625 6.90625l-1.09375 0zm3.6640625 2.65625l0 -0.859375l7.765625 0l0 0.859375l-7.765625 0zm8.490601 0l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125zm6.3343506 3.421875l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm2.9923096 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm7.4611206 -2.53125l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875z" fill-rule="nonzero"/><path fill="#000000" d="m601.3338 425.4059q0 -1.921875 1.078125 -2.84375q0.890625 -0.765625 2.171875 -0.765625q1.421875 0 2.328125 0.9375q0.90625 0.921875 0.90625 2.578125q0 1.328125 -0.40625 2.09375q-0.390625 0.765625 -1.15625 1.1875q-0.765625 0.421875 -1.671875 0.421875q-1.453125 0 -2.359375 -0.921875q-0.890625 -0.9375 -0.890625 -2.6875zm1.203125 0q0 1.328125 0.578125 1.984375q0.59375 0.65625 1.46875 0.65625q0.875 0 1.453125 -0.65625q0.578125 -0.671875 0.578125 -2.03125q0 -1.28125 -0.59375 -1.9375q-0.578125 -0.65625 -1.4375 -0.65625q-0.875 0 -1.46875 0.65625q-0.578125 0.65625 -0.578125 1.984375zm11.178101 3.453125l0 -1.015625q-0.8125 1.171875 -2.1875 1.171875q-0.609375 0 -1.140625 -0.234375q-0.53125 -0.234375 -0.796875 -0.578125q-0.25 -0.359375 -0.359375 -0.875q-0.0625 -0.34375 -0.0625 -1.09375l0 -4.28125l1.171875 0l0 3.828125q0 0.921875 0.0625 1.234375q0.109375 0.46875 0.46875 0.734375q0.359375 0.25 0.890625 0.25q0.515625 0 0.984375 -0.265625q0.46875 -0.265625 0.65625 -0.734375q0.1875 -0.46875 0.1875 -1.34375l0 -3.703125l1.171875 0l0 6.90625l-1.046875 0zm5.4437256 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm1.1405029 3.703125l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125zm10.881226 3.421875l0 -1.015625q-0.8125 1.171875 -2.1875 1.171875q-0.609375 0 -1.140625 -0.234375q-0.53125 -0.234375 -0.796875 -0.578125q-0.25 -0.359375 -0.359375 -0.875q-0.0625 -0.34375 -0.0625 -1.09375l0 -4.28125l1.171875 0l0 3.828125q0 0.921875 0.0625 1.234375q0.109375 0.46875 0.46875 0.734375q0.359375 0.25 0.890625 0.25q0.515625 0 0.984375 -0.265625q0.46875 -0.265625 0.65625 -0.734375q0.1875 -0.46875 0.1875 -1.34375l0 -3.703125l1.171875 0l0 6.90625l-1.046875 0zm5.4437256 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm0.6717529 -1.015625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625z" fill-rule="nonzero"/><path fill="#ffffff" d="m587.22363 379.61154l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m587.22363 379.61154l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11023l0 -10.055115l-36.5354 0l0 10.055115z" fill-rule="evenodd"/><path fill="#ffffff" d="m587.22363 476.66403l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11026l0 -10.055145l-36.5354 0l0 10.055145z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m587.22363 476.66403l20.11023 -20.11023l0 10.055115l36.5354 0l0 -10.055115l20.11023 20.11023l-20.11023 20.11026l0 -10.055145l-36.5354 0l0 10.055145z" fill-rule="evenodd"/><path fill="#fce5cd" d="m668.3307 457.26248l146.04724 0l0 38.80313l-146.04724 0z" fill-rule="evenodd"/><path stroke="#000000" stroke-width="1.0" stroke-linejoin="round" stroke-linecap="butt" d="m668.3307 457.26248l146.04724 0l0 38.80313l-146.04724 0z" fill-rule="evenodd"/><path fill="#000000" d="m683.25665 481.74405l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.005615 0l-2.890625 -7.59375l1.359375 0l1.625 4.546875q0.265625 0.734375 0.5 1.53125q0.15625 -0.609375 0.46875 -1.453125l1.6875 -4.625l1.328125 0l-2.875 7.59375l-1.203125 0zm4.03125 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm9.338623 0l0 -10.5l1.171875 0l0 0.984375q0.421875 -0.578125 0.9375 -0.859375q0.515625 -0.296875 1.265625 -0.296875q0.96875 0 1.71875 0.5q0.75 0.5 1.125 1.421875q0.375 0.90625 0.375 1.984375q0 1.171875 -0.421875 2.109375q-0.40625 0.921875 -1.21875 1.421875q-0.796875 0.5 -1.671875 0.5q-0.640625 0 -1.15625 -0.265625q-0.515625 -0.28125 -0.84375 -0.6875l0 3.6875l-1.28125 0zm1.15625 -6.65625q0 1.453125 0.59375 2.15625q0.609375 0.703125 1.453125 0.703125q0.859375 0 1.46875 -0.71875q0.609375 -0.734375 0.609375 -2.25q0 -1.453125 -0.609375 -2.171875q-0.59375 -0.734375 -1.421875 -0.734375q-0.8125 0 -1.453125 0.78125q-0.640625 0.765625 -0.640625 2.234375zm6.963623 3.75l0 -10.484375l1.28125 0l0 10.484375l-1.28125 0zm3.2874146 -9.015625l0 -1.46875l1.296875 0l0 1.46875l-1.296875 0zm0 9.015625l0 -7.59375l1.296875 0l0 7.59375l-1.296875 0zm8.2092285 -2.78125l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm1.1875 5.6875l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm14.291748 -5.6875l1.265625 0.15625q-0.203125 1.3125 -1.0625 2.0625q-0.84375 0.734375 -2.09375 0.734375q-1.5625 0 -2.515625 -1.015625q-0.9375 -1.03125 -0.9375 -2.921875q0 -1.234375 0.40625 -2.15625q0.40625 -0.921875 1.234375 -1.375q0.84375 -0.46875 1.8125 -0.46875q1.25 0 2.03125 0.625q0.78125 0.625 1.015625 1.765625l-1.265625 0.203125q-0.171875 -0.765625 -0.625 -1.15625q-0.453125 -0.390625 -1.09375 -0.390625q-0.984375 0 -1.59375 0.703125q-0.609375 0.703125 -0.609375 2.203125q0 1.53125 0.578125 2.234375q0.59375 0.6875 1.546875 0.6875q0.75 0 1.265625 -0.453125q0.515625 -0.46875 0.640625 -1.4375zm1.859375 0.515625l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm7.828125 2.265625l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm3.7088013 2.90625l0 -0.921875l8.53125 0l0 0.921875l-8.53125 0zm14.291687 -3.84375q-0.71875 0.609375 -1.375 0.859375q-0.65625 0.25 -1.421875 0.25q-1.25 0 -1.921875 -0.609375q-0.671875 -0.609375 -0.671875 -1.5625q0 -0.5625 0.25 -1.015625q0.25 -0.46875 0.65625 -0.75q0.421875 -0.28125 0.9375 -0.421875q0.375 -0.09375 1.140625 -0.1875q1.5625 -0.1875 2.296875 -0.453125q0.015625 -0.265625 0.015625 -0.328125q0 -0.796875 -0.375 -1.109375q-0.484375 -0.4375 -1.453125 -0.4375q-0.921875 0 -1.359375 0.328125q-0.421875 0.3125 -0.625 1.109375l-1.265625 -0.171875q0.171875 -0.796875 0.5625 -1.296875q0.390625 -0.5 1.140625 -0.765625q0.75 -0.265625 1.71875 -0.265625q0.984375 0 1.59375 0.234375q0.609375 0.21875 0.890625 0.5625q0.28125 0.34375 0.40625 0.875q0.0625 0.328125 0.0625 1.1875l0 1.71875q0 1.796875 0.078125 2.28125q0.078125 0.46875 0.328125 0.90625l-1.34375 0q-0.203125 -0.40625 -0.265625 -0.9375zm-0.109375 -2.875q-0.703125 0.28125 -2.09375 0.484375q-0.796875 0.109375 -1.125 0.265625q-0.328125 0.140625 -0.515625 0.421875q-0.171875 0.265625 -0.171875 0.59375q0 0.515625 0.390625 0.859375q0.390625 0.34375 1.140625 0.34375q0.734375 0 1.3125 -0.3125q0.59375 -0.328125 0.859375 -0.890625q0.203125 -0.4375 0.203125 -1.296875l0 -0.46875zm2.791748 1.546875l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm7.328125 0l1.265625 -0.203125q0.109375 0.765625 0.59375 1.171875q0.5 0.40625 1.375 0.40625q0.890625 0 1.3125 -0.359375q0.4375 -0.359375 0.4375 -0.84375q0 -0.4375 -0.375 -0.6875q-0.265625 -0.171875 -1.3125 -0.4375q-1.421875 -0.359375 -1.96875 -0.609375q-0.546875 -0.265625 -0.828125 -0.734375q-0.28125 -0.46875 -0.28125 -1.015625q0 -0.515625 0.21875 -0.9375q0.234375 -0.4375 0.640625 -0.734375q0.296875 -0.21875 0.8125 -0.359375q0.53125 -0.15625 1.125 -0.15625q0.890625 0 1.5625 0.265625q0.671875 0.25 1.0 0.6875q0.328125 0.4375 0.4375 1.171875l-1.25 0.171875q-0.09375 -0.578125 -0.5 -0.90625q-0.40625 -0.34375 -1.15625 -0.34375q-0.890625 0 -1.28125 0.296875q-0.375 0.296875 -0.375 0.6875q0 0.25 0.15625 0.453125q0.15625 0.203125 0.5 0.34375q0.1875 0.078125 1.140625 0.328125q1.359375 0.359375 1.890625 0.59375q0.546875 0.234375 0.859375 0.6875q0.3125 0.4375 0.3125 1.09375q0 0.640625 -0.375 1.21875q-0.375 0.5625 -1.09375 0.875q-0.703125 0.3125 -1.59375 0.3125q-1.484375 0 -2.265625 -0.609375q-0.765625 -0.625 -0.984375 -1.828125zm13.046875 -0.1875l1.328125 0.171875q-0.3125 1.171875 -1.171875 1.8125q-0.84375 0.640625 -2.171875 0.640625q-1.671875 0 -2.65625 -1.015625q-0.96875 -1.03125 -0.96875 -2.890625q0 -1.921875 0.984375 -2.96875q1.0 -1.0625 2.578125 -1.0625q1.515625 0 2.484375 1.03125q0.96875 1.03125 0.96875 2.921875q0 0.109375 -0.015625 0.34375l-5.65625 0q0.0625 1.25 0.703125 1.921875q0.640625 0.65625 1.59375 0.65625q0.703125 0 1.203125 -0.359375q0.5 -0.375 0.796875 -1.203125zm-4.234375 -2.078125l4.25 0q-0.09375 -0.953125 -0.484375 -1.4375q-0.625 -0.75 -1.609375 -0.75q-0.875 0 -1.484375 0.59375q-0.609375 0.59375 -0.671875 1.59375zm7.166748 4.53125l0 -7.59375l1.15625 0l0 1.140625q0.453125 -0.796875 0.828125 -1.046875q0.375 -0.265625 0.8125 -0.265625q0.65625 0 1.328125 0.40625l-0.4375 1.203125q-0.46875 -0.28125 -0.953125 -0.28125q-0.421875 0 -0.765625 0.25q-0.328125 0.25 -0.46875 0.703125q-0.21875 0.6875 -0.21875 1.5l0 3.984375l-1.28125 0zm7.70874 -1.15625l0.1875 1.140625q-0.546875 0.109375 -0.984375 0.109375q-0.6875 0 -1.078125 -0.21875q-0.390625 -0.21875 -0.546875 -0.578125q-0.15625 -0.359375 -0.15625 -1.515625l0 -4.375l-0.953125 0l0 -1.0l0.953125 0l0 -1.890625l1.28125 -0.765625l0 2.65625l1.296875 0l0 1.0l-1.296875 0l0 4.4375q0 0.546875 0.0625 0.71875q0.078125 0.15625 0.21875 0.25q0.15625 0.078125 0.453125 0.078125q0.203125 0 0.5625 -0.046875z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m589.23914 488.70078l89.543274 0l0 40.22049l-89.543274 0z" fill-rule="evenodd"/><path fill="#000000" d="m601.69226 510.5008l0 -8.421875l-3.140625 0l0 -1.125l7.5625 0l0 1.125l-3.15625 0l0 8.421875l-1.265625 0zm5.6569824 0l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0zm13.724976 -9.546875l1.265625 0l0 5.515625q0 1.4375 -0.328125 2.296875q-0.3125 0.84375 -1.171875 1.375q-0.84375 0.515625 -2.21875 0.515625q-1.34375 0 -2.203125 -0.453125q-0.84375 -0.46875 -1.21875 -1.34375q-0.359375 -0.875 -0.359375 -2.390625l0 -5.515625l1.265625 0l0 5.515625q0 1.234375 0.21875 1.828125q0.234375 0.59375 0.796875 0.921875q0.5625 0.3125 1.390625 0.3125q1.390625 0 1.96875 -0.625q0.59375 -0.640625 0.59375 -2.4375l0 -5.515625zm3.312622 9.546875l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0z" fill-rule="nonzero"/><path fill="#000000" d="m599.0985 526.5008l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm9.1883545 -2.21875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm11.037476 3.265625q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm7.4749756 3.46875l0 -0.875q-0.65625 1.03125 -1.9375 1.03125q-0.8125 0 -1.515625 -0.453125q-0.6875 -0.453125 -1.078125 -1.265625q-0.375 -0.828125 -0.375 -1.890625q0 -1.03125 0.34375 -1.875q0.34375 -0.84375 1.03125 -1.28125q0.703125 -0.453125 1.546875 -0.453125q0.625 0 1.109375 0.265625q0.5 0.25 0.796875 0.671875l0 -3.421875l1.171875 0l0 9.546875l-1.09375 0zm-3.703125 -3.453125q0 1.328125 0.5625 1.984375q0.5625 0.65625 1.328125 0.65625q0.765625 0 1.296875 -0.625q0.53125 -0.625 0.53125 -1.90625q0 -1.421875 -0.546875 -2.078125q-0.546875 -0.671875 -1.34375 -0.671875q-0.78125 0 -1.3125 0.640625q-0.515625 0.625 -0.515625 2.0zm5.7562256 3.609375l2.765625 -9.859375l0.9375 0l-2.765625 9.859375l-0.9375 0zm5.859253 -0.15625l-2.125 -6.90625l1.21875 0l1.09375 3.984375l0.421875 1.484375q0.015625 -0.109375 0.359375 -1.421875l1.09375 -4.046875l1.203125 0l1.03125 4.0l0.34375 1.328125l0.40625 -1.34375l1.171875 -3.984375l1.140625 0l-2.15625 6.90625l-1.21875 0l-1.09375 -4.140625l-0.265625 -1.171875l-1.40625 5.3125l-1.21875 0zm8.328247 0l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm4.4696045 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm5.5079956 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm5.874878 -1.171875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375z" fill-rule="nonzero"/><path fill="#000000" fill-opacity="0.0" d="m380.22574 456.5538l202.64566 0l0 40.22049l-202.64566 0z" fill-rule="evenodd"/><path fill="#000000" d="m390.0851 478.3538l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm6.375885 0l-2.625 -6.90625l1.234375 0l1.484375 4.140625q0.234375 0.65625 0.4375 1.390625q0.15625 -0.546875 0.4375 -1.3125l1.53125 -4.21875l1.21875 0l-2.625 6.90625l-1.09375 0zm3.6640625 2.65625l0 -0.859375l7.765625 0l0 0.859375l-7.765625 0zm8.490601 0l0 -9.5625l1.078125 0l0 0.890625q0.375 -0.53125 0.84375 -0.78125q0.484375 -0.265625 1.15625 -0.265625q0.875 0 1.546875 0.453125q0.6875 0.453125 1.03125 1.28125q0.34375 0.828125 0.34375 1.828125q0 1.046875 -0.375 1.90625q-0.375 0.84375 -1.109375 1.296875q-0.71875 0.453125 -1.53125 0.453125q-0.578125 0 -1.046875 -0.25q-0.46875 -0.25 -0.765625 -0.625l0 3.375l-1.171875 0zm1.0625 -6.078125q0 1.34375 0.53125 1.984375q0.546875 0.625 1.3125 0.625q0.78125 0 1.34375 -0.65625q0.5625 -0.65625 0.5625 -2.046875q0 -1.3125 -0.546875 -1.96875q-0.546875 -0.671875 -1.296875 -0.671875q-0.75 0 -1.328125 0.703125q-0.578125 0.703125 -0.578125 2.03125zm6.3343506 3.421875l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm2.99234 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm7.46109 -2.53125l1.15625 0.15625q-0.1875 1.1875 -0.96875 1.859375q-0.78125 0.671875 -1.921875 0.671875q-1.40625 0 -2.28125 -0.921875q-0.859375 -0.9375 -0.859375 -2.65625q0 -1.125 0.375 -1.96875q0.375 -0.84375 1.125 -1.25q0.765625 -0.421875 1.65625 -0.421875q1.125 0 1.84375 0.578125q0.71875 0.5625 0.921875 1.609375l-1.140625 0.171875q-0.171875 -0.703125 -0.59375 -1.046875q-0.40625 -0.359375 -0.984375 -0.359375q-0.890625 0 -1.453125 0.640625q-0.546875 0.640625 -0.546875 2.0q0 1.40625 0.53125 2.03125q0.546875 0.625 1.40625 0.625q0.6875 0 1.140625 -0.421875q0.46875 -0.421875 0.59375 -1.296875zm6.023285 2.53125l0 -9.546875l4.234375 0q1.265625 0 1.921875 0.265625q0.671875 0.25 1.0625 0.90625q0.40625 0.65625 0.40625 1.4375q0 1.015625 -0.65625 1.71875q-0.65625 0.6875 -2.03125 0.875q0.5 0.25 0.765625 0.484375q0.546875 0.5 1.046875 1.265625l1.65625 2.59375l-1.578125 0l-1.265625 -1.984375q-0.5625 -0.859375 -0.921875 -1.3125q-0.34375 -0.453125 -0.640625 -0.640625q-0.28125 -0.1875 -0.5625 -0.25q-0.21875 -0.046875 -0.703125 -0.046875l-1.46875 0l0 4.234375l-1.265625 0zm1.265625 -5.328125l2.71875 0q0.859375 0 1.34375 -0.171875q0.484375 -0.1875 0.734375 -0.578125q0.265625 -0.390625 0.265625 -0.859375q0 -0.671875 -0.5 -1.109375q-0.484375 -0.4375 -1.546875 -0.4375l-3.015625 0l0 3.15625zm10.524902 5.328125l0 -8.421875l-3.140625 0l0 -1.125l7.5625 0l0 1.125l-3.15625 0l0 8.421875l-1.265625 0zm5.6569824 0l0 -9.546875l1.265625 0l0 8.421875l4.703125 0l0 1.125l-5.96875 0zm10.5425415 -8.1875l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm2.945465 0l0 -6.90625l1.0625 0l0 0.984375q0.75 -1.140625 2.1875 -1.140625q0.625 0 1.15625 0.21875q0.53125 0.21875 0.78125 0.59375q0.265625 0.359375 0.375 0.859375q0.0625 0.328125 0.0625 1.140625l0 4.25l-1.171875 0l0 -4.203125q0 -0.71875 -0.140625 -1.0625q-0.140625 -0.359375 -0.484375 -0.5625q-0.34375 -0.21875 -0.8125 -0.21875q-0.75 0 -1.296875 0.46875q-0.546875 0.46875 -0.546875 1.796875l0 3.78125l-1.171875 0zm9.974976 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm5.8748474 -1.171875l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.5062256 4.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm4.45401 0l0 -6.90625l1.0625 0l0 0.984375q0.75 -1.140625 2.1875 -1.140625q0.625 0 1.15625 0.21875q0.53125 0.21875 0.78125 0.59375q0.265625 0.359375 0.375 0.859375q0.0625 0.328125 0.0625 1.140625l0 4.25l-1.171875 0l0 -4.203125q0 -0.71875 -0.140625 -1.0625q-0.140625 -0.359375 -0.484375 -0.5625q-0.34375 -0.21875 -0.8125 -0.21875q-0.75 0 -1.296875 0.46875q-0.546875 0.46875 -0.546875 1.796875l0 3.78125l-1.171875 0zm11.928101 -0.859375q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm2.9749756 3.46875l0 -9.546875l1.171875 0l0 9.546875l-1.171875 0zm11.1953125 -0.859375q-0.65625 0.5625 -1.265625 0.796875q-0.59375 0.21875 -1.28125 0.21875q-1.140625 0 -1.75 -0.546875q-0.609375 -0.5625 -0.609375 -1.4375q0 -0.5 0.21875 -0.921875q0.234375 -0.421875 0.609375 -0.671875q0.375 -0.25 0.84375 -0.390625q0.34375 -0.078125 1.046875 -0.171875q1.421875 -0.171875 2.09375 -0.40625q0 -0.234375 0 -0.296875q0 -0.71875 -0.328125 -1.015625q-0.453125 -0.390625 -1.34375 -0.390625q-0.8125 0 -1.21875 0.296875q-0.390625 0.28125 -0.578125 1.015625l-1.140625 -0.15625q0.15625 -0.734375 0.515625 -1.1875q0.359375 -0.453125 1.03125 -0.6875q0.671875 -0.25 1.5625 -0.25q0.890625 0 1.4375 0.203125q0.5625 0.203125 0.8125 0.53125q0.265625 0.3125 0.375 0.796875q0.046875 0.296875 0.046875 1.078125l0 1.5625q0 1.625 0.078125 2.0625q0.078125 0.4375 0.296875 0.828125l-1.21875 0q-0.1875 -0.359375 -0.234375 -0.859375zm-0.09375 -2.609375q-0.640625 0.265625 -1.921875 0.4375q-0.71875 0.109375 -1.015625 0.25q-0.296875 0.125 -0.46875 0.375q-0.15625 0.25 -0.15625 0.546875q0 0.46875 0.34375 0.78125q0.359375 0.3125 1.046875 0.3125q0.671875 0 1.203125 -0.296875q0.53125 -0.296875 0.78125 -0.8125q0.1875 -0.390625 0.1875 -1.171875l0 -0.421875zm2.5218506 1.40625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625zm6.6640625 0l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625zm11.8671875 -0.15625l1.203125 0.140625q-0.28125 1.0625 -1.0625 1.65625q-0.765625 0.578125 -1.96875 0.578125q-1.515625 0 -2.40625 -0.9375q-0.890625 -0.9375 -0.890625 -2.609375q0 -1.75 0.890625 -2.703125q0.90625 -0.96875 2.34375 -0.96875q1.390625 0 2.265625 0.9375q0.875 0.9375 0.875 2.65625q0 0.109375 0 0.3125l-5.15625 0q0.0625 1.140625 0.640625 1.75q0.578125 0.59375 1.4375 0.59375q0.65625 0 1.109375 -0.328125q0.453125 -0.34375 0.71875 -1.078125zm-3.84375 -1.90625l3.859375 0q-0.078125 -0.859375 -0.4375 -1.296875q-0.5625 -0.6875 -1.453125 -0.6875q-0.8125 0 -1.359375 0.546875q-0.546875 0.53125 -0.609375 1.4375zm6.5062256 4.125l0 -6.90625l1.0625 0l0 1.046875q0.40625 -0.734375 0.734375 -0.96875q0.34375 -0.234375 0.765625 -0.234375q0.59375 0 1.203125 0.375l-0.40625 1.078125q-0.4375 -0.25 -0.859375 -0.25q-0.390625 0 -0.703125 0.234375q-0.296875 0.234375 -0.421875 0.640625q-0.203125 0.625 -0.203125 1.359375l0 3.625l-1.171875 0zm7.0164795 -1.046875l0.171875 1.03125q-0.5 0.109375 -0.890625 0.109375q-0.640625 0 -1.0 -0.203125q-0.34375 -0.203125 -0.484375 -0.53125q-0.140625 -0.328125 -0.140625 -1.390625l0 -3.96875l-0.859375 0l0 -0.90625l0.859375 0l0 -1.71875l1.171875 -0.703125l0 2.421875l1.171875 0l0 0.90625l-1.171875 0l0 4.046875q0 0.5 0.046875 0.640625q0.0625 0.140625 0.203125 0.234375q0.140625 0.078125 0.40625 0.078125q0.203125 0 0.515625 -0.046875zm1.1561279 -7.140625l0 -1.359375l1.171875 0l0 1.359375l-1.171875 0zm0 8.1875l0 -6.90625l1.171875 0l0 6.90625l-1.171875 0zm2.5079956 -3.453125q0 -1.921875 1.078125 -2.84375q0.890625 -0.765625 2.171875 -0.765625q1.421875 0 2.328125 0.9375q0.90625 0.921875 0.90625 2.578125q0 1.328125 -0.40625 2.09375q-0.390625 0.765625 -1.15625 1.1875q-0.765625 0.421875 -1.671875 0.421875q-1.453125 0 -2.359375 -0.921875q-0.890625 -0.9375 -0.890625 -2.6875zm1.203125 0q0 1.328125 0.578125 1.984375q0.59375 0.65625 1.46875 0.65625q0.875 0 1.453125 -0.65625q0.578125 -0.671875 0.578125 -2.03125q0 -1.28125 -0.59375 -1.9375q-0.578125 -0.65625 -1.4375 -0.65625q-0.875 0 -1.46875 0.65625q-0.578125 0.65625 -0.578125 1.984375zm6.6468506 3.453125l0 -6.90625l1.0625 0l0 0.984375q0.75 -1.140625 2.1875 -1.140625q0.625 0 1.15625 0.21875q0.53125 0.21875 0.78125 0.59375q0.265625 0.359375 0.375 0.859375q0.0625 0.328125 0.0625 1.140625l0 4.25l-1.171875 0l0 -4.203125q0 -0.71875 -0.140625 -1.0625q-0.140625 -0.359375 -0.484375 -0.5625q-0.34375 -0.21875 -0.8125 -0.21875q-0.75 0 -1.296875 0.46875q-0.546875 0.46875 -0.546875 1.796875l0 3.78125l-1.171875 0zm6.9437256 -2.0625l1.15625 -0.1875q0.109375 0.703125 0.546875 1.078125q0.453125 0.359375 1.25 0.359375q0.8125 0 1.203125 -0.328125q0.390625 -0.328125 0.390625 -0.765625q0 -0.390625 -0.359375 -0.625q-0.234375 -0.15625 -1.1875 -0.390625q-1.296875 -0.328125 -1.796875 -0.5625q-0.484375 -0.25 -0.75 -0.65625q-0.25 -0.421875 -0.25 -0.9375q0 -0.453125 0.203125 -0.84375q0.21875 -0.40625 0.578125 -0.671875q0.28125 -0.1875 0.75 -0.328125q0.46875 -0.140625 1.015625 -0.140625q0.8125 0 1.421875 0.234375q0.609375 0.234375 0.90625 0.640625q0.296875 0.390625 0.40625 1.0625l-1.140625 0.15625q-0.078125 -0.53125 -0.453125 -0.828125q-0.375 -0.3125 -1.0625 -0.3125q-0.8125 0 -1.15625 0.265625q-0.34375 0.265625 -0.34375 0.625q0 0.234375 0.140625 0.421875q0.15625 0.1875 0.453125 0.3125q0.171875 0.0625 1.03125 0.296875q1.25 0.328125 1.734375 0.546875q0.5 0.203125 0.78125 0.609375q0.28125 0.40625 0.28125 1.0q0 0.59375 -0.34375 1.109375q-0.34375 0.515625 -1.0 0.796875q-0.640625 0.28125 -1.453125 0.28125q-1.34375 0 -2.046875 -0.5625q-0.703125 -0.5625 -0.90625 -1.65625z" fill-rule="nonzero"/></g></svg>
\ No newline at end of file
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_expected_failure.hjson b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_expected_failure.hjson
new file mode 100644
index 0000000..0a6a12b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_expected_failure.hjson
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+ unreachable:
+ [
+ rv_plic_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1
+ rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1
+ rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1
+ ]
+}
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_smc_fpv.core b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_smc_fpv.core
new file mode 100644
index 0000000..b61ebac
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/rv_plic_smc_fpv.core
@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_rv_plic_smc_fpv:0.1
+description: "FPV for RISC-V PLIC"
+
+filesets:
+ files_formal:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:prim:all
+ - lowrisc:opentitan:top_sencha_rv_plic_smc
+ - lowrisc:fpv:csr_assert_gen
+ files:
+ - tb/rv_plic_smc_bind_fpv.sv
+ - tb/rv_plic_smc_tb.sv
+ - vip/rv_plic_smc_assert_fpv.sv
+ file_type: systemVerilogSource
+
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../data/rv_plic_smc.hjson
+ depend: lowrisc:opentitan:top_sencha_rv_plic_smc
+
+targets:
+ default: &default_target
+ # note, this setting is just used
+ # to generate a file list for jg
+ default_tool: icarus
+ filesets:
+ - files_formal
+ generate:
+ - csr_assert_gen
+ toplevel: rv_plic_smc_tb
+
+ formal:
+ <<: *default_target
+
+ lint:
+ <<: *default_target
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_bind_fpv.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_bind_fpv.sv
new file mode 100644
index 0000000..2343aa0
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_bind_fpv.sv
@@ -0,0 +1,47 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module rv_plic_smc_bind_fpv;
+
+ import rv_plic_smc_reg_pkg::*;
+
+ bind rv_plic_smc rv_plic_smc_assert_fpv #(
+ .NumSrc(rv_plic_smc_reg_pkg::NumSrc),
+ .NumTarget(rv_plic_smc_reg_pkg::NumTarget),
+ .NumAlerts(rv_plic_smc_reg_pkg::NumAlerts),
+ .PRIOW(rv_plic_smc_reg_pkg::PrioWidth)
+ ) rv_plic_smc_assert_fpv(
+ .clk_i,
+ .rst_ni,
+ .intr_src_i,
+ .alert_rx_i,
+ .alert_tx_o,
+ .irq_o,
+ .irq_id_o,
+ .msip_o,
+ .ip,
+ .ie,
+ .claim,
+ .complete,
+ .prio,
+ .threshold
+ );
+
+ bind rv_plic_smc tlul_assert #(
+ .EndpointType("Device")
+ ) tlul_assert_device (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+ bind rv_plic_smc rv_plic_smc_csr_assert_fpv rv_plic_smc_csr_assert_fpv (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+endmodule : rv_plic_smc_bind_fpv
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_tb.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_tb.sv
new file mode 100644
index 0000000..b4ec978
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/tb/rv_plic_smc_tb.sv
@@ -0,0 +1,40 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Testbench module for rv_plic_smc. Intended to use with a formal tool.
+
+module rv_plic_smc_tb import rv_plic_smc_reg_pkg::*; #(
+ // test all implementations
+ localparam int unsigned NumInstances = 1
+) (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
+ output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
+ input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
+ input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
+ output [NumInstances-1:0][NumTarget-1:0] irq_o,
+ output [$clog2(NumSrc)-1:0] irq_id_o [NumInstances][NumTarget],
+ output logic [NumInstances-1:0][NumTarget-1:0] msip_o
+);
+
+ // TODO: once the PLIC is fully parameterizable in RTL, generate
+ // several instances with different NumSrc and NumTarget configs here
+ // (in a similar way as this has been done in prim_lfsr_fpv)
+ // for (genvar k = 0; k < NumInstances; k++) begin : geNumInstances
+ rv_plic_smc dut (
+ .clk_i ,
+ .rst_ni ,
+ .tl_i (tl_i[0]),
+ .tl_o (tl_o[0]),
+ .intr_src_i (intr_src_i[0]),
+ .alert_rx_i (alert_rx_i[0]),
+ .alert_tx_o (alert_tx_o[0]),
+ .irq_o (irq_o[0]),
+ .irq_id_o (irq_id_o[0]),
+ .msip_o (msip_o[0])
+ );
+
+endmodule : rv_plic_smc_tb
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/vip/rv_plic_smc_assert_fpv.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/vip/rv_plic_smc_assert_fpv.sv
new file mode 100644
index 0000000..f772f1c
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/fpv/vip/rv_plic_smc_assert_fpv.sv
@@ -0,0 +1,104 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+// Testbench module for rv_plic_smc. Intended to use with a formal tool.
+
+`include "prim_assert.sv"
+
+module rv_plic_smc_assert_fpv #(parameter int NumSrc = 1,
+ parameter int NumTarget = 1,
+ parameter int NumAlerts = 1,
+ parameter int PRIOW = $clog2(7+1)
+) (
+ input clk_i,
+ input rst_ni,
+ input [NumSrc-1:0] intr_src_i,
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ input prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+ input [NumTarget-1:0] irq_o,
+ input [$clog2(NumSrc)-1:0] irq_id_o [NumTarget],
+ input [NumTarget-1:0] msip_o,
+ // probe design signals
+ input [NumSrc-1:0] ip,
+ input [NumSrc-1:0] ie [NumTarget],
+ input [NumSrc-1:0] claim,
+ input [NumSrc-1:0] complete,
+ input [NumSrc-1:0][PRIOW-1:0] prio,
+ input [PRIOW-1:0] threshold [NumTarget]
+);
+
+ logic claim_reg, claimed;
+ logic max_priority;
+ logic irq;
+ logic [$clog2(NumSrc)-1:0] i_high_prio;
+
+ // symbolic variables
+ int unsigned src_sel;
+ int unsigned tgt_sel;
+
+ `ASSUME_FPV(IsrcRange_M, src_sel > 0 && src_sel < NumSrc, clk_i, !rst_ni)
+ `ASSUME_FPV(ItgtRange_M, tgt_sel >= 0 && tgt_sel < NumTarget, clk_i, !rst_ni)
+ `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni)
+ `ASSUME_FPV(ItgtStable_M, ##1 $stable(tgt_sel), clk_i, !rst_ni)
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ claim_reg <= 1'b0;
+ end else if (claim[src_sel]) begin
+ claim_reg <= 1'b1;
+ end else if (complete[src_sel]) begin
+ claim_reg <= 1'b0;
+ end
+ end
+
+ assign claimed = claim_reg || claim[src_sel];
+
+ always_comb begin
+ max_priority = 1'b1;
+ for (int i = 0; i < NumSrc; i++) begin
+ // conditions that if src_sel has the highest priority with the lowest ID
+ if (i != src_sel && ip[i] && ie[tgt_sel][i] &&
+ (prio[i] > prio[src_sel] || (prio[i] == prio[src_sel] && i < src_sel))) begin
+ max_priority = 1'b0;
+ break;
+ end
+ end
+ end
+
+ always_comb begin
+ automatic logic [31:0] max_prio = 0;
+ for (int i = NumSrc-1; i >= 0; i--) begin
+ if (ip[i] && ie[tgt_sel][i] && prio[i] >= max_prio) begin
+ max_prio = prio[i];
+ i_high_prio = i; // i is the smallest id if have IPs with the same priority
+ end
+ end
+ if (max_prio > threshold[tgt_sel]) irq = 1'b1;
+ else irq = 1'b0;
+ end
+
+ // when IP is set, previous cycle should follow edge or level triggered criteria
+ `ASSERT(LevelTriggeredIp_A, ##3 $rose(ip[src_sel]) |-> $past(intr_src_i[src_sel], 3))
+
+ // when interrupt is trigger, and nothing claimed yet, then next cycle should assert IP.
+ `ASSERT(LevelTriggeredIpWithClaim_A, ##2 $past(intr_src_i[src_sel], 2) &&
+ !claimed |=> ip[src_sel])
+
+ // ip stays stable until claimed, reset to 0 after claimed, and stays 0 until complete
+ `ASSERT(IpStableAfterTriggered_A, ip[src_sel] && !claimed |=> ip[src_sel])
+ `ASSERT(IpClearAfterClaim_A, ip[src_sel] && claim[src_sel] |=> !ip[src_sel])
+ `ASSERT(IpStableAfterClaimed_A, claimed |=> !ip[src_sel])
+
+ // when ip is set and priority is the largest and above threshold, and interrupt enable is set,
+ // assertion irq_o at next cycle
+ `ASSERT(TriggerIrqForwardCheck_A, ip[src_sel] && prio[src_sel] > threshold[tgt_sel] &&
+ max_priority && ie[tgt_sel][src_sel] |=> irq_o[tgt_sel])
+
+ `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[tgt_sel]) |->
+ $past(irq) && (irq_id_o[tgt_sel] == $past(i_high_prio)))
+
+ // when irq ID changed, but not to ID=0, irq_o should be high, or irq represents the largest prio
+ // but smaller than the threshold
+ `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[tgt_sel]) && irq_id_o[tgt_sel] != 0 |->
+ irq_o[tgt_sel] || ((irq_id_o[tgt_sel]) == $past(i_high_prio) && !$past(irq)))
+endmodule : rv_plic_smc_assert_fpv
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.vlt b/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.vlt
new file mode 100644
index 0000000..bc29707
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.vlt
@@ -0,0 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// waiver file for rv_plic_smc
+
+`verilator_config
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.waiver b/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.waiver
new file mode 100644
index 0000000..4b9232b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/lint/rv_plic_smc.waiver
@@ -0,0 +1,22 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for Platform-Level Interrupt Controller
+
+waive -rules ONE_BIT_MEM_WIDTH -location {rv_plic_smc.sv} -regexp {Memory '(claim_re|complete_we)' has} \
+ -comment "N_TARGET can be 1."
+
+waive -rules VAR_INDEX_RANGE -location {rv_plic_smc.sv} -regexp {(claim_id|complete_id).* (maximum|minimum) value} \
+ -comment "Claim ID is guarded inside target module, complete ID has undeterministic behavior if FW writes OOR value"
+
+waive -rules HIER_NET_NOT_READ -location {rv_plic_smc.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \
+ -comment "Register interface doesn't use upper address and param, user filed"
+
+waive -rules EXPLICIT_BITLEN -location {rv_plic_smc_target.sv} -regexp {Bit length .* '1'} \
+ -comment "i + 1 is assumed as constant and guarded by SRCW"
+waive -rules INTEGER -location {rv_plic_smc_target.sv} -regexp {'i' of type int used as} \
+ -comment "int i is static and only assigned to irq_id_next when it hits condition"
+
+waive -rules TWOS_COMP -location {rv_plic_smc_target.sv} -regexp {Explicit two's complement with terms} \
+ -comment "This is permissible in this context"
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv
new file mode 100644
index 0000000..f668469
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc.sv
@@ -0,0 +1,292 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Controller compliant INTC
+//
+// Current version doesn't support MSI interrupt but it is easy to add
+// the feature. Create one external register and connect qe signal to the
+// gateway module (as edge-triggered)
+//
+// Consider to set MAX_PRIO as small number as possible. It is main factor
+// of area increase if edge-triggered counter isn't implemented.
+//
+// Verilog parameter
+// MAX_PRIO: Maximum value of interrupt priority
+
+module rv_plic_smc import rv_plic_smc_reg_pkg::*; #(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+ // OpenTitan IP standardizes on level triggered interrupts,
+ // hence LevelEdgeTrig is set to all-zeroes by default.
+ // Note that in case of edge-triggered interrupts, CDC handling is not
+ // fully implemented yet (this would require instantiating pulse syncs
+ // and routing the source clocks / resets to the PLIC).
+ parameter logic [NumSrc-1:0] LevelEdgeTrig = '0, // 0: level, 1: edge
+ // derived parameter
+ localparam int SRCW = $clog2(NumSrc)
+) (
+ input clk_i,
+ input rst_ni,
+
+ // Bus Interface (device)
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+
+ // Interrupt Sources
+ input [NumSrc-1:0] intr_src_i,
+
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
+ // Interrupt notification to targets
+ output [NumTarget-1:0] irq_o,
+ output [SRCW-1:0] irq_id_o [NumTarget],
+
+ output logic [NumTarget-1:0] msip_o
+);
+
+ rv_plic_smc_reg2hw_t reg2hw;
+ rv_plic_smc_hw2reg_t hw2reg;
+
+ localparam int MAX_PRIO = 3;
+ localparam int PRIOW = $clog2(MAX_PRIO+1);
+
+ logic [NumSrc-1:0] ip;
+
+ logic [NumSrc-1:0] ie [NumTarget];
+
+ logic [NumTarget-1:0] claim_re; // Target read indicator
+ logic [SRCW-1:0] claim_id [NumTarget];
+ logic [NumSrc-1:0] claim; // Converted from claim_re/claim_id
+
+ logic [NumTarget-1:0] complete_we; // Target write indicator
+ logic [SRCW-1:0] complete_id [NumTarget];
+ logic [NumSrc-1:0] complete; // Converted from complete_re/complete_id
+
+ logic [SRCW-1:0] cc_id [NumTarget]; // Write ID
+
+ logic [NumSrc-1:0][PRIOW-1:0] prio;
+
+ logic [PRIOW-1:0] threshold [NumTarget];
+
+ // Glue logic between rv_plic_smc_reg_top and others
+ assign cc_id = irq_id_o;
+
+ always_comb begin
+ claim = '0;
+ for (int i = 0 ; i < NumTarget ; i++) begin
+ if (claim_re[i]) claim[claim_id[i]] = 1'b1;
+ end
+ end
+ always_comb begin
+ complete = '0;
+ for (int i = 0 ; i < NumTarget ; i++) begin
+ if (complete_we[i]) complete[complete_id[i]] = 1'b1;
+ end
+ end
+
+ //`ASSERT_PULSE(claimPulse, claim_re[i])
+ //`ASSERT_PULSE(completePulse, complete_we[i])
+
+ `ASSERT(onehot0Claim, $onehot0(claim_re))
+
+ `ASSERT(onehot0Complete, $onehot0(complete_we))
+
+ //////////////
+ // Priority //
+ //////////////
+ assign prio[0] = reg2hw.prio0.q;
+ assign prio[1] = reg2hw.prio1.q;
+ assign prio[2] = reg2hw.prio2.q;
+ assign prio[3] = reg2hw.prio3.q;
+ assign prio[4] = reg2hw.prio4.q;
+ assign prio[5] = reg2hw.prio5.q;
+ assign prio[6] = reg2hw.prio6.q;
+ assign prio[7] = reg2hw.prio7.q;
+ assign prio[8] = reg2hw.prio8.q;
+ assign prio[9] = reg2hw.prio9.q;
+ assign prio[10] = reg2hw.prio10.q;
+ assign prio[11] = reg2hw.prio11.q;
+ assign prio[12] = reg2hw.prio12.q;
+ assign prio[13] = reg2hw.prio13.q;
+ assign prio[14] = reg2hw.prio14.q;
+ assign prio[15] = reg2hw.prio15.q;
+ assign prio[16] = reg2hw.prio16.q;
+ assign prio[17] = reg2hw.prio17.q;
+ assign prio[18] = reg2hw.prio18.q;
+ assign prio[19] = reg2hw.prio19.q;
+ assign prio[20] = reg2hw.prio20.q;
+ assign prio[21] = reg2hw.prio21.q;
+ assign prio[22] = reg2hw.prio22.q;
+ assign prio[23] = reg2hw.prio23.q;
+ assign prio[24] = reg2hw.prio24.q;
+ assign prio[25] = reg2hw.prio25.q;
+ assign prio[26] = reg2hw.prio26.q;
+ assign prio[27] = reg2hw.prio27.q;
+ assign prio[28] = reg2hw.prio28.q;
+ assign prio[29] = reg2hw.prio29.q;
+ assign prio[30] = reg2hw.prio30.q;
+ assign prio[31] = reg2hw.prio31.q;
+ assign prio[32] = reg2hw.prio32.q;
+ assign prio[33] = reg2hw.prio33.q;
+ assign prio[34] = reg2hw.prio34.q;
+ assign prio[35] = reg2hw.prio35.q;
+ assign prio[36] = reg2hw.prio36.q;
+ assign prio[37] = reg2hw.prio37.q;
+ assign prio[38] = reg2hw.prio38.q;
+ assign prio[39] = reg2hw.prio39.q;
+ assign prio[40] = reg2hw.prio40.q;
+ assign prio[41] = reg2hw.prio41.q;
+ assign prio[42] = reg2hw.prio42.q;
+
+ //////////////////////
+ // Interrupt Enable //
+ //////////////////////
+ for (genvar s = 0; s < 43; s++) begin : gen_ie0
+ assign ie[0][s] = reg2hw.ie0[s].q;
+ end
+
+ ////////////////////////
+ // THRESHOLD register //
+ ////////////////////////
+ assign threshold[0] = reg2hw.threshold0.q;
+
+ /////////////////
+ // CC register //
+ /////////////////
+ assign claim_re[0] = reg2hw.cc0.re;
+ assign claim_id[0] = irq_id_o[0];
+ assign complete_we[0] = reg2hw.cc0.qe;
+ assign complete_id[0] = reg2hw.cc0.q;
+ assign hw2reg.cc0.d = cc_id[0];
+
+ ///////////////////
+ // MSIP register //
+ ///////////////////
+ assign msip_o[0] = reg2hw.msip0.q;
+
+ ////////
+ // IP //
+ ////////
+ for (genvar s = 0; s < 43; s++) begin : gen_ip
+ assign hw2reg.ip[s].de = 1'b1; // Always write
+ assign hw2reg.ip[s].d = ip[s];
+ end
+
+ //////////////
+ // Gateways //
+ //////////////
+
+ // Synchronize all incoming interrupt requests.
+ logic [NumSrc-1:0] intr_src_synced;
+ prim_flop_2sync #(
+ .Width(NumSrc)
+ ) u_prim_flop_2sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(intr_src_i),
+ .q_o(intr_src_synced)
+ );
+
+ rv_plic_smc_gateway #(
+ .N_SOURCE (NumSrc)
+ ) u_gateway (
+ .clk_i,
+ .rst_ni,
+
+ .src_i (intr_src_synced),
+ .le_i (LevelEdgeTrig),
+
+ .claim_i (claim),
+ .complete_i (complete),
+
+ .ip_o (ip)
+ );
+
+ ///////////////////////////////////
+ // Target interrupt notification //
+ ///////////////////////////////////
+ for (genvar i = 0 ; i < NumTarget ; i++) begin : gen_target
+ rv_plic_smc_target #(
+ .N_SOURCE (NumSrc),
+ .MAX_PRIO (MAX_PRIO)
+ ) u_target (
+ .clk_i,
+ .rst_ni,
+
+ .ip_i (ip),
+ .ie_i (ie[i]),
+
+ .prio_i (prio),
+ .threshold_i (threshold[i]),
+
+ .irq_o (irq_o[i]),
+ .irq_id_o (irq_id_o[i])
+
+ );
+ end
+
+ ////////////
+ // Alerts //
+ ////////////
+
+ logic [NumAlerts-1:0] alert_test, alerts;
+
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
+ ////////////////////////
+ // Register interface //
+ ////////////////////////
+ // Limitation of register tool prevents the module from having flexibility to parameters
+ // So, signals are manually tied at the top.
+ rv_plic_smc_reg_top u_reg (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i,
+ .tl_o,
+
+ .reg2hw,
+ .hw2reg,
+
+ // SEC_CM: BUS.INTEGRITY
+ .intg_err_o(alerts[0]),
+
+ .devmode_i (1'b1)
+ );
+
+ // Assertions
+ `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
+ `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(IrqKnownO_A, irq_o)
+ `ASSERT_KNOWN(MsipKnownO_A, msip_o)
+ for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known
+ `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
+ end
+
+ // Assume
+ `ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
+
+ // Alert assertions for reg_we onehot check
+ `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_gateway.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_gateway.sv
new file mode 100644
index 0000000..3f74829
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_gateway.sv
@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Gateways module
+
+module rv_plic_smc_gateway #(
+ parameter int N_SOURCE = 32
+) (
+ input clk_i,
+ input rst_ni,
+
+ input [N_SOURCE-1:0] src_i,
+ input [N_SOURCE-1:0] le_i, // Level0 Edge1
+
+ input [N_SOURCE-1:0] claim_i, // $onehot0(claim_i)
+ input [N_SOURCE-1:0] complete_i, // $onehot0(complete_i)
+
+ output logic [N_SOURCE-1:0] ip_o
+);
+
+ logic [N_SOURCE-1:0] ia; // Interrupt Active
+
+ logic [N_SOURCE-1:0] set; // Set: (le_i) ? src_i & ~src_q : src_i ;
+ logic [N_SOURCE-1:0] src_q;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) src_q <= '0;
+ else src_q <= src_i;
+ end
+
+ always_comb begin
+ for (int i = 0 ; i < N_SOURCE; i++) begin
+ set[i] = (le_i[i]) ? src_i[i] & ~src_q[i] : src_i[i] ;
+ end
+ end
+
+ // Interrupt pending is set by source (depends on le_i), cleared by claim_i.
+ // Until interrupt is claimed, set doesn't affect ip_o.
+ // RISC-V PLIC spec mentioned it can have counter for edge triggered
+ // But skipped the feature as counter consumes substantial logic size.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ip_o <= '0;
+ end else begin
+ ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i));
+ end
+ end
+
+ // Interrupt active is to control ip_o. If ip_o is set then until completed
+ // by target, ip_o shouldn't be set by source even claim_i can clear ip_o.
+ // ia can be cleared only when ia was set. If `set` and `complete_i` happen
+ // at the same time, always `set` wins.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ ia <= '0;
+ end else begin
+ ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o));
+ end
+ end
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv
new file mode 100644
index 0000000..0a3227b
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_pkg.sv
@@ -0,0 +1,451 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package rv_plic_smc_reg_pkg;
+
+ // Param list
+ parameter int NumSrc = 43;
+ parameter int NumTarget = 1;
+ parameter int PrioWidth = 2;
+ parameter int NumAlerts = 1;
+
+ // Address widths within the block
+ parameter int BlockAw = 27;
+
+ ////////////////////////////
+ // Typedefs for registers //
+ ////////////////////////////
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio0_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio1_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio2_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio3_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio4_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio5_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio6_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio7_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio8_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio9_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio10_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio11_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio12_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio13_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio14_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio15_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio16_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio17_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio18_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio19_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio20_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio21_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio22_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio23_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio24_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio25_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio26_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio27_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio28_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio29_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio30_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio31_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio32_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio33_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio34_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio35_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio36_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio37_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio38_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio39_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio40_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio41_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_prio42_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_smc_reg2hw_ie0_mreg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_smc_reg2hw_threshold0_reg_t;
+
+ typedef struct packed {
+ logic [5:0] q;
+ logic qe;
+ logic re;
+ } rv_plic_smc_reg2hw_cc0_reg_t;
+
+ typedef struct packed {
+ logic q;
+ } rv_plic_smc_reg2hw_msip0_reg_t;
+
+ typedef struct packed {
+ logic q;
+ logic qe;
+ } rv_plic_smc_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } rv_plic_smc_hw2reg_ip_mreg_t;
+
+ typedef struct packed {
+ logic [5:0] d;
+ } rv_plic_smc_hw2reg_cc0_reg_t;
+
+ // Register -> HW type
+ typedef struct packed {
+ rv_plic_smc_reg2hw_prio0_reg_t prio0; // [141:140]
+ rv_plic_smc_reg2hw_prio1_reg_t prio1; // [139:138]
+ rv_plic_smc_reg2hw_prio2_reg_t prio2; // [137:136]
+ rv_plic_smc_reg2hw_prio3_reg_t prio3; // [135:134]
+ rv_plic_smc_reg2hw_prio4_reg_t prio4; // [133:132]
+ rv_plic_smc_reg2hw_prio5_reg_t prio5; // [131:130]
+ rv_plic_smc_reg2hw_prio6_reg_t prio6; // [129:128]
+ rv_plic_smc_reg2hw_prio7_reg_t prio7; // [127:126]
+ rv_plic_smc_reg2hw_prio8_reg_t prio8; // [125:124]
+ rv_plic_smc_reg2hw_prio9_reg_t prio9; // [123:122]
+ rv_plic_smc_reg2hw_prio10_reg_t prio10; // [121:120]
+ rv_plic_smc_reg2hw_prio11_reg_t prio11; // [119:118]
+ rv_plic_smc_reg2hw_prio12_reg_t prio12; // [117:116]
+ rv_plic_smc_reg2hw_prio13_reg_t prio13; // [115:114]
+ rv_plic_smc_reg2hw_prio14_reg_t prio14; // [113:112]
+ rv_plic_smc_reg2hw_prio15_reg_t prio15; // [111:110]
+ rv_plic_smc_reg2hw_prio16_reg_t prio16; // [109:108]
+ rv_plic_smc_reg2hw_prio17_reg_t prio17; // [107:106]
+ rv_plic_smc_reg2hw_prio18_reg_t prio18; // [105:104]
+ rv_plic_smc_reg2hw_prio19_reg_t prio19; // [103:102]
+ rv_plic_smc_reg2hw_prio20_reg_t prio20; // [101:100]
+ rv_plic_smc_reg2hw_prio21_reg_t prio21; // [99:98]
+ rv_plic_smc_reg2hw_prio22_reg_t prio22; // [97:96]
+ rv_plic_smc_reg2hw_prio23_reg_t prio23; // [95:94]
+ rv_plic_smc_reg2hw_prio24_reg_t prio24; // [93:92]
+ rv_plic_smc_reg2hw_prio25_reg_t prio25; // [91:90]
+ rv_plic_smc_reg2hw_prio26_reg_t prio26; // [89:88]
+ rv_plic_smc_reg2hw_prio27_reg_t prio27; // [87:86]
+ rv_plic_smc_reg2hw_prio28_reg_t prio28; // [85:84]
+ rv_plic_smc_reg2hw_prio29_reg_t prio29; // [83:82]
+ rv_plic_smc_reg2hw_prio30_reg_t prio30; // [81:80]
+ rv_plic_smc_reg2hw_prio31_reg_t prio31; // [79:78]
+ rv_plic_smc_reg2hw_prio32_reg_t prio32; // [77:76]
+ rv_plic_smc_reg2hw_prio33_reg_t prio33; // [75:74]
+ rv_plic_smc_reg2hw_prio34_reg_t prio34; // [73:72]
+ rv_plic_smc_reg2hw_prio35_reg_t prio35; // [71:70]
+ rv_plic_smc_reg2hw_prio36_reg_t prio36; // [69:68]
+ rv_plic_smc_reg2hw_prio37_reg_t prio37; // [67:66]
+ rv_plic_smc_reg2hw_prio38_reg_t prio38; // [65:64]
+ rv_plic_smc_reg2hw_prio39_reg_t prio39; // [63:62]
+ rv_plic_smc_reg2hw_prio40_reg_t prio40; // [61:60]
+ rv_plic_smc_reg2hw_prio41_reg_t prio41; // [59:58]
+ rv_plic_smc_reg2hw_prio42_reg_t prio42; // [57:56]
+ rv_plic_smc_reg2hw_ie0_mreg_t [42:0] ie0; // [55:13]
+ rv_plic_smc_reg2hw_threshold0_reg_t threshold0; // [12:11]
+ rv_plic_smc_reg2hw_cc0_reg_t cc0; // [10:3]
+ rv_plic_smc_reg2hw_msip0_reg_t msip0; // [2:2]
+ rv_plic_smc_reg2hw_alert_test_reg_t alert_test; // [1:0]
+ } rv_plic_smc_reg2hw_t;
+
+ // HW -> register type
+ typedef struct packed {
+ rv_plic_smc_hw2reg_ip_mreg_t [42:0] ip; // [91:6]
+ rv_plic_smc_hw2reg_cc0_reg_t cc0; // [5:0]
+ } rv_plic_smc_hw2reg_t;
+
+ // Register offsets
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO0_OFFSET = 27'h 0;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO1_OFFSET = 27'h 4;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO2_OFFSET = 27'h 8;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO3_OFFSET = 27'h c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO4_OFFSET = 27'h 10;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO5_OFFSET = 27'h 14;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO6_OFFSET = 27'h 18;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO7_OFFSET = 27'h 1c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO8_OFFSET = 27'h 20;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO9_OFFSET = 27'h 24;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO10_OFFSET = 27'h 28;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO11_OFFSET = 27'h 2c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO12_OFFSET = 27'h 30;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO13_OFFSET = 27'h 34;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO14_OFFSET = 27'h 38;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO15_OFFSET = 27'h 3c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO16_OFFSET = 27'h 40;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO17_OFFSET = 27'h 44;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO18_OFFSET = 27'h 48;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO19_OFFSET = 27'h 4c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO20_OFFSET = 27'h 50;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO21_OFFSET = 27'h 54;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO22_OFFSET = 27'h 58;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO23_OFFSET = 27'h 5c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO24_OFFSET = 27'h 60;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO25_OFFSET = 27'h 64;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO26_OFFSET = 27'h 68;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO27_OFFSET = 27'h 6c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO28_OFFSET = 27'h 70;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO29_OFFSET = 27'h 74;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO30_OFFSET = 27'h 78;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO31_OFFSET = 27'h 7c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO32_OFFSET = 27'h 80;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO33_OFFSET = 27'h 84;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO34_OFFSET = 27'h 88;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO35_OFFSET = 27'h 8c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO36_OFFSET = 27'h 90;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO37_OFFSET = 27'h 94;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO38_OFFSET = 27'h 98;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO39_OFFSET = 27'h 9c;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO40_OFFSET = 27'h a0;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO41_OFFSET = 27'h a4;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_PRIO42_OFFSET = 27'h a8;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_0_OFFSET = 27'h 1000;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_IP_1_OFFSET = 27'h 1004;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_IE0_0_OFFSET = 27'h 2000;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_IE0_1_OFFSET = 27'h 2004;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_THRESHOLD0_OFFSET = 27'h 200000;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_CC0_OFFSET = 27'h 200004;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_MSIP0_OFFSET = 27'h 4000000;
+ parameter logic [BlockAw-1:0] RV_PLIC_SMC_ALERT_TEST_OFFSET = 27'h 4004000;
+
+ // Reset values for hwext registers and their fields
+ parameter logic [5:0] RV_PLIC_SMC_CC0_RESVAL = 6'h 0;
+ parameter logic [0:0] RV_PLIC_SMC_ALERT_TEST_RESVAL = 1'h 0;
+
+ // Register index
+ typedef enum int {
+ RV_PLIC_SMC_PRIO0,
+ RV_PLIC_SMC_PRIO1,
+ RV_PLIC_SMC_PRIO2,
+ RV_PLIC_SMC_PRIO3,
+ RV_PLIC_SMC_PRIO4,
+ RV_PLIC_SMC_PRIO5,
+ RV_PLIC_SMC_PRIO6,
+ RV_PLIC_SMC_PRIO7,
+ RV_PLIC_SMC_PRIO8,
+ RV_PLIC_SMC_PRIO9,
+ RV_PLIC_SMC_PRIO10,
+ RV_PLIC_SMC_PRIO11,
+ RV_PLIC_SMC_PRIO12,
+ RV_PLIC_SMC_PRIO13,
+ RV_PLIC_SMC_PRIO14,
+ RV_PLIC_SMC_PRIO15,
+ RV_PLIC_SMC_PRIO16,
+ RV_PLIC_SMC_PRIO17,
+ RV_PLIC_SMC_PRIO18,
+ RV_PLIC_SMC_PRIO19,
+ RV_PLIC_SMC_PRIO20,
+ RV_PLIC_SMC_PRIO21,
+ RV_PLIC_SMC_PRIO22,
+ RV_PLIC_SMC_PRIO23,
+ RV_PLIC_SMC_PRIO24,
+ RV_PLIC_SMC_PRIO25,
+ RV_PLIC_SMC_PRIO26,
+ RV_PLIC_SMC_PRIO27,
+ RV_PLIC_SMC_PRIO28,
+ RV_PLIC_SMC_PRIO29,
+ RV_PLIC_SMC_PRIO30,
+ RV_PLIC_SMC_PRIO31,
+ RV_PLIC_SMC_PRIO32,
+ RV_PLIC_SMC_PRIO33,
+ RV_PLIC_SMC_PRIO34,
+ RV_PLIC_SMC_PRIO35,
+ RV_PLIC_SMC_PRIO36,
+ RV_PLIC_SMC_PRIO37,
+ RV_PLIC_SMC_PRIO38,
+ RV_PLIC_SMC_PRIO39,
+ RV_PLIC_SMC_PRIO40,
+ RV_PLIC_SMC_PRIO41,
+ RV_PLIC_SMC_PRIO42,
+ RV_PLIC_SMC_IP_0,
+ RV_PLIC_SMC_IP_1,
+ RV_PLIC_SMC_IE0_0,
+ RV_PLIC_SMC_IE0_1,
+ RV_PLIC_SMC_THRESHOLD0,
+ RV_PLIC_SMC_CC0,
+ RV_PLIC_SMC_MSIP0,
+ RV_PLIC_SMC_ALERT_TEST
+ } rv_plic_smc_id_e;
+
+ // Register width information to check illegal writes
+ parameter logic [3:0] RV_PLIC_SMC_PERMIT [51] = '{
+ 4'b 0001, // index[ 0] RV_PLIC_SMC_PRIO0
+ 4'b 0001, // index[ 1] RV_PLIC_SMC_PRIO1
+ 4'b 0001, // index[ 2] RV_PLIC_SMC_PRIO2
+ 4'b 0001, // index[ 3] RV_PLIC_SMC_PRIO3
+ 4'b 0001, // index[ 4] RV_PLIC_SMC_PRIO4
+ 4'b 0001, // index[ 5] RV_PLIC_SMC_PRIO5
+ 4'b 0001, // index[ 6] RV_PLIC_SMC_PRIO6
+ 4'b 0001, // index[ 7] RV_PLIC_SMC_PRIO7
+ 4'b 0001, // index[ 8] RV_PLIC_SMC_PRIO8
+ 4'b 0001, // index[ 9] RV_PLIC_SMC_PRIO9
+ 4'b 0001, // index[10] RV_PLIC_SMC_PRIO10
+ 4'b 0001, // index[11] RV_PLIC_SMC_PRIO11
+ 4'b 0001, // index[12] RV_PLIC_SMC_PRIO12
+ 4'b 0001, // index[13] RV_PLIC_SMC_PRIO13
+ 4'b 0001, // index[14] RV_PLIC_SMC_PRIO14
+ 4'b 0001, // index[15] RV_PLIC_SMC_PRIO15
+ 4'b 0001, // index[16] RV_PLIC_SMC_PRIO16
+ 4'b 0001, // index[17] RV_PLIC_SMC_PRIO17
+ 4'b 0001, // index[18] RV_PLIC_SMC_PRIO18
+ 4'b 0001, // index[19] RV_PLIC_SMC_PRIO19
+ 4'b 0001, // index[20] RV_PLIC_SMC_PRIO20
+ 4'b 0001, // index[21] RV_PLIC_SMC_PRIO21
+ 4'b 0001, // index[22] RV_PLIC_SMC_PRIO22
+ 4'b 0001, // index[23] RV_PLIC_SMC_PRIO23
+ 4'b 0001, // index[24] RV_PLIC_SMC_PRIO24
+ 4'b 0001, // index[25] RV_PLIC_SMC_PRIO25
+ 4'b 0001, // index[26] RV_PLIC_SMC_PRIO26
+ 4'b 0001, // index[27] RV_PLIC_SMC_PRIO27
+ 4'b 0001, // index[28] RV_PLIC_SMC_PRIO28
+ 4'b 0001, // index[29] RV_PLIC_SMC_PRIO29
+ 4'b 0001, // index[30] RV_PLIC_SMC_PRIO30
+ 4'b 0001, // index[31] RV_PLIC_SMC_PRIO31
+ 4'b 0001, // index[32] RV_PLIC_SMC_PRIO32
+ 4'b 0001, // index[33] RV_PLIC_SMC_PRIO33
+ 4'b 0001, // index[34] RV_PLIC_SMC_PRIO34
+ 4'b 0001, // index[35] RV_PLIC_SMC_PRIO35
+ 4'b 0001, // index[36] RV_PLIC_SMC_PRIO36
+ 4'b 0001, // index[37] RV_PLIC_SMC_PRIO37
+ 4'b 0001, // index[38] RV_PLIC_SMC_PRIO38
+ 4'b 0001, // index[39] RV_PLIC_SMC_PRIO39
+ 4'b 0001, // index[40] RV_PLIC_SMC_PRIO40
+ 4'b 0001, // index[41] RV_PLIC_SMC_PRIO41
+ 4'b 0001, // index[42] RV_PLIC_SMC_PRIO42
+ 4'b 1111, // index[43] RV_PLIC_SMC_IP_0
+ 4'b 0011, // index[44] RV_PLIC_SMC_IP_1
+ 4'b 1111, // index[45] RV_PLIC_SMC_IE0_0
+ 4'b 0011, // index[46] RV_PLIC_SMC_IE0_1
+ 4'b 0001, // index[47] RV_PLIC_SMC_THRESHOLD0
+ 4'b 0001, // index[48] RV_PLIC_SMC_CC0
+ 4'b 0001, // index[49] RV_PLIC_SMC_MSIP0
+ 4'b 0001 // index[50] RV_PLIC_SMC_ALERT_TEST
+ };
+
+endpackage
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv
new file mode 100644
index 0000000..711efb7
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_reg_top.sv
@@ -0,0 +1,4631 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module rv_plic_smc_reg_top (
+ input clk_i,
+ input rst_ni,
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output rv_plic_smc_reg_pkg::rv_plic_smc_reg2hw_t reg2hw, // Write
+ input rv_plic_smc_reg_pkg::rv_plic_smc_hw2reg_t hw2reg, // Read
+
+ // Integrity check errors
+ output logic intg_err_o,
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import rv_plic_smc_reg_pkg::* ;
+
+ localparam int AW = 27;
+ localparam int DW = 32;
+ localparam int DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+ logic reg_busy;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+
+ // incoming payload check
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
+ .tl_i(tl_i),
+ .err_o(intg_err)
+ );
+
+ // also check for spurious write enables
+ logic reg_we_err;
+ logic [50:0] reg_we_check;
+ prim_reg_we_check #(
+ .OneHotWidth(51)
+ ) u_prim_reg_we_check (
+ .clk_i(clk_i),
+ .rst_ni(rst_ni),
+ .oh_i (reg_we_check),
+ .en_i (reg_we && !addrmiss),
+ .err_o (reg_we_err)
+ );
+
+ logic err_q;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ err_q <= '0;
+ end else if (intg_err || reg_we_err) begin
+ err_q <= 1'b1;
+ end
+ end
+
+ // integrity error output is permanent and should be used for alert generation
+ // register errors are transactional
+ assign intg_err_o = err_q | intg_err | reg_we_err;
+
+ // outgoing integrity generation
+ tlul_pkg::tl_d2h_t tl_o_pre;
+ tlul_rsp_intg_gen #(
+ .EnableRspIntgGen(1),
+ .EnableDataIntgGen(1)
+ ) u_rsp_intg_gen (
+ .tl_i(tl_o_pre),
+ .tl_o(tl_o)
+ );
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o_pre = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW),
+ .EnableDataIntgGen(0)
+ ) u_reg_if (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .en_ifetch_i(prim_mubi_pkg::MuBi4False),
+ .intg_error_o(),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .busy_i (reg_busy),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ // cdc oversampling signals
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic prio0_we;
+ logic [1:0] prio0_qs;
+ logic [1:0] prio0_wd;
+ logic prio1_we;
+ logic [1:0] prio1_qs;
+ logic [1:0] prio1_wd;
+ logic prio2_we;
+ logic [1:0] prio2_qs;
+ logic [1:0] prio2_wd;
+ logic prio3_we;
+ logic [1:0] prio3_qs;
+ logic [1:0] prio3_wd;
+ logic prio4_we;
+ logic [1:0] prio4_qs;
+ logic [1:0] prio4_wd;
+ logic prio5_we;
+ logic [1:0] prio5_qs;
+ logic [1:0] prio5_wd;
+ logic prio6_we;
+ logic [1:0] prio6_qs;
+ logic [1:0] prio6_wd;
+ logic prio7_we;
+ logic [1:0] prio7_qs;
+ logic [1:0] prio7_wd;
+ logic prio8_we;
+ logic [1:0] prio8_qs;
+ logic [1:0] prio8_wd;
+ logic prio9_we;
+ logic [1:0] prio9_qs;
+ logic [1:0] prio9_wd;
+ logic prio10_we;
+ logic [1:0] prio10_qs;
+ logic [1:0] prio10_wd;
+ logic prio11_we;
+ logic [1:0] prio11_qs;
+ logic [1:0] prio11_wd;
+ logic prio12_we;
+ logic [1:0] prio12_qs;
+ logic [1:0] prio12_wd;
+ logic prio13_we;
+ logic [1:0] prio13_qs;
+ logic [1:0] prio13_wd;
+ logic prio14_we;
+ logic [1:0] prio14_qs;
+ logic [1:0] prio14_wd;
+ logic prio15_we;
+ logic [1:0] prio15_qs;
+ logic [1:0] prio15_wd;
+ logic prio16_we;
+ logic [1:0] prio16_qs;
+ logic [1:0] prio16_wd;
+ logic prio17_we;
+ logic [1:0] prio17_qs;
+ logic [1:0] prio17_wd;
+ logic prio18_we;
+ logic [1:0] prio18_qs;
+ logic [1:0] prio18_wd;
+ logic prio19_we;
+ logic [1:0] prio19_qs;
+ logic [1:0] prio19_wd;
+ logic prio20_we;
+ logic [1:0] prio20_qs;
+ logic [1:0] prio20_wd;
+ logic prio21_we;
+ logic [1:0] prio21_qs;
+ logic [1:0] prio21_wd;
+ logic prio22_we;
+ logic [1:0] prio22_qs;
+ logic [1:0] prio22_wd;
+ logic prio23_we;
+ logic [1:0] prio23_qs;
+ logic [1:0] prio23_wd;
+ logic prio24_we;
+ logic [1:0] prio24_qs;
+ logic [1:0] prio24_wd;
+ logic prio25_we;
+ logic [1:0] prio25_qs;
+ logic [1:0] prio25_wd;
+ logic prio26_we;
+ logic [1:0] prio26_qs;
+ logic [1:0] prio26_wd;
+ logic prio27_we;
+ logic [1:0] prio27_qs;
+ logic [1:0] prio27_wd;
+ logic prio28_we;
+ logic [1:0] prio28_qs;
+ logic [1:0] prio28_wd;
+ logic prio29_we;
+ logic [1:0] prio29_qs;
+ logic [1:0] prio29_wd;
+ logic prio30_we;
+ logic [1:0] prio30_qs;
+ logic [1:0] prio30_wd;
+ logic prio31_we;
+ logic [1:0] prio31_qs;
+ logic [1:0] prio31_wd;
+ logic prio32_we;
+ logic [1:0] prio32_qs;
+ logic [1:0] prio32_wd;
+ logic prio33_we;
+ logic [1:0] prio33_qs;
+ logic [1:0] prio33_wd;
+ logic prio34_we;
+ logic [1:0] prio34_qs;
+ logic [1:0] prio34_wd;
+ logic prio35_we;
+ logic [1:0] prio35_qs;
+ logic [1:0] prio35_wd;
+ logic prio36_we;
+ logic [1:0] prio36_qs;
+ logic [1:0] prio36_wd;
+ logic prio37_we;
+ logic [1:0] prio37_qs;
+ logic [1:0] prio37_wd;
+ logic prio38_we;
+ logic [1:0] prio38_qs;
+ logic [1:0] prio38_wd;
+ logic prio39_we;
+ logic [1:0] prio39_qs;
+ logic [1:0] prio39_wd;
+ logic prio40_we;
+ logic [1:0] prio40_qs;
+ logic [1:0] prio40_wd;
+ logic prio41_we;
+ logic [1:0] prio41_qs;
+ logic [1:0] prio41_wd;
+ logic prio42_we;
+ logic [1:0] prio42_qs;
+ logic [1:0] prio42_wd;
+ logic ip_0_p_0_qs;
+ logic ip_0_p_1_qs;
+ logic ip_0_p_2_qs;
+ logic ip_0_p_3_qs;
+ logic ip_0_p_4_qs;
+ logic ip_0_p_5_qs;
+ logic ip_0_p_6_qs;
+ logic ip_0_p_7_qs;
+ logic ip_0_p_8_qs;
+ logic ip_0_p_9_qs;
+ logic ip_0_p_10_qs;
+ logic ip_0_p_11_qs;
+ logic ip_0_p_12_qs;
+ logic ip_0_p_13_qs;
+ logic ip_0_p_14_qs;
+ logic ip_0_p_15_qs;
+ logic ip_0_p_16_qs;
+ logic ip_0_p_17_qs;
+ logic ip_0_p_18_qs;
+ logic ip_0_p_19_qs;
+ logic ip_0_p_20_qs;
+ logic ip_0_p_21_qs;
+ logic ip_0_p_22_qs;
+ logic ip_0_p_23_qs;
+ logic ip_0_p_24_qs;
+ logic ip_0_p_25_qs;
+ logic ip_0_p_26_qs;
+ logic ip_0_p_27_qs;
+ logic ip_0_p_28_qs;
+ logic ip_0_p_29_qs;
+ logic ip_0_p_30_qs;
+ logic ip_0_p_31_qs;
+ logic ip_1_p_32_qs;
+ logic ip_1_p_33_qs;
+ logic ip_1_p_34_qs;
+ logic ip_1_p_35_qs;
+ logic ip_1_p_36_qs;
+ logic ip_1_p_37_qs;
+ logic ip_1_p_38_qs;
+ logic ip_1_p_39_qs;
+ logic ip_1_p_40_qs;
+ logic ip_1_p_41_qs;
+ logic ip_1_p_42_qs;
+ logic ie0_0_we;
+ logic ie0_0_e_0_qs;
+ logic ie0_0_e_0_wd;
+ logic ie0_0_e_1_qs;
+ logic ie0_0_e_1_wd;
+ logic ie0_0_e_2_qs;
+ logic ie0_0_e_2_wd;
+ logic ie0_0_e_3_qs;
+ logic ie0_0_e_3_wd;
+ logic ie0_0_e_4_qs;
+ logic ie0_0_e_4_wd;
+ logic ie0_0_e_5_qs;
+ logic ie0_0_e_5_wd;
+ logic ie0_0_e_6_qs;
+ logic ie0_0_e_6_wd;
+ logic ie0_0_e_7_qs;
+ logic ie0_0_e_7_wd;
+ logic ie0_0_e_8_qs;
+ logic ie0_0_e_8_wd;
+ logic ie0_0_e_9_qs;
+ logic ie0_0_e_9_wd;
+ logic ie0_0_e_10_qs;
+ logic ie0_0_e_10_wd;
+ logic ie0_0_e_11_qs;
+ logic ie0_0_e_11_wd;
+ logic ie0_0_e_12_qs;
+ logic ie0_0_e_12_wd;
+ logic ie0_0_e_13_qs;
+ logic ie0_0_e_13_wd;
+ logic ie0_0_e_14_qs;
+ logic ie0_0_e_14_wd;
+ logic ie0_0_e_15_qs;
+ logic ie0_0_e_15_wd;
+ logic ie0_0_e_16_qs;
+ logic ie0_0_e_16_wd;
+ logic ie0_0_e_17_qs;
+ logic ie0_0_e_17_wd;
+ logic ie0_0_e_18_qs;
+ logic ie0_0_e_18_wd;
+ logic ie0_0_e_19_qs;
+ logic ie0_0_e_19_wd;
+ logic ie0_0_e_20_qs;
+ logic ie0_0_e_20_wd;
+ logic ie0_0_e_21_qs;
+ logic ie0_0_e_21_wd;
+ logic ie0_0_e_22_qs;
+ logic ie0_0_e_22_wd;
+ logic ie0_0_e_23_qs;
+ logic ie0_0_e_23_wd;
+ logic ie0_0_e_24_qs;
+ logic ie0_0_e_24_wd;
+ logic ie0_0_e_25_qs;
+ logic ie0_0_e_25_wd;
+ logic ie0_0_e_26_qs;
+ logic ie0_0_e_26_wd;
+ logic ie0_0_e_27_qs;
+ logic ie0_0_e_27_wd;
+ logic ie0_0_e_28_qs;
+ logic ie0_0_e_28_wd;
+ logic ie0_0_e_29_qs;
+ logic ie0_0_e_29_wd;
+ logic ie0_0_e_30_qs;
+ logic ie0_0_e_30_wd;
+ logic ie0_0_e_31_qs;
+ logic ie0_0_e_31_wd;
+ logic ie0_1_we;
+ logic ie0_1_e_32_qs;
+ logic ie0_1_e_32_wd;
+ logic ie0_1_e_33_qs;
+ logic ie0_1_e_33_wd;
+ logic ie0_1_e_34_qs;
+ logic ie0_1_e_34_wd;
+ logic ie0_1_e_35_qs;
+ logic ie0_1_e_35_wd;
+ logic ie0_1_e_36_qs;
+ logic ie0_1_e_36_wd;
+ logic ie0_1_e_37_qs;
+ logic ie0_1_e_37_wd;
+ logic ie0_1_e_38_qs;
+ logic ie0_1_e_38_wd;
+ logic ie0_1_e_39_qs;
+ logic ie0_1_e_39_wd;
+ logic ie0_1_e_40_qs;
+ logic ie0_1_e_40_wd;
+ logic ie0_1_e_41_qs;
+ logic ie0_1_e_41_wd;
+ logic ie0_1_e_42_qs;
+ logic ie0_1_e_42_wd;
+ logic threshold0_we;
+ logic [1:0] threshold0_qs;
+ logic [1:0] threshold0_wd;
+ logic cc0_re;
+ logic cc0_we;
+ logic [5:0] cc0_qs;
+ logic [5:0] cc0_wd;
+ logic msip0_we;
+ logic msip0_qs;
+ logic msip0_wd;
+ logic alert_test_we;
+ logic alert_test_wd;
+
+ // Register instances
+ // R[prio0]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio0_we),
+ .wd (prio0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio0_qs)
+ );
+
+
+ // R[prio1]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio1_we),
+ .wd (prio1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio1.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio1_qs)
+ );
+
+
+ // R[prio2]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio2_we),
+ .wd (prio2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio2.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio2_qs)
+ );
+
+
+ // R[prio3]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio3_we),
+ .wd (prio3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio3.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio3_qs)
+ );
+
+
+ // R[prio4]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio4_we),
+ .wd (prio4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio4.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio4_qs)
+ );
+
+
+ // R[prio5]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio5_we),
+ .wd (prio5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio5.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio5_qs)
+ );
+
+
+ // R[prio6]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio6_we),
+ .wd (prio6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio6.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio6_qs)
+ );
+
+
+ // R[prio7]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio7_we),
+ .wd (prio7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio7.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio7_qs)
+ );
+
+
+ // R[prio8]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio8_we),
+ .wd (prio8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio8.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio8_qs)
+ );
+
+
+ // R[prio9]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio9_we),
+ .wd (prio9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio9.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio9_qs)
+ );
+
+
+ // R[prio10]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio10_we),
+ .wd (prio10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio10.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio10_qs)
+ );
+
+
+ // R[prio11]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio11_we),
+ .wd (prio11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio11.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio11_qs)
+ );
+
+
+ // R[prio12]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio12_we),
+ .wd (prio12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio12.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio12_qs)
+ );
+
+
+ // R[prio13]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio13_we),
+ .wd (prio13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio13.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio13_qs)
+ );
+
+
+ // R[prio14]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio14_we),
+ .wd (prio14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio14.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio14_qs)
+ );
+
+
+ // R[prio15]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio15_we),
+ .wd (prio15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio15.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio15_qs)
+ );
+
+
+ // R[prio16]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio16_we),
+ .wd (prio16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio16.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio16_qs)
+ );
+
+
+ // R[prio17]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio17_we),
+ .wd (prio17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio17.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio17_qs)
+ );
+
+
+ // R[prio18]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio18_we),
+ .wd (prio18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio18.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio18_qs)
+ );
+
+
+ // R[prio19]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio19_we),
+ .wd (prio19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio19.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio19_qs)
+ );
+
+
+ // R[prio20]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio20_we),
+ .wd (prio20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio20.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio20_qs)
+ );
+
+
+ // R[prio21]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio21_we),
+ .wd (prio21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio21.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio21_qs)
+ );
+
+
+ // R[prio22]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio22_we),
+ .wd (prio22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio22.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio22_qs)
+ );
+
+
+ // R[prio23]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio23_we),
+ .wd (prio23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio23.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio23_qs)
+ );
+
+
+ // R[prio24]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio24_we),
+ .wd (prio24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio24.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio24_qs)
+ );
+
+
+ // R[prio25]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio25_we),
+ .wd (prio25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio25.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio25_qs)
+ );
+
+
+ // R[prio26]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio26_we),
+ .wd (prio26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio26.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio26_qs)
+ );
+
+
+ // R[prio27]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio27_we),
+ .wd (prio27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio27.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio27_qs)
+ );
+
+
+ // R[prio28]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio28_we),
+ .wd (prio28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio28.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio28_qs)
+ );
+
+
+ // R[prio29]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio29_we),
+ .wd (prio29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio29.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio29_qs)
+ );
+
+
+ // R[prio30]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio30_we),
+ .wd (prio30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio30.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio30_qs)
+ );
+
+
+ // R[prio31]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio31_we),
+ .wd (prio31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio31.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio31_qs)
+ );
+
+
+ // R[prio32]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio32_we),
+ .wd (prio32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio32.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio32_qs)
+ );
+
+
+ // R[prio33]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio33_we),
+ .wd (prio33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio33.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio33_qs)
+ );
+
+
+ // R[prio34]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio34_we),
+ .wd (prio34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio34.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio34_qs)
+ );
+
+
+ // R[prio35]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio35_we),
+ .wd (prio35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio35.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio35_qs)
+ );
+
+
+ // R[prio36]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio36_we),
+ .wd (prio36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio36.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio36_qs)
+ );
+
+
+ // R[prio37]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio37_we),
+ .wd (prio37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio37.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio37_qs)
+ );
+
+
+ // R[prio38]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio38_we),
+ .wd (prio38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio38.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio38_qs)
+ );
+
+
+ // R[prio39]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio39_we),
+ .wd (prio39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio39.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio39_qs)
+ );
+
+
+ // R[prio40]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio40_we),
+ .wd (prio40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio40.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio40_qs)
+ );
+
+
+ // R[prio41]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio41_we),
+ .wd (prio41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio41.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio41_qs)
+ );
+
+
+ // R[prio42]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_prio42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (prio42_we),
+ .wd (prio42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio42.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (prio42_qs)
+ );
+
+
+ // Subregister 0 of Multireg ip
+ // R[ip_0]: V(False)
+ // F[p_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[0].de),
+ .d (hw2reg.ip[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_0_qs)
+ );
+
+ // F[p_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[1].de),
+ .d (hw2reg.ip[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_1_qs)
+ );
+
+ // F[p_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[2].de),
+ .d (hw2reg.ip[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_2_qs)
+ );
+
+ // F[p_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[3].de),
+ .d (hw2reg.ip[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_3_qs)
+ );
+
+ // F[p_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[4].de),
+ .d (hw2reg.ip[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_4_qs)
+ );
+
+ // F[p_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[5].de),
+ .d (hw2reg.ip[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_5_qs)
+ );
+
+ // F[p_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[6].de),
+ .d (hw2reg.ip[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_6_qs)
+ );
+
+ // F[p_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[7].de),
+ .d (hw2reg.ip[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_7_qs)
+ );
+
+ // F[p_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[8].de),
+ .d (hw2reg.ip[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_8_qs)
+ );
+
+ // F[p_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[9].de),
+ .d (hw2reg.ip[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_9_qs)
+ );
+
+ // F[p_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[10].de),
+ .d (hw2reg.ip[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_10_qs)
+ );
+
+ // F[p_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[11].de),
+ .d (hw2reg.ip[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_11_qs)
+ );
+
+ // F[p_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[12].de),
+ .d (hw2reg.ip[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_12_qs)
+ );
+
+ // F[p_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[13].de),
+ .d (hw2reg.ip[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_13_qs)
+ );
+
+ // F[p_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[14].de),
+ .d (hw2reg.ip[14].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_14_qs)
+ );
+
+ // F[p_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[15].de),
+ .d (hw2reg.ip[15].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_15_qs)
+ );
+
+ // F[p_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[16].de),
+ .d (hw2reg.ip[16].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_16_qs)
+ );
+
+ // F[p_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[17].de),
+ .d (hw2reg.ip[17].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_17_qs)
+ );
+
+ // F[p_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[18].de),
+ .d (hw2reg.ip[18].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_18_qs)
+ );
+
+ // F[p_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[19].de),
+ .d (hw2reg.ip[19].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_19_qs)
+ );
+
+ // F[p_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[20].de),
+ .d (hw2reg.ip[20].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_20_qs)
+ );
+
+ // F[p_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[21].de),
+ .d (hw2reg.ip[21].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_21_qs)
+ );
+
+ // F[p_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[22].de),
+ .d (hw2reg.ip[22].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_22_qs)
+ );
+
+ // F[p_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[23].de),
+ .d (hw2reg.ip[23].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_23_qs)
+ );
+
+ // F[p_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[24].de),
+ .d (hw2reg.ip[24].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_24_qs)
+ );
+
+ // F[p_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[25].de),
+ .d (hw2reg.ip[25].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_25_qs)
+ );
+
+ // F[p_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[26].de),
+ .d (hw2reg.ip[26].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_26_qs)
+ );
+
+ // F[p_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[27].de),
+ .d (hw2reg.ip[27].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_27_qs)
+ );
+
+ // F[p_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[28].de),
+ .d (hw2reg.ip[28].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_28_qs)
+ );
+
+ // F[p_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[29].de),
+ .d (hw2reg.ip[29].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_29_qs)
+ );
+
+ // F[p_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[30].de),
+ .d (hw2reg.ip[30].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_30_qs)
+ );
+
+ // F[p_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_0_p_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[31].de),
+ .d (hw2reg.ip[31].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_0_p_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg ip
+ // R[ip_1]: V(False)
+ // F[p_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[32].de),
+ .d (hw2reg.ip[32].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_32_qs)
+ );
+
+ // F[p_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[33].de),
+ .d (hw2reg.ip[33].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_33_qs)
+ );
+
+ // F[p_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[34].de),
+ .d (hw2reg.ip[34].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_34_qs)
+ );
+
+ // F[p_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[35].de),
+ .d (hw2reg.ip[35].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_35_qs)
+ );
+
+ // F[p_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[36].de),
+ .d (hw2reg.ip[36].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_36_qs)
+ );
+
+ // F[p_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[37].de),
+ .d (hw2reg.ip[37].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_37_qs)
+ );
+
+ // F[p_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[38].de),
+ .d (hw2reg.ip[38].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_38_qs)
+ );
+
+ // F[p_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[39].de),
+ .d (hw2reg.ip[39].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_39_qs)
+ );
+
+ // F[p_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[40].de),
+ .d (hw2reg.ip[40].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_40_qs)
+ );
+
+ // F[p_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[41].de),
+ .d (hw2reg.ip[41].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_41_qs)
+ );
+
+ // F[p_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_ip_1_p_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.ip[42].de),
+ .d (hw2reg.ip[42].d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ip_1_p_42_qs)
+ );
+
+
+ // Subregister 0 of Multireg ie0
+ // R[ie0_0]: V(False)
+ // F[e_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[0].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_0_qs)
+ );
+
+ // F[e_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[1].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_1_qs)
+ );
+
+ // F[e_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[2].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_2_qs)
+ );
+
+ // F[e_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[3].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_3_qs)
+ );
+
+ // F[e_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[4].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_4_qs)
+ );
+
+ // F[e_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[5].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_5_qs)
+ );
+
+ // F[e_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[6].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_6_qs)
+ );
+
+ // F[e_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[7].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_7_qs)
+ );
+
+ // F[e_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[8].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_8_qs)
+ );
+
+ // F[e_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[9].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_9_qs)
+ );
+
+ // F[e_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[10].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_10_qs)
+ );
+
+ // F[e_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[11].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_11_qs)
+ );
+
+ // F[e_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[12].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_12_qs)
+ );
+
+ // F[e_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[13].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_13_qs)
+ );
+
+ // F[e_14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_14 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[14].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_14_qs)
+ );
+
+ // F[e_15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_15 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[15].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_15_qs)
+ );
+
+ // F[e_16]: 16:16
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_16 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[16].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_16_qs)
+ );
+
+ // F[e_17]: 17:17
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_17 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[17].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_17_qs)
+ );
+
+ // F[e_18]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_18 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[18].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_18_qs)
+ );
+
+ // F[e_19]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_19 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[19].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_19_qs)
+ );
+
+ // F[e_20]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_20 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[20].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_20_qs)
+ );
+
+ // F[e_21]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_21 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[21].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_21_qs)
+ );
+
+ // F[e_22]: 22:22
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_22 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[22].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_22_qs)
+ );
+
+ // F[e_23]: 23:23
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_23 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[23].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_23_qs)
+ );
+
+ // F[e_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_24 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[24].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_24_qs)
+ );
+
+ // F[e_25]: 25:25
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_25 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[25].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_25_qs)
+ );
+
+ // F[e_26]: 26:26
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_26 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[26].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_26_qs)
+ );
+
+ // F[e_27]: 27:27
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_27 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[27].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_27_qs)
+ );
+
+ // F[e_28]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_28 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[28].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_28_qs)
+ );
+
+ // F[e_29]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_29 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[29].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_29_qs)
+ );
+
+ // F[e_30]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_30 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[30].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_30_qs)
+ );
+
+ // F[e_31]: 31:31
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_0_e_31 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_0_we),
+ .wd (ie0_0_e_31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[31].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_0_e_31_qs)
+ );
+
+
+ // Subregister 1 of Multireg ie0
+ // R[ie0_1]: V(False)
+ // F[e_32]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_32 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_32_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[32].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_32_qs)
+ );
+
+ // F[e_33]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_33 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_33_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[33].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_33_qs)
+ );
+
+ // F[e_34]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_34 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_34_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[34].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_34_qs)
+ );
+
+ // F[e_35]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_35 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_35_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[35].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_35_qs)
+ );
+
+ // F[e_36]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_36 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_36_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[36].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_36_qs)
+ );
+
+ // F[e_37]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_37 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_37_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[37].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_37_qs)
+ );
+
+ // F[e_38]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_38 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_38_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[38].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_38_qs)
+ );
+
+ // F[e_39]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_39 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_39_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[39].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_39_qs)
+ );
+
+ // F[e_40]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[40].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_40_qs)
+ );
+
+ // F[e_41]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_41 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_41_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[41].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_41_qs)
+ );
+
+ // F[e_42]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_ie0_1_e_42 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (ie0_1_we),
+ .wd (ie0_1_e_42_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[42].q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (ie0_1_e_42_qs)
+ );
+
+
+ // R[threshold0]: V(False)
+ prim_subreg #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_threshold0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (threshold0_we),
+ .wd (threshold0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.threshold0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (threshold0_qs)
+ );
+
+
+ // R[cc0]: V(True)
+ logic cc0_qe;
+ logic [0:0] cc0_flds_we;
+ assign cc0_qe = &cc0_flds_we;
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_cc0 (
+ .re (cc0_re),
+ .we (cc0_we),
+ .wd (cc0_wd),
+ .d (hw2reg.cc0.d),
+ .qre (reg2hw.cc0.re),
+ .qe (cc0_flds_we[0]),
+ .q (reg2hw.cc0.q),
+ .ds (),
+ .qs (cc0_qs)
+ );
+ assign reg2hw.cc0.qe = cc0_qe;
+
+
+ // R[msip0]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_msip0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (msip0_we),
+ .wd (msip0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.msip0.q),
+ .ds (),
+
+ // to register interface (read)
+ .qs (msip0_qs)
+ );
+
+
+ // R[alert_test]: V(True)
+ logic alert_test_qe;
+ logic [0:0] alert_test_flds_we;
+ assign alert_test_qe = &alert_test_flds_we;
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (alert_test_flds_we[0]),
+ .q (reg2hw.alert_test.q),
+ .ds (),
+ .qs ()
+ );
+ assign reg2hw.alert_test.qe = alert_test_qe;
+
+
+
+ logic [50:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == RV_PLIC_SMC_PRIO0_OFFSET);
+ addr_hit[ 1] = (reg_addr == RV_PLIC_SMC_PRIO1_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_SMC_PRIO2_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_SMC_PRIO3_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_SMC_PRIO4_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_SMC_PRIO5_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_SMC_PRIO6_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_SMC_PRIO7_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_SMC_PRIO8_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_SMC_PRIO9_OFFSET);
+ addr_hit[10] = (reg_addr == RV_PLIC_SMC_PRIO10_OFFSET);
+ addr_hit[11] = (reg_addr == RV_PLIC_SMC_PRIO11_OFFSET);
+ addr_hit[12] = (reg_addr == RV_PLIC_SMC_PRIO12_OFFSET);
+ addr_hit[13] = (reg_addr == RV_PLIC_SMC_PRIO13_OFFSET);
+ addr_hit[14] = (reg_addr == RV_PLIC_SMC_PRIO14_OFFSET);
+ addr_hit[15] = (reg_addr == RV_PLIC_SMC_PRIO15_OFFSET);
+ addr_hit[16] = (reg_addr == RV_PLIC_SMC_PRIO16_OFFSET);
+ addr_hit[17] = (reg_addr == RV_PLIC_SMC_PRIO17_OFFSET);
+ addr_hit[18] = (reg_addr == RV_PLIC_SMC_PRIO18_OFFSET);
+ addr_hit[19] = (reg_addr == RV_PLIC_SMC_PRIO19_OFFSET);
+ addr_hit[20] = (reg_addr == RV_PLIC_SMC_PRIO20_OFFSET);
+ addr_hit[21] = (reg_addr == RV_PLIC_SMC_PRIO21_OFFSET);
+ addr_hit[22] = (reg_addr == RV_PLIC_SMC_PRIO22_OFFSET);
+ addr_hit[23] = (reg_addr == RV_PLIC_SMC_PRIO23_OFFSET);
+ addr_hit[24] = (reg_addr == RV_PLIC_SMC_PRIO24_OFFSET);
+ addr_hit[25] = (reg_addr == RV_PLIC_SMC_PRIO25_OFFSET);
+ addr_hit[26] = (reg_addr == RV_PLIC_SMC_PRIO26_OFFSET);
+ addr_hit[27] = (reg_addr == RV_PLIC_SMC_PRIO27_OFFSET);
+ addr_hit[28] = (reg_addr == RV_PLIC_SMC_PRIO28_OFFSET);
+ addr_hit[29] = (reg_addr == RV_PLIC_SMC_PRIO29_OFFSET);
+ addr_hit[30] = (reg_addr == RV_PLIC_SMC_PRIO30_OFFSET);
+ addr_hit[31] = (reg_addr == RV_PLIC_SMC_PRIO31_OFFSET);
+ addr_hit[32] = (reg_addr == RV_PLIC_SMC_PRIO32_OFFSET);
+ addr_hit[33] = (reg_addr == RV_PLIC_SMC_PRIO33_OFFSET);
+ addr_hit[34] = (reg_addr == RV_PLIC_SMC_PRIO34_OFFSET);
+ addr_hit[35] = (reg_addr == RV_PLIC_SMC_PRIO35_OFFSET);
+ addr_hit[36] = (reg_addr == RV_PLIC_SMC_PRIO36_OFFSET);
+ addr_hit[37] = (reg_addr == RV_PLIC_SMC_PRIO37_OFFSET);
+ addr_hit[38] = (reg_addr == RV_PLIC_SMC_PRIO38_OFFSET);
+ addr_hit[39] = (reg_addr == RV_PLIC_SMC_PRIO39_OFFSET);
+ addr_hit[40] = (reg_addr == RV_PLIC_SMC_PRIO40_OFFSET);
+ addr_hit[41] = (reg_addr == RV_PLIC_SMC_PRIO41_OFFSET);
+ addr_hit[42] = (reg_addr == RV_PLIC_SMC_PRIO42_OFFSET);
+ addr_hit[43] = (reg_addr == RV_PLIC_SMC_IP_0_OFFSET);
+ addr_hit[44] = (reg_addr == RV_PLIC_SMC_IP_1_OFFSET);
+ addr_hit[45] = (reg_addr == RV_PLIC_SMC_IE0_0_OFFSET);
+ addr_hit[46] = (reg_addr == RV_PLIC_SMC_IE0_1_OFFSET);
+ addr_hit[47] = (reg_addr == RV_PLIC_SMC_THRESHOLD0_OFFSET);
+ addr_hit[48] = (reg_addr == RV_PLIC_SMC_CC0_OFFSET);
+ addr_hit[49] = (reg_addr == RV_PLIC_SMC_MSIP0_OFFSET);
+ addr_hit[50] = (reg_addr == RV_PLIC_SMC_ALERT_TEST_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = (reg_we &
+ ((addr_hit[ 0] & (|(RV_PLIC_SMC_PERMIT[ 0] & ~reg_be))) |
+ (addr_hit[ 1] & (|(RV_PLIC_SMC_PERMIT[ 1] & ~reg_be))) |
+ (addr_hit[ 2] & (|(RV_PLIC_SMC_PERMIT[ 2] & ~reg_be))) |
+ (addr_hit[ 3] & (|(RV_PLIC_SMC_PERMIT[ 3] & ~reg_be))) |
+ (addr_hit[ 4] & (|(RV_PLIC_SMC_PERMIT[ 4] & ~reg_be))) |
+ (addr_hit[ 5] & (|(RV_PLIC_SMC_PERMIT[ 5] & ~reg_be))) |
+ (addr_hit[ 6] & (|(RV_PLIC_SMC_PERMIT[ 6] & ~reg_be))) |
+ (addr_hit[ 7] & (|(RV_PLIC_SMC_PERMIT[ 7] & ~reg_be))) |
+ (addr_hit[ 8] & (|(RV_PLIC_SMC_PERMIT[ 8] & ~reg_be))) |
+ (addr_hit[ 9] & (|(RV_PLIC_SMC_PERMIT[ 9] & ~reg_be))) |
+ (addr_hit[10] & (|(RV_PLIC_SMC_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(RV_PLIC_SMC_PERMIT[11] & ~reg_be))) |
+ (addr_hit[12] & (|(RV_PLIC_SMC_PERMIT[12] & ~reg_be))) |
+ (addr_hit[13] & (|(RV_PLIC_SMC_PERMIT[13] & ~reg_be))) |
+ (addr_hit[14] & (|(RV_PLIC_SMC_PERMIT[14] & ~reg_be))) |
+ (addr_hit[15] & (|(RV_PLIC_SMC_PERMIT[15] & ~reg_be))) |
+ (addr_hit[16] & (|(RV_PLIC_SMC_PERMIT[16] & ~reg_be))) |
+ (addr_hit[17] & (|(RV_PLIC_SMC_PERMIT[17] & ~reg_be))) |
+ (addr_hit[18] & (|(RV_PLIC_SMC_PERMIT[18] & ~reg_be))) |
+ (addr_hit[19] & (|(RV_PLIC_SMC_PERMIT[19] & ~reg_be))) |
+ (addr_hit[20] & (|(RV_PLIC_SMC_PERMIT[20] & ~reg_be))) |
+ (addr_hit[21] & (|(RV_PLIC_SMC_PERMIT[21] & ~reg_be))) |
+ (addr_hit[22] & (|(RV_PLIC_SMC_PERMIT[22] & ~reg_be))) |
+ (addr_hit[23] & (|(RV_PLIC_SMC_PERMIT[23] & ~reg_be))) |
+ (addr_hit[24] & (|(RV_PLIC_SMC_PERMIT[24] & ~reg_be))) |
+ (addr_hit[25] & (|(RV_PLIC_SMC_PERMIT[25] & ~reg_be))) |
+ (addr_hit[26] & (|(RV_PLIC_SMC_PERMIT[26] & ~reg_be))) |
+ (addr_hit[27] & (|(RV_PLIC_SMC_PERMIT[27] & ~reg_be))) |
+ (addr_hit[28] & (|(RV_PLIC_SMC_PERMIT[28] & ~reg_be))) |
+ (addr_hit[29] & (|(RV_PLIC_SMC_PERMIT[29] & ~reg_be))) |
+ (addr_hit[30] & (|(RV_PLIC_SMC_PERMIT[30] & ~reg_be))) |
+ (addr_hit[31] & (|(RV_PLIC_SMC_PERMIT[31] & ~reg_be))) |
+ (addr_hit[32] & (|(RV_PLIC_SMC_PERMIT[32] & ~reg_be))) |
+ (addr_hit[33] & (|(RV_PLIC_SMC_PERMIT[33] & ~reg_be))) |
+ (addr_hit[34] & (|(RV_PLIC_SMC_PERMIT[34] & ~reg_be))) |
+ (addr_hit[35] & (|(RV_PLIC_SMC_PERMIT[35] & ~reg_be))) |
+ (addr_hit[36] & (|(RV_PLIC_SMC_PERMIT[36] & ~reg_be))) |
+ (addr_hit[37] & (|(RV_PLIC_SMC_PERMIT[37] & ~reg_be))) |
+ (addr_hit[38] & (|(RV_PLIC_SMC_PERMIT[38] & ~reg_be))) |
+ (addr_hit[39] & (|(RV_PLIC_SMC_PERMIT[39] & ~reg_be))) |
+ (addr_hit[40] & (|(RV_PLIC_SMC_PERMIT[40] & ~reg_be))) |
+ (addr_hit[41] & (|(RV_PLIC_SMC_PERMIT[41] & ~reg_be))) |
+ (addr_hit[42] & (|(RV_PLIC_SMC_PERMIT[42] & ~reg_be))) |
+ (addr_hit[43] & (|(RV_PLIC_SMC_PERMIT[43] & ~reg_be))) |
+ (addr_hit[44] & (|(RV_PLIC_SMC_PERMIT[44] & ~reg_be))) |
+ (addr_hit[45] & (|(RV_PLIC_SMC_PERMIT[45] & ~reg_be))) |
+ (addr_hit[46] & (|(RV_PLIC_SMC_PERMIT[46] & ~reg_be))) |
+ (addr_hit[47] & (|(RV_PLIC_SMC_PERMIT[47] & ~reg_be))) |
+ (addr_hit[48] & (|(RV_PLIC_SMC_PERMIT[48] & ~reg_be))) |
+ (addr_hit[49] & (|(RV_PLIC_SMC_PERMIT[49] & ~reg_be))) |
+ (addr_hit[50] & (|(RV_PLIC_SMC_PERMIT[50] & ~reg_be)))));
+ end
+
+ // Generate write-enables
+ assign prio0_we = addr_hit[0] & reg_we & !reg_error;
+
+ assign prio0_wd = reg_wdata[1:0];
+ assign prio1_we = addr_hit[1] & reg_we & !reg_error;
+
+ assign prio1_wd = reg_wdata[1:0];
+ assign prio2_we = addr_hit[2] & reg_we & !reg_error;
+
+ assign prio2_wd = reg_wdata[1:0];
+ assign prio3_we = addr_hit[3] & reg_we & !reg_error;
+
+ assign prio3_wd = reg_wdata[1:0];
+ assign prio4_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign prio4_wd = reg_wdata[1:0];
+ assign prio5_we = addr_hit[5] & reg_we & !reg_error;
+
+ assign prio5_wd = reg_wdata[1:0];
+ assign prio6_we = addr_hit[6] & reg_we & !reg_error;
+
+ assign prio6_wd = reg_wdata[1:0];
+ assign prio7_we = addr_hit[7] & reg_we & !reg_error;
+
+ assign prio7_wd = reg_wdata[1:0];
+ assign prio8_we = addr_hit[8] & reg_we & !reg_error;
+
+ assign prio8_wd = reg_wdata[1:0];
+ assign prio9_we = addr_hit[9] & reg_we & !reg_error;
+
+ assign prio9_wd = reg_wdata[1:0];
+ assign prio10_we = addr_hit[10] & reg_we & !reg_error;
+
+ assign prio10_wd = reg_wdata[1:0];
+ assign prio11_we = addr_hit[11] & reg_we & !reg_error;
+
+ assign prio11_wd = reg_wdata[1:0];
+ assign prio12_we = addr_hit[12] & reg_we & !reg_error;
+
+ assign prio12_wd = reg_wdata[1:0];
+ assign prio13_we = addr_hit[13] & reg_we & !reg_error;
+
+ assign prio13_wd = reg_wdata[1:0];
+ assign prio14_we = addr_hit[14] & reg_we & !reg_error;
+
+ assign prio14_wd = reg_wdata[1:0];
+ assign prio15_we = addr_hit[15] & reg_we & !reg_error;
+
+ assign prio15_wd = reg_wdata[1:0];
+ assign prio16_we = addr_hit[16] & reg_we & !reg_error;
+
+ assign prio16_wd = reg_wdata[1:0];
+ assign prio17_we = addr_hit[17] & reg_we & !reg_error;
+
+ assign prio17_wd = reg_wdata[1:0];
+ assign prio18_we = addr_hit[18] & reg_we & !reg_error;
+
+ assign prio18_wd = reg_wdata[1:0];
+ assign prio19_we = addr_hit[19] & reg_we & !reg_error;
+
+ assign prio19_wd = reg_wdata[1:0];
+ assign prio20_we = addr_hit[20] & reg_we & !reg_error;
+
+ assign prio20_wd = reg_wdata[1:0];
+ assign prio21_we = addr_hit[21] & reg_we & !reg_error;
+
+ assign prio21_wd = reg_wdata[1:0];
+ assign prio22_we = addr_hit[22] & reg_we & !reg_error;
+
+ assign prio22_wd = reg_wdata[1:0];
+ assign prio23_we = addr_hit[23] & reg_we & !reg_error;
+
+ assign prio23_wd = reg_wdata[1:0];
+ assign prio24_we = addr_hit[24] & reg_we & !reg_error;
+
+ assign prio24_wd = reg_wdata[1:0];
+ assign prio25_we = addr_hit[25] & reg_we & !reg_error;
+
+ assign prio25_wd = reg_wdata[1:0];
+ assign prio26_we = addr_hit[26] & reg_we & !reg_error;
+
+ assign prio26_wd = reg_wdata[1:0];
+ assign prio27_we = addr_hit[27] & reg_we & !reg_error;
+
+ assign prio27_wd = reg_wdata[1:0];
+ assign prio28_we = addr_hit[28] & reg_we & !reg_error;
+
+ assign prio28_wd = reg_wdata[1:0];
+ assign prio29_we = addr_hit[29] & reg_we & !reg_error;
+
+ assign prio29_wd = reg_wdata[1:0];
+ assign prio30_we = addr_hit[30] & reg_we & !reg_error;
+
+ assign prio30_wd = reg_wdata[1:0];
+ assign prio31_we = addr_hit[31] & reg_we & !reg_error;
+
+ assign prio31_wd = reg_wdata[1:0];
+ assign prio32_we = addr_hit[32] & reg_we & !reg_error;
+
+ assign prio32_wd = reg_wdata[1:0];
+ assign prio33_we = addr_hit[33] & reg_we & !reg_error;
+
+ assign prio33_wd = reg_wdata[1:0];
+ assign prio34_we = addr_hit[34] & reg_we & !reg_error;
+
+ assign prio34_wd = reg_wdata[1:0];
+ assign prio35_we = addr_hit[35] & reg_we & !reg_error;
+
+ assign prio35_wd = reg_wdata[1:0];
+ assign prio36_we = addr_hit[36] & reg_we & !reg_error;
+
+ assign prio36_wd = reg_wdata[1:0];
+ assign prio37_we = addr_hit[37] & reg_we & !reg_error;
+
+ assign prio37_wd = reg_wdata[1:0];
+ assign prio38_we = addr_hit[38] & reg_we & !reg_error;
+
+ assign prio38_wd = reg_wdata[1:0];
+ assign prio39_we = addr_hit[39] & reg_we & !reg_error;
+
+ assign prio39_wd = reg_wdata[1:0];
+ assign prio40_we = addr_hit[40] & reg_we & !reg_error;
+
+ assign prio40_wd = reg_wdata[1:0];
+ assign prio41_we = addr_hit[41] & reg_we & !reg_error;
+
+ assign prio41_wd = reg_wdata[1:0];
+ assign prio42_we = addr_hit[42] & reg_we & !reg_error;
+
+ assign prio42_wd = reg_wdata[1:0];
+ assign ie0_0_we = addr_hit[45] & reg_we & !reg_error;
+
+ assign ie0_0_e_0_wd = reg_wdata[0];
+
+ assign ie0_0_e_1_wd = reg_wdata[1];
+
+ assign ie0_0_e_2_wd = reg_wdata[2];
+
+ assign ie0_0_e_3_wd = reg_wdata[3];
+
+ assign ie0_0_e_4_wd = reg_wdata[4];
+
+ assign ie0_0_e_5_wd = reg_wdata[5];
+
+ assign ie0_0_e_6_wd = reg_wdata[6];
+
+ assign ie0_0_e_7_wd = reg_wdata[7];
+
+ assign ie0_0_e_8_wd = reg_wdata[8];
+
+ assign ie0_0_e_9_wd = reg_wdata[9];
+
+ assign ie0_0_e_10_wd = reg_wdata[10];
+
+ assign ie0_0_e_11_wd = reg_wdata[11];
+
+ assign ie0_0_e_12_wd = reg_wdata[12];
+
+ assign ie0_0_e_13_wd = reg_wdata[13];
+
+ assign ie0_0_e_14_wd = reg_wdata[14];
+
+ assign ie0_0_e_15_wd = reg_wdata[15];
+
+ assign ie0_0_e_16_wd = reg_wdata[16];
+
+ assign ie0_0_e_17_wd = reg_wdata[17];
+
+ assign ie0_0_e_18_wd = reg_wdata[18];
+
+ assign ie0_0_e_19_wd = reg_wdata[19];
+
+ assign ie0_0_e_20_wd = reg_wdata[20];
+
+ assign ie0_0_e_21_wd = reg_wdata[21];
+
+ assign ie0_0_e_22_wd = reg_wdata[22];
+
+ assign ie0_0_e_23_wd = reg_wdata[23];
+
+ assign ie0_0_e_24_wd = reg_wdata[24];
+
+ assign ie0_0_e_25_wd = reg_wdata[25];
+
+ assign ie0_0_e_26_wd = reg_wdata[26];
+
+ assign ie0_0_e_27_wd = reg_wdata[27];
+
+ assign ie0_0_e_28_wd = reg_wdata[28];
+
+ assign ie0_0_e_29_wd = reg_wdata[29];
+
+ assign ie0_0_e_30_wd = reg_wdata[30];
+
+ assign ie0_0_e_31_wd = reg_wdata[31];
+ assign ie0_1_we = addr_hit[46] & reg_we & !reg_error;
+
+ assign ie0_1_e_32_wd = reg_wdata[0];
+
+ assign ie0_1_e_33_wd = reg_wdata[1];
+
+ assign ie0_1_e_34_wd = reg_wdata[2];
+
+ assign ie0_1_e_35_wd = reg_wdata[3];
+
+ assign ie0_1_e_36_wd = reg_wdata[4];
+
+ assign ie0_1_e_37_wd = reg_wdata[5];
+
+ assign ie0_1_e_38_wd = reg_wdata[6];
+
+ assign ie0_1_e_39_wd = reg_wdata[7];
+
+ assign ie0_1_e_40_wd = reg_wdata[8];
+
+ assign ie0_1_e_41_wd = reg_wdata[9];
+
+ assign ie0_1_e_42_wd = reg_wdata[10];
+ assign threshold0_we = addr_hit[47] & reg_we & !reg_error;
+
+ assign threshold0_wd = reg_wdata[1:0];
+ assign cc0_re = addr_hit[48] & reg_re & !reg_error;
+ assign cc0_we = addr_hit[48] & reg_we & !reg_error;
+
+ assign cc0_wd = reg_wdata[5:0];
+ assign msip0_we = addr_hit[49] & reg_we & !reg_error;
+
+ assign msip0_wd = reg_wdata[0];
+ assign alert_test_we = addr_hit[50] & reg_we & !reg_error;
+
+ assign alert_test_wd = reg_wdata[0];
+
+ // Assign write-enables to checker logic vector.
+ always_comb begin
+ reg_we_check = '0;
+ reg_we_check[0] = prio0_we;
+ reg_we_check[1] = prio1_we;
+ reg_we_check[2] = prio2_we;
+ reg_we_check[3] = prio3_we;
+ reg_we_check[4] = prio4_we;
+ reg_we_check[5] = prio5_we;
+ reg_we_check[6] = prio6_we;
+ reg_we_check[7] = prio7_we;
+ reg_we_check[8] = prio8_we;
+ reg_we_check[9] = prio9_we;
+ reg_we_check[10] = prio10_we;
+ reg_we_check[11] = prio11_we;
+ reg_we_check[12] = prio12_we;
+ reg_we_check[13] = prio13_we;
+ reg_we_check[14] = prio14_we;
+ reg_we_check[15] = prio15_we;
+ reg_we_check[16] = prio16_we;
+ reg_we_check[17] = prio17_we;
+ reg_we_check[18] = prio18_we;
+ reg_we_check[19] = prio19_we;
+ reg_we_check[20] = prio20_we;
+ reg_we_check[21] = prio21_we;
+ reg_we_check[22] = prio22_we;
+ reg_we_check[23] = prio23_we;
+ reg_we_check[24] = prio24_we;
+ reg_we_check[25] = prio25_we;
+ reg_we_check[26] = prio26_we;
+ reg_we_check[27] = prio27_we;
+ reg_we_check[28] = prio28_we;
+ reg_we_check[29] = prio29_we;
+ reg_we_check[30] = prio30_we;
+ reg_we_check[31] = prio31_we;
+ reg_we_check[32] = prio32_we;
+ reg_we_check[33] = prio33_we;
+ reg_we_check[34] = prio34_we;
+ reg_we_check[35] = prio35_we;
+ reg_we_check[36] = prio36_we;
+ reg_we_check[37] = prio37_we;
+ reg_we_check[38] = prio38_we;
+ reg_we_check[39] = prio39_we;
+ reg_we_check[40] = prio40_we;
+ reg_we_check[41] = prio41_we;
+ reg_we_check[42] = prio42_we;
+ reg_we_check[43] = 1'b0;
+ reg_we_check[44] = 1'b0;
+ reg_we_check[45] = ie0_0_we;
+ reg_we_check[46] = ie0_1_we;
+ reg_we_check[47] = threshold0_we;
+ reg_we_check[48] = cc0_we;
+ reg_we_check[49] = msip0_we;
+ reg_we_check[50] = alert_test_we;
+ end
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[1:0] = prio0_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[1:0] = prio1_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[1:0] = prio2_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[1:0] = prio3_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[1:0] = prio4_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[1:0] = prio5_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[1:0] = prio6_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[1:0] = prio7_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[1:0] = prio8_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[1:0] = prio9_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[1:0] = prio10_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[1:0] = prio11_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[1:0] = prio12_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[1:0] = prio13_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[1:0] = prio14_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[1:0] = prio15_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[1:0] = prio16_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[1:0] = prio17_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[1:0] = prio18_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[1:0] = prio19_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[1:0] = prio20_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[1:0] = prio21_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[1:0] = prio22_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[1:0] = prio23_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[1:0] = prio24_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[1:0] = prio25_qs;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[1:0] = prio26_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[1:0] = prio27_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[1:0] = prio28_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[1:0] = prio29_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[1:0] = prio30_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[1:0] = prio31_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[1:0] = prio32_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[1:0] = prio33_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[1:0] = prio34_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[1:0] = prio35_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[1:0] = prio36_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[1:0] = prio37_qs;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[1:0] = prio38_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[1:0] = prio39_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[1:0] = prio40_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[1:0] = prio41_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[1:0] = prio42_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[0] = ip_0_p_0_qs;
+ reg_rdata_next[1] = ip_0_p_1_qs;
+ reg_rdata_next[2] = ip_0_p_2_qs;
+ reg_rdata_next[3] = ip_0_p_3_qs;
+ reg_rdata_next[4] = ip_0_p_4_qs;
+ reg_rdata_next[5] = ip_0_p_5_qs;
+ reg_rdata_next[6] = ip_0_p_6_qs;
+ reg_rdata_next[7] = ip_0_p_7_qs;
+ reg_rdata_next[8] = ip_0_p_8_qs;
+ reg_rdata_next[9] = ip_0_p_9_qs;
+ reg_rdata_next[10] = ip_0_p_10_qs;
+ reg_rdata_next[11] = ip_0_p_11_qs;
+ reg_rdata_next[12] = ip_0_p_12_qs;
+ reg_rdata_next[13] = ip_0_p_13_qs;
+ reg_rdata_next[14] = ip_0_p_14_qs;
+ reg_rdata_next[15] = ip_0_p_15_qs;
+ reg_rdata_next[16] = ip_0_p_16_qs;
+ reg_rdata_next[17] = ip_0_p_17_qs;
+ reg_rdata_next[18] = ip_0_p_18_qs;
+ reg_rdata_next[19] = ip_0_p_19_qs;
+ reg_rdata_next[20] = ip_0_p_20_qs;
+ reg_rdata_next[21] = ip_0_p_21_qs;
+ reg_rdata_next[22] = ip_0_p_22_qs;
+ reg_rdata_next[23] = ip_0_p_23_qs;
+ reg_rdata_next[24] = ip_0_p_24_qs;
+ reg_rdata_next[25] = ip_0_p_25_qs;
+ reg_rdata_next[26] = ip_0_p_26_qs;
+ reg_rdata_next[27] = ip_0_p_27_qs;
+ reg_rdata_next[28] = ip_0_p_28_qs;
+ reg_rdata_next[29] = ip_0_p_29_qs;
+ reg_rdata_next[30] = ip_0_p_30_qs;
+ reg_rdata_next[31] = ip_0_p_31_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[0] = ip_1_p_32_qs;
+ reg_rdata_next[1] = ip_1_p_33_qs;
+ reg_rdata_next[2] = ip_1_p_34_qs;
+ reg_rdata_next[3] = ip_1_p_35_qs;
+ reg_rdata_next[4] = ip_1_p_36_qs;
+ reg_rdata_next[5] = ip_1_p_37_qs;
+ reg_rdata_next[6] = ip_1_p_38_qs;
+ reg_rdata_next[7] = ip_1_p_39_qs;
+ reg_rdata_next[8] = ip_1_p_40_qs;
+ reg_rdata_next[9] = ip_1_p_41_qs;
+ reg_rdata_next[10] = ip_1_p_42_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[0] = ie0_0_e_0_qs;
+ reg_rdata_next[1] = ie0_0_e_1_qs;
+ reg_rdata_next[2] = ie0_0_e_2_qs;
+ reg_rdata_next[3] = ie0_0_e_3_qs;
+ reg_rdata_next[4] = ie0_0_e_4_qs;
+ reg_rdata_next[5] = ie0_0_e_5_qs;
+ reg_rdata_next[6] = ie0_0_e_6_qs;
+ reg_rdata_next[7] = ie0_0_e_7_qs;
+ reg_rdata_next[8] = ie0_0_e_8_qs;
+ reg_rdata_next[9] = ie0_0_e_9_qs;
+ reg_rdata_next[10] = ie0_0_e_10_qs;
+ reg_rdata_next[11] = ie0_0_e_11_qs;
+ reg_rdata_next[12] = ie0_0_e_12_qs;
+ reg_rdata_next[13] = ie0_0_e_13_qs;
+ reg_rdata_next[14] = ie0_0_e_14_qs;
+ reg_rdata_next[15] = ie0_0_e_15_qs;
+ reg_rdata_next[16] = ie0_0_e_16_qs;
+ reg_rdata_next[17] = ie0_0_e_17_qs;
+ reg_rdata_next[18] = ie0_0_e_18_qs;
+ reg_rdata_next[19] = ie0_0_e_19_qs;
+ reg_rdata_next[20] = ie0_0_e_20_qs;
+ reg_rdata_next[21] = ie0_0_e_21_qs;
+ reg_rdata_next[22] = ie0_0_e_22_qs;
+ reg_rdata_next[23] = ie0_0_e_23_qs;
+ reg_rdata_next[24] = ie0_0_e_24_qs;
+ reg_rdata_next[25] = ie0_0_e_25_qs;
+ reg_rdata_next[26] = ie0_0_e_26_qs;
+ reg_rdata_next[27] = ie0_0_e_27_qs;
+ reg_rdata_next[28] = ie0_0_e_28_qs;
+ reg_rdata_next[29] = ie0_0_e_29_qs;
+ reg_rdata_next[30] = ie0_0_e_30_qs;
+ reg_rdata_next[31] = ie0_0_e_31_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[0] = ie0_1_e_32_qs;
+ reg_rdata_next[1] = ie0_1_e_33_qs;
+ reg_rdata_next[2] = ie0_1_e_34_qs;
+ reg_rdata_next[3] = ie0_1_e_35_qs;
+ reg_rdata_next[4] = ie0_1_e_36_qs;
+ reg_rdata_next[5] = ie0_1_e_37_qs;
+ reg_rdata_next[6] = ie0_1_e_38_qs;
+ reg_rdata_next[7] = ie0_1_e_39_qs;
+ reg_rdata_next[8] = ie0_1_e_40_qs;
+ reg_rdata_next[9] = ie0_1_e_41_qs;
+ reg_rdata_next[10] = ie0_1_e_42_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[1:0] = threshold0_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[5:0] = cc0_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[0] = msip0_qs;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // shadow busy
+ logic shadow_busy;
+ assign shadow_busy = 1'b0;
+
+ // register busy
+ assign reg_busy = shadow_busy;
+
+ // Unused signal tieoff
+
+ // wdata / byte enable are not always fully used
+ // add a blanket unused statement to handle lint waivers
+ logic unused_wdata;
+ logic unused_be;
+ assign unused_wdata = ^reg_wdata;
+ assign unused_be = ^reg_be;
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ // this is formulated as an assumption such that the FPV testbenches do disprove this
+ // property by mistake
+ //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_target.sv b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_target.sv
new file mode 100644
index 0000000..34d4a14
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rtl/rv_plic_smc_target.sv
@@ -0,0 +1,74 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// RISC-V Platform-Level Interrupt Generator for Target
+//
+// This module basically doing IE & IP based on priority and threshold_i.
+// Keep in mind that increasing MAX_PRIO affects logic size a lot.
+//
+// The module implements a binary tree to find the maximal entry. the solution
+// has O(N) area and O(log(N)) delay complexity, and thus scales well with
+// many input sources.
+//
+
+`include "prim_assert.sv"
+
+module rv_plic_smc_target #(
+ parameter int N_SOURCE = 32,
+ parameter int MAX_PRIO = 7,
+
+ // Local param (Do not change this through parameter
+ localparam int SrcWidth = $clog2(N_SOURCE), // derived parameter
+ localparam int PrioWidth = $clog2(MAX_PRIO+1) // derived parameter
+) (
+ input clk_i,
+ input rst_ni,
+
+ input [N_SOURCE-1:0] ip_i,
+ input [N_SOURCE-1:0] ie_i,
+
+ input [N_SOURCE-1:0][PrioWidth-1:0] prio_i,
+ input [PrioWidth-1:0] threshold_i,
+
+ output logic irq_o,
+ output logic [SrcWidth-1:0] irq_id_o
+);
+
+ // Find maximum value and index using a binary tree implementation.
+ logic max_valid;
+ logic [PrioWidth-1:0] max_value;
+ logic [SrcWidth-1:0] max_idx;
+ prim_max_tree #(
+ .NumSrc(N_SOURCE),
+ .Width(PrioWidth)
+ ) u_prim_max_tree (
+ .clk_i,
+ .rst_ni,
+ .values_i(prio_i),
+ .valid_i(ip_i & ie_i),
+ .max_value_o(max_value),
+ .max_idx_o(max_idx),
+ .max_valid_o(max_valid)
+ );
+
+ logic irq_d, irq_q;
+ logic [SrcWidth-1:0] irq_id_d, irq_id_q;
+
+ assign irq_d = (max_value > threshold_i) ? max_valid : 1'b0;
+ assign irq_id_d = (max_valid) ? max_idx : '0;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin : gen_regs
+ if (!rst_ni) begin
+ irq_q <= 1'b0;
+ irq_id_q <= '0;
+ end else begin
+ irq_q <= irq_d;
+ irq_id_q <= irq_id_d;
+ end
+ end
+
+ assign irq_o = irq_q;
+ assign irq_id_o = irq_id_q;
+
+endmodule
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc.core b/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc.core
new file mode 100644
index 0000000..f674eea
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc.core
@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: lowrisc:opentitan:top_sencha_rv_plic_smc
+description: "RISC-V Platform Interrupt Controller (PLIC)"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:rv_plic_smc_component
+ - lowrisc:ip:tlul
+ - lowrisc:prim:subreg
+ files:
+ - rtl/rv_plic_smc_reg_pkg.sv
+ - rtl/rv_plic_smc_reg_top.sv
+ - rtl/rv_plic_smc.sv
+ file_type: systemVerilogSource
+
+parameters:
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+targets:
+ default: &default_target
+ filesets:
+ - files_rtl
+ toplevel: rv_plic_smc
+
+ lint:
+ <<: *default_target
+ default_tool: verilator
+ parameters:
+ - SYNTHESIS=true
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc_component.core b/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc_component.core
new file mode 100644
index 0000000..d3eacaa
--- /dev/null
+++ b/hw/top_sencha/ip_autogen/rv_plic_smc/rv_plic_smc_component.core
@@ -0,0 +1,51 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:rv_plic_smc_component:0.1"
+description: "RISC-V Platform Interrupt Controller (PLIC)"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:alert
+ - lowrisc:prim:max_tree
+ - lowrisc:prim:flop_2sync
+ - lowrisc:prim:reg_we_check
+ files:
+ - rtl/rv_plic_smc_gateway.sv
+ - rtl/rv_plic_smc_target.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/rv_plic_smc.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ - lint/rv_plic_smc.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/top_sencha/rtl/autogen/chip_sencha_asic.sv b/hw/top_sencha/rtl/autogen/chip_sencha_asic.sv
new file mode 100644
index 0000000..70e0d5c
--- /dev/null
+++ b/hw/top_sencha/rtl/autogen/chip_sencha_asic.sv
@@ -0,0 +1,1306 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+
+module chip_sencha_asic #(
+ parameter bit SecRomCtrlDisableScrambling = 1'b0
+) (
+ // Dedicated Pads
+ inout POR_N, // Manual Pad
+ inout USB_P, // Manual Pad
+ inout USB_N, // Manual Pad
+ `INOUT_AI CC1, // Manual Pad
+ `INOUT_AI CC2, // Manual Pad
+ inout FLASH_TEST_VOLT, // Manual Pad
+ inout FLASH_TEST_MODE0, // Manual Pad
+ inout FLASH_TEST_MODE1, // Manual Pad
+ inout OTP_EXT_VOLT, // Manual Pad
+ inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck
+ inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb
+ inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck
+ inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb
+ inout IOR8, // Dedicated Pad for sysrst_ctrl_aon_ec_rst_l
+ inout IOR9, // Dedicated Pad for sysrst_ctrl_aon_flash_wp_l
+ inout AST_MISC, // Manual Pad
+ inout CLK_EXT, // Manual Pad
+ inout CLK_BYP, // Manual Pad
+ inout CLK_200K, // Manual Pad
+ inout XTAL_IN, // Manual Pad
+ inout XTAL_OUT, // Manual Pad
+
+ // Muxed Pads
+ inout IOA0, // MIO Pad 0
+ inout IOA1, // MIO Pad 1
+ `INOUT_AO IOA2, // MIO Pad 2
+ `INOUT_AO IOA3, // MIO Pad 3
+ inout IOA4, // MIO Pad 4
+ inout IOA5, // MIO Pad 5
+ inout IOA6, // MIO Pad 6
+ inout IOA7, // MIO Pad 7
+ inout IOA8, // MIO Pad 8
+ inout IOB0, // MIO Pad 9
+ inout IOB1, // MIO Pad 10
+ inout IOB2, // MIO Pad 11
+ inout IOB3, // MIO Pad 12
+ inout IOB4, // MIO Pad 13
+ inout IOB5, // MIO Pad 14
+ inout IOB6, // MIO Pad 15
+ inout IOB7, // MIO Pad 16
+ inout IOB8, // MIO Pad 17
+ inout IOB9, // MIO Pad 18
+ inout IOB10, // MIO Pad 19
+ inout IOB11, // MIO Pad 20
+ inout IOB12, // MIO Pad 21
+ inout IOC0, // MIO Pad 22
+ inout IOC1, // MIO Pad 23
+ inout IOC2, // MIO Pad 24
+ inout IOC3, // MIO Pad 25
+ inout IOC4, // MIO Pad 26
+ inout IOC5, // MIO Pad 27
+ inout IOC6, // MIO Pad 28
+ inout IOC7, // MIO Pad 29
+ inout IOC8, // MIO Pad 30
+ inout IOC9, // MIO Pad 31
+ inout IOC10, // MIO Pad 32
+ inout IOC11, // MIO Pad 33
+ inout IOC12, // MIO Pad 34
+ inout IOR0, // MIO Pad 35
+ inout IOR1, // MIO Pad 36
+ inout IOR2, // MIO Pad 37
+ inout IOR3, // MIO Pad 38
+ inout IOR4, // MIO Pad 39
+ inout IOR5, // MIO Pad 40
+ inout IOR6, // MIO Pad 41
+ inout IOR7, // MIO Pad 42
+ inout IOR10, // MIO Pad 43
+ inout IOR11, // MIO Pad 44
+ inout IOR12, // MIO Pad 45
+ inout IOR13, // MIO Pad 46
+ inout IOD0, // MIO Pad 47
+ inout IOD1, // MIO Pad 48
+ inout IOD2, // MIO Pad 49
+ inout IOD3, // MIO Pad 50
+ inout IOD4, // MIO Pad 51
+ inout IOD5 // MIO Pad 52
+);
+
+ import top_sencha_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+
+ ////////////////////////////
+ // Special Signal Indices //
+ ////////////////////////////
+
+ localparam int Tap0PadIdx = 30;
+ localparam int Tap1PadIdx = 27;
+ localparam int Dft0PadIdx = 25;
+ localparam int Dft1PadIdx = 26;
+ localparam int TckPadIdx = 38;
+ localparam int TmsPadIdx = 35;
+ localparam int TrstNPadIdx = 39;
+ localparam int TdiPadIdx = 37;
+ localparam int TdoPadIdx = 36;
+
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevUsbDp,
+ usb_dn_idx: DioUsbdevUsbDn,
+ usb_sense_idx: MioInUsbdevSense,
+ // Pad types for attribute WARL behavior
+ dio_pad_type: {
+ BidirStd, // DIO spi_host0_csb
+ BidirStd, // DIO spi_host0_sck
+ InputStd, // DIO spi_device_csb
+ InputStd, // DIO spi_device_sck
+ BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l
+ BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO usbdev_usb_dn
+ BidirStd // DIO usbdev_usb_dp
+ },
+ mio_pad_type: {
+ BidirStd, // MIO Pad 52
+ BidirStd, // MIO Pad 51
+ BidirStd, // MIO Pad 50
+ BidirStd, // MIO Pad 49
+ BidirStd, // MIO Pad 48
+ BidirStd, // MIO Pad 47
+ BidirOd, // MIO Pad 46
+ BidirOd, // MIO Pad 45
+ BidirOd, // MIO Pad 44
+ BidirOd, // MIO Pad 43
+ BidirStd, // MIO Pad 42
+ BidirStd, // MIO Pad 41
+ BidirStd, // MIO Pad 40
+ BidirStd, // MIO Pad 39
+ BidirStd, // MIO Pad 38
+ BidirStd, // MIO Pad 37
+ BidirStd, // MIO Pad 36
+ BidirStd, // MIO Pad 35
+ BidirOd, // MIO Pad 34
+ BidirOd, // MIO Pad 33
+ BidirOd, // MIO Pad 32
+ BidirStd, // MIO Pad 31
+ BidirStd, // MIO Pad 30
+ BidirStd, // MIO Pad 29
+ BidirStd, // MIO Pad 28
+ BidirStd, // MIO Pad 27
+ BidirStd, // MIO Pad 26
+ BidirStd, // MIO Pad 25
+ BidirStd, // MIO Pad 24
+ BidirStd, // MIO Pad 23
+ BidirStd, // MIO Pad 22
+ BidirOd, // MIO Pad 21
+ BidirOd, // MIO Pad 20
+ BidirOd, // MIO Pad 19
+ BidirOd, // MIO Pad 18
+ BidirStd, // MIO Pad 17
+ BidirStd, // MIO Pad 16
+ BidirStd, // MIO Pad 15
+ BidirStd, // MIO Pad 14
+ BidirStd, // MIO Pad 13
+ BidirStd, // MIO Pad 12
+ BidirStd, // MIO Pad 11
+ BidirStd, // MIO Pad 10
+ BidirStd, // MIO Pad 9
+ BidirOd, // MIO Pad 8
+ BidirOd, // MIO Pad 7
+ BidirOd, // MIO Pad 6
+ BidirStd, // MIO Pad 5
+ BidirStd, // MIO Pad 4
+ BidirStd, // MIO Pad 3
+ BidirStd, // MIO Pad 2
+ BidirStd, // MIO Pad 1
+ BidirStd // MIO Pad 0
+ }
+ };
+
+ ////////////////////////
+ // Signal definitions //
+ ////////////////////////
+
+
+ pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+ pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+ logic unused_mio_in_raw;
+ assign unused_mio_in_raw = ^mio_in_raw;
+
+ // Manual pads
+ logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
+ logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
+ logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
+ logic manual_in_cc1, manual_out_cc1, manual_oe_cc1;
+ logic manual_in_cc2, manual_out_cc2, manual_oe_cc2;
+ logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt;
+ logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0;
+ logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1;
+ logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt;
+ logic manual_in_ast_misc, manual_out_ast_misc, manual_oe_ast_misc;
+ logic manual_in_clk_ext, manual_out_clk_ext, manual_oe_clk_ext;
+ logic manual_in_clk_byp, manual_out_clk_byp, manual_oe_clk_byp;
+ logic manual_in_clk_200k, manual_out_clk_200k, manual_oe_clk_200k;
+ logic manual_in_xtal_in, manual_out_xtal_in, manual_oe_xtal_in;
+ logic manual_in_xtal_out, manual_out_xtal_out, manual_oe_xtal_out;
+
+ pad_attr_t manual_attr_por_n;
+ pad_attr_t manual_attr_usb_p;
+ pad_attr_t manual_attr_usb_n;
+ pad_attr_t manual_attr_cc1;
+ pad_attr_t manual_attr_cc2;
+ pad_attr_t manual_attr_flash_test_volt;
+ pad_attr_t manual_attr_flash_test_mode0;
+ pad_attr_t manual_attr_flash_test_mode1;
+ pad_attr_t manual_attr_otp_ext_volt;
+ pad_attr_t manual_attr_ast_misc;
+ pad_attr_t manual_attr_clk_ext;
+ pad_attr_t manual_attr_clk_byp;
+ pad_attr_t manual_attr_clk_200k;
+ pad_attr_t manual_attr_xtal_in;
+ pad_attr_t manual_attr_xtal_out;
+
+
+ //////////////////////
+ // Padring Instance //
+ //////////////////////
+
+ ast_pkg::ast_clks_t ast_base_clks;
+
+ // AST signals needed in padring
+ logic scan_rst_n;
+ prim_mubi_pkg::mubi4_t scanmode;
+
+ padring #(
+ // Padring specific counts may differ from pinmux config due
+ // to custom, stubbed or added pads.
+ .NDioPads(29),
+ .NMioPads(53),
+ .PhysicalPads(1),
+ .NIoBanks(int'(IoBankCount)),
+ .DioScanRole ({
+ scan_role_pkg::DioPadXtalOutScanRole,
+ scan_role_pkg::DioPadXtalInScanRole,
+ scan_role_pkg::DioPadClk200kScanRole,
+ scan_role_pkg::DioPadClkBypScanRole,
+ scan_role_pkg::DioPadClkExtScanRole,
+ scan_role_pkg::DioPadAstMiscScanRole,
+ scan_role_pkg::DioPadIor9ScanRole,
+ scan_role_pkg::DioPadIor8ScanRole,
+ scan_role_pkg::DioPadSpiDevCsLScanRole,
+ scan_role_pkg::DioPadSpiDevClkScanRole,
+ scan_role_pkg::DioPadSpiDevD3ScanRole,
+ scan_role_pkg::DioPadSpiDevD2ScanRole,
+ scan_role_pkg::DioPadSpiDevD1ScanRole,
+ scan_role_pkg::DioPadSpiDevD0ScanRole,
+ scan_role_pkg::DioPadSpiHostCsLScanRole,
+ scan_role_pkg::DioPadSpiHostClkScanRole,
+ scan_role_pkg::DioPadSpiHostD3ScanRole,
+ scan_role_pkg::DioPadSpiHostD2ScanRole,
+ scan_role_pkg::DioPadSpiHostD1ScanRole,
+ scan_role_pkg::DioPadSpiHostD0ScanRole,
+ scan_role_pkg::DioPadOtpExtVoltScanRole,
+ scan_role_pkg::DioPadFlashTestMode1ScanRole,
+ scan_role_pkg::DioPadFlashTestMode0ScanRole,
+ scan_role_pkg::DioPadFlashTestVoltScanRole,
+ scan_role_pkg::DioPadCc2ScanRole,
+ scan_role_pkg::DioPadCc1ScanRole,
+ scan_role_pkg::DioPadUsbNScanRole,
+ scan_role_pkg::DioPadUsbPScanRole,
+ scan_role_pkg::DioPadPorNScanRole
+ }),
+ .MioScanRole ({
+ scan_role_pkg::MioPadIod5ScanRole,
+ scan_role_pkg::MioPadIod4ScanRole,
+ scan_role_pkg::MioPadIod3ScanRole,
+ scan_role_pkg::MioPadIod2ScanRole,
+ scan_role_pkg::MioPadIod1ScanRole,
+ scan_role_pkg::MioPadIod0ScanRole,
+ scan_role_pkg::MioPadIor13ScanRole,
+ scan_role_pkg::MioPadIor12ScanRole,
+ scan_role_pkg::MioPadIor11ScanRole,
+ scan_role_pkg::MioPadIor10ScanRole,
+ scan_role_pkg::MioPadIor7ScanRole,
+ scan_role_pkg::MioPadIor6ScanRole,
+ scan_role_pkg::MioPadIor5ScanRole,
+ scan_role_pkg::MioPadIor4ScanRole,
+ scan_role_pkg::MioPadIor3ScanRole,
+ scan_role_pkg::MioPadIor2ScanRole,
+ scan_role_pkg::MioPadIor1ScanRole,
+ scan_role_pkg::MioPadIor0ScanRole,
+ scan_role_pkg::MioPadIoc12ScanRole,
+ scan_role_pkg::MioPadIoc11ScanRole,
+ scan_role_pkg::MioPadIoc10ScanRole,
+ scan_role_pkg::MioPadIoc9ScanRole,
+ scan_role_pkg::MioPadIoc8ScanRole,
+ scan_role_pkg::MioPadIoc7ScanRole,
+ scan_role_pkg::MioPadIoc6ScanRole,
+ scan_role_pkg::MioPadIoc5ScanRole,
+ scan_role_pkg::MioPadIoc4ScanRole,
+ scan_role_pkg::MioPadIoc3ScanRole,
+ scan_role_pkg::MioPadIoc2ScanRole,
+ scan_role_pkg::MioPadIoc1ScanRole,
+ scan_role_pkg::MioPadIoc0ScanRole,
+ scan_role_pkg::MioPadIob12ScanRole,
+ scan_role_pkg::MioPadIob11ScanRole,
+ scan_role_pkg::MioPadIob10ScanRole,
+ scan_role_pkg::MioPadIob9ScanRole,
+ scan_role_pkg::MioPadIob8ScanRole,
+ scan_role_pkg::MioPadIob7ScanRole,
+ scan_role_pkg::MioPadIob6ScanRole,
+ scan_role_pkg::MioPadIob5ScanRole,
+ scan_role_pkg::MioPadIob4ScanRole,
+ scan_role_pkg::MioPadIob3ScanRole,
+ scan_role_pkg::MioPadIob2ScanRole,
+ scan_role_pkg::MioPadIob1ScanRole,
+ scan_role_pkg::MioPadIob0ScanRole,
+ scan_role_pkg::MioPadIoa8ScanRole,
+ scan_role_pkg::MioPadIoa7ScanRole,
+ scan_role_pkg::MioPadIoa6ScanRole,
+ scan_role_pkg::MioPadIoa5ScanRole,
+ scan_role_pkg::MioPadIoa4ScanRole,
+ scan_role_pkg::MioPadIoa3ScanRole,
+ scan_role_pkg::MioPadIoa2ScanRole,
+ scan_role_pkg::MioPadIoa1ScanRole,
+ scan_role_pkg::MioPadIoa0ScanRole
+ }),
+ .DioPadBank ({
+ IoBankVcc, // XTAL_OUT
+ IoBankVcc, // XTAL_IN
+ IoBankVcc, // CLK_200K
+ IoBankVcc, // CLK_BYP
+ IoBankVcc, // CLK_EXT
+ IoBankVcc, // AST_MISC
+ IoBankVcc, // IOR9
+ IoBankVcc, // IOR8
+ IoBankVioa, // SPI_DEV_CS_L
+ IoBankVioa, // SPI_DEV_CLK
+ IoBankVioa, // SPI_DEV_D3
+ IoBankVioa, // SPI_DEV_D2
+ IoBankVioa, // SPI_DEV_D1
+ IoBankVioa, // SPI_DEV_D0
+ IoBankVioa, // SPI_HOST_CS_L
+ IoBankVioa, // SPI_HOST_CLK
+ IoBankVioa, // SPI_HOST_D3
+ IoBankVioa, // SPI_HOST_D2
+ IoBankVioa, // SPI_HOST_D1
+ IoBankVioa, // SPI_HOST_D0
+ IoBankVcc, // OTP_EXT_VOLT
+ IoBankVcc, // FLASH_TEST_MODE1
+ IoBankVcc, // FLASH_TEST_MODE0
+ IoBankVcc, // FLASH_TEST_VOLT
+ IoBankAvcc, // CC2
+ IoBankAvcc, // CC1
+ IoBankVcc, // USB_N
+ IoBankVcc, // USB_P
+ IoBankVcc // POR_N
+ }),
+ .MioPadBank ({
+ IoBankVcc, // IOD5
+ IoBankVcc, // IOD4
+ IoBankVcc, // IOD3
+ IoBankVcc, // IOD2
+ IoBankVcc, // IOD1
+ IoBankVcc, // IOD0
+ IoBankVcc, // IOR13
+ IoBankVcc, // IOR12
+ IoBankVcc, // IOR11
+ IoBankVcc, // IOR10
+ IoBankVcc, // IOR7
+ IoBankVcc, // IOR6
+ IoBankVcc, // IOR5
+ IoBankVcc, // IOR4
+ IoBankVcc, // IOR3
+ IoBankVcc, // IOR2
+ IoBankVcc, // IOR1
+ IoBankVcc, // IOR0
+ IoBankVcc, // IOC12
+ IoBankVcc, // IOC11
+ IoBankVcc, // IOC10
+ IoBankVcc, // IOC9
+ IoBankVcc, // IOC8
+ IoBankVcc, // IOC7
+ IoBankVcc, // IOC6
+ IoBankVcc, // IOC5
+ IoBankVcc, // IOC4
+ IoBankVcc, // IOC3
+ IoBankVcc, // IOC2
+ IoBankVcc, // IOC1
+ IoBankVcc, // IOC0
+ IoBankViob, // IOB12
+ IoBankViob, // IOB11
+ IoBankViob, // IOB10
+ IoBankViob, // IOB9
+ IoBankViob, // IOB8
+ IoBankViob, // IOB7
+ IoBankViob, // IOB6
+ IoBankViob, // IOB5
+ IoBankViob, // IOB4
+ IoBankViob, // IOB3
+ IoBankViob, // IOB2
+ IoBankViob, // IOB1
+ IoBankViob, // IOB0
+ IoBankVioa, // IOA8
+ IoBankVioa, // IOA7
+ IoBankVioa, // IOA6
+ IoBankVioa, // IOA5
+ IoBankVioa, // IOA4
+ IoBankVioa, // IOA3
+ IoBankVioa, // IOA2
+ IoBankVioa, // IOA1
+ IoBankVioa // IOA0
+ }),
+ .DioPadType ({
+ AnalogIn0, // XTAL_OUT
+ AnalogIn0, // XTAL_IN
+ AnalogIn0, // CLK_200K
+ InputStd, // CLK_BYP
+ AnalogIn0, // CLK_EXT
+ InputStd, // AST_MISC
+ BidirOd, // IOR9
+ BidirOd, // IOR8
+ InputStd, // SPI_DEV_CS_L
+ InputStd, // SPI_DEV_CLK
+ BidirStd, // SPI_DEV_D3
+ BidirStd, // SPI_DEV_D2
+ BidirStd, // SPI_DEV_D1
+ BidirStd, // SPI_DEV_D0
+ BidirStd, // SPI_HOST_CS_L
+ BidirStd, // SPI_HOST_CLK
+ BidirStd, // SPI_HOST_D3
+ BidirStd, // SPI_HOST_D2
+ BidirStd, // SPI_HOST_D1
+ BidirStd, // SPI_HOST_D0
+ AnalogIn1, // OTP_EXT_VOLT
+ InputStd, // FLASH_TEST_MODE1
+ InputStd, // FLASH_TEST_MODE0
+ AnalogIn0, // FLASH_TEST_VOLT
+ InputStd, // CC2
+ InputStd, // CC1
+ DualBidirTol, // USB_N
+ DualBidirTol, // USB_P
+ InputStd // POR_N
+ }),
+ .MioPadType ({
+ BidirStd, // IOD5
+ BidirStd, // IOD4
+ BidirStd, // IOD3
+ BidirStd, // IOD2
+ BidirStd, // IOD1
+ BidirStd, // IOD0
+ BidirOd, // IOR13
+ BidirOd, // IOR12
+ BidirOd, // IOR11
+ BidirOd, // IOR10
+ BidirStd, // IOR7
+ BidirStd, // IOR6
+ BidirStd, // IOR5
+ BidirStd, // IOR4
+ BidirStd, // IOR3
+ BidirStd, // IOR2
+ BidirStd, // IOR1
+ BidirStd, // IOR0
+ BidirOd, // IOC12
+ BidirOd, // IOC11
+ BidirOd, // IOC10
+ BidirStd, // IOC9
+ BidirStd, // IOC8
+ BidirStd, // IOC7
+ BidirStd, // IOC6
+ BidirStd, // IOC5
+ BidirStd, // IOC4
+ BidirStd, // IOC3
+ BidirStd, // IOC2
+ BidirStd, // IOC1
+ BidirStd, // IOC0
+ BidirOd, // IOB12
+ BidirOd, // IOB11
+ BidirOd, // IOB10
+ BidirOd, // IOB9
+ BidirStd, // IOB8
+ BidirStd, // IOB7
+ BidirStd, // IOB6
+ BidirStd, // IOB5
+ BidirStd, // IOB4
+ BidirStd, // IOB3
+ BidirStd, // IOB2
+ BidirStd, // IOB1
+ BidirStd, // IOB0
+ BidirOd, // IOA8
+ BidirOd, // IOA7
+ BidirOd, // IOA6
+ BidirStd, // IOA5
+ BidirStd, // IOA4
+ BidirStd, // IOA3
+ BidirStd, // IOA2
+ BidirStd, // IOA1
+ BidirStd // IOA0
+ })
+ ) u_padring (
+ // This is only used for scan and DFT purposes
+ .clk_scan_i ( ast_base_clks.clk_sys ),
+ .scanmode_i ( lc_ctrl_pkg::lc_tx_t'(scanmode) ),
+ .dio_in_raw_o ( ),
+ // Chip IOs
+ .dio_pad_io ({
+ XTAL_OUT,
+ XTAL_IN,
+ CLK_200K,
+ CLK_BYP,
+ CLK_EXT,
+ AST_MISC,
+ IOR9,
+ IOR8,
+ SPI_DEV_CS_L,
+ SPI_DEV_CLK,
+ SPI_DEV_D3,
+ SPI_DEV_D2,
+ SPI_DEV_D1,
+ SPI_DEV_D0,
+ SPI_HOST_CS_L,
+ SPI_HOST_CLK,
+ SPI_HOST_D3,
+ SPI_HOST_D2,
+ SPI_HOST_D1,
+ SPI_HOST_D0,
+ OTP_EXT_VOLT,
+ FLASH_TEST_MODE1,
+ FLASH_TEST_MODE0,
+ FLASH_TEST_VOLT,
+`ifdef ANALOGSIM
+ '0,
+`else
+ CC2,
+`endif
+`ifdef ANALOGSIM
+ '0,
+`else
+ CC1,
+`endif
+ USB_N,
+ USB_P,
+ POR_N
+ }),
+
+ .mio_pad_io ({
+ IOD5,
+ IOD4,
+ IOD3,
+ IOD2,
+ IOD1,
+ IOD0,
+ IOR13,
+ IOR12,
+ IOR11,
+ IOR10,
+ IOR7,
+ IOR6,
+ IOR5,
+ IOR4,
+ IOR3,
+ IOR2,
+ IOR1,
+ IOR0,
+ IOC12,
+ IOC11,
+ IOC10,
+ IOC9,
+ IOC8,
+ IOC7,
+ IOC6,
+ IOC5,
+ IOC4,
+ IOC3,
+ IOC2,
+ IOC1,
+ IOC0,
+ IOB12,
+ IOB11,
+ IOB10,
+ IOB9,
+ IOB8,
+ IOB7,
+ IOB6,
+ IOB5,
+ IOB4,
+ IOB3,
+ IOB2,
+ IOB1,
+ IOB0,
+ IOA8,
+ IOA7,
+ IOA6,
+ IOA5,
+ IOA4,
+`ifdef ANALOGSIM
+ '0,
+`else
+ IOA3,
+`endif
+`ifdef ANALOGSIM
+ '0,
+`else
+ IOA2,
+`endif
+ IOA1,
+ IOA0
+ }),
+
+ // Core-facing
+ .dio_in_o ({
+ manual_in_xtal_out,
+ manual_in_xtal_in,
+ manual_in_clk_200k,
+ manual_in_clk_byp,
+ manual_in_clk_ext,
+ manual_in_ast_misc,
+ dio_in[DioSysrstCtrlAonFlashWpL],
+ dio_in[DioSysrstCtrlAonEcRstL],
+ dio_in[DioSpiDeviceCsb],
+ dio_in[DioSpiDeviceSck],
+ dio_in[DioSpiDeviceSd3],
+ dio_in[DioSpiDeviceSd2],
+ dio_in[DioSpiDeviceSd1],
+ dio_in[DioSpiDeviceSd0],
+ dio_in[DioSpiHost0Csb],
+ dio_in[DioSpiHost0Sck],
+ dio_in[DioSpiHost0Sd3],
+ dio_in[DioSpiHost0Sd2],
+ dio_in[DioSpiHost0Sd1],
+ dio_in[DioSpiHost0Sd0],
+ manual_in_otp_ext_volt,
+ manual_in_flash_test_mode1,
+ manual_in_flash_test_mode0,
+ manual_in_flash_test_volt,
+ manual_in_cc2,
+ manual_in_cc1,
+ manual_in_usb_n,
+ manual_in_usb_p,
+ manual_in_por_n
+ }),
+ .dio_out_i ({
+ manual_out_xtal_out,
+ manual_out_xtal_in,
+ manual_out_clk_200k,
+ manual_out_clk_byp,
+ manual_out_clk_ext,
+ manual_out_ast_misc,
+ dio_out[DioSysrstCtrlAonFlashWpL],
+ dio_out[DioSysrstCtrlAonEcRstL],
+ dio_out[DioSpiDeviceCsb],
+ dio_out[DioSpiDeviceSck],
+ dio_out[DioSpiDeviceSd3],
+ dio_out[DioSpiDeviceSd2],
+ dio_out[DioSpiDeviceSd1],
+ dio_out[DioSpiDeviceSd0],
+ dio_out[DioSpiHost0Csb],
+ dio_out[DioSpiHost0Sck],
+ dio_out[DioSpiHost0Sd3],
+ dio_out[DioSpiHost0Sd2],
+ dio_out[DioSpiHost0Sd1],
+ dio_out[DioSpiHost0Sd0],
+ manual_out_otp_ext_volt,
+ manual_out_flash_test_mode1,
+ manual_out_flash_test_mode0,
+ manual_out_flash_test_volt,
+ manual_out_cc2,
+ manual_out_cc1,
+ manual_out_usb_n,
+ manual_out_usb_p,
+ manual_out_por_n
+ }),
+ .dio_oe_i ({
+ manual_oe_xtal_out,
+ manual_oe_xtal_in,
+ manual_oe_clk_200k,
+ manual_oe_clk_byp,
+ manual_oe_clk_ext,
+ manual_oe_ast_misc,
+ dio_oe[DioSysrstCtrlAonFlashWpL],
+ dio_oe[DioSysrstCtrlAonEcRstL],
+ dio_oe[DioSpiDeviceCsb],
+ dio_oe[DioSpiDeviceSck],
+ dio_oe[DioSpiDeviceSd3],
+ dio_oe[DioSpiDeviceSd2],
+ dio_oe[DioSpiDeviceSd1],
+ dio_oe[DioSpiDeviceSd0],
+ dio_oe[DioSpiHost0Csb],
+ dio_oe[DioSpiHost0Sck],
+ dio_oe[DioSpiHost0Sd3],
+ dio_oe[DioSpiHost0Sd2],
+ dio_oe[DioSpiHost0Sd1],
+ dio_oe[DioSpiHost0Sd0],
+ manual_oe_otp_ext_volt,
+ manual_oe_flash_test_mode1,
+ manual_oe_flash_test_mode0,
+ manual_oe_flash_test_volt,
+ manual_oe_cc2,
+ manual_oe_cc1,
+ manual_oe_usb_n,
+ manual_oe_usb_p,
+ manual_oe_por_n
+ }),
+ .dio_attr_i ({
+ manual_attr_xtal_out,
+ manual_attr_xtal_in,
+ manual_attr_clk_200k,
+ manual_attr_clk_byp,
+ manual_attr_clk_ext,
+ manual_attr_ast_misc,
+ dio_attr[DioSysrstCtrlAonFlashWpL],
+ dio_attr[DioSysrstCtrlAonEcRstL],
+ dio_attr[DioSpiDeviceCsb],
+ dio_attr[DioSpiDeviceSck],
+ dio_attr[DioSpiDeviceSd3],
+ dio_attr[DioSpiDeviceSd2],
+ dio_attr[DioSpiDeviceSd1],
+ dio_attr[DioSpiDeviceSd0],
+ dio_attr[DioSpiHost0Csb],
+ dio_attr[DioSpiHost0Sck],
+ dio_attr[DioSpiHost0Sd3],
+ dio_attr[DioSpiHost0Sd2],
+ dio_attr[DioSpiHost0Sd1],
+ dio_attr[DioSpiHost0Sd0],
+ manual_attr_otp_ext_volt,
+ manual_attr_flash_test_mode1,
+ manual_attr_flash_test_mode0,
+ manual_attr_flash_test_volt,
+ manual_attr_cc2,
+ manual_attr_cc1,
+ manual_attr_usb_n,
+ manual_attr_usb_p,
+ manual_attr_por_n
+ }),
+
+ .mio_in_o (mio_in[52:0]),
+ .mio_out_i (mio_out[52:0]),
+ .mio_oe_i (mio_oe[52:0]),
+ .mio_attr_i (mio_attr[52:0]),
+ .mio_in_raw_o (mio_in_raw[52:0])
+ );
+
+
+
+ //////////////////////////////////
+ // AST - Common for all targets //
+ //////////////////////////////////
+
+ // pwrmgr interface
+ pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+ // assorted ast status
+ ast_pkg::ast_pwst_t ast_pwst;
+ ast_pkg::ast_pwst_t ast_pwst_h;
+
+ // TLUL interface
+ tlul_pkg::tl_h2d_t base_ast_bus;
+ tlul_pkg::tl_d2h_t ast_base_bus;
+
+ // synchronization clocks / rests
+ clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
+ rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
+
+ // external clock
+ logic ext_clk;
+
+ // monitored clock
+ logic sck_monitor;
+
+ // observe interface
+ logic [7:0] fla_obs;
+ logic [7:0] otp_obs;
+ ast_pkg::ast_obs_ctrl_t obs_ctrl;
+
+ // otp power sequence
+ otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+ otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+ logic usb_ref_pulse;
+ logic usb_ref_val;
+
+ // adc
+ ast_pkg::adc_ast_req_t adc_req;
+ ast_pkg::adc_ast_rsp_t adc_rsp;
+
+ // entropy source interface
+ // The entropy source pacakge definition should eventually be moved to es
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+ logic es_rng_fips;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+ // alerts interface
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
+
+ // Flash connections
+ prim_mubi_pkg::mubi4_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
+
+ // clock bypass req/ack
+ prim_mubi_pkg::mubi4_t io_clk_byp_req;
+ prim_mubi_pkg::mubi4_t io_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t all_clk_byp_req;
+ prim_mubi_pkg::mubi4_t all_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t hi_speed_sel;
+ prim_mubi_pkg::mubi4_t div_step_down_req;
+
+ // DFT connections
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t dft_en;
+ pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+ // Debug connections
+ logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
+
+ // Jitter enable
+ prim_mubi_pkg::mubi4_t jen;
+
+ // reset domain connections
+ import rstmgr_pkg::PowerDomains;
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
+
+ // Memory configuration connections
+ ast_pkg::spm_rm_t ast_ram_1p_cfg;
+ ast_pkg::spm_rm_t ast_rf_cfg;
+ ast_pkg::spm_rm_t ast_rom_cfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
+
+ prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
+ prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
+ prim_rom_pkg::rom_cfg_t rom_cfg;
+
+ // conversion from ast structure to memory centric structures
+ assign ram_1p_cfg = '{
+ ram_cfg: '{
+ cfg_en: ast_ram_1p_cfg.marg_en,
+ cfg: ast_ram_1p_cfg.marg
+ },
+ rf_cfg: '{
+ cfg_en: ast_rf_cfg.marg_en,
+ cfg: ast_rf_cfg.marg
+ }
+ };
+
+ assign ram_2p_cfg = '{
+ a_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_a,
+ cfg: ast_ram_2p_fcfg.marg_a
+ },
+ a_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_a,
+ cfg: ast_ram_2p_lcfg.marg_a
+ },
+ b_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_b,
+ cfg: ast_ram_2p_fcfg.marg_b
+ },
+ b_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_b,
+ cfg: ast_ram_2p_lcfg.marg_b
+ }
+ };
+
+ assign rom_cfg = '{
+ cfg_en: ast_rom_cfg.marg_en,
+ cfg: ast_rom_cfg.marg
+ };
+
+
+ //////////////////////////////////
+ // AST - Custom for targets //
+ //////////////////////////////////
+
+
+ assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
+
+ logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
+
+ // external clock comes in at a fixed position
+ assign ext_clk = mio_in_raw[MioPadIoc6];
+
+ assign pad2ast = { manual_in_ast_misc,
+ mio_in_raw[MioPadIoc3],
+ mio_in_raw[MioPadIoc2],
+ mio_in_raw[MioPadIoc1],
+ mio_in_raw[MioPadIob2],
+ mio_in_raw[MioPadIob1],
+ mio_in_raw[MioPadIob0],
+ mio_in_raw[MioPadIoa5],
+ mio_in_raw[MioPadIoa4]
+ };
+
+ // AST does not use all clocks / resets forwarded to it
+ logic unused_slow_clk_en;
+ assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
+
+ logic unused_pwr_clamp;
+ assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
+
+ logic usb_diff_rx_obs;
+
+
+ prim_mubi_pkg::mubi4_t ast_init_done;
+
+ ast #(
+ .EntropyStreams(ast_pkg::EntropyStreams),
+ .AdcChannels(ast_pkg::AdcChannels),
+ .AdcDataWidth(ast_pkg::AdcDataWidth),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+ ) u_ast (
+ // external POR
+ .por_ni ( manual_in_por_n ),
+
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( usb_io_pu_cal ),
+
+ // adc
+ .adc_a0_ai ( CC1 ),
+ .adc_a1_ai ( CC2 ),
+
+ // Direct short to PAD
+ .ast2pad_t0_ao ( IOA2 ),
+ .ast2pad_t1_ao ( IOA3 ),
+ // clocks and resets supplied for detection
+ .sns_clks_i ( clkmgr_aon_clocks ),
+ .sns_rsts_i ( rstmgr_aon_resets ),
+ .sns_spi_ext_clk_i ( sck_monitor ),
+ // tlul
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
+ // init done indication
+ .ast_init_done_o ( ast_init_done ),
+ // buffered clocks & resets
+ .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri),
+ .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri),
+ .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
+ .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_usb_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
+ .clk_ast_ext_i ( ext_clk ),
+
+ // pok test for FPGA
+ .vcc_supp_i ( 1'b1 ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
+ // pok
+ .ast_pwst_o ( ast_pwst ),
+ .ast_pwst_h_o ( ast_pwst_h ),
+ // main regulator
+ .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ // pdm control (flash)/otp
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
+ // system source clock
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( jen ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
+ // aon source clock
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
+ // io source clock
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
+ .clk_src_io_48m_o ( div_step_down_req ),
+ // usb source clock
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // smc source clock
+ .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ),
+ .clk_src_smc_o ( ast_base_clks.clk_smc ),
+ .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val),
+ // ml source clock
+ .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ),
+ .clk_src_ml_o ( ast_base_clks.clk_ml ),
+ .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val),
+ // video source clock
+ .clk_src_video_en_i ( base_ast_pwr.video_clk_en ),
+ .clk_src_video_o ( ast_base_clks.clk_video ),
+ .clk_src_video_val_o ( ast_base_pwr.video_clk_val),
+ // audio source clock
+ .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ),
+ .clk_src_audio_o ( ast_base_clks.clk_audio ),
+ .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val),
+ // adc
+ .adc_pd_i ( adc_req.pd ),
+ .adc_chnsel_i ( adc_req.channel_sel ),
+ .adc_d_o ( adc_rsp.data ),
+ .adc_d_val_o ( adc_rsp.data_valid ),
+ // rng
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_fips_i ( es_rng_fips ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
+ // entropy
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
+ // alerts
+ .alert_rsp_i ( ast_alert_rsp ),
+ .alert_req_o ( ast_alert_req ),
+ // dft
+ .dft_strap_test_i ( dft_strap_test ),
+ .lc_dft_en_i ( dft_en ),
+ .fla_obs_i ( fla_obs ),
+ .otp_obs_i ( otp_obs ),
+ .otm_obs_i ( '0 ),
+ .usb_obs_i ( usb_diff_rx_obs ),
+ .obs_ctrl_o ( obs_ctrl ),
+ // pinmux related
+ .padmux2ast_i ( pad2ast ),
+ .ast2padmux_o ( ast2pinmux ),
+ .ext_freq_is_96m_i ( hi_speed_sel ),
+ .all_clk_byp_req_i ( all_clk_byp_req ),
+ .all_clk_byp_ack_o ( all_clk_byp_ack ),
+ .io_clk_byp_req_i ( io_clk_byp_req ),
+ .io_clk_byp_ack_o ( io_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ // Memory configuration connections
+ .dpram_rmf_o ( ast_ram_2p_fcfg ),
+ .dpram_rml_o ( ast_ram_2p_lcfg ),
+ .spram_rm_o ( ast_ram_1p_cfg ),
+ .sprgf_rm_o ( ast_rf_cfg ),
+ .sprom_rm_o ( ast_rom_cfg ),
+ // scan
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
+ );
+
+
+
+ //////////////////////////////////
+ // Manual Pad / Signal Tie-offs //
+ //////////////////////////////////
+
+ assign manual_out_ast_misc = 1'b0;
+ assign manual_oe_ast_misc = 1'b0;
+ always_comb begin
+ // constantly enable pull-down
+ manual_attr_ast_misc = '0;
+ manual_attr_ast_misc.pull_select = 1'b0;
+ manual_attr_ast_misc.pull_en = 1'b1;
+ end
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+
+ assign manual_out_cc1 = 1'b0;
+ assign manual_oe_cc1 = 1'b0;
+ assign manual_out_cc2 = 1'b0;
+ assign manual_oe_cc2 = 1'b0;
+
+ assign manual_out_flash_test_mode0 = 1'b0;
+ assign manual_oe_flash_test_mode0 = 1'b0;
+ assign manual_out_flash_test_mode1 = 1'b0;
+ assign manual_oe_flash_test_mode1 = 1'b0;
+ assign manual_out_flash_test_volt = 1'b0;
+ assign manual_oe_flash_test_volt = 1'b0;
+ assign manual_out_otp_ext_volt = 1'b0;
+ assign manual_oe_otp_ext_volt = 1'b0;
+
+ // These pad attributes currently tied off permanently (these are all input-only pads).
+ assign manual_attr_por_n = '0;
+ assign manual_attr_cc1 = '0;
+ assign manual_attr_cc2 = '0;
+ assign manual_attr_flash_test_mode0 = '0;
+ assign manual_attr_flash_test_mode1 = '0;
+ assign manual_attr_flash_test_volt = '0;
+ assign manual_attr_otp_ext_volt = '0;
+ assign manual_attr_clk_ext = '0;
+ assign manual_attr_clk_byp = '0;
+
+ logic unused_manual_sigs;
+ assign unused_manual_sigs = ^{
+ manual_in_cc2,
+ manual_in_cc1,
+ manual_in_flash_test_volt,
+ manual_in_flash_test_mode0,
+ manual_in_flash_test_mode1,
+ manual_in_otp_ext_volt
+ };
+
+ ///////////////////////////////
+ // Differential USB Receiver //
+ ///////////////////////////////
+
+ // TODO: generalize this USB mux code and align with other tops.
+
+ // Connect the D+ pad
+ // Note that we use two pads in parallel for the D+ channel to meet electrical specifications.
+ assign dio_in[DioUsbdevUsbDp] = manual_in_usb_p;
+ assign manual_out_usb_p = dio_out[DioUsbdevUsbDp];
+ assign manual_oe_usb_p = dio_oe[DioUsbdevUsbDp];
+ assign manual_attr_usb_p = dio_attr[DioUsbdevUsbDp];
+
+ // Connect the D- pads
+ // Note that we use two pads in parallel for the D- channel to meet electrical specifications.
+ assign dio_in[DioUsbdevUsbDn] = manual_in_usb_n;
+ assign manual_out_usb_n = dio_out[DioUsbdevUsbDn];
+ assign manual_oe_usb_n = dio_oe[DioUsbdevUsbDn];
+ assign manual_attr_usb_n = dio_attr[DioUsbdevUsbDn];
+
+ logic usb_rx_d;
+
+ // Pullups and differential receiver enable
+ logic usb_dp_pullup_en, usb_dn_pullup_en;
+ logic usb_rx_enable;
+
+ prim_usb_diff_rx #(
+ .CalibW(ast_pkg::UsbCalibWidth)
+ ) u_prim_usb_diff_rx (
+ .input_pi ( USB_P ),
+ .input_ni ( USB_N ),
+ .input_en_i ( usb_rx_enable ),
+ .core_pok_h_i ( ast_pwst_h.aon_pok ),
+ .pullup_p_en_i ( usb_dp_pullup_en ),
+ .pullup_n_en_i ( usb_dn_pullup_en ),
+ .calibration_i ( usb_io_pu_cal ),
+ .usb_diff_rx_obs_o ( usb_diff_rx_obs ),
+ .input_o ( usb_rx_d )
+ );
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+ top_sencha #(
+ .PinmuxAonTargetCfg(PinmuxTargetCfg),
+ .SecAesAllowForcingMasks(1'b1),
+ .SecRomCtrlDisableScrambling(SecRomCtrlDisableScrambling)
+ ) top_sencha (
+ // ast connections
+ .por_n_i ( por_n ),
+ .clk_main_i ( ast_base_clks.clk_sys ),
+ .clk_io_i ( ast_base_clks.clk_io ),
+ .clk_usb_i ( ast_base_clks.clk_usb ),
+ .clk_aon_i ( ast_base_clks.clk_aon ),
+ .clk_smc_i ( ast_base_clks.clk_smc ),
+ .clk_ml_i ( ast_base_clks.clk_ml ),
+ .clk_video_i ( ast_base_clks.clk_video ),
+ .clk_audio_i ( ast_base_clks.clk_audio ),
+ .clks_ast_o ( clkmgr_aon_clocks ),
+ .clk_main_jitter_en_o ( jen ),
+ .rsts_ast_o ( rstmgr_aon_resets ),
+ .sck_monitor_o ( sck_monitor ),
+ .pwrmgr_ast_req_o ( base_ast_pwr ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ),
+ .usb_dp_pullup_en_o ( usb_dp_pullup_en ),
+ .usb_dn_pullup_en_o ( usb_dn_pullup_en ),
+ .usbdev_usb_rx_d_i ( usb_rx_d ),
+ .usbdev_usb_tx_d_o ( ),
+ .usbdev_usb_tx_se0_o ( ),
+ .usbdev_usb_tx_use_d_se0_o ( ),
+ .usbdev_usb_rx_enable_o ( usb_rx_enable ),
+ .usbdev_usb_ref_val_o ( usb_ref_val ),
+ .usbdev_usb_ref_pulse_o ( usb_ref_pulse ),
+ .ast_tl_req_o ( base_ast_bus ),
+ .ast_tl_rsp_i ( ast_base_bus ),
+ .adc_req_o ( adc_req ),
+ .adc_rsp_i ( adc_rsp ),
+ .ast_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_rsp_o ( ast_edn_edn_rsp ),
+ .obs_ctrl_i ( obs_ctrl ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+ .otp_obs_o ( otp_obs ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( flash_power_down_h ),
+ .flash_power_ready_h_i ( flash_power_ready_h ),
+ .flash_obs_o ( fla_obs ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .es_rng_fips_o ( es_rng_fips ),
+ .io_clk_byp_req_o ( io_clk_byp_req ),
+ .io_clk_byp_ack_i ( io_clk_byp_ack ),
+ .all_clk_byp_req_o ( all_clk_byp_req ),
+ .all_clk_byp_ack_i ( all_clk_byp_ack ),
+ .hi_speed_sel_o ( hi_speed_sel ),
+ .div_step_down_req_i ( div_step_down_req ),
+ .ast2pinmux_i ( ast2pinmux ),
+ .calib_rdy_i ( ast_init_done ),
+ .ast_init_done_i ( ast_init_done ),
+
+ // Flash test mode voltages
+ .flash_test_mode_a_io ( {FLASH_TEST_MODE1,
+ FLASH_TEST_MODE0} ),
+ .flash_test_voltage_h_io ( FLASH_TEST_VOLT ),
+
+ // OTP external voltage
+ .otp_ext_voltage_h_io ( OTP_EXT_VOLT ),
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+ .mio_out_o ( mio_out ),
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( ram_1p_cfg ),
+ .ram_2p_cfg_i ( ram_2p_cfg ),
+ .rom_cfg_i ( rom_cfg ),
+
+ // DFT signals
+ .ast_lc_dft_en_o ( dft_en ),
+ .dft_strap_test_o ( dft_strap_test ),
+ .dft_hold_tap_sel_i ( '0 ),
+ .scan_rst_ni ( scan_rst_n ),
+ .scan_en_i ( scan_en ),
+ .scanmode_i ( scanmode ),
+
+ // FPGA build info
+ .fpga_info_i ( '0 )
+ );
+
+
+endmodule : chip_sencha_asic
diff --git a/hw/top_sencha/rtl/autogen/chip_sencha_nexus.sv b/hw/top_sencha/rtl/autogen/chip_sencha_nexus.sv
new file mode 100644
index 0000000..0e43b88
--- /dev/null
+++ b/hw/top_sencha/rtl/autogen/chip_sencha_nexus.sv
@@ -0,0 +1,1038 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+
+module chip_sencha_nexus #(
+ // Path to a VMEM file containing the contents of the boot ROM, which will be
+ // baked into the FPGA bitstream.
+ parameter BootRomInitFile = "test_rom_fpga_nexus.32.vmem",
+ // Path to a VMEM file containing the contents of the emulated OTP, which will be
+ // baked into the FPGA bitstream.
+ parameter OtpCtrlMemInitFile = "otp_img_fpga_nexus.vmem"
+) (
+ // Dedicated Pads
+ inout POR_N, // Manual Pad
+ inout USB_P, // Manual Pad
+ inout USB_N, // Manual Pad
+ inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck
+ inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb
+ inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck
+ inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb
+ inout IOR8, // Dedicated Pad for sysrst_ctrl_aon_ec_rst_l
+ inout IOR9, // Dedicated Pad for sysrst_ctrl_aon_flash_wp_l
+ inout IO_CLK, // Manual Pad
+ inout IO_CLK_N, // Manual Pad
+ inout POR_BUTTON_N, // Manual Pad
+ inout JTAG_SRST_N, // Manual Pad
+ inout IO_CLKOUT, // Manual Pad
+ inout IO_TRIGGER, // Manual Pad
+
+ // Muxed Pads
+ inout IOA0, // MIO Pad 0
+ inout IOA1, // MIO Pad 1
+ `INOUT_AO IOA2, // MIO Pad 2
+ `INOUT_AO IOA3, // MIO Pad 3
+ inout IOA4, // MIO Pad 4
+ inout IOA5, // MIO Pad 5
+ inout IOA6, // MIO Pad 6
+ inout IOA7, // MIO Pad 7
+ inout IOA8, // MIO Pad 8
+ inout IOB0, // MIO Pad 9
+ inout IOB1, // MIO Pad 10
+ inout IOB2, // MIO Pad 11
+ inout IOB3, // MIO Pad 12
+ inout IOB4, // MIO Pad 13
+ inout IOB5, // MIO Pad 14
+ inout IOB6, // MIO Pad 15
+ inout IOB7, // MIO Pad 16
+ inout IOB8, // MIO Pad 17
+ inout IOB9, // MIO Pad 18
+ inout IOB10, // MIO Pad 19
+ inout IOB11, // MIO Pad 20
+ inout IOB12, // MIO Pad 21
+ inout IOC0, // MIO Pad 22
+ inout IOC1, // MIO Pad 23
+ inout IOC2, // MIO Pad 24
+ inout IOC3, // MIO Pad 25
+ inout IOC4, // MIO Pad 26
+ inout IOC5, // MIO Pad 27
+ inout IOC6, // MIO Pad 28
+ inout IOC7, // MIO Pad 29
+ inout IOC8, // MIO Pad 30
+ inout IOC9, // MIO Pad 31
+ inout IOC10, // MIO Pad 32
+ inout IOC11, // MIO Pad 33
+ inout IOC12, // MIO Pad 34
+ inout IOR0, // MIO Pad 35
+ inout IOR1, // MIO Pad 36
+ inout IOR2, // MIO Pad 37
+ inout IOR3, // MIO Pad 38
+ inout IOR4, // MIO Pad 39
+ inout IOR5, // MIO Pad 40
+ inout IOR6, // MIO Pad 41
+ inout IOR7, // MIO Pad 42
+ inout IOR10, // MIO Pad 43
+ inout IOR11, // MIO Pad 44
+ inout IOR12, // MIO Pad 45
+ inout IOR13, // MIO Pad 46
+ inout IOD0, // MIO Pad 47
+ inout IOD1, // MIO Pad 48
+ inout IOD2, // MIO Pad 49
+ inout IOD3, // MIO Pad 50
+ inout IOD4, // MIO Pad 51
+ inout IOD5 // MIO Pad 52
+);
+
+ import top_sencha_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+
+ ////////////////////////////
+ // Special Signal Indices //
+ ////////////////////////////
+
+ localparam int Tap0PadIdx = 30;
+ localparam int Tap1PadIdx = 27;
+ localparam int Dft0PadIdx = 25;
+ localparam int Dft1PadIdx = 26;
+ localparam int TckPadIdx = 38;
+ localparam int TmsPadIdx = 35;
+ localparam int TrstNPadIdx = 39;
+ localparam int TdiPadIdx = 37;
+ localparam int TdoPadIdx = 36;
+
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevUsbDp,
+ usb_dn_idx: DioUsbdevUsbDn,
+ usb_sense_idx: MioInUsbdevSense,
+ // Pad types for attribute WARL behavior
+ dio_pad_type: {
+ BidirStd, // DIO spi_host0_csb
+ BidirStd, // DIO spi_host0_sck
+ InputStd, // DIO spi_device_csb
+ InputStd, // DIO spi_device_sck
+ BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l
+ BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_device_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO spi_host0_sd
+ BidirStd, // DIO usbdev_usb_dn
+ BidirStd // DIO usbdev_usb_dp
+ },
+ mio_pad_type: {
+ BidirStd, // MIO Pad 52
+ BidirStd, // MIO Pad 51
+ BidirStd, // MIO Pad 50
+ BidirStd, // MIO Pad 49
+ BidirStd, // MIO Pad 48
+ BidirStd, // MIO Pad 47
+ BidirOd, // MIO Pad 46
+ BidirOd, // MIO Pad 45
+ BidirOd, // MIO Pad 44
+ BidirOd, // MIO Pad 43
+ BidirStd, // MIO Pad 42
+ BidirStd, // MIO Pad 41
+ BidirStd, // MIO Pad 40
+ BidirStd, // MIO Pad 39
+ BidirStd, // MIO Pad 38
+ BidirStd, // MIO Pad 37
+ BidirStd, // MIO Pad 36
+ BidirStd, // MIO Pad 35
+ BidirOd, // MIO Pad 34
+ BidirOd, // MIO Pad 33
+ BidirOd, // MIO Pad 32
+ BidirStd, // MIO Pad 31
+ BidirStd, // MIO Pad 30
+ BidirStd, // MIO Pad 29
+ BidirStd, // MIO Pad 28
+ BidirStd, // MIO Pad 27
+ BidirStd, // MIO Pad 26
+ BidirStd, // MIO Pad 25
+ BidirStd, // MIO Pad 24
+ BidirStd, // MIO Pad 23
+ BidirStd, // MIO Pad 22
+ BidirOd, // MIO Pad 21
+ BidirOd, // MIO Pad 20
+ BidirOd, // MIO Pad 19
+ BidirOd, // MIO Pad 18
+ BidirStd, // MIO Pad 17
+ BidirStd, // MIO Pad 16
+ BidirStd, // MIO Pad 15
+ BidirStd, // MIO Pad 14
+ BidirStd, // MIO Pad 13
+ BidirStd, // MIO Pad 12
+ BidirStd, // MIO Pad 11
+ BidirStd, // MIO Pad 10
+ BidirStd, // MIO Pad 9
+ BidirOd, // MIO Pad 8
+ BidirOd, // MIO Pad 7
+ BidirOd, // MIO Pad 6
+ BidirStd, // MIO Pad 5
+ BidirStd, // MIO Pad 4
+ BidirStd, // MIO Pad 3
+ BidirStd, // MIO Pad 2
+ BidirStd, // MIO Pad 1
+ BidirStd // MIO Pad 0
+ }
+ };
+
+ ////////////////////////
+ // Signal definitions //
+ ////////////////////////
+
+
+ pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+ pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+ logic unused_mio_in_raw;
+ assign unused_mio_in_raw = ^mio_in_raw;
+
+ // Manual pads
+ logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
+ logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
+ logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
+ logic manual_in_io_clk, manual_out_io_clk, manual_oe_io_clk;
+ logic manual_in_io_clk_n, manual_out_io_clk_n, manual_oe_io_clk_n;
+ logic manual_in_por_button_n, manual_out_por_button_n, manual_oe_por_button_n;
+ logic manual_in_jtag_srst_n, manual_out_jtag_srst_n, manual_oe_jtag_srst_n;
+ logic manual_in_io_clkout, manual_out_io_clkout, manual_oe_io_clkout;
+ logic manual_in_io_trigger, manual_out_io_trigger, manual_oe_io_trigger;
+
+ pad_attr_t manual_attr_por_n;
+ pad_attr_t manual_attr_usb_p;
+ pad_attr_t manual_attr_usb_n;
+ pad_attr_t manual_attr_io_clk;
+ pad_attr_t manual_attr_io_clk_n;
+ pad_attr_t manual_attr_por_button_n;
+ pad_attr_t manual_attr_jtag_srst_n;
+ pad_attr_t manual_attr_io_clkout;
+ pad_attr_t manual_attr_io_trigger;
+
+ /////////////////////////
+ // Stubbed pad tie-off //
+ /////////////////////////
+
+ // Only signals going to non-custom pads need to be tied off.
+ logic [75:0] unused_sig;
+
+ //////////////////////
+ // Padring Instance //
+ //////////////////////
+
+ ast_pkg::ast_clks_t ast_base_clks;
+
+
+ padring #(
+ // Padring specific counts may differ from pinmux config due
+ // to custom, stubbed or added pads.
+ .NDioPads(23),
+ .NMioPads(53),
+ .DioPadType ({
+ BidirStd, // IO_TRIGGER
+ BidirStd, // IO_CLKOUT
+ InputStd, // JTAG_SRST_N
+ InputStd, // POR_BUTTON_N
+ AnalogIn0, // IO_CLK_N
+ AnalogIn0, // IO_CLK
+ BidirOd, // IOR9
+ BidirOd, // IOR8
+ InputStd, // SPI_DEV_CS_L
+ InputStd, // SPI_DEV_CLK
+ BidirStd, // SPI_DEV_D3
+ BidirStd, // SPI_DEV_D2
+ BidirStd, // SPI_DEV_D1
+ BidirStd, // SPI_DEV_D0
+ BidirStd, // SPI_HOST_CS_L
+ BidirStd, // SPI_HOST_CLK
+ BidirStd, // SPI_HOST_D3
+ BidirStd, // SPI_HOST_D2
+ BidirStd, // SPI_HOST_D1
+ BidirStd, // SPI_HOST_D0
+ DualBidirTol, // USB_N
+ DualBidirTol, // USB_P
+ InputStd // POR_N
+ }),
+ .MioPadType ({
+ BidirStd, // IOD5
+ BidirStd, // IOD4
+ BidirStd, // IOD3
+ BidirStd, // IOD2
+ BidirStd, // IOD1
+ BidirStd, // IOD0
+ BidirOd, // IOR13
+ BidirOd, // IOR12
+ BidirOd, // IOR11
+ BidirOd, // IOR10
+ BidirStd, // IOR7
+ BidirStd, // IOR6
+ BidirStd, // IOR5
+ BidirStd, // IOR4
+ BidirStd, // IOR3
+ BidirStd, // IOR2
+ BidirStd, // IOR1
+ BidirStd, // IOR0
+ BidirOd, // IOC12
+ BidirOd, // IOC11
+ BidirOd, // IOC10
+ BidirStd, // IOC9
+ BidirStd, // IOC8
+ BidirStd, // IOC7
+ BidirStd, // IOC6
+ BidirStd, // IOC5
+ BidirStd, // IOC4
+ BidirStd, // IOC3
+ BidirStd, // IOC2
+ BidirStd, // IOC1
+ BidirStd, // IOC0
+ BidirOd, // IOB12
+ BidirOd, // IOB11
+ BidirOd, // IOB10
+ BidirOd, // IOB9
+ BidirStd, // IOB8
+ BidirStd, // IOB7
+ BidirStd, // IOB6
+ BidirStd, // IOB5
+ BidirStd, // IOB4
+ BidirStd, // IOB3
+ BidirStd, // IOB2
+ BidirStd, // IOB1
+ BidirStd, // IOB0
+ BidirOd, // IOA8
+ BidirOd, // IOA7
+ BidirOd, // IOA6
+ BidirStd, // IOA5
+ BidirStd, // IOA4
+ BidirStd, // IOA3
+ BidirStd, // IOA2
+ BidirStd, // IOA1
+ BidirStd // IOA0
+ })
+ ) u_padring (
+ // This is only used for scan and DFT purposes
+ .clk_scan_i ( 1'b0 ),
+ .scanmode_i ( prim_mubi_pkg::MuBi4False ),
+ .dio_in_raw_o ( ),
+ // Chip IOs
+ .dio_pad_io ({
+ IO_TRIGGER,
+ IO_CLKOUT,
+ JTAG_SRST_N,
+ POR_BUTTON_N,
+ IO_CLK_N,
+ IO_CLK,
+ IOR9,
+ IOR8,
+ SPI_DEV_CS_L,
+ SPI_DEV_CLK,
+ SPI_DEV_D3,
+ SPI_DEV_D2,
+ SPI_DEV_D1,
+ SPI_DEV_D0,
+ SPI_HOST_CS_L,
+ SPI_HOST_CLK,
+ SPI_HOST_D3,
+ SPI_HOST_D2,
+ SPI_HOST_D1,
+ SPI_HOST_D0,
+ USB_N,
+ USB_P,
+ POR_N
+ }),
+
+ .mio_pad_io ({
+ IOD5,
+ IOD4,
+ IOD3,
+ IOD2,
+ IOD1,
+ IOD0,
+ IOR13,
+ IOR12,
+ IOR11,
+ IOR10,
+ IOR7,
+ IOR6,
+ IOR5,
+ IOR4,
+ IOR3,
+ IOR2,
+ IOR1,
+ IOR0,
+ IOC12,
+ IOC11,
+ IOC10,
+ IOC9,
+ IOC8,
+ IOC7,
+ IOC6,
+ IOC5,
+ IOC4,
+ IOC3,
+ IOC2,
+ IOC1,
+ IOC0,
+ IOB12,
+ IOB11,
+ IOB10,
+ IOB9,
+ IOB8,
+ IOB7,
+ IOB6,
+ IOB5,
+ IOB4,
+ IOB3,
+ IOB2,
+ IOB1,
+ IOB0,
+ IOA8,
+ IOA7,
+ IOA6,
+ IOA5,
+ IOA4,
+`ifdef ANALOGSIM
+ '0,
+`else
+ IOA3,
+`endif
+`ifdef ANALOGSIM
+ '0,
+`else
+ IOA2,
+`endif
+ IOA1,
+ IOA0
+ }),
+
+ // Core-facing
+ .dio_in_o ({
+ manual_in_io_trigger,
+ manual_in_io_clkout,
+ manual_in_jtag_srst_n,
+ manual_in_por_button_n,
+ manual_in_io_clk_n,
+ manual_in_io_clk,
+ dio_in[DioSysrstCtrlAonFlashWpL],
+ dio_in[DioSysrstCtrlAonEcRstL],
+ dio_in[DioSpiDeviceCsb],
+ dio_in[DioSpiDeviceSck],
+ dio_in[DioSpiDeviceSd3],
+ dio_in[DioSpiDeviceSd2],
+ dio_in[DioSpiDeviceSd1],
+ dio_in[DioSpiDeviceSd0],
+ dio_in[DioSpiHost0Csb],
+ dio_in[DioSpiHost0Sck],
+ dio_in[DioSpiHost0Sd3],
+ dio_in[DioSpiHost0Sd2],
+ dio_in[DioSpiHost0Sd1],
+ dio_in[DioSpiHost0Sd0],
+ manual_in_usb_n,
+ manual_in_usb_p,
+ manual_in_por_n
+ }),
+ .dio_out_i ({
+ manual_out_io_trigger,
+ manual_out_io_clkout,
+ manual_out_jtag_srst_n,
+ manual_out_por_button_n,
+ manual_out_io_clk_n,
+ manual_out_io_clk,
+ dio_out[DioSysrstCtrlAonFlashWpL],
+ dio_out[DioSysrstCtrlAonEcRstL],
+ dio_out[DioSpiDeviceCsb],
+ dio_out[DioSpiDeviceSck],
+ dio_out[DioSpiDeviceSd3],
+ dio_out[DioSpiDeviceSd2],
+ dio_out[DioSpiDeviceSd1],
+ dio_out[DioSpiDeviceSd0],
+ dio_out[DioSpiHost0Csb],
+ dio_out[DioSpiHost0Sck],
+ dio_out[DioSpiHost0Sd3],
+ dio_out[DioSpiHost0Sd2],
+ dio_out[DioSpiHost0Sd1],
+ dio_out[DioSpiHost0Sd0],
+ manual_out_usb_n,
+ manual_out_usb_p,
+ manual_out_por_n
+ }),
+ .dio_oe_i ({
+ manual_oe_io_trigger,
+ manual_oe_io_clkout,
+ manual_oe_jtag_srst_n,
+ manual_oe_por_button_n,
+ manual_oe_io_clk_n,
+ manual_oe_io_clk,
+ dio_oe[DioSysrstCtrlAonFlashWpL],
+ dio_oe[DioSysrstCtrlAonEcRstL],
+ dio_oe[DioSpiDeviceCsb],
+ dio_oe[DioSpiDeviceSck],
+ dio_oe[DioSpiDeviceSd3],
+ dio_oe[DioSpiDeviceSd2],
+ dio_oe[DioSpiDeviceSd1],
+ dio_oe[DioSpiDeviceSd0],
+ dio_oe[DioSpiHost0Csb],
+ dio_oe[DioSpiHost0Sck],
+ dio_oe[DioSpiHost0Sd3],
+ dio_oe[DioSpiHost0Sd2],
+ dio_oe[DioSpiHost0Sd1],
+ dio_oe[DioSpiHost0Sd0],
+ manual_oe_usb_n,
+ manual_oe_usb_p,
+ manual_oe_por_n
+ }),
+ .dio_attr_i ({
+ manual_attr_io_trigger,
+ manual_attr_io_clkout,
+ manual_attr_jtag_srst_n,
+ manual_attr_por_button_n,
+ manual_attr_io_clk_n,
+ manual_attr_io_clk,
+ dio_attr[DioSysrstCtrlAonFlashWpL],
+ dio_attr[DioSysrstCtrlAonEcRstL],
+ dio_attr[DioSpiDeviceCsb],
+ dio_attr[DioSpiDeviceSck],
+ dio_attr[DioSpiDeviceSd3],
+ dio_attr[DioSpiDeviceSd2],
+ dio_attr[DioSpiDeviceSd1],
+ dio_attr[DioSpiDeviceSd0],
+ dio_attr[DioSpiHost0Csb],
+ dio_attr[DioSpiHost0Sck],
+ dio_attr[DioSpiHost0Sd3],
+ dio_attr[DioSpiHost0Sd2],
+ dio_attr[DioSpiHost0Sd1],
+ dio_attr[DioSpiHost0Sd0],
+ manual_attr_usb_n,
+ manual_attr_usb_p,
+ manual_attr_por_n
+ }),
+
+ .mio_in_o (mio_in[52:0]),
+ .mio_out_i (mio_out[52:0]),
+ .mio_oe_i (mio_oe[52:0]),
+ .mio_attr_i (mio_attr[52:0]),
+ .mio_in_raw_o (mio_in_raw[52:0])
+ );
+
+
+
+ //////////////////////////////////
+ // AST - Common for all targets //
+ //////////////////////////////////
+
+ // pwrmgr interface
+ pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+ // assorted ast status
+ ast_pkg::ast_pwst_t ast_pwst;
+ ast_pkg::ast_pwst_t ast_pwst_h;
+
+ // TLUL interface
+ tlul_pkg::tl_h2d_t base_ast_bus;
+ tlul_pkg::tl_d2h_t ast_base_bus;
+
+ // synchronization clocks / rests
+ clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
+ rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
+
+ // external clock
+ logic ext_clk;
+
+ // monitored clock
+ logic sck_monitor;
+
+ // observe interface
+ logic [7:0] fla_obs;
+ logic [7:0] otp_obs;
+ ast_pkg::ast_obs_ctrl_t obs_ctrl;
+
+ // otp power sequence
+ otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+ otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+ logic usb_ref_pulse;
+ logic usb_ref_val;
+
+ // adc
+ ast_pkg::adc_ast_req_t adc_req;
+ ast_pkg::adc_ast_rsp_t adc_rsp;
+
+ // entropy source interface
+ // The entropy source pacakge definition should eventually be moved to es
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+ logic es_rng_fips;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+ // alerts interface
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
+
+ // Flash connections
+ prim_mubi_pkg::mubi4_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
+
+ // clock bypass req/ack
+ prim_mubi_pkg::mubi4_t io_clk_byp_req;
+ prim_mubi_pkg::mubi4_t io_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t all_clk_byp_req;
+ prim_mubi_pkg::mubi4_t all_clk_byp_ack;
+ prim_mubi_pkg::mubi4_t hi_speed_sel;
+ prim_mubi_pkg::mubi4_t div_step_down_req;
+
+ // DFT connections
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t dft_en;
+ pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+ // Debug connections
+ logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
+
+ // Jitter enable
+ prim_mubi_pkg::mubi4_t jen;
+
+ // reset domain connections
+ import rstmgr_pkg::PowerDomains;
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
+
+ // Memory configuration connections
+ ast_pkg::spm_rm_t ast_ram_1p_cfg;
+ ast_pkg::spm_rm_t ast_rf_cfg;
+ ast_pkg::spm_rm_t ast_rom_cfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
+
+ prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
+ prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
+ prim_rom_pkg::rom_cfg_t rom_cfg;
+
+ // conversion from ast structure to memory centric structures
+ assign ram_1p_cfg = '{
+ ram_cfg: '{
+ cfg_en: ast_ram_1p_cfg.marg_en,
+ cfg: ast_ram_1p_cfg.marg
+ },
+ rf_cfg: '{
+ cfg_en: ast_rf_cfg.marg_en,
+ cfg: ast_rf_cfg.marg
+ }
+ };
+
+ assign ram_2p_cfg = '{
+ a_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_a,
+ cfg: ast_ram_2p_fcfg.marg_a
+ },
+ a_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_a,
+ cfg: ast_ram_2p_lcfg.marg_a
+ },
+ b_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_b,
+ cfg: ast_ram_2p_fcfg.marg_b
+ },
+ b_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_b,
+ cfg: ast_ram_2p_lcfg.marg_b
+ }
+ };
+
+ assign rom_cfg = '{
+ cfg_en: ast_rom_cfg.marg_en,
+ cfg: ast_rom_cfg.marg
+ };
+
+
+ //////////////////////////////////
+ // AST - Custom for targets //
+ //////////////////////////////////
+
+
+ assign ast_base_pwr.main_pok = ast_pwst.main_pok;
+
+ logic [rstmgr_pkg::PowerDomains-1:0] por_n;
+ assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
+
+ // TODO: Hook this up when FPGA pads are updated
+ assign ext_clk = '0;
+ assign pad2ast = '0;
+
+ logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n;
+ clkgen_xilultrascaleplus # (
+ .AddClkBuf(0)
+ ) clkgen (
+ .clk_i(manual_in_io_clk),
+ .clk_n_i(manual_in_io_clk_n),
+ .rst_ni(manual_in_por_n),
+ .srst_ni(srst_n),
+ .clk_main_o(clk_main),
+ .clk_48MHz_o(clk_usb_48mhz),
+ .clk_aon_o(clk_aon),
+ .rst_no(rst_n)
+ );
+
+
+ logic [31:0] fpga_info;
+ usr_access_xil7series u_info (
+ .info_o(fpga_info)
+ );
+
+ // Currently use te same clk_main for smc, ml and video, while 48mhz for audio.
+ ast_pkg::clks_osc_byp_t clks_osc_byp;
+ assign clks_osc_byp = '{
+ usb: clk_usb_48mhz,
+ sys: clk_main,
+ io: clk_main,
+ aon: clk_aon,
+ smc: clk_main,
+ ml: clk_main,
+ video: clk_main,
+ audio: clk_usb_48mhz
+ };
+
+
+ prim_mubi_pkg::mubi4_t ast_init_done;
+
+ ast #(
+ .EntropyStreams(ast_pkg::EntropyStreams),
+ .AdcChannels(ast_pkg::AdcChannels),
+ .AdcDataWidth(ast_pkg::AdcDataWidth),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+ ) u_ast (
+ // external POR
+ .por_ni ( rst_n ),
+
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( ),
+
+ // clocks' oschillator bypass for FPGA
+ .clk_osc_byp_i ( clks_osc_byp ),
+
+ // adc
+ .adc_a0_ai ( '0 ),
+ .adc_a1_ai ( '0 ),
+
+ // Direct short to PAD
+ .ast2pad_t0_ao ( ),
+ .ast2pad_t1_ao ( ),
+
+ // clocks and resets supplied for detection
+ .sns_clks_i ( clkmgr_aon_clocks ),
+ .sns_rsts_i ( rstmgr_aon_resets ),
+ .sns_spi_ext_clk_i ( sck_monitor ),
+ // tlul
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
+ // init done indication
+ .ast_init_done_o ( ast_init_done ),
+ // buffered clocks & resets
+ .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri),
+ .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri),
+ .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
+ .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ast_usb_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
+ .clk_ast_ext_i ( ext_clk ),
+
+ // pok test for FPGA
+ .vcc_supp_i ( 1'b1 ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
+ // pok
+ .ast_pwst_o ( ast_pwst ),
+ .ast_pwst_h_o ( ast_pwst_h ),
+ // main regulator
+ .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ // pdm control (flash)/otp
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
+ // system source clock
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( jen ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
+ // aon source clock
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
+ // io source clock
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
+ .clk_src_io_48m_o ( div_step_down_req ),
+ // usb source clock
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // smc source clock
+ .clk_src_smc_en_i ( base_ast_pwr.smc_clk_en ),
+ .clk_src_smc_o ( ast_base_clks.clk_smc ),
+ .clk_src_smc_val_o ( ast_base_pwr.smc_clk_val),
+ // ml source clock
+ .clk_src_ml_en_i ( base_ast_pwr.ml_clk_en ),
+ .clk_src_ml_o ( ast_base_clks.clk_ml ),
+ .clk_src_ml_val_o ( ast_base_pwr.ml_clk_val),
+ // video source clock
+ .clk_src_video_en_i ( base_ast_pwr.video_clk_en ),
+ .clk_src_video_o ( ast_base_clks.clk_video ),
+ .clk_src_video_val_o ( ast_base_pwr.video_clk_val),
+ // audio source clock
+ .clk_src_audio_en_i ( base_ast_pwr.audio_clk_en ),
+ .clk_src_audio_o ( ast_base_clks.clk_audio ),
+ .clk_src_audio_val_o ( ast_base_pwr.audio_clk_val),
+ // adc
+ .adc_pd_i ( adc_req.pd ),
+ .adc_chnsel_i ( adc_req.channel_sel ),
+ .adc_d_o ( adc_rsp.data ),
+ .adc_d_val_o ( adc_rsp.data_valid ),
+ // rng
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_fips_i ( es_rng_fips ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
+ // entropy
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
+ // alerts
+ .alert_rsp_i ( ast_alert_rsp ),
+ .alert_req_o ( ast_alert_req ),
+ // dft
+ .dft_strap_test_i ( dft_strap_test ),
+ .lc_dft_en_i ( dft_en ),
+ .fla_obs_i ( fla_obs ),
+ .otp_obs_i ( otp_obs ),
+ .otm_obs_i ( '0 ),
+ .usb_obs_i ( usb_diff_rx_obs ),
+ .obs_ctrl_o ( obs_ctrl ),
+ // pinmux related
+ .padmux2ast_i ( pad2ast ),
+ .ast2padmux_o ( ast2pinmux ),
+ .ext_freq_is_96m_i ( hi_speed_sel ),
+ .all_clk_byp_req_i ( all_clk_byp_req ),
+ .all_clk_byp_ack_o ( all_clk_byp_ack ),
+ .io_clk_byp_req_i ( io_clk_byp_req ),
+ .io_clk_byp_ack_o ( io_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ // Memory configuration connections
+ .dpram_rmf_o ( ast_ram_2p_fcfg ),
+ .dpram_rml_o ( ast_ram_2p_lcfg ),
+ .spram_rm_o ( ast_ram_1p_cfg ),
+ .sprgf_rm_o ( ast_rf_cfg ),
+ .sprom_rm_o ( ast_rom_cfg ),
+ // scan
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
+ );
+
+
+
+ //////////////////
+ // PLL for FPGA //
+ //////////////////
+
+ assign manual_attr_io_clk = '0;
+ assign manual_out_io_clk = 1'b0;
+ assign manual_oe_io_clk = 1'b0;
+ assign manual_attr_por_n = '0;
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+
+ assign manual_attr_por_button_n = '0;
+ assign manual_out_por_button_n = 1'b0;
+ assign manual_oe_por_button_n = 1'b0;
+
+ assign srst_n = manual_in_por_button_n & manual_in_jtag_srst_n;
+ assign manual_attr_jtag_srst_n = '0;
+ assign manual_out_jtag_srst_n = 1'b0;
+ assign manual_oe_jtag_srst_n = 1'b0;
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+
+ // the rst_ni pin only goes to AST
+ // the rest of the logic generates reset based on the 'pok' signal.
+ // for verilator purposes, make these two the same.
+ prim_mubi_pkg::mubi4_t lc_clk_bypass;
+
+// TODO: align this with ASIC version to minimize the duplication.
+// Also need to add AST simulation and FPGA emulation models for things like entropy source -
+// otherwise Verilator / FPGA will hang.
+ top_sencha #(
+ .SecAesMasking(1'b1),
+ .SecAesSBoxImpl(aes_pkg::SBoxImplDom),
+ .SecAesStartTriggerDelay(40),
+ .SecAesAllowForcingMasks(1'b1),
+ .SecAesSkipPRNGReseeding(1'b1),
+ .KmacEnMasking(0),
+ .SecKmacCmdDelay(40),
+ .SecKmacIdleAcceptSwMsg(1'b1),
+ .KeymgrKmacEnMasking(0),
+ .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
+ .OtbnRegFile(otbn_pkg::RegFileFPGA),
+ .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
+ .UsbdevRcvrWakeTimeUs(10000),
+ .RomCtrlBootRomInitFile(BootRomInitFile),
+ .RvCoreIbexSecRegFile(ibex_pkg::RegFileFPGA),
+ .RvCoreIbexSecPipeLine(1),
+ .RvCoreIbexSecSecureIbex(0),
+ .RvCoreIbexSmcRegFile(ibex_pkg::RegFileFPGA),
+ .RvCoreIbexSmcPipeLine(1),
+ .RvCoreIbexSmcSecureSmc(0),
+ .SramCtrlRetAonInstrExec(0),
+ .SramCtrlMainInstrExec(1),
+ .PinmuxAonTargetCfg(PinmuxTargetCfg)
+ ) top_sencha (
+ .por_n_i ( por_n ),
+ .clk_main_i ( ast_base_clks.clk_sys ),
+ .clk_io_i ( ast_base_clks.clk_io ),
+ .clk_usb_i ( ast_base_clks.clk_usb ),
+ .clk_aon_i ( ast_base_clks.clk_aon ),
+ .clk_smc_i ( ast_base_clks.clk_smc ),
+ .clk_ml_i ( ast_base_clks.clk_ml ),
+ .clk_video_i ( ast_base_clks.clk_video ),
+ .clk_audio_i ( ast_base_clks.clk_audio ),
+ .clks_ast_o ( clkmgr_aon_clocks ),
+ .clk_main_jitter_en_o ( jen ),
+ .rsts_ast_o ( rstmgr_aon_resets ),
+ .sck_monitor_o ( sck_monitor ),
+ .pwrmgr_ast_req_o ( base_ast_pwr ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .usb_dp_pullup_en_o ( usb_dp_pullup_en ),
+ .usb_dn_pullup_en_o ( usb_dn_pullup_en ),
+ .usbdev_usb_rx_d_i ( usb_rx_d ),
+ .usbdev_usb_tx_d_o ( usb_tx_d ),
+ .usbdev_usb_tx_se0_o ( usb_tx_se0 ),
+ .usbdev_usb_tx_use_d_se0_o ( usb_tx_use_d_se0 ),
+ .usbdev_usb_rx_enable_o ( usb_rx_enable ),
+ .usbdev_usb_ref_val_o ( usb_ref_val ),
+ .usbdev_usb_ref_pulse_o ( usb_ref_pulse ),
+ .ast_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_rsp_o ( ast_edn_edn_rsp ),
+ .obs_ctrl_i ( obs_ctrl ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( 1'b0 ),
+ .flash_power_ready_h_i ( 1'b1 ),
+ .flash_obs_o ( flash_obs ),
+ .io_clk_byp_req_o ( io_clk_byp_req ),
+ .io_clk_byp_ack_i ( io_clk_byp_ack ),
+ .all_clk_byp_req_o ( all_clk_byp_req ),
+ .all_clk_byp_ack_i ( all_clk_byp_ack ),
+ .hi_speed_sel_o ( hi_speed_sel ),
+ .div_step_down_req_i ( div_step_down_req ),
+ .fpga_info_i ( fpga_info ),
+ .ast_tl_req_o ( base_ast_bus ),
+ .ast_tl_rsp_i ( ast_base_bus ),
+ .adc_req_o ( adc_req ),
+ .adc_rsp_i ( adc_rsp ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+ .otp_obs_o ( otp_obs ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .es_rng_fips_o ( es_rng_fips ),
+ .ast2pinmux_i ( ast2pinmux ),
+ .calib_rdy_i ( ast_init_done ),
+ .ast_init_done_i ( ast_init_done ),
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+ .mio_out_o ( mio_out ),
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( '0 ),
+ .ram_2p_cfg_i ( '0 ),
+ .rom_cfg_i ( '0 ),
+
+ // DFT signals
+ .dft_hold_tap_sel_i ( '0 ),
+ .scan_rst_ni ( 1'b1 ),
+ .scan_en_i ( 1'b0 ),
+ .scanmode_i ( prim_mubi_pkg::MuBi4False )
+ );
+
+endmodule : chip_sencha_nexus
diff --git a/hw/top_sencha/rtl/autogen/top_sencha.sv b/hw/top_sencha/rtl/autogen/top_sencha.sv
new file mode 100644
index 0000000..525f3a2
--- /dev/null
+++ b/hw/top_sencha/rtl/autogen/top_sencha.sv
@@ -0,0 +1,4377 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+module top_sencha #(
+ // Manually defined parameters
+
+ // Auto-inferred parameters
+ // parameters for uart0
+ // parameters for uart1
+ // parameters for uart2
+ // parameters for uart3
+ // parameters for gpio
+ parameter bit GpioGpioAsyncOn = 1,
+ // parameters for spi_device
+ // parameters for i2c0
+ // parameters for i2c1
+ // parameters for i2c2
+ // parameters for pattgen
+ // parameters for rv_timer
+ // parameters for otp_ctrl
+ parameter OtpCtrlMemInitFile = "",
+ // parameters for lc_ctrl
+ parameter logic [15:0] LcCtrlChipGen = 16'h 0000,
+ parameter logic [15:0] LcCtrlChipRev = 16'h 0000,
+ parameter logic [31:0] LcCtrlIdcodeValue = jtag_id_pkg::JTAG_IDCODE,
+ // parameters for alert_handler
+ // parameters for spi_host0
+ // parameters for spi_host1
+ // parameters for usbdev
+ parameter bit UsbdevStub = 0,
+ parameter int UsbdevRcvrWakeTimeUs = 100,
+ // parameters for pwrmgr_aon
+ // parameters for rstmgr_aon
+ parameter bit SecRstmgrAonCheck = 1'b1,
+ parameter int SecRstmgrAonMaxSyncDelay = 2,
+ // parameters for clkmgr_aon
+ // parameters for sysrst_ctrl_aon
+ // parameters for adc_ctrl_aon
+ // parameters for pwm_aon
+ // parameters for pinmux_aon
+ parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg,
+ // parameters for aon_timer_aon
+ // parameters for sensor_ctrl
+ // parameters for sram_ctrl_ret_aon
+ parameter bit SramCtrlRetAonInstrExec = 0,
+ // parameters for flash_ctrl
+ parameter bit SecFlashCtrlScrambleEn = 1,
+ parameter int FlashCtrlProgFifoDepth = 4,
+ parameter int FlashCtrlRdFifoDepth = 16,
+ // parameters for rv_dm
+ parameter logic [31:0] RvDmIdcodeValue = jtag_id_pkg::JTAG_IDCODE,
+ // parameters for rv_plic
+ // parameters for aes
+ parameter bit SecAesMasking = 1,
+ parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom,
+ parameter int unsigned SecAesStartTriggerDelay = 0,
+ parameter bit SecAesAllowForcingMasks = 1'b0,
+ parameter bit SecAesSkipPRNGReseeding = 1'b0,
+ // parameters for hmac
+ // parameters for kmac
+ parameter bit KmacEnMasking = 1,
+ parameter bit KmacSwKeyMasked = 0,
+ parameter int SecKmacCmdDelay = 0,
+ parameter bit SecKmacIdleAcceptSwMsg = 0,
+ // parameters for otbn
+ parameter bit OtbnStub = 0,
+ parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF,
+ parameter bit SecOtbnMuteUrnd = 0,
+ parameter bit SecOtbnSkipUrndReseedAtStart = 0,
+ // parameters for keymgr
+ parameter bit KeymgrKmacEnMasking = 1,
+ // parameters for csrng
+ parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright,
+ // parameters for entropy_src
+ parameter bit EntropySrcStub = 0,
+ // parameters for edn0
+ // parameters for edn1
+ // parameters for sram_ctrl_main
+ parameter bit SramCtrlMainInstrExec = 1,
+ // parameters for rom_ctrl
+ parameter RomCtrlBootRomInitFile = "",
+ parameter bit SecRomCtrlDisableScrambling = 1'b0,
+ // parameters for rv_core_ibex_sec
+ parameter bit RvCoreIbexSecPMPEnable = 1,
+ parameter int unsigned RvCoreIbexSecPMPGranularity = 0,
+ parameter int unsigned RvCoreIbexSecPMPNumRegions = 16,
+ parameter int unsigned RvCoreIbexSecMHPMCounterNum = 10,
+ parameter int unsigned RvCoreIbexSecMHPMCounterWidth = 32,
+ parameter bit RvCoreIbexSecRV32E = 0,
+ parameter ibex_pkg::rv32m_e RvCoreIbexSecRV32M = ibex_pkg::RV32MSingleCycle,
+ parameter ibex_pkg::rv32b_e RvCoreIbexSecRV32B = ibex_pkg::RV32BOTEarlGrey,
+ parameter ibex_pkg::regfile_e RvCoreIbexSecRegFile = ibex_pkg::RegFileFF,
+ parameter bit RvCoreIbexSecBranchTargetALU = 1,
+ parameter bit RvCoreIbexSecWritebackStage = 1,
+ parameter bit RvCoreIbexSecICache = 1,
+ parameter bit RvCoreIbexSecICacheECC = 1,
+ parameter bit RvCoreIbexSecICacheScramble = 1,
+ parameter bit RvCoreIbexSecBranchPredictor = 0,
+ parameter bit RvCoreIbexSecDbgTriggerEn = 1,
+ parameter int RvCoreIbexSecDbgHwBreakNum = 4,
+ parameter bit RvCoreIbexSecSecureIbex = 1,
+ parameter int unsigned RvCoreIbexSecDmHaltAddr =
+ tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0],
+ parameter int unsigned RvCoreIbexSecDmExceptionAddr =
+ tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0],
+ parameter bit RvCoreIbexSecPipeLine = 0,
+ // parameters for dma0
+ // parameters for smc_uart
+ // parameters for rv_timer_smc
+ // parameters for smc_ctrl
+ // parameters for cam_i2c
+ // parameters for cam_ctrl
+ // parameters for isp_wrapper
+ parameter int IspWrapperAhbLiteDataWidth = 32,
+ parameter int IspWrapperTimeoutLimit = 65535,
+ // parameters for dma_smc
+ // parameters for rv_plic_smc
+ // parameters for tlul_mailbox_sec
+ parameter int TlulMailboxSecMailboxDepth = 8,
+ // parameters for tlul_mailbox_smc
+ parameter int TlulMailboxSmcMailboxDepth = 8,
+ // parameters for ml_top
+ // parameters for spi_host2
+ // parameters for rv_timer_smc2
+ // parameters for i2s0
+ // parameters for rv_core_ibex_smc
+ parameter bit RvCoreIbexSmcPMPEnable = 0,
+ parameter int unsigned RvCoreIbexSmcPMPGranularity = 0,
+ parameter int unsigned RvCoreIbexSmcPMPNumRegions = 16,
+ parameter int unsigned RvCoreIbexSmcMHPMCounterNum = 10,
+ parameter int unsigned RvCoreIbexSmcMHPMCounterWidth = 32,
+ parameter bit RvCoreIbexSmcRV32E = 0,
+ parameter smc_pkg::rv32m_e RvCoreIbexSmcRV32M = smc_pkg::RV32MSingleCycle,
+ parameter smc_pkg::rv32b_e RvCoreIbexSmcRV32B = smc_pkg::RV32BNone,
+ parameter bit RvCoreIbexSmcRV32A = 1,
+ parameter smc_pkg::regfile_e RvCoreIbexSmcRegFile = smc_pkg::RegFileFF,
+ parameter bit RvCoreIbexSmcBranchTargetALU = 0,
+ parameter bit RvCoreIbexSmcWritebackStage = 0,
+ parameter bit RvCoreIbexSmcICache = 0,
+ parameter bit RvCoreIbexSmcICacheECC = 0,
+ parameter bit RvCoreIbexSmcICacheScramble = 0,
+ parameter bit RvCoreIbexSmcBranchPredictor = 0,
+ parameter bit RvCoreIbexSmcDbgTriggerEn = 1,
+ parameter int RvCoreIbexSmcDbgHwBreakNum = 1,
+ parameter bit RvCoreIbexSmcSecureSmc = 0,
+ parameter int unsigned RvCoreIbexSmcDmHaltAddr =
+ tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress[31:0],
+ parameter int unsigned RvCoreIbexSmcDmExceptionAddr =
+ tl_main_pkg::ADDR_SPACE_DBG + dm::ExceptionAddress[31:0],
+ parameter bit RvCoreIbexSmcPipeLine = 0,
+ parameter int RvCoreIbexSmcITLBEntries = 64,
+ parameter int RvCoreIbexSmcDTLBEntries = 64,
+ parameter int RvCoreIbexSmcASIDWidth = 9
+) (
+ // Multiplexed I/O
+ input [52:0] mio_in_i,
+ output logic [52:0] mio_out_o,
+ output logic [52:0] mio_oe_o,
+ // Dedicated I/O
+ input [15:0] dio_in_i,
+ output logic [15:0] dio_out_o,
+ output logic [15:0] dio_oe_o,
+
+ // pad attributes to padring
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o,
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o,
+
+
+ // Inter-module Signal External type
+ output ast_pkg::adc_ast_req_t adc_req_o,
+ input ast_pkg::adc_ast_rsp_t adc_rsp_i,
+ input edn_pkg::edn_req_t ast_edn_req_i,
+ output edn_pkg::edn_rsp_t ast_edn_rsp_o,
+ output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o,
+ input ast_pkg::ast_obs_ctrl_t obs_ctrl_i,
+ input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i,
+ input prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg_i,
+ input prim_rom_pkg::rom_cfg_t rom_cfg_i,
+ output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o,
+ output prim_mubi_pkg::mubi4_t io_clk_byp_req_o,
+ input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i,
+ output prim_mubi_pkg::mubi4_t all_clk_byp_req_o,
+ input prim_mubi_pkg::mubi4_t all_clk_byp_ack_i,
+ output prim_mubi_pkg::mubi4_t hi_speed_sel_o,
+ input prim_mubi_pkg::mubi4_t div_step_down_req_i,
+ input prim_mubi_pkg::mubi4_t calib_rdy_i,
+ input prim_mubi_pkg::mubi4_t flash_bist_enable_i,
+ input logic flash_power_down_h_i,
+ input logic flash_power_ready_h_i,
+ inout [1:0] flash_test_mode_a_io,
+ inout flash_test_voltage_h_io,
+ output logic [7:0] flash_obs_o,
+ output entropy_src_pkg::entropy_src_rng_req_t es_rng_req_o,
+ input entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp_i,
+ output logic es_rng_fips_o,
+ output tlul_pkg::tl_h2d_t ast_tl_req_o,
+ input tlul_pkg::tl_d2h_t ast_tl_rsp_i,
+ output pinmux_pkg::dft_strap_test_req_t dft_strap_test_o,
+ input logic dft_hold_tap_sel_i,
+ output logic usb_dp_pullup_en_o,
+ output logic usb_dn_pullup_en_o,
+ output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o,
+ input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i,
+ output otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq_o,
+ input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i,
+ inout otp_ext_voltage_h_io,
+ output logic [7:0] otp_obs_o,
+ input logic [1:0] por_n_i,
+ input logic [31:0] fpga_info_i,
+ input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i,
+ output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o,
+ input ast_pkg::ast_status_t sensor_ctrl_ast_status_i,
+ input logic [8:0] ast2pinmux_i,
+ input prim_mubi_pkg::mubi4_t ast_init_done_i,
+ output logic sck_monitor_o,
+ input logic usbdev_usb_rx_d_i,
+ output logic usbdev_usb_tx_d_o,
+ output logic usbdev_usb_tx_se0_o,
+ output logic usbdev_usb_tx_use_d_se0_o,
+ output logic usbdev_usb_rx_enable_o,
+ output logic usbdev_usb_ref_val_o,
+ output logic usbdev_usb_ref_pulse_o,
+
+
+ // All externally supplied clocks
+ input clk_main_i,
+ input clk_io_i,
+ input clk_usb_i,
+ input clk_aon_i,
+ input clk_ml_i,
+ input clk_smc_i,
+ input clk_video_i,
+ input clk_audio_i,
+
+ // All clocks forwarded to ast
+ output clkmgr_pkg::clkmgr_out_t clks_ast_o,
+ output rstmgr_pkg::rstmgr_out_t rsts_ast_o,
+
+ input scan_rst_ni, // reset used for test mode
+ input scan_en_i,
+ input prim_mubi_pkg::mubi4_t scanmode_i // lc_ctrl_pkg::On for Scan
+);
+
+ import tlul_pkg::*;
+ import top_pkg::*;
+ import tl_main_pkg::*;
+ import tl_smc_pkg::*;
+ import top_sencha_pkg::*;
+ // Compile-time random constants
+ import top_sencha_rnd_cnst_pkg::*;
+
+ // Signals
+ logic [75:0] mio_p2d;
+ logic [88:0] mio_d2p;
+ logic [88:0] mio_en_d2p;
+ logic [15:0] dio_p2d;
+ logic [15:0] dio_d2p;
+ logic [15:0] dio_en_d2p;
+ // uart0
+ logic cio_uart0_rx_p2d;
+ logic cio_uart0_tx_d2p;
+ logic cio_uart0_tx_en_d2p;
+ // uart1
+ logic cio_uart1_rx_p2d;
+ logic cio_uart1_tx_d2p;
+ logic cio_uart1_tx_en_d2p;
+ // uart2
+ logic cio_uart2_rx_p2d;
+ logic cio_uart2_tx_d2p;
+ logic cio_uart2_tx_en_d2p;
+ // uart3
+ logic cio_uart3_rx_p2d;
+ logic cio_uart3_tx_d2p;
+ logic cio_uart3_tx_en_d2p;
+ // gpio
+ logic [31:0] cio_gpio_gpio_p2d;
+ logic [31:0] cio_gpio_gpio_d2p;
+ logic [31:0] cio_gpio_gpio_en_d2p;
+ // spi_device
+ logic cio_spi_device_sck_p2d;
+ logic cio_spi_device_csb_p2d;
+ logic cio_spi_device_tpm_csb_p2d;
+ logic [3:0] cio_spi_device_sd_p2d;
+ logic [3:0] cio_spi_device_sd_d2p;
+ logic [3:0] cio_spi_device_sd_en_d2p;
+ // i2c0
+ logic cio_i2c0_sda_p2d;
+ logic cio_i2c0_scl_p2d;
+ logic cio_i2c0_sda_d2p;
+ logic cio_i2c0_sda_en_d2p;
+ logic cio_i2c0_scl_d2p;
+ logic cio_i2c0_scl_en_d2p;
+ // i2c1
+ logic cio_i2c1_sda_p2d;
+ logic cio_i2c1_scl_p2d;
+ logic cio_i2c1_sda_d2p;
+ logic cio_i2c1_sda_en_d2p;
+ logic cio_i2c1_scl_d2p;
+ logic cio_i2c1_scl_en_d2p;
+ // i2c2
+ logic cio_i2c2_sda_p2d;
+ logic cio_i2c2_scl_p2d;
+ logic cio_i2c2_sda_d2p;
+ logic cio_i2c2_sda_en_d2p;
+ logic cio_i2c2_scl_d2p;
+ logic cio_i2c2_scl_en_d2p;
+ // pattgen
+ logic cio_pattgen_pda0_tx_d2p;
+ logic cio_pattgen_pda0_tx_en_d2p;
+ logic cio_pattgen_pcl0_tx_d2p;
+ logic cio_pattgen_pcl0_tx_en_d2p;
+ logic cio_pattgen_pda1_tx_d2p;
+ logic cio_pattgen_pda1_tx_en_d2p;
+ logic cio_pattgen_pcl1_tx_d2p;
+ logic cio_pattgen_pcl1_tx_en_d2p;
+ // rv_timer
+ // otp_ctrl
+ logic [7:0] cio_otp_ctrl_test_d2p;
+ logic [7:0] cio_otp_ctrl_test_en_d2p;
+ // lc_ctrl
+ // alert_handler
+ // spi_host0
+ logic [3:0] cio_spi_host0_sd_p2d;
+ logic cio_spi_host0_sck_d2p;
+ logic cio_spi_host0_sck_en_d2p;
+ logic cio_spi_host0_csb_d2p;
+ logic cio_spi_host0_csb_en_d2p;
+ logic [3:0] cio_spi_host0_sd_d2p;
+ logic [3:0] cio_spi_host0_sd_en_d2p;
+ // spi_host1
+ logic [3:0] cio_spi_host1_sd_p2d;
+ logic cio_spi_host1_sck_d2p;
+ logic cio_spi_host1_sck_en_d2p;
+ logic cio_spi_host1_csb_d2p;
+ logic cio_spi_host1_csb_en_d2p;
+ logic [3:0] cio_spi_host1_sd_d2p;
+ logic [3:0] cio_spi_host1_sd_en_d2p;
+ // usbdev
+ logic cio_usbdev_sense_p2d;
+ logic cio_usbdev_usb_dp_p2d;
+ logic cio_usbdev_usb_dn_p2d;
+ logic cio_usbdev_usb_dp_d2p;
+ logic cio_usbdev_usb_dp_en_d2p;
+ logic cio_usbdev_usb_dn_d2p;
+ logic cio_usbdev_usb_dn_en_d2p;
+ // pwrmgr_aon
+ // rstmgr_aon
+ // clkmgr_aon
+ // sysrst_ctrl_aon
+ logic cio_sysrst_ctrl_aon_ac_present_p2d;
+ logic cio_sysrst_ctrl_aon_key0_in_p2d;
+ logic cio_sysrst_ctrl_aon_key1_in_p2d;
+ logic cio_sysrst_ctrl_aon_key2_in_p2d;
+ logic cio_sysrst_ctrl_aon_pwrb_in_p2d;
+ logic cio_sysrst_ctrl_aon_lid_open_p2d;
+ logic cio_sysrst_ctrl_aon_ec_rst_l_p2d;
+ logic cio_sysrst_ctrl_aon_flash_wp_l_p2d;
+ logic cio_sysrst_ctrl_aon_bat_disable_d2p;
+ logic cio_sysrst_ctrl_aon_bat_disable_en_d2p;
+ logic cio_sysrst_ctrl_aon_key0_out_d2p;
+ logic cio_sysrst_ctrl_aon_key0_out_en_d2p;
+ logic cio_sysrst_ctrl_aon_key1_out_d2p;
+ logic cio_sysrst_ctrl_aon_key1_out_en_d2p;
+ logic cio_sysrst_ctrl_aon_key2_out_d2p;
+ logic cio_sysrst_ctrl_aon_key2_out_en_d2p;
+ logic cio_sysrst_ctrl_aon_pwrb_out_d2p;
+ logic cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
+ logic cio_sysrst_ctrl_aon_z3_wakeup_d2p;
+ logic cio_sysrst_ctrl_aon_z3_wakeup_en_d2p;
+ logic cio_sysrst_ctrl_aon_ec_rst_l_d2p;
+ logic cio_sysrst_ctrl_aon_ec_rst_l_en_d2p;
+ logic cio_sysrst_ctrl_aon_flash_wp_l_d2p;
+ logic cio_sysrst_ctrl_aon_flash_wp_l_en_d2p;
+ // adc_ctrl_aon
+ // pwm_aon
+ logic [5:0] cio_pwm_aon_pwm_d2p;
+ logic [5:0] cio_pwm_aon_pwm_en_d2p;
+ // pinmux_aon
+ // aon_timer_aon
+ // sensor_ctrl
+ logic [8:0] cio_sensor_ctrl_ast_debug_out_d2p;
+ logic [8:0] cio_sensor_ctrl_ast_debug_out_en_d2p;
+ // sram_ctrl_ret_aon
+ // flash_ctrl
+ logic cio_flash_ctrl_tck_p2d;
+ logic cio_flash_ctrl_tms_p2d;
+ logic cio_flash_ctrl_tdi_p2d;
+ logic cio_flash_ctrl_tdo_d2p;
+ logic cio_flash_ctrl_tdo_en_d2p;
+ // rv_dm
+ // rv_plic
+ // aes
+ // hmac
+ // kmac
+ // otbn
+ // keymgr
+ // csrng
+ // entropy_src
+ // edn0
+ // edn1
+ // sram_ctrl_main
+ // rom_ctrl
+ // rv_core_ibex_sec
+ // dma0
+ // smc_uart
+ logic cio_smc_uart_rx_p2d;
+ logic cio_smc_uart_tx_d2p;
+ logic cio_smc_uart_tx_en_d2p;
+ // rv_timer_smc
+ // smc_ctrl
+ // cam_i2c
+ logic cio_cam_i2c_sda_p2d;
+ logic cio_cam_i2c_scl_p2d;
+ logic cio_cam_i2c_sda_d2p;
+ logic cio_cam_i2c_sda_en_d2p;
+ logic cio_cam_i2c_scl_d2p;
+ logic cio_cam_i2c_scl_en_d2p;
+ // cam_ctrl
+ logic cio_cam_ctrl_cam_int_p2d;
+ logic cio_cam_ctrl_cam_trig_d2p;
+ logic cio_cam_ctrl_cam_trig_en_d2p;
+ // isp_wrapper
+ logic cio_isp_wrapper_s_pclk_p2d;
+ logic [7:0] cio_isp_wrapper_s_data_p2d;
+ logic cio_isp_wrapper_s_hsync_p2d;
+ logic cio_isp_wrapper_s_vsync_p2d;
+ // dma_smc
+ // rv_plic_smc
+ // tlul_mailbox_sec
+ // tlul_mailbox_smc
+ // ml_top
+ // spi_host2
+ logic [3:0] cio_spi_host2_sd_p2d;
+ logic cio_spi_host2_sck_d2p;
+ logic cio_spi_host2_sck_en_d2p;
+ logic cio_spi_host2_csb_d2p;
+ logic cio_spi_host2_csb_en_d2p;
+ logic [3:0] cio_spi_host2_sd_d2p;
+ logic [3:0] cio_spi_host2_sd_en_d2p;
+ // rv_timer_smc2
+ // i2s0
+ logic cio_i2s0_rx_sd_p2d;
+ logic cio_i2s0_rx_sclk_d2p;
+ logic cio_i2s0_rx_sclk_en_d2p;
+ logic cio_i2s0_rx_ws_d2p;
+ logic cio_i2s0_rx_ws_en_d2p;
+ logic cio_i2s0_tx_sclk_d2p;
+ logic cio_i2s0_tx_sclk_en_d2p;
+ logic cio_i2s0_tx_ws_d2p;
+ logic cio_i2s0_tx_ws_en_d2p;
+ logic cio_i2s0_tx_sd_d2p;
+ logic cio_i2s0_tx_sd_en_d2p;
+ // rv_core_ibex_smc
+
+
+ logic [189:0] sec_intr_vector;
+ // Interrupt source list for Security core
+ logic intr_uart0_tx_watermark;
+ logic intr_uart0_rx_watermark;
+ logic intr_uart0_tx_empty;
+ logic intr_uart0_rx_overflow;
+ logic intr_uart0_rx_frame_err;
+ logic intr_uart0_rx_break_err;
+ logic intr_uart0_rx_timeout;
+ logic intr_uart0_rx_parity_err;
+ logic intr_uart1_tx_watermark;
+ logic intr_uart1_rx_watermark;
+ logic intr_uart1_tx_empty;
+ logic intr_uart1_rx_overflow;
+ logic intr_uart1_rx_frame_err;
+ logic intr_uart1_rx_break_err;
+ logic intr_uart1_rx_timeout;
+ logic intr_uart1_rx_parity_err;
+ logic intr_uart2_tx_watermark;
+ logic intr_uart2_rx_watermark;
+ logic intr_uart2_tx_empty;
+ logic intr_uart2_rx_overflow;
+ logic intr_uart2_rx_frame_err;
+ logic intr_uart2_rx_break_err;
+ logic intr_uart2_rx_timeout;
+ logic intr_uart2_rx_parity_err;
+ logic intr_uart3_tx_watermark;
+ logic intr_uart3_rx_watermark;
+ logic intr_uart3_tx_empty;
+ logic intr_uart3_rx_overflow;
+ logic intr_uart3_rx_frame_err;
+ logic intr_uart3_rx_break_err;
+ logic intr_uart3_rx_timeout;
+ logic intr_uart3_rx_parity_err;
+ logic [31:0] intr_gpio_gpio;
+ logic intr_spi_device_generic_rx_full;
+ logic intr_spi_device_generic_rx_watermark;
+ logic intr_spi_device_generic_tx_watermark;
+ logic intr_spi_device_generic_rx_error;
+ logic intr_spi_device_generic_rx_overflow;
+ logic intr_spi_device_generic_tx_underflow;
+ logic intr_spi_device_upload_cmdfifo_not_empty;
+ logic intr_spi_device_upload_payload_not_empty;
+ logic intr_spi_device_upload_payload_overflow;
+ logic intr_spi_device_readbuf_watermark;
+ logic intr_spi_device_readbuf_flip;
+ logic intr_spi_device_tpm_header_not_empty;
+ logic intr_i2c0_fmt_threshold;
+ logic intr_i2c0_rx_threshold;
+ logic intr_i2c0_fmt_overflow;
+ logic intr_i2c0_rx_overflow;
+ logic intr_i2c0_nak;
+ logic intr_i2c0_scl_interference;
+ logic intr_i2c0_sda_interference;
+ logic intr_i2c0_stretch_timeout;
+ logic intr_i2c0_sda_unstable;
+ logic intr_i2c0_cmd_complete;
+ logic intr_i2c0_tx_stretch;
+ logic intr_i2c0_tx_overflow;
+ logic intr_i2c0_acq_full;
+ logic intr_i2c0_unexp_stop;
+ logic intr_i2c0_host_timeout;
+ logic intr_i2c1_fmt_threshold;
+ logic intr_i2c1_rx_threshold;
+ logic intr_i2c1_fmt_overflow;
+ logic intr_i2c1_rx_overflow;
+ logic intr_i2c1_nak;
+ logic intr_i2c1_scl_interference;
+ logic intr_i2c1_sda_interference;
+ logic intr_i2c1_stretch_timeout;
+ logic intr_i2c1_sda_unstable;
+ logic intr_i2c1_cmd_complete;
+ logic intr_i2c1_tx_stretch;
+ logic intr_i2c1_tx_overflow;
+ logic intr_i2c1_acq_full;
+ logic intr_i2c1_unexp_stop;
+ logic intr_i2c1_host_timeout;
+ logic intr_i2c2_fmt_threshold;
+ logic intr_i2c2_rx_threshold;
+ logic intr_i2c2_fmt_overflow;
+ logic intr_i2c2_rx_overflow;
+ logic intr_i2c2_nak;
+ logic intr_i2c2_scl_interference;
+ logic intr_i2c2_sda_interference;
+ logic intr_i2c2_stretch_timeout;
+ logic intr_i2c2_sda_unstable;
+ logic intr_i2c2_cmd_complete;
+ logic intr_i2c2_tx_stretch;
+ logic intr_i2c2_tx_overflow;
+ logic intr_i2c2_acq_full;
+ logic intr_i2c2_unexp_stop;
+ logic intr_i2c2_host_timeout;
+ logic intr_pattgen_done_ch0;
+ logic intr_pattgen_done_ch1;
+ logic intr_rv_timer_timer_expired_hart0_timer0;
+ logic intr_otp_ctrl_otp_operation_done;
+ logic intr_otp_ctrl_otp_error;
+ logic intr_alert_handler_classa;
+ logic intr_alert_handler_classb;
+ logic intr_alert_handler_classc;
+ logic intr_alert_handler_classd;
+ logic intr_spi_host0_error;
+ logic intr_spi_host0_spi_event;
+ logic intr_spi_host1_error;
+ logic intr_spi_host1_spi_event;
+ logic intr_usbdev_pkt_received;
+ logic intr_usbdev_pkt_sent;
+ logic intr_usbdev_disconnected;
+ logic intr_usbdev_host_lost;
+ logic intr_usbdev_link_reset;
+ logic intr_usbdev_link_suspend;
+ logic intr_usbdev_link_resume;
+ logic intr_usbdev_av_empty;
+ logic intr_usbdev_rx_full;
+ logic intr_usbdev_av_overflow;
+ logic intr_usbdev_link_in_err;
+ logic intr_usbdev_rx_crc_err;
+ logic intr_usbdev_rx_pid_err;
+ logic intr_usbdev_rx_bitstuff_err;
+ logic intr_usbdev_frame;
+ logic intr_usbdev_powered;
+ logic intr_usbdev_link_out_err;
+ logic intr_pwrmgr_aon_wakeup;
+ logic intr_sysrst_ctrl_aon_event_detected;
+ logic intr_adc_ctrl_aon_match_done;
+ logic intr_aon_timer_aon_wkup_timer_expired;
+ logic intr_aon_timer_aon_wdog_timer_bark;
+ logic intr_sensor_ctrl_io_status_change;
+ logic intr_sensor_ctrl_init_status_change;
+ logic intr_flash_ctrl_prog_empty;
+ logic intr_flash_ctrl_prog_lvl;
+ logic intr_flash_ctrl_rd_full;
+ logic intr_flash_ctrl_rd_lvl;
+ logic intr_flash_ctrl_op_done;
+ logic intr_flash_ctrl_corr_err;
+ logic intr_hmac_hmac_done;
+ logic intr_hmac_fifo_empty;
+ logic intr_hmac_hmac_err;
+ logic intr_kmac_kmac_done;
+ logic intr_kmac_fifo_empty;
+ logic intr_kmac_kmac_err;
+ logic intr_otbn_done;
+ logic intr_keymgr_op_done;
+ logic intr_csrng_cs_cmd_req_done;
+ logic intr_csrng_cs_entropy_req;
+ logic intr_csrng_cs_hw_inst_exc;
+ logic intr_csrng_cs_fatal_err;
+ logic intr_entropy_src_es_entropy_valid;
+ logic intr_entropy_src_es_health_test_failed;
+ logic intr_entropy_src_es_observe_fifo_ready;
+ logic intr_entropy_src_es_fatal_err;
+ logic intr_edn0_edn_cmd_req_done;
+ logic intr_edn0_edn_fatal_err;
+ logic intr_edn1_edn_cmd_req_done;
+ logic intr_edn1_edn_fatal_err;
+ logic intr_dma0_writer_done;
+ logic intr_dma0_reader_done;
+ logic intr_tlul_mailbox_sec_wtirq;
+ logic intr_tlul_mailbox_sec_rtirq;
+ logic intr_tlul_mailbox_sec_eirq;
+
+ // smc_intr_vector for SMC core
+ logic [42:0] smc_intr_vector;
+ // Interrupt source list for SMC core
+ logic intr_smc_uart_tx_watermark;
+ logic intr_smc_uart_rx_watermark;
+ logic intr_smc_uart_tx_empty;
+ logic intr_smc_uart_rx_overflow;
+ logic intr_smc_uart_rx_frame_err;
+ logic intr_smc_uart_rx_break_err;
+ logic intr_smc_uart_rx_timeout;
+ logic intr_smc_uart_rx_parity_err;
+ logic intr_rv_timer_smc_timer_expired_hart0_timer0;
+ logic intr_cam_i2c_fmt_threshold;
+ logic intr_cam_i2c_rx_threshold;
+ logic intr_cam_i2c_fmt_overflow;
+ logic intr_cam_i2c_rx_overflow;
+ logic intr_cam_i2c_nak;
+ logic intr_cam_i2c_scl_interference;
+ logic intr_cam_i2c_sda_interference;
+ logic intr_cam_i2c_stretch_timeout;
+ logic intr_cam_i2c_sda_unstable;
+ logic intr_cam_i2c_cmd_complete;
+ logic intr_cam_i2c_tx_stretch;
+ logic intr_cam_i2c_tx_overflow;
+ logic intr_cam_i2c_acq_full;
+ logic intr_cam_i2c_unexp_stop;
+ logic intr_cam_i2c_host_timeout;
+ logic intr_cam_ctrl_cam_motion_detect;
+ logic intr_isp_wrapper_isp;
+ logic intr_isp_wrapper_mi;
+ logic intr_dma_smc_writer_done;
+ logic intr_dma_smc_reader_done;
+ logic intr_tlul_mailbox_smc_wtirq;
+ logic intr_tlul_mailbox_smc_rtirq;
+ logic intr_tlul_mailbox_smc_eirq;
+ logic intr_ml_top_host_req;
+ logic intr_ml_top_finish;
+ logic intr_ml_top_fault;
+ logic intr_spi_host2_error;
+ logic intr_spi_host2_spi_event;
+ logic intr_rv_timer_smc2_timer_expired_hart0_timer0;
+ logic intr_i2s0_tx_watermark;
+ logic intr_i2s0_rx_watermark;
+ logic intr_i2s0_tx_empty;
+ logic intr_i2s0_rx_overflow;
+
+
+ // Alert list
+ prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx;
+ prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx;
+
+
+ // define inter-module signals
+ ast_pkg::ast_obs_ctrl_t ast_obs_ctrl;
+ prim_ram_1p_pkg::ram_1p_cfg_t ast_ram_1p_cfg;
+ prim_ram_2p_pkg::ram_2p_cfg_t ast_ram_2p_cfg;
+ prim_rom_pkg::rom_cfg_t ast_rom_cfg;
+ alert_pkg::alert_crashdump_t alert_handler_crashdump;
+ prim_esc_pkg::esc_rx_t [3:0] alert_handler_esc_rx;
+ prim_esc_pkg::esc_tx_t [3:0] alert_handler_esc_tx;
+ logic aon_timer_aon_nmi_wdog_timer_bark;
+ csrng_pkg::csrng_req_t [1:0] csrng_csrng_cmd_req;
+ csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp;
+ entropy_src_pkg::entropy_src_hw_if_req_t csrng_entropy_src_hw_if_req;
+ entropy_src_pkg::entropy_src_hw_if_rsp_t csrng_entropy_src_hw_if_rsp;
+ entropy_src_pkg::cs_aes_halt_req_t csrng_cs_aes_halt_req;
+ entropy_src_pkg::cs_aes_halt_rsp_t csrng_cs_aes_halt_rsp;
+ flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr;
+ otp_ctrl_pkg::flash_otp_key_req_t flash_ctrl_otp_req;
+ otp_ctrl_pkg::flash_otp_key_rsp_t flash_ctrl_otp_rsp;
+ lc_ctrl_pkg::lc_flash_rma_seed_t flash_ctrl_rma_seed;
+ otp_ctrl_pkg::sram_otp_key_req_t [2:0] otp_ctrl_sram_otp_key_req;
+ otp_ctrl_pkg::sram_otp_key_rsp_t [2:0] otp_ctrl_sram_otp_key_rsp;
+ pwrmgr_pkg::pwr_flash_t pwrmgr_aon_pwr_flash;
+ pwrmgr_pkg::pwr_rst_req_t pwrmgr_aon_pwr_rst_req;
+ pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_aon_pwr_rst_rsp;
+ pwrmgr_pkg::pwr_clk_req_t pwrmgr_aon_pwr_clk_req;
+ pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_aon_pwr_clk_rsp;
+ pwrmgr_pkg::pwr_otp_req_t pwrmgr_aon_pwr_otp_req;
+ pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_aon_pwr_otp_rsp;
+ pwrmgr_pkg::pwr_lc_req_t pwrmgr_aon_pwr_lc_req;
+ pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_aon_pwr_lc_rsp;
+ logic pwrmgr_aon_strap;
+ logic pwrmgr_aon_low_power;
+ lc_ctrl_pkg::lc_tx_t pwrmgr_aon_fetch_en;
+ rom_ctrl_pkg::pwrmgr_data_t rom_ctrl_pwrmgr_data;
+ rom_ctrl_pkg::keymgr_data_t rom_ctrl_keymgr_data;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_flash_rma_req;
+ lc_ctrl_pkg::lc_tx_t flash_ctrl_rma_ack;
+ lc_ctrl_pkg::lc_tx_t otbn_lc_rma_ack;
+ logic usbdev_usb_dp_pullup;
+ logic usbdev_usb_dn_pullup;
+ logic usbdev_usb_aon_suspend_req;
+ logic usbdev_usb_aon_wake_ack;
+ logic usbdev_usb_aon_bus_reset;
+ logic usbdev_usb_aon_sense_lost;
+ logic pinmux_aon_usbdev_wake_detect_active;
+ logic isp_wrapper_isp_cvalid;
+ logic isp_wrapper_isp_cready;
+ logic isp_wrapper_isp_cwrite;
+ logic [21:0] isp_wrapper_isp_caddr;
+ logic [255:0] isp_wrapper_isp_wdata;
+ logic [31:0] isp_wrapper_isp_wmask;
+ logic isp_wrapper_isp_sp_cvalid;
+ logic isp_wrapper_isp_sp_cready;
+ logic isp_wrapper_isp_sp_cwrite;
+ logic [21:0] isp_wrapper_isp_sp_caddr;
+ logic [255:0] isp_wrapper_isp_sp_wdata;
+ logic [31:0] isp_wrapper_isp_sp_wmask;
+ edn_pkg::edn_req_t [7:0] edn0_edn_req;
+ edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp;
+ edn_pkg::edn_req_t [7:0] edn1_edn_req;
+ edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp;
+ otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req;
+ otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp;
+ otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key;
+ keymgr_pkg::hw_key_req_t keymgr_aes_key;
+ keymgr_pkg::hw_key_req_t keymgr_kmac_key;
+ keymgr_pkg::otbn_key_req_t keymgr_otbn_key;
+ kmac_pkg::app_req_t [2:0] kmac_app_req;
+ kmac_pkg::app_rsp_t [2:0] kmac_app_rsp;
+ logic kmac_en_masking;
+ prim_mubi_pkg::mubi4_t [3:0] clkmgr_aon_idle;
+ jtag_pkg::jtag_req_t pinmux_aon_lc_jtag_req;
+ jtag_pkg::jtag_rsp_t pinmux_aon_lc_jtag_rsp;
+ jtag_pkg::jtag_req_t pinmux_aon_rv_jtag_req;
+ jtag_pkg::jtag_rsp_t pinmux_aon_rv_jtag_rsp;
+ lc_ctrl_pkg::lc_tx_t pinmux_aon_pinmux_hw_debug_en;
+ otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data;
+ otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req;
+ otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp;
+ otp_ctrl_pkg::lc_otp_vendor_test_req_t lc_ctrl_lc_otp_vendor_test_req;
+ otp_ctrl_pkg::lc_otp_vendor_test_rsp_t lc_ctrl_lc_otp_vendor_test_rsp;
+ lc_ctrl_pkg::lc_keymgr_div_t lc_ctrl_lc_keymgr_div;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_dft_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_nvm_debug_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_hw_debug_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_cpu_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_keymgr_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_escalate_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_check_byp_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_req;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_ack;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_creator_seed_sw_rw_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_owner_seed_sw_rw_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_rd_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_wr_en;
+ lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_seed_hw_rd_en;
+ logic [1:0] rv_plic_msip;
+ logic [1:0] rv_plic_irq;
+ logic rv_plic_smc_msip;
+ logic rv_plic_smc_irq;
+ logic [2:0] rv_dm_debug_req;
+ rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_sec_crash_dump;
+ pwrmgr_pkg::pwr_cpu_t rv_core_ibex_sec_pwrmgr;
+ lc_ctrl_pkg::lc_tx_t rv_core_ibex_smc_pwrmgr_cpu_en;
+ spi_device_pkg::passthrough_req_t spi_device_passthrough_req;
+ spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp;
+ logic rv_dm_ndmreset_req;
+ prim_mubi_pkg::mubi4_t rstmgr_aon_sw_rst_req;
+ logic [5:0] pwrmgr_aon_wakeups;
+ logic [1:0] pwrmgr_aon_rstreqs;
+ tlul_pkg::tl_h2d_t main_tl_rv_core_ibex_sec__corei_req;
+ tlul_pkg::tl_d2h_t main_tl_rv_core_ibex_sec__corei_rsp;
+ tlul_pkg::tl_h2d_t main_tl_rv_core_ibex_sec__cored_req;
+ tlul_pkg::tl_d2h_t main_tl_rv_core_ibex_sec__cored_rsp;
+ tlul_pkg::tl_h2d_t main_tl_rv_dm__sba_req;
+ tlul_pkg::tl_d2h_t main_tl_rv_dm__sba_rsp;
+ tlul_pkg::tl_h2d_t main_tl_dma0__reader_req;
+ tlul_pkg::tl_d2h_t main_tl_dma0__reader_rsp;
+ tlul_pkg::tl_h2d_t main_tl_dma0__writer_req;
+ tlul_pkg::tl_d2h_t main_tl_dma0__writer_rsp;
+ tlul_pkg::tl_h2d_t dma0_tl_d_req;
+ tlul_pkg::tl_d2h_t dma0_tl_d_rsp;
+ tlul_pkg::tl_h2d_t rom_ctrl_rom_tl_req;
+ tlul_pkg::tl_d2h_t rom_ctrl_rom_tl_rsp;
+ tlul_pkg::tl_h2d_t rom_ctrl_regs_tl_req;
+ tlul_pkg::tl_d2h_t rom_ctrl_regs_tl_rsp;
+ tlul_pkg::tl_h2d_t main_tl_peri_req;
+ tlul_pkg::tl_d2h_t main_tl_peri_rsp;
+ tlul_pkg::tl_h2d_t spi_host0_tl_req;
+ tlul_pkg::tl_d2h_t spi_host0_tl_rsp;
+ tlul_pkg::tl_h2d_t spi_host1_tl_req;
+ tlul_pkg::tl_d2h_t spi_host1_tl_rsp;
+ tlul_pkg::tl_h2d_t usbdev_tl_req;
+ tlul_pkg::tl_d2h_t usbdev_tl_rsp;
+ tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req;
+ tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp;
+ tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req;
+ tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp;
+ tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req;
+ tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp;
+ tlul_pkg::tl_h2d_t hmac_tl_req;
+ tlul_pkg::tl_d2h_t hmac_tl_rsp;
+ tlul_pkg::tl_h2d_t kmac_tl_req;
+ tlul_pkg::tl_d2h_t kmac_tl_rsp;
+ tlul_pkg::tl_h2d_t aes_tl_req;
+ tlul_pkg::tl_d2h_t aes_tl_rsp;
+ tlul_pkg::tl_h2d_t entropy_src_tl_req;
+ tlul_pkg::tl_d2h_t entropy_src_tl_rsp;
+ tlul_pkg::tl_h2d_t csrng_tl_req;
+ tlul_pkg::tl_d2h_t csrng_tl_rsp;
+ tlul_pkg::tl_h2d_t edn0_tl_req;
+ tlul_pkg::tl_d2h_t edn0_tl_rsp;
+ tlul_pkg::tl_h2d_t edn1_tl_req;
+ tlul_pkg::tl_d2h_t edn1_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_plic_tl_req;
+ tlul_pkg::tl_d2h_t rv_plic_tl_rsp;
+ tlul_pkg::tl_h2d_t otbn_tl_req;
+ tlul_pkg::tl_d2h_t otbn_tl_rsp;
+ tlul_pkg::tl_h2d_t keymgr_tl_req;
+ tlul_pkg::tl_d2h_t keymgr_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_core_ibex_sec_cfg_tl_d_req;
+ tlul_pkg::tl_d2h_t rv_core_ibex_sec_cfg_tl_d_rsp;
+ tlul_pkg::tl_h2d_t sram_ctrl_main_regs_tl_req;
+ tlul_pkg::tl_d2h_t sram_ctrl_main_regs_tl_rsp;
+ tlul_pkg::tl_h2d_t sram_ctrl_main_ram_tl_req;
+ tlul_pkg::tl_d2h_t sram_ctrl_main_ram_tl_rsp;
+ tlul_pkg::tl_h2d_t tlul_mailbox_sec_tl_req;
+ tlul_pkg::tl_d2h_t tlul_mailbox_sec_tl_rsp;
+ tlul_pkg::tl_h2d_t main_tl_smc_req;
+ tlul_pkg::tl_d2h_t main_tl_smc_rsp;
+ tlul_pkg::tl_h2d_t main_tl_dbg_req;
+ tlul_pkg::tl_d2h_t main_tl_dbg_rsp;
+ tlul_pkg::tl_h2d_t uart0_tl_req;
+ tlul_pkg::tl_d2h_t uart0_tl_rsp;
+ tlul_pkg::tl_h2d_t uart1_tl_req;
+ tlul_pkg::tl_d2h_t uart1_tl_rsp;
+ tlul_pkg::tl_h2d_t uart2_tl_req;
+ tlul_pkg::tl_d2h_t uart2_tl_rsp;
+ tlul_pkg::tl_h2d_t uart3_tl_req;
+ tlul_pkg::tl_d2h_t uart3_tl_rsp;
+ tlul_pkg::tl_h2d_t i2c0_tl_req;
+ tlul_pkg::tl_d2h_t i2c0_tl_rsp;
+ tlul_pkg::tl_h2d_t i2c1_tl_req;
+ tlul_pkg::tl_d2h_t i2c1_tl_rsp;
+ tlul_pkg::tl_h2d_t i2c2_tl_req;
+ tlul_pkg::tl_d2h_t i2c2_tl_rsp;
+ tlul_pkg::tl_h2d_t pattgen_tl_req;
+ tlul_pkg::tl_d2h_t pattgen_tl_rsp;
+ tlul_pkg::tl_h2d_t pwm_aon_tl_req;
+ tlul_pkg::tl_d2h_t pwm_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t gpio_tl_req;
+ tlul_pkg::tl_d2h_t gpio_tl_rsp;
+ tlul_pkg::tl_h2d_t spi_device_tl_req;
+ tlul_pkg::tl_d2h_t spi_device_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_timer_tl_req;
+ tlul_pkg::tl_d2h_t rv_timer_tl_rsp;
+ tlul_pkg::tl_h2d_t pwrmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t pwrmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t rstmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t rstmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t clkmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t pinmux_aon_tl_req;
+ tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t otp_ctrl_core_tl_req;
+ tlul_pkg::tl_d2h_t otp_ctrl_core_tl_rsp;
+ tlul_pkg::tl_h2d_t otp_ctrl_prim_tl_req;
+ tlul_pkg::tl_d2h_t otp_ctrl_prim_tl_rsp;
+ tlul_pkg::tl_h2d_t lc_ctrl_tl_req;
+ tlul_pkg::tl_d2h_t lc_ctrl_tl_rsp;
+ tlul_pkg::tl_h2d_t sensor_ctrl_tl_req;
+ tlul_pkg::tl_d2h_t sensor_ctrl_tl_rsp;
+ tlul_pkg::tl_h2d_t alert_handler_tl_req;
+ tlul_pkg::tl_d2h_t alert_handler_tl_rsp;
+ tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_regs_tl_req;
+ tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_regs_tl_rsp;
+ tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_ram_tl_req;
+ tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_ram_tl_rsp;
+ tlul_pkg::tl_h2d_t aon_timer_aon_tl_req;
+ tlul_pkg::tl_d2h_t aon_timer_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t sysrst_ctrl_aon_tl_req;
+ tlul_pkg::tl_d2h_t sysrst_ctrl_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t adc_ctrl_aon_tl_req;
+ tlul_pkg::tl_d2h_t adc_ctrl_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t smc_tl_rv_core_ibex_smc__corei_req;
+ tlul_pkg::tl_d2h_t smc_tl_rv_core_ibex_smc__corei_rsp;
+ tlul_pkg::tl_h2d_t smc_tl_rv_core_ibex_smc__cored_req;
+ tlul_pkg::tl_d2h_t smc_tl_rv_core_ibex_smc__cored_rsp;
+ tlul_pkg::tl_h2d_t smc_tl_dma_smc__reader_req;
+ tlul_pkg::tl_d2h_t smc_tl_dma_smc__reader_rsp;
+ tlul_pkg::tl_h2d_t smc_tl_dma_smc__writer_req;
+ tlul_pkg::tl_d2h_t smc_tl_dma_smc__writer_rsp;
+ tlul_pkg::tl_h2d_t rv_plic_smc_tl_req;
+ tlul_pkg::tl_d2h_t rv_plic_smc_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_core_ibex_smc_cfg_tl_d_req;
+ tlul_pkg::tl_d2h_t rv_core_ibex_smc_cfg_tl_d_rsp;
+ tlul_pkg::tl_h2d_t ram_smc_tl_req;
+ tlul_pkg::tl_d2h_t ram_smc_tl_rsp;
+ tlul_pkg::tl_h2d_t smc_uart_tl_req;
+ tlul_pkg::tl_d2h_t smc_uart_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_timer_smc_tl_req;
+ tlul_pkg::tl_d2h_t rv_timer_smc_tl_rsp;
+ tlul_pkg::tl_h2d_t tlul_mailbox_smc_tl_req;
+ tlul_pkg::tl_d2h_t tlul_mailbox_smc_tl_rsp;
+ tlul_pkg::tl_h2d_t smc_ctrl_tl_req;
+ tlul_pkg::tl_d2h_t smc_ctrl_tl_rsp;
+ tlul_pkg::tl_h2d_t cam_i2c_tl_req;
+ tlul_pkg::tl_d2h_t cam_i2c_tl_rsp;
+ tlul_pkg::tl_h2d_t cam_ctrl_tl_req;
+ tlul_pkg::tl_d2h_t cam_ctrl_tl_rsp;
+ tlul_pkg::tl_h2d_t ml_top_dmem_tl_req;
+ tlul_pkg::tl_d2h_t ml_top_dmem_tl_rsp;
+ tlul_pkg::tl_h2d_t ml_top_core_tl_req;
+ tlul_pkg::tl_d2h_t ml_top_core_tl_rsp;
+ tlul_pkg::tl_h2d_t isp_wrapper_tl_req;
+ tlul_pkg::tl_d2h_t isp_wrapper_tl_rsp;
+ tlul_pkg::tl_h2d_t dma_smc_tl_d_req;
+ tlul_pkg::tl_d2h_t dma_smc_tl_d_rsp;
+ tlul_pkg::tl_h2d_t spi_host2_tl_req;
+ tlul_pkg::tl_d2h_t spi_host2_tl_rsp;
+ tlul_pkg::tl_h2d_t smc_tl_dbg_req;
+ tlul_pkg::tl_d2h_t smc_tl_dbg_rsp;
+ tlul_pkg::tl_h2d_t rv_timer_smc2_tl_req;
+ tlul_pkg::tl_d2h_t rv_timer_smc2_tl_rsp;
+ tlul_pkg::tl_h2d_t i2s0_tl_req;
+ tlul_pkg::tl_d2h_t i2s0_tl_rsp;
+ tlul_pkg::tl_h2d_t rv_dm_regs_tl_d_req;
+ tlul_pkg::tl_d2h_t rv_dm_regs_tl_d_rsp;
+ tlul_pkg::tl_h2d_t rv_dm_mem_tl_d_req;
+ tlul_pkg::tl_d2h_t rv_dm_mem_tl_d_rsp;
+ clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
+ clkmgr_pkg::clkmgr_cg_en_t clkmgr_aon_cg_en;
+ rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
+ rstmgr_pkg::rstmgr_rst_en_t rstmgr_aon_rst_en;
+ logic rv_core_ibex_sec_irq_timer;
+ logic rv_core_ibex_smc_irq_timer;
+ logic [31:0] rv_core_ibex_sec_hart_id;
+ logic [31:0] rv_core_ibex_sec_boot_addr;
+ logic [31:0] rv_core_ibex_smc_hart_id;
+ logic [31:0] rv_core_ibex_smc_boot_addr;
+ jtag_pkg::jtag_req_t pinmux_aon_dft_jtag_req;
+ jtag_pkg::jtag_rsp_t pinmux_aon_dft_jtag_rsp;
+ otp_ctrl_part_pkg::otp_hw_cfg_t otp_ctrl_otp_hw_cfg;
+ prim_mubi_pkg::mubi8_t csrng_otp_en_csrng_sw_app_read;
+ prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_read;
+ prim_mubi_pkg::mubi8_t entropy_src_otp_en_entropy_src_fw_over;
+ otp_ctrl_pkg::otp_device_id_t lc_ctrl_otp_device_id;
+ otp_ctrl_pkg::otp_manuf_state_t lc_ctrl_otp_manuf_state;
+ otp_ctrl_pkg::otp_device_id_t keymgr_otp_device_id;
+ prim_mubi_pkg::mubi8_t sram_ctrl_main_otp_en_sram_ifetch;
+
+ // define mixed connection to port
+ assign edn0_edn_req[2] = ast_edn_req_i;
+ assign ast_edn_rsp_o = edn0_edn_rsp[2];
+ assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en;
+ assign ast_obs_ctrl = obs_ctrl_i;
+ assign ast_ram_1p_cfg = ram_1p_cfg_i;
+ assign ast_ram_2p_cfg = ram_2p_cfg_i;
+ assign ast_rom_cfg = rom_cfg_i;
+
+ // define partial inter-module tie-off
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp1;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp2;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp3;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp4;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp5;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp6;
+ edn_pkg::edn_rsp_t unused_edn1_edn_rsp7;
+
+ // assign partial inter-module tie-off
+ assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1];
+ assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2];
+ assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3];
+ assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4];
+ assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5];
+ assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6];
+ assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7];
+ assign edn1_edn_req[1] = '0;
+ assign edn1_edn_req[2] = '0;
+ assign edn1_edn_req[3] = '0;
+ assign edn1_edn_req[4] = '0;
+ assign edn1_edn_req[5] = '0;
+ assign edn1_edn_req[6] = '0;
+ assign edn1_edn_req[7] = '0;
+
+
+ // OTP HW_CFG Broadcast signals.
+ // TODO(#6713): The actual struct breakout and mapping currently needs to
+ // be performed by hand.
+ assign csrng_otp_en_csrng_sw_app_read = otp_ctrl_otp_hw_cfg.data.en_csrng_sw_app_read;
+ assign entropy_src_otp_en_entropy_src_fw_read = otp_ctrl_otp_hw_cfg.data.en_entropy_src_fw_read;
+ assign entropy_src_otp_en_entropy_src_fw_over = otp_ctrl_otp_hw_cfg.data.en_entropy_src_fw_over;
+ assign sram_ctrl_main_otp_en_sram_ifetch = otp_ctrl_otp_hw_cfg.data.en_sram_ifetch;
+ assign lc_ctrl_otp_device_id = otp_ctrl_otp_hw_cfg.data.device_id;
+ assign lc_ctrl_otp_manuf_state = otp_ctrl_otp_hw_cfg.data.manuf_state;
+ assign keymgr_otp_device_id = otp_ctrl_otp_hw_cfg.data.device_id;
+
+ logic unused_otp_hw_cfg_bits;
+ assign unused_otp_hw_cfg_bits = ^{
+ otp_ctrl_otp_hw_cfg.valid,
+ otp_ctrl_otp_hw_cfg.data.hw_cfg_digest,
+ otp_ctrl_otp_hw_cfg.data.unallocated
+ };
+
+ // See #7978 This below is a hack.
+ // This is because ast is a comportable-like module that sits outside
+ // of top_sencha's boundary.
+ assign clks_ast_o = clkmgr_aon_clocks;
+ assign rsts_ast_o = rstmgr_aon_resets;
+
+ // ibex specific assignments
+ // TODO(b/271173103).
+ assign rv_core_ibex_sec_irq_timer = intr_rv_timer_timer_expired_hart0_timer0;
+ assign rv_core_ibex_sec_hart_id = 0;
+
+ assign rv_core_ibex_smc_irq_timer = intr_rv_timer_smc_timer_expired_hart0_timer0;
+ assign rv_core_ibex_smc_hart_id = 1;
+
+ assign rv_core_ibex_sec_boot_addr = ADDR_SPACE_ROM_CTRL__ROM;
+ assign rv_core_ibex_smc_boot_addr = ADDR_SPACE_RAM_SMC;
+
+
+ // Struct breakout module tool-inserted DFT TAP signals
+ pinmux_jtag_breakout u_dft_tap_breakout (
+ .req_i (pinmux_aon_dft_jtag_req),
+ .rsp_o (pinmux_aon_dft_jtag_rsp),
+ .tck_o (),
+ .trst_no (),
+ .tms_o (),
+ .tdi_o (),
+ .tdo_i (1'b0),
+ .tdo_oe_i (1'b0)
+ );
+
+ // sram device
+ logic ram_smc_req;
+ logic ram_smc_we;
+ logic [19:0] ram_smc_addr;
+ logic [31:0] ram_smc_wdata;
+ logic [31:0] ram_smc_wmask;
+ logic [31:0] ram_smc_rdata;
+ logic ram_smc_rvalid;
+ logic [1:0] ram_smc_rerror;
+
+ tluh_adapter_sram #(
+ .MemLatency(1),
+ .MaxBurstSize(2)
+ ) u_tl_adapter_ram_smc (
+ .clk_i (clkmgr_aon_clocks.clk_smc_infra),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]),
+ .tl_i (ram_smc_tl_req),
+ .tl_o (ram_smc_tl_rsp),
+
+ .req_o (ram_smc_req),
+ .gnt_i (ram_smc_req), // Grant when requests occur
+ .we_o (ram_smc_we),
+ .addr_o (ram_smc_addr),
+ .wdata_o (ram_smc_wdata),
+ .wmask_o (ram_smc_wmask),
+ .rdata_i (ram_smc_rdata),
+ .rvalid_i (ram_smc_rvalid),
+ .err_i (ram_smc_rerror[0])
+ );
+
+ prim_ram_1p_adv #(
+ .Width(32),
+ .Depth(1048576),
+ .DataBitsPerMask(8),
+ // TODO: enable parity once supported by the simulation infrastructure
+ .EnableParity(0)
+ ) u_ram1p_ram_smc (
+ .clk_i (clkmgr_aon_clocks.clk_smc_infra),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]),
+ .req_i (ram_smc_req),
+ .write_i (ram_smc_we),
+ .addr_i (ram_smc_addr),
+ .wdata_i (ram_smc_wdata),
+ .wmask_i (ram_smc_wmask),
+ .rdata_o (ram_smc_rdata),
+ .rvalid_o (ram_smc_rvalid),
+ .rerror_o (ram_smc_rerror),
+ .cfg_i ('0)
+ );
+
+ // Wire up alert handler LPGs
+ prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_cg_en;
+ prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_rst_en;
+
+
+ // peri_lc_io_div4_0
+ assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ // peri_spi_device_0
+ assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel];
+ // peri_i2c0_0
+ assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel];
+ // peri_i2c1_0
+ assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[3] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel];
+ // peri_i2c2_0
+ assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel];
+ // timers_lc_io_div4_0
+ assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers;
+ assign lpg_rst_en[5] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ // secure_lc_io_div4_0
+ assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_secure;
+ assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ // peri_spi_host0_0
+ assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_peri;
+ assign lpg_rst_en[7] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel];
+ // peri_spi_host1_0
+ assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_peri;
+ assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel];
+ // peri_usb_0
+ assign lpg_cg_en[9] = clkmgr_aon_cg_en.usb_peri;
+ assign lpg_rst_en[9] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel];
+ // powerup_por_io_div4_Aon
+ assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup;
+ assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel];
+ // powerup_lc_io_div4_Aon
+ assign lpg_cg_en[11] = clkmgr_aon_cg_en.io_div4_powerup;
+ assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
+ // secure_lc_io_div4_Aon
+ assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_secure;
+ assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
+ // peri_lc_io_div4_Aon
+ assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
+ // timers_lc_io_div4_Aon
+ assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_timers;
+ assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
+ // infra_lc_io_div4_0
+ assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_infra;
+ assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
+ // infra_lc_io_div4_Aon
+ assign lpg_cg_en[16] = clkmgr_aon_cg_en.io_div4_infra;
+ assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
+ // infra_lc_0
+ assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_infra;
+ assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // infra_sys_0
+ assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_infra;
+ assign lpg_rst_en[18] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel];
+ // secure_lc_0
+ assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure;
+ assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // aes_trans_lc_0
+ assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes;
+ assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // hmac_trans_lc_0
+ assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac;
+ assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // kmac_trans_lc_0
+ assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac;
+ assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // otbn_trans_lc_0
+ assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn;
+ assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
+ // secure_smc_0
+ assign lpg_cg_en[24] = clkmgr_aon_cg_en.smc_secure;
+ assign lpg_rst_en[24] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel];
+ // peri_cam_i2c_0
+ assign lpg_cg_en[25] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[25] = rstmgr_aon_rst_en.cam_i2c[rstmgr_pkg::Domain0Sel];
+ // peri_smc_0
+ assign lpg_cg_en[26] = clkmgr_aon_cg_en.video_peri;
+ assign lpg_rst_en[26] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel];
+ // infra_smc_0
+ assign lpg_cg_en[27] = clkmgr_aon_cg_en.smc_infra;
+ assign lpg_rst_en[27] = rstmgr_aon_rst_en.smc[rstmgr_pkg::Domain0Sel];
+ // peri_ml_0
+ assign lpg_cg_en[28] = clkmgr_aon_cg_en.ml_peri;
+ assign lpg_rst_en[28] = rstmgr_aon_rst_en.ml[rstmgr_pkg::Domain0Sel];
+ // peri_spi_host2_0
+ assign lpg_cg_en[29] = clkmgr_aon_cg_en.io_peri;
+ assign lpg_rst_en[29] = rstmgr_aon_rst_en.spi_host2[rstmgr_pkg::Domain0Sel];
+ // timers_sys_io_div4_0
+ assign lpg_cg_en[30] = clkmgr_aon_cg_en.io_div4_timers;
+ assign lpg_rst_en[30] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
+ // peri_sys_io_div4_0
+ assign lpg_cg_en[31] = clkmgr_aon_cg_en.io_div4_peri;
+ assign lpg_rst_en[31] = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
+
+// tie-off unused connections
+//VCS coverage off
+// pragma coverage off
+ prim_mubi_pkg::mubi4_t unused_cg_en_0;
+ assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_1;
+ assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_2;
+ assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_3;
+ assign unused_cg_en_3 = clkmgr_aon_cg_en.usb_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_4;
+ assign unused_cg_en_4 = clkmgr_aon_cg_en.io_div2_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_5;
+ assign unused_cg_en_5 = clkmgr_aon_cg_en.smc_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_6;
+ assign unused_cg_en_6 = clkmgr_aon_cg_en.ml_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_7;
+ assign unused_cg_en_7 = clkmgr_aon_cg_en.video_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_8;
+ assign unused_cg_en_8 = clkmgr_aon_cg_en.audio_powerup;
+ prim_mubi_pkg::mubi4_t unused_cg_en_9;
+ assign unused_cg_en_9 = clkmgr_aon_cg_en.aon_secure;
+ prim_mubi_pkg::mubi4_t unused_cg_en_10;
+ assign unused_cg_en_10 = clkmgr_aon_cg_en.aon_peri;
+ prim_mubi_pkg::mubi4_t unused_cg_en_11;
+ assign unused_cg_en_11 = clkmgr_aon_cg_en.aon_timers;
+ prim_mubi_pkg::mubi4_t unused_cg_en_12;
+ assign unused_cg_en_12 = clkmgr_aon_cg_en.usb_infra;
+ prim_mubi_pkg::mubi4_t unused_cg_en_13;
+ assign unused_cg_en_13 = clkmgr_aon_cg_en.io_infra;
+ prim_mubi_pkg::mubi4_t unused_cg_en_14;
+ assign unused_cg_en_14 = clkmgr_aon_cg_en.ml_infra;
+ prim_mubi_pkg::mubi4_t unused_cg_en_15;
+ assign unused_cg_en_15 = clkmgr_aon_cg_en.video_infra;
+ prim_mubi_pkg::mubi4_t unused_cg_en_16;
+ assign unused_cg_en_16 = clkmgr_aon_cg_en.audio_infra;
+ prim_mubi_pkg::mubi4_t unused_cg_en_17;
+ assign unused_cg_en_17 = clkmgr_aon_cg_en.io_div2_peri;
+ prim_mubi_pkg::mubi4_t unused_cg_en_18;
+ assign unused_cg_en_18 = clkmgr_aon_cg_en.audio_peri;
+ prim_mubi_pkg::mubi4_t unused_cg_en_19;
+ assign unused_cg_en_19 = clkmgr_aon_cg_en.smc_peri;
+ prim_mubi_pkg::mubi4_t unused_rst_en_0;
+ assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_1;
+ assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_2;
+ assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_3;
+ assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_4;
+ assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_5;
+ assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_6;
+ assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_7;
+ assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_8;
+ assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_9;
+ assign unused_rst_en_9 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_10;
+ assign unused_rst_en_10 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_11;
+ assign unused_rst_en_11 = rstmgr_aon_rst_en.por_smc[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_12;
+ assign unused_rst_en_12 = rstmgr_aon_rst_en.por_smc[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_13;
+ assign unused_rst_en_13 = rstmgr_aon_rst_en.por_ml[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_14;
+ assign unused_rst_en_14 = rstmgr_aon_rst_en.por_ml[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_15;
+ assign unused_rst_en_15 = rstmgr_aon_rst_en.por_video[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_16;
+ assign unused_rst_en_16 = rstmgr_aon_rst_en.por_video[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_17;
+ assign unused_rst_en_17 = rstmgr_aon_rst_en.por_audio[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_18;
+ assign unused_rst_en_18 = rstmgr_aon_rst_en.por_audio[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_19;
+ assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_20;
+ assign unused_rst_en_20 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_21;
+ assign unused_rst_en_21 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_22;
+ assign unused_rst_en_22 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_23;
+ assign unused_rst_en_23 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_24;
+ assign unused_rst_en_24 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_25;
+ assign unused_rst_en_25 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_26;
+ assign unused_rst_en_26 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_27;
+ assign unused_rst_en_27 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_28;
+ assign unused_rst_en_28 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_29;
+ assign unused_rst_en_29 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_30;
+ assign unused_rst_en_30 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_31;
+ assign unused_rst_en_31 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_32;
+ assign unused_rst_en_32 = rstmgr_aon_rst_en.lc_smc[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_33;
+ assign unused_rst_en_33 = rstmgr_aon_rst_en.lc_smc[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_34;
+ assign unused_rst_en_34 = rstmgr_aon_rst_en.lc_ml[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_35;
+ assign unused_rst_en_35 = rstmgr_aon_rst_en.lc_ml[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_36;
+ assign unused_rst_en_36 = rstmgr_aon_rst_en.lc_video[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_37;
+ assign unused_rst_en_37 = rstmgr_aon_rst_en.lc_video[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_38;
+ assign unused_rst_en_38 = rstmgr_aon_rst_en.lc_audio[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_39;
+ assign unused_rst_en_39 = rstmgr_aon_rst_en.lc_audio[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_40;
+ assign unused_rst_en_40 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_41;
+ assign unused_rst_en_41 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_42;
+ assign unused_rst_en_42 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_43;
+ assign unused_rst_en_43 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_44;
+ assign unused_rst_en_44 = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_45;
+ assign unused_rst_en_45 = rstmgr_aon_rst_en.spi_host2[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_46;
+ assign unused_rst_en_46 = rstmgr_aon_rst_en.usb[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_47;
+ assign unused_rst_en_47 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_48;
+ assign unused_rst_en_48 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_49;
+ assign unused_rst_en_49 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_50;
+ assign unused_rst_en_50 = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_51;
+ assign unused_rst_en_51 = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_52;
+ assign unused_rst_en_52 = rstmgr_aon_rst_en.smc[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_53;
+ assign unused_rst_en_53 = rstmgr_aon_rst_en.ml[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_54;
+ assign unused_rst_en_54 = rstmgr_aon_rst_en.cam_i2c[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_55;
+ assign unused_rst_en_55 = rstmgr_aon_rst_en.video[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_56;
+ assign unused_rst_en_56 = rstmgr_aon_rst_en.video[rstmgr_pkg::Domain0Sel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_57;
+ assign unused_rst_en_57 = rstmgr_aon_rst_en.audio[rstmgr_pkg::DomainAonSel];
+ prim_mubi_pkg::mubi4_t unused_rst_en_58;
+ assign unused_rst_en_58 = rstmgr_aon_rst_en.audio[rstmgr_pkg::Domain0Sel];
+//VCS coverage on
+// pragma coverage on
+
+ // Peripheral Instantiation
+
+ uart #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
+ ) u_uart0 (
+
+ // Input
+ .cio_rx_i (cio_uart0_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart0_tx_d2p),
+ .cio_tx_en_o (cio_uart0_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart0_tx_watermark),
+ .intr_rx_watermark_o (intr_uart0_rx_watermark),
+ .intr_tx_empty_o (intr_uart0_tx_empty),
+ .intr_rx_overflow_o (intr_uart0_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart0_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart0_rx_break_err),
+ .intr_rx_timeout_o (intr_uart0_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart0_rx_parity_err),
+ // [0]: fatal_fault
+ .alert_tx_o ( alert_tx[0:0] ),
+ .alert_rx_i ( alert_rx[0:0] ),
+
+ // Inter-module signals
+ .tl_i(uart0_tl_req),
+ .tl_o(uart0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ uart #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
+ ) u_uart1 (
+
+ // Input
+ .cio_rx_i (cio_uart1_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart1_tx_d2p),
+ .cio_tx_en_o (cio_uart1_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart1_tx_watermark),
+ .intr_rx_watermark_o (intr_uart1_rx_watermark),
+ .intr_tx_empty_o (intr_uart1_tx_empty),
+ .intr_rx_overflow_o (intr_uart1_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart1_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart1_rx_break_err),
+ .intr_rx_timeout_o (intr_uart1_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart1_rx_parity_err),
+ // [1]: fatal_fault
+ .alert_tx_o ( alert_tx[1:1] ),
+ .alert_rx_i ( alert_rx[1:1] ),
+
+ // Inter-module signals
+ .tl_i(uart1_tl_req),
+ .tl_o(uart1_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ uart #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
+ ) u_uart2 (
+
+ // Input
+ .cio_rx_i (cio_uart2_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart2_tx_d2p),
+ .cio_tx_en_o (cio_uart2_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart2_tx_watermark),
+ .intr_rx_watermark_o (intr_uart2_rx_watermark),
+ .intr_tx_empty_o (intr_uart2_tx_empty),
+ .intr_rx_overflow_o (intr_uart2_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart2_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart2_rx_break_err),
+ .intr_rx_timeout_o (intr_uart2_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart2_rx_parity_err),
+ // [2]: fatal_fault
+ .alert_tx_o ( alert_tx[2:2] ),
+ .alert_rx_i ( alert_rx[2:2] ),
+
+ // Inter-module signals
+ .tl_i(uart2_tl_req),
+ .tl_o(uart2_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ uart #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3])
+ ) u_uart3 (
+
+ // Input
+ .cio_rx_i (cio_uart3_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart3_tx_d2p),
+ .cio_tx_en_o (cio_uart3_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart3_tx_watermark),
+ .intr_rx_watermark_o (intr_uart3_rx_watermark),
+ .intr_tx_empty_o (intr_uart3_tx_empty),
+ .intr_rx_overflow_o (intr_uart3_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart3_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart3_rx_break_err),
+ .intr_rx_timeout_o (intr_uart3_rx_timeout),
+ .intr_rx_parity_err_o (intr_uart3_rx_parity_err),
+ // [3]: fatal_fault
+ .alert_tx_o ( alert_tx[3:3] ),
+ .alert_rx_i ( alert_rx[3:3] ),
+
+ // Inter-module signals
+ .tl_i(uart3_tl_req),
+ .tl_o(uart3_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ gpio #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4]),
+ .GpioAsyncOn(GpioGpioAsyncOn)
+ ) u_gpio (
+
+ // Input
+ .cio_gpio_i (cio_gpio_gpio_p2d),
+
+ // Output
+ .cio_gpio_o (cio_gpio_gpio_d2p),
+ .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
+
+ // Interrupt
+ .intr_gpio_o (intr_gpio_gpio),
+ // [4]: fatal_fault
+ .alert_tx_o ( alert_tx[4:4] ),
+ .alert_rx_i ( alert_rx[4:4] ),
+
+ // Inter-module signals
+ .tl_i(gpio_tl_req),
+ .tl_o(gpio_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ spi_device #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:5])
+ ) u_spi_device (
+
+ // Input
+ .cio_sck_i (cio_spi_device_sck_p2d),
+ .cio_csb_i (cio_spi_device_csb_p2d),
+ .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d),
+ .cio_sd_i (cio_spi_device_sd_p2d),
+
+ // Output
+ .cio_sd_o (cio_spi_device_sd_d2p),
+ .cio_sd_en_o (cio_spi_device_sd_en_d2p),
+
+ // Interrupt
+ .intr_generic_rx_full_o (intr_spi_device_generic_rx_full),
+ .intr_generic_rx_watermark_o (intr_spi_device_generic_rx_watermark),
+ .intr_generic_tx_watermark_o (intr_spi_device_generic_tx_watermark),
+ .intr_generic_rx_error_o (intr_spi_device_generic_rx_error),
+ .intr_generic_rx_overflow_o (intr_spi_device_generic_rx_overflow),
+ .intr_generic_tx_underflow_o (intr_spi_device_generic_tx_underflow),
+ .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty),
+ .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty),
+ .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow),
+ .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark),
+ .intr_readbuf_flip_o (intr_spi_device_readbuf_flip),
+ .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty),
+ // [5]: fatal_fault
+ .alert_tx_o ( alert_tx[5:5] ),
+ .alert_rx_i ( alert_rx[5:5] ),
+
+ // Inter-module signals
+ .ram_cfg_i(ast_ram_2p_cfg),
+ .passthrough_o(spi_device_passthrough_req),
+ .passthrough_i(spi_device_passthrough_rsp),
+ .mbist_en_i('0),
+ .sck_monitor_o(sck_monitor_o),
+ .tl_i(spi_device_tl_req),
+ .tl_o(spi_device_tl_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
+ );
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6])
+ ) u_i2c0 (
+
+ // Input
+ .cio_sda_i (cio_i2c0_sda_p2d),
+ .cio_scl_i (cio_i2c0_scl_p2d),
+
+ // Output
+ .cio_sda_o (cio_i2c0_sda_d2p),
+ .cio_sda_en_o (cio_i2c0_sda_en_d2p),
+ .cio_scl_o (cio_i2c0_scl_d2p),
+ .cio_scl_en_o (cio_i2c0_scl_en_d2p),
+
+ // Interrupt
+ .intr_fmt_threshold_o (intr_i2c0_fmt_threshold),
+ .intr_rx_threshold_o (intr_i2c0_rx_threshold),
+ .intr_fmt_overflow_o (intr_i2c0_fmt_overflow),
+ .intr_rx_overflow_o (intr_i2c0_rx_overflow),
+ .intr_nak_o (intr_i2c0_nak),
+ .intr_scl_interference_o (intr_i2c0_scl_interference),
+ .intr_sda_interference_o (intr_i2c0_sda_interference),
+ .intr_stretch_timeout_o (intr_i2c0_stretch_timeout),
+ .intr_sda_unstable_o (intr_i2c0_sda_unstable),
+ .intr_cmd_complete_o (intr_i2c0_cmd_complete),
+ .intr_tx_stretch_o (intr_i2c0_tx_stretch),
+ .intr_tx_overflow_o (intr_i2c0_tx_overflow),
+ .intr_acq_full_o (intr_i2c0_acq_full),
+ .intr_unexp_stop_o (intr_i2c0_unexp_stop),
+ .intr_host_timeout_o (intr_i2c0_host_timeout),
+ // [6]: fatal_fault
+ .alert_tx_o ( alert_tx[6:6] ),
+ .alert_rx_i ( alert_rx[6:6] ),
+
+ // Inter-module signals
+ .tl_i(i2c0_tl_req),
+ .tl_o(i2c0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
+ );
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7])
+ ) u_i2c1 (
+
+ // Input
+ .cio_sda_i (cio_i2c1_sda_p2d),
+ .cio_scl_i (cio_i2c1_scl_p2d),
+
+ // Output
+ .cio_sda_o (cio_i2c1_sda_d2p),
+ .cio_sda_en_o (cio_i2c1_sda_en_d2p),
+ .cio_scl_o (cio_i2c1_scl_d2p),
+ .cio_scl_en_o (cio_i2c1_scl_en_d2p),
+
+ // Interrupt
+ .intr_fmt_threshold_o (intr_i2c1_fmt_threshold),
+ .intr_rx_threshold_o (intr_i2c1_rx_threshold),
+ .intr_fmt_overflow_o (intr_i2c1_fmt_overflow),
+ .intr_rx_overflow_o (intr_i2c1_rx_overflow),
+ .intr_nak_o (intr_i2c1_nak),
+ .intr_scl_interference_o (intr_i2c1_scl_interference),
+ .intr_sda_interference_o (intr_i2c1_sda_interference),
+ .intr_stretch_timeout_o (intr_i2c1_stretch_timeout),
+ .intr_sda_unstable_o (intr_i2c1_sda_unstable),
+ .intr_cmd_complete_o (intr_i2c1_cmd_complete),
+ .intr_tx_stretch_o (intr_i2c1_tx_stretch),
+ .intr_tx_overflow_o (intr_i2c1_tx_overflow),
+ .intr_acq_full_o (intr_i2c1_acq_full),
+ .intr_unexp_stop_o (intr_i2c1_unexp_stop),
+ .intr_host_timeout_o (intr_i2c1_host_timeout),
+ // [7]: fatal_fault
+ .alert_tx_o ( alert_tx[7:7] ),
+ .alert_rx_i ( alert_rx[7:7] ),
+
+ // Inter-module signals
+ .tl_i(i2c1_tl_req),
+ .tl_o(i2c1_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
+ );
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
+ ) u_i2c2 (
+
+ // Input
+ .cio_sda_i (cio_i2c2_sda_p2d),
+ .cio_scl_i (cio_i2c2_scl_p2d),
+
+ // Output
+ .cio_sda_o (cio_i2c2_sda_d2p),
+ .cio_sda_en_o (cio_i2c2_sda_en_d2p),
+ .cio_scl_o (cio_i2c2_scl_d2p),
+ .cio_scl_en_o (cio_i2c2_scl_en_d2p),
+
+ // Interrupt
+ .intr_fmt_threshold_o (intr_i2c2_fmt_threshold),
+ .intr_rx_threshold_o (intr_i2c2_rx_threshold),
+ .intr_fmt_overflow_o (intr_i2c2_fmt_overflow),
+ .intr_rx_overflow_o (intr_i2c2_rx_overflow),
+ .intr_nak_o (intr_i2c2_nak),
+ .intr_scl_interference_o (intr_i2c2_scl_interference),
+ .intr_sda_interference_o (intr_i2c2_sda_interference),
+ .intr_stretch_timeout_o (intr_i2c2_stretch_timeout),
+ .intr_sda_unstable_o (intr_i2c2_sda_unstable),
+ .intr_cmd_complete_o (intr_i2c2_cmd_complete),
+ .intr_tx_stretch_o (intr_i2c2_tx_stretch),
+ .intr_tx_overflow_o (intr_i2c2_tx_overflow),
+ .intr_acq_full_o (intr_i2c2_acq_full),
+ .intr_unexp_stop_o (intr_i2c2_unexp_stop),
+ .intr_host_timeout_o (intr_i2c2_host_timeout),
+ // [8]: fatal_fault
+ .alert_tx_o ( alert_tx[8:8] ),
+ .alert_rx_i ( alert_rx[8:8] ),
+
+ // Inter-module signals
+ .tl_i(i2c2_tl_req),
+ .tl_o(i2c2_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
+ );
+ pattgen #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
+ ) u_pattgen (
+
+ // Output
+ .cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p),
+ .cio_pda0_tx_en_o (cio_pattgen_pda0_tx_en_d2p),
+ .cio_pcl0_tx_o (cio_pattgen_pcl0_tx_d2p),
+ .cio_pcl0_tx_en_o (cio_pattgen_pcl0_tx_en_d2p),
+ .cio_pda1_tx_o (cio_pattgen_pda1_tx_d2p),
+ .cio_pda1_tx_en_o (cio_pattgen_pda1_tx_en_d2p),
+ .cio_pcl1_tx_o (cio_pattgen_pcl1_tx_d2p),
+ .cio_pcl1_tx_en_o (cio_pattgen_pcl1_tx_en_d2p),
+
+ // Interrupt
+ .intr_done_ch0_o (intr_pattgen_done_ch0),
+ .intr_done_ch1_o (intr_pattgen_done_ch1),
+ // [9]: fatal_fault
+ .alert_tx_o ( alert_tx[9:9] ),
+ .alert_rx_i ( alert_rx[9:9] ),
+
+ // Inter-module signals
+ .tl_i(pattgen_tl_req),
+ .tl_o(pattgen_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_timer #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
+ ) u_rv_timer (
+
+ // Interrupt
+ .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0),
+ // [10]: fatal_fault
+ .alert_tx_o ( alert_tx[10:10] ),
+ .alert_rx_i ( alert_rx[10:10] ),
+
+ // Inter-module signals
+ .tl_i(rv_timer_tl_req),
+ .tl_o(rv_timer_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ otp_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:11]),
+ .MemInitFile(OtpCtrlMemInitFile),
+ .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm),
+ .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit)
+ ) u_otp_ctrl (
+
+ // Output
+ .cio_test_o (cio_otp_ctrl_test_d2p),
+ .cio_test_en_o (cio_otp_ctrl_test_en_d2p),
+
+ // Interrupt
+ .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
+ .intr_otp_error_o (intr_otp_ctrl_otp_error),
+ // [11]: fatal_macro_error
+ // [12]: fatal_check_error
+ // [13]: fatal_bus_integ_error
+ // [14]: fatal_prim_otp_alert
+ // [15]: recov_prim_otp_alert
+ .alert_tx_o ( alert_tx[15:11] ),
+ .alert_rx_i ( alert_rx[15:11] ),
+
+ // Inter-module signals
+ .otp_ext_voltage_h_io(otp_ext_voltage_h_io),
+ .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
+ .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
+ .edn_o(edn0_edn_req[1]),
+ .edn_i(edn0_edn_rsp[1]),
+ .pwr_otp_i(pwrmgr_aon_pwr_otp_req),
+ .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp),
+ .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_req),
+ .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_rsp),
+ .lc_otp_program_i(lc_ctrl_lc_otp_program_req),
+ .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp),
+ .otp_lc_data_o(otp_ctrl_otp_lc_data),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
+ .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
+ .lc_dft_en_i(lc_ctrl_lc_dft_en),
+ .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
+ .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key),
+ .flash_otp_key_i(flash_ctrl_otp_req),
+ .flash_otp_key_o(flash_ctrl_otp_rsp),
+ .sram_otp_key_i(otp_ctrl_sram_otp_key_req),
+ .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp),
+ .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req),
+ .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp),
+ .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg),
+ .obs_ctrl_i(ast_obs_ctrl),
+ .otp_obs_o(otp_obs_o),
+ .core_tl_i(otp_ctrl_core_tl_req),
+ .core_tl_o(otp_ctrl_core_tl_rsp),
+ .prim_tl_i(otp_ctrl_prim_tl_req),
+ .prim_tl_o(otp_ctrl_prim_tl_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+ .scan_en_i,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ lc_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]),
+ .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
+ .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
+ .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction),
+ .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens),
+ .ChipGen(LcCtrlChipGen),
+ .ChipRev(LcCtrlChipRev),
+ .IdcodeValue(LcCtrlIdcodeValue)
+ ) u_lc_ctrl (
+ // [16]: fatal_prog_error
+ // [17]: fatal_state_error
+ // [18]: fatal_bus_integ_error
+ .alert_tx_o ( alert_tx[18:16] ),
+ .alert_rx_i ( alert_rx[18:16] ),
+
+ // Inter-module signals
+ .jtag_i(pinmux_aon_lc_jtag_req),
+ .jtag_o(pinmux_aon_lc_jtag_rsp),
+ .esc_scrap_state0_tx_i(alert_handler_esc_tx[1]),
+ .esc_scrap_state0_rx_o(alert_handler_esc_rx[1]),
+ .esc_scrap_state1_tx_i(alert_handler_esc_tx[2]),
+ .esc_scrap_state1_rx_o(alert_handler_esc_rx[2]),
+ .pwr_lc_i(pwrmgr_aon_pwr_lc_req),
+ .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp),
+ .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req),
+ .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp),
+ .otp_lc_data_i(otp_ctrl_otp_lc_data),
+ .lc_otp_program_o(lc_ctrl_lc_otp_program_req),
+ .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp),
+ .kmac_data_o(kmac_app_req[1]),
+ .kmac_data_i(kmac_app_rsp[1]),
+ .lc_dft_en_o(lc_ctrl_lc_dft_en),
+ .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en),
+ .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en),
+ .lc_cpu_en_o(lc_ctrl_lc_cpu_en),
+ .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en),
+ .lc_escalate_en_o(lc_ctrl_lc_escalate_en),
+ .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
+ .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
+ .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req),
+ .lc_flash_rma_seed_o(flash_ctrl_rma_seed),
+ .lc_flash_rma_ack_i(otbn_lc_rma_ack),
+ .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en),
+ .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en),
+ .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en),
+ .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en),
+ .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en),
+ .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en),
+ .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div),
+ .otp_device_id_i(lc_ctrl_otp_device_id),
+ .otp_manuf_state_i(lc_ctrl_otp_manuf_state),
+ .hw_rev_o(),
+ .tl_i(lc_ctrl_tl_req),
+ .tl_o(lc_ctrl_tl_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ alert_handler #(
+ .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
+ ) u_alert_handler (
+
+ // Interrupt
+ .intr_classa_o (intr_alert_handler_classa),
+ .intr_classb_o (intr_alert_handler_classb),
+ .intr_classc_o (intr_alert_handler_classc),
+ .intr_classd_o (intr_alert_handler_classd),
+
+ // Inter-module signals
+ .crashdump_o(alert_handler_crashdump),
+ .edn_o(edn0_edn_req[4]),
+ .edn_i(edn0_edn_rsp[4]),
+ .esc_rx_i(alert_handler_esc_rx),
+ .esc_tx_o(alert_handler_esc_tx),
+ .tl_i(alert_handler_tl_req),
+ .tl_o(alert_handler_tl_rsp),
+ // alert signals
+ .alert_rx_o ( alert_rx ),
+ .alert_tx_i ( alert_tx ),
+ // synchronized clock gated / reset asserted
+ // indications for each alert
+ .lpg_cg_en_i ( lpg_cg_en ),
+ .lpg_rst_en_i ( lpg_rst_en ),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ spi_host #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19])
+ ) u_spi_host0 (
+
+ // Input
+ .cio_sd_i (cio_spi_host0_sd_p2d),
+
+ // Output
+ .cio_sck_o (cio_spi_host0_sck_d2p),
+ .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
+ .cio_csb_o (cio_spi_host0_csb_d2p),
+ .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
+ .cio_sd_o (cio_spi_host0_sd_d2p),
+ .cio_sd_en_o (cio_spi_host0_sd_en_d2p),
+
+ // Interrupt
+ .intr_error_o (intr_spi_host0_error),
+ .intr_spi_event_o (intr_spi_host0_spi_event),
+ // [19]: fatal_fault
+ .alert_tx_o ( alert_tx[19:19] ),
+ .alert_rx_i ( alert_rx[19:19] ),
+
+ // Inter-module signals
+ .passthrough_i(spi_device_passthrough_req),
+ .passthrough_o(spi_device_passthrough_rsp),
+ .tl_i(spi_host0_tl_req),
+ .tl_o(spi_host0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
+ );
+ spi_host #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20])
+ ) u_spi_host1 (
+
+ // Input
+ .cio_sd_i (cio_spi_host1_sd_p2d),
+
+ // Output
+ .cio_sck_o (cio_spi_host1_sck_d2p),
+ .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
+ .cio_csb_o (cio_spi_host1_csb_d2p),
+ .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
+ .cio_sd_o (cio_spi_host1_sd_d2p),
+ .cio_sd_en_o (cio_spi_host1_sd_en_d2p),
+
+ // Interrupt
+ .intr_error_o (intr_spi_host1_error),
+ .intr_spi_event_o (intr_spi_host1_spi_event),
+ // [20]: fatal_fault
+ .alert_tx_o ( alert_tx[20:20] ),
+ .alert_rx_i ( alert_rx[20:20] ),
+
+ // Inter-module signals
+ .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+ .passthrough_o(),
+ .tl_i(spi_host1_tl_req),
+ .tl_o(spi_host1_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
+ );
+ usbdev #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]),
+ .Stub(UsbdevStub),
+ .RcvrWakeTimeUs(UsbdevRcvrWakeTimeUs)
+ ) u_usbdev (
+
+ // Input
+ .cio_sense_i (cio_usbdev_sense_p2d),
+ .cio_usb_dp_i (cio_usbdev_usb_dp_p2d),
+ .cio_usb_dn_i (cio_usbdev_usb_dn_p2d),
+
+ // Output
+ .cio_usb_dp_o (cio_usbdev_usb_dp_d2p),
+ .cio_usb_dp_en_o (cio_usbdev_usb_dp_en_d2p),
+ .cio_usb_dn_o (cio_usbdev_usb_dn_d2p),
+ .cio_usb_dn_en_o (cio_usbdev_usb_dn_en_d2p),
+
+ // Interrupt
+ .intr_pkt_received_o (intr_usbdev_pkt_received),
+ .intr_pkt_sent_o (intr_usbdev_pkt_sent),
+ .intr_disconnected_o (intr_usbdev_disconnected),
+ .intr_host_lost_o (intr_usbdev_host_lost),
+ .intr_link_reset_o (intr_usbdev_link_reset),
+ .intr_link_suspend_o (intr_usbdev_link_suspend),
+ .intr_link_resume_o (intr_usbdev_link_resume),
+ .intr_av_empty_o (intr_usbdev_av_empty),
+ .intr_rx_full_o (intr_usbdev_rx_full),
+ .intr_av_overflow_o (intr_usbdev_av_overflow),
+ .intr_link_in_err_o (intr_usbdev_link_in_err),
+ .intr_rx_crc_err_o (intr_usbdev_rx_crc_err),
+ .intr_rx_pid_err_o (intr_usbdev_rx_pid_err),
+ .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err),
+ .intr_frame_o (intr_usbdev_frame),
+ .intr_powered_o (intr_usbdev_powered),
+ .intr_link_out_err_o (intr_usbdev_link_out_err),
+ // [21]: fatal_fault
+ .alert_tx_o ( alert_tx[21:21] ),
+ .alert_rx_i ( alert_rx[21:21] ),
+
+ // Inter-module signals
+ .usb_rx_d_i(usbdev_usb_rx_d_i),
+ .usb_tx_d_o(usbdev_usb_tx_d_o),
+ .usb_tx_se0_o(usbdev_usb_tx_se0_o),
+ .usb_tx_use_d_se0_o(usbdev_usb_tx_use_d_se0_o),
+ .usb_dp_pullup_o(usbdev_usb_dp_pullup),
+ .usb_dn_pullup_o(usbdev_usb_dn_pullup),
+ .usb_rx_enable_o(usbdev_usb_rx_enable_o),
+ .usb_ref_val_o(usbdev_usb_ref_val_o),
+ .usb_ref_pulse_o(usbdev_usb_ref_pulse_o),
+ .usb_aon_suspend_req_o(usbdev_usb_aon_suspend_req),
+ .usb_aon_wake_ack_o(usbdev_usb_aon_wake_ack),
+ .usb_aon_bus_reset_i(usbdev_usb_aon_bus_reset),
+ .usb_aon_sense_lost_i(usbdev_usb_aon_sense_lost),
+ .usb_aon_wake_detect_active_i(pinmux_aon_usbdev_wake_detect_active),
+ .ram_cfg_i(ast_ram_2p_cfg),
+ .tl_i(usbdev_tl_req),
+ .tl_o(usbdev_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_usb_peri),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
+ .rst_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel])
+ );
+ pwrmgr #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22])
+ ) u_pwrmgr_aon (
+
+ // Interrupt
+ .intr_wakeup_o (intr_pwrmgr_aon_wakeup),
+ // [22]: fatal_fault
+ .alert_tx_o ( alert_tx[22:22] ),
+ .alert_rx_i ( alert_rx[22:22] ),
+
+ // Inter-module signals
+ .pwr_ast_o(pwrmgr_ast_req_o),
+ .pwr_ast_i(pwrmgr_ast_rsp_i),
+ .pwr_rst_o(pwrmgr_aon_pwr_rst_req),
+ .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp),
+ .pwr_clk_o(pwrmgr_aon_pwr_clk_req),
+ .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp),
+ .pwr_otp_o(pwrmgr_aon_pwr_otp_req),
+ .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp),
+ .pwr_lc_o(pwrmgr_aon_pwr_lc_req),
+ .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp),
+ .pwr_flash_i(pwrmgr_aon_pwr_flash),
+ .esc_rst_tx_i(alert_handler_esc_tx[3]),
+ .esc_rst_rx_o(alert_handler_esc_rx[3]),
+ .pwr_cpu_i(rv_core_ibex_sec_pwrmgr),
+ .wakeups_i(pwrmgr_aon_wakeups),
+ .rstreqs_i(pwrmgr_aon_rstreqs),
+ .ndmreset_req_i(rv_dm_ndmreset_req),
+ .strap_o(pwrmgr_aon_strap),
+ .low_power_o(pwrmgr_aon_low_power),
+ .rom_ctrl_i(rom_ctrl_pwrmgr_data),
+ .fetch_en_o(pwrmgr_aon_fetch_en),
+ .lc_dft_en_i(lc_ctrl_lc_dft_en),
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .sw_rst_req_i(rstmgr_aon_sw_rst_req),
+ .tl_i(pwrmgr_aon_tl_req),
+ .tl_o(pwrmgr_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup),
+ .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]),
+ .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ rstmgr #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]),
+ .SecCheck(SecRstmgrAonCheck),
+ .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay)
+ ) u_rstmgr_aon (
+ // [23]: fatal_fault
+ // [24]: fatal_cnsty_fault
+ .alert_tx_o ( alert_tx[24:23] ),
+ .alert_rx_i ( alert_rx[24:23] ),
+
+ // Inter-module signals
+ .por_n_i(por_n_i),
+ .pwr_i(pwrmgr_aon_pwr_rst_req),
+ .pwr_o(pwrmgr_aon_pwr_rst_rsp),
+ .resets_o(rstmgr_aon_resets),
+ .rst_en_o(rstmgr_aon_rst_en),
+ .alert_dump_i(alert_handler_crashdump),
+ .cpu_dump_i(rv_core_ibex_sec_crash_dump),
+ .sw_rst_req_o(rstmgr_aon_sw_rst_req),
+ .tl_i(rstmgr_aon_tl_req),
+ .tl_o(rstmgr_aon_tl_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
+ .clk_main_i (clkmgr_aon_clocks.clk_main_powerup),
+ .clk_io_i (clkmgr_aon_clocks.clk_io_powerup),
+ .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup),
+ .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup),
+ .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_smc_i (clkmgr_aon_clocks.clk_smc_powerup),
+ .clk_ml_i (clkmgr_aon_clocks.clk_ml_powerup),
+ .clk_video_i (clkmgr_aon_clocks.clk_video_powerup),
+ .clk_audio_i (clkmgr_aon_clocks.clk_audio_powerup),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
+ );
+ clkmgr #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25])
+ ) u_clkmgr_aon (
+ // [25]: recov_fault
+ // [26]: fatal_fault
+ .alert_tx_o ( alert_tx[26:25] ),
+ .alert_rx_i ( alert_rx[26:25] ),
+
+ // Inter-module signals
+ .clocks_o(clkmgr_aon_clocks),
+ .cg_en_o(clkmgr_aon_cg_en),
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .io_clk_byp_req_o(io_clk_byp_req_o),
+ .io_clk_byp_ack_i(io_clk_byp_ack_i),
+ .all_clk_byp_req_o(all_clk_byp_req_o),
+ .all_clk_byp_ack_i(all_clk_byp_ack_i),
+ .hi_speed_sel_o(hi_speed_sel_o),
+ .div_step_down_req_i(div_step_down_req_i),
+ .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req),
+ .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack),
+ .jitter_en_o(clk_main_jitter_en_o),
+ .pwr_i(pwrmgr_aon_pwr_clk_req),
+ .pwr_o(pwrmgr_aon_pwr_clk_rsp),
+ .idle_i(clkmgr_aon_idle),
+ .calib_rdy_i(calib_rdy_i),
+ .tl_i(clkmgr_aon_tl_req),
+ .tl_o(clkmgr_aon_tl_rsp),
+ .scanmode_i,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_main_i (clk_main_i),
+ .clk_io_i (clk_io_i),
+ .clk_usb_i (clk_usb_i),
+ .clk_aon_i (clk_aon_i),
+ .clk_ml_i (clk_ml_i),
+ .clk_smc_i (clk_smc_i),
+ .clk_video_i (clk_video_i),
+ .clk_audio_i (clk_audio_i),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]),
+ .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::DomainAonSel]),
+ .rst_smc_ni (rstmgr_aon_resets.rst_lc_smc_n[rstmgr_pkg::DomainAonSel]),
+ .rst_ml_ni (rstmgr_aon_resets.rst_lc_ml_n[rstmgr_pkg::DomainAonSel]),
+ .rst_video_ni (rstmgr_aon_resets.rst_lc_video_n[rstmgr_pkg::DomainAonSel]),
+ .rst_audio_ni (rstmgr_aon_resets.rst_lc_audio_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_smc_ni (rstmgr_aon_resets.rst_por_smc_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_ml_ni (rstmgr_aon_resets.rst_por_ml_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_video_ni (rstmgr_aon_resets.rst_por_video_n[rstmgr_pkg::DomainAonSel]),
+ .rst_root_audio_ni (rstmgr_aon_resets.rst_por_audio_n[rstmgr_pkg::DomainAonSel])
+ );
+ sysrst_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27])
+ ) u_sysrst_ctrl_aon (
+
+ // Input
+ .cio_ac_present_i (cio_sysrst_ctrl_aon_ac_present_p2d),
+ .cio_key0_in_i (cio_sysrst_ctrl_aon_key0_in_p2d),
+ .cio_key1_in_i (cio_sysrst_ctrl_aon_key1_in_p2d),
+ .cio_key2_in_i (cio_sysrst_ctrl_aon_key2_in_p2d),
+ .cio_pwrb_in_i (cio_sysrst_ctrl_aon_pwrb_in_p2d),
+ .cio_lid_open_i (cio_sysrst_ctrl_aon_lid_open_p2d),
+ .cio_ec_rst_l_i (cio_sysrst_ctrl_aon_ec_rst_l_p2d),
+ .cio_flash_wp_l_i (cio_sysrst_ctrl_aon_flash_wp_l_p2d),
+
+ // Output
+ .cio_bat_disable_o (cio_sysrst_ctrl_aon_bat_disable_d2p),
+ .cio_bat_disable_en_o (cio_sysrst_ctrl_aon_bat_disable_en_d2p),
+ .cio_key0_out_o (cio_sysrst_ctrl_aon_key0_out_d2p),
+ .cio_key0_out_en_o (cio_sysrst_ctrl_aon_key0_out_en_d2p),
+ .cio_key1_out_o (cio_sysrst_ctrl_aon_key1_out_d2p),
+ .cio_key1_out_en_o (cio_sysrst_ctrl_aon_key1_out_en_d2p),
+ .cio_key2_out_o (cio_sysrst_ctrl_aon_key2_out_d2p),
+ .cio_key2_out_en_o (cio_sysrst_ctrl_aon_key2_out_en_d2p),
+ .cio_pwrb_out_o (cio_sysrst_ctrl_aon_pwrb_out_d2p),
+ .cio_pwrb_out_en_o (cio_sysrst_ctrl_aon_pwrb_out_en_d2p),
+ .cio_z3_wakeup_o (cio_sysrst_ctrl_aon_z3_wakeup_d2p),
+ .cio_z3_wakeup_en_o (cio_sysrst_ctrl_aon_z3_wakeup_en_d2p),
+ .cio_ec_rst_l_o (cio_sysrst_ctrl_aon_ec_rst_l_d2p),
+ .cio_ec_rst_l_en_o (cio_sysrst_ctrl_aon_ec_rst_l_en_d2p),
+ .cio_flash_wp_l_o (cio_sysrst_ctrl_aon_flash_wp_l_d2p),
+ .cio_flash_wp_l_en_o (cio_sysrst_ctrl_aon_flash_wp_l_en_d2p),
+
+ // Interrupt
+ .intr_event_detected_o (intr_sysrst_ctrl_aon_event_detected),
+ // [27]: fatal_fault
+ .alert_tx_o ( alert_tx[27:27] ),
+ .alert_rx_i ( alert_rx[27:27] ),
+
+ // Inter-module signals
+ .wkup_req_o(pwrmgr_aon_wakeups[0]),
+ .rst_req_o(pwrmgr_aon_rstreqs[0]),
+ .tl_i(sysrst_ctrl_aon_tl_req),
+ .tl_o(sysrst_ctrl_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ adc_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28])
+ ) u_adc_ctrl_aon (
+
+ // Interrupt
+ .intr_match_done_o (intr_adc_ctrl_aon_match_done),
+ // [28]: fatal_fault
+ .alert_tx_o ( alert_tx[28:28] ),
+ .alert_rx_i ( alert_rx[28:28] ),
+
+ // Inter-module signals
+ .adc_o(adc_req_o),
+ .adc_i(adc_rsp_i),
+ .wkup_req_o(pwrmgr_aon_wakeups[1]),
+ .tl_i(adc_ctrl_aon_tl_req),
+ .tl_o(adc_ctrl_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ pwm #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29])
+ ) u_pwm_aon (
+
+ // Output
+ .cio_pwm_o (cio_pwm_aon_pwm_d2p),
+ .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p),
+ // [29]: fatal_fault
+ .alert_tx_o ( alert_tx[29:29] ),
+ .alert_rx_i ( alert_rx[29:29] ),
+
+ // Inter-module signals
+ .tl_i(pwm_aon_tl_req),
+ .tl_o(pwm_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .clk_core_i (clkmgr_aon_clocks.clk_aon_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_core_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ pinmux #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
+ .TargetCfg(PinmuxAonTargetCfg)
+ ) u_pinmux_aon (
+ // [30]: fatal_fault
+ .alert_tx_o ( alert_tx[30:30] ),
+ .alert_rx_i ( alert_rx[30:30] ),
+
+ // Inter-module signals
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .lc_dft_en_i(lc_ctrl_lc_dft_en),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
+ .pinmux_hw_debug_en_o(pinmux_aon_pinmux_hw_debug_en),
+ .lc_jtag_o(pinmux_aon_lc_jtag_req),
+ .lc_jtag_i(pinmux_aon_lc_jtag_rsp),
+ .rv_jtag_o(pinmux_aon_rv_jtag_req),
+ .rv_jtag_i(pinmux_aon_rv_jtag_rsp),
+ .dft_jtag_o(pinmux_aon_dft_jtag_req),
+ .dft_jtag_i(pinmux_aon_dft_jtag_rsp),
+ .dft_strap_test_o(dft_strap_test_o),
+ .dft_hold_tap_sel_i(dft_hold_tap_sel_i),
+ .sleep_en_i(pwrmgr_aon_low_power),
+ .strap_en_i(pwrmgr_aon_strap),
+ .pin_wkup_req_o(pwrmgr_aon_wakeups[2]),
+ .usbdev_dppullup_en_i(usbdev_usb_dp_pullup),
+ .usbdev_dnpullup_en_i(usbdev_usb_dn_pullup),
+ .usb_dppullup_en_o(usb_dp_pullup_en_o),
+ .usb_dnpullup_en_o(usb_dn_pullup_en_o),
+ .usb_wkup_req_o(pwrmgr_aon_wakeups[3]),
+ .usbdev_suspend_req_i(usbdev_usb_aon_suspend_req),
+ .usbdev_wake_ack_i(usbdev_usb_aon_wake_ack),
+ .usbdev_bus_reset_o(usbdev_usb_aon_bus_reset),
+ .usbdev_sense_lost_o(usbdev_usb_aon_sense_lost),
+ .usbdev_wake_detect_active_o(pinmux_aon_usbdev_wake_detect_active),
+ .tl_i(pinmux_aon_tl_req),
+ .tl_o(pinmux_aon_tl_rsp),
+
+ .periph_to_mio_i (mio_d2p ),
+ .periph_to_mio_oe_i (mio_en_d2p ),
+ .mio_to_periph_o (mio_p2d ),
+
+ .mio_attr_o,
+ .mio_out_o,
+ .mio_oe_o,
+ .mio_in_i,
+
+ .periph_to_dio_i (dio_d2p ),
+ .periph_to_dio_oe_i (dio_en_d2p ),
+ .dio_to_periph_o (dio_p2d ),
+
+ .dio_attr_o,
+ .dio_out_o,
+ .dio_oe_o,
+ .dio_in_i,
+
+ .scanmode_i,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
+ .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
+ );
+ aon_timer #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31])
+ ) u_aon_timer_aon (
+
+ // Interrupt
+ .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired),
+ .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark),
+ // [31]: fatal_fault
+ .alert_tx_o ( alert_tx[31:31] ),
+ .alert_rx_i ( alert_rx[31:31] ),
+
+ // Inter-module signals
+ .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark),
+ .wkup_req_o(pwrmgr_aon_wakeups[4]),
+ .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[1]),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .sleep_mode_i(pwrmgr_aon_low_power),
+ .tl_i(aon_timer_aon_tl_req),
+ .tl_o(aon_timer_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ sensor_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32])
+ ) u_sensor_ctrl (
+
+ // Output
+ .cio_ast_debug_out_o (cio_sensor_ctrl_ast_debug_out_d2p),
+ .cio_ast_debug_out_en_o (cio_sensor_ctrl_ast_debug_out_en_d2p),
+
+ // Interrupt
+ .intr_io_status_change_o (intr_sensor_ctrl_io_status_change),
+ .intr_init_status_change_o (intr_sensor_ctrl_init_status_change),
+ // [32]: recov_alert
+ // [33]: fatal_alert
+ .alert_tx_o ( alert_tx[33:32] ),
+ .alert_rx_i ( alert_rx[33:32] ),
+
+ // Inter-module signals
+ .ast_alert_i(sensor_ctrl_ast_alert_req_i),
+ .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
+ .ast_status_i(sensor_ctrl_ast_status_i),
+ .ast_init_done_i(ast_init_done_i),
+ .ast2pinmux_i(ast2pinmux_i),
+ .wkup_req_o(pwrmgr_aon_wakeups[5]),
+ .tl_i(sensor_ctrl_tl_req),
+ .tl_o(sensor_ctrl_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+ sram_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
+ .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
+ .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
+ .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm),
+ .MemSizeRam(4096),
+ .InstrExec(SramCtrlRetAonInstrExec)
+ ) u_sram_ctrl_ret_aon (
+ // [34]: fatal_error
+ .alert_tx_o ( alert_tx[34:34] ),
+ .alert_rx_i ( alert_rx[34:34] ),
+
+ // Inter-module signals
+ .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
+ .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]),
+ .cfg_i(ast_ram_1p_cfg),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_hw_debug_en_i(lc_ctrl_pkg::Off),
+ .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False),
+ .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req),
+ .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp),
+ .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req),
+ .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
+ );
+ flash_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]),
+ .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
+ .RndCnstDataKey(RndCnstFlashCtrlDataKey),
+ .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds),
+ .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm),
+ .SecScrambleEn(SecFlashCtrlScrambleEn),
+ .ProgFifoDepth(FlashCtrlProgFifoDepth),
+ .RdFifoDepth(FlashCtrlRdFifoDepth)
+ ) u_flash_ctrl (
+
+ // Input
+ .cio_tck_i (cio_flash_ctrl_tck_p2d),
+ .cio_tms_i (cio_flash_ctrl_tms_p2d),
+ .cio_tdi_i (cio_flash_ctrl_tdi_p2d),
+
+ // Output
+ .cio_tdo_o (cio_flash_ctrl_tdo_d2p),
+ .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p),
+
+ // Interrupt
+ .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
+ .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
+ .intr_rd_full_o (intr_flash_ctrl_rd_full),
+ .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
+ .intr_op_done_o (intr_flash_ctrl_op_done),
+ .intr_corr_err_o (intr_flash_ctrl_corr_err),
+ // [35]: recov_err
+ // [36]: fatal_std_err
+ // [37]: fatal_err
+ // [38]: fatal_prim_flash_alert
+ // [39]: recov_prim_flash_alert
+ .alert_tx_o ( alert_tx[39:35] ),
+ .alert_rx_i ( alert_rx[39:35] ),
+
+ // Inter-module signals
+ .otp_o(flash_ctrl_otp_req),
+ .otp_i(flash_ctrl_otp_rsp),
+ .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en),
+ .flash_bist_enable_i(flash_bist_enable_i),
+ .flash_power_down_h_i(flash_power_down_h_i),
+ .flash_power_ready_h_i(flash_power_ready_h_i),
+ .flash_test_mode_a_io(flash_test_mode_a_io),
+ .flash_test_voltage_h_io(flash_test_voltage_h_io),
+ .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
+ .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en),
+ .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en),
+ .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en),
+ .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .rma_req_i(lc_ctrl_lc_flash_rma_req),
+ .rma_ack_o(flash_ctrl_rma_ack),
+ .rma_seed_i(flash_ctrl_rma_seed),
+ .pwrmgr_o(pwrmgr_aon_pwr_flash),
+ .keymgr_o(flash_ctrl_keymgr),
+ .obs_ctrl_i(ast_obs_ctrl),
+ .fla_obs_o(flash_obs_o),
+ .core_tl_i(flash_ctrl_core_tl_req),
+ .core_tl_o(flash_ctrl_core_tl_rsp),
+ .prim_tl_i(flash_ctrl_prim_tl_req),
+ .prim_tl_o(flash_ctrl_prim_tl_rsp),
+ .mem_tl_i(flash_ctrl_mem_tl_req),
+ .mem_tl_o(flash_ctrl_mem_tl_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+ .scan_en_i,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_dm #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]),
+ .IdcodeValue(RvDmIdcodeValue)
+ ) u_rv_dm (
+ // [40]: fatal_fault
+ .alert_tx_o ( alert_tx[40:40] ),
+ .alert_rx_i ( alert_rx[40:40] ),
+
+ // Inter-module signals
+ .jtag_i(pinmux_aon_rv_jtag_req),
+ .jtag_o(pinmux_aon_rv_jtag_rsp),
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en),
+ .unavailable_i(2'b0),
+ .ndmreset_req_o(rv_dm_ndmreset_req),
+ .dmactive_o(),
+ .debug_req_o(rv_dm_debug_req),
+ .sba_tl_h_o(main_tl_rv_dm__sba_req),
+ .sba_tl_h_i(main_tl_rv_dm__sba_rsp),
+ .regs_tl_d_i(rv_dm_regs_tl_d_req),
+ .regs_tl_d_o(rv_dm_regs_tl_d_rsp),
+ .mem_tl_d_i(rv_dm_mem_tl_d_req),
+ .mem_tl_d_o(rv_dm_mem_tl_d_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_plic #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
+ ) u_rv_plic (
+ // [41]: fatal_fault
+ .alert_tx_o ( alert_tx[41:41] ),
+ .alert_rx_i ( alert_rx[41:41] ),
+
+ // Inter-module signals
+ .irq_o(rv_plic_irq),
+ .irq_id_o(),
+ .msip_o(rv_plic_msip),
+ .tl_i(rv_plic_tl_req),
+ .tl_o(rv_plic_tl_rsp),
+ .intr_src_i (sec_intr_vector),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ aes #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
+ .AES192Enable(1'b1),
+ .SecMasking(SecAesMasking),
+ .SecSBoxImpl(SecAesSBoxImpl),
+ .SecStartTriggerDelay(SecAesStartTriggerDelay),
+ .SecAllowForcingMasks(SecAesAllowForcingMasks),
+ .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding),
+ .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed),
+ .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm),
+ .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm),
+ .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
+ .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm)
+ ) u_aes (
+ // [42]: recov_ctrl_update_err
+ // [43]: fatal_fault
+ .alert_tx_o ( alert_tx[43:42] ),
+ .alert_rx_i ( alert_rx[43:42] ),
+
+ // Inter-module signals
+ .idle_o(clkmgr_aon_idle[0]),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .edn_o(edn0_edn_req[5]),
+ .edn_i(edn0_edn_rsp[5]),
+ .keymgr_key_i(keymgr_aes_key),
+ .tl_i(aes_tl_req),
+ .tl_o(aes_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_aes),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_aes),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ hmac #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44])
+ ) u_hmac (
+
+ // Interrupt
+ .intr_hmac_done_o (intr_hmac_hmac_done),
+ .intr_fifo_empty_o (intr_hmac_fifo_empty),
+ .intr_hmac_err_o (intr_hmac_hmac_err),
+ // [44]: fatal_fault
+ .alert_tx_o ( alert_tx[44:44] ),
+ .alert_rx_i ( alert_rx[44:44] ),
+
+ // Inter-module signals
+ .idle_o(clkmgr_aon_idle[1]),
+ .tl_i(hmac_tl_req),
+ .tl_o(hmac_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_hmac),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ kmac #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
+ .EnMasking(KmacEnMasking),
+ .SwKeyMasked(KmacSwKeyMasked),
+ .SecCmdDelay(SecKmacCmdDelay),
+ .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg),
+ .RndCnstLfsrSeed(RndCnstKmacLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstKmacLfsrPerm),
+ .RndCnstLfsrFwdPerm(RndCnstKmacLfsrFwdPerm),
+ .RndCnstMsgPerm(RndCnstKmacMsgPerm)
+ ) u_kmac (
+
+ // Interrupt
+ .intr_kmac_done_o (intr_kmac_kmac_done),
+ .intr_fifo_empty_o (intr_kmac_fifo_empty),
+ .intr_kmac_err_o (intr_kmac_kmac_err),
+ // [45]: recov_operation_err
+ // [46]: fatal_fault_err
+ .alert_tx_o ( alert_tx[46:45] ),
+ .alert_rx_i ( alert_rx[46:45] ),
+
+ // Inter-module signals
+ .keymgr_key_i(keymgr_kmac_key),
+ .app_i(kmac_app_req),
+ .app_o(kmac_app_rsp),
+ .entropy_o(edn0_edn_req[3]),
+ .entropy_i(edn0_edn_rsp[3]),
+ .idle_o(clkmgr_aon_idle[2]),
+ .en_masking_o(kmac_en_masking),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .tl_i(kmac_tl_req),
+ .tl_o(kmac_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_kmac),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ otbn #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
+ .Stub(OtbnStub),
+ .RegFile(OtbnRegFile),
+ .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
+ .SecMuteUrnd(SecOtbnMuteUrnd),
+ .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart),
+ .RndCnstOtbnKey(RndCnstOtbnOtbnKey),
+ .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce)
+ ) u_otbn (
+
+ // Interrupt
+ .intr_done_o (intr_otbn_done),
+ // [47]: fatal
+ // [48]: recov
+ .alert_tx_o ( alert_tx[48:47] ),
+ .alert_rx_i ( alert_rx[48:47] ),
+
+ // Inter-module signals
+ .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
+ .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp),
+ .edn_rnd_o(edn1_edn_req[0]),
+ .edn_rnd_i(edn1_edn_rsp[0]),
+ .edn_urnd_o(edn0_edn_req[6]),
+ .edn_urnd_i(edn0_edn_rsp[6]),
+ .idle_o(clkmgr_aon_idle[3]),
+ .ram_cfg_i(ast_ram_1p_cfg),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_rma_req_i(flash_ctrl_rma_ack),
+ .lc_rma_ack_o(otbn_lc_rma_ack),
+ .keymgr_key_i(keymgr_otbn_key),
+ .tl_i(otbn_tl_req),
+ .tl_o(otbn_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_otbn),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ keymgr #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
+ .KmacEnMasking(KeymgrKmacEnMasking),
+ .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
+ .RndCnstRandPerm(RndCnstKeymgrRandPerm),
+ .RndCnstRevisionSeed(RndCnstKeymgrRevisionSeed),
+ .RndCnstCreatorIdentitySeed(RndCnstKeymgrCreatorIdentitySeed),
+ .RndCnstOwnerIntIdentitySeed(RndCnstKeymgrOwnerIntIdentitySeed),
+ .RndCnstOwnerIdentitySeed(RndCnstKeymgrOwnerIdentitySeed),
+ .RndCnstSoftOutputSeed(RndCnstKeymgrSoftOutputSeed),
+ .RndCnstHardOutputSeed(RndCnstKeymgrHardOutputSeed),
+ .RndCnstAesSeed(RndCnstKeymgrAesSeed),
+ .RndCnstKmacSeed(RndCnstKeymgrKmacSeed),
+ .RndCnstOtbnSeed(RndCnstKeymgrOtbnSeed),
+ .RndCnstCdi(RndCnstKeymgrCdi),
+ .RndCnstNoneSeed(RndCnstKeymgrNoneSeed)
+ ) u_keymgr (
+
+ // Interrupt
+ .intr_op_done_o (intr_keymgr_op_done),
+ // [49]: recov_operation_err
+ // [50]: fatal_fault_err
+ .alert_tx_o ( alert_tx[50:49] ),
+ .alert_rx_i ( alert_rx[50:49] ),
+
+ // Inter-module signals
+ .edn_o(edn0_edn_req[0]),
+ .edn_i(edn0_edn_rsp[0]),
+ .aes_key_o(keymgr_aes_key),
+ .kmac_key_o(keymgr_kmac_key),
+ .otbn_key_o(keymgr_otbn_key),
+ .kmac_data_o(kmac_app_req[0]),
+ .kmac_data_i(kmac_app_rsp[0]),
+ .otp_key_i(otp_ctrl_otp_keymgr_key),
+ .otp_device_id_i(keymgr_otp_device_id),
+ .flash_i(flash_ctrl_keymgr),
+ .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en),
+ .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div),
+ .rom_digest_i(rom_ctrl_keymgr_data),
+ .kmac_en_masking_i(kmac_en_masking),
+ .tl_i(keymgr_tl_req),
+ .tl_o(keymgr_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ csrng #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
+ .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
+ .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
+ .SBoxImpl(CsrngSBoxImpl)
+ ) u_csrng (
+
+ // Interrupt
+ .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done),
+ .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
+ .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
+ .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
+ // [51]: recov_alert
+ // [52]: fatal_alert
+ .alert_tx_o ( alert_tx[52:51] ),
+ .alert_rx_i ( alert_rx[52:51] ),
+
+ // Inter-module signals
+ .csrng_cmd_i(csrng_csrng_cmd_req),
+ .csrng_cmd_o(csrng_csrng_cmd_rsp),
+ .entropy_src_hw_if_o(csrng_entropy_src_hw_if_req),
+ .entropy_src_hw_if_i(csrng_entropy_src_hw_if_rsp),
+ .cs_aes_halt_i(csrng_cs_aes_halt_req),
+ .cs_aes_halt_o(csrng_cs_aes_halt_rsp),
+ .otp_en_csrng_sw_app_read_i(csrng_otp_en_csrng_sw_app_read),
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .tl_i(csrng_tl_req),
+ .tl_o(csrng_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ entropy_src #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]),
+ .Stub(EntropySrcStub)
+ ) u_entropy_src (
+
+ // Interrupt
+ .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid),
+ .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
+ .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
+ .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
+ // [53]: recov_alert
+ // [54]: fatal_alert
+ .alert_tx_o ( alert_tx[54:53] ),
+ .alert_rx_i ( alert_rx[54:53] ),
+
+ // Inter-module signals
+ .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
+ .entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp),
+ .cs_aes_halt_o(csrng_cs_aes_halt_req),
+ .cs_aes_halt_i(csrng_cs_aes_halt_rsp),
+ .entropy_src_rng_o(es_rng_req_o),
+ .entropy_src_rng_i(es_rng_rsp_i),
+ .entropy_src_xht_o(),
+ .entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT),
+ .otp_en_entropy_src_fw_read_i(entropy_src_otp_en_entropy_src_fw_read),
+ .otp_en_entropy_src_fw_over_i(entropy_src_otp_en_entropy_src_fw_over),
+ .rng_fips_o(es_rng_fips_o),
+ .tl_i(entropy_src_tl_req),
+ .tl_o(entropy_src_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ edn #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55])
+ ) u_edn0 (
+
+ // Interrupt
+ .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
+ .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
+ // [55]: recov_alert
+ // [56]: fatal_alert
+ .alert_tx_o ( alert_tx[56:55] ),
+ .alert_rx_i ( alert_rx[56:55] ),
+
+ // Inter-module signals
+ .csrng_cmd_o(csrng_csrng_cmd_req[0]),
+ .csrng_cmd_i(csrng_csrng_cmd_rsp[0]),
+ .edn_i(edn0_edn_req),
+ .edn_o(edn0_edn_rsp),
+ .tl_i(edn0_tl_req),
+ .tl_o(edn0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ edn #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57])
+ ) u_edn1 (
+
+ // Interrupt
+ .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
+ .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
+ // [57]: recov_alert
+ // [58]: fatal_alert
+ .alert_tx_o ( alert_tx[58:57] ),
+ .alert_rx_i ( alert_rx[58:57] ),
+
+ // Inter-module signals
+ .csrng_cmd_o(csrng_csrng_cmd_req[1]),
+ .csrng_cmd_i(csrng_csrng_cmd_rsp[1]),
+ .edn_i(edn1_edn_req),
+ .edn_o(edn1_edn_rsp),
+ .tl_i(edn1_tl_req),
+ .tl_o(edn1_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ sram_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]),
+ .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
+ .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
+ .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm),
+ .MemSizeRam(131072),
+ .InstrExec(SramCtrlMainInstrExec)
+ ) u_sram_ctrl_main (
+ // [59]: fatal_error
+ .alert_tx_o ( alert_tx[59:59] ),
+ .alert_rx_i ( alert_rx[59:59] ),
+
+ // Inter-module signals
+ .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
+ .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]),
+ .cfg_i(ast_ram_1p_cfg),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
+ .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch),
+ .regs_tl_i(sram_ctrl_main_regs_tl_req),
+ .regs_tl_o(sram_ctrl_main_regs_tl_rsp),
+ .ram_tl_i(sram_ctrl_main_ram_tl_req),
+ .ram_tl_o(sram_ctrl_main_ram_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ rom_ctrl #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]),
+ .BootRomInitFile(RomCtrlBootRomInitFile),
+ .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
+ .RndCnstScrKey(RndCnstRomCtrlScrKey),
+ .SecDisableScrambling(SecRomCtrlDisableScrambling)
+ ) u_rom_ctrl (
+ // [60]: fatal
+ .alert_tx_o ( alert_tx[60:60] ),
+ .alert_rx_i ( alert_rx[60:60] ),
+
+ // Inter-module signals
+ .rom_cfg_i(ast_rom_cfg),
+ .pwrmgr_data_o(rom_ctrl_pwrmgr_data),
+ .keymgr_data_o(rom_ctrl_keymgr_data),
+ .kmac_data_o(kmac_app_req[2]),
+ .kmac_data_i(kmac_app_rsp[2]),
+ .regs_tl_i(rom_ctrl_regs_tl_req),
+ .regs_tl_o(rom_ctrl_regs_tl_rsp),
+ .rom_tl_i(rom_ctrl_rom_tl_req),
+ .rom_tl_o(rom_ctrl_rom_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_core_ibex #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]),
+ .RndCnstLfsrSeed(RndCnstRvCoreIbexSecLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstRvCoreIbexSecLfsrPerm),
+ .RndCnstIbexKeyDefault(RndCnstRvCoreIbexSecIbexKeyDefault),
+ .RndCnstIbexNonceDefault(RndCnstRvCoreIbexSecIbexNonceDefault),
+ .PMPEnable(RvCoreIbexSecPMPEnable),
+ .PMPGranularity(RvCoreIbexSecPMPGranularity),
+ .PMPNumRegions(RvCoreIbexSecPMPNumRegions),
+ .MHPMCounterNum(RvCoreIbexSecMHPMCounterNum),
+ .MHPMCounterWidth(RvCoreIbexSecMHPMCounterWidth),
+ .RV32E(RvCoreIbexSecRV32E),
+ .RV32M(RvCoreIbexSecRV32M),
+ .RV32B(RvCoreIbexSecRV32B),
+ .RegFile(RvCoreIbexSecRegFile),
+ .BranchTargetALU(RvCoreIbexSecBranchTargetALU),
+ .WritebackStage(RvCoreIbexSecWritebackStage),
+ .ICache(RvCoreIbexSecICache),
+ .ICacheECC(RvCoreIbexSecICacheECC),
+ .ICacheScramble(RvCoreIbexSecICacheScramble),
+ .BranchPredictor(RvCoreIbexSecBranchPredictor),
+ .DbgTriggerEn(RvCoreIbexSecDbgTriggerEn),
+ .DbgHwBreakNum(RvCoreIbexSecDbgHwBreakNum),
+ .SecureIbex(RvCoreIbexSecSecureIbex),
+ .DmHaltAddr(RvCoreIbexSecDmHaltAddr),
+ .DmExceptionAddr(RvCoreIbexSecDmExceptionAddr),
+ .PipeLine(RvCoreIbexSecPipeLine)
+ ) u_rv_core_ibex_sec (
+ // [61]: fatal_sw_err
+ // [62]: recov_sw_err
+ // [63]: fatal_hw_err
+ // [64]: recov_hw_err
+ .alert_tx_o ( alert_tx[64:61] ),
+ .alert_rx_i ( alert_rx[64:61] ),
+
+ // Inter-module signals
+ .rst_cpu_n_o(),
+ .ram_cfg_i(ast_ram_1p_cfg),
+ .hart_id_i(rv_core_ibex_sec_hart_id),
+ .boot_addr_i(rv_core_ibex_sec_boot_addr),
+ .irq_software_i(rv_plic_msip[0]),
+ .irq_timer_i(rv_core_ibex_sec_irq_timer),
+ .irq_external_i(rv_plic_irq[0]),
+ .esc_tx_i(alert_handler_esc_tx[0]),
+ .esc_rx_o(alert_handler_esc_rx[0]),
+ .debug_req_i(rv_dm_debug_req[0]),
+ .crash_dump_o(rv_core_ibex_sec_crash_dump),
+ .lc_cpu_en_i(lc_ctrl_lc_cpu_en),
+ .pwrmgr_cpu_en_i(pwrmgr_aon_fetch_en),
+ .pwrmgr_o(rv_core_ibex_sec_pwrmgr),
+ .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark),
+ .edn_o(edn0_edn_req[7]),
+ .edn_i(edn0_edn_rsp[7]),
+ .icache_otp_key_o(otp_ctrl_sram_otp_key_req[2]),
+ .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]),
+ .fpga_info_i(fpga_info_i),
+ .corei_tl_h_o(main_tl_rv_core_ibex_sec__corei_req),
+ .corei_tl_h_i(main_tl_rv_core_ibex_sec__corei_rsp),
+ .cored_tl_h_o(main_tl_rv_core_ibex_sec__cored_req),
+ .cored_tl_h_i(main_tl_rv_core_ibex_sec__cored_rsp),
+ .cfg_tl_d_i(rv_core_ibex_sec_cfg_tl_d_req),
+ .cfg_tl_d_o(rv_core_ibex_sec_cfg_tl_d_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ dma u_dma0 (
+
+ // Interrupt
+ .intr_writer_done_o (intr_dma0_writer_done),
+ .intr_reader_done_o (intr_dma0_reader_done),
+
+ // Inter-module signals
+ .writer_tl_h_o(main_tl_dma0__writer_req),
+ .writer_tl_h_i(main_tl_dma0__writer_rsp),
+ .reader_tl_h_o(main_tl_dma0__reader_req),
+ .reader_tl_h_i(main_tl_dma0__reader_rsp),
+ .tl_d_i(dma0_tl_d_req),
+ .tl_d_o(dma0_tl_d_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ uart #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:65])
+ ) u_smc_uart (
+
+ // Input
+ .cio_rx_i (cio_smc_uart_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_smc_uart_tx_d2p),
+ .cio_tx_en_o (cio_smc_uart_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_smc_uart_tx_watermark),
+ .intr_rx_watermark_o (intr_smc_uart_rx_watermark),
+ .intr_tx_empty_o (intr_smc_uart_tx_empty),
+ .intr_rx_overflow_o (intr_smc_uart_rx_overflow),
+ .intr_rx_frame_err_o (intr_smc_uart_rx_frame_err),
+ .intr_rx_break_err_o (intr_smc_uart_rx_break_err),
+ .intr_rx_timeout_o (intr_smc_uart_rx_timeout),
+ .intr_rx_parity_err_o (intr_smc_uart_rx_parity_err),
+ // [65]: fatal_fault
+ .alert_tx_o ( alert_tx[65:65] ),
+ .alert_rx_i ( alert_rx[65:65] ),
+
+ // Inter-module signals
+ .tl_i(smc_uart_tl_req),
+ .tl_o(smc_uart_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_timer #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[66:66])
+ ) u_rv_timer_smc (
+
+ // Interrupt
+ .intr_timer_expired_hart0_timer0_o (intr_rv_timer_smc_timer_expired_hart0_timer0),
+ // [66]: fatal_fault
+ .alert_tx_o ( alert_tx[66:66] ),
+ .alert_rx_i ( alert_rx[66:66] ),
+
+ // Inter-module signals
+ .tl_i(rv_timer_smc_tl_req),
+ .tl_o(rv_timer_smc_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ logic smc_ctrl_boot_en_o;
+ assign rv_core_ibex_smc_pwrmgr_cpu_en = lc_ctrl_pkg::lc_tx_t'(smc_ctrl_boot_en_o);
+ smc_ctrl u_smc_ctrl (
+
+ // Inter-module signals
+ .smc_boot_en_o(smc_ctrl_boot_en_o),
+ .tl_i(smc_ctrl_tl_req),
+ .tl_o(smc_ctrl_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_smc_secure),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel])
+ );
+ i2c #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[67:67])
+ ) u_cam_i2c (
+
+ // Input
+ .cio_sda_i (cio_cam_i2c_sda_p2d),
+ .cio_scl_i (cio_cam_i2c_scl_p2d),
+
+ // Output
+ .cio_sda_o (cio_cam_i2c_sda_d2p),
+ .cio_sda_en_o (cio_cam_i2c_sda_en_d2p),
+ .cio_scl_o (cio_cam_i2c_scl_d2p),
+ .cio_scl_en_o (cio_cam_i2c_scl_en_d2p),
+
+ // Interrupt
+ .intr_fmt_threshold_o (intr_cam_i2c_fmt_threshold),
+ .intr_rx_threshold_o (intr_cam_i2c_rx_threshold),
+ .intr_fmt_overflow_o (intr_cam_i2c_fmt_overflow),
+ .intr_rx_overflow_o (intr_cam_i2c_rx_overflow),
+ .intr_nak_o (intr_cam_i2c_nak),
+ .intr_scl_interference_o (intr_cam_i2c_scl_interference),
+ .intr_sda_interference_o (intr_cam_i2c_sda_interference),
+ .intr_stretch_timeout_o (intr_cam_i2c_stretch_timeout),
+ .intr_sda_unstable_o (intr_cam_i2c_sda_unstable),
+ .intr_cmd_complete_o (intr_cam_i2c_cmd_complete),
+ .intr_tx_stretch_o (intr_cam_i2c_tx_stretch),
+ .intr_tx_overflow_o (intr_cam_i2c_tx_overflow),
+ .intr_acq_full_o (intr_cam_i2c_acq_full),
+ .intr_unexp_stop_o (intr_cam_i2c_unexp_stop),
+ .intr_host_timeout_o (intr_cam_i2c_host_timeout),
+ // [67]: fatal_fault
+ .alert_tx_o ( alert_tx[67:67] ),
+ .alert_rx_i ( alert_rx[67:67] ),
+
+ // Inter-module signals
+ .tl_i(cam_i2c_tl_req),
+ .tl_o(cam_i2c_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_cam_i2c_n[rstmgr_pkg::Domain0Sel])
+ );
+ cam_ctrl u_cam_ctrl (
+
+ // Input
+ .cio_cam_int_i (cio_cam_ctrl_cam_int_p2d),
+
+ // Output
+ .cio_cam_trig_o (cio_cam_ctrl_cam_trig_d2p),
+ .cio_cam_trig_en_o (cio_cam_ctrl_cam_trig_en_d2p),
+
+ // Interrupt
+ .intr_cam_motion_detect_o (intr_cam_ctrl_cam_motion_detect),
+
+ // Inter-module signals
+ .tl_i(cam_ctrl_tl_req),
+ .tl_o(cam_ctrl_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ isp_wrapper #(
+ .AhbLiteDataWidth(IspWrapperAhbLiteDataWidth),
+ .TimeoutLimit(IspWrapperTimeoutLimit)
+ ) u_isp_wrapper (
+
+ // Input
+ .cio_s_pclk_i (cio_isp_wrapper_s_pclk_p2d),
+ .cio_s_data_i (cio_isp_wrapper_s_data_p2d),
+ .cio_s_hsync_i (cio_isp_wrapper_s_hsync_p2d),
+ .cio_s_vsync_i (cio_isp_wrapper_s_vsync_p2d),
+
+ // Interrupt
+ .intr_isp_o (intr_isp_wrapper_isp),
+ .intr_mi_o (intr_isp_wrapper_mi),
+
+ // Inter-module signals
+ .disable_isp_i('0),
+ .scanmode_i('0),
+ .out_y_r_frame_start_o(),
+ .out_y_r_frame_end_o(),
+ .out_y_r_line_start_o(),
+ .out_y_r_line_end_o(),
+ .out_cb_g_frame_start_o(),
+ .out_cb_g_frame_end_o(),
+ .out_cb_g_line_start_o(),
+ .out_cb_g_line_end_o(),
+ .out_cr_b_frame_start_o(),
+ .out_cr_b_frame_end_o(),
+ .out_cr_b_line_start_o(),
+ .out_cr_b_line_end_o(),
+ .out_y_r_val_stream_o(),
+ .out_y_r_data_stream_o(),
+ .out_cb_g_val_stream_o(),
+ .out_cb_g_data_stream_o(),
+ .out_cr_b_val_stream_o(),
+ .out_cr_b_data_stream_o(),
+ .isp_cvalid_o(isp_wrapper_isp_cvalid),
+ .isp_cready_i(isp_wrapper_isp_cready),
+ .isp_cwrite_o(isp_wrapper_isp_cwrite),
+ .isp_caddr_o(isp_wrapper_isp_caddr),
+ .isp_wdata_o(isp_wrapper_isp_wdata),
+ .isp_wmask_o(isp_wrapper_isp_wmask),
+ .isp_sp_cvalid_o(isp_wrapper_isp_sp_cvalid),
+ .isp_sp_cready_i(isp_wrapper_isp_sp_cready),
+ .isp_sp_cwrite_o(isp_wrapper_isp_sp_cwrite),
+ .isp_sp_caddr_o(isp_wrapper_isp_sp_caddr),
+ .isp_sp_wdata_o(isp_wrapper_isp_sp_wdata),
+ .isp_sp_wmask_o(isp_wrapper_isp_sp_wmask),
+ .tl_i(isp_wrapper_tl_req),
+ .tl_o(isp_wrapper_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_video_peri),
+ .clk_core_i (clkmgr_aon_clocks.clk_video_peri),
+ .clk_axi_i (clkmgr_aon_clocks.clk_video_peri),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel])
+ );
+ dma u_dma_smc (
+
+ // Interrupt
+ .intr_writer_done_o (intr_dma_smc_writer_done),
+ .intr_reader_done_o (intr_dma_smc_reader_done),
+
+ // Inter-module signals
+ .writer_tl_h_o(smc_tl_dma_smc__writer_req),
+ .writer_tl_h_i(smc_tl_dma_smc__writer_rsp),
+ .reader_tl_h_o(smc_tl_dma_smc__reader_req),
+ .reader_tl_h_i(smc_tl_dma_smc__reader_rsp),
+ .tl_d_i(dma_smc_tl_d_req),
+ .tl_d_o(dma_smc_tl_d_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_smc_infra),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_plic_smc #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[68:68])
+ ) u_rv_plic_smc (
+ // [68]: fatal_fault
+ .alert_tx_o ( alert_tx[68:68] ),
+ .alert_rx_i ( alert_rx[68:68] ),
+
+ // Inter-module signals
+ .irq_o(rv_plic_smc_irq),
+ .irq_id_o(),
+ .msip_o(rv_plic_smc_msip),
+ .tl_i(rv_plic_smc_tl_req),
+ .tl_o(rv_plic_smc_tl_rsp),
+ .intr_src_i (smc_intr_vector),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_smc_infra),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel])
+ );
+ tlul_mailbox #(
+ .MailboxDepth(TlulMailboxSecMailboxDepth)
+ ) u_tlul_mailbox_sec (
+
+ // Interrupt
+ .intr_core0_wtirq_o (intr_tlul_mailbox_sec_wtirq),
+ .intr_core1_wtirq_o (intr_tlul_mailbox_smc_wtirq),
+ .intr_core0_rtirq_o (intr_tlul_mailbox_sec_rtirq),
+ .intr_core1_rtirq_o (intr_tlul_mailbox_smc_rtirq),
+ .intr_core0_eirq_o (intr_tlul_mailbox_sec_eirq),
+ .intr_core1_eirq_o (intr_tlul_mailbox_smc_eirq),
+
+ // Inter-module signals
+ .core0_tl_i(tlul_mailbox_sec_tl_req),
+ .core0_tl_o(tlul_mailbox_sec_tl_rsp),
+
+ .core1_tl_i(tlul_mailbox_smc_tl_req),
+ .core1_tl_o(tlul_mailbox_smc_tl_rsp),
+
+ .test_i (1'b0),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
+ );
+ ml_top u_ml_top (
+
+ // Interrupt
+ .intr_host_req_o (intr_ml_top_host_req),
+ .intr_finish_o (intr_ml_top_finish),
+ .intr_fault_o (intr_ml_top_fault),
+
+ // Inter-module signals
+ .isp_cvalid_i(isp_wrapper_isp_cvalid),
+ .isp_cready_o(isp_wrapper_isp_cready),
+ .isp_cwrite_i(isp_wrapper_isp_cwrite),
+ .isp_caddr_i(isp_wrapper_isp_caddr),
+ .isp_wdata_i(isp_wrapper_isp_wdata),
+ .isp_wmask_i(isp_wrapper_isp_wmask),
+ .isp_sp_cvalid_i(isp_wrapper_isp_sp_cvalid),
+ .isp_sp_cready_o(isp_wrapper_isp_sp_cready),
+ .isp_sp_cwrite_i(isp_wrapper_isp_sp_cwrite),
+ .isp_sp_caddr_i(isp_wrapper_isp_sp_caddr),
+ .isp_sp_wdata_i(isp_wrapper_isp_sp_wdata),
+ .isp_sp_wmask_i(isp_wrapper_isp_sp_wmask),
+ .debug_req_i(rv_dm_debug_req[2]),
+ .core_tl_i(ml_top_core_tl_req),
+ .core_tl_o(ml_top_core_tl_rsp),
+ .dmem_tl_i(ml_top_dmem_tl_req),
+ .dmem_tl_o(ml_top_dmem_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_ml_peri),
+ .rst_ni (rstmgr_aon_resets.rst_ml_n[rstmgr_pkg::Domain0Sel])
+ );
+ spi_host #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[69:69])
+ ) u_spi_host2 (
+
+ // Input
+ .cio_sd_i (cio_spi_host2_sd_p2d),
+
+ // Output
+ .cio_sck_o (cio_spi_host2_sck_d2p),
+ .cio_sck_en_o (cio_spi_host2_sck_en_d2p),
+ .cio_csb_o (cio_spi_host2_csb_d2p),
+ .cio_csb_en_o (cio_spi_host2_csb_en_d2p),
+ .cio_sd_o (cio_spi_host2_sd_d2p),
+ .cio_sd_en_o (cio_spi_host2_sd_en_d2p),
+
+ // Interrupt
+ .intr_error_o (intr_spi_host2_error),
+ .intr_spi_event_o (intr_spi_host2_spi_event),
+ // [69]: fatal_fault
+ .alert_tx_o ( alert_tx[69:69] ),
+ .alert_rx_i ( alert_rx[69:69] ),
+
+ // Inter-module signals
+ .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
+ .passthrough_o(),
+ .tl_i(spi_host2_tl_req),
+ .tl_o(spi_host2_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_host2_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_timer #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[70:70])
+ ) u_rv_timer_smc2 (
+
+ // Interrupt
+ .intr_timer_expired_hart0_timer0_o (intr_rv_timer_smc2_timer_expired_hart0_timer0),
+ // [70]: fatal_fault
+ .alert_tx_o ( alert_tx[70:70] ),
+ .alert_rx_i ( alert_rx[70:70] ),
+
+ // Inter-module signals
+ .tl_i(rv_timer_smc2_tl_req),
+ .tl_o(rv_timer_smc2_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ i2s u_i2s0 (
+
+ // Input
+ .cio_rx_sd_i (cio_i2s0_rx_sd_p2d),
+
+ // Output
+ .cio_rx_sclk_o (cio_i2s0_rx_sclk_d2p),
+ .cio_rx_sclk_en_o (cio_i2s0_rx_sclk_en_d2p),
+ .cio_rx_ws_o (cio_i2s0_rx_ws_d2p),
+ .cio_rx_ws_en_o (cio_i2s0_rx_ws_en_d2p),
+ .cio_tx_sclk_o (cio_i2s0_tx_sclk_d2p),
+ .cio_tx_sclk_en_o (cio_i2s0_tx_sclk_en_d2p),
+ .cio_tx_ws_o (cio_i2s0_tx_ws_d2p),
+ .cio_tx_ws_en_o (cio_i2s0_tx_ws_en_d2p),
+ .cio_tx_sd_o (cio_i2s0_tx_sd_d2p),
+ .cio_tx_sd_en_o (cio_i2s0_tx_sd_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_i2s0_tx_watermark),
+ .intr_rx_watermark_o (intr_i2s0_rx_watermark),
+ .intr_tx_empty_o (intr_i2s0_tx_empty),
+ .intr_rx_overflow_o (intr_i2s0_rx_overflow),
+
+ // Inter-module signals
+ .tl_i(i2s0_tl_req),
+ .tl_o(i2s0_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .clk_audio_i (clkmgr_aon_clocks.clk_audio_peri),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+ rv_core_smc #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[74:71]),
+ .RndCnstLfsrSeed(RndCnstRvCoreIbexSmcLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstRvCoreIbexSmcLfsrPerm),
+ .RndCnstSmcKeyDefault(RndCnstRvCoreIbexSmcSmcKeyDefault),
+ .RndCnstSmcNonceDefault(RndCnstRvCoreIbexSmcSmcNonceDefault),
+ .PMPEnable(RvCoreIbexSmcPMPEnable),
+ .PMPGranularity(RvCoreIbexSmcPMPGranularity),
+ .PMPNumRegions(RvCoreIbexSmcPMPNumRegions),
+ .MHPMCounterNum(RvCoreIbexSmcMHPMCounterNum),
+ .MHPMCounterWidth(RvCoreIbexSmcMHPMCounterWidth),
+ .RV32E(RvCoreIbexSmcRV32E),
+ .RV32M(RvCoreIbexSmcRV32M),
+ .RV32B(RvCoreIbexSmcRV32B),
+ .RV32A(RvCoreIbexSmcRV32A),
+ .RegFile(RvCoreIbexSmcRegFile),
+ .BranchTargetALU(RvCoreIbexSmcBranchTargetALU),
+ .WritebackStage(RvCoreIbexSmcWritebackStage),
+ .ICache(RvCoreIbexSmcICache),
+ .ICacheECC(RvCoreIbexSmcICacheECC),
+ .ICacheScramble(RvCoreIbexSmcICacheScramble),
+ .BranchPredictor(RvCoreIbexSmcBranchPredictor),
+ .DbgTriggerEn(RvCoreIbexSmcDbgTriggerEn),
+ .DbgHwBreakNum(RvCoreIbexSmcDbgHwBreakNum),
+ .SecureSmc(RvCoreIbexSmcSecureSmc),
+ .DmHaltAddr(RvCoreIbexSmcDmHaltAddr),
+ .DmExceptionAddr(RvCoreIbexSmcDmExceptionAddr),
+ .PipeLine(RvCoreIbexSmcPipeLine),
+ .ITLBEntries(RvCoreIbexSmcITLBEntries),
+ .DTLBEntries(RvCoreIbexSmcDTLBEntries),
+ .ASIDWidth(RvCoreIbexSmcASIDWidth)
+ ) u_rv_core_ibex_smc (
+ // [71]: fatal_sw_err
+ // [72]: recov_sw_err
+ // [73]: fatal_hw_err
+ // [74]: recov_hw_err
+ .alert_tx_o ( alert_tx[74:71] ),
+ .alert_rx_i ( alert_rx[74:71] ),
+
+ // Inter-module signals
+ .rst_cpu_n_o(),
+ .ram_cfg_i(ast_ram_1p_cfg),
+ .hart_id_i(rv_core_ibex_smc_hart_id),
+ .boot_addr_i(rv_core_ibex_smc_boot_addr),
+ .irq_software_i(rv_plic_smc_msip),
+ .irq_timer_i(rv_core_ibex_smc_irq_timer),
+ .irq_external_i(rv_plic_smc_irq),
+ .esc_tx_i(prim_esc_pkg::ESC_TX_DEFAULT),
+ .esc_rx_o(),
+ .debug_req_i(rv_dm_debug_req[1]),
+ .crash_dump_o(),
+ .lc_cpu_en_i(lc_ctrl_lc_cpu_en),
+ .pwrmgr_cpu_en_i(rv_core_ibex_smc_pwrmgr_cpu_en),
+ .pwrmgr_o(),
+ .nmi_wdog_i('0),
+ .edn_o(),
+ .edn_i(edn_pkg::EDN_RSP_DEFAULT),
+ .icache_otp_key_o(),
+ .icache_otp_key_i(otp_ctrl_pkg::SRAM_OTP_KEY_RSP_DEFAULT),
+ .fpga_info_i('0),
+ .corei_tl_h_o(smc_tl_rv_core_ibex_smc__corei_req),
+ .corei_tl_h_i(smc_tl_rv_core_ibex_smc__corei_rsp),
+ .cored_tl_h_o(smc_tl_rv_core_ibex_smc__cored_req),
+ .cored_tl_h_i(smc_tl_rv_core_ibex_smc__cored_rsp),
+ .cfg_tl_d_i(rv_core_ibex_smc_cfg_tl_d_req),
+ .cfg_tl_d_o(rv_core_ibex_smc_cfg_tl_d_rsp),
+ .scanmode_i,
+ .scan_rst_ni,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_smc_peri),
+ .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ // security core interrupt assignments
+ assign sec_intr_vector = {
+ intr_tlul_mailbox_sec_eirq, // IDs [189 +: 1]
+ intr_tlul_mailbox_sec_rtirq, // IDs [188 +: 1]
+ intr_tlul_mailbox_sec_wtirq, // IDs [187 +: 1]
+ intr_dma0_reader_done, // IDs [186 +: 1]
+ intr_dma0_writer_done, // IDs [185 +: 1]
+ intr_edn1_edn_fatal_err, // IDs [184 +: 1]
+ intr_edn1_edn_cmd_req_done, // IDs [183 +: 1]
+ intr_edn0_edn_fatal_err, // IDs [182 +: 1]
+ intr_edn0_edn_cmd_req_done, // IDs [181 +: 1]
+ intr_entropy_src_es_fatal_err, // IDs [180 +: 1]
+ intr_entropy_src_es_observe_fifo_ready, // IDs [179 +: 1]
+ intr_entropy_src_es_health_test_failed, // IDs [178 +: 1]
+ intr_entropy_src_es_entropy_valid, // IDs [177 +: 1]
+ intr_csrng_cs_fatal_err, // IDs [176 +: 1]
+ intr_csrng_cs_hw_inst_exc, // IDs [175 +: 1]
+ intr_csrng_cs_entropy_req, // IDs [174 +: 1]
+ intr_csrng_cs_cmd_req_done, // IDs [173 +: 1]
+ intr_keymgr_op_done, // IDs [172 +: 1]
+ intr_otbn_done, // IDs [171 +: 1]
+ intr_kmac_kmac_err, // IDs [170 +: 1]
+ intr_kmac_fifo_empty, // IDs [169 +: 1]
+ intr_kmac_kmac_done, // IDs [168 +: 1]
+ intr_hmac_hmac_err, // IDs [167 +: 1]
+ intr_hmac_fifo_empty, // IDs [166 +: 1]
+ intr_hmac_hmac_done, // IDs [165 +: 1]
+ intr_flash_ctrl_corr_err, // IDs [164 +: 1]
+ intr_flash_ctrl_op_done, // IDs [163 +: 1]
+ intr_flash_ctrl_rd_lvl, // IDs [162 +: 1]
+ intr_flash_ctrl_rd_full, // IDs [161 +: 1]
+ intr_flash_ctrl_prog_lvl, // IDs [160 +: 1]
+ intr_flash_ctrl_prog_empty, // IDs [159 +: 1]
+ intr_sensor_ctrl_init_status_change, // IDs [158 +: 1]
+ intr_sensor_ctrl_io_status_change, // IDs [157 +: 1]
+ intr_aon_timer_aon_wdog_timer_bark, // IDs [156 +: 1]
+ intr_aon_timer_aon_wkup_timer_expired, // IDs [155 +: 1]
+ intr_adc_ctrl_aon_match_done, // IDs [154 +: 1]
+ intr_sysrst_ctrl_aon_event_detected, // IDs [153 +: 1]
+ intr_pwrmgr_aon_wakeup, // IDs [152 +: 1]
+ intr_usbdev_link_out_err, // IDs [151 +: 1]
+ intr_usbdev_powered, // IDs [150 +: 1]
+ intr_usbdev_frame, // IDs [149 +: 1]
+ intr_usbdev_rx_bitstuff_err, // IDs [148 +: 1]
+ intr_usbdev_rx_pid_err, // IDs [147 +: 1]
+ intr_usbdev_rx_crc_err, // IDs [146 +: 1]
+ intr_usbdev_link_in_err, // IDs [145 +: 1]
+ intr_usbdev_av_overflow, // IDs [144 +: 1]
+ intr_usbdev_rx_full, // IDs [143 +: 1]
+ intr_usbdev_av_empty, // IDs [142 +: 1]
+ intr_usbdev_link_resume, // IDs [141 +: 1]
+ intr_usbdev_link_suspend, // IDs [140 +: 1]
+ intr_usbdev_link_reset, // IDs [139 +: 1]
+ intr_usbdev_host_lost, // IDs [138 +: 1]
+ intr_usbdev_disconnected, // IDs [137 +: 1]
+ intr_usbdev_pkt_sent, // IDs [136 +: 1]
+ intr_usbdev_pkt_received, // IDs [135 +: 1]
+ intr_spi_host1_spi_event, // IDs [134 +: 1]
+ intr_spi_host1_error, // IDs [133 +: 1]
+ intr_spi_host0_spi_event, // IDs [132 +: 1]
+ intr_spi_host0_error, // IDs [131 +: 1]
+ intr_alert_handler_classd, // IDs [130 +: 1]
+ intr_alert_handler_classc, // IDs [129 +: 1]
+ intr_alert_handler_classb, // IDs [128 +: 1]
+ intr_alert_handler_classa, // IDs [127 +: 1]
+ intr_otp_ctrl_otp_error, // IDs [126 +: 1]
+ intr_otp_ctrl_otp_operation_done, // IDs [125 +: 1]
+ intr_rv_timer_timer_expired_hart0_timer0, // IDs [124 +: 1]
+ intr_pattgen_done_ch1, // IDs [123 +: 1]
+ intr_pattgen_done_ch0, // IDs [122 +: 1]
+ intr_i2c2_host_timeout, // IDs [121 +: 1]
+ intr_i2c2_unexp_stop, // IDs [120 +: 1]
+ intr_i2c2_acq_full, // IDs [119 +: 1]
+ intr_i2c2_tx_overflow, // IDs [118 +: 1]
+ intr_i2c2_tx_stretch, // IDs [117 +: 1]
+ intr_i2c2_cmd_complete, // IDs [116 +: 1]
+ intr_i2c2_sda_unstable, // IDs [115 +: 1]
+ intr_i2c2_stretch_timeout, // IDs [114 +: 1]
+ intr_i2c2_sda_interference, // IDs [113 +: 1]
+ intr_i2c2_scl_interference, // IDs [112 +: 1]
+ intr_i2c2_nak, // IDs [111 +: 1]
+ intr_i2c2_rx_overflow, // IDs [110 +: 1]
+ intr_i2c2_fmt_overflow, // IDs [109 +: 1]
+ intr_i2c2_rx_threshold, // IDs [108 +: 1]
+ intr_i2c2_fmt_threshold, // IDs [107 +: 1]
+ intr_i2c1_host_timeout, // IDs [106 +: 1]
+ intr_i2c1_unexp_stop, // IDs [105 +: 1]
+ intr_i2c1_acq_full, // IDs [104 +: 1]
+ intr_i2c1_tx_overflow, // IDs [103 +: 1]
+ intr_i2c1_tx_stretch, // IDs [102 +: 1]
+ intr_i2c1_cmd_complete, // IDs [101 +: 1]
+ intr_i2c1_sda_unstable, // IDs [100 +: 1]
+ intr_i2c1_stretch_timeout, // IDs [99 +: 1]
+ intr_i2c1_sda_interference, // IDs [98 +: 1]
+ intr_i2c1_scl_interference, // IDs [97 +: 1]
+ intr_i2c1_nak, // IDs [96 +: 1]
+ intr_i2c1_rx_overflow, // IDs [95 +: 1]
+ intr_i2c1_fmt_overflow, // IDs [94 +: 1]
+ intr_i2c1_rx_threshold, // IDs [93 +: 1]
+ intr_i2c1_fmt_threshold, // IDs [92 +: 1]
+ intr_i2c0_host_timeout, // IDs [91 +: 1]
+ intr_i2c0_unexp_stop, // IDs [90 +: 1]
+ intr_i2c0_acq_full, // IDs [89 +: 1]
+ intr_i2c0_tx_overflow, // IDs [88 +: 1]
+ intr_i2c0_tx_stretch, // IDs [87 +: 1]
+ intr_i2c0_cmd_complete, // IDs [86 +: 1]
+ intr_i2c0_sda_unstable, // IDs [85 +: 1]
+ intr_i2c0_stretch_timeout, // IDs [84 +: 1]
+ intr_i2c0_sda_interference, // IDs [83 +: 1]
+ intr_i2c0_scl_interference, // IDs [82 +: 1]
+ intr_i2c0_nak, // IDs [81 +: 1]
+ intr_i2c0_rx_overflow, // IDs [80 +: 1]
+ intr_i2c0_fmt_overflow, // IDs [79 +: 1]
+ intr_i2c0_rx_threshold, // IDs [78 +: 1]
+ intr_i2c0_fmt_threshold, // IDs [77 +: 1]
+ intr_spi_device_tpm_header_not_empty, // IDs [76 +: 1]
+ intr_spi_device_readbuf_flip, // IDs [75 +: 1]
+ intr_spi_device_readbuf_watermark, // IDs [74 +: 1]
+ intr_spi_device_upload_payload_overflow, // IDs [73 +: 1]
+ intr_spi_device_upload_payload_not_empty, // IDs [72 +: 1]
+ intr_spi_device_upload_cmdfifo_not_empty, // IDs [71 +: 1]
+ intr_spi_device_generic_tx_underflow, // IDs [70 +: 1]
+ intr_spi_device_generic_rx_overflow, // IDs [69 +: 1]
+ intr_spi_device_generic_rx_error, // IDs [68 +: 1]
+ intr_spi_device_generic_tx_watermark, // IDs [67 +: 1]
+ intr_spi_device_generic_rx_watermark, // IDs [66 +: 1]
+ intr_spi_device_generic_rx_full, // IDs [65 +: 1]
+ intr_gpio_gpio, // IDs [33 +: 32]
+ intr_uart3_rx_parity_err, // IDs [32 +: 1]
+ intr_uart3_rx_timeout, // IDs [31 +: 1]
+ intr_uart3_rx_break_err, // IDs [30 +: 1]
+ intr_uart3_rx_frame_err, // IDs [29 +: 1]
+ intr_uart3_rx_overflow, // IDs [28 +: 1]
+ intr_uart3_tx_empty, // IDs [27 +: 1]
+ intr_uart3_rx_watermark, // IDs [26 +: 1]
+ intr_uart3_tx_watermark, // IDs [25 +: 1]
+ intr_uart2_rx_parity_err, // IDs [24 +: 1]
+ intr_uart2_rx_timeout, // IDs [23 +: 1]
+ intr_uart2_rx_break_err, // IDs [22 +: 1]
+ intr_uart2_rx_frame_err, // IDs [21 +: 1]
+ intr_uart2_rx_overflow, // IDs [20 +: 1]
+ intr_uart2_tx_empty, // IDs [19 +: 1]
+ intr_uart2_rx_watermark, // IDs [18 +: 1]
+ intr_uart2_tx_watermark, // IDs [17 +: 1]
+ intr_uart1_rx_parity_err, // IDs [16 +: 1]
+ intr_uart1_rx_timeout, // IDs [15 +: 1]
+ intr_uart1_rx_break_err, // IDs [14 +: 1]
+ intr_uart1_rx_frame_err, // IDs [13 +: 1]
+ intr_uart1_rx_overflow, // IDs [12 +: 1]
+ intr_uart1_tx_empty, // IDs [11 +: 1]
+ intr_uart1_rx_watermark, // IDs [10 +: 1]
+ intr_uart1_tx_watermark, // IDs [9 +: 1]
+ intr_uart0_rx_parity_err, // IDs [8 +: 1]
+ intr_uart0_rx_timeout, // IDs [7 +: 1]
+ intr_uart0_rx_break_err, // IDs [6 +: 1]
+ intr_uart0_rx_frame_err, // IDs [5 +: 1]
+ intr_uart0_rx_overflow, // IDs [4 +: 1]
+ intr_uart0_tx_empty, // IDs [3 +: 1]
+ intr_uart0_rx_watermark, // IDs [2 +: 1]
+ intr_uart0_tx_watermark, // IDs [1 +: 1]
+ 1'b 0 // ID [0 +: 1] is a special case and tied to zero.
+ };
+
+ // smc core interrupt assignments
+ assign smc_intr_vector = {
+ intr_i2s0_rx_overflow, // IDs [42 +: 1]
+ intr_i2s0_tx_empty, // IDs [41 +: 1]
+ intr_i2s0_rx_watermark, // IDs [40 +: 1]
+ intr_i2s0_tx_watermark, // IDs [39 +: 1]
+ intr_rv_timer_smc2_timer_expired_hart0_timer0, // IDs [38 +: 1]
+ intr_spi_host2_spi_event, // IDs [37 +: 1]
+ intr_spi_host2_error, // IDs [36 +: 1]
+ intr_ml_top_fault, // IDs [35 +: 1]
+ intr_ml_top_finish, // IDs [34 +: 1]
+ intr_ml_top_host_req, // IDs [33 +: 1]
+ intr_tlul_mailbox_smc_eirq, // IDs [32 +: 1]
+ intr_tlul_mailbox_smc_rtirq, // IDs [31 +: 1]
+ intr_tlul_mailbox_smc_wtirq, // IDs [30 +: 1]
+ intr_dma_smc_reader_done, // IDs [29 +: 1]
+ intr_dma_smc_writer_done, // IDs [28 +: 1]
+ intr_isp_wrapper_mi, // IDs [27 +: 1]
+ intr_isp_wrapper_isp, // IDs [26 +: 1]
+ intr_cam_ctrl_cam_motion_detect, // IDs [25 +: 1]
+ intr_cam_i2c_host_timeout, // IDs [24 +: 1]
+ intr_cam_i2c_unexp_stop, // IDs [23 +: 1]
+ intr_cam_i2c_acq_full, // IDs [22 +: 1]
+ intr_cam_i2c_tx_overflow, // IDs [21 +: 1]
+ intr_cam_i2c_tx_stretch, // IDs [20 +: 1]
+ intr_cam_i2c_cmd_complete, // IDs [19 +: 1]
+ intr_cam_i2c_sda_unstable, // IDs [18 +: 1]
+ intr_cam_i2c_stretch_timeout, // IDs [17 +: 1]
+ intr_cam_i2c_sda_interference, // IDs [16 +: 1]
+ intr_cam_i2c_scl_interference, // IDs [15 +: 1]
+ intr_cam_i2c_nak, // IDs [14 +: 1]
+ intr_cam_i2c_rx_overflow, // IDs [13 +: 1]
+ intr_cam_i2c_fmt_overflow, // IDs [12 +: 1]
+ intr_cam_i2c_rx_threshold, // IDs [11 +: 1]
+ intr_cam_i2c_fmt_threshold, // IDs [10 +: 1]
+ intr_rv_timer_smc_timer_expired_hart0_timer0, // IDs [9 +: 1]
+ intr_smc_uart_rx_parity_err, // IDs [8 +: 1]
+ intr_smc_uart_rx_timeout, // IDs [7 +: 1]
+ intr_smc_uart_rx_break_err, // IDs [6 +: 1]
+ intr_smc_uart_rx_frame_err, // IDs [5 +: 1]
+ intr_smc_uart_rx_overflow, // IDs [4 +: 1]
+ intr_smc_uart_tx_empty, // IDs [3 +: 1]
+ intr_smc_uart_rx_watermark, // IDs [2 +: 1]
+ intr_smc_uart_tx_watermark, // IDs [1 +: 1]
+ 1'b 0 // ID [0 +: 1] is a special case and tied to zero.
+ };
+
+
+ // TL-UL Crossbar
+ xbar_main u_xbar_main (
+ .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_usb_i (clkmgr_aon_clocks.clk_usb_infra),
+ .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra),
+ .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_infra),
+ .clk_smc_i (clkmgr_aon_clocks.clk_smc_infra),
+ .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::Domain0Sel]),
+ .rst_spi_host0_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
+ .rst_spi_host1_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
+ .rst_smc_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]),
+
+ // port: tl_rv_core_ibex_sec__corei
+ .tl_rv_core_ibex_sec__corei_i(main_tl_rv_core_ibex_sec__corei_req),
+ .tl_rv_core_ibex_sec__corei_o(main_tl_rv_core_ibex_sec__corei_rsp),
+
+ // port: tl_rv_core_ibex_sec__cored
+ .tl_rv_core_ibex_sec__cored_i(main_tl_rv_core_ibex_sec__cored_req),
+ .tl_rv_core_ibex_sec__cored_o(main_tl_rv_core_ibex_sec__cored_rsp),
+
+ // port: tl_rv_dm__sba
+ .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req),
+ .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp),
+
+ // port: tl_dma0__reader
+ .tl_dma0__reader_i(main_tl_dma0__reader_req),
+ .tl_dma0__reader_o(main_tl_dma0__reader_rsp),
+
+ // port: tl_dma0__writer
+ .tl_dma0__writer_i(main_tl_dma0__writer_req),
+ .tl_dma0__writer_o(main_tl_dma0__writer_rsp),
+
+ // port: tl_dma0
+ .tl_dma0_o(dma0_tl_d_req),
+ .tl_dma0_i(dma0_tl_d_rsp),
+
+ // port: tl_rom_ctrl__rom
+ .tl_rom_ctrl__rom_o(rom_ctrl_rom_tl_req),
+ .tl_rom_ctrl__rom_i(rom_ctrl_rom_tl_rsp),
+
+ // port: tl_rom_ctrl__regs
+ .tl_rom_ctrl__regs_o(rom_ctrl_regs_tl_req),
+ .tl_rom_ctrl__regs_i(rom_ctrl_regs_tl_rsp),
+
+ // port: tl_peri
+ .tl_peri_o(main_tl_peri_req),
+ .tl_peri_i(main_tl_peri_rsp),
+
+ // port: tl_spi_host0
+ .tl_spi_host0_o(spi_host0_tl_req),
+ .tl_spi_host0_i(spi_host0_tl_rsp),
+
+ // port: tl_spi_host1
+ .tl_spi_host1_o(spi_host1_tl_req),
+ .tl_spi_host1_i(spi_host1_tl_rsp),
+
+ // port: tl_usbdev
+ .tl_usbdev_o(usbdev_tl_req),
+ .tl_usbdev_i(usbdev_tl_rsp),
+
+ // port: tl_flash_ctrl__core
+ .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req),
+ .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp),
+
+ // port: tl_flash_ctrl__prim
+ .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req),
+ .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp),
+
+ // port: tl_flash_ctrl__mem
+ .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req),
+ .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp),
+
+ // port: tl_hmac
+ .tl_hmac_o(hmac_tl_req),
+ .tl_hmac_i(hmac_tl_rsp),
+
+ // port: tl_kmac
+ .tl_kmac_o(kmac_tl_req),
+ .tl_kmac_i(kmac_tl_rsp),
+
+ // port: tl_aes
+ .tl_aes_o(aes_tl_req),
+ .tl_aes_i(aes_tl_rsp),
+
+ // port: tl_entropy_src
+ .tl_entropy_src_o(entropy_src_tl_req),
+ .tl_entropy_src_i(entropy_src_tl_rsp),
+
+ // port: tl_csrng
+ .tl_csrng_o(csrng_tl_req),
+ .tl_csrng_i(csrng_tl_rsp),
+
+ // port: tl_edn0
+ .tl_edn0_o(edn0_tl_req),
+ .tl_edn0_i(edn0_tl_rsp),
+
+ // port: tl_edn1
+ .tl_edn1_o(edn1_tl_req),
+ .tl_edn1_i(edn1_tl_rsp),
+
+ // port: tl_rv_plic
+ .tl_rv_plic_o(rv_plic_tl_req),
+ .tl_rv_plic_i(rv_plic_tl_rsp),
+
+ // port: tl_otbn
+ .tl_otbn_o(otbn_tl_req),
+ .tl_otbn_i(otbn_tl_rsp),
+
+ // port: tl_keymgr
+ .tl_keymgr_o(keymgr_tl_req),
+ .tl_keymgr_i(keymgr_tl_rsp),
+
+ // port: tl_rv_core_ibex_sec__cfg
+ .tl_rv_core_ibex_sec__cfg_o(rv_core_ibex_sec_cfg_tl_d_req),
+ .tl_rv_core_ibex_sec__cfg_i(rv_core_ibex_sec_cfg_tl_d_rsp),
+
+ // port: tl_sram_ctrl_main__regs
+ .tl_sram_ctrl_main__regs_o(sram_ctrl_main_regs_tl_req),
+ .tl_sram_ctrl_main__regs_i(sram_ctrl_main_regs_tl_rsp),
+
+ // port: tl_sram_ctrl_main__ram
+ .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req),
+ .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp),
+
+ // port: tl_tlul_mailbox_sec
+ .tl_tlul_mailbox_sec_o(tlul_mailbox_sec_tl_req),
+ .tl_tlul_mailbox_sec_i(tlul_mailbox_sec_tl_rsp),
+
+ // port: tl_smc
+ .tl_smc_o(main_tl_smc_req),
+ .tl_smc_i(main_tl_smc_rsp),
+
+ // port: tl_dbg
+ .tl_dbg_o(main_tl_dbg_req),
+ .tl_dbg_i(main_tl_dbg_rsp),
+
+
+ .scanmode_i
+ );
+ xbar_peri u_xbar_peri (
+ .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+
+ // port: tl_main
+ .tl_main_i(main_tl_peri_req),
+ .tl_main_o(main_tl_peri_rsp),
+
+ // port: tl_uart0
+ .tl_uart0_o(uart0_tl_req),
+ .tl_uart0_i(uart0_tl_rsp),
+
+ // port: tl_uart1
+ .tl_uart1_o(uart1_tl_req),
+ .tl_uart1_i(uart1_tl_rsp),
+
+ // port: tl_uart2
+ .tl_uart2_o(uart2_tl_req),
+ .tl_uart2_i(uart2_tl_rsp),
+
+ // port: tl_uart3
+ .tl_uart3_o(uart3_tl_req),
+ .tl_uart3_i(uart3_tl_rsp),
+
+ // port: tl_i2c0
+ .tl_i2c0_o(i2c0_tl_req),
+ .tl_i2c0_i(i2c0_tl_rsp),
+
+ // port: tl_i2c1
+ .tl_i2c1_o(i2c1_tl_req),
+ .tl_i2c1_i(i2c1_tl_rsp),
+
+ // port: tl_i2c2
+ .tl_i2c2_o(i2c2_tl_req),
+ .tl_i2c2_i(i2c2_tl_rsp),
+
+ // port: tl_pattgen
+ .tl_pattgen_o(pattgen_tl_req),
+ .tl_pattgen_i(pattgen_tl_rsp),
+
+ // port: tl_pwm_aon
+ .tl_pwm_aon_o(pwm_aon_tl_req),
+ .tl_pwm_aon_i(pwm_aon_tl_rsp),
+
+ // port: tl_gpio
+ .tl_gpio_o(gpio_tl_req),
+ .tl_gpio_i(gpio_tl_rsp),
+
+ // port: tl_spi_device
+ .tl_spi_device_o(spi_device_tl_req),
+ .tl_spi_device_i(spi_device_tl_rsp),
+
+ // port: tl_rv_timer
+ .tl_rv_timer_o(rv_timer_tl_req),
+ .tl_rv_timer_i(rv_timer_tl_rsp),
+
+ // port: tl_pwrmgr_aon
+ .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req),
+ .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp),
+
+ // port: tl_rstmgr_aon
+ .tl_rstmgr_aon_o(rstmgr_aon_tl_req),
+ .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp),
+
+ // port: tl_clkmgr_aon
+ .tl_clkmgr_aon_o(clkmgr_aon_tl_req),
+ .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp),
+
+ // port: tl_pinmux_aon
+ .tl_pinmux_aon_o(pinmux_aon_tl_req),
+ .tl_pinmux_aon_i(pinmux_aon_tl_rsp),
+
+ // port: tl_otp_ctrl__core
+ .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req),
+ .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp),
+
+ // port: tl_otp_ctrl__prim
+ .tl_otp_ctrl__prim_o(otp_ctrl_prim_tl_req),
+ .tl_otp_ctrl__prim_i(otp_ctrl_prim_tl_rsp),
+
+ // port: tl_lc_ctrl
+ .tl_lc_ctrl_o(lc_ctrl_tl_req),
+ .tl_lc_ctrl_i(lc_ctrl_tl_rsp),
+
+ // port: tl_sensor_ctrl
+ .tl_sensor_ctrl_o(sensor_ctrl_tl_req),
+ .tl_sensor_ctrl_i(sensor_ctrl_tl_rsp),
+
+ // port: tl_alert_handler
+ .tl_alert_handler_o(alert_handler_tl_req),
+ .tl_alert_handler_i(alert_handler_tl_rsp),
+
+ // port: tl_sram_ctrl_ret_aon__regs
+ .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req),
+ .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp),
+
+ // port: tl_sram_ctrl_ret_aon__ram
+ .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req),
+ .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp),
+
+ // port: tl_aon_timer_aon
+ .tl_aon_timer_aon_o(aon_timer_aon_tl_req),
+ .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp),
+
+ // port: tl_sysrst_ctrl_aon
+ .tl_sysrst_ctrl_aon_o(sysrst_ctrl_aon_tl_req),
+ .tl_sysrst_ctrl_aon_i(sysrst_ctrl_aon_tl_rsp),
+
+ // port: tl_adc_ctrl_aon
+ .tl_adc_ctrl_aon_o(adc_ctrl_aon_tl_req),
+ .tl_adc_ctrl_aon_i(adc_ctrl_aon_tl_rsp),
+
+ // port: tl_ast
+ .tl_ast_o(ast_tl_req_o),
+ .tl_ast_i(ast_tl_rsp_i),
+
+
+ .scanmode_i
+ );
+ xbar_smc u_xbar_smc (
+ .clk_smc_i (clkmgr_aon_clocks.clk_smc_infra),
+ .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .clk_spi_host2_i (clkmgr_aon_clocks.clk_io_infra),
+ .clk_ml_i (clkmgr_aon_clocks.clk_ml_infra),
+ .clk_video_i (clkmgr_aon_clocks.clk_video_infra),
+ .clk_audio_i (clkmgr_aon_clocks.clk_audio_infra),
+ .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_smc_ni (rstmgr_aon_resets.rst_smc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_spi_host2_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
+ .rst_ml_ni (rstmgr_aon_resets.rst_ml_n[rstmgr_pkg::Domain0Sel]),
+ .rst_video_ni (rstmgr_aon_resets.rst_video_n[rstmgr_pkg::Domain0Sel]),
+ .rst_audio_ni (rstmgr_aon_resets.rst_audio_n[rstmgr_pkg::Domain0Sel]),
+ .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+
+ // port: tl_main
+ .tl_main_i(main_tl_smc_req),
+ .tl_main_o(main_tl_smc_rsp),
+
+ // port: tl_rv_core_ibex_smc__corei
+ .tl_rv_core_ibex_smc__corei_i(smc_tl_rv_core_ibex_smc__corei_req),
+ .tl_rv_core_ibex_smc__corei_o(smc_tl_rv_core_ibex_smc__corei_rsp),
+
+ // port: tl_rv_core_ibex_smc__cored
+ .tl_rv_core_ibex_smc__cored_i(smc_tl_rv_core_ibex_smc__cored_req),
+ .tl_rv_core_ibex_smc__cored_o(smc_tl_rv_core_ibex_smc__cored_rsp),
+
+ // port: tl_dma_smc__reader
+ .tl_dma_smc__reader_i(smc_tl_dma_smc__reader_req),
+ .tl_dma_smc__reader_o(smc_tl_dma_smc__reader_rsp),
+
+ // port: tl_dma_smc__writer
+ .tl_dma_smc__writer_i(smc_tl_dma_smc__writer_req),
+ .tl_dma_smc__writer_o(smc_tl_dma_smc__writer_rsp),
+
+ // port: tl_rv_plic_smc
+ .tl_rv_plic_smc_o(rv_plic_smc_tl_req),
+ .tl_rv_plic_smc_i(rv_plic_smc_tl_rsp),
+
+ // port: tl_rv_core_ibex_smc__cfg
+ .tl_rv_core_ibex_smc__cfg_o(rv_core_ibex_smc_cfg_tl_d_req),
+ .tl_rv_core_ibex_smc__cfg_i(rv_core_ibex_smc_cfg_tl_d_rsp),
+
+ // port: tl_ram_smc
+ .tl_ram_smc_o(ram_smc_tl_req),
+ .tl_ram_smc_i(ram_smc_tl_rsp),
+
+ // port: tl_smc_uart
+ .tl_smc_uart_o(smc_uart_tl_req),
+ .tl_smc_uart_i(smc_uart_tl_rsp),
+
+ // port: tl_rv_timer_smc
+ .tl_rv_timer_smc_o(rv_timer_smc_tl_req),
+ .tl_rv_timer_smc_i(rv_timer_smc_tl_rsp),
+
+ // port: tl_tlul_mailbox_smc
+ .tl_tlul_mailbox_smc_o(tlul_mailbox_smc_tl_req),
+ .tl_tlul_mailbox_smc_i(tlul_mailbox_smc_tl_rsp),
+
+ // port: tl_smc_ctrl
+ .tl_smc_ctrl_o(smc_ctrl_tl_req),
+ .tl_smc_ctrl_i(smc_ctrl_tl_rsp),
+
+ // port: tl_cam_i2c
+ .tl_cam_i2c_o(cam_i2c_tl_req),
+ .tl_cam_i2c_i(cam_i2c_tl_rsp),
+
+ // port: tl_cam_ctrl
+ .tl_cam_ctrl_o(cam_ctrl_tl_req),
+ .tl_cam_ctrl_i(cam_ctrl_tl_rsp),
+
+ // port: tl_ml_top__dmem
+ .tl_ml_top__dmem_o(ml_top_dmem_tl_req),
+ .tl_ml_top__dmem_i(ml_top_dmem_tl_rsp),
+
+ // port: tl_ml_top__core
+ .tl_ml_top__core_o(ml_top_core_tl_req),
+ .tl_ml_top__core_i(ml_top_core_tl_rsp),
+
+ // port: tl_isp_wrapper
+ .tl_isp_wrapper_o(isp_wrapper_tl_req),
+ .tl_isp_wrapper_i(isp_wrapper_tl_rsp),
+
+ // port: tl_dma_smc
+ .tl_dma_smc_o(dma_smc_tl_d_req),
+ .tl_dma_smc_i(dma_smc_tl_d_rsp),
+
+ // port: tl_spi_host2
+ .tl_spi_host2_o(spi_host2_tl_req),
+ .tl_spi_host2_i(spi_host2_tl_rsp),
+
+ // port: tl_dbg
+ .tl_dbg_o(smc_tl_dbg_req),
+ .tl_dbg_i(smc_tl_dbg_rsp),
+
+ // port: tl_rv_timer_smc2
+ .tl_rv_timer_smc2_o(rv_timer_smc2_tl_req),
+ .tl_rv_timer_smc2_i(rv_timer_smc2_tl_rsp),
+
+ // port: tl_i2s0
+ .tl_i2s0_o(i2s0_tl_req),
+ .tl_i2s0_i(i2s0_tl_rsp),
+
+
+ .scanmode_i
+ );
+ xbar_dbg u_xbar_dbg (
+ .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+
+ // port: tl_main
+ .tl_main_i(main_tl_dbg_req),
+ .tl_main_o(main_tl_dbg_rsp),
+
+ // port: tl_smc
+ .tl_smc_i(smc_tl_dbg_req),
+ .tl_smc_o(smc_tl_dbg_rsp),
+
+ // port: tl_rv_dm__regs
+ .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req),
+ .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp),
+
+ // port: tl_rv_dm__mem
+ .tl_rv_dm__mem_o(rv_dm_mem_tl_d_req),
+ .tl_rv_dm__mem_i(rv_dm_mem_tl_d_rsp),
+
+
+ .scanmode_i
+ );
+
+ // Pinmux connections
+ // All muxed inputs
+ assign cio_gpio_gpio_p2d[0] = mio_p2d[MioInGpioGpio0];
+ assign cio_gpio_gpio_p2d[1] = mio_p2d[MioInGpioGpio1];
+ assign cio_gpio_gpio_p2d[2] = mio_p2d[MioInGpioGpio2];
+ assign cio_gpio_gpio_p2d[3] = mio_p2d[MioInGpioGpio3];
+ assign cio_gpio_gpio_p2d[4] = mio_p2d[MioInGpioGpio4];
+ assign cio_gpio_gpio_p2d[5] = mio_p2d[MioInGpioGpio5];
+ assign cio_gpio_gpio_p2d[6] = mio_p2d[MioInGpioGpio6];
+ assign cio_gpio_gpio_p2d[7] = mio_p2d[MioInGpioGpio7];
+ assign cio_gpio_gpio_p2d[8] = mio_p2d[MioInGpioGpio8];
+ assign cio_gpio_gpio_p2d[9] = mio_p2d[MioInGpioGpio9];
+ assign cio_gpio_gpio_p2d[10] = mio_p2d[MioInGpioGpio10];
+ assign cio_gpio_gpio_p2d[11] = mio_p2d[MioInGpioGpio11];
+ assign cio_gpio_gpio_p2d[12] = mio_p2d[MioInGpioGpio12];
+ assign cio_gpio_gpio_p2d[13] = mio_p2d[MioInGpioGpio13];
+ assign cio_gpio_gpio_p2d[14] = mio_p2d[MioInGpioGpio14];
+ assign cio_gpio_gpio_p2d[15] = mio_p2d[MioInGpioGpio15];
+ assign cio_gpio_gpio_p2d[16] = mio_p2d[MioInGpioGpio16];
+ assign cio_gpio_gpio_p2d[17] = mio_p2d[MioInGpioGpio17];
+ assign cio_gpio_gpio_p2d[18] = mio_p2d[MioInGpioGpio18];
+ assign cio_gpio_gpio_p2d[19] = mio_p2d[MioInGpioGpio19];
+ assign cio_gpio_gpio_p2d[20] = mio_p2d[MioInGpioGpio20];
+ assign cio_gpio_gpio_p2d[21] = mio_p2d[MioInGpioGpio21];
+ assign cio_gpio_gpio_p2d[22] = mio_p2d[MioInGpioGpio22];
+ assign cio_gpio_gpio_p2d[23] = mio_p2d[MioInGpioGpio23];
+ assign cio_gpio_gpio_p2d[24] = mio_p2d[MioInGpioGpio24];
+ assign cio_gpio_gpio_p2d[25] = mio_p2d[MioInGpioGpio25];
+ assign cio_gpio_gpio_p2d[26] = mio_p2d[MioInGpioGpio26];
+ assign cio_gpio_gpio_p2d[27] = mio_p2d[MioInGpioGpio27];
+ assign cio_gpio_gpio_p2d[28] = mio_p2d[MioInGpioGpio28];
+ assign cio_gpio_gpio_p2d[29] = mio_p2d[MioInGpioGpio29];
+ assign cio_gpio_gpio_p2d[30] = mio_p2d[MioInGpioGpio30];
+ assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31];
+ assign cio_i2c0_sda_p2d = mio_p2d[MioInI2c0Sda];
+ assign cio_i2c0_scl_p2d = mio_p2d[MioInI2c0Scl];
+ assign cio_i2c1_sda_p2d = mio_p2d[MioInI2c1Sda];
+ assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl];
+ assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda];
+ assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl];
+ assign cio_cam_i2c_sda_p2d = mio_p2d[MioInCamI2cSda];
+ assign cio_cam_i2c_scl_p2d = mio_p2d[MioInCamI2cScl];
+ assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0];
+ assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1];
+ assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2];
+ assign cio_spi_host1_sd_p2d[3] = mio_p2d[MioInSpiHost1Sd3];
+ assign cio_spi_host2_sd_p2d[0] = mio_p2d[MioInSpiHost2Sd0];
+ assign cio_spi_host2_sd_p2d[1] = mio_p2d[MioInSpiHost2Sd1];
+ assign cio_spi_host2_sd_p2d[2] = mio_p2d[MioInSpiHost2Sd2];
+ assign cio_spi_host2_sd_p2d[3] = mio_p2d[MioInSpiHost2Sd3];
+ assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx];
+ assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx];
+ assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx];
+ assign cio_smc_uart_rx_p2d = mio_p2d[MioInSmcUartRx];
+ assign cio_cam_ctrl_cam_int_p2d = mio_p2d[MioInCamCtrlCamInt];
+ assign cio_isp_wrapper_s_pclk_p2d = mio_p2d[MioInIspWrapperSPclk];
+ assign cio_isp_wrapper_s_data_p2d[0] = mio_p2d[MioInIspWrapperSData0];
+ assign cio_isp_wrapper_s_data_p2d[1] = mio_p2d[MioInIspWrapperSData1];
+ assign cio_isp_wrapper_s_data_p2d[2] = mio_p2d[MioInIspWrapperSData2];
+ assign cio_isp_wrapper_s_data_p2d[3] = mio_p2d[MioInIspWrapperSData3];
+ assign cio_isp_wrapper_s_data_p2d[4] = mio_p2d[MioInIspWrapperSData4];
+ assign cio_isp_wrapper_s_data_p2d[5] = mio_p2d[MioInIspWrapperSData5];
+ assign cio_isp_wrapper_s_data_p2d[6] = mio_p2d[MioInIspWrapperSData6];
+ assign cio_isp_wrapper_s_data_p2d[7] = mio_p2d[MioInIspWrapperSData7];
+ assign cio_isp_wrapper_s_hsync_p2d = mio_p2d[MioInIspWrapperSHsync];
+ assign cio_isp_wrapper_s_vsync_p2d = mio_p2d[MioInIspWrapperSVsync];
+ assign cio_i2s0_rx_sd_p2d = mio_p2d[MioInI2s0RxSd];
+ assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb];
+ assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck];
+ assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms];
+ assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi];
+ assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent];
+ assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In];
+ assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In];
+ assign cio_sysrst_ctrl_aon_key2_in_p2d = mio_p2d[MioInSysrstCtrlAonKey2In];
+ assign cio_sysrst_ctrl_aon_pwrb_in_p2d = mio_p2d[MioInSysrstCtrlAonPwrbIn];
+ assign cio_sysrst_ctrl_aon_lid_open_p2d = mio_p2d[MioInSysrstCtrlAonLidOpen];
+ assign cio_usbdev_sense_p2d = mio_p2d[MioInUsbdevSense];
+
+ // All muxed outputs
+ assign mio_d2p[MioOutGpioGpio0] = cio_gpio_gpio_d2p[0];
+ assign mio_d2p[MioOutGpioGpio1] = cio_gpio_gpio_d2p[1];
+ assign mio_d2p[MioOutGpioGpio2] = cio_gpio_gpio_d2p[2];
+ assign mio_d2p[MioOutGpioGpio3] = cio_gpio_gpio_d2p[3];
+ assign mio_d2p[MioOutGpioGpio4] = cio_gpio_gpio_d2p[4];
+ assign mio_d2p[MioOutGpioGpio5] = cio_gpio_gpio_d2p[5];
+ assign mio_d2p[MioOutGpioGpio6] = cio_gpio_gpio_d2p[6];
+ assign mio_d2p[MioOutGpioGpio7] = cio_gpio_gpio_d2p[7];
+ assign mio_d2p[MioOutGpioGpio8] = cio_gpio_gpio_d2p[8];
+ assign mio_d2p[MioOutGpioGpio9] = cio_gpio_gpio_d2p[9];
+ assign mio_d2p[MioOutGpioGpio10] = cio_gpio_gpio_d2p[10];
+ assign mio_d2p[MioOutGpioGpio11] = cio_gpio_gpio_d2p[11];
+ assign mio_d2p[MioOutGpioGpio12] = cio_gpio_gpio_d2p[12];
+ assign mio_d2p[MioOutGpioGpio13] = cio_gpio_gpio_d2p[13];
+ assign mio_d2p[MioOutGpioGpio14] = cio_gpio_gpio_d2p[14];
+ assign mio_d2p[MioOutGpioGpio15] = cio_gpio_gpio_d2p[15];
+ assign mio_d2p[MioOutGpioGpio16] = cio_gpio_gpio_d2p[16];
+ assign mio_d2p[MioOutGpioGpio17] = cio_gpio_gpio_d2p[17];
+ assign mio_d2p[MioOutGpioGpio18] = cio_gpio_gpio_d2p[18];
+ assign mio_d2p[MioOutGpioGpio19] = cio_gpio_gpio_d2p[19];
+ assign mio_d2p[MioOutGpioGpio20] = cio_gpio_gpio_d2p[20];
+ assign mio_d2p[MioOutGpioGpio21] = cio_gpio_gpio_d2p[21];
+ assign mio_d2p[MioOutGpioGpio22] = cio_gpio_gpio_d2p[22];
+ assign mio_d2p[MioOutGpioGpio23] = cio_gpio_gpio_d2p[23];
+ assign mio_d2p[MioOutGpioGpio24] = cio_gpio_gpio_d2p[24];
+ assign mio_d2p[MioOutGpioGpio25] = cio_gpio_gpio_d2p[25];
+ assign mio_d2p[MioOutGpioGpio26] = cio_gpio_gpio_d2p[26];
+ assign mio_d2p[MioOutGpioGpio27] = cio_gpio_gpio_d2p[27];
+ assign mio_d2p[MioOutGpioGpio28] = cio_gpio_gpio_d2p[28];
+ assign mio_d2p[MioOutGpioGpio29] = cio_gpio_gpio_d2p[29];
+ assign mio_d2p[MioOutGpioGpio30] = cio_gpio_gpio_d2p[30];
+ assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31];
+ assign mio_d2p[MioOutI2c0Sda] = cio_i2c0_sda_d2p;
+ assign mio_d2p[MioOutI2c0Scl] = cio_i2c0_scl_d2p;
+ assign mio_d2p[MioOutI2c1Sda] = cio_i2c1_sda_d2p;
+ assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p;
+ assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p;
+ assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p;
+ assign mio_d2p[MioOutCamI2cSda] = cio_cam_i2c_sda_d2p;
+ assign mio_d2p[MioOutCamI2cScl] = cio_cam_i2c_scl_d2p;
+ assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0];
+ assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1];
+ assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2];
+ assign mio_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_d2p[3];
+ assign mio_d2p[MioOutSpiHost2Sd0] = cio_spi_host2_sd_d2p[0];
+ assign mio_d2p[MioOutSpiHost2Sd1] = cio_spi_host2_sd_d2p[1];
+ assign mio_d2p[MioOutSpiHost2Sd2] = cio_spi_host2_sd_d2p[2];
+ assign mio_d2p[MioOutSpiHost2Sd3] = cio_spi_host2_sd_d2p[3];
+ assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p;
+ assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p;
+ assign mio_d2p[MioOutUart2Tx] = cio_uart2_tx_d2p;
+ assign mio_d2p[MioOutSmcUartTx] = cio_smc_uart_tx_d2p;
+ assign mio_d2p[MioOutCamCtrlCamTrig] = cio_cam_ctrl_cam_trig_d2p;
+ assign mio_d2p[MioOutI2s0RxSclk] = cio_i2s0_rx_sclk_d2p;
+ assign mio_d2p[MioOutI2s0RxWs] = cio_i2s0_rx_ws_d2p;
+ assign mio_d2p[MioOutI2s0TxSclk] = cio_i2s0_tx_sclk_d2p;
+ assign mio_d2p[MioOutI2s0TxWs] = cio_i2s0_tx_ws_d2p;
+ assign mio_d2p[MioOutI2s0TxSd] = cio_i2s0_tx_sd_d2p;
+ assign mio_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_d2p;
+ assign mio_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_d2p;
+ assign mio_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_d2p;
+ assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p;
+ assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p;
+ assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p;
+ assign mio_d2p[MioOutSpiHost2Sck] = cio_spi_host2_sck_d2p;
+ assign mio_d2p[MioOutSpiHost2Csb] = cio_spi_host2_csb_d2p;
+ assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p;
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_d2p[0];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_d2p[1];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut2] = cio_sensor_ctrl_ast_debug_out_d2p[2];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut3] = cio_sensor_ctrl_ast_debug_out_d2p[3];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut4] = cio_sensor_ctrl_ast_debug_out_d2p[4];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut5] = cio_sensor_ctrl_ast_debug_out_d2p[5];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut6] = cio_sensor_ctrl_ast_debug_out_d2p[6];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut7] = cio_sensor_ctrl_ast_debug_out_d2p[7];
+ assign mio_d2p[MioOutSensorCtrlAstDebugOut8] = cio_sensor_ctrl_ast_debug_out_d2p[8];
+ assign mio_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_d2p[0];
+ assign mio_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_d2p[1];
+ assign mio_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_d2p[2];
+ assign mio_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_d2p[3];
+ assign mio_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_d2p[4];
+ assign mio_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_d2p[5];
+ assign mio_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_d2p[0];
+ assign mio_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_d2p;
+ assign mio_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_d2p;
+ assign mio_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_d2p;
+ assign mio_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_d2p;
+ assign mio_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_d2p;
+ assign mio_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_d2p;
+
+ // All muxed output enables
+ assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0];
+ assign mio_en_d2p[MioOutGpioGpio1] = cio_gpio_gpio_en_d2p[1];
+ assign mio_en_d2p[MioOutGpioGpio2] = cio_gpio_gpio_en_d2p[2];
+ assign mio_en_d2p[MioOutGpioGpio3] = cio_gpio_gpio_en_d2p[3];
+ assign mio_en_d2p[MioOutGpioGpio4] = cio_gpio_gpio_en_d2p[4];
+ assign mio_en_d2p[MioOutGpioGpio5] = cio_gpio_gpio_en_d2p[5];
+ assign mio_en_d2p[MioOutGpioGpio6] = cio_gpio_gpio_en_d2p[6];
+ assign mio_en_d2p[MioOutGpioGpio7] = cio_gpio_gpio_en_d2p[7];
+ assign mio_en_d2p[MioOutGpioGpio8] = cio_gpio_gpio_en_d2p[8];
+ assign mio_en_d2p[MioOutGpioGpio9] = cio_gpio_gpio_en_d2p[9];
+ assign mio_en_d2p[MioOutGpioGpio10] = cio_gpio_gpio_en_d2p[10];
+ assign mio_en_d2p[MioOutGpioGpio11] = cio_gpio_gpio_en_d2p[11];
+ assign mio_en_d2p[MioOutGpioGpio12] = cio_gpio_gpio_en_d2p[12];
+ assign mio_en_d2p[MioOutGpioGpio13] = cio_gpio_gpio_en_d2p[13];
+ assign mio_en_d2p[MioOutGpioGpio14] = cio_gpio_gpio_en_d2p[14];
+ assign mio_en_d2p[MioOutGpioGpio15] = cio_gpio_gpio_en_d2p[15];
+ assign mio_en_d2p[MioOutGpioGpio16] = cio_gpio_gpio_en_d2p[16];
+ assign mio_en_d2p[MioOutGpioGpio17] = cio_gpio_gpio_en_d2p[17];
+ assign mio_en_d2p[MioOutGpioGpio18] = cio_gpio_gpio_en_d2p[18];
+ assign mio_en_d2p[MioOutGpioGpio19] = cio_gpio_gpio_en_d2p[19];
+ assign mio_en_d2p[MioOutGpioGpio20] = cio_gpio_gpio_en_d2p[20];
+ assign mio_en_d2p[MioOutGpioGpio21] = cio_gpio_gpio_en_d2p[21];
+ assign mio_en_d2p[MioOutGpioGpio22] = cio_gpio_gpio_en_d2p[22];
+ assign mio_en_d2p[MioOutGpioGpio23] = cio_gpio_gpio_en_d2p[23];
+ assign mio_en_d2p[MioOutGpioGpio24] = cio_gpio_gpio_en_d2p[24];
+ assign mio_en_d2p[MioOutGpioGpio25] = cio_gpio_gpio_en_d2p[25];
+ assign mio_en_d2p[MioOutGpioGpio26] = cio_gpio_gpio_en_d2p[26];
+ assign mio_en_d2p[MioOutGpioGpio27] = cio_gpio_gpio_en_d2p[27];
+ assign mio_en_d2p[MioOutGpioGpio28] = cio_gpio_gpio_en_d2p[28];
+ assign mio_en_d2p[MioOutGpioGpio29] = cio_gpio_gpio_en_d2p[29];
+ assign mio_en_d2p[MioOutGpioGpio30] = cio_gpio_gpio_en_d2p[30];
+ assign mio_en_d2p[MioOutGpioGpio31] = cio_gpio_gpio_en_d2p[31];
+ assign mio_en_d2p[MioOutI2c0Sda] = cio_i2c0_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c0Scl] = cio_i2c0_scl_en_d2p;
+ assign mio_en_d2p[MioOutI2c1Sda] = cio_i2c1_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c1Scl] = cio_i2c1_scl_en_d2p;
+ assign mio_en_d2p[MioOutI2c2Sda] = cio_i2c2_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c2Scl] = cio_i2c2_scl_en_d2p;
+ assign mio_en_d2p[MioOutCamI2cSda] = cio_cam_i2c_sda_en_d2p;
+ assign mio_en_d2p[MioOutCamI2cScl] = cio_cam_i2c_scl_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_en_d2p[0];
+ assign mio_en_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_en_d2p[1];
+ assign mio_en_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_en_d2p[2];
+ assign mio_en_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_en_d2p[3];
+ assign mio_en_d2p[MioOutSpiHost2Sd0] = cio_spi_host2_sd_en_d2p[0];
+ assign mio_en_d2p[MioOutSpiHost2Sd1] = cio_spi_host2_sd_en_d2p[1];
+ assign mio_en_d2p[MioOutSpiHost2Sd2] = cio_spi_host2_sd_en_d2p[2];
+ assign mio_en_d2p[MioOutSpiHost2Sd3] = cio_spi_host2_sd_en_d2p[3];
+ assign mio_en_d2p[MioOutUart0Tx] = cio_uart0_tx_en_d2p;
+ assign mio_en_d2p[MioOutUart1Tx] = cio_uart1_tx_en_d2p;
+ assign mio_en_d2p[MioOutUart2Tx] = cio_uart2_tx_en_d2p;
+ assign mio_en_d2p[MioOutSmcUartTx] = cio_smc_uart_tx_en_d2p;
+ assign mio_en_d2p[MioOutCamCtrlCamTrig] = cio_cam_ctrl_cam_trig_en_d2p;
+ assign mio_en_d2p[MioOutI2s0RxSclk] = cio_i2s0_rx_sclk_en_d2p;
+ assign mio_en_d2p[MioOutI2s0RxWs] = cio_i2s0_rx_ws_en_d2p;
+ assign mio_en_d2p[MioOutI2s0TxSclk] = cio_i2s0_tx_sclk_en_d2p;
+ assign mio_en_d2p[MioOutI2s0TxWs] = cio_i2s0_tx_ws_en_d2p;
+ assign mio_en_d2p[MioOutI2s0TxSd] = cio_i2s0_tx_sd_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost2Sck] = cio_spi_host2_sck_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost2Csb] = cio_spi_host2_csb_en_d2p;
+ assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p;
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut0] = cio_sensor_ctrl_ast_debug_out_en_d2p[0];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut1] = cio_sensor_ctrl_ast_debug_out_en_d2p[1];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut2] = cio_sensor_ctrl_ast_debug_out_en_d2p[2];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut3] = cio_sensor_ctrl_ast_debug_out_en_d2p[3];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut4] = cio_sensor_ctrl_ast_debug_out_en_d2p[4];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut5] = cio_sensor_ctrl_ast_debug_out_en_d2p[5];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut6] = cio_sensor_ctrl_ast_debug_out_en_d2p[6];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut7] = cio_sensor_ctrl_ast_debug_out_en_d2p[7];
+ assign mio_en_d2p[MioOutSensorCtrlAstDebugOut8] = cio_sensor_ctrl_ast_debug_out_en_d2p[8];
+ assign mio_en_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_en_d2p[0];
+ assign mio_en_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_en_d2p[1];
+ assign mio_en_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_en_d2p[2];
+ assign mio_en_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_en_d2p[3];
+ assign mio_en_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_en_d2p[4];
+ assign mio_en_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_en_d2p[5];
+ assign mio_en_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_en_d2p[0];
+ assign mio_en_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_en_d2p;
+ assign mio_en_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_en_d2p;
+ assign mio_en_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_en_d2p;
+ assign mio_en_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_en_d2p;
+ assign mio_en_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
+ assign mio_en_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_en_d2p;
+
+ // All dedicated inputs
+ logic [15:0] unused_dio_p2d;
+ assign unused_dio_p2d = dio_p2d;
+ assign cio_usbdev_usb_dp_p2d = dio_p2d[DioUsbdevUsbDp];
+ assign cio_usbdev_usb_dn_p2d = dio_p2d[DioUsbdevUsbDn];
+ assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0];
+ assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1];
+ assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2];
+ assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3];
+ assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0];
+ assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1];
+ assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2];
+ assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3];
+ assign cio_sysrst_ctrl_aon_ec_rst_l_p2d = dio_p2d[DioSysrstCtrlAonEcRstL];
+ assign cio_sysrst_ctrl_aon_flash_wp_l_p2d = dio_p2d[DioSysrstCtrlAonFlashWpL];
+ assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck];
+ assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb];
+
+ // All dedicated outputs
+ assign dio_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_d2p;
+ assign dio_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_d2p;
+ assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0];
+ assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1];
+ assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2];
+ assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3];
+ assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0];
+ assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1];
+ assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2];
+ assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3];
+ assign dio_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_d2p;
+ assign dio_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_d2p;
+ assign dio_d2p[DioSpiDeviceSck] = 1'b0;
+ assign dio_d2p[DioSpiDeviceCsb] = 1'b0;
+ assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p;
+ assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p;
+
+ // All dedicated output enables
+ assign dio_en_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_en_d2p;
+ assign dio_en_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_en_d2p;
+ assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0];
+ assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1];
+ assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2];
+ assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3];
+ assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0];
+ assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1];
+ assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2];
+ assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3];
+ assign dio_en_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_en_d2p;
+ assign dio_en_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_en_d2p;
+ assign dio_en_d2p[DioSpiDeviceSck] = 1'b0;
+ assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0;
+ assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p;
+ assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p;
+
+
+ // make sure scanmode_i is never X (including during reset)
+ `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0)
+
+endmodule
diff --git a/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
new file mode 100644
index 0000000..7726939
--- /dev/null
+++ b/hw/top_sencha/rtl/autogen/top_sencha_pkg.sv
@@ -0,0 +1,1251 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+package top_sencha_pkg;
+ /**
+ * Peripheral base address for uart0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART0_BASE_ADDR = 32'h40000000;
+
+ /**
+ * Peripheral size in bytes for uart0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART0_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for uart1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART1_BASE_ADDR = 32'h40010000;
+
+ /**
+ * Peripheral size in bytes for uart1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART1_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for uart2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART2_BASE_ADDR = 32'h40020000;
+
+ /**
+ * Peripheral size in bytes for uart2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART2_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for uart3 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART3_BASE_ADDR = 32'h40030000;
+
+ /**
+ * Peripheral size in bytes for uart3 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_UART3_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for gpio in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_GPIO_BASE_ADDR = 32'h40040000;
+
+ /**
+ * Peripheral size in bytes for gpio in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_GPIO_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for spi_device in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_DEVICE_BASE_ADDR = 32'h40050000;
+
+ /**
+ * Peripheral size in bytes for spi_device in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_DEVICE_SIZE_BYTES = 32'h2000;
+
+ /**
+ * Peripheral base address for i2c0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C0_BASE_ADDR = 32'h40080000;
+
+ /**
+ * Peripheral size in bytes for i2c0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C0_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for i2c1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C1_BASE_ADDR = 32'h40090000;
+
+ /**
+ * Peripheral size in bytes for i2c1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C1_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for i2c2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C2_BASE_ADDR = 32'h400A0000;
+
+ /**
+ * Peripheral size in bytes for i2c2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2C2_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for pattgen in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PATTGEN_BASE_ADDR = 32'h400E0000;
+
+ /**
+ * Peripheral size in bytes for pattgen in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PATTGEN_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for rv_timer in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_BASE_ADDR = 32'h40100000;
+
+ /**
+ * Peripheral size in bytes for rv_timer in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_SIZE_BYTES = 32'h200;
+
+ /**
+ * Peripheral base address for core device on otp_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR = 32'h40130000;
+
+ /**
+ * Peripheral size in bytes for core device on otp_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTP_CTRL_CORE_SIZE_BYTES = 32'h2000;
+
+ /**
+ * Peripheral base address for prim device on otp_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR = 32'h40132000;
+
+ /**
+ * Peripheral size in bytes for prim device on otp_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTP_CTRL_PRIM_SIZE_BYTES = 32'h20;
+
+ /**
+ * Peripheral base address for lc_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_LC_CTRL_BASE_ADDR = 32'h40140000;
+
+ /**
+ * Peripheral size in bytes for lc_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_LC_CTRL_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for alert_handler in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ALERT_HANDLER_BASE_ADDR = 32'h40150000;
+
+ /**
+ * Peripheral size in bytes for alert_handler in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ALERT_HANDLER_SIZE_BYTES = 32'h800;
+
+ /**
+ * Peripheral base address for spi_host0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST0_BASE_ADDR = 32'h40300000;
+
+ /**
+ * Peripheral size in bytes for spi_host0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST0_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for spi_host1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST1_BASE_ADDR = 32'h40310000;
+
+ /**
+ * Peripheral size in bytes for spi_host1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST1_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for usbdev in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_USBDEV_BASE_ADDR = 32'h40320000;
+
+ /**
+ * Peripheral size in bytes for usbdev in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_USBDEV_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for pwrmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PWRMGR_AON_BASE_ADDR = 32'h40400000;
+
+ /**
+ * Peripheral size in bytes for pwrmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PWRMGR_AON_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for rstmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RSTMGR_AON_BASE_ADDR = 32'h40410000;
+
+ /**
+ * Peripheral size in bytes for rstmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RSTMGR_AON_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for clkmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CLKMGR_AON_BASE_ADDR = 32'h40420000;
+
+ /**
+ * Peripheral size in bytes for clkmgr_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CLKMGR_AON_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for sysrst_ctrl_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR = 32'h40430000;
+
+ /**
+ * Peripheral size in bytes for sysrst_ctrl_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SYSRST_CTRL_AON_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for adc_ctrl_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR = 32'h40440000;
+
+ /**
+ * Peripheral size in bytes for adc_ctrl_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ADC_CTRL_AON_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for pwm_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PWM_AON_BASE_ADDR = 32'h40450000;
+
+ /**
+ * Peripheral size in bytes for pwm_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PWM_AON_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for pinmux_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PINMUX_AON_BASE_ADDR = 32'h40460000;
+
+ /**
+ * Peripheral size in bytes for pinmux_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_PINMUX_AON_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for aon_timer_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AON_TIMER_AON_BASE_ADDR = 32'h40470000;
+
+ /**
+ * Peripheral size in bytes for aon_timer_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AON_TIMER_AON_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for ast in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AST_BASE_ADDR = 32'h40480000;
+
+ /**
+ * Peripheral size in bytes for ast in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AST_SIZE_BYTES = 32'h400;
+
+ /**
+ * Peripheral base address for sensor_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SENSOR_CTRL_BASE_ADDR = 32'h40490000;
+
+ /**
+ * Peripheral size in bytes for sensor_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SENSOR_CTRL_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR = 32'h40500000;
+
+ /**
+ * Peripheral size in bytes for regs device on sram_ctrl_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES = 32'h20;
+
+ /**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR = 32'h40600000;
+
+ /**
+ * Peripheral size in bytes for ram device on sram_ctrl_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for core device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR = 32'h41000000;
+
+ /**
+ * Peripheral size in bytes for core device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_CORE_SIZE_BYTES = 32'h200;
+
+ /**
+ * Peripheral base address for prim device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR = 32'h41008000;
+
+ /**
+ * Peripheral size in bytes for prim device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for mem device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR = 32'h20000000;
+
+ /**
+ * Peripheral size in bytes for mem device on flash_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_FLASH_CTRL_MEM_SIZE_BYTES = 32'h100000;
+
+ /**
+ * Peripheral base address for regs device on rv_dm in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_DM_REGS_BASE_ADDR = 32'h6000;
+
+ /**
+ * Peripheral size in bytes for regs device on rv_dm in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_DM_REGS_SIZE_BYTES = 32'h4;
+
+ /**
+ * Peripheral base address for mem device on rv_dm in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_DM_MEM_BASE_ADDR = 32'h4000;
+
+ /**
+ * Peripheral size in bytes for mem device on rv_dm in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_DM_MEM_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for rv_plic in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_PLIC_BASE_ADDR = 32'h48000000;
+
+ /**
+ * Peripheral size in bytes for rv_plic in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_PLIC_SIZE_BYTES = 32'h8000000;
+
+ /**
+ * Peripheral base address for aes in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AES_BASE_ADDR = 32'h41100000;
+
+ /**
+ * Peripheral size in bytes for aes in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_AES_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for hmac in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_HMAC_BASE_ADDR = 32'h41110000;
+
+ /**
+ * Peripheral size in bytes for hmac in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_HMAC_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for kmac in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_KMAC_BASE_ADDR = 32'h41120000;
+
+ /**
+ * Peripheral size in bytes for kmac in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_KMAC_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Peripheral base address for otbn in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTBN_BASE_ADDR = 32'h41130000;
+
+ /**
+ * Peripheral size in bytes for otbn in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_OTBN_SIZE_BYTES = 32'h10000;
+
+ /**
+ * Peripheral base address for keymgr in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_KEYMGR_BASE_ADDR = 32'h41140000;
+
+ /**
+ * Peripheral size in bytes for keymgr in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_KEYMGR_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for csrng in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CSRNG_BASE_ADDR = 32'h41150000;
+
+ /**
+ * Peripheral size in bytes for csrng in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CSRNG_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for entropy_src in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ENTROPY_SRC_BASE_ADDR = 32'h41160000;
+
+ /**
+ * Peripheral size in bytes for entropy_src in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ENTROPY_SRC_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for edn0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EDN0_BASE_ADDR = 32'h41170000;
+
+ /**
+ * Peripheral size in bytes for edn0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EDN0_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for edn1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EDN1_BASE_ADDR = 32'h41180000;
+
+ /**
+ * Peripheral size in bytes for edn1 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EDN1_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for regs device on sram_ctrl_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR = 32'h411C0000;
+
+ /**
+ * Peripheral size in bytes for regs device on sram_ctrl_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES = 32'h20;
+
+ /**
+ * Peripheral base address for ram device on sram_ctrl_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR = 32'h10000000;
+
+ /**
+ * Peripheral size in bytes for ram device on sram_ctrl_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES = 32'h20000;
+
+ /**
+ * Peripheral base address for regs device on rom_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR = 32'h411E0000;
+
+ /**
+ * Peripheral size in bytes for regs device on rom_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_CTRL_REGS_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for rom device on rom_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR = 32'h8000;
+
+ /**
+ * Peripheral size in bytes for rom device on rom_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_CTRL_ROM_SIZE_BYTES = 32'h8000;
+
+ /**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR = 32'h411F0000;
+
+ /**
+ * Peripheral size in bytes for cfg device on rv_core_ibex_sec in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES = 32'h100;
+
+ /**
+ * Peripheral base address for dma0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_DMA0_BASE_ADDR = 32'h40200000;
+
+ /**
+ * Peripheral size in bytes for dma0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_DMA0_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for smc_uart in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SMC_UART_BASE_ADDR = 32'h54000000;
+
+ /**
+ * Peripheral size in bytes for smc_uart in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SMC_UART_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for rv_timer_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR = 32'h54010000;
+
+ /**
+ * Peripheral size in bytes for rv_timer_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_SMC_SIZE_BYTES = 32'h200;
+
+ /**
+ * Peripheral base address for smc_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SMC_CTRL_BASE_ADDR = 32'h54020000;
+
+ /**
+ * Peripheral size in bytes for smc_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SMC_CTRL_SIZE_BYTES = 32'h8;
+
+ /**
+ * Peripheral base address for cam_i2c in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CAM_I2C_BASE_ADDR = 32'h54040000;
+
+ /**
+ * Peripheral size in bytes for cam_i2c in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CAM_I2C_SIZE_BYTES = 32'h80;
+
+ /**
+ * Peripheral base address for cam_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CAM_CTRL_BASE_ADDR = 32'h54050000;
+
+ /**
+ * Peripheral size in bytes for cam_ctrl in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_CAM_CTRL_SIZE_BYTES = 32'h10;
+
+ /**
+ * Peripheral base address for isp_wrapper in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ISP_WRAPPER_BASE_ADDR = 32'h54060000;
+
+ /**
+ * Peripheral size in bytes for isp_wrapper in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ISP_WRAPPER_SIZE_BYTES = 32'h2000;
+
+ /**
+ * Peripheral base address for dma_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_DMA_SMC_BASE_ADDR = 32'h54070000;
+
+ /**
+ * Peripheral size in bytes for dma_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_DMA_SMC_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for rv_plic_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR = 32'h60000000;
+
+ /**
+ * Peripheral size in bytes for rv_plic_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_PLIC_SMC_SIZE_BYTES = 32'h8000000;
+
+ /**
+ * Peripheral base address for tlul_mailbox_sec in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR = 32'h40800000;
+
+ /**
+ * Peripheral size in bytes for tlul_mailbox_sec in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_TLUL_MAILBOX_SEC_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for tlul_mailbox_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR = 32'h540F1000;
+
+ /**
+ * Peripheral size in bytes for tlul_mailbox_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_TLUL_MAILBOX_SMC_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for core device on ml_top in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ML_TOP_CORE_BASE_ADDR = 32'h5C000000;
+
+ /**
+ * Peripheral size in bytes for core device on ml_top in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ML_TOP_CORE_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for dmem device on ml_top in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR = 32'h5A000000;
+
+ /**
+ * Peripheral size in bytes for dmem device on ml_top in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES = 32'h400000;
+
+ /**
+ * Peripheral base address for spi_host2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST2_BASE_ADDR = 32'h54090000;
+
+ /**
+ * Peripheral size in bytes for spi_host2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_SPI_HOST2_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for rv_timer_smc2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR = 32'h54011000;
+
+ /**
+ * Peripheral size in bytes for rv_timer_smc2 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_TIMER_SMC2_SIZE_BYTES = 32'h200;
+
+ /**
+ * Peripheral base address for i2s0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2S0_BASE_ADDR = 32'h54100000;
+
+ /**
+ * Peripheral size in bytes for i2s0 in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_I2S0_SIZE_BYTES = 32'h40;
+
+ /**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR = 32'h54030000;
+
+ /**
+ * Peripheral size in bytes for cfg device on rv_core_ibex_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES = 32'h100;
+
+ /**
+ * Memory base address for ram_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_SMC_BASE_ADDR = 32'h50000000;
+
+ /**
+ * Memory size for ram_smc in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_SMC_SIZE_BYTES = 32'h400000;
+
+ /**
+ * Memory base address for ram_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_RET_AON_BASE_ADDR = 32'h40600000;
+
+ /**
+ * Memory size for ram_ret_aon in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_RET_AON_SIZE_BYTES = 32'h1000;
+
+ /**
+ * Memory base address for eflash in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EFLASH_BASE_ADDR = 32'h20000000;
+
+ /**
+ * Memory size for eflash in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_EFLASH_SIZE_BYTES = 32'h100000;
+
+ /**
+ * Memory base address for ram_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_MAIN_BASE_ADDR = 32'h10000000;
+
+ /**
+ * Memory size for ram_main in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_MAIN_SIZE_BYTES = 32'h20000;
+
+ /**
+ * Memory base address for rom in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_BASE_ADDR = 32'h8000;
+
+ /**
+ * Memory size for rom in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_ROM_SIZE_BYTES = 32'h8000;
+
+ /**
+ * Memory base address for ram_ml_dmem in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_ML_DMEM_BASE_ADDR = 32'h5a000000;
+
+ /**
+ * Memory size for ram_ml_dmem in top sencha.
+ */
+ parameter int unsigned TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES = 32'h400000;
+
+
+ // Enumeration of alert modules
+ typedef enum int unsigned {
+ TopSenchaAlertPeripheralUart0 = 0,
+ TopSenchaAlertPeripheralUart1 = 1,
+ TopSenchaAlertPeripheralUart2 = 2,
+ TopSenchaAlertPeripheralUart3 = 3,
+ TopSenchaAlertPeripheralGpio = 4,
+ TopSenchaAlertPeripheralSpiDevice = 5,
+ TopSenchaAlertPeripheralI2c0 = 6,
+ TopSenchaAlertPeripheralI2c1 = 7,
+ TopSenchaAlertPeripheralI2c2 = 8,
+ TopSenchaAlertPeripheralPattgen = 9,
+ TopSenchaAlertPeripheralRvTimer = 10,
+ TopSenchaAlertPeripheralOtpCtrl = 11,
+ TopSenchaAlertPeripheralLcCtrl = 12,
+ TopSenchaAlertPeripheralSpiHost0 = 13,
+ TopSenchaAlertPeripheralSpiHost1 = 14,
+ TopSenchaAlertPeripheralUsbdev = 15,
+ TopSenchaAlertPeripheralPwrmgrAon = 16,
+ TopSenchaAlertPeripheralRstmgrAon = 17,
+ TopSenchaAlertPeripheralClkmgrAon = 18,
+ TopSenchaAlertPeripheralSysrstCtrlAon = 19,
+ TopSenchaAlertPeripheralAdcCtrlAon = 20,
+ TopSenchaAlertPeripheralPwmAon = 21,
+ TopSenchaAlertPeripheralPinmuxAon = 22,
+ TopSenchaAlertPeripheralAonTimerAon = 23,
+ TopSenchaAlertPeripheralSensorCtrl = 24,
+ TopSenchaAlertPeripheralSramCtrlRetAon = 25,
+ TopSenchaAlertPeripheralFlashCtrl = 26,
+ TopSenchaAlertPeripheralRvDm = 27,
+ TopSenchaAlertPeripheralRvPlic = 28,
+ TopSenchaAlertPeripheralAes = 29,
+ TopSenchaAlertPeripheralHmac = 30,
+ TopSenchaAlertPeripheralKmac = 31,
+ TopSenchaAlertPeripheralOtbn = 32,
+ TopSenchaAlertPeripheralKeymgr = 33,
+ TopSenchaAlertPeripheralCsrng = 34,
+ TopSenchaAlertPeripheralEntropySrc = 35,
+ TopSenchaAlertPeripheralEdn0 = 36,
+ TopSenchaAlertPeripheralEdn1 = 37,
+ TopSenchaAlertPeripheralSramCtrlMain = 38,
+ TopSenchaAlertPeripheralRomCtrl = 39,
+ TopSenchaAlertPeripheralRvCoreIbexSec = 40,
+ TopSenchaAlertPeripheralSmcUart = 41,
+ TopSenchaAlertPeripheralRvTimerSmc = 42,
+ TopSenchaAlertPeripheralCamI2c = 43,
+ TopSenchaAlertPeripheralRvPlicSmc = 44,
+ TopSenchaAlertPeripheralSpiHost2 = 45,
+ TopSenchaAlertPeripheralRvTimerSmc2 = 46,
+ TopSenchaAlertPeripheralRvCoreIbexSmc = 47,
+ TopEarlgreyAlertPeripheralCount
+ } alert_peripheral_e;
+
+ // Enumeration of alerts
+ typedef enum int unsigned {
+ TopSenchaAlertIdUart0FatalFault = 0,
+ TopSenchaAlertIdUart1FatalFault = 1,
+ TopSenchaAlertIdUart2FatalFault = 2,
+ TopSenchaAlertIdUart3FatalFault = 3,
+ TopSenchaAlertIdGpioFatalFault = 4,
+ TopSenchaAlertIdSpiDeviceFatalFault = 5,
+ TopSenchaAlertIdI2c0FatalFault = 6,
+ TopSenchaAlertIdI2c1FatalFault = 7,
+ TopSenchaAlertIdI2c2FatalFault = 8,
+ TopSenchaAlertIdPattgenFatalFault = 9,
+ TopSenchaAlertIdRvTimerFatalFault = 10,
+ TopSenchaAlertIdOtpCtrlFatalMacroError = 11,
+ TopSenchaAlertIdOtpCtrlFatalCheckError = 12,
+ TopSenchaAlertIdOtpCtrlFatalBusIntegError = 13,
+ TopSenchaAlertIdOtpCtrlFatalPrimOtpAlert = 14,
+ TopSenchaAlertIdOtpCtrlRecovPrimOtpAlert = 15,
+ TopSenchaAlertIdLcCtrlFatalProgError = 16,
+ TopSenchaAlertIdLcCtrlFatalStateError = 17,
+ TopSenchaAlertIdLcCtrlFatalBusIntegError = 18,
+ TopSenchaAlertIdSpiHost0FatalFault = 19,
+ TopSenchaAlertIdSpiHost1FatalFault = 20,
+ TopSenchaAlertIdUsbdevFatalFault = 21,
+ TopSenchaAlertIdPwrmgrAonFatalFault = 22,
+ TopSenchaAlertIdRstmgrAonFatalFault = 23,
+ TopSenchaAlertIdRstmgrAonFatalCnstyFault = 24,
+ TopSenchaAlertIdClkmgrAonRecovFault = 25,
+ TopSenchaAlertIdClkmgrAonFatalFault = 26,
+ TopSenchaAlertIdSysrstCtrlAonFatalFault = 27,
+ TopSenchaAlertIdAdcCtrlAonFatalFault = 28,
+ TopSenchaAlertIdPwmAonFatalFault = 29,
+ TopSenchaAlertIdPinmuxAonFatalFault = 30,
+ TopSenchaAlertIdAonTimerAonFatalFault = 31,
+ TopSenchaAlertIdSensorCtrlRecovAlert = 32,
+ TopSenchaAlertIdSensorCtrlFatalAlert = 33,
+ TopSenchaAlertIdSramCtrlRetAonFatalError = 34,
+ TopSenchaAlertIdFlashCtrlRecovErr = 35,
+ TopSenchaAlertIdFlashCtrlFatalStdErr = 36,
+ TopSenchaAlertIdFlashCtrlFatalErr = 37,
+ TopSenchaAlertIdFlashCtrlFatalPrimFlashAlert = 38,
+ TopSenchaAlertIdFlashCtrlRecovPrimFlashAlert = 39,
+ TopSenchaAlertIdRvDmFatalFault = 40,
+ TopSenchaAlertIdRvPlicFatalFault = 41,
+ TopSenchaAlertIdAesRecovCtrlUpdateErr = 42,
+ TopSenchaAlertIdAesFatalFault = 43,
+ TopSenchaAlertIdHmacFatalFault = 44,
+ TopSenchaAlertIdKmacRecovOperationErr = 45,
+ TopSenchaAlertIdKmacFatalFaultErr = 46,
+ TopSenchaAlertIdOtbnFatal = 47,
+ TopSenchaAlertIdOtbnRecov = 48,
+ TopSenchaAlertIdKeymgrRecovOperationErr = 49,
+ TopSenchaAlertIdKeymgrFatalFaultErr = 50,
+ TopSenchaAlertIdCsrngRecovAlert = 51,
+ TopSenchaAlertIdCsrngFatalAlert = 52,
+ TopSenchaAlertIdEntropySrcRecovAlert = 53,
+ TopSenchaAlertIdEntropySrcFatalAlert = 54,
+ TopSenchaAlertIdEdn0RecovAlert = 55,
+ TopSenchaAlertIdEdn0FatalAlert = 56,
+ TopSenchaAlertIdEdn1RecovAlert = 57,
+ TopSenchaAlertIdEdn1FatalAlert = 58,
+ TopSenchaAlertIdSramCtrlMainFatalError = 59,
+ TopSenchaAlertIdRomCtrlFatal = 60,
+ TopSenchaAlertIdRvCoreIbexSecFatalSwErr = 61,
+ TopSenchaAlertIdRvCoreIbexSecRecovSwErr = 62,
+ TopSenchaAlertIdRvCoreIbexSecFatalHwErr = 63,
+ TopSenchaAlertIdRvCoreIbexSecRecovHwErr = 64,
+ TopSenchaAlertIdSmcUartFatalFault = 65,
+ TopSenchaAlertIdRvTimerSmcFatalFault = 66,
+ TopSenchaAlertIdCamI2cFatalFault = 67,
+ TopSenchaAlertIdRvPlicSmcFatalFault = 68,
+ TopSenchaAlertIdSpiHost2FatalFault = 69,
+ TopSenchaAlertIdRvTimerSmc2FatalFault = 70,
+ TopSenchaAlertIdRvCoreIbexSmcFatalSwErr = 71,
+ TopSenchaAlertIdRvCoreIbexSmcRecovSwErr = 72,
+ TopSenchaAlertIdRvCoreIbexSmcFatalHwErr = 73,
+ TopSenchaAlertIdRvCoreIbexSmcRecovHwErr = 74,
+ TopEarlgreyAlertIdCount
+ } alert_id_e;
+
+ // Enumeration of IO power domains.
+ // Only used in ASIC target.
+ typedef enum logic [2:0] {
+ IoBankVcc = 0,
+ IoBankAvcc = 1,
+ IoBankVioa = 2,
+ IoBankViob = 3,
+ IoBankCount = 4
+ } pwr_dom_e;
+
+ // Enumeration for MIO signals on the top-level.
+ typedef enum int unsigned {
+ MioInGpioGpio0 = 0,
+ MioInGpioGpio1 = 1,
+ MioInGpioGpio2 = 2,
+ MioInGpioGpio3 = 3,
+ MioInGpioGpio4 = 4,
+ MioInGpioGpio5 = 5,
+ MioInGpioGpio6 = 6,
+ MioInGpioGpio7 = 7,
+ MioInGpioGpio8 = 8,
+ MioInGpioGpio9 = 9,
+ MioInGpioGpio10 = 10,
+ MioInGpioGpio11 = 11,
+ MioInGpioGpio12 = 12,
+ MioInGpioGpio13 = 13,
+ MioInGpioGpio14 = 14,
+ MioInGpioGpio15 = 15,
+ MioInGpioGpio16 = 16,
+ MioInGpioGpio17 = 17,
+ MioInGpioGpio18 = 18,
+ MioInGpioGpio19 = 19,
+ MioInGpioGpio20 = 20,
+ MioInGpioGpio21 = 21,
+ MioInGpioGpio22 = 22,
+ MioInGpioGpio23 = 23,
+ MioInGpioGpio24 = 24,
+ MioInGpioGpio25 = 25,
+ MioInGpioGpio26 = 26,
+ MioInGpioGpio27 = 27,
+ MioInGpioGpio28 = 28,
+ MioInGpioGpio29 = 29,
+ MioInGpioGpio30 = 30,
+ MioInGpioGpio31 = 31,
+ MioInI2c0Sda = 32,
+ MioInI2c0Scl = 33,
+ MioInI2c1Sda = 34,
+ MioInI2c1Scl = 35,
+ MioInI2c2Sda = 36,
+ MioInI2c2Scl = 37,
+ MioInCamI2cSda = 38,
+ MioInCamI2cScl = 39,
+ MioInSpiHost1Sd0 = 40,
+ MioInSpiHost1Sd1 = 41,
+ MioInSpiHost1Sd2 = 42,
+ MioInSpiHost1Sd3 = 43,
+ MioInSpiHost2Sd0 = 44,
+ MioInSpiHost2Sd1 = 45,
+ MioInSpiHost2Sd2 = 46,
+ MioInSpiHost2Sd3 = 47,
+ MioInUart0Rx = 48,
+ MioInUart1Rx = 49,
+ MioInUart2Rx = 50,
+ MioInSmcUartRx = 51,
+ MioInCamCtrlCamInt = 52,
+ MioInIspWrapperSPclk = 53,
+ MioInIspWrapperSData0 = 54,
+ MioInIspWrapperSData1 = 55,
+ MioInIspWrapperSData2 = 56,
+ MioInIspWrapperSData3 = 57,
+ MioInIspWrapperSData4 = 58,
+ MioInIspWrapperSData5 = 59,
+ MioInIspWrapperSData6 = 60,
+ MioInIspWrapperSData7 = 61,
+ MioInIspWrapperSHsync = 62,
+ MioInIspWrapperSVsync = 63,
+ MioInI2s0RxSd = 64,
+ MioInSpiDeviceTpmCsb = 65,
+ MioInFlashCtrlTck = 66,
+ MioInFlashCtrlTms = 67,
+ MioInFlashCtrlTdi = 68,
+ MioInSysrstCtrlAonAcPresent = 69,
+ MioInSysrstCtrlAonKey0In = 70,
+ MioInSysrstCtrlAonKey1In = 71,
+ MioInSysrstCtrlAonKey2In = 72,
+ MioInSysrstCtrlAonPwrbIn = 73,
+ MioInSysrstCtrlAonLidOpen = 74,
+ MioInUsbdevSense = 75,
+ MioInCount = 76
+ } mio_in_e;
+
+ typedef enum {
+ MioOutGpioGpio0 = 0,
+ MioOutGpioGpio1 = 1,
+ MioOutGpioGpio2 = 2,
+ MioOutGpioGpio3 = 3,
+ MioOutGpioGpio4 = 4,
+ MioOutGpioGpio5 = 5,
+ MioOutGpioGpio6 = 6,
+ MioOutGpioGpio7 = 7,
+ MioOutGpioGpio8 = 8,
+ MioOutGpioGpio9 = 9,
+ MioOutGpioGpio10 = 10,
+ MioOutGpioGpio11 = 11,
+ MioOutGpioGpio12 = 12,
+ MioOutGpioGpio13 = 13,
+ MioOutGpioGpio14 = 14,
+ MioOutGpioGpio15 = 15,
+ MioOutGpioGpio16 = 16,
+ MioOutGpioGpio17 = 17,
+ MioOutGpioGpio18 = 18,
+ MioOutGpioGpio19 = 19,
+ MioOutGpioGpio20 = 20,
+ MioOutGpioGpio21 = 21,
+ MioOutGpioGpio22 = 22,
+ MioOutGpioGpio23 = 23,
+ MioOutGpioGpio24 = 24,
+ MioOutGpioGpio25 = 25,
+ MioOutGpioGpio26 = 26,
+ MioOutGpioGpio27 = 27,
+ MioOutGpioGpio28 = 28,
+ MioOutGpioGpio29 = 29,
+ MioOutGpioGpio30 = 30,
+ MioOutGpioGpio31 = 31,
+ MioOutI2c0Sda = 32,
+ MioOutI2c0Scl = 33,
+ MioOutI2c1Sda = 34,
+ MioOutI2c1Scl = 35,
+ MioOutI2c2Sda = 36,
+ MioOutI2c2Scl = 37,
+ MioOutCamI2cSda = 38,
+ MioOutCamI2cScl = 39,
+ MioOutSpiHost1Sd0 = 40,
+ MioOutSpiHost1Sd1 = 41,
+ MioOutSpiHost1Sd2 = 42,
+ MioOutSpiHost1Sd3 = 43,
+ MioOutSpiHost2Sd0 = 44,
+ MioOutSpiHost2Sd1 = 45,
+ MioOutSpiHost2Sd2 = 46,
+ MioOutSpiHost2Sd3 = 47,
+ MioOutUart0Tx = 48,
+ MioOutUart1Tx = 49,
+ MioOutUart2Tx = 50,
+ MioOutSmcUartTx = 51,
+ MioOutCamCtrlCamTrig = 52,
+ MioOutI2s0RxSclk = 53,
+ MioOutI2s0RxWs = 54,
+ MioOutI2s0TxSclk = 55,
+ MioOutI2s0TxWs = 56,
+ MioOutI2s0TxSd = 57,
+ MioOutPattgenPda0Tx = 58,
+ MioOutPattgenPcl0Tx = 59,
+ MioOutPattgenPda1Tx = 60,
+ MioOutPattgenPcl1Tx = 61,
+ MioOutSpiHost1Sck = 62,
+ MioOutSpiHost1Csb = 63,
+ MioOutSpiHost2Sck = 64,
+ MioOutSpiHost2Csb = 65,
+ MioOutFlashCtrlTdo = 66,
+ MioOutSensorCtrlAstDebugOut0 = 67,
+ MioOutSensorCtrlAstDebugOut1 = 68,
+ MioOutSensorCtrlAstDebugOut2 = 69,
+ MioOutSensorCtrlAstDebugOut3 = 70,
+ MioOutSensorCtrlAstDebugOut4 = 71,
+ MioOutSensorCtrlAstDebugOut5 = 72,
+ MioOutSensorCtrlAstDebugOut6 = 73,
+ MioOutSensorCtrlAstDebugOut7 = 74,
+ MioOutSensorCtrlAstDebugOut8 = 75,
+ MioOutPwmAonPwm0 = 76,
+ MioOutPwmAonPwm1 = 77,
+ MioOutPwmAonPwm2 = 78,
+ MioOutPwmAonPwm3 = 79,
+ MioOutPwmAonPwm4 = 80,
+ MioOutPwmAonPwm5 = 81,
+ MioOutOtpCtrlTest0 = 82,
+ MioOutSysrstCtrlAonBatDisable = 83,
+ MioOutSysrstCtrlAonKey0Out = 84,
+ MioOutSysrstCtrlAonKey1Out = 85,
+ MioOutSysrstCtrlAonKey2Out = 86,
+ MioOutSysrstCtrlAonPwrbOut = 87,
+ MioOutSysrstCtrlAonZ3Wakeup = 88,
+ MioOutCount = 89
+ } mio_out_e;
+
+ // Enumeration for DIO signals, used on both the top and chip-levels.
+ typedef enum int unsigned {
+ DioUsbdevUsbDp = 0,
+ DioUsbdevUsbDn = 1,
+ DioSpiHost0Sd0 = 2,
+ DioSpiHost0Sd1 = 3,
+ DioSpiHost0Sd2 = 4,
+ DioSpiHost0Sd3 = 5,
+ DioSpiDeviceSd0 = 6,
+ DioSpiDeviceSd1 = 7,
+ DioSpiDeviceSd2 = 8,
+ DioSpiDeviceSd3 = 9,
+ DioSysrstCtrlAonEcRstL = 10,
+ DioSysrstCtrlAonFlashWpL = 11,
+ DioSpiDeviceSck = 12,
+ DioSpiDeviceCsb = 13,
+ DioSpiHost0Sck = 14,
+ DioSpiHost0Csb = 15,
+ DioCount = 16
+ } dio_e;
+
+ // Enumeration for the types of pads.
+ typedef enum {
+ MioPad,
+ DioPad
+ } pad_type_e;
+
+ // Raw MIO/DIO input array indices on chip-level.
+ // TODO: Does not account for target specific stubbed/added pads.
+ // Need to make a target-specific package for those.
+ typedef enum int unsigned {
+ MioPadIoa0 = 0,
+ MioPadIoa1 = 1,
+ MioPadIoa2 = 2,
+ MioPadIoa3 = 3,
+ MioPadIoa4 = 4,
+ MioPadIoa5 = 5,
+ MioPadIoa6 = 6,
+ MioPadIoa7 = 7,
+ MioPadIoa8 = 8,
+ MioPadIob0 = 9,
+ MioPadIob1 = 10,
+ MioPadIob2 = 11,
+ MioPadIob3 = 12,
+ MioPadIob4 = 13,
+ MioPadIob5 = 14,
+ MioPadIob6 = 15,
+ MioPadIob7 = 16,
+ MioPadIob8 = 17,
+ MioPadIob9 = 18,
+ MioPadIob10 = 19,
+ MioPadIob11 = 20,
+ MioPadIob12 = 21,
+ MioPadIoc0 = 22,
+ MioPadIoc1 = 23,
+ MioPadIoc2 = 24,
+ MioPadIoc3 = 25,
+ MioPadIoc4 = 26,
+ MioPadIoc5 = 27,
+ MioPadIoc6 = 28,
+ MioPadIoc7 = 29,
+ MioPadIoc8 = 30,
+ MioPadIoc9 = 31,
+ MioPadIoc10 = 32,
+ MioPadIoc11 = 33,
+ MioPadIoc12 = 34,
+ MioPadIor0 = 35,
+ MioPadIor1 = 36,
+ MioPadIor2 = 37,
+ MioPadIor3 = 38,
+ MioPadIor4 = 39,
+ MioPadIor5 = 40,
+ MioPadIor6 = 41,
+ MioPadIor7 = 42,
+ MioPadIor10 = 43,
+ MioPadIor11 = 44,
+ MioPadIor12 = 45,
+ MioPadIor13 = 46,
+ MioPadIod0 = 47,
+ MioPadIod1 = 48,
+ MioPadIod2 = 49,
+ MioPadIod3 = 50,
+ MioPadIod4 = 51,
+ MioPadIod5 = 52,
+ MioPadCount
+ } mio_pad_e;
+
+ typedef enum int unsigned {
+ DioPadPorN = 0,
+ DioPadUsbP = 1,
+ DioPadUsbN = 2,
+ DioPadCc1 = 3,
+ DioPadCc2 = 4,
+ DioPadFlashTestVolt = 5,
+ DioPadFlashTestMode0 = 6,
+ DioPadFlashTestMode1 = 7,
+ DioPadOtpExtVolt = 8,
+ DioPadSpiHostD0 = 9,
+ DioPadSpiHostD1 = 10,
+ DioPadSpiHostD2 = 11,
+ DioPadSpiHostD3 = 12,
+ DioPadSpiHostClk = 13,
+ DioPadSpiHostCsL = 14,
+ DioPadSpiDevD0 = 15,
+ DioPadSpiDevD1 = 16,
+ DioPadSpiDevD2 = 17,
+ DioPadSpiDevD3 = 18,
+ DioPadSpiDevClk = 19,
+ DioPadSpiDevCsL = 20,
+ DioPadIor8 = 21,
+ DioPadIor9 = 22,
+ DioPadCount
+ } dio_pad_e;
+
+ // List of peripheral instantiated in this chip.
+ typedef enum {
+ PeripheralAdcCtrlAon,
+ PeripheralAes,
+ PeripheralAlertHandler,
+ PeripheralAonTimerAon,
+ PeripheralAst,
+ PeripheralCamCtrl,
+ PeripheralCamI2c,
+ PeripheralClkmgrAon,
+ PeripheralCsrng,
+ PeripheralDma0,
+ PeripheralDmaSmc,
+ PeripheralEdn0,
+ PeripheralEdn1,
+ PeripheralEntropySrc,
+ PeripheralFlashCtrl,
+ PeripheralGpio,
+ PeripheralHmac,
+ PeripheralI2c0,
+ PeripheralI2c1,
+ PeripheralI2c2,
+ PeripheralI2s0,
+ PeripheralIspWrapper,
+ PeripheralKeymgr,
+ PeripheralKmac,
+ PeripheralLcCtrl,
+ PeripheralMlTop,
+ PeripheralOtbn,
+ PeripheralOtpCtrl,
+ PeripheralPattgen,
+ PeripheralPinmuxAon,
+ PeripheralPwmAon,
+ PeripheralPwrmgrAon,
+ PeripheralRomCtrl,
+ PeripheralRstmgrAon,
+ PeripheralRvCoreIbexSec,
+ PeripheralRvCoreIbexSmc,
+ PeripheralRvDm,
+ PeripheralRvPlic,
+ PeripheralRvPlicSmc,
+ PeripheralRvTimer,
+ PeripheralRvTimerSmc,
+ PeripheralRvTimerSmc2,
+ PeripheralSensorCtrl,
+ PeripheralSmcCtrl,
+ PeripheralSmcUart,
+ PeripheralSpiDevice,
+ PeripheralSpiHost0,
+ PeripheralSpiHost1,
+ PeripheralSpiHost2,
+ PeripheralSramCtrlMain,
+ PeripheralSramCtrlRetAon,
+ PeripheralSysrstCtrlAon,
+ PeripheralTlulMailboxSec,
+ PeripheralTlulMailboxSmc,
+ PeripheralUart0,
+ PeripheralUart1,
+ PeripheralUart2,
+ PeripheralUart3,
+ PeripheralUsbdev,
+ PeripheralCount
+ } peripheral_e;
+
+ // TODO: Enumeration for PLIC Interrupt source peripheral.
+ // TODO: Enumeration for PLIC Interrupt Ids.
+
+// MACROs for AST analog simulation support
+`ifdef ANALOGSIM
+ `define INOUT_AI input ast_pkg::awire_t
+ `define INOUT_AO output ast_pkg::awire_t
+`else
+ `define INOUT_AI inout
+ `define INOUT_AO inout
+`endif
+
+endpackage
diff --git a/hw/top_sencha/rtl/autogen/top_sencha_rnd_cnst_pkg.sv b/hw/top_sencha/rtl/autogen/top_sencha_rnd_cnst_pkg.sv
new file mode 100644
index 0000000..7510801
--- /dev/null
+++ b/hw/top_sencha/rtl/autogen/top_sencha_rnd_cnst_pkg.sv
@@ -0,0 +1,405 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson \
+// -o hw/top_sencha/ \
+// --rnd_cnst_seed 4881560218908238235
+
+
+package top_sencha_rnd_cnst_pkg;
+
+ ////////////////////////////////////////////
+ // otp_ctrl
+ ////////////////////////////////////////////
+ // Compile-time random bits for initial LFSR seed
+ parameter otp_ctrl_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = {
+ 40'hC2_1D577A17
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter otp_ctrl_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = {
+ 240'h1A15_4F304292_6667A741_724D8089_1C88059D_94E44216_34C761B5_1A0DF04B
+ };
+
+ // Compile-time random permutation for scrambling key/nonce register reset value
+ parameter otp_ctrl_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = {
+ 256'hEBA81E1C_4EC8EBDE_EE291106_2E039F8C_7E1AFA78_A1D42886_CC89AE75_9CF865B2
+ };
+
+ ////////////////////////////////////////////
+ // lc_ctrl
+ ////////////////////////////////////////////
+ // Compile-time random bits for lc state group diversification value
+ parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = {
+ 128'h2A5F28DE_2ECA36AF_C2E8A402_302CBDCF
+ };
+
+ // Compile-time random bits for lc state group diversification value
+ parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestDevRma = {
+ 128'h2B4819AF_AA0A11CB_68371EEF_174D9831
+ };
+
+ // Compile-time random bits for lc state group diversification value
+ parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = {
+ 128'h5696C49A_8EF53C96_F11E4F43_FFD421E4
+ };
+
+ // Compile-time random bits used for invalid tokens in the token mux
+ parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = {
+ 256'h56B4D6A9_D1D2AB4A_836F1545_EBF50FF8_7BC3FE84_73A3B8A6_98EB44C3_B5821FC5,
+ 256'hBAE3E1BD_59723B69_B2D7B533_0424C308_45EB1F7A_5EEF762A_1F9129C2_B7FCBAE1,
+ 256'hB8009909_ADEC2586_C494F5DA_C82C170B_9DE79AF5_B2710CE4_BFCAC18E_D45328D7,
+ 256'hD63CA958_AC39F21A_BC3925A2_B2B291A9_84707162_74C976B8_106DD974_CC66D7F9
+ };
+
+ ////////////////////////////////////////////
+ // alert_handler
+ ////////////////////////////////////////////
+ // Compile-time random bits for initial LFSR seed
+ parameter alert_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = {
+ 32'hC8518EEF
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter alert_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = {
+ 160'h27C474BA_71E9735D_07CC1839_4799B2DA_20ABE176
+ };
+
+ ////////////////////////////////////////////
+ // sram_ctrl_ret_aon
+ ////////////////////////////////////////////
+ // Compile-time random reset value for SRAM scrambling key.
+ parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = {
+ 128'h63285ACA_0C8D4B9E_2FC1918D_324C4CFB
+ };
+
+ // Compile-time random reset value for SRAM scrambling nonce.
+ parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = {
+ 128'h1A95698E_A1EB7868_F8497078_38F547A2
+ };
+
+ // Compile-time random bits for initial LFSR seed
+ parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = {
+ 32'hC2A64A91
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = {
+ 160'hFF1ED11B_1B3F6175_7A892856_490F3663_A3340355
+ };
+
+ ////////////////////////////////////////////
+ // flash_ctrl
+ ////////////////////////////////////////////
+ // Compile-time random bits for default address key
+ parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlAddrKey = {
+ 128'h51FD2ACF_21290117_4C9576A1_12CEA79B
+ };
+
+ // Compile-time random bits for default data key
+ parameter flash_ctrl_pkg::flash_key_t RndCnstFlashCtrlDataKey = {
+ 128'h52282399_833DA888_C02546E7_2EB6F09A
+ };
+
+ // Compile-time random bits for default seeds
+ parameter flash_ctrl_pkg::all_seeds_t RndCnstFlashCtrlAllSeeds = {
+ 256'h26A1661A_0D5DB701_DDF4ED7C_6F488781_71C320FD_F1FDEF79_13525470_E04A549E,
+ 256'hBDD80D4F_7B729F25_A1926E51_73690709_F09E8597_D26DFC56_265ED80D_03E335CB
+ };
+
+ // Compile-time random bits for initial LFSR seed
+ parameter flash_ctrl_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = {
+ 32'h77683AF6
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter flash_ctrl_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = {
+ 160'h905EB602_E4D987FD_179EAD33_8B20516C_DDD824EA
+ };
+
+ ////////////////////////////////////////////
+ // aes
+ ////////////////////////////////////////////
+ // Default seed of the PRNG used for register clearing.
+ parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = {
+ 64'h5353AB78_F79F8769
+ };
+
+ // Permutation applied to the LFSR of the PRNG used for clearing.
+ parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = {
+ 128'h6BF8FDEE_FD6D6568_141875EB_08ED1026,
+ 256'h6CCC9366_3979597C_45BA0849_D36A9E23_C5C400EE_C93DE92C_4B3071FE_8A061E3E
+ };
+
+ // Permutation applied to the clearing PRNG output for clearing the second share of registers.
+ parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = {
+ 128'h51625930_4F83AD02_9361772E_D0FEF98A,
+ 256'h07F66FF2_E98C1B2D_CC5025F3_255284DB_C2448AB1_D7A19AF5_D3A7C247_87DE6A38
+ };
+
+ // Default seed of the PRNG used for masking.
+ parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = {
+ 160'h7FBFA00E_47BF71DC_7947873B_F1A7B4CB_AD77105A
+ };
+
+ // Permutation applied to the concatenated LFSRs of the PRNG used for masking.
+ parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = {
+ 256'h1A06086A_775B2B11_374D5A9E_2A1F9B6F_6D4C7E4B_9F316085_2F654A99_4F494272,
+ 256'h43919555_23105D15_962E2C7D_218F4416_0330530D_529D8E09_26862018_98025013,
+ 256'h83454080_6C04129A_7A54071D_79943B6E_6235610A_75700C2D_327B9C5C_92177487,
+ 256'h0E331C88_6B760001_41059338_571B2814_5F71847F_89474856_27193F3E_6682293A,
+ 256'h34978C51_678D2439_6473581E_590B633D_814E3C8A_36788B7C_460F6968_9022255E
+ };
+
+ ////////////////////////////////////////////
+ // kmac
+ ////////////////////////////////////////////
+ // Compile-time random data for LFSR default seed
+ parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = {
+ 32'h2E3FB236,
+ 256'h8EBDE95C_97FA3B0E_8F6629A1_6E94D4E4_3991FBDC_31303EE6_BD9C4285_BE6303D3,
+ 256'hE48A9FAE_8AB504B3_C162C97E_295803BE_F65B6566_6292F222_316E41C5_5EA3B7A5,
+ 256'hDED4BE1F_548D0A22_72AD3124_BE0E850C_631EBF06_28DBA982_A4523510_FA7D3B97
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = {
+ 64'h3C436606_C45E0123,
+ 256'hCCC44064_27E45E27_8D34F6B3_3289C9FF_176DD0CA_8A849311_F6C1B508_2981DD83,
+ 256'hB32038EC_1824AE07_4A404AD5_EC10BAA5_2A1C797F_87656790_61AC96DC_394B962C,
+ 256'h9A8EAB19_31106EB1_652049DA_D3A5CEC0_6A456B88_5978CF7A_44CAB848_39D5C4F0,
+ 256'hC3636A85_CAF46BC9_F4746028_D0A1FC8A_4B685154_E865D4D4_781143E4_71A9892B,
+ 256'h06B484E2_9C230A42_446C93E5_59F32EE5_B43AC2A9_C69776E3_10B05BCA_D6315488,
+ 256'h80D748D3_4865C397_22932431_97CB2450_CE4DC3C2_6C220765_4C7D326B_52A41ACA,
+ 256'hAF6F624E_6A725937_1D76BE21_80707498_2E8B1601_C48BE79D_C5666D49_BE392BA2,
+ 256'h177D82B4_B0895DDE_92D110F8_D212ADC0_2AFF2648_193F0C35_81E08C15_C54F84D6,
+ 256'hD9620960_C8839A21_131A6DA3_8F461C26_4944787E_C87D0A66_45431149_4482469E,
+ 256'h082B6A75_718E19D2_BB0E55A1_C0DC7A28_08D30B7D_E7D0EDFD_7FB00828_05059E07,
+ 256'h3592B7EE_DB79744E_6129DC6F_126EA091_8A2C58F2_8A627C1D_85CEE472_1D91E6DD,
+ 256'h592D129D_E24B2730_BDA86C6B_C54871BF_8975022D_1EDEDAD5_57BC1598_2E89A55A,
+ 256'h91B4A014_43357692_8AE55974_8CC50A4C_4E7C37C1_37543569_D171B938_2DD183EA,
+ 256'h3C02568A_9AB83DE0_F0E9449C_69C7FD95_8EA33892_A0B356C9_EF1C3F5C_03556F58,
+ 256'h6649EA4E_B2DE559A_E26EE4DC_0C4E8594_9AB0A889_971BE889_0208EC5B_199CAFC4,
+ 256'h0B07641B_64114587_8DD7BDBD_0F4805E4_68A18840_31DA07CB_F330EA39_636744BD,
+ 256'hBF4F0928_14B861B6_FC527C4A_11F68884_23732E14_85DCB00E_8F62CF97_E9EC7F10,
+ 256'hD100CDAD_EBABB263_670B3556_38006EB1_72BFA0A8_D0B6F73A_EB93048D_BCCF2454,
+ 256'hC7274388_F6233648_667EB0A6_A6682696_8C6BE2B5_4F6E5F81_431BA653_0809A69A,
+ 256'h6875E9FB_46A6EB40_070B2223_9A088564_15AB10B0_1D673243_15D800D1_BA0AAE78,
+ 256'hD6651E9A_0C0AC196_910B1A93_6E053B54_4654D845_D43F13D0_B322A41C_CDB94986,
+ 256'h44A512A8_76B0ECF6_15278685_A3D9E17D_AAD19522_45969112_3F7A9367_9A00065D,
+ 256'hCA2903C7_4EF8B8C2_9ADBE873_01531EB7_42B44BF0_62553A76_DB365B0F_C2AE6C60,
+ 256'h78035655_285D58C0_417D7B4E_DF53EC21_425A17C9_243BA9E3_42AFBE52_E5180F56,
+ 256'hEF5630D4_B1D98A47_0D57C4D3_469D2E54_E66D1BB6_C754FC90_9B08B094_17C68665,
+ 256'h51504203_018DA294_06C02E59_19E0EBB8_5B41DD78_9D9E3A57_C8C80E10_E9F21D29,
+ 256'h294E0244_E48A91C0_DE816AEB_6A6E61B3_A7E1668B_15A076D2_0D5F9CE2_C0BC74C4,
+ 256'h12BC4B56_105691C4_BC4E33F9_C15C2EF8_323E5B8B_50412626_82E8A2A9_6957D1F0,
+ 256'h291F8886_B0AB8951_358A0523_EE978C28_5AD6700A_06504B87_B9771C95_1464FFA9,
+ 256'h59DB9542_369473B4_D8638274_A22F162F_B6A8C0AA_8B48B249_921CA188_DEC25607,
+ 256'h3DBC94D0_0B61C266_8B63F0A9_9E454000_2B750F58_4E8368E6_7B5C064C_C98A3131
+ };
+
+ // Compile-time random permutation for forwarding LFSR state
+ parameter kmac_pkg::lfsr_fwd_perm_t RndCnstKmacLfsrFwdPerm = {
+ 160'hB2F48B90_7BAF5899_E1CDF3FF_0904B957_007150D1
+ };
+
+ // Compile-time random permutation for LFSR Message output
+ parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = {
+ 128'h9E6F6DAE_8AB2B076_765490D3_50F10B20,
+ 256'h688DF0AE_DE4008DB_45660168_27E19643_29DEFE75_C45773FF_AB8E5F07_12E3ED20
+ };
+
+ ////////////////////////////////////////////
+ // otbn
+ ////////////////////////////////////////////
+ // Default seed of the PRNG used for URND.
+ parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = {
+ 256'h2EBA3F71_E4EBAC6F_4F9643C6_2E4091E1_1907A673_4572487F_85F60D1F_1F254A38
+ };
+
+ // Compile-time random reset value for IMem/DMem scrambling key.
+ parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = {
+ 128'h01CC3DB4_DB727F0D_96DE4A0E_05A5DC7F
+ };
+
+ // Compile-time random reset value for IMem/DMem scrambling nonce.
+ parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = {
+ 64'hF64F231D_7DB9C9BD
+ };
+
+ ////////////////////////////////////////////
+ // keymgr
+ ////////////////////////////////////////////
+ // Compile-time random bits for initial LFSR seed
+ parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrLfsrSeed = {
+ 64'h90CF465B_59731B72
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrLfsrPerm = {
+ 128'h02E84BD5_BFF8B63E_9C33CBE0_39FAD42A,
+ 256'h4F6236A1_15B1D25E_0772325E_94A63F66_B1C195A5_1F9CC3EC_59FED021_93411A18
+ };
+
+ // Compile-time random permutation for entropy used in share overriding
+ parameter keymgr_pkg::rand_perm_t RndCnstKeymgrRandPerm = {
+ 160'h26CA8669_F97286B1_78F86CA6_985B81FD_3A6AC417
+ };
+
+ // Compile-time random bits for revision seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrRevisionSeed = {
+ 256'h8F73D707_CD0EC1D3_3DAAEF20_E285FA65_8FDD1B42_6C037151_B16C8D44_4C444F39
+ };
+
+ // Compile-time random bits for creator identity seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrCreatorIdentitySeed = {
+ 256'h6F4479CB_795CF94B_9E409D18_381BD5D5_6821E298_5E479971_05C4900F_25557467
+ };
+
+ // Compile-time random bits for owner intermediate identity seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIntIdentitySeed = {
+ 256'h5985B210_E1A968E4_5E5B35E4_60FDAF1F_F382AB01_95E33689_D99BCEBF_2B79B683
+ };
+
+ // Compile-time random bits for owner identity seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrOwnerIdentitySeed = {
+ 256'h9264EDF4_DE2B39F3_94059891_A38BD1D1_6C763BBD_90347E58_152D7FCA_99380365
+ };
+
+ // Compile-time random bits for software generation seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrSoftOutputSeed = {
+ 256'h25AAA3F8_9E3DE8F1_278645E1_1D7CAC76_310205E1_9CD3F2ED_294A279F_3C6D0649
+ };
+
+ // Compile-time random bits for hardware generation seed
+ parameter keymgr_pkg::seed_t RndCnstKeymgrHardOutputSeed = {
+ 256'hA905CC9B_10A67A16_161FED72_416DFD29_3DE3A18A_8837B0DD_4CB694DD_540451D7
+ };
+
+ // Compile-time random bits for generation seed when aes destination selected
+ parameter keymgr_pkg::seed_t RndCnstKeymgrAesSeed = {
+ 256'h69D28E1D_9E76007B_7A9E0F6E_3D591A7F_D8C7BA26_4AF78F28_AEE0D28E_4D638D95
+ };
+
+ // Compile-time random bits for generation seed when kmac destination selected
+ parameter keymgr_pkg::seed_t RndCnstKeymgrKmacSeed = {
+ 256'hD1806E87_0336CD96_1D2049F3_32011CAB_7D512B69_B6B766DC_84760801_C9AAE19E
+ };
+
+ // Compile-time random bits for generation seed when otbn destination selected
+ parameter keymgr_pkg::seed_t RndCnstKeymgrOtbnSeed = {
+ 256'h8A6DD42F_94A9A15F_A77F118B_21BA52C5_D59D755F_58D2D862_44D2DC25_8CA12CC7
+ };
+
+ // Compile-time random bits for generation seed when no CDI is selected
+ parameter keymgr_pkg::seed_t RndCnstKeymgrCdi = {
+ 256'h0B776B16_DD95013B_9569BD77_059093ED_3CE77AEA_86FFD82C_B1CDEE3F_CD6039C7
+ };
+
+ // Compile-time random bits for generation seed when no destination selected
+ parameter keymgr_pkg::seed_t RndCnstKeymgrNoneSeed = {
+ 256'hC0402496_5B7C1E1C_07548A9B_F5956E74_82848DE7_D401512A_2573043A_8E0AD9B1
+ };
+
+ ////////////////////////////////////////////
+ // csrng
+ ////////////////////////////////////////////
+ // Compile-time random bits for csrng state group diversification value
+ parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = {
+ 128'h56D761AD_532F38F0_767AFF4B_BB54571D,
+ 256'h7BA3EBC3_93927B56_CC945C44_B5348892_0A7555F7_7BFC936F_EA411188_8D196ACF
+ };
+
+ // Compile-time random bits for csrng state group diversification value
+ parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = {
+ 128'h43EEF65B_7D755CF0_0BD7432C_3F8CD4E7,
+ 256'hEFF1B9EC_59CE8124_47C57145_95F17463_DB6FD530_F6331E81_C7753E50_D3CF1164
+ };
+
+ ////////////////////////////////////////////
+ // sram_ctrl_main
+ ////////////////////////////////////////////
+ // Compile-time random reset value for SRAM scrambling key.
+ parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = {
+ 128'h99003D01_80063719_91F8FDF8_344ADD67
+ };
+
+ // Compile-time random reset value for SRAM scrambling nonce.
+ parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = {
+ 128'h7AFE9E6A_7BBA1DDD_C10D8DD7_F82D1584
+ };
+
+ // Compile-time random bits for initial LFSR seed
+ parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = {
+ 32'h4E53A6AF
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = {
+ 160'h8BDD7B67_D592A834_9A6C0745_A6879BC7_D0559E04
+ };
+
+ ////////////////////////////////////////////
+ // rom_ctrl
+ ////////////////////////////////////////////
+ // Fixed nonce used for address / data scrambling
+ parameter bit [63:0] RndCnstRomCtrlScrNonce = {
+ 64'hD7C90B2B_3C3EF8B3
+ };
+
+ // Randomised constant used as a scrambling key for ROM data
+ parameter bit [127:0] RndCnstRomCtrlScrKey = {
+ 128'h80C4E835_FB113AAD_6D7DCA2F_2C7D9BF2
+ };
+
+ ////////////////////////////////////////////
+ // rv_core_ibex_sec
+ ////////////////////////////////////////////
+ // Default seed of the PRNG used for random instructions.
+ parameter ibex_pkg::lfsr_seed_t RndCnstRvCoreIbexSecLfsrSeed = {
+ 32'h459D71E7
+ };
+
+ // Permutation applied to the LFSR of the PRNG used for random instructions.
+ parameter ibex_pkg::lfsr_perm_t RndCnstRvCoreIbexSecLfsrPerm = {
+ 160'h81AAEBFD_8DD1F80F_0BA32151_95E1FB52_693B0632
+ };
+
+ // Default icache scrambling key
+ parameter logic [ibex_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexSecIbexKeyDefault = {
+ 128'h196F6434_EDB26190_42C8C7CF_F5B4EC68
+ };
+
+ // Default icache scrambling nonce
+ parameter logic [ibex_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexSecIbexNonceDefault = {
+ 64'h1D5A3EF3_7CD3F7FE
+ };
+
+ ////////////////////////////////////////////
+ // rv_core_ibex_smc
+ ////////////////////////////////////////////
+ // Default seed of the PRNG used for random instructions.
+ parameter smc_pkg::lfsr_seed_t RndCnstRvCoreIbexSmcLfsrSeed = {
+ 32'hF64E04C8
+ };
+
+ // Permutation applied to the LFSR of the PRNG used for random instructions.
+ parameter smc_pkg::lfsr_perm_t RndCnstRvCoreIbexSmcLfsrPerm = {
+ 160'h6DC5830F_965D7E92_828E8BE7_BC93D242_BA1D4187
+ };
+
+ // Default icache scrambling key
+ parameter logic [smc_pkg::SCRAMBLE_KEY_W-1:0] RndCnstRvCoreIbexSmcSmcKeyDefault = {
+ 128'hE24FC1D6_CFA034F6_E43EB3D9_A0C8E9A6
+ };
+
+ // Default icache scrambling nonce
+ parameter logic [smc_pkg::SCRAMBLE_NONCE_W-1:0] RndCnstRvCoreIbexSmcSmcNonceDefault = {
+ 64'h805472C5_BAC69C84
+ };
+
+endpackage : top_sencha_rnd_cnst_pkg
diff --git a/hw/top_sencha/sw/autogen/top_sencha.c b/hw/top_sencha/sw/autogen/top_sencha.c
new file mode 100644
index 0000000..06f4733
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/top_sencha.c
@@ -0,0 +1,351 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#include "hw/top_sencha/sw/autogen/top_sencha.h"
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_plic_irq_id_t` to
+ * `top_sencha_plic_peripheral_t`.
+ */
+const top_sencha_plic_peripheral_t
+ top_sencha_plic_interrupt_for_peripheral[190] = {
+ [kTopSenchaPlicIrqIdNone] = kTopSenchaPlicPeripheralUnknown,
+ [kTopSenchaPlicIrqIdUart0TxWatermark] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxWatermark] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0TxEmpty] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxOverflow] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxFrameErr] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxBreakErr] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxTimeout] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart0RxParityErr] = kTopSenchaPlicPeripheralUart0,
+ [kTopSenchaPlicIrqIdUart1TxWatermark] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxWatermark] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1TxEmpty] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxOverflow] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxFrameErr] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxBreakErr] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxTimeout] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart1RxParityErr] = kTopSenchaPlicPeripheralUart1,
+ [kTopSenchaPlicIrqIdUart2TxWatermark] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxWatermark] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2TxEmpty] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxOverflow] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxFrameErr] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxBreakErr] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxTimeout] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart2RxParityErr] = kTopSenchaPlicPeripheralUart2,
+ [kTopSenchaPlicIrqIdUart3TxWatermark] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxWatermark] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3TxEmpty] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxOverflow] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxFrameErr] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxBreakErr] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxTimeout] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdUart3RxParityErr] = kTopSenchaPlicPeripheralUart3,
+ [kTopSenchaPlicIrqIdGpioGpio0] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio1] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio2] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio3] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio4] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio5] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio6] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio7] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio8] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio9] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio10] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio11] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio12] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio13] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio14] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio15] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio16] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio17] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio18] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio19] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio20] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio21] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio22] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio23] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio24] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio25] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio26] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio27] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio28] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio29] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio30] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdGpioGpio31] = kTopSenchaPlicPeripheralGpio,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericRxFull] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericRxWatermark] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericTxWatermark] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericRxError] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericRxOverflow] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceGenericTxUnderflow] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceUploadPayloadOverflow] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceReadbufWatermark] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceReadbufFlip] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopSenchaPlicPeripheralSpiDevice,
+ [kTopSenchaPlicIrqIdI2c0FmtThreshold] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0RxThreshold] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0FmtOverflow] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0RxOverflow] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0Nak] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0SclInterference] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0SdaInterference] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0StretchTimeout] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0SdaUnstable] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0CmdComplete] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0TxStretch] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0TxOverflow] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0AcqFull] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0UnexpStop] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c0HostTimeout] = kTopSenchaPlicPeripheralI2c0,
+ [kTopSenchaPlicIrqIdI2c1FmtThreshold] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1RxThreshold] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1FmtOverflow] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1RxOverflow] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1Nak] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1SclInterference] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1SdaInterference] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1StretchTimeout] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1SdaUnstable] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1CmdComplete] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1TxStretch] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1TxOverflow] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1AcqFull] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1UnexpStop] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c1HostTimeout] = kTopSenchaPlicPeripheralI2c1,
+ [kTopSenchaPlicIrqIdI2c2FmtThreshold] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2RxThreshold] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2FmtOverflow] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2RxOverflow] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2Nak] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2SclInterference] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2SdaInterference] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2StretchTimeout] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2SdaUnstable] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2CmdComplete] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2TxStretch] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2TxOverflow] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2AcqFull] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2UnexpStop] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdI2c2HostTimeout] = kTopSenchaPlicPeripheralI2c2,
+ [kTopSenchaPlicIrqIdPattgenDoneCh0] = kTopSenchaPlicPeripheralPattgen,
+ [kTopSenchaPlicIrqIdPattgenDoneCh1] = kTopSenchaPlicPeripheralPattgen,
+ [kTopSenchaPlicIrqIdRvTimerTimerExpiredHart0Timer0] = kTopSenchaPlicPeripheralRvTimer,
+ [kTopSenchaPlicIrqIdOtpCtrlOtpOperationDone] = kTopSenchaPlicPeripheralOtpCtrl,
+ [kTopSenchaPlicIrqIdOtpCtrlOtpError] = kTopSenchaPlicPeripheralOtpCtrl,
+ [kTopSenchaPlicIrqIdAlertHandlerClassa] = kTopSenchaPlicPeripheralAlertHandler,
+ [kTopSenchaPlicIrqIdAlertHandlerClassb] = kTopSenchaPlicPeripheralAlertHandler,
+ [kTopSenchaPlicIrqIdAlertHandlerClassc] = kTopSenchaPlicPeripheralAlertHandler,
+ [kTopSenchaPlicIrqIdAlertHandlerClassd] = kTopSenchaPlicPeripheralAlertHandler,
+ [kTopSenchaPlicIrqIdSpiHost0Error] = kTopSenchaPlicPeripheralSpiHost0,
+ [kTopSenchaPlicIrqIdSpiHost0SpiEvent] = kTopSenchaPlicPeripheralSpiHost0,
+ [kTopSenchaPlicIrqIdSpiHost1Error] = kTopSenchaPlicPeripheralSpiHost1,
+ [kTopSenchaPlicIrqIdSpiHost1SpiEvent] = kTopSenchaPlicPeripheralSpiHost1,
+ [kTopSenchaPlicIrqIdUsbdevPktReceived] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevPktSent] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevDisconnected] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevHostLost] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevLinkReset] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevLinkSuspend] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevLinkResume] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevAvEmpty] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevRxFull] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevAvOverflow] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevLinkInErr] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevRxCrcErr] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevRxPidErr] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevRxBitstuffErr] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevFrame] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevPowered] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdUsbdevLinkOutErr] = kTopSenchaPlicPeripheralUsbdev,
+ [kTopSenchaPlicIrqIdPwrmgrAonWakeup] = kTopSenchaPlicPeripheralPwrmgrAon,
+ [kTopSenchaPlicIrqIdSysrstCtrlAonEventDetected] = kTopSenchaPlicPeripheralSysrstCtrlAon,
+ [kTopSenchaPlicIrqIdAdcCtrlAonMatchDone] = kTopSenchaPlicPeripheralAdcCtrlAon,
+ [kTopSenchaPlicIrqIdAonTimerAonWkupTimerExpired] = kTopSenchaPlicPeripheralAonTimerAon,
+ [kTopSenchaPlicIrqIdAonTimerAonWdogTimerBark] = kTopSenchaPlicPeripheralAonTimerAon,
+ [kTopSenchaPlicIrqIdSensorCtrlIoStatusChange] = kTopSenchaPlicPeripheralSensorCtrl,
+ [kTopSenchaPlicIrqIdSensorCtrlInitStatusChange] = kTopSenchaPlicPeripheralSensorCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlProgEmpty] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlProgLvl] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlRdFull] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlRdLvl] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlOpDone] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdFlashCtrlCorrErr] = kTopSenchaPlicPeripheralFlashCtrl,
+ [kTopSenchaPlicIrqIdHmacHmacDone] = kTopSenchaPlicPeripheralHmac,
+ [kTopSenchaPlicIrqIdHmacFifoEmpty] = kTopSenchaPlicPeripheralHmac,
+ [kTopSenchaPlicIrqIdHmacHmacErr] = kTopSenchaPlicPeripheralHmac,
+ [kTopSenchaPlicIrqIdKmacKmacDone] = kTopSenchaPlicPeripheralKmac,
+ [kTopSenchaPlicIrqIdKmacFifoEmpty] = kTopSenchaPlicPeripheralKmac,
+ [kTopSenchaPlicIrqIdKmacKmacErr] = kTopSenchaPlicPeripheralKmac,
+ [kTopSenchaPlicIrqIdOtbnDone] = kTopSenchaPlicPeripheralOtbn,
+ [kTopSenchaPlicIrqIdKeymgrOpDone] = kTopSenchaPlicPeripheralKeymgr,
+ [kTopSenchaPlicIrqIdCsrngCsCmdReqDone] = kTopSenchaPlicPeripheralCsrng,
+ [kTopSenchaPlicIrqIdCsrngCsEntropyReq] = kTopSenchaPlicPeripheralCsrng,
+ [kTopSenchaPlicIrqIdCsrngCsHwInstExc] = kTopSenchaPlicPeripheralCsrng,
+ [kTopSenchaPlicIrqIdCsrngCsFatalErr] = kTopSenchaPlicPeripheralCsrng,
+ [kTopSenchaPlicIrqIdEntropySrcEsEntropyValid] = kTopSenchaPlicPeripheralEntropySrc,
+ [kTopSenchaPlicIrqIdEntropySrcEsHealthTestFailed] = kTopSenchaPlicPeripheralEntropySrc,
+ [kTopSenchaPlicIrqIdEntropySrcEsObserveFifoReady] = kTopSenchaPlicPeripheralEntropySrc,
+ [kTopSenchaPlicIrqIdEntropySrcEsFatalErr] = kTopSenchaPlicPeripheralEntropySrc,
+ [kTopSenchaPlicIrqIdEdn0EdnCmdReqDone] = kTopSenchaPlicPeripheralEdn0,
+ [kTopSenchaPlicIrqIdEdn0EdnFatalErr] = kTopSenchaPlicPeripheralEdn0,
+ [kTopSenchaPlicIrqIdEdn1EdnCmdReqDone] = kTopSenchaPlicPeripheralEdn1,
+ [kTopSenchaPlicIrqIdEdn1EdnFatalErr] = kTopSenchaPlicPeripheralEdn1,
+ [kTopSenchaPlicIrqIdDma0WriterDone] = kTopSenchaPlicPeripheralDma0,
+ [kTopSenchaPlicIrqIdDma0ReaderDone] = kTopSenchaPlicPeripheralDma0,
+ [kTopSenchaPlicIrqIdTlulMailboxSecWtirq] = kTopSenchaPlicPeripheralTlulMailboxSec,
+ [kTopSenchaPlicIrqIdTlulMailboxSecRtirq] = kTopSenchaPlicPeripheralTlulMailboxSec,
+ [kTopSenchaPlicIrqIdTlulMailboxSecEirq] = kTopSenchaPlicPeripheralTlulMailboxSec,
+};
+
+const top_sencha_plic_peripheral_smc_t
+ top_sencha_plic_interrupt_for_peripheral_smc[43] = {
+ [kTopSenchaPlicIrqIdNoneSmc] = kTopSenchaPlicPeripheralUnknownSmc,
+ [kTopSenchaPlicIrqIdSmcUartTxWatermark] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxWatermark] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartTxEmpty] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxOverflow] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxFrameErr] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxBreakErr] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxTimeout] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdSmcUartRxParityErr] = kTopSenchaPlicPeripheralSmcUart,
+ [kTopSenchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0] = kTopSenchaPlicPeripheralRvTimerSmc,
+ [kTopSenchaPlicIrqIdCamI2cFmtThreshold] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cRxThreshold] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cFmtOverflow] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cRxOverflow] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cNak] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cSclInterference] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cSdaInterference] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cStretchTimeout] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cSdaUnstable] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cCmdComplete] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cTxStretch] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cTxOverflow] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cAcqFull] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cUnexpStop] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamI2cHostTimeout] = kTopSenchaPlicPeripheralCamI2c,
+ [kTopSenchaPlicIrqIdCamCtrlCamMotionDetect] = kTopSenchaPlicPeripheralCamCtrl,
+ [kTopSenchaPlicIrqIdIspWrapperIsp] = kTopSenchaPlicPeripheralIspWrapper,
+ [kTopSenchaPlicIrqIdIspWrapperMi] = kTopSenchaPlicPeripheralIspWrapper,
+ [kTopSenchaPlicIrqIdDmaSmcWriterDone] = kTopSenchaPlicPeripheralDmaSmc,
+ [kTopSenchaPlicIrqIdDmaSmcReaderDone] = kTopSenchaPlicPeripheralDmaSmc,
+ [kTopSenchaPlicIrqIdTlulMailboxSmcWtirq] = kTopSenchaPlicPeripheralTlulMailboxSmc,
+ [kTopSenchaPlicIrqIdTlulMailboxSmcRtirq] = kTopSenchaPlicPeripheralTlulMailboxSmc,
+ [kTopSenchaPlicIrqIdTlulMailboxSmcEirq] = kTopSenchaPlicPeripheralTlulMailboxSmc,
+ [kTopSenchaPlicIrqIdMlTopHostReq] = kTopSenchaPlicPeripheralMlTop,
+ [kTopSenchaPlicIrqIdMlTopFinish] = kTopSenchaPlicPeripheralMlTop,
+ [kTopSenchaPlicIrqIdMlTopFault] = kTopSenchaPlicPeripheralMlTop,
+ [kTopSenchaPlicIrqIdSpiHost2Error] = kTopSenchaPlicPeripheralSpiHost2,
+ [kTopSenchaPlicIrqIdSpiHost2SpiEvent] = kTopSenchaPlicPeripheralSpiHost2,
+ [kTopSenchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0] = kTopSenchaPlicPeripheralRvTimerSmc2,
+ [kTopSenchaPlicIrqIdI2s0TxWatermark] = kTopSenchaPlicPeripheralI2s0,
+ [kTopSenchaPlicIrqIdI2s0RxWatermark] = kTopSenchaPlicPeripheralI2s0,
+ [kTopSenchaPlicIrqIdI2s0TxEmpty] = kTopSenchaPlicPeripheralI2s0,
+ [kTopSenchaPlicIrqIdI2s0RxOverflow] = kTopSenchaPlicPeripheralI2s0,
+};
+
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_alert_id_t` to
+ * `top_sencha_alert_peripheral_t`.
+ */
+const top_sencha_alert_peripheral_t
+ top_sencha_alert_for_peripheral[75] = {
+ [kTopSenchaAlertIdUart0FatalFault] = kTopSenchaAlertPeripheralUart0,
+ [kTopSenchaAlertIdUart1FatalFault] = kTopSenchaAlertPeripheralUart1,
+ [kTopSenchaAlertIdUart2FatalFault] = kTopSenchaAlertPeripheralUart2,
+ [kTopSenchaAlertIdUart3FatalFault] = kTopSenchaAlertPeripheralUart3,
+ [kTopSenchaAlertIdGpioFatalFault] = kTopSenchaAlertPeripheralGpio,
+ [kTopSenchaAlertIdSpiDeviceFatalFault] = kTopSenchaAlertPeripheralSpiDevice,
+ [kTopSenchaAlertIdI2c0FatalFault] = kTopSenchaAlertPeripheralI2c0,
+ [kTopSenchaAlertIdI2c1FatalFault] = kTopSenchaAlertPeripheralI2c1,
+ [kTopSenchaAlertIdI2c2FatalFault] = kTopSenchaAlertPeripheralI2c2,
+ [kTopSenchaAlertIdPattgenFatalFault] = kTopSenchaAlertPeripheralPattgen,
+ [kTopSenchaAlertIdRvTimerFatalFault] = kTopSenchaAlertPeripheralRvTimer,
+ [kTopSenchaAlertIdOtpCtrlFatalMacroError] = kTopSenchaAlertPeripheralOtpCtrl,
+ [kTopSenchaAlertIdOtpCtrlFatalCheckError] = kTopSenchaAlertPeripheralOtpCtrl,
+ [kTopSenchaAlertIdOtpCtrlFatalBusIntegError] = kTopSenchaAlertPeripheralOtpCtrl,
+ [kTopSenchaAlertIdOtpCtrlFatalPrimOtpAlert] = kTopSenchaAlertPeripheralOtpCtrl,
+ [kTopSenchaAlertIdOtpCtrlRecovPrimOtpAlert] = kTopSenchaAlertPeripheralOtpCtrl,
+ [kTopSenchaAlertIdLcCtrlFatalProgError] = kTopSenchaAlertPeripheralLcCtrl,
+ [kTopSenchaAlertIdLcCtrlFatalStateError] = kTopSenchaAlertPeripheralLcCtrl,
+ [kTopSenchaAlertIdLcCtrlFatalBusIntegError] = kTopSenchaAlertPeripheralLcCtrl,
+ [kTopSenchaAlertIdSpiHost0FatalFault] = kTopSenchaAlertPeripheralSpiHost0,
+ [kTopSenchaAlertIdSpiHost1FatalFault] = kTopSenchaAlertPeripheralSpiHost1,
+ [kTopSenchaAlertIdUsbdevFatalFault] = kTopSenchaAlertPeripheralUsbdev,
+ [kTopSenchaAlertIdPwrmgrAonFatalFault] = kTopSenchaAlertPeripheralPwrmgrAon,
+ [kTopSenchaAlertIdRstmgrAonFatalFault] = kTopSenchaAlertPeripheralRstmgrAon,
+ [kTopSenchaAlertIdRstmgrAonFatalCnstyFault] = kTopSenchaAlertPeripheralRstmgrAon,
+ [kTopSenchaAlertIdClkmgrAonRecovFault] = kTopSenchaAlertPeripheralClkmgrAon,
+ [kTopSenchaAlertIdClkmgrAonFatalFault] = kTopSenchaAlertPeripheralClkmgrAon,
+ [kTopSenchaAlertIdSysrstCtrlAonFatalFault] = kTopSenchaAlertPeripheralSysrstCtrlAon,
+ [kTopSenchaAlertIdAdcCtrlAonFatalFault] = kTopSenchaAlertPeripheralAdcCtrlAon,
+ [kTopSenchaAlertIdPwmAonFatalFault] = kTopSenchaAlertPeripheralPwmAon,
+ [kTopSenchaAlertIdPinmuxAonFatalFault] = kTopSenchaAlertPeripheralPinmuxAon,
+ [kTopSenchaAlertIdAonTimerAonFatalFault] = kTopSenchaAlertPeripheralAonTimerAon,
+ [kTopSenchaAlertIdSensorCtrlRecovAlert] = kTopSenchaAlertPeripheralSensorCtrl,
+ [kTopSenchaAlertIdSensorCtrlFatalAlert] = kTopSenchaAlertPeripheralSensorCtrl,
+ [kTopSenchaAlertIdSramCtrlRetAonFatalError] = kTopSenchaAlertPeripheralSramCtrlRetAon,
+ [kTopSenchaAlertIdFlashCtrlRecovErr] = kTopSenchaAlertPeripheralFlashCtrl,
+ [kTopSenchaAlertIdFlashCtrlFatalStdErr] = kTopSenchaAlertPeripheralFlashCtrl,
+ [kTopSenchaAlertIdFlashCtrlFatalErr] = kTopSenchaAlertPeripheralFlashCtrl,
+ [kTopSenchaAlertIdFlashCtrlFatalPrimFlashAlert] = kTopSenchaAlertPeripheralFlashCtrl,
+ [kTopSenchaAlertIdFlashCtrlRecovPrimFlashAlert] = kTopSenchaAlertPeripheralFlashCtrl,
+ [kTopSenchaAlertIdRvDmFatalFault] = kTopSenchaAlertPeripheralRvDm,
+ [kTopSenchaAlertIdRvPlicFatalFault] = kTopSenchaAlertPeripheralRvPlic,
+ [kTopSenchaAlertIdAesRecovCtrlUpdateErr] = kTopSenchaAlertPeripheralAes,
+ [kTopSenchaAlertIdAesFatalFault] = kTopSenchaAlertPeripheralAes,
+ [kTopSenchaAlertIdHmacFatalFault] = kTopSenchaAlertPeripheralHmac,
+ [kTopSenchaAlertIdKmacRecovOperationErr] = kTopSenchaAlertPeripheralKmac,
+ [kTopSenchaAlertIdKmacFatalFaultErr] = kTopSenchaAlertPeripheralKmac,
+ [kTopSenchaAlertIdOtbnFatal] = kTopSenchaAlertPeripheralOtbn,
+ [kTopSenchaAlertIdOtbnRecov] = kTopSenchaAlertPeripheralOtbn,
+ [kTopSenchaAlertIdKeymgrRecovOperationErr] = kTopSenchaAlertPeripheralKeymgr,
+ [kTopSenchaAlertIdKeymgrFatalFaultErr] = kTopSenchaAlertPeripheralKeymgr,
+ [kTopSenchaAlertIdCsrngRecovAlert] = kTopSenchaAlertPeripheralCsrng,
+ [kTopSenchaAlertIdCsrngFatalAlert] = kTopSenchaAlertPeripheralCsrng,
+ [kTopSenchaAlertIdEntropySrcRecovAlert] = kTopSenchaAlertPeripheralEntropySrc,
+ [kTopSenchaAlertIdEntropySrcFatalAlert] = kTopSenchaAlertPeripheralEntropySrc,
+ [kTopSenchaAlertIdEdn0RecovAlert] = kTopSenchaAlertPeripheralEdn0,
+ [kTopSenchaAlertIdEdn0FatalAlert] = kTopSenchaAlertPeripheralEdn0,
+ [kTopSenchaAlertIdEdn1RecovAlert] = kTopSenchaAlertPeripheralEdn1,
+ [kTopSenchaAlertIdEdn1FatalAlert] = kTopSenchaAlertPeripheralEdn1,
+ [kTopSenchaAlertIdSramCtrlMainFatalError] = kTopSenchaAlertPeripheralSramCtrlMain,
+ [kTopSenchaAlertIdRomCtrlFatal] = kTopSenchaAlertPeripheralRomCtrl,
+ [kTopSenchaAlertIdRvCoreIbexSecFatalSwErr] = kTopSenchaAlertPeripheralRvCoreIbexSec,
+ [kTopSenchaAlertIdRvCoreIbexSecRecovSwErr] = kTopSenchaAlertPeripheralRvCoreIbexSec,
+ [kTopSenchaAlertIdRvCoreIbexSecFatalHwErr] = kTopSenchaAlertPeripheralRvCoreIbexSec,
+ [kTopSenchaAlertIdRvCoreIbexSecRecovHwErr] = kTopSenchaAlertPeripheralRvCoreIbexSec,
+ [kTopSenchaAlertIdSmcUartFatalFault] = kTopSenchaAlertPeripheralSmcUart,
+ [kTopSenchaAlertIdRvTimerSmcFatalFault] = kTopSenchaAlertPeripheralRvTimerSmc,
+ [kTopSenchaAlertIdCamI2cFatalFault] = kTopSenchaAlertPeripheralCamI2c,
+ [kTopSenchaAlertIdRvPlicSmcFatalFault] = kTopSenchaAlertPeripheralRvPlicSmc,
+ [kTopSenchaAlertIdSpiHost2FatalFault] = kTopSenchaAlertPeripheralSpiHost2,
+ [kTopSenchaAlertIdRvTimerSmc2FatalFault] = kTopSenchaAlertPeripheralRvTimerSmc2,
+ [kTopSenchaAlertIdRvCoreIbexSmcFatalSwErr] = kTopSenchaAlertPeripheralRvCoreIbexSmc,
+ [kTopSenchaAlertIdRvCoreIbexSmcRecovSwErr] = kTopSenchaAlertPeripheralRvCoreIbexSmc,
+ [kTopSenchaAlertIdRvCoreIbexSmcFatalHwErr] = kTopSenchaAlertPeripheralRvCoreIbexSmc,
+ [kTopSenchaAlertIdRvCoreIbexSmcRecovHwErr] = kTopSenchaAlertPeripheralRvCoreIbexSmc,
+};
+
diff --git a/hw/top_sencha/sw/autogen/top_sencha.h b/hw/top_sencha/sw/autogen/top_sencha.h
new file mode 100644
index 0000000..a8572e3
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/top_sencha.h
@@ -0,0 +1,2280 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_H_
+#define MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_H_
+
+/**
+ * @file
+ * @brief Top-specific Definitions
+ *
+ * This file contains preprocessor and type definitions for use within the
+ * device C/C++ codebase.
+ *
+ * These definitions are for information that depends on the top-specific chip
+ * configuration, which includes:
+ * - Device Memory Information (for Peripherals and Memory)
+ * - PLIC Interrupt ID Names and Source Mappings
+ * - Alert ID Names and Source Mappings
+ * - Pinmux Pin/Select Names
+ * - Power Manager Wakeups
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Peripheral base address for uart0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART0_BASE_ADDR 0x40000000u
+
+/**
+ * Peripheral size for uart0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART0_BASE_ADDR and
+ * `TOP_SENCHA_UART0_BASE_ADDR + TOP_SENCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART1_BASE_ADDR 0x40010000u
+
+/**
+ * Peripheral size for uart1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART1_BASE_ADDR and
+ * `TOP_SENCHA_UART1_BASE_ADDR + TOP_SENCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART2_BASE_ADDR 0x40020000u
+
+/**
+ * Peripheral size for uart2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART2_BASE_ADDR and
+ * `TOP_SENCHA_UART2_BASE_ADDR + TOP_SENCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart3 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART3_BASE_ADDR 0x40030000u
+
+/**
+ * Peripheral size for uart3 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART3_BASE_ADDR and
+ * `TOP_SENCHA_UART3_BASE_ADDR + TOP_SENCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART3_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for gpio in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_GPIO_BASE_ADDR 0x40040000u
+
+/**
+ * Peripheral size for gpio in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_GPIO_BASE_ADDR and
+ * `TOP_SENCHA_GPIO_BASE_ADDR + TOP_SENCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_GPIO_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_device in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_DEVICE_BASE_ADDR 0x40050000u
+
+/**
+ * Peripheral size for spi_device in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_SENCHA_SPI_DEVICE_BASE_ADDR + TOP_SENCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_DEVICE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for i2c0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C0_BASE_ADDR 0x40080000u
+
+/**
+ * Peripheral size for i2c0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C0_BASE_ADDR and
+ * `TOP_SENCHA_I2C0_BASE_ADDR + TOP_SENCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C1_BASE_ADDR 0x40090000u
+
+/**
+ * Peripheral size for i2c1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C1_BASE_ADDR and
+ * `TOP_SENCHA_I2C1_BASE_ADDR + TOP_SENCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C2_BASE_ADDR 0x400A0000u
+
+/**
+ * Peripheral size for i2c2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C2_BASE_ADDR and
+ * `TOP_SENCHA_I2C2_BASE_ADDR + TOP_SENCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C2_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pattgen in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PATTGEN_BASE_ADDR 0x400E0000u
+
+/**
+ * Peripheral size for pattgen in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PATTGEN_BASE_ADDR and
+ * `TOP_SENCHA_PATTGEN_BASE_ADDR + TOP_SENCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PATTGEN_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_BASE_ADDR 0x40100000u
+
+/**
+ * Peripheral size for rv_timer in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_BASE_ADDR + TOP_SENCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for core device on otp_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
+
+/**
+ * Peripheral size for core device on otp_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_SENCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for prim device on otp_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000u
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_SENCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for lc_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_LC_CTRL_BASE_ADDR 0x40140000u
+
+/**
+ * Peripheral size for lc_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_LC_CTRL_BASE_ADDR + TOP_SENCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_LC_CTRL_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for alert_handler in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ALERT_HANDLER_BASE_ADDR 0x40150000u
+
+/**
+ * Peripheral size for alert_handler in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_SENCHA_ALERT_HANDLER_BASE_ADDR + TOP_SENCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ALERT_HANDLER_SIZE_BYTES 0x800u
+
+/**
+ * Peripheral base address for spi_host0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST0_BASE_ADDR 0x40300000u
+
+/**
+ * Peripheral size for spi_host0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST0_BASE_ADDR + TOP_SENCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_host1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST1_BASE_ADDR 0x40310000u
+
+/**
+ * Peripheral size for spi_host1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST1_BASE_ADDR + TOP_SENCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for usbdev in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_USBDEV_BASE_ADDR 0x40320000u
+
+/**
+ * Peripheral size for usbdev in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_USBDEV_BASE_ADDR and
+ * `TOP_SENCHA_USBDEV_BASE_ADDR + TOP_SENCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_USBDEV_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for pwrmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PWRMGR_AON_BASE_ADDR 0x40400000u
+
+/**
+ * Peripheral size for pwrmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_PWRMGR_AON_BASE_ADDR + TOP_SENCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PWRMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rstmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RSTMGR_AON_BASE_ADDR 0x40410000u
+
+/**
+ * Peripheral size for rstmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_RSTMGR_AON_BASE_ADDR + TOP_SENCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RSTMGR_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for clkmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CLKMGR_AON_BASE_ADDR 0x40420000u
+
+/**
+ * Peripheral size for clkmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_CLKMGR_AON_BASE_ADDR + TOP_SENCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CLKMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_SENCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for adc_ctrl_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000u
+
+/**
+ * Peripheral size for adc_ctrl_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR + TOP_SENCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ADC_CTRL_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pwm_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PWM_AON_BASE_ADDR 0x40450000u
+
+/**
+ * Peripheral size for pwm_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PWM_AON_BASE_ADDR and
+ * `TOP_SENCHA_PWM_AON_BASE_ADDR + TOP_SENCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PWM_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pinmux_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PINMUX_AON_BASE_ADDR 0x40460000u
+
+/**
+ * Peripheral size for pinmux_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_SENCHA_PINMUX_AON_BASE_ADDR + TOP_SENCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PINMUX_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for aon_timer_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AON_TIMER_AON_BASE_ADDR 0x40470000u
+
+/**
+ * Peripheral size for aon_timer_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_SENCHA_AON_TIMER_AON_BASE_ADDR + TOP_SENCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AON_TIMER_AON_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for ast in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AST_BASE_ADDR 0x40480000u
+
+/**
+ * Peripheral size for ast in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AST_BASE_ADDR and
+ * `TOP_SENCHA_AST_BASE_ADDR + TOP_SENCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AST_SIZE_BYTES 0x400u
+
+/**
+ * Peripheral base address for sensor_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SENSOR_CTRL_BASE_ADDR 0x40490000u
+
+/**
+ * Peripheral size for sensor_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_SENSOR_CTRL_BASE_ADDR + TOP_SENCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SENSOR_CTRL_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for core device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
+
+/**
+ * Peripheral size for core device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for prim device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for mem device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
+
+/**
+ * Peripheral base address for regs device on rv_dm in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_DM_REGS_BASE_ADDR 0x6000u
+
+/**
+ * Peripheral size for regs device on rv_dm in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_SENCHA_RV_DM_REGS_BASE_ADDR + TOP_SENCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_DM_REGS_SIZE_BYTES 0x4u
+
+/**
+ * Peripheral base address for mem device on rv_dm in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_DM_MEM_BASE_ADDR 0x4000u
+
+/**
+ * Peripheral size for mem device on rv_dm in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_SENCHA_RV_DM_MEM_BASE_ADDR + TOP_SENCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_DM_MEM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for rv_plic in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_PLIC_BASE_ADDR 0x48000000u
+
+/**
+ * Peripheral size for rv_plic in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_SENCHA_RV_PLIC_BASE_ADDR + TOP_SENCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_PLIC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for aes in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AES_BASE_ADDR 0x41100000u
+
+/**
+ * Peripheral size for aes in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AES_BASE_ADDR and
+ * `TOP_SENCHA_AES_BASE_ADDR + TOP_SENCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AES_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for hmac in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_HMAC_BASE_ADDR 0x41110000u
+
+/**
+ * Peripheral size for hmac in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_HMAC_BASE_ADDR and
+ * `TOP_SENCHA_HMAC_BASE_ADDR + TOP_SENCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_HMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for kmac in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_KMAC_BASE_ADDR 0x41120000u
+
+/**
+ * Peripheral size for kmac in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_KMAC_BASE_ADDR and
+ * `TOP_SENCHA_KMAC_BASE_ADDR + TOP_SENCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_KMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for otbn in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTBN_BASE_ADDR 0x41130000u
+
+/**
+ * Peripheral size for otbn in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTBN_BASE_ADDR and
+ * `TOP_SENCHA_OTBN_BASE_ADDR + TOP_SENCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTBN_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for keymgr in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_KEYMGR_BASE_ADDR 0x41140000u
+
+/**
+ * Peripheral size for keymgr in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_KEYMGR_BASE_ADDR and
+ * `TOP_SENCHA_KEYMGR_BASE_ADDR + TOP_SENCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_KEYMGR_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for csrng in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CSRNG_BASE_ADDR 0x41150000u
+
+/**
+ * Peripheral size for csrng in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CSRNG_BASE_ADDR and
+ * `TOP_SENCHA_CSRNG_BASE_ADDR + TOP_SENCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CSRNG_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for entropy_src in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ENTROPY_SRC_BASE_ADDR 0x41160000u
+
+/**
+ * Peripheral size for entropy_src in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_SENCHA_ENTROPY_SRC_BASE_ADDR + TOP_SENCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ENTROPY_SRC_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for edn0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_EDN0_BASE_ADDR 0x41170000u
+
+/**
+ * Peripheral size for edn0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_EDN0_BASE_ADDR and
+ * `TOP_SENCHA_EDN0_BASE_ADDR + TOP_SENCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_EDN0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for edn1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_EDN1_BASE_ADDR 0x41180000u
+
+/**
+ * Peripheral size for edn1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_EDN1_BASE_ADDR and
+ * `TOP_SENCHA_EDN1_BASE_ADDR + TOP_SENCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_EDN1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
+
+/**
+ * Peripheral base address for regs device on rom_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_SENCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rom device on rom_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_SENCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for dma0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_DMA0_BASE_ADDR 0x40200000u
+
+/**
+ * Peripheral size for dma0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_DMA0_BASE_ADDR and
+ * `TOP_SENCHA_DMA0_BASE_ADDR + TOP_SENCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_DMA0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for smc_uart in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SMC_UART_BASE_ADDR 0x54000000u
+
+/**
+ * Peripheral size for smc_uart in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SMC_UART_BASE_ADDR and
+ * `TOP_SENCHA_SMC_UART_BASE_ADDR + TOP_SENCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SMC_UART_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000u
+
+/**
+ * Peripheral size for rv_timer_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR + TOP_SENCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SMC_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for smc_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SMC_CTRL_BASE_ADDR 0x54020000u
+
+/**
+ * Peripheral size for smc_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_SMC_CTRL_BASE_ADDR + TOP_SENCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SMC_CTRL_SIZE_BYTES 0x8u
+
+/**
+ * Peripheral base address for cam_i2c in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CAM_I2C_BASE_ADDR 0x54040000u
+
+/**
+ * Peripheral size for cam_i2c in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_SENCHA_CAM_I2C_BASE_ADDR + TOP_SENCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CAM_I2C_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for cam_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CAM_CTRL_BASE_ADDR 0x54050000u
+
+/**
+ * Peripheral size for cam_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_CAM_CTRL_BASE_ADDR + TOP_SENCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CAM_CTRL_SIZE_BYTES 0x10u
+
+/**
+ * Peripheral base address for isp_wrapper in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ISP_WRAPPER_BASE_ADDR 0x54060000u
+
+/**
+ * Peripheral size for isp_wrapper in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ISP_WRAPPER_BASE_ADDR and
+ * `TOP_SENCHA_ISP_WRAPPER_BASE_ADDR + TOP_SENCHA_ISP_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ISP_WRAPPER_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for dma_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_DMA_SMC_BASE_ADDR 0x54070000u
+
+/**
+ * Peripheral size for dma_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_SENCHA_DMA_SMC_BASE_ADDR + TOP_SENCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_DMA_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_plic_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000u
+
+/**
+ * Peripheral size for rv_plic_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR + TOP_SENCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for tlul_mailbox_sec in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000u
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_SENCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for tlul_mailbox_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000u
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_SENCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for core device on ml_top in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000u
+
+/**
+ * Peripheral size for core device on ml_top in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_SENCHA_ML_TOP_CORE_BASE_ADDR + TOP_SENCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ML_TOP_CORE_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for dmem device on ml_top in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Peripheral size for dmem device on ml_top in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR + TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000u
+
+/**
+ * Peripheral base address for spi_host2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST2_BASE_ADDR 0x54090000u
+
+/**
+ * Peripheral size for spi_host2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST2_BASE_ADDR + TOP_SENCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000u
+
+/**
+ * Peripheral size for rv_timer_smc2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_SENCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for i2s0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2S0_BASE_ADDR 0x54100000u
+
+/**
+ * Peripheral size for i2s0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2S0_BASE_ADDR and
+ * `TOP_SENCHA_I2S0_BASE_ADDR + TOP_SENCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2S0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100u
+
+
+/**
+ * Memory base address for ram_smc in top sencha.
+ */
+#define TOP_SENCHA_RAM_SMC_BASE_ADDR 0x50000000u
+
+/**
+ * Memory size for ram_smc in top sencha.
+ */
+#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x400000u
+
+/**
+ * Memory base address for ram_ret_aon in top sencha.
+ */
+#define TOP_SENCHA_RAM_RET_AON_BASE_ADDR 0x40600000u
+
+/**
+ * Memory size for ram_ret_aon in top sencha.
+ */
+#define TOP_SENCHA_RAM_RET_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Memory base address for eflash in top sencha.
+ */
+#define TOP_SENCHA_EFLASH_BASE_ADDR 0x20000000u
+
+/**
+ * Memory size for eflash in top sencha.
+ */
+#define TOP_SENCHA_EFLASH_SIZE_BYTES 0x100000u
+
+/**
+ * Memory base address for ram_main in top sencha.
+ */
+#define TOP_SENCHA_RAM_MAIN_BASE_ADDR 0x10000000u
+
+/**
+ * Memory size for ram_main in top sencha.
+ */
+#define TOP_SENCHA_RAM_MAIN_SIZE_BYTES 0x20000u
+
+/**
+ * Memory base address for rom in top sencha.
+ */
+#define TOP_SENCHA_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Memory size for rom in top sencha.
+ */
+#define TOP_SENCHA_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Memory base address for ram_ml_dmem in top sencha.
+ */
+#define TOP_SENCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Memory size for ram_ml_dmem in top sencha.
+ */
+#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000u
+
+
+/**
+ * PLIC Interrupt Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * interrupt.
+ */
+typedef enum top_sencha_plic_peripheral {
+ kTopSenchaPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
+ kTopSenchaPlicPeripheralUart0 = 1, /**< uart0 */
+ kTopSenchaPlicPeripheralUart1 = 2, /**< uart1 */
+ kTopSenchaPlicPeripheralUart2 = 3, /**< uart2 */
+ kTopSenchaPlicPeripheralUart3 = 4, /**< uart3 */
+ kTopSenchaPlicPeripheralGpio = 5, /**< gpio */
+ kTopSenchaPlicPeripheralSpiDevice = 6, /**< spi_device */
+ kTopSenchaPlicPeripheralI2c0 = 7, /**< i2c0 */
+ kTopSenchaPlicPeripheralI2c1 = 8, /**< i2c1 */
+ kTopSenchaPlicPeripheralI2c2 = 9, /**< i2c2 */
+ kTopSenchaPlicPeripheralPattgen = 10, /**< pattgen */
+ kTopSenchaPlicPeripheralRvTimer = 11, /**< rv_timer */
+ kTopSenchaPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
+ kTopSenchaPlicPeripheralAlertHandler = 13, /**< alert_handler */
+ kTopSenchaPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
+ kTopSenchaPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
+ kTopSenchaPlicPeripheralUsbdev = 16, /**< usbdev */
+ kTopSenchaPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
+ kTopSenchaPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
+ kTopSenchaPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
+ kTopSenchaPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
+ kTopSenchaPlicPeripheralSensorCtrl = 21, /**< sensor_ctrl */
+ kTopSenchaPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
+ kTopSenchaPlicPeripheralHmac = 23, /**< hmac */
+ kTopSenchaPlicPeripheralKmac = 24, /**< kmac */
+ kTopSenchaPlicPeripheralOtbn = 25, /**< otbn */
+ kTopSenchaPlicPeripheralKeymgr = 26, /**< keymgr */
+ kTopSenchaPlicPeripheralCsrng = 27, /**< csrng */
+ kTopSenchaPlicPeripheralEntropySrc = 28, /**< entropy_src */
+ kTopSenchaPlicPeripheralEdn0 = 29, /**< edn0 */
+ kTopSenchaPlicPeripheralEdn1 = 30, /**< edn1 */
+ kTopSenchaPlicPeripheralDma0 = 31, /**< dma0 */
+ kTopSenchaPlicPeripheralTlulMailboxSec = 32, /**< tlul_mailbox_sec */
+ kTopSenchaPlicPeripheralLast = 32, /**< \internal Final PLIC peripheral */
+} top_sencha_plic_peripheral_t;
+
+typedef enum top_sencha_plic_peripheral_smc {
+ kTopSenchaPlicPeripheralUnknownSmc = 0, /**< Unknown Peripheral */
+ kTopSenchaPlicPeripheralSmcUart = 1, /**< smc_uart */
+ kTopSenchaPlicPeripheralRvTimerSmc = 2, /**< rv_timer_smc */
+ kTopSenchaPlicPeripheralCamI2c = 3, /**< cam_i2c */
+ kTopSenchaPlicPeripheralCamCtrl = 4, /**< cam_ctrl */
+ kTopSenchaPlicPeripheralIspWrapper = 5, /**< isp_wrapper */
+ kTopSenchaPlicPeripheralDmaSmc = 6, /**< dma_smc */
+ kTopSenchaPlicPeripheralTlulMailboxSmc = 7, /**< tlul_mailbox_smc */
+ kTopSenchaPlicPeripheralMlTop = 8, /**< ml_top */
+ kTopSenchaPlicPeripheralSpiHost2 = 9, /**< spi_host2 */
+ kTopSenchaPlicPeripheralRvTimerSmc2 = 10, /**< rv_timer_smc2 */
+ kTopSenchaPlicPeripheralI2s0 = 11, /**< i2s0 */
+ kTopSenchaPlicPeripheralLastSmc = 11, /**< \internal Final PLIC peripheral */
+} top_sencha_plic_peripheral_smc_t;
+
+/**
+ * PLIC Interrupt Source.
+ *
+ * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_sencha_plic_irq_id {
+ kTopSenchaPlicIrqIdNone = 0, /**< No Interrupt */
+ kTopSenchaPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
+ kTopSenchaPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
+ kTopSenchaPlicIrqIdUart0TxEmpty = 3, /**< uart0_tx_empty */
+ kTopSenchaPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
+ kTopSenchaPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
+ kTopSenchaPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
+ kTopSenchaPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
+ kTopSenchaPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
+ kTopSenchaPlicIrqIdUart1TxWatermark = 9, /**< uart1_tx_watermark */
+ kTopSenchaPlicIrqIdUart1RxWatermark = 10, /**< uart1_rx_watermark */
+ kTopSenchaPlicIrqIdUart1TxEmpty = 11, /**< uart1_tx_empty */
+ kTopSenchaPlicIrqIdUart1RxOverflow = 12, /**< uart1_rx_overflow */
+ kTopSenchaPlicIrqIdUart1RxFrameErr = 13, /**< uart1_rx_frame_err */
+ kTopSenchaPlicIrqIdUart1RxBreakErr = 14, /**< uart1_rx_break_err */
+ kTopSenchaPlicIrqIdUart1RxTimeout = 15, /**< uart1_rx_timeout */
+ kTopSenchaPlicIrqIdUart1RxParityErr = 16, /**< uart1_rx_parity_err */
+ kTopSenchaPlicIrqIdUart2TxWatermark = 17, /**< uart2_tx_watermark */
+ kTopSenchaPlicIrqIdUart2RxWatermark = 18, /**< uart2_rx_watermark */
+ kTopSenchaPlicIrqIdUart2TxEmpty = 19, /**< uart2_tx_empty */
+ kTopSenchaPlicIrqIdUart2RxOverflow = 20, /**< uart2_rx_overflow */
+ kTopSenchaPlicIrqIdUart2RxFrameErr = 21, /**< uart2_rx_frame_err */
+ kTopSenchaPlicIrqIdUart2RxBreakErr = 22, /**< uart2_rx_break_err */
+ kTopSenchaPlicIrqIdUart2RxTimeout = 23, /**< uart2_rx_timeout */
+ kTopSenchaPlicIrqIdUart2RxParityErr = 24, /**< uart2_rx_parity_err */
+ kTopSenchaPlicIrqIdUart3TxWatermark = 25, /**< uart3_tx_watermark */
+ kTopSenchaPlicIrqIdUart3RxWatermark = 26, /**< uart3_rx_watermark */
+ kTopSenchaPlicIrqIdUart3TxEmpty = 27, /**< uart3_tx_empty */
+ kTopSenchaPlicIrqIdUart3RxOverflow = 28, /**< uart3_rx_overflow */
+ kTopSenchaPlicIrqIdUart3RxFrameErr = 29, /**< uart3_rx_frame_err */
+ kTopSenchaPlicIrqIdUart3RxBreakErr = 30, /**< uart3_rx_break_err */
+ kTopSenchaPlicIrqIdUart3RxTimeout = 31, /**< uart3_rx_timeout */
+ kTopSenchaPlicIrqIdUart3RxParityErr = 32, /**< uart3_rx_parity_err */
+ kTopSenchaPlicIrqIdGpioGpio0 = 33, /**< gpio_gpio 0 */
+ kTopSenchaPlicIrqIdGpioGpio1 = 34, /**< gpio_gpio 1 */
+ kTopSenchaPlicIrqIdGpioGpio2 = 35, /**< gpio_gpio 2 */
+ kTopSenchaPlicIrqIdGpioGpio3 = 36, /**< gpio_gpio 3 */
+ kTopSenchaPlicIrqIdGpioGpio4 = 37, /**< gpio_gpio 4 */
+ kTopSenchaPlicIrqIdGpioGpio5 = 38, /**< gpio_gpio 5 */
+ kTopSenchaPlicIrqIdGpioGpio6 = 39, /**< gpio_gpio 6 */
+ kTopSenchaPlicIrqIdGpioGpio7 = 40, /**< gpio_gpio 7 */
+ kTopSenchaPlicIrqIdGpioGpio8 = 41, /**< gpio_gpio 8 */
+ kTopSenchaPlicIrqIdGpioGpio9 = 42, /**< gpio_gpio 9 */
+ kTopSenchaPlicIrqIdGpioGpio10 = 43, /**< gpio_gpio 10 */
+ kTopSenchaPlicIrqIdGpioGpio11 = 44, /**< gpio_gpio 11 */
+ kTopSenchaPlicIrqIdGpioGpio12 = 45, /**< gpio_gpio 12 */
+ kTopSenchaPlicIrqIdGpioGpio13 = 46, /**< gpio_gpio 13 */
+ kTopSenchaPlicIrqIdGpioGpio14 = 47, /**< gpio_gpio 14 */
+ kTopSenchaPlicIrqIdGpioGpio15 = 48, /**< gpio_gpio 15 */
+ kTopSenchaPlicIrqIdGpioGpio16 = 49, /**< gpio_gpio 16 */
+ kTopSenchaPlicIrqIdGpioGpio17 = 50, /**< gpio_gpio 17 */
+ kTopSenchaPlicIrqIdGpioGpio18 = 51, /**< gpio_gpio 18 */
+ kTopSenchaPlicIrqIdGpioGpio19 = 52, /**< gpio_gpio 19 */
+ kTopSenchaPlicIrqIdGpioGpio20 = 53, /**< gpio_gpio 20 */
+ kTopSenchaPlicIrqIdGpioGpio21 = 54, /**< gpio_gpio 21 */
+ kTopSenchaPlicIrqIdGpioGpio22 = 55, /**< gpio_gpio 22 */
+ kTopSenchaPlicIrqIdGpioGpio23 = 56, /**< gpio_gpio 23 */
+ kTopSenchaPlicIrqIdGpioGpio24 = 57, /**< gpio_gpio 24 */
+ kTopSenchaPlicIrqIdGpioGpio25 = 58, /**< gpio_gpio 25 */
+ kTopSenchaPlicIrqIdGpioGpio26 = 59, /**< gpio_gpio 26 */
+ kTopSenchaPlicIrqIdGpioGpio27 = 60, /**< gpio_gpio 27 */
+ kTopSenchaPlicIrqIdGpioGpio28 = 61, /**< gpio_gpio 28 */
+ kTopSenchaPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
+ kTopSenchaPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
+ kTopSenchaPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
+ kTopSenchaPlicIrqIdSpiDeviceGenericRxFull = 65, /**< spi_device_generic_rx_full */
+ kTopSenchaPlicIrqIdSpiDeviceGenericRxWatermark = 66, /**< spi_device_generic_rx_watermark */
+ kTopSenchaPlicIrqIdSpiDeviceGenericTxWatermark = 67, /**< spi_device_generic_tx_watermark */
+ kTopSenchaPlicIrqIdSpiDeviceGenericRxError = 68, /**< spi_device_generic_rx_error */
+ kTopSenchaPlicIrqIdSpiDeviceGenericRxOverflow = 69, /**< spi_device_generic_rx_overflow */
+ kTopSenchaPlicIrqIdSpiDeviceGenericTxUnderflow = 70, /**< spi_device_generic_tx_underflow */
+ kTopSenchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 71, /**< spi_device_upload_cmdfifo_not_empty */
+ kTopSenchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 72, /**< spi_device_upload_payload_not_empty */
+ kTopSenchaPlicIrqIdSpiDeviceUploadPayloadOverflow = 73, /**< spi_device_upload_payload_overflow */
+ kTopSenchaPlicIrqIdSpiDeviceReadbufWatermark = 74, /**< spi_device_readbuf_watermark */
+ kTopSenchaPlicIrqIdSpiDeviceReadbufFlip = 75, /**< spi_device_readbuf_flip */
+ kTopSenchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 76, /**< spi_device_tpm_header_not_empty */
+ kTopSenchaPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
+ kTopSenchaPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
+ kTopSenchaPlicIrqIdI2c0FmtOverflow = 79, /**< i2c0_fmt_overflow */
+ kTopSenchaPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
+ kTopSenchaPlicIrqIdI2c0Nak = 81, /**< i2c0_nak */
+ kTopSenchaPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
+ kTopSenchaPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
+ kTopSenchaPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
+ kTopSenchaPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
+ kTopSenchaPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
+ kTopSenchaPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
+ kTopSenchaPlicIrqIdI2c0TxOverflow = 88, /**< i2c0_tx_overflow */
+ kTopSenchaPlicIrqIdI2c0AcqFull = 89, /**< i2c0_acq_full */
+ kTopSenchaPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
+ kTopSenchaPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
+ kTopSenchaPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
+ kTopSenchaPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
+ kTopSenchaPlicIrqIdI2c1FmtOverflow = 94, /**< i2c1_fmt_overflow */
+ kTopSenchaPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
+ kTopSenchaPlicIrqIdI2c1Nak = 96, /**< i2c1_nak */
+ kTopSenchaPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
+ kTopSenchaPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
+ kTopSenchaPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
+ kTopSenchaPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
+ kTopSenchaPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
+ kTopSenchaPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
+ kTopSenchaPlicIrqIdI2c1TxOverflow = 103, /**< i2c1_tx_overflow */
+ kTopSenchaPlicIrqIdI2c1AcqFull = 104, /**< i2c1_acq_full */
+ kTopSenchaPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
+ kTopSenchaPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
+ kTopSenchaPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
+ kTopSenchaPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
+ kTopSenchaPlicIrqIdI2c2FmtOverflow = 109, /**< i2c2_fmt_overflow */
+ kTopSenchaPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
+ kTopSenchaPlicIrqIdI2c2Nak = 111, /**< i2c2_nak */
+ kTopSenchaPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
+ kTopSenchaPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
+ kTopSenchaPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
+ kTopSenchaPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
+ kTopSenchaPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
+ kTopSenchaPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
+ kTopSenchaPlicIrqIdI2c2TxOverflow = 118, /**< i2c2_tx_overflow */
+ kTopSenchaPlicIrqIdI2c2AcqFull = 119, /**< i2c2_acq_full */
+ kTopSenchaPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
+ kTopSenchaPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
+ kTopSenchaPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
+ kTopSenchaPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
+ kTopSenchaPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
+ kTopSenchaPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
+ kTopSenchaPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
+ kTopSenchaPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
+ kTopSenchaPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
+ kTopSenchaPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
+ kTopSenchaPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
+ kTopSenchaPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
+ kTopSenchaPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
+ kTopSenchaPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
+ kTopSenchaPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
+ kTopSenchaPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
+ kTopSenchaPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
+ kTopSenchaPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
+ kTopSenchaPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
+ kTopSenchaPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
+ kTopSenchaPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
+ kTopSenchaPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
+ kTopSenchaPlicIrqIdUsbdevAvEmpty = 142, /**< usbdev_av_empty */
+ kTopSenchaPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
+ kTopSenchaPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
+ kTopSenchaPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
+ kTopSenchaPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
+ kTopSenchaPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
+ kTopSenchaPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
+ kTopSenchaPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
+ kTopSenchaPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
+ kTopSenchaPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
+ kTopSenchaPlicIrqIdPwrmgrAonWakeup = 152, /**< pwrmgr_aon_wakeup */
+ kTopSenchaPlicIrqIdSysrstCtrlAonEventDetected = 153, /**< sysrst_ctrl_aon_event_detected */
+ kTopSenchaPlicIrqIdAdcCtrlAonMatchDone = 154, /**< adc_ctrl_aon_match_done */
+ kTopSenchaPlicIrqIdAonTimerAonWkupTimerExpired = 155, /**< aon_timer_aon_wkup_timer_expired */
+ kTopSenchaPlicIrqIdAonTimerAonWdogTimerBark = 156, /**< aon_timer_aon_wdog_timer_bark */
+ kTopSenchaPlicIrqIdSensorCtrlIoStatusChange = 157, /**< sensor_ctrl_io_status_change */
+ kTopSenchaPlicIrqIdSensorCtrlInitStatusChange = 158, /**< sensor_ctrl_init_status_change */
+ kTopSenchaPlicIrqIdFlashCtrlProgEmpty = 159, /**< flash_ctrl_prog_empty */
+ kTopSenchaPlicIrqIdFlashCtrlProgLvl = 160, /**< flash_ctrl_prog_lvl */
+ kTopSenchaPlicIrqIdFlashCtrlRdFull = 161, /**< flash_ctrl_rd_full */
+ kTopSenchaPlicIrqIdFlashCtrlRdLvl = 162, /**< flash_ctrl_rd_lvl */
+ kTopSenchaPlicIrqIdFlashCtrlOpDone = 163, /**< flash_ctrl_op_done */
+ kTopSenchaPlicIrqIdFlashCtrlCorrErr = 164, /**< flash_ctrl_corr_err */
+ kTopSenchaPlicIrqIdHmacHmacDone = 165, /**< hmac_hmac_done */
+ kTopSenchaPlicIrqIdHmacFifoEmpty = 166, /**< hmac_fifo_empty */
+ kTopSenchaPlicIrqIdHmacHmacErr = 167, /**< hmac_hmac_err */
+ kTopSenchaPlicIrqIdKmacKmacDone = 168, /**< kmac_kmac_done */
+ kTopSenchaPlicIrqIdKmacFifoEmpty = 169, /**< kmac_fifo_empty */
+ kTopSenchaPlicIrqIdKmacKmacErr = 170, /**< kmac_kmac_err */
+ kTopSenchaPlicIrqIdOtbnDone = 171, /**< otbn_done */
+ kTopSenchaPlicIrqIdKeymgrOpDone = 172, /**< keymgr_op_done */
+ kTopSenchaPlicIrqIdCsrngCsCmdReqDone = 173, /**< csrng_cs_cmd_req_done */
+ kTopSenchaPlicIrqIdCsrngCsEntropyReq = 174, /**< csrng_cs_entropy_req */
+ kTopSenchaPlicIrqIdCsrngCsHwInstExc = 175, /**< csrng_cs_hw_inst_exc */
+ kTopSenchaPlicIrqIdCsrngCsFatalErr = 176, /**< csrng_cs_fatal_err */
+ kTopSenchaPlicIrqIdEntropySrcEsEntropyValid = 177, /**< entropy_src_es_entropy_valid */
+ kTopSenchaPlicIrqIdEntropySrcEsHealthTestFailed = 178, /**< entropy_src_es_health_test_failed */
+ kTopSenchaPlicIrqIdEntropySrcEsObserveFifoReady = 179, /**< entropy_src_es_observe_fifo_ready */
+ kTopSenchaPlicIrqIdEntropySrcEsFatalErr = 180, /**< entropy_src_es_fatal_err */
+ kTopSenchaPlicIrqIdEdn0EdnCmdReqDone = 181, /**< edn0_edn_cmd_req_done */
+ kTopSenchaPlicIrqIdEdn0EdnFatalErr = 182, /**< edn0_edn_fatal_err */
+ kTopSenchaPlicIrqIdEdn1EdnCmdReqDone = 183, /**< edn1_edn_cmd_req_done */
+ kTopSenchaPlicIrqIdEdn1EdnFatalErr = 184, /**< edn1_edn_fatal_err */
+ kTopSenchaPlicIrqIdDma0WriterDone = 185, /**< dma0_writer_done */
+ kTopSenchaPlicIrqIdDma0ReaderDone = 186, /**< dma0_reader_done */
+ kTopSenchaPlicIrqIdTlulMailboxSecWtirq = 187, /**< tlul_mailbox_sec_wtirq */
+ kTopSenchaPlicIrqIdTlulMailboxSecRtirq = 188, /**< tlul_mailbox_sec_rtirq */
+ kTopSenchaPlicIrqIdTlulMailboxSecEirq = 189, /**< tlul_mailbox_sec_eirq */
+ kTopSenchaPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */
+} top_sencha_plic_irq_id_t;
+
+typedef enum top_sencha_plic_irq_id_smc {
+ kTopSenchaPlicIrqIdNoneSmc = 0, /**< No Interrupt */
+ kTopSenchaPlicIrqIdSmcUartTxWatermark = 1, /**< smc_uart_tx_watermark */
+ kTopSenchaPlicIrqIdSmcUartRxWatermark = 2, /**< smc_uart_rx_watermark */
+ kTopSenchaPlicIrqIdSmcUartTxEmpty = 3, /**< smc_uart_tx_empty */
+ kTopSenchaPlicIrqIdSmcUartRxOverflow = 4, /**< smc_uart_rx_overflow */
+ kTopSenchaPlicIrqIdSmcUartRxFrameErr = 5, /**< smc_uart_rx_frame_err */
+ kTopSenchaPlicIrqIdSmcUartRxBreakErr = 6, /**< smc_uart_rx_break_err */
+ kTopSenchaPlicIrqIdSmcUartRxTimeout = 7, /**< smc_uart_rx_timeout */
+ kTopSenchaPlicIrqIdSmcUartRxParityErr = 8, /**< smc_uart_rx_parity_err */
+ kTopSenchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0 = 9, /**< rv_timer_smc_timer_expired_hart0_timer0 */
+ kTopSenchaPlicIrqIdCamI2cFmtThreshold = 10, /**< cam_i2c_fmt_threshold */
+ kTopSenchaPlicIrqIdCamI2cRxThreshold = 11, /**< cam_i2c_rx_threshold */
+ kTopSenchaPlicIrqIdCamI2cFmtOverflow = 12, /**< cam_i2c_fmt_overflow */
+ kTopSenchaPlicIrqIdCamI2cRxOverflow = 13, /**< cam_i2c_rx_overflow */
+ kTopSenchaPlicIrqIdCamI2cNak = 14, /**< cam_i2c_nak */
+ kTopSenchaPlicIrqIdCamI2cSclInterference = 15, /**< cam_i2c_scl_interference */
+ kTopSenchaPlicIrqIdCamI2cSdaInterference = 16, /**< cam_i2c_sda_interference */
+ kTopSenchaPlicIrqIdCamI2cStretchTimeout = 17, /**< cam_i2c_stretch_timeout */
+ kTopSenchaPlicIrqIdCamI2cSdaUnstable = 18, /**< cam_i2c_sda_unstable */
+ kTopSenchaPlicIrqIdCamI2cCmdComplete = 19, /**< cam_i2c_cmd_complete */
+ kTopSenchaPlicIrqIdCamI2cTxStretch = 20, /**< cam_i2c_tx_stretch */
+ kTopSenchaPlicIrqIdCamI2cTxOverflow = 21, /**< cam_i2c_tx_overflow */
+ kTopSenchaPlicIrqIdCamI2cAcqFull = 22, /**< cam_i2c_acq_full */
+ kTopSenchaPlicIrqIdCamI2cUnexpStop = 23, /**< cam_i2c_unexp_stop */
+ kTopSenchaPlicIrqIdCamI2cHostTimeout = 24, /**< cam_i2c_host_timeout */
+ kTopSenchaPlicIrqIdCamCtrlCamMotionDetect = 25, /**< cam_ctrl_cam_motion_detect */
+ kTopSenchaPlicIrqIdIspWrapperIsp = 26, /**< isp_wrapper_isp */
+ kTopSenchaPlicIrqIdIspWrapperMi = 27, /**< isp_wrapper_mi */
+ kTopSenchaPlicIrqIdDmaSmcWriterDone = 28, /**< dma_smc_writer_done */
+ kTopSenchaPlicIrqIdDmaSmcReaderDone = 29, /**< dma_smc_reader_done */
+ kTopSenchaPlicIrqIdTlulMailboxSmcWtirq = 30, /**< tlul_mailbox_smc_wtirq */
+ kTopSenchaPlicIrqIdTlulMailboxSmcRtirq = 31, /**< tlul_mailbox_smc_rtirq */
+ kTopSenchaPlicIrqIdTlulMailboxSmcEirq = 32, /**< tlul_mailbox_smc_eirq */
+ kTopSenchaPlicIrqIdMlTopHostReq = 33, /**< ml_top_host_req */
+ kTopSenchaPlicIrqIdMlTopFinish = 34, /**< ml_top_finish */
+ kTopSenchaPlicIrqIdMlTopFault = 35, /**< ml_top_fault */
+ kTopSenchaPlicIrqIdSpiHost2Error = 36, /**< spi_host2_error */
+ kTopSenchaPlicIrqIdSpiHost2SpiEvent = 37, /**< spi_host2_spi_event */
+ kTopSenchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 38, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+ kTopSenchaPlicIrqIdI2s0TxWatermark = 39, /**< i2s0_tx_watermark */
+ kTopSenchaPlicIrqIdI2s0RxWatermark = 40, /**< i2s0_rx_watermark */
+ kTopSenchaPlicIrqIdI2s0TxEmpty = 41, /**< i2s0_tx_empty */
+ kTopSenchaPlicIrqIdI2s0RxOverflow = 42, /**< i2s0_rx_overflow */
+ kTopSenchaPlicIrqIdLastSmc = 42, /**< \internal The Last Valid Interrupt ID. */
+} top_sencha_plic_irq_id_smc_t;
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_plic_irq_id_t` to
+ * `top_sencha_plic_peripheral_t`.
+ */
+extern const top_sencha_plic_peripheral_t
+ top_sencha_plic_interrupt_for_peripheral[190];
+
+extern const top_sencha_plic_peripheral_smc_t
+ top_sencha_plic_interrupt_for_peripheral_smc[43];
+
+/**
+ * PLIC Interrupt Target.
+ *
+ * Enumeration used to determine which set of IE, CC, threshold registers to
+ * access for a given interrupt target.
+ */
+typedef enum top_sencha_plic_target {
+ kTopSenchaPlicTargetIbex0 = 0, /**< Ibex Core 0 */
+ kTopSenchaPlicTargetIbex1 = 1, /**< Ibex Core 1 */
+ kTopSenchaPlicTargetLast = 1, /**< \internal Final PLIC target */
+} top_sencha_plic_target_t;
+
+typedef enum top_sencha_plic_target_smc {
+ kTopSenchaPlicTargetIbex0Smc = 0, /**< Ibex Core 0 */
+ kTopSenchaPlicTargetLastSmc = 0, /**< \internal Final PLIC target */
+} top_sencha_plic_target_smc_t;
+
+/**
+ * Alert Handler Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * alert.
+ */
+typedef enum top_sencha_alert_peripheral {
+ kTopSenchaAlertPeripheralUart0 = 0, /**< uart0 */
+ kTopSenchaAlertPeripheralUart1 = 1, /**< uart1 */
+ kTopSenchaAlertPeripheralUart2 = 2, /**< uart2 */
+ kTopSenchaAlertPeripheralUart3 = 3, /**< uart3 */
+ kTopSenchaAlertPeripheralGpio = 4, /**< gpio */
+ kTopSenchaAlertPeripheralSpiDevice = 5, /**< spi_device */
+ kTopSenchaAlertPeripheralI2c0 = 6, /**< i2c0 */
+ kTopSenchaAlertPeripheralI2c1 = 7, /**< i2c1 */
+ kTopSenchaAlertPeripheralI2c2 = 8, /**< i2c2 */
+ kTopSenchaAlertPeripheralPattgen = 9, /**< pattgen */
+ kTopSenchaAlertPeripheralRvTimer = 10, /**< rv_timer */
+ kTopSenchaAlertPeripheralOtpCtrl = 11, /**< otp_ctrl */
+ kTopSenchaAlertPeripheralLcCtrl = 12, /**< lc_ctrl */
+ kTopSenchaAlertPeripheralSpiHost0 = 13, /**< spi_host0 */
+ kTopSenchaAlertPeripheralSpiHost1 = 14, /**< spi_host1 */
+ kTopSenchaAlertPeripheralUsbdev = 15, /**< usbdev */
+ kTopSenchaAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
+ kTopSenchaAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */
+ kTopSenchaAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */
+ kTopSenchaAlertPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */
+ kTopSenchaAlertPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */
+ kTopSenchaAlertPeripheralPwmAon = 21, /**< pwm_aon */
+ kTopSenchaAlertPeripheralPinmuxAon = 22, /**< pinmux_aon */
+ kTopSenchaAlertPeripheralAonTimerAon = 23, /**< aon_timer_aon */
+ kTopSenchaAlertPeripheralSensorCtrl = 24, /**< sensor_ctrl */
+ kTopSenchaAlertPeripheralSramCtrlRetAon = 25, /**< sram_ctrl_ret_aon */
+ kTopSenchaAlertPeripheralFlashCtrl = 26, /**< flash_ctrl */
+ kTopSenchaAlertPeripheralRvDm = 27, /**< rv_dm */
+ kTopSenchaAlertPeripheralRvPlic = 28, /**< rv_plic */
+ kTopSenchaAlertPeripheralAes = 29, /**< aes */
+ kTopSenchaAlertPeripheralHmac = 30, /**< hmac */
+ kTopSenchaAlertPeripheralKmac = 31, /**< kmac */
+ kTopSenchaAlertPeripheralOtbn = 32, /**< otbn */
+ kTopSenchaAlertPeripheralKeymgr = 33, /**< keymgr */
+ kTopSenchaAlertPeripheralCsrng = 34, /**< csrng */
+ kTopSenchaAlertPeripheralEntropySrc = 35, /**< entropy_src */
+ kTopSenchaAlertPeripheralEdn0 = 36, /**< edn0 */
+ kTopSenchaAlertPeripheralEdn1 = 37, /**< edn1 */
+ kTopSenchaAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */
+ kTopSenchaAlertPeripheralRomCtrl = 39, /**< rom_ctrl */
+ kTopSenchaAlertPeripheralRvCoreIbexSec = 40, /**< rv_core_ibex_sec */
+ kTopSenchaAlertPeripheralSmcUart = 41, /**< smc_uart */
+ kTopSenchaAlertPeripheralRvTimerSmc = 42, /**< rv_timer_smc */
+ kTopSenchaAlertPeripheralCamI2c = 43, /**< cam_i2c */
+ kTopSenchaAlertPeripheralRvPlicSmc = 44, /**< rv_plic_smc */
+ kTopSenchaAlertPeripheralSpiHost2 = 45, /**< spi_host2 */
+ kTopSenchaAlertPeripheralRvTimerSmc2 = 46, /**< rv_timer_smc2 */
+ kTopSenchaAlertPeripheralRvCoreIbexSmc = 47, /**< rv_core_ibex_smc */
+ kTopSenchaAlertPeripheralLast = 47, /**< \internal Final Alert peripheral */
+} top_sencha_alert_peripheral_t;
+
+/**
+ * Alert Handler Alert Source.
+ *
+ * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_sencha_alert_id {
+ kTopSenchaAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
+ kTopSenchaAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
+ kTopSenchaAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
+ kTopSenchaAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
+ kTopSenchaAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
+ kTopSenchaAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
+ kTopSenchaAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
+ kTopSenchaAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
+ kTopSenchaAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
+ kTopSenchaAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
+ kTopSenchaAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
+ kTopSenchaAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
+ kTopSenchaAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
+ kTopSenchaAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
+ kTopSenchaAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
+ kTopSenchaAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
+ kTopSenchaAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
+ kTopSenchaAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
+ kTopSenchaAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopSenchaAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
+ kTopSenchaAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
+ kTopSenchaAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
+ kTopSenchaAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
+ kTopSenchaAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
+ kTopSenchaAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
+ kTopSenchaAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
+ kTopSenchaAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
+ kTopSenchaAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
+ kTopSenchaAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
+ kTopSenchaAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
+ kTopSenchaAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
+ kTopSenchaAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
+ kTopSenchaAlertIdSensorCtrlRecovAlert = 32, /**< sensor_ctrl_recov_alert */
+ kTopSenchaAlertIdSensorCtrlFatalAlert = 33, /**< sensor_ctrl_fatal_alert */
+ kTopSenchaAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
+ kTopSenchaAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
+ kTopSenchaAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
+ kTopSenchaAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
+ kTopSenchaAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
+ kTopSenchaAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
+ kTopSenchaAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
+ kTopSenchaAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
+ kTopSenchaAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
+ kTopSenchaAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
+ kTopSenchaAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
+ kTopSenchaAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
+ kTopSenchaAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
+ kTopSenchaAlertIdOtbnFatal = 47, /**< otbn_fatal */
+ kTopSenchaAlertIdOtbnRecov = 48, /**< otbn_recov */
+ kTopSenchaAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
+ kTopSenchaAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
+ kTopSenchaAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
+ kTopSenchaAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
+ kTopSenchaAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
+ kTopSenchaAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
+ kTopSenchaAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
+ kTopSenchaAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
+ kTopSenchaAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
+ kTopSenchaAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
+ kTopSenchaAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
+ kTopSenchaAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
+ kTopSenchaAlertIdRvCoreIbexSecFatalSwErr = 61, /**< rv_core_ibex_sec_fatal_sw_err */
+ kTopSenchaAlertIdRvCoreIbexSecRecovSwErr = 62, /**< rv_core_ibex_sec_recov_sw_err */
+ kTopSenchaAlertIdRvCoreIbexSecFatalHwErr = 63, /**< rv_core_ibex_sec_fatal_hw_err */
+ kTopSenchaAlertIdRvCoreIbexSecRecovHwErr = 64, /**< rv_core_ibex_sec_recov_hw_err */
+ kTopSenchaAlertIdSmcUartFatalFault = 65, /**< smc_uart_fatal_fault */
+ kTopSenchaAlertIdRvTimerSmcFatalFault = 66, /**< rv_timer_smc_fatal_fault */
+ kTopSenchaAlertIdCamI2cFatalFault = 67, /**< cam_i2c_fatal_fault */
+ kTopSenchaAlertIdRvPlicSmcFatalFault = 68, /**< rv_plic_smc_fatal_fault */
+ kTopSenchaAlertIdSpiHost2FatalFault = 69, /**< spi_host2_fatal_fault */
+ kTopSenchaAlertIdRvTimerSmc2FatalFault = 70, /**< rv_timer_smc2_fatal_fault */
+ kTopSenchaAlertIdRvCoreIbexSmcFatalSwErr = 71, /**< rv_core_ibex_smc_fatal_sw_err */
+ kTopSenchaAlertIdRvCoreIbexSmcRecovSwErr = 72, /**< rv_core_ibex_smc_recov_sw_err */
+ kTopSenchaAlertIdRvCoreIbexSmcFatalHwErr = 73, /**< rv_core_ibex_smc_fatal_hw_err */
+ kTopSenchaAlertIdRvCoreIbexSmcRecovHwErr = 74, /**< rv_core_ibex_smc_recov_hw_err */
+ kTopSenchaAlertIdLast = 74, /**< \internal The Last Valid Alert ID. */
+} top_sencha_alert_id_t;
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_sencha_alert_id_t` to
+ * `top_sencha_alert_peripheral_t`.
+ */
+extern const top_sencha_alert_peripheral_t
+ top_sencha_alert_for_peripheral[75];
+
+#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
+// 0 and 1 are tied to value 0 and 1
+#define NUM_MIO_PADS 53
+#define NUM_DIO_PADS 16
+
+#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
+
+/**
+ * Pinmux Peripheral Input.
+ */
+typedef enum top_sencha_pinmux_peripheral_in {
+ kTopSenchaPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
+ kTopSenchaPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
+ kTopSenchaPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
+ kTopSenchaPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
+ kTopSenchaPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
+ kTopSenchaPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
+ kTopSenchaPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
+ kTopSenchaPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
+ kTopSenchaPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
+ kTopSenchaPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
+ kTopSenchaPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
+ kTopSenchaPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
+ kTopSenchaPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
+ kTopSenchaPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
+ kTopSenchaPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
+ kTopSenchaPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
+ kTopSenchaPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
+ kTopSenchaPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
+ kTopSenchaPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
+ kTopSenchaPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
+ kTopSenchaPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
+ kTopSenchaPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
+ kTopSenchaPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
+ kTopSenchaPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
+ kTopSenchaPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
+ kTopSenchaPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
+ kTopSenchaPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
+ kTopSenchaPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
+ kTopSenchaPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
+ kTopSenchaPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
+ kTopSenchaPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
+ kTopSenchaPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
+ kTopSenchaPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
+ kTopSenchaPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
+ kTopSenchaPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
+ kTopSenchaPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
+ kTopSenchaPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
+ kTopSenchaPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
+ kTopSenchaPinmuxPeripheralInCamI2cSda = 38, /**< Peripheral Input 38 */
+ kTopSenchaPinmuxPeripheralInCamI2cScl = 39, /**< Peripheral Input 39 */
+ kTopSenchaPinmuxPeripheralInSpiHost1Sd0 = 40, /**< Peripheral Input 40 */
+ kTopSenchaPinmuxPeripheralInSpiHost1Sd1 = 41, /**< Peripheral Input 41 */
+ kTopSenchaPinmuxPeripheralInSpiHost1Sd2 = 42, /**< Peripheral Input 42 */
+ kTopSenchaPinmuxPeripheralInSpiHost1Sd3 = 43, /**< Peripheral Input 43 */
+ kTopSenchaPinmuxPeripheralInSpiHost2Sd0 = 44, /**< Peripheral Input 44 */
+ kTopSenchaPinmuxPeripheralInSpiHost2Sd1 = 45, /**< Peripheral Input 45 */
+ kTopSenchaPinmuxPeripheralInSpiHost2Sd2 = 46, /**< Peripheral Input 46 */
+ kTopSenchaPinmuxPeripheralInSpiHost2Sd3 = 47, /**< Peripheral Input 47 */
+ kTopSenchaPinmuxPeripheralInUart0Rx = 48, /**< Peripheral Input 48 */
+ kTopSenchaPinmuxPeripheralInUart1Rx = 49, /**< Peripheral Input 49 */
+ kTopSenchaPinmuxPeripheralInUart2Rx = 50, /**< Peripheral Input 50 */
+ kTopSenchaPinmuxPeripheralInSmcUartRx = 51, /**< Peripheral Input 51 */
+ kTopSenchaPinmuxPeripheralInCamCtrlCamInt = 52, /**< Peripheral Input 52 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSPclk = 53, /**< Peripheral Input 53 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData0 = 54, /**< Peripheral Input 54 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData1 = 55, /**< Peripheral Input 55 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData2 = 56, /**< Peripheral Input 56 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData3 = 57, /**< Peripheral Input 57 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData4 = 58, /**< Peripheral Input 58 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData5 = 59, /**< Peripheral Input 59 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData6 = 60, /**< Peripheral Input 60 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSData7 = 61, /**< Peripheral Input 61 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSHsync = 62, /**< Peripheral Input 62 */
+ kTopSenchaPinmuxPeripheralInIspWrapperSVsync = 63, /**< Peripheral Input 63 */
+ kTopSenchaPinmuxPeripheralInI2s0RxSd = 64, /**< Peripheral Input 64 */
+ kTopSenchaPinmuxPeripheralInSpiDeviceTpmCsb = 65, /**< Peripheral Input 65 */
+ kTopSenchaPinmuxPeripheralInFlashCtrlTck = 66, /**< Peripheral Input 66 */
+ kTopSenchaPinmuxPeripheralInFlashCtrlTms = 67, /**< Peripheral Input 67 */
+ kTopSenchaPinmuxPeripheralInFlashCtrlTdi = 68, /**< Peripheral Input 68 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 69, /**< Peripheral Input 69 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey0In = 70, /**< Peripheral Input 70 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey1In = 71, /**< Peripheral Input 71 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonKey2In = 72, /**< Peripheral Input 72 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 73, /**< Peripheral Input 73 */
+ kTopSenchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 74, /**< Peripheral Input 74 */
+ kTopSenchaPinmuxPeripheralInUsbdevSense = 75, /**< Peripheral Input 75 */
+ kTopSenchaPinmuxPeripheralInLast = 75, /**< \internal Last valid peripheral input */
+} top_sencha_pinmux_peripheral_in_t;
+
+/**
+ * Pinmux MIO Input Selector.
+ */
+typedef enum top_sencha_pinmux_insel {
+ kTopSenchaPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
+ kTopSenchaPinmuxInselConstantOne = 1, /**< Tie constantly to one */
+ kTopSenchaPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
+ kTopSenchaPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
+ kTopSenchaPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
+ kTopSenchaPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
+ kTopSenchaPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
+ kTopSenchaPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
+ kTopSenchaPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
+ kTopSenchaPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
+ kTopSenchaPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
+ kTopSenchaPinmuxInselIob0 = 11, /**< MIO Pad 9 */
+ kTopSenchaPinmuxInselIob1 = 12, /**< MIO Pad 10 */
+ kTopSenchaPinmuxInselIob2 = 13, /**< MIO Pad 11 */
+ kTopSenchaPinmuxInselIob3 = 14, /**< MIO Pad 12 */
+ kTopSenchaPinmuxInselIob4 = 15, /**< MIO Pad 13 */
+ kTopSenchaPinmuxInselIob5 = 16, /**< MIO Pad 14 */
+ kTopSenchaPinmuxInselIob6 = 17, /**< MIO Pad 15 */
+ kTopSenchaPinmuxInselIob7 = 18, /**< MIO Pad 16 */
+ kTopSenchaPinmuxInselIob8 = 19, /**< MIO Pad 17 */
+ kTopSenchaPinmuxInselIob9 = 20, /**< MIO Pad 18 */
+ kTopSenchaPinmuxInselIob10 = 21, /**< MIO Pad 19 */
+ kTopSenchaPinmuxInselIob11 = 22, /**< MIO Pad 20 */
+ kTopSenchaPinmuxInselIob12 = 23, /**< MIO Pad 21 */
+ kTopSenchaPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
+ kTopSenchaPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
+ kTopSenchaPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
+ kTopSenchaPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
+ kTopSenchaPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
+ kTopSenchaPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
+ kTopSenchaPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
+ kTopSenchaPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
+ kTopSenchaPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
+ kTopSenchaPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
+ kTopSenchaPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
+ kTopSenchaPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
+ kTopSenchaPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
+ kTopSenchaPinmuxInselIor0 = 37, /**< MIO Pad 35 */
+ kTopSenchaPinmuxInselIor1 = 38, /**< MIO Pad 36 */
+ kTopSenchaPinmuxInselIor2 = 39, /**< MIO Pad 37 */
+ kTopSenchaPinmuxInselIor3 = 40, /**< MIO Pad 38 */
+ kTopSenchaPinmuxInselIor4 = 41, /**< MIO Pad 39 */
+ kTopSenchaPinmuxInselIor5 = 42, /**< MIO Pad 40 */
+ kTopSenchaPinmuxInselIor6 = 43, /**< MIO Pad 41 */
+ kTopSenchaPinmuxInselIor7 = 44, /**< MIO Pad 42 */
+ kTopSenchaPinmuxInselIor10 = 45, /**< MIO Pad 43 */
+ kTopSenchaPinmuxInselIor11 = 46, /**< MIO Pad 44 */
+ kTopSenchaPinmuxInselIor12 = 47, /**< MIO Pad 45 */
+ kTopSenchaPinmuxInselIor13 = 48, /**< MIO Pad 46 */
+ kTopSenchaPinmuxInselIod0 = 49, /**< MIO Pad 47 */
+ kTopSenchaPinmuxInselIod1 = 50, /**< MIO Pad 48 */
+ kTopSenchaPinmuxInselIod2 = 51, /**< MIO Pad 49 */
+ kTopSenchaPinmuxInselIod3 = 52, /**< MIO Pad 50 */
+ kTopSenchaPinmuxInselIod4 = 53, /**< MIO Pad 51 */
+ kTopSenchaPinmuxInselIod5 = 54, /**< MIO Pad 52 */
+ kTopSenchaPinmuxInselLast = 54, /**< \internal Last valid insel value */
+} top_sencha_pinmux_insel_t;
+
+/**
+ * Pinmux MIO Output.
+ */
+typedef enum top_sencha_pinmux_mio_out {
+ kTopSenchaPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
+ kTopSenchaPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
+ kTopSenchaPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
+ kTopSenchaPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
+ kTopSenchaPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
+ kTopSenchaPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
+ kTopSenchaPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
+ kTopSenchaPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
+ kTopSenchaPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
+ kTopSenchaPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
+ kTopSenchaPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
+ kTopSenchaPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
+ kTopSenchaPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
+ kTopSenchaPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
+ kTopSenchaPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
+ kTopSenchaPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
+ kTopSenchaPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
+ kTopSenchaPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
+ kTopSenchaPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
+ kTopSenchaPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
+ kTopSenchaPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
+ kTopSenchaPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
+ kTopSenchaPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
+ kTopSenchaPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
+ kTopSenchaPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
+ kTopSenchaPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
+ kTopSenchaPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
+ kTopSenchaPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
+ kTopSenchaPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
+ kTopSenchaPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
+ kTopSenchaPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
+ kTopSenchaPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
+ kTopSenchaPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
+ kTopSenchaPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
+ kTopSenchaPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
+ kTopSenchaPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
+ kTopSenchaPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
+ kTopSenchaPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
+ kTopSenchaPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
+ kTopSenchaPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
+ kTopSenchaPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
+ kTopSenchaPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
+ kTopSenchaPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
+ kTopSenchaPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
+ kTopSenchaPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
+ kTopSenchaPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
+ kTopSenchaPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
+ kTopSenchaPinmuxMioOutIod0 = 47, /**< MIO Pad 47 */
+ kTopSenchaPinmuxMioOutIod1 = 48, /**< MIO Pad 48 */
+ kTopSenchaPinmuxMioOutIod2 = 49, /**< MIO Pad 49 */
+ kTopSenchaPinmuxMioOutIod3 = 50, /**< MIO Pad 50 */
+ kTopSenchaPinmuxMioOutIod4 = 51, /**< MIO Pad 51 */
+ kTopSenchaPinmuxMioOutIod5 = 52, /**< MIO Pad 52 */
+ kTopSenchaPinmuxMioOutLast = 52, /**< \internal Last valid mio output */
+} top_sencha_pinmux_mio_out_t;
+
+/**
+ * Pinmux Peripheral Output Selector.
+ */
+typedef enum top_sencha_pinmux_outsel {
+ kTopSenchaPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
+ kTopSenchaPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
+ kTopSenchaPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
+ kTopSenchaPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
+ kTopSenchaPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
+ kTopSenchaPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
+ kTopSenchaPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
+ kTopSenchaPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
+ kTopSenchaPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
+ kTopSenchaPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
+ kTopSenchaPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
+ kTopSenchaPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
+ kTopSenchaPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
+ kTopSenchaPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
+ kTopSenchaPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
+ kTopSenchaPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
+ kTopSenchaPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
+ kTopSenchaPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
+ kTopSenchaPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
+ kTopSenchaPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
+ kTopSenchaPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
+ kTopSenchaPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
+ kTopSenchaPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
+ kTopSenchaPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
+ kTopSenchaPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
+ kTopSenchaPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
+ kTopSenchaPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
+ kTopSenchaPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
+ kTopSenchaPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
+ kTopSenchaPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
+ kTopSenchaPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
+ kTopSenchaPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
+ kTopSenchaPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
+ kTopSenchaPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
+ kTopSenchaPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
+ kTopSenchaPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
+ kTopSenchaPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
+ kTopSenchaPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
+ kTopSenchaPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
+ kTopSenchaPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
+ kTopSenchaPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
+ kTopSenchaPinmuxOutselCamI2cSda = 41, /**< Peripheral Output 38 */
+ kTopSenchaPinmuxOutselCamI2cScl = 42, /**< Peripheral Output 39 */
+ kTopSenchaPinmuxOutselSpiHost1Sd0 = 43, /**< Peripheral Output 40 */
+ kTopSenchaPinmuxOutselSpiHost1Sd1 = 44, /**< Peripheral Output 41 */
+ kTopSenchaPinmuxOutselSpiHost1Sd2 = 45, /**< Peripheral Output 42 */
+ kTopSenchaPinmuxOutselSpiHost1Sd3 = 46, /**< Peripheral Output 43 */
+ kTopSenchaPinmuxOutselSpiHost2Sd0 = 47, /**< Peripheral Output 44 */
+ kTopSenchaPinmuxOutselSpiHost2Sd1 = 48, /**< Peripheral Output 45 */
+ kTopSenchaPinmuxOutselSpiHost2Sd2 = 49, /**< Peripheral Output 46 */
+ kTopSenchaPinmuxOutselSpiHost2Sd3 = 50, /**< Peripheral Output 47 */
+ kTopSenchaPinmuxOutselUart0Tx = 51, /**< Peripheral Output 48 */
+ kTopSenchaPinmuxOutselUart1Tx = 52, /**< Peripheral Output 49 */
+ kTopSenchaPinmuxOutselUart2Tx = 53, /**< Peripheral Output 50 */
+ kTopSenchaPinmuxOutselSmcUartTx = 54, /**< Peripheral Output 51 */
+ kTopSenchaPinmuxOutselCamCtrlCamTrig = 55, /**< Peripheral Output 52 */
+ kTopSenchaPinmuxOutselI2s0RxSclk = 56, /**< Peripheral Output 53 */
+ kTopSenchaPinmuxOutselI2s0RxWs = 57, /**< Peripheral Output 54 */
+ kTopSenchaPinmuxOutselI2s0TxSclk = 58, /**< Peripheral Output 55 */
+ kTopSenchaPinmuxOutselI2s0TxWs = 59, /**< Peripheral Output 56 */
+ kTopSenchaPinmuxOutselI2s0TxSd = 60, /**< Peripheral Output 57 */
+ kTopSenchaPinmuxOutselPattgenPda0Tx = 61, /**< Peripheral Output 58 */
+ kTopSenchaPinmuxOutselPattgenPcl0Tx = 62, /**< Peripheral Output 59 */
+ kTopSenchaPinmuxOutselPattgenPda1Tx = 63, /**< Peripheral Output 60 */
+ kTopSenchaPinmuxOutselPattgenPcl1Tx = 64, /**< Peripheral Output 61 */
+ kTopSenchaPinmuxOutselSpiHost1Sck = 65, /**< Peripheral Output 62 */
+ kTopSenchaPinmuxOutselSpiHost1Csb = 66, /**< Peripheral Output 63 */
+ kTopSenchaPinmuxOutselSpiHost2Sck = 67, /**< Peripheral Output 64 */
+ kTopSenchaPinmuxOutselSpiHost2Csb = 68, /**< Peripheral Output 65 */
+ kTopSenchaPinmuxOutselFlashCtrlTdo = 69, /**< Peripheral Output 66 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut0 = 70, /**< Peripheral Output 67 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut1 = 71, /**< Peripheral Output 68 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut2 = 72, /**< Peripheral Output 69 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut3 = 73, /**< Peripheral Output 70 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut4 = 74, /**< Peripheral Output 71 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut5 = 75, /**< Peripheral Output 72 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut6 = 76, /**< Peripheral Output 73 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut7 = 77, /**< Peripheral Output 74 */
+ kTopSenchaPinmuxOutselSensorCtrlAstDebugOut8 = 78, /**< Peripheral Output 75 */
+ kTopSenchaPinmuxOutselPwmAonPwm0 = 79, /**< Peripheral Output 76 */
+ kTopSenchaPinmuxOutselPwmAonPwm1 = 80, /**< Peripheral Output 77 */
+ kTopSenchaPinmuxOutselPwmAonPwm2 = 81, /**< Peripheral Output 78 */
+ kTopSenchaPinmuxOutselPwmAonPwm3 = 82, /**< Peripheral Output 79 */
+ kTopSenchaPinmuxOutselPwmAonPwm4 = 83, /**< Peripheral Output 80 */
+ kTopSenchaPinmuxOutselPwmAonPwm5 = 84, /**< Peripheral Output 81 */
+ kTopSenchaPinmuxOutselOtpCtrlTest0 = 85, /**< Peripheral Output 82 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonBatDisable = 86, /**< Peripheral Output 83 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonKey0Out = 87, /**< Peripheral Output 84 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonKey1Out = 88, /**< Peripheral Output 85 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonKey2Out = 89, /**< Peripheral Output 86 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonPwrbOut = 90, /**< Peripheral Output 87 */
+ kTopSenchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 91, /**< Peripheral Output 88 */
+ kTopSenchaPinmuxOutselLast = 91, /**< \internal Last valid outsel value */
+} top_sencha_pinmux_outsel_t;
+
+/**
+ * Dedicated Pad Selects
+ */
+typedef enum top_sencha_direct_pads {
+ kTopSenchaDirectPadsUsbdevUsbDp = 0, /**< */
+ kTopSenchaDirectPadsUsbdevUsbDn = 1, /**< */
+ kTopSenchaDirectPadsSpiHost0Sd0 = 2, /**< */
+ kTopSenchaDirectPadsSpiHost0Sd1 = 3, /**< */
+ kTopSenchaDirectPadsSpiHost0Sd2 = 4, /**< */
+ kTopSenchaDirectPadsSpiHost0Sd3 = 5, /**< */
+ kTopSenchaDirectPadsSpiDeviceSd0 = 6, /**< */
+ kTopSenchaDirectPadsSpiDeviceSd1 = 7, /**< */
+ kTopSenchaDirectPadsSpiDeviceSd2 = 8, /**< */
+ kTopSenchaDirectPadsSpiDeviceSd3 = 9, /**< */
+ kTopSenchaDirectPadsSysrstCtrlAonEcRstL = 10, /**< */
+ kTopSenchaDirectPadsSysrstCtrlAonFlashWpL = 11, /**< */
+ kTopSenchaDirectPadsSpiDeviceSck = 12, /**< */
+ kTopSenchaDirectPadsSpiDeviceCsb = 13, /**< */
+ kTopSenchaDirectPadsSpiHost0Sck = 14, /**< */
+ kTopSenchaDirectPadsSpiHost0Csb = 15, /**< */
+ kTopSenchaDirectPadsLast = 15, /**< \internal Last valid direct pad */
+} top_sencha_direct_pads_t;
+
+/**
+ * Muxed Pad Selects
+ */
+typedef enum top_sencha_muxed_pads {
+ kTopSenchaMuxedPadsIoa0 = 0, /**< */
+ kTopSenchaMuxedPadsIoa1 = 1, /**< */
+ kTopSenchaMuxedPadsIoa2 = 2, /**< */
+ kTopSenchaMuxedPadsIoa3 = 3, /**< */
+ kTopSenchaMuxedPadsIoa4 = 4, /**< */
+ kTopSenchaMuxedPadsIoa5 = 5, /**< */
+ kTopSenchaMuxedPadsIoa6 = 6, /**< */
+ kTopSenchaMuxedPadsIoa7 = 7, /**< */
+ kTopSenchaMuxedPadsIoa8 = 8, /**< */
+ kTopSenchaMuxedPadsIob0 = 9, /**< */
+ kTopSenchaMuxedPadsIob1 = 10, /**< */
+ kTopSenchaMuxedPadsIob2 = 11, /**< */
+ kTopSenchaMuxedPadsIob3 = 12, /**< */
+ kTopSenchaMuxedPadsIob4 = 13, /**< */
+ kTopSenchaMuxedPadsIob5 = 14, /**< */
+ kTopSenchaMuxedPadsIob6 = 15, /**< */
+ kTopSenchaMuxedPadsIob7 = 16, /**< */
+ kTopSenchaMuxedPadsIob8 = 17, /**< */
+ kTopSenchaMuxedPadsIob9 = 18, /**< */
+ kTopSenchaMuxedPadsIob10 = 19, /**< */
+ kTopSenchaMuxedPadsIob11 = 20, /**< */
+ kTopSenchaMuxedPadsIob12 = 21, /**< */
+ kTopSenchaMuxedPadsIoc0 = 22, /**< */
+ kTopSenchaMuxedPadsIoc1 = 23, /**< */
+ kTopSenchaMuxedPadsIoc2 = 24, /**< */
+ kTopSenchaMuxedPadsIoc3 = 25, /**< */
+ kTopSenchaMuxedPadsIoc4 = 26, /**< */
+ kTopSenchaMuxedPadsIoc5 = 27, /**< */
+ kTopSenchaMuxedPadsIoc6 = 28, /**< */
+ kTopSenchaMuxedPadsIoc7 = 29, /**< */
+ kTopSenchaMuxedPadsIoc8 = 30, /**< */
+ kTopSenchaMuxedPadsIoc9 = 31, /**< */
+ kTopSenchaMuxedPadsIoc10 = 32, /**< */
+ kTopSenchaMuxedPadsIoc11 = 33, /**< */
+ kTopSenchaMuxedPadsIoc12 = 34, /**< */
+ kTopSenchaMuxedPadsIor0 = 35, /**< */
+ kTopSenchaMuxedPadsIor1 = 36, /**< */
+ kTopSenchaMuxedPadsIor2 = 37, /**< */
+ kTopSenchaMuxedPadsIor3 = 38, /**< */
+ kTopSenchaMuxedPadsIor4 = 39, /**< */
+ kTopSenchaMuxedPadsIor5 = 40, /**< */
+ kTopSenchaMuxedPadsIor6 = 41, /**< */
+ kTopSenchaMuxedPadsIor7 = 42, /**< */
+ kTopSenchaMuxedPadsIor10 = 43, /**< */
+ kTopSenchaMuxedPadsIor11 = 44, /**< */
+ kTopSenchaMuxedPadsIor12 = 45, /**< */
+ kTopSenchaMuxedPadsIor13 = 46, /**< */
+ kTopSenchaMuxedPadsIod0 = 47, /**< */
+ kTopSenchaMuxedPadsIod1 = 48, /**< */
+ kTopSenchaMuxedPadsIod2 = 49, /**< */
+ kTopSenchaMuxedPadsIod3 = 50, /**< */
+ kTopSenchaMuxedPadsIod4 = 51, /**< */
+ kTopSenchaMuxedPadsIod5 = 52, /**< */
+ kTopSenchaMuxedPadsLast = 52, /**< \internal Last valid muxed pad */
+} top_sencha_muxed_pads_t;
+
+/**
+ * Power Manager Wakeup Signals
+ */
+typedef enum top_sencha_power_manager_wake_ups {
+ kTopSenchaPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**< */
+ kTopSenchaPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**< */
+ kTopSenchaPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**< */
+ kTopSenchaPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
+ kTopSenchaPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**< */
+ kTopSenchaPowerManagerWakeUpsSensorCtrlWkupReq = 5, /**< */
+ kTopSenchaPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
+} top_sencha_power_manager_wake_ups_t;
+
+/**
+ * Reset Manager Software Controlled Resets
+ */
+typedef enum top_sencha_reset_manager_sw_resets {
+ kTopSenchaResetManagerSwResetsSpiDevice = 0, /**< */
+ kTopSenchaResetManagerSwResetsSpiHost0 = 1, /**< */
+ kTopSenchaResetManagerSwResetsSpiHost1 = 2, /**< */
+ kTopSenchaResetManagerSwResetsSpiHost2 = 3, /**< */
+ kTopSenchaResetManagerSwResetsUsb = 4, /**< */
+ kTopSenchaResetManagerSwResetsUsbAon = 5, /**< */
+ kTopSenchaResetManagerSwResetsI2c0 = 6, /**< */
+ kTopSenchaResetManagerSwResetsI2c1 = 7, /**< */
+ kTopSenchaResetManagerSwResetsI2c2 = 8, /**< */
+ kTopSenchaResetManagerSwResetsSmc = 9, /**< */
+ kTopSenchaResetManagerSwResetsMl = 10, /**< */
+ kTopSenchaResetManagerSwResetsCamI2c = 11, /**< */
+ kTopSenchaResetManagerSwResetsVideo = 12, /**< */
+ kTopSenchaResetManagerSwResetsAudio = 13, /**< */
+ kTopSenchaResetManagerSwResetsLast = 13, /**< \internal Last valid rstmgr software reset request */
+} top_sencha_reset_manager_sw_resets_t;
+
+/**
+ * Power Manager Reset Request Signals
+ */
+typedef enum top_sencha_power_manager_reset_requests {
+ kTopSenchaPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**< */
+ kTopSenchaPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
+ kTopSenchaPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
+} top_sencha_power_manager_reset_requests_t;
+
+/**
+ * Clock Manager Software-Controlled ("Gated") Clocks.
+ *
+ * The Software has full control over these clocks.
+ */
+typedef enum top_sencha_gateable_clocks {
+ kTopSenchaGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
+ kTopSenchaGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
+ kTopSenchaGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
+ kTopSenchaGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
+ kTopSenchaGateableClocksVideoPeri = 4, /**< Clock clk_video_peri in group peri */
+ kTopSenchaGateableClocksMlPeri = 5, /**< Clock clk_ml_peri in group peri */
+ kTopSenchaGateableClocksAudioPeri = 6, /**< Clock clk_audio_peri in group peri */
+ kTopSenchaGateableClocksSmcPeri = 7, /**< Clock clk_smc_peri in group peri */
+ kTopSenchaGateableClocksLast = 7, /**< \internal Last Valid Gateable Clock */
+} top_sencha_gateable_clocks_t;
+
+/**
+ * Clock Manager Software-Hinted Clocks.
+ *
+ * The Software has partial control over these clocks. It can ask them to stop,
+ * but the clock manager is in control of whether the clock actually is stopped.
+ */
+typedef enum top_sencha_hintable_clocks {
+ kTopSenchaHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
+ kTopSenchaHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
+ kTopSenchaHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
+ kTopSenchaHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
+ kTopSenchaHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */
+} top_sencha_hintable_clocks_t;
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_SENCHA_MMIO_BASE_ADDR 0x40000000u
+#define TOP_SENCHA_MMIO_SIZE_BYTES 0x28000000u
+
+// Header Extern Guard
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_H_
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.h b/hw/top_sencha/sw/autogen/top_sencha_memory.h
new file mode 100644
index 0000000..03afdcb
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/top_sencha_memory.h
@@ -0,0 +1,1238 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_MEMORY_H_
+#define MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_MEMORY_H_
+
+/**
+ * @file
+ * @brief Assembler-only Top-Specific Definitions.
+ *
+ * This file contains preprocessor definitions for use within assembly code.
+ *
+ * These are not shared with C/C++ code because these are only allowed to be
+ * preprocessor definitions, no data or type declarations are allowed. The
+ * assembler is also stricter about literals (not allowing suffixes for
+ * signed/unsigned which are sensible to use for unsigned values in C/C++).
+ */
+
+// Include guard for assembler
+#ifdef __ASSEMBLER__
+
+
+/**
+ * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top sencha.
+ */
+#define TOP_SENCHA_RAM_RET_AON_BASE_ADDR 0x40600000
+
+/**
+ * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top sencha.
+ */
+#define TOP_SENCHA_RAM_RET_AON_SIZE_BYTES 0x1000
+
+/**
+ * Memory base for flash_ctrl_eflash in top sencha.
+ */
+#define TOP_SENCHA_EFLASH_BASE_ADDR 0x20000000
+
+/**
+ * Memory size for flash_ctrl_eflash in top sencha.
+ */
+#define TOP_SENCHA_EFLASH_SIZE_BYTES 0x100000
+
+/**
+ * Memory base for sram_ctrl_main_ram_main in top sencha.
+ */
+#define TOP_SENCHA_RAM_MAIN_BASE_ADDR 0x10000000
+
+/**
+ * Memory size for sram_ctrl_main_ram_main in top sencha.
+ */
+#define TOP_SENCHA_RAM_MAIN_SIZE_BYTES 0x20000
+
+/**
+ * Memory base for rom_ctrl_rom in top sencha.
+ */
+#define TOP_SENCHA_ROM_BASE_ADDR 0x00008000
+
+/**
+ * Memory size for rom_ctrl_rom in top sencha.
+ */
+#define TOP_SENCHA_ROM_SIZE_BYTES 0x8000
+
+/**
+ * Memory base for ml_top_ram_ml_dmem in top sencha.
+ */
+#define TOP_SENCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Memory size for ml_top_ram_ml_dmem in top sencha.
+ */
+#define TOP_SENCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000
+
+
+/**
+ * Memory base address for ram_smc in top sencha.
+ */
+#define TOP_SENCHA_RAM_SMC_BASE_ADDR 0x50000000
+
+/**
+ * Memory size for ram_smc in top sencha.
+ */
+#define TOP_SENCHA_RAM_SMC_SIZE_BYTES 0x400000
+
+
+/**
+ * Peripheral base address for uart0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART0_BASE_ADDR 0x40000000
+
+/**
+ * Peripheral size for uart0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART0_BASE_ADDR and
+ * `TOP_SENCHA_UART0_BASE_ADDR + TOP_SENCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART1_BASE_ADDR 0x40010000
+
+/**
+ * Peripheral size for uart1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART1_BASE_ADDR and
+ * `TOP_SENCHA_UART1_BASE_ADDR + TOP_SENCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART2_BASE_ADDR 0x40020000
+
+/**
+ * Peripheral size for uart2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART2_BASE_ADDR and
+ * `TOP_SENCHA_UART2_BASE_ADDR + TOP_SENCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart3 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_UART3_BASE_ADDR 0x40030000
+
+/**
+ * Peripheral size for uart3 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_UART3_BASE_ADDR and
+ * `TOP_SENCHA_UART3_BASE_ADDR + TOP_SENCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_UART3_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for gpio in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_GPIO_BASE_ADDR 0x40040000
+
+/**
+ * Peripheral size for gpio in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_GPIO_BASE_ADDR and
+ * `TOP_SENCHA_GPIO_BASE_ADDR + TOP_SENCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_GPIO_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_device in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_DEVICE_BASE_ADDR 0x40050000
+
+/**
+ * Peripheral size for spi_device in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_SENCHA_SPI_DEVICE_BASE_ADDR + TOP_SENCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_DEVICE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for i2c0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C0_BASE_ADDR 0x40080000
+
+/**
+ * Peripheral size for i2c0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C0_BASE_ADDR and
+ * `TOP_SENCHA_I2C0_BASE_ADDR + TOP_SENCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C1_BASE_ADDR 0x40090000
+
+/**
+ * Peripheral size for i2c1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C1_BASE_ADDR and
+ * `TOP_SENCHA_I2C1_BASE_ADDR + TOP_SENCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2C2_BASE_ADDR 0x400A0000
+
+/**
+ * Peripheral size for i2c2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2C2_BASE_ADDR and
+ * `TOP_SENCHA_I2C2_BASE_ADDR + TOP_SENCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2C2_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pattgen in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PATTGEN_BASE_ADDR 0x400E0000
+
+/**
+ * Peripheral size for pattgen in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PATTGEN_BASE_ADDR and
+ * `TOP_SENCHA_PATTGEN_BASE_ADDR + TOP_SENCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PATTGEN_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_BASE_ADDR 0x40100000
+
+/**
+ * Peripheral size for rv_timer in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_BASE_ADDR + TOP_SENCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for core device on otp_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000
+
+/**
+ * Peripheral size for core device on otp_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_SENCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for prim device on otp_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_SENCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_SENCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for lc_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_LC_CTRL_BASE_ADDR 0x40140000
+
+/**
+ * Peripheral size for lc_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_LC_CTRL_BASE_ADDR + TOP_SENCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_LC_CTRL_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for alert_handler in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ALERT_HANDLER_BASE_ADDR 0x40150000
+
+/**
+ * Peripheral size for alert_handler in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_SENCHA_ALERT_HANDLER_BASE_ADDR + TOP_SENCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ALERT_HANDLER_SIZE_BYTES 0x800
+/**
+ * Peripheral base address for spi_host0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST0_BASE_ADDR 0x40300000
+
+/**
+ * Peripheral size for spi_host0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST0_BASE_ADDR + TOP_SENCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_host1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST1_BASE_ADDR 0x40310000
+
+/**
+ * Peripheral size for spi_host1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST1_BASE_ADDR + TOP_SENCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for usbdev in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_USBDEV_BASE_ADDR 0x40320000
+
+/**
+ * Peripheral size for usbdev in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_USBDEV_BASE_ADDR and
+ * `TOP_SENCHA_USBDEV_BASE_ADDR + TOP_SENCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_USBDEV_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for pwrmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PWRMGR_AON_BASE_ADDR 0x40400000
+
+/**
+ * Peripheral size for pwrmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_PWRMGR_AON_BASE_ADDR + TOP_SENCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PWRMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rstmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RSTMGR_AON_BASE_ADDR 0x40410000
+
+/**
+ * Peripheral size for rstmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_RSTMGR_AON_BASE_ADDR + TOP_SENCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RSTMGR_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for clkmgr_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CLKMGR_AON_BASE_ADDR 0x40420000
+
+/**
+ * Peripheral size for clkmgr_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_SENCHA_CLKMGR_AON_BASE_ADDR + TOP_SENCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CLKMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_SENCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for adc_ctrl_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000
+
+/**
+ * Peripheral size for adc_ctrl_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR + TOP_SENCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ADC_CTRL_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pwm_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PWM_AON_BASE_ADDR 0x40450000
+
+/**
+ * Peripheral size for pwm_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PWM_AON_BASE_ADDR and
+ * `TOP_SENCHA_PWM_AON_BASE_ADDR + TOP_SENCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PWM_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pinmux_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_PINMUX_AON_BASE_ADDR 0x40460000
+
+/**
+ * Peripheral size for pinmux_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_SENCHA_PINMUX_AON_BASE_ADDR + TOP_SENCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_PINMUX_AON_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for aon_timer_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AON_TIMER_AON_BASE_ADDR 0x40470000
+
+/**
+ * Peripheral size for aon_timer_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_SENCHA_AON_TIMER_AON_BASE_ADDR + TOP_SENCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AON_TIMER_AON_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for ast in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AST_BASE_ADDR 0x40480000
+
+/**
+ * Peripheral size for ast in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AST_BASE_ADDR and
+ * `TOP_SENCHA_AST_BASE_ADDR + TOP_SENCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AST_SIZE_BYTES 0x400
+/**
+ * Peripheral base address for sensor_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SENSOR_CTRL_BASE_ADDR 0x40490000
+
+/**
+ * Peripheral size for sensor_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_SENSOR_CTRL_BASE_ADDR + TOP_SENCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SENSOR_CTRL_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for core device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
+
+/**
+ * Peripheral size for core device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for prim device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for mem device on flash_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_SENCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_SENCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
+/**
+ * Peripheral base address for regs device on rv_dm in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_DM_REGS_BASE_ADDR 0x6000
+
+/**
+ * Peripheral size for regs device on rv_dm in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_SENCHA_RV_DM_REGS_BASE_ADDR + TOP_SENCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_DM_REGS_SIZE_BYTES 0x4
+/**
+ * Peripheral base address for mem device on rv_dm in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_DM_MEM_BASE_ADDR 0x4000
+
+/**
+ * Peripheral size for mem device on rv_dm in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_SENCHA_RV_DM_MEM_BASE_ADDR + TOP_SENCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_DM_MEM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for rv_plic in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_PLIC_BASE_ADDR 0x48000000
+
+/**
+ * Peripheral size for rv_plic in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_SENCHA_RV_PLIC_BASE_ADDR + TOP_SENCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_PLIC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for aes in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_AES_BASE_ADDR 0x41100000
+
+/**
+ * Peripheral size for aes in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_AES_BASE_ADDR and
+ * `TOP_SENCHA_AES_BASE_ADDR + TOP_SENCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_AES_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for hmac in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_HMAC_BASE_ADDR 0x41110000
+
+/**
+ * Peripheral size for hmac in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_HMAC_BASE_ADDR and
+ * `TOP_SENCHA_HMAC_BASE_ADDR + TOP_SENCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_HMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for kmac in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_KMAC_BASE_ADDR 0x41120000
+
+/**
+ * Peripheral size for kmac in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_KMAC_BASE_ADDR and
+ * `TOP_SENCHA_KMAC_BASE_ADDR + TOP_SENCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_KMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for otbn in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_OTBN_BASE_ADDR 0x41130000
+
+/**
+ * Peripheral size for otbn in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_OTBN_BASE_ADDR and
+ * `TOP_SENCHA_OTBN_BASE_ADDR + TOP_SENCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_OTBN_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for keymgr in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_KEYMGR_BASE_ADDR 0x41140000
+
+/**
+ * Peripheral size for keymgr in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_KEYMGR_BASE_ADDR and
+ * `TOP_SENCHA_KEYMGR_BASE_ADDR + TOP_SENCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_KEYMGR_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for csrng in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CSRNG_BASE_ADDR 0x41150000
+
+/**
+ * Peripheral size for csrng in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CSRNG_BASE_ADDR and
+ * `TOP_SENCHA_CSRNG_BASE_ADDR + TOP_SENCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CSRNG_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for entropy_src in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ENTROPY_SRC_BASE_ADDR 0x41160000
+
+/**
+ * Peripheral size for entropy_src in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_SENCHA_ENTROPY_SRC_BASE_ADDR + TOP_SENCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ENTROPY_SRC_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for edn0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_EDN0_BASE_ADDR 0x41170000
+
+/**
+ * Peripheral size for edn0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_EDN0_BASE_ADDR and
+ * `TOP_SENCHA_EDN0_BASE_ADDR + TOP_SENCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_EDN0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for edn1 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_EDN1_BASE_ADDR 0x41180000
+
+/**
+ * Peripheral size for edn1 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_EDN1_BASE_ADDR and
+ * `TOP_SENCHA_EDN1_BASE_ADDR + TOP_SENCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_EDN1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_SENCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_SENCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
+/**
+ * Peripheral base address for regs device on rom_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_SENCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rom device on rom_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_SENCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_SENCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for dma0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_DMA0_BASE_ADDR 0x40200000
+
+/**
+ * Peripheral size for dma0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_DMA0_BASE_ADDR and
+ * `TOP_SENCHA_DMA0_BASE_ADDR + TOP_SENCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_DMA0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for smc_uart in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SMC_UART_BASE_ADDR 0x54000000
+
+/**
+ * Peripheral size for smc_uart in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SMC_UART_BASE_ADDR and
+ * `TOP_SENCHA_SMC_UART_BASE_ADDR + TOP_SENCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SMC_UART_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000
+
+/**
+ * Peripheral size for rv_timer_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_SMC_BASE_ADDR + TOP_SENCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SMC_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for smc_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SMC_CTRL_BASE_ADDR 0x54020000
+
+/**
+ * Peripheral size for smc_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_SMC_CTRL_BASE_ADDR + TOP_SENCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SMC_CTRL_SIZE_BYTES 0x8
+/**
+ * Peripheral base address for cam_i2c in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CAM_I2C_BASE_ADDR 0x54040000
+
+/**
+ * Peripheral size for cam_i2c in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_SENCHA_CAM_I2C_BASE_ADDR + TOP_SENCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CAM_I2C_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for cam_ctrl in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_CAM_CTRL_BASE_ADDR 0x54050000
+
+/**
+ * Peripheral size for cam_ctrl in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_SENCHA_CAM_CTRL_BASE_ADDR + TOP_SENCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_CAM_CTRL_SIZE_BYTES 0x10
+/**
+ * Peripheral base address for isp_wrapper in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ISP_WRAPPER_BASE_ADDR 0x54060000
+
+/**
+ * Peripheral size for isp_wrapper in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ISP_WRAPPER_BASE_ADDR and
+ * `TOP_SENCHA_ISP_WRAPPER_BASE_ADDR + TOP_SENCHA_ISP_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ISP_WRAPPER_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for dma_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_DMA_SMC_BASE_ADDR 0x54070000
+
+/**
+ * Peripheral size for dma_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_SENCHA_DMA_SMC_BASE_ADDR + TOP_SENCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_DMA_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_plic_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000
+
+/**
+ * Peripheral size for rv_plic_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_SENCHA_RV_PLIC_SMC_BASE_ADDR + TOP_SENCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for tlul_mailbox_sec in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_SENCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for tlul_mailbox_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_SENCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_SENCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for core device on ml_top in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000
+
+/**
+ * Peripheral size for core device on ml_top in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_SENCHA_ML_TOP_CORE_BASE_ADDR + TOP_SENCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ML_TOP_CORE_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for dmem device on ml_top in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Peripheral size for dmem device on ml_top in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_SENCHA_ML_TOP_DMEM_BASE_ADDR + TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000
+/**
+ * Peripheral base address for spi_host2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_SPI_HOST2_BASE_ADDR 0x54090000
+
+/**
+ * Peripheral size for spi_host2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_SENCHA_SPI_HOST2_BASE_ADDR + TOP_SENCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_SPI_HOST2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc2 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000
+
+/**
+ * Peripheral size for rv_timer_smc2 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_SENCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_SENCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for i2s0 in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_I2S0_BASE_ADDR 0x54100000
+
+/**
+ * Peripheral size for i2s0 in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_I2S0_BASE_ADDR and
+ * `TOP_SENCHA_I2S0_BASE_ADDR + TOP_SENCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_I2S0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top sencha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top sencha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_SENCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_SENCHA_MMIO_BASE_ADDR 0x40000000
+#define TOP_SENCHA_MMIO_SIZE_BYTES 0x28000000
+
+#endif // __ASSEMBLER__
+
+#endif // MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_MEMORY_H_
diff --git a/hw/top_sencha/sw/autogen/top_sencha_memory.ld b/hw/top_sencha/sw/autogen/top_sencha_memory.ld
new file mode 100644
index 0000000..6dfb4e8
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/top_sencha_memory.ld
@@ -0,0 +1,48 @@
+/* Copyright lowRISC contributors. */
+/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/**
+ * Partial linker script for chip memory configuration.
+ * rom_ext_virtual and owner_virtual are address windows that provide a fixed translation
+ * address for whichever half of the flash contains the corresponding boot stage.
+ */
+MEMORY {
+ ram_ret_aon(rwx) : ORIGIN = 0x40600000, LENGTH = 0x1000
+ eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000
+ ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000
+ rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000
+ ram_ml_dmem(rwx) : ORIGIN = 0x5A000000, LENGTH = 0x400000
+ ram_smc(rw) : ORIGIN = 0x50000000, LENGTH = 0x400000
+ rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000
+ owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000
+}
+
+/**
+ * Stack at the top of the main SRAM.
+ */
+_stack_size = 16384;
+_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);
+_stack_start = _stack_end - _stack_size;
+
+/**
+ * Size of the `.static_critical` section at the bottom of the main SRAM (in
+ * bytes).
+ */
+_static_critical_size = 8132;
+
+/**
+ * `.chip_info` at the top of ROM.
+ */
+_chip_info_size = 128;
+_chip_info_end = ORIGIN(rom) + LENGTH(rom);
+_chip_info_start = _chip_info_end - _chip_info_size;
+
+/**
+ * Size of the initial ePMP RX region at reset (in bytes). This region must be
+ * large enough to cover the .crt section.
+ *
+ * NOTE: This value must match the size of the RX region in
+ * hw/ip/rv_core_ibex/rtl/ibex_pmp_reset.svh.
+ */
+_epmp_reset_rx_size = 2048;
diff --git a/hw/top_sencha/sw/autogen/top_sencha_smc_irq.h b/hw/top_sencha/sw/autogen/top_sencha_smc_irq.h
new file mode 100644
index 0000000..1cd9d23
--- /dev/null
+++ b/hw/top_sencha/sw/autogen/top_sencha_smc_irq.h
@@ -0,0 +1,82 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_IRQ_H_
+#define MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_IRQ_H_
+
+/**
+ * @file
+ * @brief Assembler-only Top-specific Definitions
+ *
+ * This file contains preprocessor definitions for use within assembly code.
+ */
+
+#ifdef __ASSEMBLER__
+
+/**
+ * SMC PLIC Interrupt Source.
+ *
+ * Enumeration of all SMC PLIC interrupt sources. The interrupt sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+#define TOP_SENCHA_PLIC_IRQ_ID_NONE_SMC 0 /**< No Interrupt */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_TX_WATERMARK 1 /**< smc_uart_tx_watermark */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_WATERMARK 2 /**< smc_uart_rx_watermark */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_TX_EMPTY 3 /**< smc_uart_tx_empty */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_OVERFLOW 4 /**< smc_uart_rx_overflow */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_FRAME_ERR 5 /**< smc_uart_rx_frame_err */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_BREAK_ERR 6 /**< smc_uart_rx_break_err */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_TIMEOUT 7 /**< smc_uart_rx_timeout */
+#define TOP_SENCHA_PLIC_IRQ_ID_SMC_UART_RX_PARITY_ERR 8 /**< smc_uart_rx_parity_err */
+#define TOP_SENCHA_PLIC_IRQ_ID_RV_TIMER_SMC_TIMER_EXPIRED_HART0_TIMER0 9 /**< rv_timer_smc_timer_expired_hart0_timer0 */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_FMT_THRESHOLD 10 /**< cam_i2c_fmt_threshold */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_RX_THRESHOLD 11 /**< cam_i2c_rx_threshold */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_FMT_OVERFLOW 12 /**< cam_i2c_fmt_overflow */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_RX_OVERFLOW 13 /**< cam_i2c_rx_overflow */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_NAK 14 /**< cam_i2c_nak */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_SCL_INTERFERENCE 15 /**< cam_i2c_scl_interference */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_SDA_INTERFERENCE 16 /**< cam_i2c_sda_interference */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_STRETCH_TIMEOUT 17 /**< cam_i2c_stretch_timeout */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_SDA_UNSTABLE 18 /**< cam_i2c_sda_unstable */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_CMD_COMPLETE 19 /**< cam_i2c_cmd_complete */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_TX_STRETCH 20 /**< cam_i2c_tx_stretch */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_TX_OVERFLOW 21 /**< cam_i2c_tx_overflow */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_ACQ_FULL 22 /**< cam_i2c_acq_full */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_UNEXP_STOP 23 /**< cam_i2c_unexp_stop */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_I2C_HOST_TIMEOUT 24 /**< cam_i2c_host_timeout */
+#define TOP_SENCHA_PLIC_IRQ_ID_CAM_CTRL_CAM_MOTION_DETECT 25 /**< cam_ctrl_cam_motion_detect */
+#define TOP_SENCHA_PLIC_IRQ_ID_ISP_WRAPPER_ISP 26 /**< isp_wrapper_isp */
+#define TOP_SENCHA_PLIC_IRQ_ID_ISP_WRAPPER_MI 27 /**< isp_wrapper_mi */
+#define TOP_SENCHA_PLIC_IRQ_ID_DMA_SMC_WRITER_DONE 28 /**< dma_smc_writer_done */
+#define TOP_SENCHA_PLIC_IRQ_ID_DMA_SMC_READER_DONE 29 /**< dma_smc_reader_done */
+#define TOP_SENCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_WTIRQ 30 /**< tlul_mailbox_smc_wtirq */
+#define TOP_SENCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_RTIRQ 31 /**< tlul_mailbox_smc_rtirq */
+#define TOP_SENCHA_PLIC_IRQ_ID_TLUL_MAILBOX_SMC_EIRQ 32 /**< tlul_mailbox_smc_eirq */
+#define TOP_SENCHA_PLIC_IRQ_ID_ML_TOP_HOST_REQ 33 /**< ml_top_host_req */
+#define TOP_SENCHA_PLIC_IRQ_ID_ML_TOP_FINISH 34 /**< ml_top_finish */
+#define TOP_SENCHA_PLIC_IRQ_ID_ML_TOP_FAULT 35 /**< ml_top_fault */
+#define TOP_SENCHA_PLIC_IRQ_ID_SPI_HOST2_ERROR 36 /**< spi_host2_error */
+#define TOP_SENCHA_PLIC_IRQ_ID_SPI_HOST2_SPI_EVENT 37 /**< spi_host2_spi_event */
+#define TOP_SENCHA_PLIC_IRQ_ID_RV_TIMER_SMC2_TIMER_EXPIRED_HART0_TIMER0 38 /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+#define TOP_SENCHA_PLIC_IRQ_ID_I2S0_TX_WATERMARK 39 /**< i2s0_tx_watermark */
+#define TOP_SENCHA_PLIC_IRQ_ID_I2S0_RX_WATERMARK 40 /**< i2s0_rx_watermark */
+#define TOP_SENCHA_PLIC_IRQ_ID_I2S0_TX_EMPTY 41 /**< i2s0_tx_empty */
+#define TOP_SENCHA_PLIC_IRQ_ID_I2S0_RX_OVERFLOW 42 /**< i2s0_rx_overflow */
+#define TOP_SENCHA_PLIC_IRQ_ID_LAST_SMC 42 /**< \internal The Last Valid Interrupt ID. */
+
+
+#endif // __ASSEMBLER__
+
+#endif // MATCHA_HW_TOP_SENCHA_SW_AUTOGEN_TOP_SENCHA_IRQ_H_
diff --git a/sw/device/tests/autogen/sencha/alert_test.c b/sw/device/tests/autogen/sencha/alert_test.c
new file mode 100644
index 0000000..0ebf51c
--- /dev/null
+++ b/sw/device/tests/autogen/sencha/alert_test.c
@@ -0,0 +1,992 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// clang-format off
+
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson
+// -o sw/device/tests/autogen
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_adc_ctrl.h"
+#include "sw/device/lib/dif/dif_aes.h"
+#include "sw/device/lib/dif/dif_alert_handler.h"
+#include "sw/device/lib/dif/dif_aon_timer.h"
+#include "sw/device/lib/dif/dif_clkmgr.h"
+#include "sw/device/lib/dif/dif_csrng.h"
+#include "sw/device/lib/dif/dif_edn.h"
+#include "sw/device/lib/dif/dif_entropy_src.h"
+#include "sw/device/lib/dif/dif_flash_ctrl.h"
+#include "sw/device/lib/dif/dif_gpio.h"
+#include "sw/device/lib/dif/dif_hmac.h"
+#include "sw/device/lib/dif/dif_i2c.h"
+#include "sw/device/lib/dif/dif_keymgr.h"
+#include "sw/device/lib/dif/dif_kmac.h"
+#include "sw/device/lib/dif/dif_lc_ctrl.h"
+#include "sw/device/lib/dif/dif_otbn.h"
+#include "sw/device/lib/dif/dif_otp_ctrl.h"
+#include "sw/device/lib/dif/dif_pattgen.h"
+#include "sw/device/lib/dif/dif_pinmux.h"
+#include "sw/device/lib/dif/dif_pwm.h"
+#include "sw/device/lib/dif/dif_pwrmgr.h"
+#include "sw/device/lib/dif/dif_rom_ctrl.h"
+#include "sw/device/lib/dif/dif_rstmgr.h"
+#include "sw/device/lib/dif/dif_rv_core_ibex.h"
+#include "sw/device/lib/dif/dif_rv_plic.h"
+#include "sw/device/lib/dif/dif_rv_timer.h"
+#include "sw/device/lib/dif/dif_sensor_ctrl.h"
+#include "sw/device/lib/dif/dif_spi_device.h"
+#include "sw/device/lib/dif/dif_spi_host.h"
+#include "sw/device/lib/dif/dif_sram_ctrl.h"
+#include "sw/device/lib/dif/dif_sysrst_ctrl.h"
+#include "sw/device/lib/dif/dif_uart.h"
+#include "sw/device/lib/dif/dif_usbdev.h"
+#include "sw/device/lib/testing/alert_handler_testutils.h"
+#include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
+
+#include "alert_handler_regs.h" // Generated.
+#include "hw/top_sencha/sw/autogen/top_sencha.h"
+
+OTTF_DEFINE_TEST_CONFIG();
+
+static dif_alert_handler_t alert_handler;
+static dif_adc_ctrl_t adc_ctrl_aon;
+static dif_aes_t aes;
+static dif_aon_timer_t aon_timer_aon;
+static dif_i2c_t cam_i2c;
+static dif_clkmgr_t clkmgr_aon;
+static dif_csrng_t csrng;
+static dif_edn_t edn0;
+static dif_edn_t edn1;
+static dif_entropy_src_t entropy_src;
+static dif_flash_ctrl_t flash_ctrl;
+static dif_gpio_t gpio;
+static dif_hmac_t hmac;
+static dif_i2c_t i2c0;
+static dif_i2c_t i2c1;
+static dif_i2c_t i2c2;
+static dif_keymgr_t keymgr;
+static dif_kmac_t kmac;
+static dif_lc_ctrl_t lc_ctrl;
+static dif_otbn_t otbn;
+static dif_otp_ctrl_t otp_ctrl;
+static dif_pattgen_t pattgen;
+static dif_pinmux_t pinmux_aon;
+static dif_pwm_t pwm_aon;
+static dif_pwrmgr_t pwrmgr_aon;
+static dif_rom_ctrl_t rom_ctrl;
+static dif_rstmgr_t rstmgr_aon;
+static dif_rv_core_ibex_t rv_core_ibex_sec;
+static dif_rv_plic_t rv_plic;
+static dif_rv_timer_t rv_timer;
+static dif_sensor_ctrl_t sensor_ctrl;
+static dif_uart_t smc_uart;
+static dif_spi_device_t spi_device;
+static dif_spi_host_t spi_host0;
+static dif_spi_host_t spi_host1;
+static dif_spi_host_t spi_host2;
+static dif_sram_ctrl_t sram_ctrl_main;
+static dif_sram_ctrl_t sram_ctrl_ret_aon;
+static dif_sysrst_ctrl_t sysrst_ctrl_aon;
+static dif_uart_t uart0;
+static dif_uart_t uart1;
+static dif_uart_t uart2;
+static dif_uart_t uart3;
+static dif_usbdev_t usbdev;
+
+/**
+ * Initialize the peripherals used in this test.
+ */
+static void init_peripherals(void) {
+ mmio_region_t base_addr;
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ALERT_HANDLER_BASE_ADDR);
+ CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_AES_BASE_ADDR);
+ CHECK_DIF_OK(dif_aes_init(base_addr, &aes));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_AON_TIMER_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_CAM_I2C_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &cam_i2c));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_CLKMGR_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_clkmgr_init(base_addr, &clkmgr_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_CSRNG_BASE_ADDR);
+ CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_EDN0_BASE_ADDR);
+ CHECK_DIF_OK(dif_edn_init(base_addr, &edn0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_EDN1_BASE_ADDR);
+ CHECK_DIF_OK(dif_edn_init(base_addr, &edn1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ENTROPY_SRC_BASE_ADDR);
+ CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR);
+ CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_GPIO_BASE_ADDR);
+ CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_HMAC_BASE_ADDR);
+ CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C0_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C1_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C2_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_KEYMGR_BASE_ADDR);
+ CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_KMAC_BASE_ADDR);
+ CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_LC_CTRL_BASE_ADDR);
+ CHECK_DIF_OK(dif_lc_ctrl_init(base_addr, &lc_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_OTBN_BASE_ADDR);
+ CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR);
+ CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PATTGEN_BASE_ADDR);
+ CHECK_DIF_OK(dif_pattgen_init(base_addr, &pattgen));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PINMUX_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_pinmux_init(base_addr, &pinmux_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PWM_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_pwm_init(base_addr, &pwm_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PWRMGR_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ROM_CTRL_REGS_BASE_ADDR);
+ CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RSTMGR_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR);
+ CHECK_DIF_OK(dif_rv_core_ibex_init(base_addr, &rv_core_ibex_sec));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RV_PLIC_BASE_ADDR);
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, &rv_plic));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RV_TIMER_BASE_ADDR);
+ CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SENSOR_CTRL_BASE_ADDR);
+ CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SMC_UART_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &smc_uart));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_DEVICE_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_HOST0_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_HOST1_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_HOST2_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host2));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR);
+ CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_main));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR);
+ CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_ret_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART0_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART1_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART2_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart2));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART3_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart3));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_USBDEV_BASE_ADDR);
+ CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev));
+
+}
+
+/**
+ * Configure the alert handler to escalate on alerts upto phase 1 (i.e. wipe
+ * secret) but not trigger reset. Then CPU can check if alert_handler triggers the correct
+ * alert_cause register.
+ */
+static void alert_handler_config(void) {
+ dif_alert_handler_alert_t alerts[ALERT_HANDLER_PARAM_N_ALERTS];
+ dif_alert_handler_class_t alert_classes[ALERT_HANDLER_PARAM_N_ALERTS];
+
+ // Enable all incoming alerts and configure them to classa.
+ // This alert should never fire because we do not expect any incoming alerts.
+ for (int i = 0; i < ALERT_HANDLER_PARAM_N_ALERTS; ++i) {
+ alerts[i] = i;
+ alert_classes[i] = kDifAlertHandlerClassA;
+ }
+
+ dif_alert_handler_escalation_phase_t esc_phases[] = {
+ {.phase = kDifAlertHandlerClassStatePhase0,
+ .signal = 0,
+ .duration_cycles = 2000}};
+
+ dif_alert_handler_class_config_t class_config = {
+ .auto_lock_accumulation_counter = kDifToggleDisabled,
+ .accumulator_threshold = 0,
+ .irq_deadline_cycles = 10000,
+ .escalation_phases = esc_phases,
+ .escalation_phases_len = ARRAYSIZE(esc_phases),
+ .crashdump_escalation_phase = kDifAlertHandlerClassStatePhase1,
+ };
+
+ dif_alert_handler_class_config_t class_configs[] = {class_config,
+ class_config};
+
+ dif_alert_handler_class_t classes[] = {kDifAlertHandlerClassA,
+ kDifAlertHandlerClassB};
+ dif_alert_handler_config_t config = {
+ .alerts = alerts,
+ .alert_classes = alert_classes,
+ .alerts_len = ARRAYSIZE(alerts),
+ .classes = classes,
+ .class_configs = class_configs,
+ .classes_len = ARRAYSIZE(class_configs),
+ .ping_timeout = 1000,
+ };
+
+ alert_handler_testutils_configure_all(&alert_handler, config,
+ kDifToggleEnabled);
+}
+
+// Trigger alert for each module by writing one to `alert_test` register.
+// Then check alert_handler's alert_cause register to make sure the correct alert reaches
+// alert_handler.
+static void trigger_alert_test(void) {
+ bool is_cause;
+ dif_alert_handler_alert_t exp_alert;
+
+#ifndef DISABLE_RENODE_TEST
+ // Write adc_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_adc_ctrl_alert_force(&adc_ctrl_aon, kDifAdcCtrlAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdAdcCtrlAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write aes's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdAesRecovCtrlUpdateErr + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write aon_timer's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_aon_timer_alert_force(&aon_timer_aon, kDifAonTimerAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdAonTimerAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write i2c's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_i2c_alert_force(&cam_i2c, kDifI2cAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdCamI2cFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write clkmgr's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_clkmgr_alert_force(&clkmgr_aon, kDifClkmgrAlertRecovFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdClkmgrAonRecovFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write csrng's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_csrng_alert_force(&csrng, kDifCsrngAlertRecovAlert + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdCsrngRecovAlert + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write edn's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_edn_alert_force(&edn0, kDifEdnAlertRecovAlert + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdEdn0RecovAlert + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write edn's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_edn_alert_force(&edn1, kDifEdnAlertRecovAlert + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdEdn1RecovAlert + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write entropy_src's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_entropy_src_alert_force(&entropy_src, kDifEntropySrcAlertRecovAlert + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdEntropySrcRecovAlert + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write flash_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 5; ++i) {
+ CHECK_DIF_OK(dif_flash_ctrl_alert_force(&flash_ctrl, kDifFlashCtrlAlertRecovErr + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdFlashCtrlRecovErr + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write gpio's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdGpioFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write hmac's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_hmac_alert_force(&hmac, kDifHmacAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdHmacFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write i2c's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_i2c_alert_force(&i2c0, kDifI2cAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdI2c0FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write i2c's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_i2c_alert_force(&i2c1, kDifI2cAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdI2c1FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write i2c's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_i2c_alert_force(&i2c2, kDifI2cAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdI2c2FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write keymgr's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_keymgr_alert_force(&keymgr, kDifKeymgrAlertRecovOperationErr + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdKeymgrRecovOperationErr + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write kmac's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_kmac_alert_force(&kmac, kDifKmacAlertRecovOperationErr + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdKmacRecovOperationErr + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write lc_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 3; ++i) {
+ CHECK_DIF_OK(dif_lc_ctrl_alert_force(&lc_ctrl, kDifLcCtrlAlertFatalProgError + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdLcCtrlFatalProgError + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write otbn's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdOtbnFatal + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write otp_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 5; ++i) {
+ CHECK_DIF_OK(dif_otp_ctrl_alert_force(&otp_ctrl, kDifOtpCtrlAlertFatalMacroError + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdOtpCtrlFatalMacroError + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write pattgen's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_pattgen_alert_force(&pattgen, kDifPattgenAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdPattgenFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write pinmux's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_pinmux_alert_force(&pinmux_aon, kDifPinmuxAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdPinmuxAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write pwm's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_pwm_alert_force(&pwm_aon, kDifPwmAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdPwmAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write pwrmgr's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_pwrmgr_alert_force(&pwrmgr_aon, kDifPwrmgrAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdPwrmgrAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write rom_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl, kDifRomCtrlAlertFatal + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdRomCtrlFatal + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write rstmgr's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_rstmgr_alert_force(&rstmgr_aon, kDifRstmgrAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdRstmgrAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write rv_core_ibex's alert_test reg and check alert_cause.
+ for (int i = 0; i < 4; ++i) {
+ CHECK_DIF_OK(dif_rv_core_ibex_alert_force(&rv_core_ibex_sec, kDifRvCoreIbexAlertFatalSwErr + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdRvCoreIbexSecFatalSwErr + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write rv_plic's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_rv_plic_alert_force(&rv_plic, kDifRvPlicAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdRvPlicFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write rv_timer's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_rv_timer_alert_force(&rv_timer, kDifRvTimerAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdRvTimerFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write sensor_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 2; ++i) {
+ CHECK_DIF_OK(dif_sensor_ctrl_alert_force(&sensor_ctrl, kDifSensorCtrlAlertRecovAlert + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSensorCtrlRecovAlert + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write uart's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_uart_alert_force(&smc_uart, kDifUartAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSmcUartFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write spi_device's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_spi_device_alert_force(&spi_device, kDifSpiDeviceAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSpiDeviceFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write spi_host's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host0, kDifSpiHostAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSpiHost0FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write spi_host's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host1, kDifSpiHostAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSpiHost1FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write spi_host's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host2, kDifSpiHostAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSpiHost2FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write sram_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_main, kDifSramCtrlAlertFatalError + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSramCtrlMainFatalError + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write sram_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_ret_aon, kDifSramCtrlAlertFatalError + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSramCtrlRetAonFatalError + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+#ifndef DISABLE_RENODE_TEST
+ // Write sysrst_ctrl's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_sysrst_ctrl_alert_force(&sysrst_ctrl_aon, kDifSysrstCtrlAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdSysrstCtrlAonFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+
+ // Write uart's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_uart_alert_force(&uart0, kDifUartAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdUart0FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write uart's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_uart_alert_force(&uart1, kDifUartAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdUart1FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write uart's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_uart_alert_force(&uart2, kDifUartAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdUart2FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+ // Write uart's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_uart_alert_force(&uart3, kDifUartAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdUart3FatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+
+#ifndef DISABLE_RENODE_TEST
+ // Write usbdev's alert_test reg and check alert_cause.
+ for (int i = 0; i < 1; ++i) {
+ CHECK_DIF_OK(dif_usbdev_alert_force(&usbdev, kDifUsbdevAlertFatalFault + i));
+
+ // Verify that alert handler received it.
+ exp_alert = kTopSenchaAlertIdUsbdevFatalFault + i;
+ CHECK_DIF_OK(dif_alert_handler_alert_is_cause(
+ &alert_handler, exp_alert, &is_cause));
+ CHECK(is_cause, "Expect alert %d!", exp_alert);
+
+ // Clear alert cause register
+ CHECK_DIF_OK(dif_alert_handler_alert_acknowledge(
+ &alert_handler, exp_alert));
+ }
+#endif
+}
+
+bool test_main(void) {
+ init_peripherals();
+ alert_handler_config();
+ trigger_alert_test();
+ return true;
+}
diff --git a/sw/device/tests/autogen/sencha/plic_all_irqs_test.c b/sw/device/tests/autogen/sencha/plic_all_irqs_test.c
new file mode 100644
index 0000000..5f6c86f
--- /dev/null
+++ b/sw/device/tests/autogen/sencha/plic_all_irqs_test.c
@@ -0,0 +1,1574 @@
+// Copyright 2024 Google LLC
+// Copyright lowRISC contributors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// clang-format off
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen_matcha.py -t hw/top_sencha/data/top_sencha.hjson
+// -o sw/device/tests/autogen
+#include <limits.h>
+
+#include "sw/device/lib/base/csr.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_adc_ctrl.h"
+#include "sw/device/lib/dif/dif_alert_handler.h"
+#include "sw/device/lib/dif/dif_aon_timer.h"
+#include "sw/device/lib/dif/dif_csrng.h"
+#include "sw/device/lib/dif/dif_edn.h"
+#include "sw/device/lib/dif/dif_entropy_src.h"
+#include "sw/device/lib/dif/dif_flash_ctrl.h"
+#include "sw/device/lib/dif/dif_gpio.h"
+#include "sw/device/lib/dif/dif_hmac.h"
+#include "sw/device/lib/dif/dif_i2c.h"
+#include "sw/device/lib/dif/dif_keymgr.h"
+#include "sw/device/lib/dif/dif_kmac.h"
+#include "sw/device/lib/dif/dif_otbn.h"
+#include "sw/device/lib/dif/dif_otp_ctrl.h"
+#include "sw/device/lib/dif/dif_pattgen.h"
+#include "sw/device/lib/dif/dif_pwrmgr.h"
+#include "sw/device/lib/dif/dif_rv_plic.h"
+#include "sw/device/lib/dif/dif_rv_timer.h"
+#include "sw/device/lib/dif/dif_sensor_ctrl.h"
+#include "sw/device/lib/dif/dif_spi_device.h"
+#include "sw/device/lib/dif/dif_spi_host.h"
+#include "sw/device/lib/dif/dif_sysrst_ctrl.h"
+#include "sw/device/lib/dif/dif_tlul_mailbox.h"
+#include "sw/device/lib/dif/dif_uart.h"
+#include "sw/device/lib/dif/dif_usbdev.h"
+#include "sw/device/lib/runtime/ibex.h"
+#include "sw/device/lib/runtime/irq.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/rv_plic_testutils.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+#include "sw/device/lib/testing/test_framework/status.h"
+#include "hw/top_sencha/sw/autogen/top_sencha.h"
+
+static dif_adc_ctrl_t adc_ctrl_aon;
+static dif_alert_handler_t alert_handler;
+static dif_aon_timer_t aon_timer_aon;
+static dif_csrng_t csrng;
+static dif_edn_t edn0;
+static dif_edn_t edn1;
+static dif_entropy_src_t entropy_src;
+static dif_flash_ctrl_t flash_ctrl;
+static dif_gpio_t gpio;
+static dif_hmac_t hmac;
+static dif_i2c_t i2c0;
+static dif_i2c_t i2c1;
+static dif_i2c_t i2c2;
+static dif_keymgr_t keymgr;
+static dif_kmac_t kmac;
+static dif_otbn_t otbn;
+static dif_otp_ctrl_t otp_ctrl;
+static dif_pattgen_t pattgen;
+static dif_pwrmgr_t pwrmgr_aon;
+static dif_rv_timer_t rv_timer;
+static dif_sensor_ctrl_t sensor_ctrl;
+static dif_spi_device_t spi_device;
+static dif_spi_host_t spi_host0;
+static dif_spi_host_t spi_host1;
+static dif_sysrst_ctrl_t sysrst_ctrl_aon;
+static dif_tlul_mailbox_t tlul_mailbox_sec;
+static dif_uart_t uart0;
+static dif_uart_t uart1;
+static dif_uart_t uart2;
+static dif_uart_t uart3;
+static dif_usbdev_t usbdev;
+static dif_rv_plic_t plic;
+static const top_sencha_plic_target_t kHart = kTopSenchaPlicTargetIbex0;
+
+/**
+ * Flag indicating which peripheral is under test.
+ *
+ * Declared volatile because it is referenced in the main program flow as well
+ * as the ISR.
+ */
+static volatile top_sencha_plic_peripheral_t peripheral_expected;
+
+/**
+ * Flags indicating the IRQ expected to have triggered and serviced within the
+ * peripheral.
+ *
+ * Declared volatile because it is referenced in the main program flow as well
+ * as the ISR.
+ */
+static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_expected;
+static volatile dif_adc_ctrl_irq_t adc_ctrl_irq_serviced;
+static volatile dif_alert_handler_irq_t alert_handler_irq_expected;
+static volatile dif_alert_handler_irq_t alert_handler_irq_serviced;
+static volatile dif_aon_timer_irq_t aon_timer_irq_expected;
+static volatile dif_aon_timer_irq_t aon_timer_irq_serviced;
+static volatile dif_csrng_irq_t csrng_irq_expected;
+static volatile dif_csrng_irq_t csrng_irq_serviced;
+static volatile dif_edn_irq_t edn_irq_expected;
+static volatile dif_edn_irq_t edn_irq_serviced;
+static volatile dif_entropy_src_irq_t entropy_src_irq_expected;
+static volatile dif_entropy_src_irq_t entropy_src_irq_serviced;
+static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_expected;
+static volatile dif_flash_ctrl_irq_t flash_ctrl_irq_serviced;
+static volatile dif_gpio_irq_t gpio_irq_expected;
+static volatile dif_gpio_irq_t gpio_irq_serviced;
+static volatile dif_hmac_irq_t hmac_irq_expected;
+static volatile dif_hmac_irq_t hmac_irq_serviced;
+static volatile dif_i2c_irq_t i2c_irq_expected;
+static volatile dif_i2c_irq_t i2c_irq_serviced;
+static volatile dif_keymgr_irq_t keymgr_irq_expected;
+static volatile dif_keymgr_irq_t keymgr_irq_serviced;
+static volatile dif_kmac_irq_t kmac_irq_expected;
+static volatile dif_kmac_irq_t kmac_irq_serviced;
+static volatile dif_otbn_irq_t otbn_irq_expected;
+static volatile dif_otbn_irq_t otbn_irq_serviced;
+static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected;
+static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced;
+static volatile dif_pattgen_irq_t pattgen_irq_expected;
+static volatile dif_pattgen_irq_t pattgen_irq_serviced;
+static volatile dif_pwrmgr_irq_t pwrmgr_irq_expected;
+static volatile dif_pwrmgr_irq_t pwrmgr_irq_serviced;
+static volatile dif_rv_timer_irq_t rv_timer_irq_expected;
+static volatile dif_rv_timer_irq_t rv_timer_irq_serviced;
+static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_expected;
+static volatile dif_sensor_ctrl_irq_t sensor_ctrl_irq_serviced;
+static volatile dif_spi_device_irq_t spi_device_irq_expected;
+static volatile dif_spi_device_irq_t spi_device_irq_serviced;
+static volatile dif_spi_host_irq_t spi_host_irq_expected;
+static volatile dif_spi_host_irq_t spi_host_irq_serviced;
+static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_expected;
+static volatile dif_sysrst_ctrl_irq_t sysrst_ctrl_irq_serviced;
+static volatile dif_tlul_mailbox_irq_t tlul_mailbox_irq_expected;
+static volatile dif_tlul_mailbox_irq_t tlul_mailbox_irq_serviced;
+static volatile dif_uart_irq_t uart_irq_expected;
+static volatile dif_uart_irq_t uart_irq_serviced;
+static volatile dif_usbdev_irq_t usbdev_irq_expected;
+static volatile dif_usbdev_irq_t usbdev_irq_serviced;
+
+/**
+ * Provides external IRQ handling for this test.
+ *
+ * This function overrides the default OTTF external ISR.
+ *
+ * For each IRQ, it performs the following:
+ * 1. Claims the IRQ fired (finds PLIC IRQ index).
+ * 2. Checks that the index belongs to the expected peripheral.
+ * 3. Checks that the correct and the only IRQ from the expected peripheral
+ * triggered.
+ * 4. Clears the IRQ at the peripheral.
+ * 5. Completes the IRQ service at PLIC.
+ */
+void ottf_external_isr(void) {
+ dif_rv_plic_irq_id_t plic_irq_id;
+ CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id));
+
+ top_sencha_plic_peripheral_t peripheral = (top_sencha_plic_peripheral_t)
+ top_sencha_plic_interrupt_for_peripheral[plic_irq_id];
+ CHECK(peripheral == peripheral_expected,
+ "Interrupt from incorrect peripheral: exp = %d, obs = %d",
+ peripheral_expected, peripheral);
+
+ switch (peripheral) {
+ case kTopSenchaPlicPeripheralAdcCtrlAon: {
+ dif_adc_ctrl_irq_t irq = (dif_adc_ctrl_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdAdcCtrlAonMatchDone);
+ CHECK(irq == adc_ctrl_irq_expected,
+ "Incorrect adc_ctrl_aon IRQ triggered: exp = %d, obs = %d",
+ adc_ctrl_irq_expected, irq);
+ adc_ctrl_irq_serviced = irq;
+
+ dif_adc_ctrl_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_adc_ctrl_irq_get_state(&adc_ctrl_aon, &snapshot));
+ CHECK(snapshot == (dif_adc_ctrl_irq_state_snapshot_t)(1 << irq),
+ "Only adc_ctrl_aon IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_adc_ctrl_irq_force(&adc_ctrl_aon, irq, false));
+ CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge(&adc_ctrl_aon, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralAlertHandler: {
+ dif_alert_handler_irq_t irq = (dif_alert_handler_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdAlertHandlerClassa);
+ CHECK(irq == alert_handler_irq_expected,
+ "Incorrect alert_handler IRQ triggered: exp = %d, obs = %d",
+ alert_handler_irq_expected, irq);
+ alert_handler_irq_serviced = irq;
+
+ dif_alert_handler_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_alert_handler_irq_get_state(&alert_handler, &snapshot));
+ CHECK(snapshot == (dif_alert_handler_irq_state_snapshot_t)(1 << irq),
+ "Only alert_handler IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_alert_handler_irq_force(&alert_handler, irq, false));
+ CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralAonTimerAon: {
+ dif_aon_timer_irq_t irq = (dif_aon_timer_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdAonTimerAonWkupTimerExpired);
+ CHECK(irq == aon_timer_irq_expected,
+ "Incorrect aon_timer_aon IRQ triggered: exp = %d, obs = %d",
+ aon_timer_irq_expected, irq);
+ aon_timer_irq_serviced = irq;
+
+ dif_aon_timer_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_aon_timer_irq_get_state(&aon_timer_aon, &snapshot));
+ CHECK(snapshot == (dif_aon_timer_irq_state_snapshot_t)(1 << irq),
+ "Only aon_timer_aon IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_aon_timer_irq_force(&aon_timer_aon, irq, false));
+ CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(&aon_timer_aon, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralCsrng: {
+ dif_csrng_irq_t irq = (dif_csrng_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdCsrngCsCmdReqDone);
+ CHECK(irq == csrng_irq_expected,
+ "Incorrect csrng IRQ triggered: exp = %d, obs = %d",
+ csrng_irq_expected, irq);
+ csrng_irq_serviced = irq;
+
+ dif_csrng_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_csrng_irq_get_state(&csrng, &snapshot));
+ CHECK(snapshot == (dif_csrng_irq_state_snapshot_t)(1 << irq),
+ "Only csrng IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, false));
+ CHECK_DIF_OK(dif_csrng_irq_acknowledge(&csrng, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralEdn0: {
+ dif_edn_irq_t irq = (dif_edn_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdEdn0EdnCmdReqDone);
+ CHECK(irq == edn_irq_expected,
+ "Incorrect edn0 IRQ triggered: exp = %d, obs = %d",
+ edn_irq_expected, irq);
+ edn_irq_serviced = irq;
+
+ dif_edn_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_edn_irq_get_state(&edn0, &snapshot));
+ CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq),
+ "Only edn0 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_edn_irq_force(&edn0, irq, false));
+ CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn0, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralEdn1: {
+ dif_edn_irq_t irq = (dif_edn_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdEdn1EdnCmdReqDone);
+ CHECK(irq == edn_irq_expected,
+ "Incorrect edn1 IRQ triggered: exp = %d, obs = %d",
+ edn_irq_expected, irq);
+ edn_irq_serviced = irq;
+
+ dif_edn_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_edn_irq_get_state(&edn1, &snapshot));
+ CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq),
+ "Only edn1 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_edn_irq_force(&edn1, irq, false));
+ CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn1, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralEntropySrc: {
+ dif_entropy_src_irq_t irq = (dif_entropy_src_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdEntropySrcEsEntropyValid);
+ CHECK(irq == entropy_src_irq_expected,
+ "Incorrect entropy_src IRQ triggered: exp = %d, obs = %d",
+ entropy_src_irq_expected, irq);
+ entropy_src_irq_serviced = irq;
+
+ dif_entropy_src_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_entropy_src_irq_get_state(&entropy_src, &snapshot));
+ CHECK(snapshot == (dif_entropy_src_irq_state_snapshot_t)(1 << irq),
+ "Only entropy_src IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_entropy_src_irq_force(&entropy_src, irq, false));
+ CHECK_DIF_OK(dif_entropy_src_irq_acknowledge(&entropy_src, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralFlashCtrl: {
+ dif_flash_ctrl_irq_t irq = (dif_flash_ctrl_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdFlashCtrlProgEmpty);
+ CHECK(irq == flash_ctrl_irq_expected,
+ "Incorrect flash_ctrl IRQ triggered: exp = %d, obs = %d",
+ flash_ctrl_irq_expected, irq);
+ flash_ctrl_irq_serviced = irq;
+
+ dif_flash_ctrl_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_flash_ctrl_irq_get_state(&flash_ctrl, &snapshot));
+ CHECK(snapshot == (dif_flash_ctrl_irq_state_snapshot_t)(1 << irq),
+ "Only flash_ctrl IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_flash_ctrl_irq_force(&flash_ctrl, irq, false));
+ CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge(&flash_ctrl, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralGpio: {
+ dif_gpio_irq_t irq = (dif_gpio_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdGpioGpio0);
+ CHECK(irq == gpio_irq_expected,
+ "Incorrect gpio IRQ triggered: exp = %d, obs = %d",
+ gpio_irq_expected, irq);
+ gpio_irq_serviced = irq;
+
+ dif_gpio_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_gpio_irq_get_state(&gpio, &snapshot));
+ CHECK(snapshot == (dif_gpio_irq_state_snapshot_t)(1 << irq),
+ "Only gpio IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_gpio_irq_force(&gpio, irq, false));
+ CHECK_DIF_OK(dif_gpio_irq_acknowledge(&gpio, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralHmac: {
+ dif_hmac_irq_t irq = (dif_hmac_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdHmacHmacDone);
+ CHECK(irq == hmac_irq_expected,
+ "Incorrect hmac IRQ triggered: exp = %d, obs = %d",
+ hmac_irq_expected, irq);
+ hmac_irq_serviced = irq;
+
+ dif_hmac_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_hmac_irq_get_state(&hmac, &snapshot));
+ CHECK(snapshot == (dif_hmac_irq_state_snapshot_t)(1 << irq),
+ "Only hmac IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, false));
+ CHECK_DIF_OK(dif_hmac_irq_acknowledge(&hmac, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralI2c0: {
+ dif_i2c_irq_t irq = (dif_i2c_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdI2c0FmtThreshold);
+ CHECK(irq == i2c_irq_expected,
+ "Incorrect i2c0 IRQ triggered: exp = %d, obs = %d",
+ i2c_irq_expected, irq);
+ i2c_irq_serviced = irq;
+
+ dif_i2c_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c0, &snapshot));
+ CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq),
+ "Only i2c0 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, false));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c0, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralI2c1: {
+ dif_i2c_irq_t irq = (dif_i2c_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdI2c1FmtThreshold);
+ CHECK(irq == i2c_irq_expected,
+ "Incorrect i2c1 IRQ triggered: exp = %d, obs = %d",
+ i2c_irq_expected, irq);
+ i2c_irq_serviced = irq;
+
+ dif_i2c_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c1, &snapshot));
+ CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq),
+ "Only i2c1 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c1, irq, false));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c1, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralI2c2: {
+ dif_i2c_irq_t irq = (dif_i2c_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdI2c2FmtThreshold);
+ CHECK(irq == i2c_irq_expected,
+ "Incorrect i2c2 IRQ triggered: exp = %d, obs = %d",
+ i2c_irq_expected, irq);
+ i2c_irq_serviced = irq;
+
+ dif_i2c_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c2, &snapshot));
+ CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq),
+ "Only i2c2 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c2, irq, false));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c2, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralKeymgr: {
+ dif_keymgr_irq_t irq = (dif_keymgr_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdKeymgrOpDone);
+ CHECK(irq == keymgr_irq_expected,
+ "Incorrect keymgr IRQ triggered: exp = %d, obs = %d",
+ keymgr_irq_expected, irq);
+ keymgr_irq_serviced = irq;
+
+ dif_keymgr_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_keymgr_irq_get_state(&keymgr, &snapshot));
+ CHECK(snapshot == (dif_keymgr_irq_state_snapshot_t)(1 << irq),
+ "Only keymgr IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_keymgr_irq_force(&keymgr, irq, false));
+ CHECK_DIF_OK(dif_keymgr_irq_acknowledge(&keymgr, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralKmac: {
+ dif_kmac_irq_t irq = (dif_kmac_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdKmacKmacDone);
+ CHECK(irq == kmac_irq_expected,
+ "Incorrect kmac IRQ triggered: exp = %d, obs = %d",
+ kmac_irq_expected, irq);
+ kmac_irq_serviced = irq;
+
+ dif_kmac_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_kmac_irq_get_state(&kmac, &snapshot));
+ CHECK(snapshot == (dif_kmac_irq_state_snapshot_t)(1 << irq),
+ "Only kmac IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, false));
+ CHECK_DIF_OK(dif_kmac_irq_acknowledge(&kmac, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralOtbn: {
+ dif_otbn_irq_t irq = (dif_otbn_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdOtbnDone);
+ CHECK(irq == otbn_irq_expected,
+ "Incorrect otbn IRQ triggered: exp = %d, obs = %d",
+ otbn_irq_expected, irq);
+ otbn_irq_serviced = irq;
+
+ dif_otbn_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &snapshot));
+ CHECK(snapshot == (dif_otbn_irq_state_snapshot_t)(1 << irq),
+ "Only otbn IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, false));
+ CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralOtpCtrl: {
+ dif_otp_ctrl_irq_t irq = (dif_otp_ctrl_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdOtpCtrlOtpOperationDone);
+ CHECK(irq == otp_ctrl_irq_expected,
+ "Incorrect otp_ctrl IRQ triggered: exp = %d, obs = %d",
+ otp_ctrl_irq_expected, irq);
+ otp_ctrl_irq_serviced = irq;
+
+ dif_otp_ctrl_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(&otp_ctrl, &snapshot));
+ CHECK(snapshot == (dif_otp_ctrl_irq_state_snapshot_t)(1 << irq),
+ "Only otp_ctrl IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl, irq, false));
+ CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(&otp_ctrl, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralPattgen: {
+ dif_pattgen_irq_t irq = (dif_pattgen_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdPattgenDoneCh0);
+ CHECK(irq == pattgen_irq_expected,
+ "Incorrect pattgen IRQ triggered: exp = %d, obs = %d",
+ pattgen_irq_expected, irq);
+ pattgen_irq_serviced = irq;
+
+ dif_pattgen_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_pattgen_irq_get_state(&pattgen, &snapshot));
+ CHECK(snapshot == (dif_pattgen_irq_state_snapshot_t)(1 << irq),
+ "Only pattgen IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_pattgen_irq_force(&pattgen, irq, false));
+ CHECK_DIF_OK(dif_pattgen_irq_acknowledge(&pattgen, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralPwrmgrAon: {
+ dif_pwrmgr_irq_t irq = (dif_pwrmgr_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdPwrmgrAonWakeup);
+ CHECK(irq == pwrmgr_irq_expected,
+ "Incorrect pwrmgr_aon IRQ triggered: exp = %d, obs = %d",
+ pwrmgr_irq_expected, irq);
+ pwrmgr_irq_serviced = irq;
+
+ dif_pwrmgr_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_aon, &snapshot));
+ CHECK(snapshot == (dif_pwrmgr_irq_state_snapshot_t)(1 << irq),
+ "Only pwrmgr_aon IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_aon, irq, false));
+ CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(&pwrmgr_aon, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralRvTimer: {
+ dif_rv_timer_irq_t irq = (dif_rv_timer_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdRvTimerTimerExpiredHart0Timer0);
+ CHECK(irq == rv_timer_irq_expected,
+ "Incorrect rv_timer IRQ triggered: exp = %d, obs = %d",
+ rv_timer_irq_expected, irq);
+ rv_timer_irq_serviced = irq;
+
+ dif_rv_timer_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_rv_timer_irq_get_state(&rv_timer, kHart, &snapshot));
+ CHECK(snapshot == (dif_rv_timer_irq_state_snapshot_t)(1 << irq),
+ "Only rv_timer IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_rv_timer_irq_force(&rv_timer, irq, false));
+ CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(&rv_timer, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralSensorCtrl: {
+ dif_sensor_ctrl_irq_t irq = (dif_sensor_ctrl_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdSensorCtrlIoStatusChange);
+ CHECK(irq == sensor_ctrl_irq_expected,
+ "Incorrect sensor_ctrl IRQ triggered: exp = %d, obs = %d",
+ sensor_ctrl_irq_expected, irq);
+ sensor_ctrl_irq_serviced = irq;
+
+ dif_sensor_ctrl_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_sensor_ctrl_irq_get_state(&sensor_ctrl, &snapshot));
+ CHECK(snapshot == (dif_sensor_ctrl_irq_state_snapshot_t)(1 << irq),
+ "Only sensor_ctrl IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_sensor_ctrl_irq_force(&sensor_ctrl, irq, false));
+ CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge(&sensor_ctrl, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralSpiDevice: {
+ dif_spi_device_irq_t irq = (dif_spi_device_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdSpiDeviceGenericRxFull);
+ CHECK(irq == spi_device_irq_expected,
+ "Incorrect spi_device IRQ triggered: exp = %d, obs = %d",
+ spi_device_irq_expected, irq);
+ spi_device_irq_serviced = irq;
+
+ dif_spi_device_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_spi_device_irq_get_state(&spi_device, &snapshot));
+ CHECK(snapshot == (dif_spi_device_irq_state_snapshot_t)(1 << irq),
+ "Only spi_device IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, false));
+ CHECK_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralSpiHost0: {
+ dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdSpiHost0Error);
+ CHECK(irq == spi_host_irq_expected,
+ "Incorrect spi_host0 IRQ triggered: exp = %d, obs = %d",
+ spi_host_irq_expected, irq);
+ spi_host_irq_serviced = irq;
+
+ dif_spi_host_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host0, &snapshot));
+ CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq),
+ "Only spi_host0 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, false));
+ CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host0, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralSpiHost1: {
+ dif_spi_host_irq_t irq = (dif_spi_host_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdSpiHost1Error);
+ CHECK(irq == spi_host_irq_expected,
+ "Incorrect spi_host1 IRQ triggered: exp = %d, obs = %d",
+ spi_host_irq_expected, irq);
+ spi_host_irq_serviced = irq;
+
+ dif_spi_host_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host1, &snapshot));
+ CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq),
+ "Only spi_host1 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host1, irq, false));
+ CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host1, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralSysrstCtrlAon: {
+ dif_sysrst_ctrl_irq_t irq = (dif_sysrst_ctrl_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdSysrstCtrlAonEventDetected);
+ CHECK(irq == sysrst_ctrl_irq_expected,
+ "Incorrect sysrst_ctrl_aon IRQ triggered: exp = %d, obs = %d",
+ sysrst_ctrl_irq_expected, irq);
+ sysrst_ctrl_irq_serviced = irq;
+
+ dif_sysrst_ctrl_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_aon, &snapshot));
+ CHECK(snapshot == (dif_sysrst_ctrl_irq_state_snapshot_t)(1 << irq),
+ "Only sysrst_ctrl_aon IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_sysrst_ctrl_irq_force(&sysrst_ctrl_aon, irq, false));
+ CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge(&sysrst_ctrl_aon, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralTlulMailboxSec: {
+ dif_tlul_mailbox_irq_t irq = (dif_tlul_mailbox_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdTlulMailboxSecWtirq);
+ CHECK(irq == tlul_mailbox_irq_expected,
+ "Incorrect tlul_mailbox_sec IRQ triggered: exp = %d, obs = %d",
+ tlul_mailbox_irq_expected, irq);
+ tlul_mailbox_irq_serviced = irq;
+
+ dif_tlul_mailbox_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_tlul_mailbox_irq_get_state(&tlul_mailbox_sec, &snapshot));
+ CHECK(snapshot == (dif_tlul_mailbox_irq_state_snapshot_t)(1 << irq),
+ "Only tlul_mailbox_sec IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_tlul_mailbox_irq_force(&tlul_mailbox_sec, irq, false));
+ CHECK_DIF_OK(dif_tlul_mailbox_irq_acknowledge(&tlul_mailbox_sec, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralUart0: {
+ dif_uart_irq_t irq = (dif_uart_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdUart0TxWatermark);
+ CHECK(irq == uart_irq_expected,
+ "Incorrect uart0 IRQ triggered: exp = %d, obs = %d",
+ uart_irq_expected, irq);
+ uart_irq_serviced = irq;
+
+ dif_uart_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_uart_irq_get_state(&uart0, &snapshot));
+ CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq),
+ "Only uart0 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, false));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart0, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralUart1: {
+ dif_uart_irq_t irq = (dif_uart_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdUart1TxWatermark);
+ CHECK(irq == uart_irq_expected,
+ "Incorrect uart1 IRQ triggered: exp = %d, obs = %d",
+ uart_irq_expected, irq);
+ uart_irq_serviced = irq;
+
+ dif_uart_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_uart_irq_get_state(&uart1, &snapshot));
+ CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq),
+ "Only uart1 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_uart_irq_force(&uart1, irq, false));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart1, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralUart2: {
+ dif_uart_irq_t irq = (dif_uart_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdUart2TxWatermark);
+ CHECK(irq == uart_irq_expected,
+ "Incorrect uart2 IRQ triggered: exp = %d, obs = %d",
+ uart_irq_expected, irq);
+ uart_irq_serviced = irq;
+
+ dif_uart_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_uart_irq_get_state(&uart2, &snapshot));
+ CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq),
+ "Only uart2 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_uart_irq_force(&uart2, irq, false));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart2, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralUart3: {
+ dif_uart_irq_t irq = (dif_uart_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdUart3TxWatermark);
+ CHECK(irq == uart_irq_expected,
+ "Incorrect uart3 IRQ triggered: exp = %d, obs = %d",
+ uart_irq_expected, irq);
+ uart_irq_serviced = irq;
+
+ dif_uart_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_uart_irq_get_state(&uart3, &snapshot));
+ CHECK(snapshot == (dif_uart_irq_state_snapshot_t)(1 << irq),
+ "Only uart3 IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_uart_irq_force(&uart3, irq, false));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart3, irq));
+ break;
+ }
+
+ case kTopSenchaPlicPeripheralUsbdev: {
+ dif_usbdev_irq_t irq = (dif_usbdev_irq_t)(
+ plic_irq_id -
+ (dif_rv_plic_irq_id_t)kTopSenchaPlicIrqIdUsbdevPktReceived);
+ CHECK(irq == usbdev_irq_expected,
+ "Incorrect usbdev IRQ triggered: exp = %d, obs = %d",
+ usbdev_irq_expected, irq);
+ usbdev_irq_serviced = irq;
+
+ dif_usbdev_irq_state_snapshot_t snapshot;
+ CHECK_DIF_OK(dif_usbdev_irq_get_state(&usbdev, &snapshot));
+ CHECK(snapshot == (dif_usbdev_irq_state_snapshot_t)(1 << irq),
+ "Only usbdev IRQ %d expected to fire. Actual interrupt "
+ "status = %x",
+ irq, snapshot);
+
+ // TODO: Check Interrupt type then clear INTR_TEST if needed.
+ CHECK_DIF_OK(dif_usbdev_irq_force(&usbdev, irq, false));
+ CHECK_DIF_OK(dif_usbdev_irq_acknowledge(&usbdev, irq));
+ break;
+ }
+
+ default:
+ LOG_FATAL("ISR is not implemented!");
+ test_status_set(kTestStatusFailed);
+ }
+
+ // Complete the IRQ at PLIC.
+ CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id));
+}
+
+/**
+ * Initializes the handles to all peripherals.
+ */
+static void peripherals_init(void) {
+ mmio_region_t base_addr;
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ADC_CTRL_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_adc_ctrl_init(base_addr, &adc_ctrl_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ALERT_HANDLER_BASE_ADDR);
+ CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_AON_TIMER_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_CSRNG_BASE_ADDR);
+ CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_EDN0_BASE_ADDR);
+ CHECK_DIF_OK(dif_edn_init(base_addr, &edn0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_EDN1_BASE_ADDR);
+ CHECK_DIF_OK(dif_edn_init(base_addr, &edn1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_ENTROPY_SRC_BASE_ADDR);
+ CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_FLASH_CTRL_CORE_BASE_ADDR);
+ CHECK_DIF_OK(dif_flash_ctrl_init(base_addr, &flash_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_GPIO_BASE_ADDR);
+ CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_HMAC_BASE_ADDR);
+ CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C0_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C1_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_I2C2_BASE_ADDR);
+ CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c2));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_KEYMGR_BASE_ADDR);
+ CHECK_DIF_OK(dif_keymgr_init(base_addr, &keymgr));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_KMAC_BASE_ADDR);
+ CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_OTBN_BASE_ADDR);
+ CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_OTP_CTRL_CORE_BASE_ADDR);
+ CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PATTGEN_BASE_ADDR);
+ CHECK_DIF_OK(dif_pattgen_init(base_addr, &pattgen));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_PWRMGR_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RV_TIMER_BASE_ADDR);
+ CHECK_DIF_OK(dif_rv_timer_init(base_addr, &rv_timer));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SENSOR_CTRL_BASE_ADDR);
+ CHECK_DIF_OK(dif_sensor_ctrl_init(base_addr, &sensor_ctrl));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_DEVICE_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_HOST0_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SPI_HOST1_BASE_ADDR);
+ CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_SYSRST_CTRL_AON_BASE_ADDR);
+ CHECK_DIF_OK(dif_sysrst_ctrl_init(base_addr, &sysrst_ctrl_aon));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_TLUL_MAILBOX_SEC_BASE_ADDR);
+ CHECK_DIF_OK(dif_tlul_mailbox_init(base_addr, &tlul_mailbox_sec));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART0_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart0));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART1_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart1));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART2_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart2));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_UART3_BASE_ADDR);
+ CHECK_DIF_OK(dif_uart_init(base_addr, &uart3));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_USBDEV_BASE_ADDR);
+ CHECK_DIF_OK(dif_usbdev_init(base_addr, &usbdev));
+
+ base_addr = mmio_region_from_addr(TOP_SENCHA_RV_PLIC_BASE_ADDR);
+ CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic));
+}
+
+/**
+ * Clears pending IRQs in all peripherals.
+ */
+static void peripheral_irqs_clear(void) {
+ CHECK_DIF_OK(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_aon));
+ CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler));
+ CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon));
+ CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng));
+ CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn0));
+ CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn1));
+ CHECK_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src));
+ CHECK_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl));
+ CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio));
+ CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c1));
+ CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c2));
+ CHECK_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr));
+ CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac));
+ CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn));
+ CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl));
+ CHECK_DIF_OK(dif_pattgen_irq_acknowledge_all(&pattgen));
+ CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_aon));
+ CHECK_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer, kHart));
+ CHECK_DIF_OK(dif_sensor_ctrl_irq_acknowledge_all(&sensor_ctrl));
+ CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device));
+ CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0));
+ CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host1));
+ CHECK_DIF_OK(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl_aon));
+ CHECK_DIF_OK(dif_tlul_mailbox_irq_acknowledge_all(&tlul_mailbox_sec));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart1));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart2));
+ CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart3));
+ CHECK_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev));
+}
+
+/**
+ * Enables all IRQs in all peripherals.
+ */
+static void peripheral_irqs_enable(void) {
+ dif_adc_ctrl_irq_state_snapshot_t adc_ctrl_irqs =
+ (dif_adc_ctrl_irq_state_snapshot_t)UINT_MAX;
+ dif_alert_handler_irq_state_snapshot_t alert_handler_irqs =
+ (dif_alert_handler_irq_state_snapshot_t)UINT_MAX;
+ dif_csrng_irq_state_snapshot_t csrng_irqs =
+ (dif_csrng_irq_state_snapshot_t)UINT_MAX;
+ dif_edn_irq_state_snapshot_t edn_irqs =
+ (dif_edn_irq_state_snapshot_t)UINT_MAX;
+ dif_entropy_src_irq_state_snapshot_t entropy_src_irqs =
+ (dif_entropy_src_irq_state_snapshot_t)UINT_MAX;
+ dif_flash_ctrl_irq_state_snapshot_t flash_ctrl_irqs =
+ (dif_flash_ctrl_irq_state_snapshot_t)UINT_MAX;
+ dif_gpio_irq_state_snapshot_t gpio_irqs =
+ (dif_gpio_irq_state_snapshot_t)UINT_MAX;
+ dif_hmac_irq_state_snapshot_t hmac_irqs =
+ (dif_hmac_irq_state_snapshot_t)UINT_MAX;
+ dif_i2c_irq_state_snapshot_t i2c_irqs =
+ (dif_i2c_irq_state_snapshot_t)UINT_MAX;
+ dif_keymgr_irq_state_snapshot_t keymgr_irqs =
+ (dif_keymgr_irq_state_snapshot_t)UINT_MAX;
+ dif_kmac_irq_state_snapshot_t kmac_irqs =
+ (dif_kmac_irq_state_snapshot_t)UINT_MAX;
+ dif_otbn_irq_state_snapshot_t otbn_irqs =
+ (dif_otbn_irq_state_snapshot_t)UINT_MAX;
+ dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs =
+ (dif_otp_ctrl_irq_state_snapshot_t)UINT_MAX;
+ dif_pattgen_irq_state_snapshot_t pattgen_irqs =
+ (dif_pattgen_irq_state_snapshot_t)UINT_MAX;
+ dif_pwrmgr_irq_state_snapshot_t pwrmgr_irqs =
+ (dif_pwrmgr_irq_state_snapshot_t)UINT_MAX;
+ dif_rv_timer_irq_state_snapshot_t rv_timer_irqs =
+ (dif_rv_timer_irq_state_snapshot_t)UINT_MAX;
+ dif_sensor_ctrl_irq_state_snapshot_t sensor_ctrl_irqs =
+ (dif_sensor_ctrl_irq_state_snapshot_t)UINT_MAX;
+ dif_spi_device_irq_state_snapshot_t spi_device_irqs =
+ (dif_spi_device_irq_state_snapshot_t)UINT_MAX;
+ dif_spi_host_irq_state_snapshot_t spi_host_irqs =
+ (dif_spi_host_irq_state_snapshot_t)UINT_MAX;
+ dif_sysrst_ctrl_irq_state_snapshot_t sysrst_ctrl_irqs =
+ (dif_sysrst_ctrl_irq_state_snapshot_t)UINT_MAX;
+ dif_tlul_mailbox_irq_state_snapshot_t tlul_mailbox_irqs =
+ (dif_tlul_mailbox_irq_state_snapshot_t)UINT_MAX;
+ dif_uart_irq_state_snapshot_t uart_irqs =
+ (dif_uart_irq_state_snapshot_t)UINT_MAX;
+ dif_usbdev_irq_state_snapshot_t usbdev_irqs =
+ (dif_usbdev_irq_state_snapshot_t)UINT_MAX;
+
+ CHECK_DIF_OK(
+ dif_adc_ctrl_irq_restore_all(&adc_ctrl_aon, &adc_ctrl_irqs));
+ CHECK_DIF_OK(
+ dif_alert_handler_irq_restore_all(&alert_handler, &alert_handler_irqs));
+ CHECK_DIF_OK(
+ dif_csrng_irq_restore_all(&csrng, &csrng_irqs));
+ CHECK_DIF_OK(
+ dif_edn_irq_restore_all(&edn0, &edn_irqs));
+ CHECK_DIF_OK(
+ dif_edn_irq_restore_all(&edn1, &edn_irqs));
+ CHECK_DIF_OK(
+ dif_entropy_src_irq_restore_all(&entropy_src, &entropy_src_irqs));
+ CHECK_DIF_OK(
+ dif_flash_ctrl_irq_restore_all(&flash_ctrl, &flash_ctrl_irqs));
+ CHECK_DIF_OK(
+ dif_gpio_irq_restore_all(&gpio, &gpio_irqs));
+ CHECK_DIF_OK(
+ dif_hmac_irq_restore_all(&hmac, &hmac_irqs));
+ CHECK_DIF_OK(
+ dif_i2c_irq_restore_all(&i2c0, &i2c_irqs));
+ CHECK_DIF_OK(
+ dif_i2c_irq_restore_all(&i2c1, &i2c_irqs));
+ CHECK_DIF_OK(
+ dif_i2c_irq_restore_all(&i2c2, &i2c_irqs));
+ CHECK_DIF_OK(
+ dif_keymgr_irq_restore_all(&keymgr, &keymgr_irqs));
+ CHECK_DIF_OK(
+ dif_kmac_irq_restore_all(&kmac, &kmac_irqs));
+ CHECK_DIF_OK(
+ dif_otbn_irq_restore_all(&otbn, &otbn_irqs));
+ CHECK_DIF_OK(
+ dif_otp_ctrl_irq_restore_all(&otp_ctrl, &otp_ctrl_irqs));
+ CHECK_DIF_OK(
+ dif_pattgen_irq_restore_all(&pattgen, &pattgen_irqs));
+ CHECK_DIF_OK(
+ dif_pwrmgr_irq_restore_all(&pwrmgr_aon, &pwrmgr_irqs));
+ CHECK_DIF_OK(
+ dif_rv_timer_irq_restore_all(&rv_timer, kHart, &rv_timer_irqs));
+ CHECK_DIF_OK(
+ dif_sensor_ctrl_irq_restore_all(&sensor_ctrl, &sensor_ctrl_irqs));
+ CHECK_DIF_OK(
+ dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs));
+ CHECK_DIF_OK(
+ dif_spi_host_irq_restore_all(&spi_host0, &spi_host_irqs));
+ CHECK_DIF_OK(
+ dif_spi_host_irq_restore_all(&spi_host1, &spi_host_irqs));
+ CHECK_DIF_OK(
+ dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_aon, &sysrst_ctrl_irqs));
+ CHECK_DIF_OK(
+ dif_tlul_mailbox_irq_restore_all(&tlul_mailbox_sec, &tlul_mailbox_irqs));
+ // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference
+ // from the logging facility.
+ if (kDeviceType == kDeviceSimDV) {
+ CHECK_DIF_OK(
+ dif_uart_irq_restore_all(&uart0, &uart_irqs));
+ }
+ CHECK_DIF_OK(
+ dif_uart_irq_restore_all(&uart1, &uart_irqs));
+ CHECK_DIF_OK(
+ dif_uart_irq_restore_all(&uart2, &uart_irqs));
+ CHECK_DIF_OK(
+ dif_uart_irq_restore_all(&uart3, &uart_irqs));
+ CHECK_DIF_OK(
+ dif_usbdev_irq_restore_all(&usbdev, &usbdev_irqs));
+}
+
+/**
+ * Triggers all IRQs in all peripherals one by one.
+ *
+ * Walks through all instances of all peripherals and triggers an interrupt one
+ * by one, by forcing with the `intr_test` CSR. On trigger, the CPU instantly
+ * jumps into the ISR. The main flow of execution thus proceeds to check that
+ * the correct IRQ was serviced immediately. The ISR, in turn checks if the
+ * expected IRQ from the expected peripheral triggered.
+ */
+static void peripheral_irqs_trigger(void) {
+ peripheral_expected = kTopSenchaPlicPeripheralAdcCtrlAon;
+ for (dif_adc_ctrl_irq_t irq = kDifAdcCtrlIrqMatchDone;
+ irq <= kDifAdcCtrlIrqMatchDone; ++irq) {
+ adc_ctrl_irq_expected = irq;
+ LOG_INFO("Triggering adc_ctrl_aon IRQ %d.", irq);
+ CHECK_DIF_OK(dif_adc_ctrl_irq_force(&adc_ctrl_aon, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(adc_ctrl_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from adc_ctrl_aon is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralAlertHandler;
+ for (dif_alert_handler_irq_t irq = kDifAlertHandlerIrqClassa;
+ irq <= kDifAlertHandlerIrqClassd; ++irq) {
+ alert_handler_irq_expected = irq;
+ LOG_INFO("Triggering alert_handler IRQ %d.", irq);
+ CHECK_DIF_OK(dif_alert_handler_irq_force(&alert_handler, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(alert_handler_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from alert_handler is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralAonTimerAon;
+ for (dif_aon_timer_irq_t irq = kDifAonTimerIrqWkupTimerExpired;
+ irq <= kDifAonTimerIrqWdogTimerBark; ++irq) {
+ aon_timer_irq_expected = irq;
+ LOG_INFO("Triggering aon_timer_aon IRQ %d.", irq);
+ CHECK_DIF_OK(dif_aon_timer_irq_force(&aon_timer_aon, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(aon_timer_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from aon_timer_aon is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralCsrng;
+ for (dif_csrng_irq_t irq = kDifCsrngIrqCsCmdReqDone;
+ irq <= kDifCsrngIrqCsFatalErr; ++irq) {
+ csrng_irq_expected = irq;
+ LOG_INFO("Triggering csrng IRQ %d.", irq);
+ CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(csrng_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from csrng is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralEdn0;
+ for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone;
+ irq <= kDifEdnIrqEdnFatalErr; ++irq) {
+ edn_irq_expected = irq;
+ LOG_INFO("Triggering edn0 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_edn_irq_force(&edn0, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(edn_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from edn0 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralEdn1;
+ for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone;
+ irq <= kDifEdnIrqEdnFatalErr; ++irq) {
+ edn_irq_expected = irq;
+ LOG_INFO("Triggering edn1 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_edn_irq_force(&edn1, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(edn_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from edn1 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralEntropySrc;
+ for (dif_entropy_src_irq_t irq = kDifEntropySrcIrqEsEntropyValid;
+ irq <= kDifEntropySrcIrqEsFatalErr; ++irq) {
+ entropy_src_irq_expected = irq;
+ LOG_INFO("Triggering entropy_src IRQ %d.", irq);
+ CHECK_DIF_OK(dif_entropy_src_irq_force(&entropy_src, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(entropy_src_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from entropy_src is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralFlashCtrl;
+ for (dif_flash_ctrl_irq_t irq = kDifFlashCtrlIrqProgEmpty;
+ irq <= kDifFlashCtrlIrqCorrErr; ++irq) {
+ flash_ctrl_irq_expected = irq;
+ LOG_INFO("Triggering flash_ctrl IRQ %d.", irq);
+ CHECK_DIF_OK(dif_flash_ctrl_irq_force(&flash_ctrl, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(flash_ctrl_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from flash_ctrl is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralGpio;
+ for (dif_gpio_irq_t irq = kDifGpioIrqGpio0;
+ irq <= kDifGpioIrqGpio31; ++irq) {
+ gpio_irq_expected = irq;
+ LOG_INFO("Triggering gpio IRQ %d.", irq);
+ CHECK_DIF_OK(dif_gpio_irq_force(&gpio, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(gpio_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from gpio is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralHmac;
+ for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone;
+ irq <= kDifHmacIrqHmacErr; ++irq) {
+ hmac_irq_expected = irq;
+ LOG_INFO("Triggering hmac IRQ %d.", irq);
+ CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(hmac_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from hmac is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralI2c0;
+ for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold;
+ irq <= kDifI2cIrqHostTimeout; ++irq) {
+ i2c_irq_expected = irq;
+ LOG_INFO("Triggering i2c0 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from i2c0 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralI2c1;
+ for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold;
+ irq <= kDifI2cIrqHostTimeout; ++irq) {
+ i2c_irq_expected = irq;
+ LOG_INFO("Triggering i2c1 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c1, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from i2c1 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralI2c2;
+ for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold;
+ irq <= kDifI2cIrqHostTimeout; ++irq) {
+ i2c_irq_expected = irq;
+ LOG_INFO("Triggering i2c2 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_i2c_irq_force(&i2c2, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from i2c2 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralKeymgr;
+ for (dif_keymgr_irq_t irq = kDifKeymgrIrqOpDone;
+ irq <= kDifKeymgrIrqOpDone; ++irq) {
+ keymgr_irq_expected = irq;
+ LOG_INFO("Triggering keymgr IRQ %d.", irq);
+ CHECK_DIF_OK(dif_keymgr_irq_force(&keymgr, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(keymgr_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from keymgr is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralKmac;
+ for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone;
+ irq <= kDifKmacIrqKmacErr; ++irq) {
+ kmac_irq_expected = irq;
+ LOG_INFO("Triggering kmac IRQ %d.", irq);
+ CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(kmac_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from kmac is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralOtbn;
+ for (dif_otbn_irq_t irq = kDifOtbnIrqDone;
+ irq <= kDifOtbnIrqDone; ++irq) {
+ otbn_irq_expected = irq;
+ LOG_INFO("Triggering otbn IRQ %d.", irq);
+ CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(otbn_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from otbn is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralOtpCtrl;
+ for (dif_otp_ctrl_irq_t irq = kDifOtpCtrlIrqOtpOperationDone;
+ irq <= kDifOtpCtrlIrqOtpError; ++irq) {
+ otp_ctrl_irq_expected = irq;
+ LOG_INFO("Triggering otp_ctrl IRQ %d.", irq);
+ CHECK_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(otp_ctrl_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from otp_ctrl is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralPattgen;
+ for (dif_pattgen_irq_t irq = kDifPattgenIrqDoneCh0;
+ irq <= kDifPattgenIrqDoneCh1; ++irq) {
+ pattgen_irq_expected = irq;
+ LOG_INFO("Triggering pattgen IRQ %d.", irq);
+ CHECK_DIF_OK(dif_pattgen_irq_force(&pattgen, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(pattgen_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from pattgen is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralPwrmgrAon;
+ for (dif_pwrmgr_irq_t irq = kDifPwrmgrIrqWakeup;
+ irq <= kDifPwrmgrIrqWakeup; ++irq) {
+ pwrmgr_irq_expected = irq;
+ LOG_INFO("Triggering pwrmgr_aon IRQ %d.", irq);
+ CHECK_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_aon, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(pwrmgr_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from pwrmgr_aon is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralRvTimer;
+ for (dif_rv_timer_irq_t irq = kDifRvTimerIrqTimerExpiredHart0Timer0;
+ irq <= kDifRvTimerIrqTimerExpiredHart0Timer0; ++irq) {
+ rv_timer_irq_expected = irq;
+ LOG_INFO("Triggering rv_timer IRQ %d.", irq);
+ CHECK_DIF_OK(dif_rv_timer_irq_force(&rv_timer, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(rv_timer_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from rv_timer is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralSensorCtrl;
+ for (dif_sensor_ctrl_irq_t irq = kDifSensorCtrlIrqIoStatusChange;
+ irq <= kDifSensorCtrlIrqInitStatusChange; ++irq) {
+ sensor_ctrl_irq_expected = irq;
+ LOG_INFO("Triggering sensor_ctrl IRQ %d.", irq);
+ CHECK_DIF_OK(dif_sensor_ctrl_irq_force(&sensor_ctrl, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(sensor_ctrl_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from sensor_ctrl is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralSpiDevice;
+ for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqGenericRxFull;
+ irq <= kDifSpiDeviceIrqTpmHeaderNotEmpty; ++irq) {
+ spi_device_irq_expected = irq;
+ LOG_INFO("Triggering spi_device IRQ %d.", irq);
+ CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(spi_device_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from spi_device is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralSpiHost0;
+ for (dif_spi_host_irq_t irq = kDifSpiHostIrqError;
+ irq <= kDifSpiHostIrqSpiEvent; ++irq) {
+ spi_host_irq_expected = irq;
+ LOG_INFO("Triggering spi_host0 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(spi_host_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from spi_host0 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralSpiHost1;
+ for (dif_spi_host_irq_t irq = kDifSpiHostIrqError;
+ irq <= kDifSpiHostIrqSpiEvent; ++irq) {
+ spi_host_irq_expected = irq;
+ LOG_INFO("Triggering spi_host1 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host1, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(spi_host_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from spi_host1 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralSysrstCtrlAon;
+ for (dif_sysrst_ctrl_irq_t irq = kDifSysrstCtrlIrqEventDetected;
+ irq <= kDifSysrstCtrlIrqEventDetected; ++irq) {
+ sysrst_ctrl_irq_expected = irq;
+ LOG_INFO("Triggering sysrst_ctrl_aon IRQ %d.", irq);
+ CHECK_DIF_OK(dif_sysrst_ctrl_irq_force(&sysrst_ctrl_aon, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(sysrst_ctrl_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from sysrst_ctrl_aon is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralTlulMailboxSec;
+ for (dif_tlul_mailbox_irq_t irq = kDifTlulMailboxIrqWtirq;
+ irq <= kDifTlulMailboxIrqEirq; ++irq) {
+ tlul_mailbox_irq_expected = irq;
+ LOG_INFO("Triggering tlul_mailbox_sec IRQ %d.", irq);
+ CHECK_DIF_OK(dif_tlul_mailbox_irq_force(&tlul_mailbox_sec, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(tlul_mailbox_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from tlul_mailbox_sec is serviced.", irq);
+ }
+
+ // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference
+ // from the logging facility.
+ if (kDeviceType == kDeviceSimDV) {
+ peripheral_expected = kTopSenchaPlicPeripheralUart0;
+ for (dif_uart_irq_t irq = kDifUartIrqTxWatermark;
+ irq <= kDifUartIrqRxParityErr; ++irq) {
+ uart_irq_expected = irq;
+ LOG_INFO("Triggering uart0 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(uart_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from uart0 is serviced.", irq);
+ }
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralUart1;
+ for (dif_uart_irq_t irq = kDifUartIrqTxWatermark;
+ irq <= kDifUartIrqRxParityErr; ++irq) {
+ uart_irq_expected = irq;
+ LOG_INFO("Triggering uart1 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_uart_irq_force(&uart1, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(uart_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from uart1 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralUart2;
+ for (dif_uart_irq_t irq = kDifUartIrqTxWatermark;
+ irq <= kDifUartIrqRxParityErr; ++irq) {
+ uart_irq_expected = irq;
+ LOG_INFO("Triggering uart2 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_uart_irq_force(&uart2, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(uart_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from uart2 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralUart3;
+ for (dif_uart_irq_t irq = kDifUartIrqTxWatermark;
+ irq <= kDifUartIrqRxParityErr; ++irq) {
+ uart_irq_expected = irq;
+ LOG_INFO("Triggering uart3 IRQ %d.", irq);
+ CHECK_DIF_OK(dif_uart_irq_force(&uart3, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(uart_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from uart3 is serviced.", irq);
+ }
+
+ peripheral_expected = kTopSenchaPlicPeripheralUsbdev;
+ for (dif_usbdev_irq_t irq = kDifUsbdevIrqPktReceived;
+ irq <= kDifUsbdevIrqLinkOutErr; ++irq) {
+ usbdev_irq_expected = irq;
+ LOG_INFO("Triggering usbdev IRQ %d.", irq);
+ CHECK_DIF_OK(dif_usbdev_irq_force(&usbdev, irq, true));
+
+ // This avoids a race where *irq_serviced is read before
+ // entering the ISR.
+ IBEX_SPIN_FOR(usbdev_irq_serviced == irq, 1);
+ LOG_INFO("IRQ %d from usbdev is serviced.", irq);
+ }
+}
+
+/**
+ * Checks that the target ID corresponds to the ID of the hart on which
+ * this test is executed on. This check is meant to be used in a
+ * single-hart system only.
+ */
+static void check_hart_id(uint32_t exp_hart_id) {
+ uint32_t act_hart_id;
+ CSR_READ(CSR_REG_MHARTID, &act_hart_id);
+ CHECK(act_hart_id == exp_hart_id, "Processor has unexpected HART ID.");
+}
+
+OTTF_DEFINE_TEST_CONFIG();
+
+bool test_main(void) {
+ irq_global_ctrl(true);
+ irq_external_ctrl(true);
+ peripherals_init();
+ check_hart_id((uint32_t)kHart);
+ rv_plic_testutils_irq_range_enable(
+ &plic, kHart, kTopSenchaPlicIrqIdNone + 1, kTopSenchaPlicIrqIdLast);
+ peripheral_irqs_clear();
+ peripheral_irqs_enable();
+ peripheral_irqs_trigger();
+ return true;
+}
+
+// clang-format on
