Force URAM Usage for ML and SMC Memories
BRAM utilization was approximately 90% prior to change. This appeared to
be the cause of build failures.
This change effectively change targets large u_ram1p_ram_smc and
u_ml_dmem RAMs and requests the vivado tool to set these to URAM with
new synth only constraint (synth.xdc).
Louhi build available temporarily here
https://louhi.dev/5958780716318720/execution-detail/4590981286068224
Build is successful and imp utilization report available in the logs at
the above Louhi link shows the following utilization changes:
URAM utilization increase to ~31% (from ~1%)
BRAM utilization reduced to ~13% (from ~90%)
Change-Id: Ib9ef26b54815043882adcd644c936a3739e74f62
diff --git a/hw/top_matcha/chip_matcha_nexus.core b/hw/top_matcha/chip_matcha_nexus.core
index 5219495..49153c9 100644
--- a/hw/top_matcha/chip_matcha_nexus.core
+++ b/hw/top_matcha/chip_matcha_nexus.core
@@ -22,6 +22,7 @@
- data/clocks_nexus.xdc
- data/pins_nexus.xdc
- data/placement.xdc
+ - data/synth.xdc
file_type: xdc
files_tcl:
diff --git a/hw/top_matcha/data/synth.xdc b/hw/top_matcha/data/synth.xdc
new file mode 100644
index 0000000..cbedf1d
--- /dev/null
+++ b/hw/top_matcha/data/synth.xdc
@@ -0,0 +1,23 @@
+# Copyright 2023 Google LLC
+# Copyright lowRISC contributors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# File is configured in vivado_setup_hooks.tcl to only be used for synth
+
+# Force SMC to use ULTRARAM instead of BRAM for memory
+set_property ram_style ultra [get_cells -hierarchical -filter {NAME =~ "*u_ram1p_ram_smc/u_mem/gen_generic.u_impl_generic/mem_reg*"} ]
+
+# Force ML CORE to use ULTRARAM instead of BRAM for memory
+set_property ram_style ultra [get_cells -hierarchical -filter {NAME =~ "*u_ml_dmem/u_ram1p_dmem/u_mem/gen_generic.u_impl_generic/mem_reg*"} ]
diff --git a/hw/top_matcha/util/vivado_setup_hooks.tcl b/hw/top_matcha/util/vivado_setup_hooks.tcl
index 8003037..3b76967 100644
--- a/hw/top_matcha/util/vivado_setup_hooks.tcl
+++ b/hw/top_matcha/util/vivado_setup_hooks.tcl
@@ -40,3 +40,6 @@
# As workaround, we use the post route design hook, which gets called.
set_property STEPS.ROUTE_DESIGN.TCL.POST "${workroot}/vivado_hook_write_bitstream_pre.tcl" [get_runs impl_1]
+
+# Set synth.xdc to only be used for synthesis (initial implementation is to force URAM instead of BRAM)
+set_property used_in_implementation false [filter -regexp [get_files -of [get_filesets constrs_1]] {NAME=~".*\/synth.xdc"}]
