)]}'
{
  "commit": "6574fa669b40a2d32033763a18224d0b65067edc",
  "tree": "73f9824639f0c9d3300430b3be6150f5ad765e12",
  "parents": [
    "ca943b5628a55cbd5a1850deca7aa8f92263ecd0"
  ],
  "author": {
    "name": "Sam Leffler",
    "email": "sleffler@google.com",
    "time": "Tue Jun 11 09:28:26 2024 -0700"
  },
  "committer": {
    "name": "Sam Leffler",
    "email": "sleffler@google.com",
    "time": "Tue Aug 27 16:34:16 2024 -0700"
  },
  "message": "test_rom: initial bancha support\n\nChanges in support of booting CHERIoT firmware images on a bancha system,\nThis has been tested only with OTP_IS_RAM and requires the 2nd-level\nfirmware image be loaded from SPI into RAM.\n\nNB: 2nd-level firmware images currently lack the expected manifest\n\nSpecific changes:\n- many files forked to isolate / simplify adding CHERI support\n- memory layout is somewhat different per CHERIoT requirements (e.g.\n  r/w data is collected in one ELF section for CGP-relative addressing)\n- remove PMP usage because CHERIoT does not support it and it\u0027s use\n  can be done with CHERI caps\n- static_critical section size differs from non-CHERI\n- eflash, flash_ctrl, spi_flash, and bootstrap api\u0027s take capabilities\n  for the MMIO regions (using mmio_region_t) instead of crafting pointers\n  from raw addresses\n- tag the build target with \"cheri\" so we can filter it out for CI\n\nBypass-Presubmit-Reason: verified as part of topic\n\nChange-Id: Iecbb7f9eaedc52a8988e7da9015d89e058f9d844\n",
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