Merge "500kHz JTAG - 5MHz SPI Slave"
diff --git a/hw/top_matcha/data/clocks_nexus.xdc b/hw/top_matcha/data/clocks_nexus.xdc
index 4d9961e..2d644b5 100644
--- a/hw/top_matcha/data/clocks_nexus.xdc
+++ b/hw/top_matcha/data/clocks_nexus.xdc
@@ -59,14 +59,16 @@
] \
]
-## JTAG clocks TODO - clock frequency
-create_clock -add -name lc_jtag_tck -period 200.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
-create_clock -add -name rv_jtag_tck -period 200.00 -waveform {0 5} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+## JTAG clocks -- JTAG clock max frequency is set to 500KHz
+create_clock -add -name lc_jtag_tck -period 2000.00 -waveform {0 1000} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_lc/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+create_clock -add -name rv_jtag_tck -period 2000.00 -waveform {0 1000} [get_pin top_*/u_pinmux_aon/u_pinmux_strap_sampling/u_pinmux_jtag_buf_rv/prim_clock_buf_tck/gen_xilinx.u_impl_xilinx/gen_fpga_buf.gen_bufg.bufg_i/O]
+set clk_spi_period 200
+set clk_spi_half_period [expr ${clk_spi_period} / 2]
## SPI clocks
set spi_dev_data [get_ports {SPI_DEV_D0 SPI_DEV_D1 SPI_DEV_D2 SPI_DEV_D3}]
-create_clock -add -name clk_spi -period $clk_main_period -waveform {0 50} [get_ports SPI_DEV_CLK]
-create_clock -add -name clk_cs -period [expr $clk_main_period * 10] -waveform {0 50} [get_ports SPI_DEV_CS_L]
+create_clock -add -name clk_spi -period ${clk_spi_period} -waveform "0 ${clk_spi_half_period}" [get_ports SPI_DEV_CLK]
+create_clock -add -name clk_cs -period [expr $clk_spi_period * 10]
set_input_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
set_output_delay -clock clk_spi 5 ${spi_dev_data} -add_delay
# set_input_delay -clock clk_spi -clock_fall -min ${spi_dev_in_delay_min} ${spi_dev_data} -add_delay
