Get xbar_sram from @kelvin_hw
- The source-of-truth for xbar_sram is the Crossbar module in
@kelvin_hw. Pull the verilog from the external repository, and update
the name we reference by from xbar_sram->Crossbar.
Change-Id: I1ef6794487ac9720f92ce3533d285bb0ffc03c56
diff --git a/doc/getting_started/setup_dv.md b/doc/getting_started/setup_dv.md
index f58f008..aa5a209 100644
--- a/doc/getting_started/setup_dv.md
+++ b/doc/getting_started/setup_dv.md
@@ -88,14 +88,3 @@
$assertoff(0, tb.dut);
end
```
-
-2. Add the following lines:
- ```
- `define STOP_COND 0
- `define PRINTF_COND 0
- ```
- at the top of the files:
- ```
- hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
- ```
- to turn off the $fatal statements and the unwanted debug messages
diff --git a/hw/top_matcha/ip/ml_top/ml_top.core b/hw/top_matcha/ip/ml_top/ml_top.core
index 127344a..21c614e 100644
--- a/hw/top_matcha/ip/ml_top/ml_top.core
+++ b/hw/top_matcha/ip/ml_top/ml_top.core
@@ -11,6 +11,7 @@
- lowrisc:ip:tlul
- lowrisc:prim:mubi
- google:ip:kelvin
+ - google:ip:crossbar
files:
- rtl/ml_pkg.sv
@@ -18,7 +19,6 @@
- rtl/ml_top_core_reg_top.sv
- rtl/ml_dmem.sv
- rtl/ml_top.sv
- - rtl/xbar_sram.v
file_type: systemVerilogSource
files_verilator_waiver:
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
index 211bdb9..2a294ec 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_dmem.sv
@@ -16,7 +16,7 @@
// This module implements the D-Mem inside the Vector Core Top Level
//
-// This memory can be accessed either by TLUL or ML cores through xbar_sram
+// This memory can be accessed either by TLUL or ML cores through Crossbar
module ml_dmem
import ml_pkg::*;
@@ -97,7 +97,7 @@
assign ram_cfg.ram_cfg = { 3'b0, volt_sel_i, 1'b0 };
assign ram_cfg.rf_cfg = 5'b0;
- // xbar_sram only support Byte-Mask for now. i.e 8 data bits per mask bit.
+ // Crossbar only support Byte-Mask for now. i.e 8 data bits per mask bit.
assign xbar_wmask_b = {xbar_wmask[248], xbar_wmask[240], xbar_wmask[232], xbar_wmask[224],
xbar_wmask[216], xbar_wmask[208], xbar_wmask[200], xbar_wmask[192],
xbar_wmask[184], xbar_wmask[176], xbar_wmask[168], xbar_wmask[160],
@@ -168,7 +168,7 @@
// crossbar
- xbar_sram u_xbar_sram(
+ Crossbar u_crossbar(
.clock (clk_i),
.reset (~rst_ni),
// In Port 0 -- TLUL-SRAM Adatper
diff --git a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
index 4d98fec..b70bc3f 100644
--- a/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
+++ b/hw/top_matcha/ip/ml_top/rtl/ml_top.sv
@@ -158,7 +158,7 @@
);
- // Memory Block (inlcude xbar_sram and SRAM banks)
+ // Memory Block (inlcude Crossbar and SRAM banks)
ml_dmem u_ml_dmem (
.rst_ni ( rst_ni ),
.clk_i ( clk_i ),
diff --git a/hw/top_matcha/ip/ml_top/rtl/xbar_sram.v b/hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
deleted file mode 100644
index a39b220..0000000
--- a/hw/top_matcha/ip/ml_top/rtl/xbar_sram.v
+++ /dev/null
@@ -1,405 +0,0 @@
-// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-//----------------------------------------------
-// Description: SRAM Crossbar
-// Files: xbar_sram.v
-// --4 way
-// --Address Width =22
-// --Data Width =256
-// --ID Width = 8
-// --Maintain selection if no activitiy
-
-`define STOP_COND 0
-`define PRINTF_COND 0
-
-// SHA: b07e5a3168f36e80ae0186116e2bc9abef6595c3
-module xbar_sram(
- input clock,
- input reset,
- input io_in_0_cvalid,
- output io_in_0_cready,
- input io_in_0_cwrite,
- input [21:0] io_in_0_caddr,
- input [7:0] io_in_0_cid,
- input [255:0] io_in_0_wdata,
- input [31:0] io_in_0_wmask,
- output io_in_0_rvalid,
- output [7:0] io_in_0_rid,
- output [255:0] io_in_0_rdata,
- input io_in_1_cvalid,
- output io_in_1_cready,
- input io_in_1_cwrite,
- input [21:0] io_in_1_caddr,
- input [7:0] io_in_1_cid,
- input [255:0] io_in_1_wdata,
- input [31:0] io_in_1_wmask,
- output io_in_1_rvalid,
- output [7:0] io_in_1_rid,
- output [255:0] io_in_1_rdata,
- input io_in_2_cvalid,
- output io_in_2_cready,
- input io_in_2_cwrite,
- input [21:0] io_in_2_caddr,
- input [7:0] io_in_2_cid,
- input [255:0] io_in_2_wdata,
- input [31:0] io_in_2_wmask,
- output io_in_2_rvalid,
- output [7:0] io_in_2_rid,
- output [255:0] io_in_2_rdata,
- input io_in_3_cvalid,
- output io_in_3_cready,
- input io_in_3_cwrite,
- input [21:0] io_in_3_caddr,
- input [7:0] io_in_3_cid,
- input [255:0] io_in_3_wdata,
- input [31:0] io_in_3_wmask,
- output io_in_3_rvalid,
- output [7:0] io_in_3_rid,
- output [255:0] io_in_3_rdata,
- output io_out_valid,
- output io_out_write,
- output [21:0] io_out_addr,
- output [255:0] io_out_wdata,
- output [31:0] io_out_wmask,
- input [255:0] io_out_rdata
-);
-`ifdef RANDOMIZE_REG_INIT
- reg [31:0] _RAND_0;
- reg [31:0] _RAND_1;
- reg [31:0] _RAND_2;
- reg [31:0] _RAND_3;
- reg [31:0] _RAND_4;
- reg [255:0] _RAND_5;
- reg [31:0] _RAND_6;
- reg [31:0] _RAND_7;
- reg [31:0] _RAND_8;
- reg [31:0] _RAND_9;
- reg [31:0] _RAND_10;
- reg [31:0] _RAND_11;
- reg [31:0] _RAND_12;
- reg [31:0] _RAND_13;
- reg [255:0] _RAND_14;
-`endif // RANDOMIZE_REG_INIT
- reg [3:0] csel0; // @[Crossbar.scala 61:24]
- wire [1:0] _T_5 = csel0[0] + csel0[1]; // @[Bitwise.scala 48:55]
- wire [1:0] _T_7 = csel0[2] + csel0[3]; // @[Bitwise.scala 48:55]
- wire [2:0] _T_9 = _T_5 + _T_7; // @[Bitwise.scala 48:55]
- wire _T_13 = ~reset; // @[Crossbar.scala 62:11]
- wire [3:0] _T_15 = {io_in_3_cvalid,io_in_2_cvalid,io_in_1_cvalid,io_in_0_cvalid}; // @[Crossbar.scala 88:18]
- wire _csel0_T = io_in_0_cvalid | io_in_1_cvalid; // @[Crossbar.scala 74:18]
- wire _csel0_T_2 = io_in_1_cvalid & ~io_in_0_cvalid; // @[Crossbar.scala 75:31]
- wire _csel0_T_5 = io_in_0_cvalid | io_in_1_cvalid | io_in_2_cvalid; // @[Crossbar.scala 74:18]
- wire _csel0_T_7 = io_in_2_cvalid & ~_csel0_T; // @[Crossbar.scala 75:31]
- wire _csel0_T_12 = io_in_3_cvalid & ~_csel0_T_5; // @[Crossbar.scala 75:31]
- wire [3:0] _csel0_T_14 = {_csel0_T_12,_csel0_T_7,_csel0_T_2,io_in_0_cvalid}; // @[Cat.scala 31:58]
- wire cen0 = io_in_0_cvalid & csel0[0] | io_in_1_cvalid & csel0[1] | io_in_2_cvalid & csel0[2] | io_in_3_cvalid &
- csel0[3]; // @[Crossbar.scala 102:18]
- reg cvalid1; // @[Crossbar.scala 113:26]
- reg cwrite1; // @[Crossbar.scala 114:26]
- reg [16:0] cindex1; // @[Crossbar.scala 115:22]
- reg [9:0] cid1; // @[Crossbar.scala 116:22]
- reg [255:0] wdata1; // @[Crossbar.scala 117:22]
- reg [31:0] wmask1; // @[Crossbar.scala 118:22]
- wire [16:0] _T_22 = csel0[0] ? io_in_0_caddr[21:5] : 17'h0; // @[Crossbar.scala 128:24]
- wire [8:0] _T_25 = {1'h0,io_in_0_cid}; // @[Cat.scala 31:58]
- wire [8:0] _T_26 = csel0[0] ? _T_25 : 9'h0; // @[Crossbar.scala 129:24]
- wire [9:0] _T_27 = {{1'd0}, _T_26}; // @[Crossbar.scala 129:19]
- wire [255:0] _T_29 = csel0[0] ? io_in_0_wdata : 256'h0; // @[Crossbar.scala 130:24]
- wire [31:0] _T_32 = csel0[0] ? io_in_0_wmask : 32'h0; // @[Crossbar.scala 131:24]
- wire [16:0] _T_39 = csel0[1] ? io_in_1_caddr[21:5] : 17'h0; // @[Crossbar.scala 128:24]
- wire [16:0] _T_40 = _T_22 | _T_39; // @[Crossbar.scala 128:19]
- wire [8:0] _T_42 = {1'h1,io_in_1_cid}; // @[Cat.scala 31:58]
- wire [8:0] _T_43 = csel0[1] ? _T_42 : 9'h0; // @[Crossbar.scala 129:24]
- wire [9:0] _GEN_10 = {{1'd0}, _T_43}; // @[Crossbar.scala 129:19]
- wire [9:0] _T_44 = _T_27 | _GEN_10; // @[Crossbar.scala 129:19]
- wire [255:0] _T_46 = csel0[1] ? io_in_1_wdata : 256'h0; // @[Crossbar.scala 130:24]
- wire [255:0] _T_47 = _T_29 | _T_46; // @[Crossbar.scala 130:19]
- wire [31:0] _T_49 = csel0[1] ? io_in_1_wmask : 32'h0; // @[Crossbar.scala 131:24]
- wire [31:0] _T_50 = _T_32 | _T_49; // @[Crossbar.scala 131:19]
- wire [16:0] _T_56 = csel0[2] ? io_in_2_caddr[21:5] : 17'h0; // @[Crossbar.scala 128:24]
- wire [16:0] _T_57 = _T_40 | _T_56; // @[Crossbar.scala 128:19]
- wire [9:0] _T_59 = {2'h2,io_in_2_cid}; // @[Cat.scala 31:58]
- wire [9:0] _T_60 = csel0[2] ? _T_59 : 10'h0; // @[Crossbar.scala 129:24]
- wire [9:0] _T_61 = _T_44 | _T_60; // @[Crossbar.scala 129:19]
- wire [255:0] _T_63 = csel0[2] ? io_in_2_wdata : 256'h0; // @[Crossbar.scala 130:24]
- wire [255:0] _T_64 = _T_47 | _T_63; // @[Crossbar.scala 130:19]
- wire [31:0] _T_66 = csel0[2] ? io_in_2_wmask : 32'h0; // @[Crossbar.scala 131:24]
- wire [31:0] _T_67 = _T_50 | _T_66; // @[Crossbar.scala 131:19]
- wire cwriteNxt = csel0[0] & io_in_0_cwrite | csel0[1] & io_in_1_cwrite | csel0[2] & io_in_2_cwrite | csel0[3] &
- io_in_3_cwrite; // @[Crossbar.scala 127:18]
- wire [16:0] _T_72 = csel0[3] ? io_in_3_caddr[21:5] : 17'h0; // @[Crossbar.scala 128:24]
- wire [16:0] cindexNxt = _T_57 | _T_72; // @[Crossbar.scala 128:19]
- wire [9:0] _T_74 = {2'h3,io_in_3_cid}; // @[Cat.scala 31:58]
- wire [9:0] _T_75 = csel0[3] ? _T_74 : 10'h0; // @[Crossbar.scala 129:24]
- wire [9:0] cidNxt = _T_61 | _T_75; // @[Crossbar.scala 129:19]
- wire [255:0] _T_77 = csel0[3] ? io_in_3_wdata : 256'h0; // @[Crossbar.scala 130:24]
- wire [255:0] wdataNxt = _T_64 | _T_77; // @[Crossbar.scala 130:19]
- wire [31:0] _T_79 = csel0[3] ? io_in_3_wmask : 32'h0; // @[Crossbar.scala 131:24]
- wire [31:0] wmaskNxt = _T_67 | _T_79; // @[Crossbar.scala 131:19]
- reg rvalid2; // @[Crossbar.scala 161:26]
- reg [9:0] rid2; // @[Crossbar.scala 162:22]
- reg rvalid3_0; // @[Crossbar.scala 169:26]
- reg rvalid3_1; // @[Crossbar.scala 169:26]
- reg rvalid3_2; // @[Crossbar.scala 169:26]
- reg rvalid3_3; // @[Crossbar.scala 169:26]
- reg [7:0] rid3; // @[Crossbar.scala 170:22]
- reg [255:0] rdata3; // @[Crossbar.scala 171:22]
- assign io_in_0_cready = csel0[0]; // @[Crossbar.scala 93:31]
- assign io_in_0_rvalid = rvalid3_0; // @[Crossbar.scala 187:23]
- assign io_in_0_rid = rvalid3_0 ? rid3 : 8'h0; // @[Crossbar.scala 189:29]
- assign io_in_0_rdata = rvalid3_0 ? rdata3 : 256'h0; // @[Crossbar.scala 188:29]
- assign io_in_1_cready = csel0[1]; // @[Crossbar.scala 93:31]
- assign io_in_1_rvalid = rvalid3_1; // @[Crossbar.scala 187:23]
- assign io_in_1_rid = rvalid3_1 ? rid3 : 8'h0; // @[Crossbar.scala 189:29]
- assign io_in_1_rdata = rvalid3_1 ? rdata3 : 256'h0; // @[Crossbar.scala 188:29]
- assign io_in_2_cready = csel0[2]; // @[Crossbar.scala 93:31]
- assign io_in_2_rvalid = rvalid3_2; // @[Crossbar.scala 187:23]
- assign io_in_2_rid = rvalid3_2 ? rid3 : 8'h0; // @[Crossbar.scala 189:29]
- assign io_in_2_rdata = rvalid3_2 ? rdata3 : 256'h0; // @[Crossbar.scala 188:29]
- assign io_in_3_cready = csel0[3]; // @[Crossbar.scala 93:31]
- assign io_in_3_rvalid = rvalid3_3; // @[Crossbar.scala 187:23]
- assign io_in_3_rid = rvalid3_3 ? rid3 : 8'h0; // @[Crossbar.scala 189:29]
- assign io_in_3_rdata = rvalid3_3 ? rdata3 : 256'h0; // @[Crossbar.scala 188:29]
- assign io_out_valid = cvalid1; // @[Crossbar.scala 151:18]
- assign io_out_write = cwrite1; // @[Crossbar.scala 152:18]
- assign io_out_addr = {cindex1,5'h0}; // @[Cat.scala 31:58]
- assign io_out_wdata = wdata1; // @[Crossbar.scala 154:18]
- assign io_out_wmask = wmask1; // @[Crossbar.scala 155:18]
- always @(posedge clock) begin
- if (cen0) begin // @[Crossbar.scala 140:17]
- cindex1 <= cindexNxt; // @[Crossbar.scala 143:15]
- end
- if (cen0) begin // @[Crossbar.scala 140:17]
- cid1 <= cidNxt; // @[Crossbar.scala 144:15]
- end
- if (cen0) begin // @[Crossbar.scala 140:17]
- if (cwriteNxt) begin // @[Crossbar.scala 145:24]
- wdata1 <= wdataNxt; // @[Crossbar.scala 146:17]
- end
- end
- if (cen0) begin // @[Crossbar.scala 140:17]
- if (cwriteNxt) begin // @[Crossbar.scala 145:24]
- wmask1 <= wmaskNxt; // @[Crossbar.scala 147:17]
- end
- end
- rid2 <= cid1; // @[Crossbar.scala 165:13]
- if (rvalid2) begin // @[Crossbar.scala 181:20]
- rid3 <= rid2[7:0]; // @[Crossbar.scala 183:14]
- end
- if (rvalid2) begin // @[Crossbar.scala 181:20]
- rdata3 <= io_out_rdata; // @[Crossbar.scala 182:14]
- end
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (~reset & ~(_T_9 == 3'h1)) begin
- $fatal; // @[Crossbar.scala 62:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (~reset & ~(_T_9 == 3'h1)) begin
- $fwrite(32'h80000002,"Assertion failed\n at Crossbar.scala:62 assert(PopCount(csel0) === 1.U)\n"); // @[Crossbar.scala 62:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef STOP_COND
- if (`STOP_COND) begin
- `endif
- if (_T_13 & ~(~(io_out_valid & io_out_addr[4:0] != 5'h0))) begin
- $fatal; // @[Crossbar.scala 157:11]
- end
- `ifdef STOP_COND
- end
- `endif
- `endif // SYNTHESIS
- `ifndef SYNTHESIS
- `ifdef PRINTF_COND
- if (`PRINTF_COND) begin
- `endif
- if (_T_13 & ~(~(io_out_valid & io_out_addr[4:0] != 5'h0))) begin
- $fwrite(32'h80000002,
- "Assertion failed\n at Crossbar.scala:157 assert(!(io.out.valid && io.out.addr(alsb - 1, 0) =/= 0.U))\n"
- ); // @[Crossbar.scala 157:11]
- end
- `ifdef PRINTF_COND
- end
- `endif
- `endif // SYNTHESIS
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 88:34]
- csel0 <= 4'h1; // @[Crossbar.scala 89:13]
- end else if (_T_15 != 4'h0) begin // @[Crossbar.scala 61:24]
- csel0 <= _csel0_T_14;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 102:18]
- cvalid1 <= 1'h0;
- end else begin
- cvalid1 <= io_in_0_cvalid & csel0[0] | io_in_1_cvalid & csel0[1] | io_in_2_cvalid & csel0[2] | io_in_3_cvalid &
- csel0[3];
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 140:17]
- cwrite1 <= 1'h0; // @[Crossbar.scala 142:15]
- end else if (cen0) begin // @[Crossbar.scala 114:26]
- cwrite1 <= cwriteNxt;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 164:24]
- rvalid2 <= 1'h0;
- end else begin
- rvalid2 <= cvalid1 & ~cwrite1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 175:31]
- rvalid3_0 <= 1'h0;
- end else begin
- rvalid3_0 <= rvalid2 & rid2[9:8] == 2'h0;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 175:31]
- rvalid3_1 <= 1'h0;
- end else begin
- rvalid3_1 <= rvalid2 & rid2[9:8] == 2'h1;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 175:31]
- rvalid3_2 <= 1'h0;
- end else begin
- rvalid3_2 <= rvalid2 & rid2[9:8] == 2'h2;
- end
- end
- always @(posedge clock or posedge reset) begin
- if (reset) begin // @[Crossbar.scala 175:31]
- rvalid3_3 <= 1'h0;
- end else begin
- rvalid3_3 <= rvalid2 & rid2[9:8] == 2'h3;
- end
- end
-// Register and memory initialization
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
- integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
- `ifdef RANDOMIZE
- `ifdef INIT_RANDOM
- `INIT_RANDOM
- `endif
- `ifndef VERILATOR
- `ifdef RANDOMIZE_DELAY
- #`RANDOMIZE_DELAY begin end
- `else
- #0.002 begin end
- `endif
- `endif
-`ifdef RANDOMIZE_REG_INIT
- _RAND_0 = {1{`RANDOM}};
- csel0 = _RAND_0[3:0];
- _RAND_1 = {1{`RANDOM}};
- cvalid1 = _RAND_1[0:0];
- _RAND_2 = {1{`RANDOM}};
- cwrite1 = _RAND_2[0:0];
- _RAND_3 = {1{`RANDOM}};
- cindex1 = _RAND_3[16:0];
- _RAND_4 = {1{`RANDOM}};
- cid1 = _RAND_4[9:0];
- _RAND_5 = {8{`RANDOM}};
- wdata1 = _RAND_5[255:0];
- _RAND_6 = {1{`RANDOM}};
- wmask1 = _RAND_6[31:0];
- _RAND_7 = {1{`RANDOM}};
- rvalid2 = _RAND_7[0:0];
- _RAND_8 = {1{`RANDOM}};
- rid2 = _RAND_8[9:0];
- _RAND_9 = {1{`RANDOM}};
- rvalid3_0 = _RAND_9[0:0];
- _RAND_10 = {1{`RANDOM}};
- rvalid3_1 = _RAND_10[0:0];
- _RAND_11 = {1{`RANDOM}};
- rvalid3_2 = _RAND_11[0:0];
- _RAND_12 = {1{`RANDOM}};
- rvalid3_3 = _RAND_12[0:0];
- _RAND_13 = {1{`RANDOM}};
- rid3 = _RAND_13[7:0];
- _RAND_14 = {8{`RANDOM}};
- rdata3 = _RAND_14[255:0];
-`endif // RANDOMIZE_REG_INIT
- if (reset) begin
- csel0 = 4'h1;
- end
- if (reset) begin
- cvalid1 = 1'h0;
- end
- if (reset) begin
- cwrite1 = 1'h0;
- end
- if (reset) begin
- rvalid2 = 1'h0;
- end
- if (reset) begin
- rvalid3_0 = 1'h0;
- end
- if (reset) begin
- rvalid3_1 = 1'h0;
- end
- if (reset) begin
- rvalid3_2 = 1'h0;
- end
- if (reset) begin
- rvalid3_3 = 1'h0;
- end
- `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-endmodule
