Remove top_matcha references in hw/ip DV configs
Change-Id: Ie8e922708c825db6d566c02e828989053b51b584
diff --git a/hw/ip/cam_ctrl/dv/cam_ctrl_sim.core b/hw/ip/cam_ctrl/dv/cam_ctrl_sim.core
index 18dbf89..c4bbf1b 100644
--- a/hw/ip/cam_ctrl/dv/cam_ctrl_sim.core
+++ b/hw/ip/cam_ctrl/dv/cam_ctrl_sim.core
@@ -25,6 +25,6 @@
- files_dv
default_tool: vcs
- # TODO: add a lint check cfg in `hw/top_matcha/lint/top_matcha_dv_lint_cfgs.hjson`
+ # TODO: add a lint check cfg in `hw/lint/top_matcha_dv_lint_cfgs.hjson`
lint:
<<: *sim_target
diff --git a/hw/ip/cam_ctrl/dv/cam_ctrl_sim_cfg.hjson b/hw/ip/cam_ctrl/dv/cam_ctrl_sim_cfg.hjson
index 7b96efb..1437f3c 100644
--- a/hw/ip/cam_ctrl/dv/cam_ctrl_sim_cfg.hjson
+++ b/hw/ip/cam_ctrl/dv/cam_ctrl_sim_cfg.hjson
@@ -18,10 +18,10 @@
fusesoc_core: google:dv:cam_ctrl_sim:0.1
// Testplan hjson file.
- testplan: "{proj_root}/hw/top_matcha/ip/cam_ctrl/data/cam_ctrl_testplan.hjson"
+ testplan: "{proj_root}/hw/ip/cam_ctrl/data/cam_ctrl_testplan.hjson"
// RAL spec - used to generate the RAL model.
- ral_spec: "{proj_root}/hw/top_matcha/ip/cam_ctrl/data/cam_ctrl.hjson"
+ ral_spec: "{proj_root}/hw/ip/cam_ctrl/data/cam_ctrl.hjson"
// Import additional common sim cfg files.
// TODO: remove imported cfgs that do not apply.
diff --git a/hw/ip/dma/dv/README.md b/hw/ip/dma/dv/README.md
index c14d6a0..5657d7c 100644
--- a/hw/ip/dma/dv/README.md
+++ b/hw/ip/dma/dv/README.md
@@ -14,9 +14,9 @@
```
cd $ROOTDIR/hw/matcha
-./util/dvsim_matcha/dvsim.py ./hw/top_matcha/ip/dma/dv/dma_sim_cfg.hjson -i dma_smoke
+./util/dvsim_matcha/dvsim.py ./hw/ip/dma/dv/dma_sim_cfg.hjson -i dma_smoke
```
3. Run in debug mode with `-v d` option
-4. Dump out waveform with `-w fsdb` option
\ No newline at end of file
+4. Dump out waveform with `-w fsdb` option
diff --git a/hw/ip/dma/dv/dma_sim_cfg.hjson b/hw/ip/dma/dv/dma_sim_cfg.hjson
index 0596648..154c4b6 100644
--- a/hw/ip/dma/dv/dma_sim_cfg.hjson
+++ b/hw/ip/dma/dv/dma_sim_cfg.hjson
@@ -19,7 +19,7 @@
fusesoc_core: lowrisc:dv:dma_sim:0.1
// Testplan hjson file.
- testplan: "{proj_root}/hw/top_matcha/ip/dma/data/dma_testplan.hjson"
+ testplan: "{proj_root}/hw/ip/dma/data/dma_testplan.hjson"
// RAL spec - used to generate the RAL model.
ral_spec: "{proj_root}/hw/ip/dma/data/dma.hjson"
diff --git a/hw/ip/ml_top/dv/ml_top_sim.core b/hw/ip/ml_top/dv/ml_top_sim.core
index 62dd478..ae272f9 100644
--- a/hw/ip/ml_top/dv/ml_top_sim.core
+++ b/hw/ip/ml_top/dv/ml_top_sim.core
@@ -24,6 +24,6 @@
- files_dv
default_tool: vcs
- # TODO: add a lint check cfg in `hw/top_matcha/lint/top_matcha_dv_lint_cfgs.hjson`
+ # TODO: add a lint check cfg in `hw/lint/top_matcha_dv_lint_cfgs.hjson`
lint:
<<: *sim_target
diff --git a/hw/ip/rv_core_smc/doc/dv/_index.md b/hw/ip/rv_core_smc/doc/dv/_index.md
index c46218c..dd5d26f 100644
--- a/hw/ip/rv_core_smc/doc/dv/_index.md
+++ b/hw/ip/rv_core_smc/doc/dv/_index.md
@@ -28,7 +28,7 @@
The main Ibex testbench is not contained in the OpenTitan repository.
Verification is primarily done by the testbench in the Ibex reposity, see the [Ibex Testplan](https://ibex-core.readthedocs.io/en/latest/03_reference/testplan.html) for more details.
-The additional features provided by the RISC-V Core Wrapper are verified at a chip level only (See the [Earlgrey Chip DV testplan]({{< relref "hw/top_matcha/doc/dv" >}}).
+The additional features provided by the RISC-V Core Wrapper are verified at a chip level only (See the [Earlgrey Chip DV testplan]({{< relref "hw/doc/dv" >}}).
As they are simple features chip level only verification suffices to meet our goals.
Similarly there is no specific verification for the TL-UL <-> Ibex memory protocol wrappers (provided by the separate [TLUL IP]({{< relref "hw/ip/tlul/doc" >}})).
diff --git a/hw/ip/smc_ctrl/dv/smc_ctrl_sim.core b/hw/ip/smc_ctrl/dv/smc_ctrl_sim.core
index 1258ed2..845e7cf 100644
--- a/hw/ip/smc_ctrl/dv/smc_ctrl_sim.core
+++ b/hw/ip/smc_ctrl/dv/smc_ctrl_sim.core
@@ -25,6 +25,6 @@
- files_dv
default_tool: vcs
- # TODO: add a lint check cfg in `hw/top_matcha/lint/top_matcha_dv_lint_cfgs.hjson`
+ # TODO: add a lint check cfg in `hw/lint/top_matcha_dv_lint_cfgs.hjson`
lint:
<<: *sim_target
diff --git a/hw/ip/smc_ctrl/dv/smc_ctrl_sim_cfg.hjson b/hw/ip/smc_ctrl/dv/smc_ctrl_sim_cfg.hjson
index a13c5ac..09a62a8 100644
--- a/hw/ip/smc_ctrl/dv/smc_ctrl_sim_cfg.hjson
+++ b/hw/ip/smc_ctrl/dv/smc_ctrl_sim_cfg.hjson
@@ -18,10 +18,10 @@
fusesoc_core: google:dv:smc_ctrl_sim:0.1
// Testplan hjson file.
- testplan: "{proj_root}/hw/top_matcha/ip/smc_ctrl/data/smc_ctrl_testplan.hjson"
+ testplan: "{proj_root}/hw/ip/smc_ctrl/data/smc_ctrl_testplan.hjson"
// RAL spec - used to generate the RAL model.
- ral_spec: "{proj_root}/hw/top_matcha/ip/smc_ctrl/data/smc_ctrl.hjson"
+ ral_spec: "{proj_root}/hw/ip/smc_ctrl/data/smc_ctrl.hjson"
// Import additional common sim cfg files.
// TODO: remove imported cfgs that do not apply.
diff --git a/hw/ip/tlul_mailbox/doc/dv/index.md b/hw/ip/tlul_mailbox/doc/dv/index.md
index 80e64d8..7abf0ac 100644
--- a/hw/ip/tlul_mailbox/doc/dv/index.md
+++ b/hw/ip/tlul_mailbox/doc/dv/index.md
@@ -2,12 +2,12 @@
title: "MAILBOX DV document"
---
-<!-- Copy this file to hw/top_matcha/ip/tlul_mailbox/doc/dv/index.md and make changes as needed.
+<!-- Copy this file to hw/ip/tlul_mailbox/doc/dv/index.md and make changes as needed.
For convenience 'tlul_mailbox' in the document can be searched and replaced easily with the
desired IP (with case sensitivity!). Also, use the testbench block diagram
located at OpenTitan team drive / 'design verification'
as a starting point and modify it to reflect your tlul_mailbox testbench and save it
-to hw/top_matcha/ip/tlul_mailbox/doc/dv/tb.svg. It should get linked and rendered under the block
+to hw/ip/tlul_mailbox/doc/dv/tb.svg. It should get linked and rendered under the block
diagram section below. Please update / modify / remove sections below as
applicable. Once done, remove this comment before making a PR. -->
@@ -21,10 +21,10 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
* [HW development stages]({{< relref "doc/project/development_stages" >}})
-* [Simulation results](https://reports.opentitan.org/hw/top_matcha/ip/tlul_mailboxdv/latest/results.html)
+* [Simulation results](https://reports.opentitan.org/hw/ip/tlul_mailboxdv/latest/results.html)
## Design features
-For detailed information on MAILBOX design features, please see the [MAILBOX HWIP technical specification]({{< relref "hw/top_matcha/ip/tlul_mailboxdoc" >}}).
+For detailed information on MAILBOX design features, please see the [MAILBOX HWIP technical specification]({{< relref "hw/ip/tlul_mailboxdoc" >}}).
## Testbench architecture
MAILBOX testbench has been constructed based on the [CIP testbench architecture]({{< relref "hw/dv/sv/cip_lib/doc" >}}).
@@ -33,8 +33,8 @@
### Top level testbench
-The top level testbench is located at `hw/top_matcha/ip/tlul_mailboxdv/tb.sv`.
-It instantiates the MAILBOX DUT module `hw/top_matcha/ip/tlul_mailboxrtl/tlul_mailbox.sv`.
+The top level testbench is located at `hw/ip/tlul_mailboxdv/tb.sv`.
+It instantiates the MAILBOX DUT module `hw/ip/tlul_mailboxrtl/tlul_mailbox.sv`.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
* [Clock and reset interface]({{< relref "hw/dv/sv/common_ifs" >}})
* [TileLink host interface]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
@@ -77,7 +77,7 @@
### Stimulus strategy
#### Test sequences
-The test sequences reside in `hw/top_matcha/ip/tlul_mailboxdv/env/seq_lib`.
+The test sequences reside in `hw/ip/tlul_mailboxdv/env/seq_lib`.
All test sequences are extended from `tlul_mailbox_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
@@ -109,7 +109,7 @@
Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
Here's how to run a smoke test:
```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_matcha/ip/tlul_mailboxdv/tlul_mailbox_sim_cfg.hjson -i tlul_mailbox_smoke
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/tlul_mailboxdv/tlul_mailbox_sim_cfg.hjson -i tlul_mailbox_smoke
```
## Testplan
diff --git a/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim.core b/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim.core
index a188a00..4f9f98e 100644
--- a/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim.core
+++ b/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim.core
@@ -25,6 +25,6 @@
- files_dv
default_tool: vcs
- # TODO: add a lint check cfg in `hw/top_matcha/lint/top_matcha_dv_lint_cfgs.hjson`
+ # TODO: add a lint check cfg in `hw/lint/top_matcha_dv_lint_cfgs.hjson`
lint:
<<: *sim_target
diff --git a/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim_cfg.hjson b/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim_cfg.hjson
index 969d4ca..d786c47 100644
--- a/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim_cfg.hjson
+++ b/hw/ip/tlul_mailbox/dv/tlul_mailbox_sim_cfg.hjson
@@ -18,10 +18,10 @@
fusesoc_core: google:dv:tlul_mailbox_sim:0.1
// Testplan hjson file.
- testplan: "{proj_root}/hw/top_matcha/ip/tlul_mailbox/data/tlul_mailbox_testplan.hjson"
+ testplan: "{proj_root}/hw/ip/tlul_mailbox/data/tlul_mailbox_testplan.hjson"
// RAL spec - used to generate the RAL model.
- ral_spec: "{proj_root}/hw/top_matcha/ip/tlul_mailbox/data/tlul_mailbox.hjson"
+ ral_spec: "{proj_root}/hw/ip/tlul_mailbox/data/tlul_mailbox.hjson"
// Import additional common sim cfg files.
// TODO: remove imported cfgs that do not apply.
diff --git a/hw/top_matcha/README.md b/hw/top_matcha/README.md
index d1bf259..ef87602 100644
--- a/hw/top_matcha/README.md
+++ b/hw/top_matcha/README.md
@@ -57,7 +57,7 @@
the list of peripherals, memories, crossbars, and interrupts in the configuration
file. The tool then reads relevant information from the configuration of each
peripheral block. For example, if the `dma` module is used, the tool reads
- `hw/matcha/hw/top_matcha/ip/dma/data/dma.hjson` and parses information such as
+ `hw/matcha/hw/ip/dma/data/dma.hjson` and parses information such as
input/output, the size of its register space, and interrupts.
The peripherals can be instantiated by `module` which is defined with multiple parameters.
diff --git a/util/bazel_airgapped.patch b/util/bazel_airgapped.patch
index 98cb12a..f87ec0b 100644
--- a/util/bazel_airgapped.patch
+++ b/util/bazel_airgapped.patch
@@ -12,7 +12,7 @@
- "@kelvin_core//:kelvin.core",
- ],
- "//conditions:default": [
-- "//hw/top_matcha/ip/dma/chisel:fastvdma.core",
+- "//hw/ip/dma/chisel:fastvdma.core",
- "@kelvin_hw//hdl/chisel:kelvin.core",
- ],
- }),
@@ -21,11 +21,11 @@
+ ],
)
diff --git a/hw/BUILD b/hw/BUILD
-index ec4c0d3..56ce85c 100644
+index cd7f31a..13d43fa 100644
--- a/hw/BUILD
+++ b/hw/BUILD
-@@ -83,14 +83,7 @@ filegroup(
- srcs = glob(["**"]) + [
+@@ -84,14 +84,7 @@ filegroup(
+ "//hw/ip:all_files",
"//hw/top_matcha:all_files",
"@lowrisc_opentitan//hw/dv:all_files",
- ] + select({
@@ -34,7 +34,7 @@
- "@kelvin_core//:all_files",
- ],
- "//conditions:default": [
-- "//hw/top_matcha/ip/dma/chisel:fastvdma_core",
+- "//hw/ip/dma/chisel:fastvdma_core",
- "@kelvin_hw//hdl/chisel:kelvin_core",
- ],
- }),
@@ -42,10 +42,10 @@
+ "@kelvin_core//:all_files",
+ ],
)
-diff --git a/hw/top_matcha/ip/dma/chisel/BUILD b/hw/top_matcha/ip/dma/chisel/BUILD
+diff --git a/hw/ip/dma/chisel/BUILD b/hw/ip/dma/chisel/BUILD
deleted file mode 100644
index 2a102ea..0000000
---- a/hw/top_matcha/ip/dma/chisel/BUILD
+--- a/hw/ip/dma/chisel/BUILD
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright 2023 Google LLC
@@ -65,14 +65,14 @@
-genrule(
- name = "fastvdma_verilog",
- srcs = [
-- "//hw/top_matcha/ip/dma/chisel/src:DMATop.sv"
+- "//hw/ip/dma/chisel/src:DMATop.sv"
- ],
- outs = [
- "fastvdma.sv",
- ],
-
- cmd = """
-- cat $(location //hw/top_matcha/ip/dma/chisel/src:DMATop.sv) >> $(location fastvdma.sv)
+- cat $(location //hw/ip/dma/chisel/src:DMATop.sv) >> $(location fastvdma.sv)
- """,
- visibility = ["//visibility:public"],
-)
@@ -93,10 +93,10 @@
- """,
- visibility = ["//visibility:public"],
-)
-diff --git a/hw/top_matcha/ip/dma/chisel/src/BUILD b/hw/top_matcha/ip/dma/chisel/src/BUILD
+diff --git a/hw/ip/dma/chisel/src/BUILD b/hw/ip/dma/chisel/src/BUILD
deleted file mode 100644
index 745cb3f..0000000
---- a/hw/top_matcha/ip/dma/chisel/src/BUILD
+--- a/hw/ip/dma/chisel/src/BUILD
+++ /dev/null
@@ -1,54 +0,0 @@
-# Copyright 2024 Google LLC
