commit	0f13aca8866b36ae203fdfce0a95b24c7960a47f	[log] [tgz]
author	Cindy Liu <hcindyl@google.com>	Wed Mar 15 20:29:59 2023 -0700
committer	Bangfei <pbf@google.com>	Thu Apr 06 19:14:36 2023 +0000
tree	f57b2d029a24ce08c2eac0d933f88eb44af83f7c
parent	7304706104ad5ddff6becb2849e0d8982beee450 [diff]

[HW][TOP] Update top level together with opentitan f243e680

1. Update WORKSPACE
2. Update util topgen functionality and templates
3. Update top_matcha.hjson based on the merge of opentitan f243e680
4. Update xbar_dbg.hjson for th rv_dm.mem (was rom).
5. Update dv/env files.
6. Update several lint files
7. Update chip_matcha_verilator.sv
8. Update files under lint/ and cdc/
9. Update the util/vivado_hook_write_bitstream_pre.tcl
10. Added new rdc/ folder as placeholder
11. Updated the syn/chip_matcha_asic.sdc
12. Updated rtl/chip_matcha_verilator.sv
13: Update all files under hw/top_matcha/dv/verilator/*
14. Absorbed the rv_time_smc2 change.
15. Fixed a IO level for W31 pin in pins_nexus.xdc.
16. Add "testonly = true" for all targets at hw/bitstream/vivado/BUILD
17. Reserve 4KB register space in isp_wrapper.hjson
18. Add more IO delay (was missing) in clocks.xdc which help the hold
    time violation, and fixed the BRAM primitive type in the tcl file.

Change-Id: Id252779cde5cf1de869aee49a64975d1ad9878e1

196 files changed

tree: f57b2d029a24ce08c2eac0d933f88eb44af83f7c

README.md

Matcha

About the project

[Matcha] will be an open source SOC(system on chip) project.

About this repository

This repository contains hardware, software and utilities written as part of the Matcha project. Plus it leverages the Opentitan Repository for its HW IPs, templates and utilities.

Documentation

The project contains comprehensive documentation of all IPs and tools. You can access it.

How to contribute

Have a look at our GettingStarted Guide for guidelines on how to contribute code to this repository.

Licensing

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).

Prerequisites

Development for matcha requires that the necessary tools and prerequisites be installed. See GettingStarted Guide

To setup the build system, run following steps at root of repo:

source build/setup.sh

Install the prerequisites:

m prereqs

Install the tools used for development:

m tools

Code/Repo Structure

<root_dir>/hw/matcha/
    hw/top_matcha/
        BUILD
        data/
        dv/
        formal/
        ip/
        ip_autogen/
        ip_templates/
        lint/
        rtl/
        sw/
        syn/
        util/
    hw/
        BUILD
        Makefile
    sw/
        BUILD
        device/
        hw_tests/
        Maefile
    util/
        BUILD
        topgen/
        topgen_util
        topgen_matcha.py

<root_dir>/hw/opentitan_upstream/
<root_dir>/build/
<root_dir>/Manifest/
<root_dir>/Makefile
<root_dir>/GettingStarted.md
<toot_dir>/...

Quick start guide and cheat sheet

For following steps, make sure the above “Prerequisites” steps have been run if the repo is been checked out at the first time.

Build RTL top Level and generate registers, interrupt and address map:

m matcha_hw_generate_all

Build verilator simulation target:

m matcha_hw_verilator_sim

Run matcha verilator test suite

m matcha_hw_verilator_tests

Run FPGA compilation flow for V6 FPGA board:

m matcha_hw_fpga_v6

Run FPGA compilation flow for Nexus FPGA board:

m matcha_hw_fpga_nexus

Bazel debug

Run matcha single test with messages to stdout

bazel test --test_output=streamed //sw/device/tests:verilator_mailbox_test

Run matcha test suites

bazel test --test_output=streamed //sw/device/tests:verilator_test_suite

Run FPGA compilation flow for V6 FPGA board with debug commands:

bazel build -s //hw/bitstream/vivado:fpga_v6

Simulation logs

Enable tracing on a single test

bazel test --test_output=streamed  --test_timeout=1000000 --test_arg=--trace //sw/device/tests:verilator_cam_ctrl_test

Note: --test_timeout=1000000 sets timeout in seconds. This helps prevent timeout issues then using trace.

Waveform dump and peripheral logs for a test located in:

<root_dir>/hw/matcha/bazel-testlogs/sw/device/tests/<test_name>/test.outputs/output.zip
    sim.fst (if tracing is enabled)
    uart0.log
    smc_uart.log
    spi0.log
    usb0.log

Note: The trace_core_#.log files available in output.zip is currently a TODO item.

The FPGA compiled bitstream and reports (resource utilization, pin assignment, etc) can be found in following directory:

<matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_v6/synth-vivado/google_systems_chip_matcha_v6_0.1.runs/impl_1/chip_matcha_v6.bit <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_v6/synth-vivado/google_systems_chip_matcha_v6_0.1.runs/impl_1/.rpt <matcha_root_dir>/bazel-bin/hw/bitstream/vivado/build.fpga_v6/synth-vivado/google_systems_chip_matcha_v6_0.1.runs/synth_1/.rpt

DV flow

Setup DV flow