Port Width Fixes: Required for syn
Synopsys synthesis will not resolve port mismatches in real time and
mismatches therefore result in matcha syn runs failing.
This CL topic fixes port width mismatches in matcha and ips
A separate CL:1600 in opensecura 3p/ip/isp was also made in an effort to
fix port mismatches.
https://opensecura-review.git.corp.google.com/c/3p/ip/isp/+/1600
Change-Id: I72e5014a8a4182bb71cf53811ae4e5315f319752
diff --git a/hw/ip/ahb/rtl/ahb_pkg.sv b/hw/ip/ahb/rtl/ahb_pkg.sv
index 4543234..8d7f8ab 100644
--- a/hw/ip/ahb/rtl/ahb_pkg.sv
+++ b/hw/ip/ahb/rtl/ahb_pkg.sv
@@ -17,8 +17,8 @@
typedef struct packed {
logic [top_pkg::TL_AW-1:0] haddr;
- logic [top_pkg::TL_SZW-1:0] hsize;
- logic [1:0] hburst;
+ logic [2:0] hsize;
+ logic [2:0] hburst;
logic [top_pkg::TL_DW-1:0] hwdata;
logic [1:0] htrans;
logic hwrite;
diff --git a/hw/ip/isp_wrapper/rtl/isp_wrapper.sv b/hw/ip/isp_wrapper/rtl/isp_wrapper.sv
index 82ee88d..b1ccd1d 100644
--- a/hw/ip/isp_wrapper/rtl/isp_wrapper.sv
+++ b/hw/ip/isp_wrapper/rtl/isp_wrapper.sv
@@ -61,11 +61,11 @@
output out_cr_b_line_start_o,
output out_cr_b_line_end_o,
output out_y_r_val_stream_o,
- output out_y_r_data_stream_o,
output out_cb_g_val_stream_o,
- output out_cb_g_data_stream_o,
output out_cr_b_val_stream_o,
- output out_cr_b_data_stream_o,
+ output [7:0] out_y_r_data_stream_o,
+ output [7:0] out_cb_g_data_stream_o,
+ output [7:0] out_cr_b_data_stream_o,
//the others
input disable_isp_i,
input scanmode_i
@@ -134,6 +134,9 @@
.hresp (ahb_d2h.hresp)
);
+ logic [1:0] hresp_marvin_out_pre;
+ assign ahb_d2h.hresp = hresp_marvin_out_pre[0];
+
VSISP_MARVIN_TOP_X u_isp
(/*AUTOINST*/
//MP Outputs
@@ -169,7 +172,7 @@
.axi_m2_marvin_wid (axi_sp_o.wid[3:0]),
.axi_m2_marvin_bready (axi_sp_o.bready),
.hrdata_s (ahb_d2h.hrdata),
- .hresp_s (ahb_d2h.hresp),
+ .hresp_s (hresp_marvin_out_pre), // Widen single bit to 2 bits for port compatibility vsisp_marvin
.hready_s (ahb_d2h.hready),
.mi_irq (intr_mi_o),
.isp_irq (intr_isp_o),
@@ -224,12 +227,12 @@
.out_cr_b_ack_stream (1'b1));
-axi2sramcrs u_axi2sramcrs (
+axi2sramcrs #() u_axi2sramcrs (
.aclk (clk_i),
.aresetn (rst_ni),
.awid_s (axi_o.awid),
.awaddr_s ({axi_o.awaddr[31:3],3'b0}),
- .awlen_s (axi_o.awlen),
+ .awlen_s (axi_o.awlen[3:0]), // 4 wide for axi3 used in axi2sramcrs
.awsize_s (axi_o.awsize),
.awburst_s (axi_o.awburst),
.awlock_s (axi_o.awlock),
@@ -261,12 +264,16 @@
.sram_wmask (isp_wmask_o)
);
-axi2sramcrs u_axi2sramcrs_sp (
+axi2sramcrs #(
+ .AWID_WIDTH($bits(axi_sp_o.awid)),
+ .ARID_WIDTH($bits(axi_sp_o.awid)),
+ .ADDR_WIDTH($bits(axi_sp_o.awaddr))
+)u_axi2sramcrs_sp (
.aclk (clk_i),
.aresetn (rst_ni),
.awid_s (axi_sp_o.awid),
.awaddr_s ({axi_sp_o.awaddr[31:3],3'b0}),
- .awlen_s (axi_sp_o.awlen),
+ .awlen_s (axi_o.awlen[3:0]), // 4 wide for axi3 used in axi2sramcrs
.awsize_s (axi_sp_o.awsize),
.awburst_s (axi_sp_o.awburst),
.awlock_s (axi_sp_o.awlock),
diff --git a/hw/ip/ml_top/rtl/ml_top.sv b/hw/ip/ml_top/rtl/ml_top.sv
index 0699f4f..a8a3f6f 100644
--- a/hw/ip/ml_top/rtl/ml_top.sv
+++ b/hw/ip/ml_top/rtl/ml_top.sv
@@ -135,7 +135,8 @@
// Writing 0 will take it out of reset.
// Kelvin core execution start address {PC[21:0]}, 4MB address space. See register definition for bitfield lsb.
- .pc_start (ctrl.pc_start),
+ // Expand 22 bit ctrl.pc_start in ml_top control register to 32 bit pc_start in kelvin to avoid port width mismatch
+ .pc_start ({10'b0, ctrl.pc_start}),
.volt_sel (ctrl.volt_sel), // Default 0 for 0.8V memory macros, write 1 for 0.65V.
// SRAM Interface
diff --git a/hw/ip/tluh/rtl/tluh_adapter_sram.sv b/hw/ip/tluh/rtl/tluh_adapter_sram.sv
index 1461757..988bc92 100644
--- a/hw/ip/tluh/rtl/tluh_adapter_sram.sv
+++ b/hw/ip/tluh/rtl/tluh_adapter_sram.sv
@@ -101,6 +101,12 @@
.tl_o
);
+ localparam int DataWidth = top_pkg::TL_DW;
+ localparam int BusAddrWidth = top_pkg::TL_AW;
+ localparam int MemAddrWidth = BusAddrWidth - $clog2(DataWidth / 8);
+
+ logic [MemAddrWidth-1 : 0] addr_o_pre;
+ assign addr_o = (top_pkg::TL_AW)'(addr_o_pre);
tluh_mem_bridge #(
) mem_bridge (
@@ -109,7 +115,7 @@
.tlu_port (tluh_if.target),
- .mem_address(addr_o),
+ .mem_address(addr_o_pre),
.mem_we(we_o),
.mem_wdata(wdata_o),
.mem_ble(mem_ble_int),
diff --git a/hw/ip/tlul2ahblite/rtl/tlul2ahblite.v b/hw/ip/tlul2ahblite/rtl/tlul2ahblite.v
index 5a501c6..34bd1e4 100644
--- a/hw/ip/tlul2ahblite/rtl/tlul2ahblite.v
+++ b/hw/ip/tlul2ahblite/rtl/tlul2ahblite.v
@@ -155,7 +155,8 @@
ahblite_enc #(
.AhbLiteDataWidth (AhbLiteDataWidth),
- .TlulDataWidth (TlulDataWidth)
+ .TlulDataWidth (TlulDataWidth),
+ .IdWidth ( IdWidth )
) u_ahblite_enc (/*AUTOINST*/
// Outputs
.haddr (haddr[31:0]),
diff --git a/hw/ip/tlul2axi4/rtl/axi_enc.v b/hw/ip/tlul2axi4/rtl/axi_enc.v
index 86d49c2..b5dea13 100644
--- a/hw/ip/tlul2axi4/rtl/axi_enc.v
+++ b/hw/ip/tlul2axi4/rtl/axi_enc.v
@@ -81,7 +81,7 @@
output awvalid;
output [IdWidth-1:0] awid;
output [31:0] awaddr;
-output [7:0] awlen;
+output [3:0] awlen;
output [AxiSizeWidth-1:0] awsize;
output [1:0] awburst;
input wready;
@@ -182,7 +182,7 @@
assign bready = resp_ready;
assign awid = req_id;
assign awaddr = addr;
-assign awlen = 8'h0;
+assign awlen = 4'h0;
assign awsize = size;
assign awburst = 2'b01;
assign wlast = wvalid;
diff --git a/hw/ip/tlul2axi4/rtl/tlul2axi.v b/hw/ip/tlul2axi4/rtl/tlul2axi.v
index 380ec51..17b4c0a 100644
--- a/hw/ip/tlul2axi4/rtl/tlul2axi.v
+++ b/hw/ip/tlul2axi4/rtl/tlul2axi.v
@@ -103,7 +103,7 @@
output awvalid;
output [IdWidth-1:0] awid;
output [31:0] awaddr;
-output [7:0] awlen;
+output [3:0] awlen;
output [AxiSizeWidth-1:0] awsize;
output [1:0] awburst;
input wready;
@@ -196,7 +196,7 @@
.awvalid (awvalid),
.awid (awid[IdWidth-1:0]),
.awaddr (awaddr[31:0]),
- .awlen (awlen[7:0]),
+ .awlen (awlen[3:0]),
.awsize (awsize[AxiSizeWidth-1:0]),
.awburst (awburst[1:0]),
.wvalid (wvalid),
diff --git a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
index 6ece7be..2b41812 100644
--- a/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
+++ b/hw/top_matcha/rtl/autogen/chip_matcha_nexus.sv
@@ -969,9 +969,9 @@
- ///////////////////
- // USB for FPGA //
- ///////////////////
+ //////////////////////////////////////////////
+ // USB for FPGA (USB1T1105AMHX transceiver) //
+ //////////////////////////////////////////////
logic usb_rx_d;
logic usb_tx_d;
logic usb_tx_se0;
@@ -988,20 +988,20 @@
// VP / VPO
assign manual_attr_io_uphy_vpo = '0;
- assign manual_oe_io_uphy_vpo = 1'b1;
assign manual_out_io_uphy_vpo = dio_out[DioUsbdevUsbDp];
+ assign manual_oe_io_uphy_vpo = 1'b1;
assign dio_in[DioUsbdevUsbDp] = manual_in_io_uphy_vp;
// VM / VMO
assign manual_attr_io_uphy_vmo = '0;
- assign manual_oe_io_uphy_vmo = 1'b1;
assign manual_out_io_uphy_vmo = dio_out[DioUsbdevUsbDn];
+ assign manual_oe_io_uphy_vmo = 1'b1;
assign dio_in[DioUsbdevUsbDn] = manual_in_io_uphy_vm;
// MODE
assign manual_attr_io_uphy_mode = '0;
- assign manual_oe_io_uphy_mode = 1'b1;
assign manual_out_io_uphy_mode = 1'b1;
+ assign manual_oe_io_uphy_mode = 1'b1;
// CONFIG
assign manual_attr_io_uphy_cfg = '0;
diff --git a/hw/top_matcha/rtl/autogen/top_matcha.sv b/hw/top_matcha/rtl/autogen/top_matcha.sv
index bac7343..c5ec406 100644
--- a/hw/top_matcha/rtl/autogen/top_matcha.sv
+++ b/hw/top_matcha/rtl/autogen/top_matcha.sv
@@ -1070,6 +1070,10 @@
logic ram_smc_rvalid;
logic [1:0] ram_smc_rerror;
+ // intermediate addr to avoid port with mismatch
+ logic [top_pkg::TL_AW-1:0] ram_smc_addr_pre;
+ assign ram_smc_addr = ram_smc_addr_pre[19:0];
+
tluh_adapter_sram #(
.MemLatency(1),
.MaxBurstSize(2)
@@ -1082,7 +1086,7 @@
.req_o (ram_smc_req),
.gnt_i (ram_smc_req), // Grant when requests occur
.we_o (ram_smc_we),
- .addr_o (ram_smc_addr),
+ .addr_o (ram_smc_addr_pre),
.wdata_o (ram_smc_wdata),
.wmask_o (ram_smc_wmask),
.rdata_i (ram_smc_rdata),
@@ -2530,7 +2534,7 @@
.jtag_o(pinmux_aon_rv_jtag_rsp),
.lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
.pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en),
- .unavailable_i(2'b0),
+ .unavailable_i(3'b0),
.ndmreset_req_o(rv_dm_ndmreset_req),
.dmactive_o(),
.debug_req_o(rv_dm_debug_req),
diff --git a/util/topgen_matcha/templates/toplevel.sv.tpl b/util/topgen_matcha/templates/toplevel.sv.tpl
index 6cd9ec8..87bfd1c 100644
--- a/util/topgen_matcha/templates/toplevel.sv.tpl
+++ b/util/topgen_matcha/templates/toplevel.sv.tpl
@@ -357,6 +357,10 @@
logic ${lib.bitarray(1, max_char)} ${m["name"]}_rvalid;
logic ${lib.bitarray(2, max_char)} ${m["name"]}_rerror;
+ // intermediate addr to avoid port width mismatch
+ logic [top_pkg::TL_AW-1:0] ${m["name"]}_addr_pre;
+ assign ${m["name"]}_addr = ${m["name"]}_addr_pre${lib.bitarray(addr_width, max_char)};
+
tluh_adapter_sram #(
.MemLatency(1),
.MaxBurstSize(2)
@@ -373,7 +377,7 @@
.req_o (${m["name"]}_req),
.gnt_i (${m["name"]}_req), // Grant when requests occur
.we_o (${m["name"]}_we),
- .addr_o (${m["name"]}_addr),
+ .addr_o (${m["name"]}_addr_pre),
.wdata_o (${m["name"]}_wdata),
.wmask_o (${m["name"]}_wmask),
.rdata_i (${m["name"]}_rdata),
