sw/device/lib/testing/test_rom/test_rom_cheri.ld

/* Copyright 2023 Google LLC. */
/* Copyright lowRISC contributors. */
/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */
/* SPDX-License-Identifier: Apache-2.0 */

/**
 * Linker script for an OpenTitan (test) boot ROM on CHERIoT.
 */

OUTPUT_ARCH(riscv)

/**
 * Indicate that there are no dynamic libraries, whatsoever.
 */
__DYNAMIC = 0;

INCLUDE hw/top_matcha/sw/autogen/top_matcha_memory_cheri.ld

/**
 * The boot address, which indicates the location of the initial interrupt
 * vector.
 */
_boot_address = ORIGIN(rom);

/**
 * Symbols to be used in the setup of the address translation for ROM_EXT.
 */

_rom_digest_size = 32;
/*_chip_info_start = ORIGIN(rom) + LENGTH(rom) - _rom_digest_size - _chip_info_size;*/

/* DV Log offset (has to be different to other boot stages). */
_dv_log_offset = 0x0;

/**
 * We define an entry point only for documentation purposes (and to stop LLD
 * erroring). In reality, we don't use this information within the ROM image, as
 * we start at a fixed offset.
 */
ENTRY(_reset_start);

/**
 * NOTE: We have to align each section to word boundaries as our current
 * s19->slm conversion scripts are not able to handle non-word aligned sections.
 */
SECTIONS {
  /**
   * Ibex interrupt vector. See test_rom_start.S for more information.
   *
   * This has to be set up at the boot address, so that execution jumps to the
   * reset handler correctly.
   * XXX not used on CHERIoT where only direct mode is supported
   */
  .vectors _boot_address : ALIGN(4) {
    KEEP(*(.vectors))
  } > rom
  /**
   * Standard text section, containing program code.
   */
  .text : ALIGN(4) {
    *(.text)
    *(.text.*)
    *(.crt)  /* currently in crt_cheri.S, could be merged */

    /**
     * Read-only data section, containing all large compile-time constants, like
     * strings. Note this goes inside the output text segment to get pcc-relative
     * addressing; otherwise it is considered global DATA and cgp-relative
     * addressing is generated.
     */
    /* Small read-only data comes before regular read-only data for the same
     * reasons as in the data section */
    *(.srodata)
    *(.srodata.*)
    *(.rodata)
    *(.rodata.*)

    /**
     * Immutable chip_info data, containing build-time-recorded information.
     */
    (*(.chip_info))
  } > rom

  /**
   * Standard mutable data section, at the bottom of RAM. This is
   * initialized from the .idata section at runtime by the CRT.
   */
  .data : ALIGN(4) {
    _data_start = .;
    _data_init_start = LOADADDR(.data);

    /**
     * Critical static data.
     * NB: want only in RAM but this data needs to be in the same
     *     segment as other data to be addressable through cgp
     */
    KEEP(*(.static_critical.boot_measurements))
    KEEP(*(.static_critical.epmp_state))
    KEEP(*(.static_critical.sec_mmio_ctx))

    /* Small data should come before larger data. This helps to ensure small
     * globals are within 2048 bytes of the value of `gp`, making their accesses
     * hopefully only take one instruction. */
    *(.sdata)
    *(.sdata.*)

    /* Other data will likely need multiple instructions to load, so we're less
     * concerned about address materialisation taking more than one instruction.
     */
    *(.data)
    *(.data.*)

    /* Ensure section end is word-aligned. */
    . = ALIGN(4);
    _data_end = .;
    _data_init_end = LOADADDR(.data) + SIZEOF(.data);

    _bss_start = .;
    /* Small BSS comes before regular BSS for the same reasons as in the data
     * section */
    *(.sbss)
    *(.sbss.*)
    *(.bss)
    *(.bss.*)
    . = ALIGN(4);
    _bss_end = .;

    /* This puts it in ram_main at runtime (for the VMA), but puts the section
     * into rom for load time (for the LMA). This is why `_data_init_*` uses
     * `LOADADDR`. */
  } > ram_rom AT> rom

  /**
   * Discard capability relocation data. There are no global caps
   * to be relocated. XXX need to undestand where these are coming from
   */
  /DISCARD/ : { *(__cap_relocs) }

  INCLUDE external/lowrisc_opentitan/sw/device/info_sections.ld
}