sw/device/examples/demo_hps_from_test_images/kelvin_model_smc.c

/*
 * Copyright 2023 Google LLC
 * Copyright lowRISC contributors
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

#include "hw/top_matcha/ip/ml_top/data/ml_top_regs.h"  // Generated.
#include "hw/top_matcha/sw/autogen/top_matcha.h"
#include "sw/device/examples/testdata/hps_images/hps_images.h"  // Generated.
#include "sw/device/examples/testdata/kelvin_model_ml_bin.h"    // Generated.
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/dif/dif_ml_top.h"
#include "sw/device/lib/dif/dif_rv_plic.h"
#include "sw/device/lib/dif/dif_uart.h"
#include "sw/device/lib/runtime/irq.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/test_framework/check.h"
#include "sw/device/lib/testing/test_framework/ottf_test_config.h"
#include "sw/device/lib/testing/test_framework/status.h"
#include "sw/device/lib/testing/test_framework/test_util.h"

#define TOP_MATCHA_RAM_ML_DMEM_IMG_OFFSET_ADDR 0x00300000
#define TOP_MATCHA_RAM_ML_DMEM_OUT_OFFSET_ADDR 0x00380000
#define TOP_MATCHA_RAM_ML_DMEM_CMD_OFFSET_ADDR 0x003FF000

OTTF_DEFINE_TEST_CONFIG();

static dif_ml_top_t ml_top;
static dif_rv_plic_t plic_smc;
static dif_uart_t smc_uart;

static volatile bool ml_top_finish_done = false;

static void handle_ml_top_isr(const dif_rv_plic_irq_id_t interrupt_id) {
  switch (interrupt_id) {
    case kTopMatchaPlicIrqIdMlTopFinish:
      ml_top_finish_done = true;
      break;
    case kTopMatchaPlicIrqIdMlTopFinish | kTopMatchaPlicIrqIdMlTopFault:
      LOG_ERROR("ML core raised fault interrupt.");
      test_status_set(kTestStatusFailed);
    default:
      LOG_FATAL("ISR is not implemented!");
      test_status_set(kTestStatusFailed);
  }
  CHECK_DIF_OK(dif_ml_top_reset_ctrl_en(&ml_top));
  CHECK_DIF_OK(dif_ml_top_irq_acknowledge_all(&ml_top));
}

void ottf_external_isr(void) {
  // Claim the IRQ by reading the Ibex specific CC register.
  dif_rv_plic_irq_id_t interrupt_id;

  CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                     &interrupt_id));

  // Check if the interrupted peripheral is ISP WRAPPER.
  top_matcha_plic_peripheral_smc_t peripheral_id =
      top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
  CHECK(peripheral_id == kTopMatchaPlicPeripheralMlTop,
        "Unexpected peripheral in ISR: %d", peripheral_id);
  switch (peripheral_id) {
    case kTopMatchaPlicPeripheralMlTop: {
      handle_ml_top_isr(interrupt_id);
      break;
    }
    default:
      LOG_FATAL("Peripheral is not implemented!");
  }

  // Complete the IRQ by writing the IRQ source to the Ibex specific CC
  // register.
  CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic_smc, kTopMatchaPlicTargetIbex0Smc,
                                        interrupt_id));
}

// Configures all relevant interrupts in PLIC_SMC.
static void plic_smc_configure_irqs(dif_rv_plic_t *plic) {
  // Set IRQ priorities to MAX
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
      plic, kTopMatchaPlicIrqIdMlTopFinish, kDifRvPlicMaxPriority));
  CHECK_DIF_OK(dif_rv_plic_irq_set_priority(plic, kTopMatchaPlicIrqIdMlTopFault,
                                            kDifRvPlicMaxPriority));

  // Set Ibex IRQ priority threshold level
  CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
      plic, kTopMatchaPlicTargetIbex0Smc, kDifRvPlicMinPriority));

  // Enable ML core IRQs
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFinish,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
  CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(plic, kTopMatchaPlicIrqIdMlTopFault,
                                           kTopMatchaPlicTargetIbex0Smc,
                                           kDifToggleEnabled));
}

void _ottf_main(void) {
  test_status_set(kTestStatusInTest);
  init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
  LOG_INFO("[SMC] Start from SMC!");

  // Init IRQs
  CHECK_DIF_OK(dif_rv_plic_init(
      mmio_region_from_addr(TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR), &plic_smc));
  plic_smc_configure_irqs(&plic_smc);
  irq_global_ctrl(true);
  irq_external_ctrl(true);

  // Init ML_TOP
  CHECK_DIF_OK(dif_ml_top_init(
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_CORE_BASE_ADDR), &ml_top));
  CHECK_DIF_OK(dif_ml_top_irq_set_enabled(&ml_top, kDifMlTopIrqFinish,
                                          kDifToggleEnabled));
  CHECK_DIF_OK(dif_ml_top_irq_set_enabled(&ml_top, kDifMlTopIrqFault,
                                          kDifToggleEnabled));
  dif_ml_top_reset_ctrl_en(&ml_top);

  // Create an array with the pointers to the image frame
  // Cast the type from unsigned char into uint32_t
  const uint32_t *const hps_image_frame[] = {
      (const uint32_t *)hps_0, (const uint32_t *)hps_1, (const uint32_t *)hps_2,
      (const uint32_t *)hps_3, (const uint32_t *)hps_4, (const uint32_t *)hps_5,
      (const uint32_t *)hps_6};
  const unsigned int hps_image_frame_byte_len[] = {
      hps_0_len, hps_1_len, hps_2_len, hps_3_len,
      hps_4_len, hps_5_len, hps_6_len};
  const int kNumOfFrames = 7;

  const int expected_output[][2] = {
      {-118, -128}, {127, -128}, {127, 127},  {-115, -128},
      {-97, -128}, {127, -128}, {127, -115},
  };

  // Fill the memory with zeroes.
  mmio_region_t ml_dmem =
      mmio_region_from_addr(TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR);
  for (int i = 0; i < TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES / sizeof(uint32_t);
       ++i) {
    mmio_region_write32(ml_dmem, i * sizeof(uint32_t), 0);
  }
  LOG_INFO("[SMC] Finished initializing ML DMEM");

  // Load Kelvin binary.
  uint32_t *kelvin_bin_uint32 = (uint32_t *)kelvin_bin;
  for (int i = 0; i < kelvin_bin_len / sizeof(uint32_t); ++i) {
    mmio_region_write32(ml_dmem, i * sizeof(uint32_t), kelvin_bin_uint32[i]);
  }
  LOG_INFO("[SMC] Finished loading Kelvin binary");
  mmio_region_write32(ml_dmem, TOP_MATCHA_RAM_ML_DMEM_CMD_OFFSET_ADDR,
                      TOP_MATCHA_RAM_ML_DMEM_IMG_OFFSET_ADDR);
  mmio_region_write32(ml_dmem,
                      TOP_MATCHA_RAM_ML_DMEM_CMD_OFFSET_ADDR + sizeof(uint32_t),
                      TOP_MATCHA_RAM_ML_DMEM_OUT_OFFSET_ADDR);

  mmio_region_t ml_hps_base =
      mmio_region_from_addr(TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR +
                            TOP_MATCHA_RAM_ML_DMEM_IMG_OFFSET_ADDR);
  CHECK_DIF_OK(dif_ml_top_reset_ctrl_en(&ml_top));
  for (int frame_idx = 0; frame_idx < kNumOfFrames; ++frame_idx) {
    // Load HPS images 0-6 into ML DMEM.
    LOG_INFO("[SMC] Start frame [%d]", frame_idx);
    CHECK(hps_image_frame_byte_len[frame_idx] % sizeof(uint32_t) == 0,
          "The frame is not word align");
    for (uintptr_t word_idx = 0;
         word_idx < hps_image_frame_byte_len[frame_idx] / sizeof(uint32_t);
         ++word_idx) {
      uintptr_t offset = word_idx * sizeof(uint32_t);
      mmio_region_write32(ml_hps_base, offset,
                          hps_image_frame[frame_idx][word_idx]);
    }

    // Start up Kelvin.
    ml_top_finish_done = false;
    CHECK_DIF_OK(dif_ml_top_release_ctrl_en(&ml_top));
    while (!ml_top_finish_done) {
      asm volatile("wfi");
    }

    // Verify model output
    mmio_region_t ml_model_out_base =
        mmio_region_from_addr(TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR +
                              TOP_MATCHA_RAM_ML_DMEM_OUT_OFFSET_ADDR);
    const int8_t model_out_val0 = mmio_region_read8(ml_model_out_base, 0);
    const int8_t model_out_val1 = mmio_region_read8(ml_model_out_base, 1);
    CHECK(model_out_val0 == expected_output[frame_idx][0] &&
              model_out_val1 == expected_output[frame_idx][1],
          "Frame %d failed - Expected: {%d, %d} | Actual: {%d, %d}", frame_idx,
          expected_output[frame_idx][0], expected_output[frame_idx][1],
          model_out_val0, model_out_val1);
  }

  test_status_set(kTestStatusPassed);
  asm volatile("wfi");
}