hw/top_matcha/data/xbar_smc.hjson

// Copyright 2023 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

{ name: "smc",
  type: "xbar",
  clock_primary: "clk_smc_i", // Main clock, used in sockets
  other_clock_list: [ "clk_peri_i", "clk_spi_host2_i" , "clk_ml_i", "clk_video_i", "clk_audio_i", "clk_main_i"],
  reset_primary: "rst_smc_ni", // Main reset, used in sockets
  other_reset_list: [ "rst_peri_ni", "rst_spi_host2_ni" , "rst_ml_ni" , "rst_video_ni", "rst_audio_ni", "rst_main_ni"],

  nodes: [
    { name:     "main",
      type:     "host",
      clock:    "clk_smc_i",
      reset:    "rst_smc_ni",
      xbar:     "true",
      pipeline: "false"
    },
    { name:     "rv_core_ibex_smc.corei",
      type:     "host",
      clock:    "clk_smc_i",
      reset:    "rst_smc_ni",
      pipeline: "false"
    },
    { name:     "rv_core_ibex_smc.cored",
      type:     "host",
      clock:    "clk_smc_i",
      reset:    "rst_smc_ni",
      pipeline: "false"
    },
    { name:     "dma_smc.reader",
      type:     "host",
      clock:    "clk_smc_i",
      reset:    "rst_smc_ni",
      pipeline: "false"
    },
    { name:     "dma_smc.writer",
      type:     "host",
      clock:    "clk_smc_i",
      reset:    "rst_smc_ni",
      pipeline: "false"
    },
    { name:         "rv_plic_smc",
      type:         "device",
      clock:        "clk_smc_i",
      reset:        "rst_smc_ni",
      inst_type:    "rv_plic",
      pipeline_byp: "false"
    },
    { name:         "rv_core_ibex_smc.cfg",
      type:         "device",
      clock:        "clk_smc_i"
      reset:        "rst_smc_ni"
      pipeline_byp: "false"
    },
    { name:      "ram_smc",
      type:      "device",
      clock:     "clk_smc_i",
      reset:     "rst_smc_ni",
      pipeline:  "false"
    },
    { name:      "smc_uart",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "rv_timer_smc",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "tlul_mailbox_smc",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "smc_ctrl",
      type:      "device",
      clock:     "clk_smc_i",
      reset:     "rst_smc_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "cam_i2c",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "cam_ctrl",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "ml_top.dmem",
      type:      "device",
      clock:     "clk_ml_i",
      reset:     "rst_ml_ni",
      pipeline:  "false"
    },
    { name:      "ml_top.core",
      type:      "device",
      clock:     "clk_ml_i",
      reset:     "rst_ml_ni",
      pipeline:  "false"
    },
    { name:      "isp_wrapper",
      type:      "device",
      clock:     "clk_smc_i",
      reset:     "rst_smc_ni",
      pipeline:  "false"
    },
    { name:      "dma_smc",
      type:      "device",
      clock:     "clk_smc_i",
      reset:     "rst_smc_ni",
      pipeline:  "false"
    },
    { name:      "spi_host2",
      type:      "device",
      clock:     "clk_spi_host2_i",
      reset:     "rst_spi_host2_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "dbg",
      type:      "device",
      clock:     "clk_main_i",
      reset:     "rst_main_ni",
      xbar:      "true",
      pipeline:  "false"
    },
    { name:      "rv_timer_smc2",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
    { name:      "i2s0",
      type:      "device",
      clock:     "clk_peri_i",
      reset:     "rst_peri_ni",
      req_fifo_pass: false,
      rsp_fifo_pass: false,
    },
  ],
  connections: {
    // TODO: connections from main xbar (security core) to some of the SMC subsystem peripherals,
    //       such as smc_uart, rv_timer_smc, cam_i2c, cam_ctrl, isp_wrapper are optional to
    //       allow software tests to run from the security core. They may be removed
    //       in the final silicon netlist.
    main:  ["ram_smc", "smc_ctrl", "smc_uart", "rv_timer_smc", "cam_i2c", "cam_ctrl",
             "ml_top.dmem","ml_top.core", "isp_wrapper", "dma_smc", "spi_host2", "rv_timer_smc2", "i2s0"],

    rv_core_ibex_smc.corei:  ["ram_smc", "dbg"],
    rv_core_ibex_smc.cored:  [ "ram_smc", "rv_core_ibex_smc.cfg",
      "smc_uart", "rv_timer_smc", "rv_plic_smc", "tlul_mailbox_smc", "cam_i2c", "cam_ctrl",
      "ml_top.dmem", "ml_top.core", "isp_wrapper", "dma_smc", "spi_host2", "dbg", "rv_timer_smc2", "i2s0"],
     dma_smc.reader:  ["ram_smc", "ml_top.dmem"],
     dma_smc.writer:  ["ram_smc", "ml_top.dmem"],
  },
}