hw/top_matcha/chip_matcha_nexus.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "google:systems:chip_matcha_nexus:0.1"
description: "Matcha toplevel for the Nexus board"
filesets:
  files_rtl_nexus:
    depend:
      - lowrisc:systems:top_matcha:0.1
      - lowrisc:systems:top_matcha_pkg
      - google:systems:ast
      - lowrisc:systems:padring
    files:
      - rtl/clkgen_xilultrascaleplus.sv
      - rtl/usr_access_xil7series.sv
      - rtl/autogen/chip_matcha_nexus.sv
    file_type: systemVerilogSource

  files_constraints:
    files:
      - data/clocks_nexus.xdc
      - data/pins_nexus.xdc
      - data/placement.xdc
    file_type: xdc

  files_tcl:
    files:
      - util/vivado_setup_hooks.tcl: { file_type: tclSource }
      # File copied by fusesoc into the workroot (the file containing the
      # .eda.yml file), and referenced from vivado_setup_hooks.tcl
      - util/vivado_hook_synth_design_pre.tcl: { file_type: user, copyto: vivado_hook_synth_design_pre.tcl }
      - util/vivado_hook_write_bitstream_pre.tcl: { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
      - util/vivado_hook_opt_design_post.tcl: { file_type: user, copyto: vivado_hook_opt_design_post.tcl }

parameters:
  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
  # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexus.scr.39.vmem
  # XXX: The VMEM file should be added to the sources of the Vivado project to
  # make the Vivado dependency tracking work. However this requires changes to
  # fusesoc first.
  BootRomInitFile:
    datatype: str
    description: Scrambled boot ROM initialization file in 40 bit vmem hex format
    default: "../../../../../../out/matcha/hw/rom_splices/test_rom_fpga_nexus.scr.39.vmem"
    paramtype: vlogparam
  OtpCtrlMemInitFile:
    datatype: str
    description: OTP initialization file in vmem hex format
    default: "../../../../../../out/matcha/hw/rom_splices/otp_img_fpga_nexus.vmem"
    paramtype: vlogparam
  # For value definition, please see ip/prim/rtl/prim_pkg.sv
  PRIM_DEFAULT_IMPL:
    datatype: str
    paramtype: vlogdefine
    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
  AST_BYPASS_CLK:
    datatype: bool
    paramtype: vlogdefine
  IBEX_CUSTOM_PMP_RESET_VALUES:
    datatype: bool
    default: true
    paramtype: vlogdefine
  # New parameter for ISP so the CG can be bypassed.
  FPGA:
    datatype: bool
    default: true
    paramtype: vlogdefine

targets:
  default: &default_target
    filesets:
      - files_rtl_nexus
    toplevel: chip_matcha_nexus
    parameters:
      - IBEX_CUSTOM_PMP_RESET_VALUES
      - AST_BYPASS_CLK=true

  synth:
    default_tool: vivado
    filesets:
      - files_rtl_nexus
      - files_constraints
      - files_tcl
    toplevel: chip_matcha_nexus
    parameters:
      - BootRomInitFile
      - OtpCtrlMemInitFile
      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
      - IBEX_CUSTOM_PMP_RESET_VALUES
      - AST_BYPASS_CLK=true
      - FPGA=true
    tools:
      vivado:
        part: "xcvu13p-fhga2104-2-e" # nexus with XCVU13P-FHGA2104-2-e

  lint:
    <<: *default_target
    default_tool: verilator
    tools:
      verilator:
        mode: lint-only
        verilator_options:
          - "-Wall"