Diversion libs for Sparrow builds
- Libraries which use `select` to pick either HJSON-generated register
headers, or exported ones for the Sparrow ASIC.
- Minor build rule tweaks to have the correct platform transition for
the `asic` build targets.
Change-Id: I23fa7e9f0395fc6d279d016ce1bb2f0b02f1eb58
diff --git a/.bazelrc b/.bazelrc
index 0dea8ef..43d1234 100644
--- a/.bazelrc
+++ b/.bazelrc
@@ -26,6 +26,7 @@
# --config=riscv32
build:riscv32 --platforms=@crt//platforms/riscv32:opentitan
build:kelvin --platforms=//platforms/riscv32:kelvin
+build:sparrow --platforms=@matcha//platforms/riscv32:sparrow
# Shared configuration for clang's source-based coverage instrumentation.
# Bazel seems to support this only partially, thus we have to perform some
diff --git a/hw/top_matcha/BUILD b/hw/top_matcha/BUILD
index add6798..6700398 100644
--- a/hw/top_matcha/BUILD
+++ b/hw/top_matcha/BUILD
@@ -57,3 +57,141 @@
"//hw/top_matcha/ip:all_hjson_files",
],
)
+
+cc_library(
+ name = "alert_handler_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:alert_handler_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha:alert_handler_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "ast_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:ip/ast/data/ast_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha/ip/ast/data",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha/ip/ast/data:ast_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "clkmgr_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:ip/clkmgr/data/autogen/clkmgr_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha/ip/clkmgr/data/autogen",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "pinmux_regs",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:ip/pinmux/data/autogen/pinmux_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha/ip/pinmux/data/autogen",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha/ip/pinmux/data/autogen:pinmux_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "rv_plic_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:rv_plic_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha:rv_plic_regs",
+ ],
+ }),
+)
+
+cc_library(
+ name = "rv_plic_smc_regs_h",
+ hdrs = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow/hw/top_matcha:rv_plic_smc_regs.h",
+ ],
+ "//conditions:default": [],
+ }),
+ includes = select({
+ "//rules:sparrow_platform": [
+ "sparrow/hw/top_matcha",
+ ],
+ "//conditions:default": [],
+ }),
+ deps = select({
+ "//rules:sparrow_platform": [
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha:rv_plic_smc_regs",
+ ],
+ }),
+)
diff --git a/hw/top_matcha/sparrow/BUILD b/hw/top_matcha/sparrow/BUILD
new file mode 100644
index 0000000..114a916
--- /dev/null
+++ b/hw/top_matcha/sparrow/BUILD
@@ -0,0 +1,20 @@
+# Copyright 2024 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:linker.bzl", "ld_library")
+
+package(default_visibility = ["//visibility:public"])
+
+cc_library(
+ name = "top_matcha",
+ srcs = [
+ "//hw/top_matcha/sparrow/hw/top_matcha/sw/autogen:top_matcha.c",
+ ],
+ hdrs = [
+ "//hw/top_matcha/sparrow/hw/top_matcha/sw/autogen:top_matcha.h",
+ "//hw/top_matcha/sparrow/hw/top_matcha/sw/autogen:top_matcha_memory.h",
+ ],
+ includes = ["."],
+)
+
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/BUILD b/hw/top_matcha/sparrow/hw/top_matcha/BUILD
new file mode 100644
index 0000000..3553a05
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/BUILD
@@ -0,0 +1,5 @@
+# Copyright 2024 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+exports_files(glob(["**/*.h"]))
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/alert_handler_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/alert_handler_regs.h
new file mode 100644
index 0000000..c6bf13c
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/alert_handler_regs.h
@@ -0,0 +1,2504 @@
+// Generated register defines for alert_handler
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _ALERT_HANDLER_REG_DEFS_
+#define _ALERT_HANDLER_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of alert channels.
+#define ALERT_HANDLER_PARAM_N_ALERTS 75
+
+// Number of LPGs.
+#define ALERT_HANDLER_PARAM_N_LPG 33
+
+// Width of LPG ID.
+#define ALERT_HANDLER_PARAM_N_LPG_WIDTH 6
+
+// Width of the escalation timer.
+#define ALERT_HANDLER_PARAM_ESC_CNT_DW 32
+
+// Width of the accumulation counter.
+#define ALERT_HANDLER_PARAM_ACCU_CNT_DW 16
+
+// Number of classes
+#define ALERT_HANDLER_PARAM_N_CLASSES 4
+
+// Number of escalation severities
+#define ALERT_HANDLER_PARAM_N_ESC_SEV 4
+
+// Number of escalation phases
+#define ALERT_HANDLER_PARAM_N_PHASES 4
+
+// Number of local alerts
+#define ALERT_HANDLER_PARAM_N_LOC_ALERT 7
+
+// Width of ping counter
+#define ALERT_HANDLER_PARAM_PING_CNT_DW 16
+
+// Width of phase ID
+#define ALERT_HANDLER_PARAM_PHASE_DW 2
+
+// Width of class ID
+#define ALERT_HANDLER_PARAM_CLASS_DW 2
+
+// Local alert ID for alert ping failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL 0
+
+// Local alert ID for escalation ping failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL 1
+
+// Local alert ID for alert integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL 2
+
+// Local alert ID for escalation integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL 3
+
+// Local alert ID for bus integrity failure.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL 4
+
+// Local alert ID for shadow register update error.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR 5
+
+// Local alert ID for shadow register storage error.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR 6
+
+// Last local alert ID.
+#define ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST 6
+
+// Register width
+#define ALERT_HANDLER_PARAM_REG_WIDTH 32
+
+// Common Interrupt Offsets
+#define ALERT_HANDLER_INTR_COMMON_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_COMMON_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_COMMON_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_COMMON_CLASSD_BIT 3
+
+// Interrupt State Register
+#define ALERT_HANDLER_INTR_STATE_REG_OFFSET 0x0
+#define ALERT_HANDLER_INTR_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_STATE_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_STATE_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_STATE_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_STATE_CLASSD_BIT 3
+
+// Interrupt Enable Register
+#define ALERT_HANDLER_INTR_ENABLE_REG_OFFSET 0x4
+#define ALERT_HANDLER_INTR_ENABLE_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT 3
+
+// Interrupt Test Register
+#define ALERT_HANDLER_INTR_TEST_REG_OFFSET 0x8
+#define ALERT_HANDLER_INTR_TEST_REG_RESVAL 0x0
+#define ALERT_HANDLER_INTR_TEST_CLASSA_BIT 0
+#define ALERT_HANDLER_INTR_TEST_CLASSB_BIT 1
+#define ALERT_HANDLER_INTR_TEST_CLASSC_BIT 2
+#define ALERT_HANDLER_INTR_TEST_CLASSD_BIT 3
+
+// Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and
+// !!PING_TIMER_EN_SHADOWED.
+#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET 0xc
+#define ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT 0
+
+// Ping timeout cycle count.
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x10
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x100
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK, .index = ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET })
+
+// Ping timer enable.
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET 0x14
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT 0
+
+// Register write enable for alert enable bits. (common parameters)
+#define ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT 75
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET 0x18
+#define ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET 0x1c
+#define ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET 0x20
+#define ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET 0x24
+#define ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET 0x28
+#define ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET 0x2c
+#define ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET 0x30
+#define ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET 0x34
+#define ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET 0x38
+#define ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET 0x3c
+#define ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET 0x40
+#define ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET 0x44
+#define ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET 0x48
+#define ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET 0x4c
+#define ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET 0x50
+#define ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET 0x54
+#define ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET 0x58
+#define ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET 0x5c
+#define ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET 0x60
+#define ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET 0x64
+#define ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET 0x68
+#define ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET 0x6c
+#define ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET 0x70
+#define ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET 0x74
+#define ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET 0x78
+#define ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET 0x7c
+#define ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET 0x80
+#define ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET 0x84
+#define ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET 0x88
+#define ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET 0x8c
+#define ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET 0x90
+#define ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET 0x94
+#define ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET 0x98
+#define ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET 0x9c
+#define ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET 0xa0
+#define ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET 0xa4
+#define ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET 0xa8
+#define ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET 0xac
+#define ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET 0xb0
+#define ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET 0xb4
+#define ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET 0xb8
+#define ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET 0xbc
+#define ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET 0xc0
+#define ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET 0xc4
+#define ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET 0xc8
+#define ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET 0xcc
+#define ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET 0xd0
+#define ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET 0xd4
+#define ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET 0xd8
+#define ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET 0xdc
+#define ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET 0xe0
+#define ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET 0xe4
+#define ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET 0xe8
+#define ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET 0xec
+#define ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET 0xf0
+#define ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET 0xf4
+#define ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET 0xf8
+#define ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET 0xfc
+#define ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET 0x100
+#define ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET 0x104
+#define ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET 0x108
+#define ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET 0x10c
+#define ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET 0x110
+#define ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET 0x114
+#define ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET 0x118
+#define ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_65_REG_OFFSET 0x11c
+#define ALERT_HANDLER_ALERT_REGWEN_65_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_65_EN_65_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_66_REG_OFFSET 0x120
+#define ALERT_HANDLER_ALERT_REGWEN_66_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_66_EN_66_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_67_REG_OFFSET 0x124
+#define ALERT_HANDLER_ALERT_REGWEN_67_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_67_EN_67_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_68_REG_OFFSET 0x128
+#define ALERT_HANDLER_ALERT_REGWEN_68_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_68_EN_68_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_69_REG_OFFSET 0x12c
+#define ALERT_HANDLER_ALERT_REGWEN_69_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_69_EN_69_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_70_REG_OFFSET 0x130
+#define ALERT_HANDLER_ALERT_REGWEN_70_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_70_EN_70_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_71_REG_OFFSET 0x134
+#define ALERT_HANDLER_ALERT_REGWEN_71_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_71_EN_71_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_72_REG_OFFSET 0x138
+#define ALERT_HANDLER_ALERT_REGWEN_72_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_72_EN_72_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_73_REG_OFFSET 0x13c
+#define ALERT_HANDLER_ALERT_REGWEN_73_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_73_EN_73_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_ALERT_REGWEN_74_REG_OFFSET 0x140
+#define ALERT_HANDLER_ALERT_REGWEN_74_REG_RESVAL 0x1
+#define ALERT_HANDLER_ALERT_REGWEN_74_EN_74_BIT 0
+
+// Enable register for alerts. (common parameters)
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT 75
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET 0x144
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET 0x148
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET 0x14c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET 0x150
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET 0x154
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET 0x158
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET 0x15c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET 0x160
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET 0x164
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET 0x168
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET 0x16c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET 0x170
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET 0x174
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET 0x178
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET 0x17c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET 0x180
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET 0x184
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET 0x188
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET 0x18c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET 0x190
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET 0x194
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET 0x198
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET 0x19c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET 0x1a0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET 0x1a4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET 0x1a8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET 0x1ac
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET 0x1b0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET 0x1b4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET 0x1b8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET 0x1bc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET 0x1c0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET 0x1c4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET 0x1c8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET 0x1cc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET 0x1d0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET 0x1d4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET 0x1d8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET 0x1dc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET 0x1e0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET 0x1e4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET 0x1e8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET 0x1ec
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET 0x1f0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET 0x1f4
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET 0x1f8
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET 0x1fc
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET 0x200
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET 0x204
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET 0x208
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET 0x20c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET 0x210
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET 0x214
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET 0x218
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET 0x21c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET 0x220
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET 0x224
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET 0x228
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET 0x22c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET 0x230
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET 0x234
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET 0x238
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET 0x23c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET 0x240
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET 0x244
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_OFFSET 0x248
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_65_EN_A_65_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_OFFSET 0x24c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_66_EN_A_66_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_OFFSET 0x250
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_67_EN_A_67_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_OFFSET 0x254
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_68_EN_A_68_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_OFFSET 0x258
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_69_EN_A_69_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_OFFSET 0x25c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_70_EN_A_70_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_OFFSET 0x260
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_71_EN_A_71_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_OFFSET 0x264
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_72_EN_A_72_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_OFFSET 0x268
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_73_EN_A_73_BIT 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_OFFSET 0x26c
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_EN_SHADOWED_74_EN_A_74_BIT 0
+
+// Class assignment of alerts. (common parameters)
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH 2
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 75
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x270
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET })
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB 0x1
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC 0x2
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD 0x3
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x274
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x278
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x27c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x280
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x284
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x288
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET 0x28c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET 0x290
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET 0x294
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET 0x298
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET 0x29c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET 0x2a0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET 0x2a4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET 0x2a8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET 0x2ac
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET 0x2b0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET 0x2b4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET 0x2b8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET 0x2bc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET 0x2c0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET 0x2c4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET 0x2c8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET 0x2cc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET 0x2d0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET 0x2d4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET 0x2d8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET 0x2dc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET 0x2e0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET 0x2e4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET 0x2e8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET 0x2ec
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET 0x2f0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET 0x2f4
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET 0x2f8
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET 0x2fc
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET 0x300
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET 0x304
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET 0x308
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET 0x30c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET 0x310
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET 0x314
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET 0x318
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET 0x31c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET 0x320
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET 0x324
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET 0x328
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET 0x32c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET 0x330
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET 0x334
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET 0x338
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET 0x33c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET 0x340
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET 0x344
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET 0x348
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET 0x34c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET 0x350
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET 0x354
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET 0x358
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET 0x35c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET 0x360
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET 0x364
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET 0x368
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET 0x36c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET 0x370
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_OFFSET 0x374
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_CLASS_A_65_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_OFFSET 0x378
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_CLASS_A_66_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_OFFSET 0x37c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_CLASS_A_67_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_OFFSET 0x380
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_CLASS_A_68_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_OFFSET 0x384
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_CLASS_A_69_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_OFFSET 0x388
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_CLASS_A_70_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_OFFSET 0x38c
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_CLASS_A_71_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_OFFSET 0x390
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_CLASS_A_72_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_OFFSET 0x394
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_CLASS_A_73_OFFSET })
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_OFFSET 0x398
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_MASK, .index = ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_CLASS_A_74_OFFSET })
+
+// Alert Cause Register (common parameters)
+#define ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH 1
+#define ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT 75
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET 0x39c
+#define ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET 0x3a0
+#define ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET 0x3a4
+#define ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET 0x3a8
+#define ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET 0x3ac
+#define ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET 0x3b0
+#define ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET 0x3b4
+#define ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET 0x3b8
+#define ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET 0x3bc
+#define ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET 0x3c0
+#define ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET 0x3c4
+#define ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET 0x3c8
+#define ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET 0x3cc
+#define ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET 0x3d0
+#define ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET 0x3d4
+#define ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET 0x3d8
+#define ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET 0x3dc
+#define ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET 0x3e0
+#define ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET 0x3e4
+#define ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET 0x3e8
+#define ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET 0x3ec
+#define ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET 0x3f0
+#define ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET 0x3f4
+#define ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET 0x3f8
+#define ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET 0x3fc
+#define ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET 0x400
+#define ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET 0x404
+#define ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET 0x408
+#define ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET 0x40c
+#define ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET 0x410
+#define ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET 0x414
+#define ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET 0x418
+#define ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET 0x41c
+#define ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET 0x420
+#define ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET 0x424
+#define ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET 0x428
+#define ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET 0x42c
+#define ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET 0x430
+#define ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET 0x434
+#define ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET 0x438
+#define ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET 0x43c
+#define ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET 0x440
+#define ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET 0x444
+#define ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET 0x448
+#define ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET 0x44c
+#define ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET 0x450
+#define ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET 0x454
+#define ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET 0x458
+#define ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET 0x45c
+#define ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET 0x460
+#define ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET 0x464
+#define ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET 0x468
+#define ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET 0x46c
+#define ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET 0x470
+#define ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET 0x474
+#define ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET 0x478
+#define ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET 0x47c
+#define ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET 0x480
+#define ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET 0x484
+#define ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET 0x488
+#define ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET 0x48c
+#define ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET 0x490
+#define ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET 0x494
+#define ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET 0x498
+#define ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET 0x49c
+#define ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_65_REG_OFFSET 0x4a0
+#define ALERT_HANDLER_ALERT_CAUSE_65_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_65_A_65_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_66_REG_OFFSET 0x4a4
+#define ALERT_HANDLER_ALERT_CAUSE_66_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_66_A_66_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_67_REG_OFFSET 0x4a8
+#define ALERT_HANDLER_ALERT_CAUSE_67_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_67_A_67_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_68_REG_OFFSET 0x4ac
+#define ALERT_HANDLER_ALERT_CAUSE_68_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_68_A_68_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_69_REG_OFFSET 0x4b0
+#define ALERT_HANDLER_ALERT_CAUSE_69_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_69_A_69_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_70_REG_OFFSET 0x4b4
+#define ALERT_HANDLER_ALERT_CAUSE_70_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_70_A_70_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_71_REG_OFFSET 0x4b8
+#define ALERT_HANDLER_ALERT_CAUSE_71_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_71_A_71_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_72_REG_OFFSET 0x4bc
+#define ALERT_HANDLER_ALERT_CAUSE_72_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_72_A_72_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_73_REG_OFFSET 0x4c0
+#define ALERT_HANDLER_ALERT_CAUSE_73_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_73_A_73_BIT 0
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE_74_REG_OFFSET 0x4c4
+#define ALERT_HANDLER_ALERT_CAUSE_74_REG_RESVAL 0x0
+#define ALERT_HANDLER_ALERT_CAUSE_74_A_74_BIT 0
+
+// Register write enable for alert enable bits. (common parameters)
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT 7
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET 0x4c8
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET 0x4cc
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET 0x4d0
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET 0x4d4
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET 0x4d8
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET 0x4dc
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for alert enable bits.
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET 0x4e0
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL 0x1
+#define ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT 7
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET 0x4e4
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET 0x4e8
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET 0x4ec
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET 0x4f0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET 0x4f4
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET 0x4f8
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT 0
+
+// Enable register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET 0x4fc
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT 0
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH 2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT 7
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET 0x500
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET })
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB 0x1
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC 0x2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD 0x3
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET 0x504
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET 0x508
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET 0x50c
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET 0x510
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET 0x514
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET })
+
+// Class assignment of the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET 0x518
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK, .index = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET })
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH 1
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT 7
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET 0x51c
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET 0x520
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET 0x524
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET 0x528
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET 0x52c
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET 0x530
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT 0
+
+// Alert Cause Register for the local alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET 0x534
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL 0x0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT 0
+
+// Lock bit for Class A configuration.
+#define ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET 0x538
+#define ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT 0
+
+// Escalation control register for alert Class A. Can not be modified if
+// !!CLASSA_REGWEN is false.
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET 0x53c
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class A alerts.
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET 0x540
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class A.
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET 0x544
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class A. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET 0x548
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class A.
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x54c
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x550
+#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class A.
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x554
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET 0x558
+#define ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET 0x55c
+#define ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET 0x560
+#define ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class A.
+#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET 0x564
+#define ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class A.
+#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET 0x568
+#define ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+#define ALERT_HANDLER_CLASSA_STATE_REG_OFFSET 0x56c
+#define ALERT_HANDLER_CLASSA_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK, .index = ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class B configuration.
+#define ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET 0x570
+#define ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT 0
+
+// Escalation control register for alert Class B. Can not be modified if
+// !!CLASSB_REGWEN is false.
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET 0x574
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class B alerts.
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET 0x578
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class B.
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET 0x57c
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class B. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET 0x580
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class B.
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x584
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x588
+#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class B.
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x58c
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET 0x590
+#define ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET 0x594
+#define ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET 0x598
+#define ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class B.
+#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET 0x59c
+#define ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class B.
+#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET 0x5a0
+#define ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+#define ALERT_HANDLER_CLASSB_STATE_REG_OFFSET 0x5a4
+#define ALERT_HANDLER_CLASSB_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK, .index = ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class C configuration.
+#define ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET 0x5a8
+#define ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT 0
+
+// Escalation control register for alert Class C. Can not be modified if
+// !!CLASSC_REGWEN is false.
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET 0x5ac
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class C alerts.
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET 0x5b0
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class C.
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET 0x5b4
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class C. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET 0x5b8
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class C.
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x5bc
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x5c0
+#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class C.
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x5c4
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET 0x5c8
+#define ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET 0x5cc
+#define ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET 0x5d0
+#define ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class C.
+#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET 0x5d4
+#define ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class C.
+#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET 0x5d8
+#define ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+#define ALERT_HANDLER_CLASSC_STATE_REG_OFFSET 0x5dc
+#define ALERT_HANDLER_CLASSC_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK, .index = ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3 0x7
+
+// Lock bit for Class D configuration.
+#define ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET 0x5e0
+#define ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT 0
+
+// Escalation control register for alert Class D. Can not be modified if
+// !!CLASSD_REGWEN is false.
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET 0x5e4
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL 0x393c
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT 0
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT 1
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT 2
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT 3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT 4
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT 5
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET })
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET 12
+#define ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK, .index = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET })
+
+// Clear enable for escalation protocol of Class D alerts.
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET 0x5e8
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL 0x1
+#define ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT 0
+
+// Clear for escalation protocol of Class D.
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET 0x5ec
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT 0
+
+// Current accumulation value for alert Class D. Software can clear this
+// register
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET 0x5f0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET 0
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET })
+
+// Accumulation threshold value for alert Class D.
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET 0x5f4
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK \
+ 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET })
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET 0x5f8
+#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Crashdump trigger configuration for Class D.
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET 0x5fc
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK \
+ 0x3
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET \
+ 0
+#define ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK, .index = ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET })
+
+// Duration of escalation phase 0 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET 0x600
+#define ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 1 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET 0x604
+#define ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 2 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET 0x608
+#define ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Duration of escalation phase 3 for Class D.
+#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET 0x60c
+#define ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL 0x0
+
+// Escalation counter in cycles for Class D.
+#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET 0x610
+#define ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL 0x0
+
+// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+#define ALERT_HANDLER_CLASSD_STATE_REG_OFFSET 0x614
+#define ALERT_HANDLER_CLASSD_STATE_REG_RESVAL 0x0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_FIELD \
+ ((bitfield_field32_t) { .mask = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK, .index = ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET })
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE 0x0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT 0x1
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR 0x2
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL 0x3
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0 0x4
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1 0x5
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2 0x6
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3 0x7
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _ALERT_HANDLER_REG_DEFS_
+// End generated register defines for alert_handler
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/ip/ast/data/ast_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/ip/ast/data/ast_regs.h
new file mode 100644
index 0000000..1428f3b
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/ip/ast/data/ast_regs.h
@@ -0,0 +1,458 @@
+// Generated register defines for ast
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _AST_REG_DEFS_
+#define _AST_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of registers in the Array-B
+#define AST_PARAM_NUM_REGS_B 5
+
+// Number of USB valid beacon pulses for clock to re-calibrate
+#define AST_PARAM_NUM_USB_BEACON_PULSES 8
+
+// Register width
+#define AST_PARAM_REG_WIDTH 32
+
+// AST Register 0 for OTP/ROM Write Testing
+#define AST_REGA0_REG_OFFSET 0x0
+#define AST_REGA0_REG_RESVAL 0x0
+
+// AST 1 Register for OTP/ROM Write Testing
+#define AST_REGA1_REG_OFFSET 0x4
+#define AST_REGA1_REG_RESVAL 0x1
+
+// AST 2 Register for OTP/ROM Write Testing
+#define AST_REGA2_REG_OFFSET 0x8
+#define AST_REGA2_REG_RESVAL 0x2
+
+// AST 3 Register for OTP/ROM Write Testing
+#define AST_REGA3_REG_OFFSET 0xc
+#define AST_REGA3_REG_RESVAL 0x3
+
+// AST 4 Register for OTP/ROM Write Testing
+#define AST_REGA4_REG_OFFSET 0x10
+#define AST_REGA4_REG_RESVAL 0x4
+
+// AST 5 Register for OTP/ROM Write Testing
+#define AST_REGA5_REG_OFFSET 0x14
+#define AST_REGA5_REG_RESVAL 0x5
+
+// AST 6 Register for OTP/ROM Write Testing
+#define AST_REGA6_REG_OFFSET 0x18
+#define AST_REGA6_REG_RESVAL 0x6
+
+// AST 7 Register for OTP/ROM Write Testing
+#define AST_REGA7_REG_OFFSET 0x1c
+#define AST_REGA7_REG_RESVAL 0x7
+
+// AST 8 Register for OTP/ROM Write Testing
+#define AST_REGA8_REG_OFFSET 0x20
+#define AST_REGA8_REG_RESVAL 0x8
+
+// AST 9 Register for OTP/ROM Write Testing
+#define AST_REGA9_REG_OFFSET 0x24
+#define AST_REGA9_REG_RESVAL 0x9
+
+// AST 10 Register for OTP/ROM Write Testing
+#define AST_REGA10_REG_OFFSET 0x28
+#define AST_REGA10_REG_RESVAL 0xa
+
+// AST 11 Register for OTP/ROM Write Testing
+#define AST_REGA11_REG_OFFSET 0x2c
+#define AST_REGA11_REG_RESVAL 0xb
+
+// AST 13 Register for OTP/ROM Write Testing
+#define AST_REGA12_REG_OFFSET 0x30
+#define AST_REGA12_REG_RESVAL 0xc
+
+// AST 13 Register for OTP/ROM Write Testing
+#define AST_REGA13_REG_OFFSET 0x34
+#define AST_REGA13_REG_RESVAL 0xd
+
+// AST 14 Register for OTP/ROM Write Testing
+#define AST_REGA14_REG_OFFSET 0x38
+#define AST_REGA14_REG_RESVAL 0xe
+
+// AST 15 Register for OTP/ROM Write Testing
+#define AST_REGA15_REG_OFFSET 0x3c
+#define AST_REGA15_REG_RESVAL 0xf
+
+// AST 16 Register for OTP/ROM Write Testing
+#define AST_REGA16_REG_OFFSET 0x40
+#define AST_REGA16_REG_RESVAL 0x10
+
+// AST 17 Register for OTP/ROM Write Testing
+#define AST_REGA17_REG_OFFSET 0x44
+#define AST_REGA17_REG_RESVAL 0x11
+
+// AST 18 Register for OTP/ROM Write Testing
+#define AST_REGA18_REG_OFFSET 0x48
+#define AST_REGA18_REG_RESVAL 0x12
+
+// AST 19 Register for OTP/ROM Write Testing
+#define AST_REGA19_REG_OFFSET 0x4c
+#define AST_REGA19_REG_RESVAL 0x13
+
+// AST 20 Register for OTP/ROM Write Testing
+#define AST_REGA20_REG_OFFSET 0x50
+#define AST_REGA20_REG_RESVAL 0x14
+
+// AST 21 Register for OTP/ROM Write Testing
+#define AST_REGA21_REG_OFFSET 0x54
+#define AST_REGA21_REG_RESVAL 0x15
+
+// AST 22 Register for OTP/ROM Write Testing
+#define AST_REGA22_REG_OFFSET 0x58
+#define AST_REGA22_REG_RESVAL 0x16
+
+// AST 23 Register for OTP/ROM Write Testing
+#define AST_REGA23_REG_OFFSET 0x5c
+#define AST_REGA23_REG_RESVAL 0x17
+
+// AST 24 Register for OTP/ROM Write Testing
+#define AST_REGA24_REG_OFFSET 0x60
+#define AST_REGA24_REG_RESVAL 0x18
+
+// AST 25 Register for OTP/ROM Write Testing
+#define AST_REGA25_REG_OFFSET 0x64
+#define AST_REGA25_REG_RESVAL 0x19
+
+// AST 26 Register for OTP/ROM Write Testing
+#define AST_REGA26_REG_OFFSET 0x68
+#define AST_REGA26_REG_RESVAL 0x1a
+
+// AST 27 Register for OTP/ROM Write Testing
+#define AST_REGA27_REG_OFFSET 0x6c
+#define AST_REGA27_REG_RESVAL 0x1b
+
+// AST 28 Register for OTP/ROM Write Testing
+#define AST_REGA28_REG_OFFSET 0x70
+#define AST_REGA28_REG_RESVAL 0x1c
+
+// AST 29 Register for OTP/ROM Write Testing
+#define AST_REGA29_REG_OFFSET 0x74
+#define AST_REGA29_REG_RESVAL 0x1d
+
+// AST 30 Register for OTP/ROM Write Testing
+#define AST_REGA30_REG_OFFSET 0x78
+#define AST_REGA30_REG_RESVAL 0x1e
+
+// AST 31 Register for OTP/ROM Write Testing
+#define AST_REGA31_REG_OFFSET 0x7c
+#define AST_REGA31_REG_RESVAL 0x1f
+
+// AST 32 Register for OTP/ROM Write Testing
+#define AST_REGA32_REG_OFFSET 0x80
+#define AST_REGA32_REG_RESVAL 0x20
+
+// AST 33 Register for OTP/ROM Write Testing
+#define AST_REGA33_REG_OFFSET 0x84
+#define AST_REGA33_REG_RESVAL 0x21
+
+// AST 34 Register for OTP/ROM Write Testing
+#define AST_REGA34_REG_OFFSET 0x88
+#define AST_REGA34_REG_RESVAL 0x22
+
+// AST 35 Register for OTP/ROM Write Testing
+#define AST_REGA35_REG_OFFSET 0x8c
+#define AST_REGA35_REG_RESVAL 0x23
+
+// AST 36 Register for OTP/ROM Write Testing
+#define AST_REGA36_REG_OFFSET 0x90
+#define AST_REGA36_REG_RESVAL 0x24
+
+// AST 37 Register for OTP/ROM Write Testing
+#define AST_REGA37_REG_OFFSET 0x94
+#define AST_REGA37_REG_RESVAL 0x25
+
+// AST Last Register for OTP/ROM Write Testing
+#define AST_REGAL_REG_OFFSET 0x98
+#define AST_REGAL_REG_RESVAL 0x26
+
+// PLL0 register contrrol part0
+#define AST_PLL0_CTRL0_REG_OFFSET 0x9c
+#define AST_PLL0_CTRL0_REG_RESVAL 0xc0c00
+#define AST_PLL0_CTRL0_DM_MASK 0x3f
+#define AST_PLL0_CTRL0_DM_OFFSET 0
+#define AST_PLL0_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DM_MASK, .index = AST_PLL0_CTRL0_DM_OFFSET })
+#define AST_PLL0_CTRL0_DN_MASK 0x7ff
+#define AST_PLL0_CTRL0_DN_OFFSET 6
+#define AST_PLL0_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DN_MASK, .index = AST_PLL0_CTRL0_DN_OFFSET })
+#define AST_PLL0_CTRL0_DP_MASK 0x7
+#define AST_PLL0_CTRL0_DP_OFFSET 17
+#define AST_PLL0_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_DP_MASK, .index = AST_PLL0_CTRL0_DP_OFFSET })
+#define AST_PLL0_CTRL0_PD_BIT 20
+#define AST_PLL0_CTRL0_PDP_BIT 21
+#define AST_PLL0_CTRL0_RESETN_BIT 22
+#define AST_PLL0_CTRL0_MODE_MASK 0x3
+#define AST_PLL0_CTRL0_MODE_OFFSET 23
+#define AST_PLL0_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_MODE_MASK, .index = AST_PLL0_CTRL0_MODE_OFFSET })
+#define AST_PLL0_CTRL0_BYPASS_BIT 25
+#define AST_PLL0_CTRL0_TEST_EN_BIT 26
+#define AST_PLL0_CTRL0_RSV_MASK 0x1f
+#define AST_PLL0_CTRL0_RSV_OFFSET 27
+#define AST_PLL0_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL0_RSV_MASK, .index = AST_PLL0_CTRL0_RSV_OFFSET })
+
+// PLL0 CTRL1 register control part1
+#define AST_PLL0_CTRL1_REG_OFFSET 0xa0
+#define AST_PLL0_CTRL1_REG_RESVAL 0x0
+#define AST_PLL0_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL0_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL0_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL1_SSRATE_MASK, .index = AST_PLL0_CTRL1_SSRATE_OFFSET })
+#define AST_PLL0_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL0_CTRL1_RSV_OFFSET 11
+#define AST_PLL0_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL1_RSV_MASK, .index = AST_PLL0_CTRL1_RSV_OFFSET })
+
+// PLL0 register control part2
+#define AST_PLL0_CTRL2_REG_OFFSET 0xa4
+#define AST_PLL0_CTRL2_REG_RESVAL 0x0
+#define AST_PLL0_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL0_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL0_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL2_SLOPE_MASK, .index = AST_PLL0_CTRL2_SLOPE_OFFSET })
+#define AST_PLL0_CTRL2_RSV_MASK 0xff
+#define AST_PLL0_CTRL2_RSV_OFFSET 24
+#define AST_PLL0_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL2_RSV_MASK, .index = AST_PLL0_CTRL2_RSV_OFFSET })
+
+// PLL0 register control part3
+#define AST_PLL0_CTRL3_REG_OFFSET 0xa8
+#define AST_PLL0_CTRL3_REG_RESVAL 0x0
+#define AST_PLL0_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL0_CTRL3_FRAC_OFFSET 0
+#define AST_PLL0_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL3_FRAC_MASK, .index = AST_PLL0_CTRL3_FRAC_OFFSET })
+#define AST_PLL0_CTRL3_RSV_MASK 0xff
+#define AST_PLL0_CTRL3_RSV_OFFSET 24
+#define AST_PLL0_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL0_CTRL3_RSV_MASK, .index = AST_PLL0_CTRL3_RSV_OFFSET })
+
+// PLL1 register control part0
+#define AST_PLL1_CTRL0_REG_OFFSET 0xac
+#define AST_PLL1_CTRL0_REG_RESVAL 0xc1f42
+#define AST_PLL1_CTRL0_DM_MASK 0x3f
+#define AST_PLL1_CTRL0_DM_OFFSET 0
+#define AST_PLL1_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DM_MASK, .index = AST_PLL1_CTRL0_DM_OFFSET })
+#define AST_PLL1_CTRL0_DN_MASK 0x7ff
+#define AST_PLL1_CTRL0_DN_OFFSET 6
+#define AST_PLL1_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DN_MASK, .index = AST_PLL1_CTRL0_DN_OFFSET })
+#define AST_PLL1_CTRL0_DP_MASK 0x7
+#define AST_PLL1_CTRL0_DP_OFFSET 17
+#define AST_PLL1_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_DP_MASK, .index = AST_PLL1_CTRL0_DP_OFFSET })
+#define AST_PLL1_CTRL0_PD_BIT 20
+#define AST_PLL1_CTRL0_PDP_BIT 21
+#define AST_PLL1_CTRL0_RESETN_BIT 22
+#define AST_PLL1_CTRL0_MODE_MASK 0x3
+#define AST_PLL1_CTRL0_MODE_OFFSET 23
+#define AST_PLL1_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_MODE_MASK, .index = AST_PLL1_CTRL0_MODE_OFFSET })
+#define AST_PLL1_CTRL0_BYPASS_BIT 25
+#define AST_PLL1_CTRL0_TEST_EN_BIT 26
+#define AST_PLL1_CTRL0_RSV_MASK 0x1f
+#define AST_PLL1_CTRL0_RSV_OFFSET 27
+#define AST_PLL1_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL0_RSV_MASK, .index = AST_PLL1_CTRL0_RSV_OFFSET })
+
+// PLL1 register control part1
+#define AST_PLL1_CTRL1_REG_OFFSET 0xb0
+#define AST_PLL1_CTRL1_REG_RESVAL 0x0
+#define AST_PLL1_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL1_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL1_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL1_SSRATE_MASK, .index = AST_PLL1_CTRL1_SSRATE_OFFSET })
+#define AST_PLL1_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL1_CTRL1_RSV_OFFSET 11
+#define AST_PLL1_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL1_RSV_MASK, .index = AST_PLL1_CTRL1_RSV_OFFSET })
+
+// PLL1 register control part2
+#define AST_PLL1_CTRL2_REG_OFFSET 0xb4
+#define AST_PLL1_CTRL2_REG_RESVAL 0x0
+#define AST_PLL1_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL1_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL1_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL2_SLOPE_MASK, .index = AST_PLL1_CTRL2_SLOPE_OFFSET })
+#define AST_PLL1_CTRL2_RSV_MASK 0xff
+#define AST_PLL1_CTRL2_RSV_OFFSET 24
+#define AST_PLL1_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL2_RSV_MASK, .index = AST_PLL1_CTRL2_RSV_OFFSET })
+
+// PLL1 register control part3
+#define AST_PLL1_CTRL3_REG_OFFSET 0xb8
+#define AST_PLL1_CTRL3_REG_RESVAL 0x0
+#define AST_PLL1_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL1_CTRL3_FRAC_OFFSET 0
+#define AST_PLL1_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL3_FRAC_MASK, .index = AST_PLL1_CTRL3_FRAC_OFFSET })
+#define AST_PLL1_CTRL3_RSV_MASK 0xff
+#define AST_PLL1_CTRL3_RSV_OFFSET 24
+#define AST_PLL1_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL1_CTRL3_RSV_MASK, .index = AST_PLL1_CTRL3_RSV_OFFSET })
+
+// PLL2 register control part0
+#define AST_PLL2_CTRL0_REG_OFFSET 0xbc
+#define AST_PLL2_CTRL0_REG_RESVAL 0x8e08c0
+#define AST_PLL2_CTRL0_DM_MASK 0x3f
+#define AST_PLL2_CTRL0_DM_OFFSET 0
+#define AST_PLL2_CTRL0_DM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DM_MASK, .index = AST_PLL2_CTRL0_DM_OFFSET })
+#define AST_PLL2_CTRL0_DN_MASK 0x7ff
+#define AST_PLL2_CTRL0_DN_OFFSET 6
+#define AST_PLL2_CTRL0_DN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DN_MASK, .index = AST_PLL2_CTRL0_DN_OFFSET })
+#define AST_PLL2_CTRL0_DP_MASK 0x7
+#define AST_PLL2_CTRL0_DP_OFFSET 17
+#define AST_PLL2_CTRL0_DP_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_DP_MASK, .index = AST_PLL2_CTRL0_DP_OFFSET })
+#define AST_PLL2_CTRL0_PD_BIT 20
+#define AST_PLL2_CTRL0_PDP_BIT 21
+#define AST_PLL2_CTRL0_RESETN_BIT 22
+#define AST_PLL2_CTRL0_MODE_MASK 0x3
+#define AST_PLL2_CTRL0_MODE_OFFSET 23
+#define AST_PLL2_CTRL0_MODE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_MODE_MASK, .index = AST_PLL2_CTRL0_MODE_OFFSET })
+#define AST_PLL2_CTRL0_BYPASS_BIT 25
+#define AST_PLL2_CTRL0_TEST_EN_BIT 26
+#define AST_PLL2_CTRL0_RSV_MASK 0x1f
+#define AST_PLL2_CTRL0_RSV_OFFSET 27
+#define AST_PLL2_CTRL0_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL0_RSV_MASK, .index = AST_PLL2_CTRL0_RSV_OFFSET })
+
+// PLL2 register control part1
+#define AST_PLL2_CTRL1_REG_OFFSET 0xc0
+#define AST_PLL2_CTRL1_REG_RESVAL 0x0
+#define AST_PLL2_CTRL1_SSRATE_MASK 0x7ff
+#define AST_PLL2_CTRL1_SSRATE_OFFSET 0
+#define AST_PLL2_CTRL1_SSRATE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL1_SSRATE_MASK, .index = AST_PLL2_CTRL1_SSRATE_OFFSET })
+#define AST_PLL2_CTRL1_RSV_MASK 0x1fffff
+#define AST_PLL2_CTRL1_RSV_OFFSET 11
+#define AST_PLL2_CTRL1_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL1_RSV_MASK, .index = AST_PLL2_CTRL1_RSV_OFFSET })
+
+// PLL2 register control part2
+#define AST_PLL2_CTRL2_REG_OFFSET 0xc4
+#define AST_PLL2_CTRL2_REG_RESVAL 0x0
+#define AST_PLL2_CTRL2_SLOPE_MASK 0xffffff
+#define AST_PLL2_CTRL2_SLOPE_OFFSET 0
+#define AST_PLL2_CTRL2_SLOPE_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL2_SLOPE_MASK, .index = AST_PLL2_CTRL2_SLOPE_OFFSET })
+#define AST_PLL2_CTRL2_RSV_MASK 0xff
+#define AST_PLL2_CTRL2_RSV_OFFSET 24
+#define AST_PLL2_CTRL2_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL2_RSV_MASK, .index = AST_PLL2_CTRL2_RSV_OFFSET })
+
+// PLL2 register control part3
+#define AST_PLL2_CTRL3_REG_OFFSET 0xc8
+#define AST_PLL2_CTRL3_REG_RESVAL 0xd70a3e
+#define AST_PLL2_CTRL3_FRAC_MASK 0xffffff
+#define AST_PLL2_CTRL3_FRAC_OFFSET 0
+#define AST_PLL2_CTRL3_FRAC_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL3_FRAC_MASK, .index = AST_PLL2_CTRL3_FRAC_OFFSET })
+#define AST_PLL2_CTRL3_RSV_MASK 0xff
+#define AST_PLL2_CTRL3_RSV_OFFSET 24
+#define AST_PLL2_CTRL3_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_PLL2_CTRL3_RSV_MASK, .index = AST_PLL2_CTRL3_RSV_OFFSET })
+
+// SARADC register control
+#define AST_SARADC_CTRL_REG_OFFSET 0xcc
+#define AST_SARADC_CTRL_REG_RESVAL 0x1
+#define AST_SARADC_CTRL_SOC_BIT 0
+#define AST_SARADC_CTRL_PD_ADC_BIT 1
+#define AST_SARADC_CTRL_SEL_DIFF_BIT 2
+#define AST_SARADC_CTRL_SEL_SPEED_BIT 3
+#define AST_SARADC_CTRL_SEL_CHA_MASK 0x7
+#define AST_SARADC_CTRL_SEL_CHA_OFFSET 4
+#define AST_SARADC_CTRL_SEL_CHA_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_CTRL_SEL_CHA_MASK, .index = AST_SARADC_CTRL_SEL_CHA_OFFSET })
+#define AST_SARADC_CTRL_EN_VCM_BIT 7
+#define AST_SARADC_CTRL_EN_CAL_BIT 8
+#define AST_SARADC_CTRL_SEL_CMP_BIT 9
+#define AST_SARADC_CTRL_RSV_MASK 0x3fffff
+#define AST_SARADC_CTRL_RSV_OFFSET 10
+#define AST_SARADC_CTRL_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_CTRL_RSV_MASK, .index = AST_SARADC_CTRL_RSV_OFFSET })
+
+// SARADC register control
+#define AST_SARADC_DATA_REG_OFFSET 0xd0
+#define AST_SARADC_DATA_REG_RESVAL 0x0
+#define AST_SARADC_DATA_CAL_DONE_BIT 0
+#define AST_SARADC_DATA_EOC_BIT 1
+#define AST_SARADC_DATA_ADC_OUTPUT_MASK 0xfff
+#define AST_SARADC_DATA_ADC_OUTPUT_OFFSET 2
+#define AST_SARADC_DATA_ADC_OUTPUT_FIELD \
+ ((bitfield_field32_t) { .mask = AST_SARADC_DATA_ADC_OUTPUT_MASK, .index = AST_SARADC_DATA_ADC_OUTPUT_OFFSET })
+
+// VT_SENSOR register control
+#define AST_VT_SENSOR_CTRL_REG_OFFSET 0xd4
+#define AST_VT_SENSOR_CTRL_REG_RESVAL 0xc
+#define AST_VT_SENSOR_CTRL_PD_BIT 0
+#define AST_VT_SENSOR_CTRL_TSTCON_BIT 1
+#define AST_VT_SENSOR_CTRL_TSEL_BIT 2
+#define AST_VT_SENSOR_CTRL_VSEL_BIT 3
+#define AST_VT_SENSOR_CTRL_VTRIM_MASK 0xf
+#define AST_VT_SENSOR_CTRL_VTRIM_OFFSET 4
+#define AST_VT_SENSOR_CTRL_VTRIM_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_CTRL_VTRIM_MASK, .index = AST_VT_SENSOR_CTRL_VTRIM_OFFSET })
+#define AST_VT_SENSOR_CTRL_RSV_MASK 0xffffff
+#define AST_VT_SENSOR_CTRL_RSV_OFFSET 8
+#define AST_VT_SENSOR_CTRL_RSV_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_CTRL_RSV_MASK, .index = AST_VT_SENSOR_CTRL_RSV_OFFSET })
+
+// VT_SENSOR DATA read register
+#define AST_VT_SENSOR_DATA_REG_OFFSET 0xd8
+#define AST_VT_SENSOR_DATA_REG_RESVAL 0x0
+#define AST_VT_SENSOR_DATA_BN_MASK 0xfff
+#define AST_VT_SENSOR_DATA_BN_OFFSET 0
+#define AST_VT_SENSOR_DATA_BN_FIELD \
+ ((bitfield_field32_t) { .mask = AST_VT_SENSOR_DATA_BN_MASK, .index = AST_VT_SENSOR_DATA_BN_OFFSET })
+#define AST_VT_SENSOR_DATA_EOC_BIT 12
+
+// AST Registers Array-B to set address space size (common parameters)
+#define AST_REGB_REG32_FIELD_WIDTH 32
+#define AST_REGB_MULTIREG_COUNT 5
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_0_REG_OFFSET 0x200
+#define AST_REGB_0_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_1_REG_OFFSET 0x204
+#define AST_REGB_1_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_2_REG_OFFSET 0x208
+#define AST_REGB_2_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_3_REG_OFFSET 0x20c
+#define AST_REGB_3_REG_RESVAL 0x0
+
+// AST Registers Array-B to set address space size
+#define AST_REGB_4_REG_OFFSET 0x210
+#define AST_REGB_4_REG_RESVAL 0x0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _AST_REG_DEFS_
+// End generated register defines for ast
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/ip/clkmgr/data/autogen/clkmgr_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/ip/clkmgr/data/autogen/clkmgr_regs.h
new file mode 100644
index 0000000..6d6fdd2
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/ip/clkmgr/data/autogen/clkmgr_regs.h
@@ -0,0 +1,327 @@
+// Generated register defines for clkmgr
+
+// Copyright information found in source file:
+// Copyright 2022 Google Inc.Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _CLKMGR_REG_DEFS_
+#define _CLKMGR_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of clock groups
+#define CLKMGR_PARAM_NUM_GROUPS 7
+
+// Number of SW gateable clocks
+#define CLKMGR_PARAM_NUM_SW_GATEABLE_CLOCKS 7
+
+// Number of hintable clocks
+#define CLKMGR_PARAM_NUM_HINTABLE_CLOCKS 7
+
+// Number of alerts
+#define CLKMGR_PARAM_NUM_ALERTS 2
+
+// Register width
+#define CLKMGR_PARAM_REG_WIDTH 32
+
+// Alert Test Register
+#define CLKMGR_ALERT_TEST_REG_OFFSET 0x0
+#define CLKMGR_ALERT_TEST_REG_RESVAL 0x0
+#define CLKMGR_ALERT_TEST_RECOV_FAULT_BIT 0
+#define CLKMGR_ALERT_TEST_FATAL_FAULT_BIT 1
+
+// External clock control write enable
+#define CLKMGR_EXTCLK_CTRL_REGWEN_REG_OFFSET 0x4
+#define CLKMGR_EXTCLK_CTRL_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_EXTCLK_CTRL_REGWEN_EN_BIT 0
+
+// Select external clock
+#define CLKMGR_EXTCLK_CTRL_REG_OFFSET 0x8
+#define CLKMGR_EXTCLK_CTRL_REG_RESVAL 0x99
+#define CLKMGR_EXTCLK_CTRL_SEL_MASK 0xf
+#define CLKMGR_EXTCLK_CTRL_SEL_OFFSET 0
+#define CLKMGR_EXTCLK_CTRL_SEL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_CTRL_SEL_MASK, .index = CLKMGR_EXTCLK_CTRL_SEL_OFFSET })
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_MASK 0xf
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_OFFSET 4
+#define CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_MASK, .index = CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_OFFSET })
+
+// Status of requested external clock switch
+#define CLKMGR_EXTCLK_STATUS_REG_OFFSET 0xc
+#define CLKMGR_EXTCLK_STATUS_REG_RESVAL 0x9
+#define CLKMGR_EXTCLK_STATUS_ACK_MASK 0xf
+#define CLKMGR_EXTCLK_STATUS_ACK_OFFSET 0
+#define CLKMGR_EXTCLK_STATUS_ACK_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_EXTCLK_STATUS_ACK_MASK, .index = CLKMGR_EXTCLK_STATUS_ACK_OFFSET })
+
+// Jitter write enable
+#define CLKMGR_JITTER_REGWEN_REG_OFFSET 0x10
+#define CLKMGR_JITTER_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_JITTER_REGWEN_EN_BIT 0
+
+// Enable jittery clock
+#define CLKMGR_JITTER_ENABLE_REG_OFFSET 0x14
+#define CLKMGR_JITTER_ENABLE_REG_RESVAL 0x9
+#define CLKMGR_JITTER_ENABLE_VAL_MASK 0xf
+#define CLKMGR_JITTER_ENABLE_VAL_OFFSET 0
+#define CLKMGR_JITTER_ENABLE_VAL_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_JITTER_ENABLE_VAL_MASK, .index = CLKMGR_JITTER_ENABLE_VAL_OFFSET })
+
+// Clock enable for software gateable clocks.
+#define CLKMGR_CLK_ENABLES_REG_OFFSET 0x18
+#define CLKMGR_CLK_ENABLES_REG_RESVAL 0x7f
+#define CLKMGR_CLK_ENABLES_CLK_IO_DIV4_PERI_EN_BIT 0
+#define CLKMGR_CLK_ENABLES_CLK_IO_DIV2_PERI_EN_BIT 1
+#define CLKMGR_CLK_ENABLES_CLK_IO_PERI_EN_BIT 2
+#define CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT 3
+#define CLKMGR_CLK_ENABLES_CLK_ML_PERI_EN_BIT 4
+#define CLKMGR_CLK_ENABLES_CLK_AUDIO_PERI_EN_BIT 5
+#define CLKMGR_CLK_ENABLES_CLK_SMC_PERI_EN_BIT 6
+
+// Clock hint for software gateable transactional clocks during active mode.
+#define CLKMGR_CLK_HINTS_REG_OFFSET 0x1c
+#define CLKMGR_CLK_HINTS_REG_RESVAL 0x7f
+#define CLKMGR_CLK_HINTS_CLK_MAIN_AES_HINT_BIT 0
+#define CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT 1
+#define CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT 2
+#define CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT 3
+#define CLKMGR_CLK_HINTS_CLK_SMC_VIDEO_AUDIO_WRAPPER_HINT_BIT 4
+#define CLKMGR_CLK_HINTS_CLK_AUDIO_VSI_CTL_WRAPPER_HINT_BIT 5
+#define CLKMGR_CLK_HINTS_CLK_VIDEO_VSI_CTL_WRAPPER_HINT_BIT 6
+
+// Since the final state of !!CLK_HINTS is not always determined by software,
+#define CLKMGR_CLK_HINTS_STATUS_REG_OFFSET 0x20
+#define CLKMGR_CLK_HINTS_STATUS_REG_RESVAL 0x7f
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_AES_VAL_BIT 0
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_HMAC_VAL_BIT 1
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_KMAC_VAL_BIT 2
+#define CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT 3
+#define CLKMGR_CLK_HINTS_STATUS_CLK_SMC_VIDEO_AUDIO_WRAPPER_VAL_BIT 4
+#define CLKMGR_CLK_HINTS_STATUS_CLK_AUDIO_VSI_CTL_WRAPPER_VAL_BIT 5
+#define CLKMGR_CLK_HINTS_STATUS_CLK_VIDEO_VSI_CTL_WRAPPER_VAL_BIT 6
+
+// Measurement control write enable
+#define CLKMGR_MEASURE_CTRL_REGWEN_REG_OFFSET 0x24
+#define CLKMGR_MEASURE_CTRL_REGWEN_REG_RESVAL 0x1
+#define CLKMGR_MEASURE_CTRL_REGWEN_EN_BIT 0
+
+// Enable for measurement control
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_REG_OFFSET 0x28
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_AUDIO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for audio measurement.
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x2c
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x12e270
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_MASK 0x7ff
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_MASK 0x7ff
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_OFFSET 11
+#define CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_AUDIO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET 0x30
+#define CLKMGR_IO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io measurement.
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x34
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_REG_OFFSET 0x38
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io_div2 measurement.
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_REG_OFFSET 0x3c
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_REG_RESVAL 0x1ccfa
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_MASK 0x1ff
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_MASK 0x1ff
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_OFFSET 9
+#define CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_OFFSET 0x40
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for io_div4 measurement.
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_OFFSET 0x44
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_RESVAL 0x6e82
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_MASK 0xff
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_MASK 0xff
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_OFFSET 8
+#define CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET 0x48
+#define CLKMGR_MAIN_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for main measurement.
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET 0x4c
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_ML_MEAS_CTRL_EN_REG_OFFSET 0x50
+#define CLKMGR_ML_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_ML_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_ML_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for ml measurement.
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_REG_OFFSET 0x54
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_REG_RESVAL 0x4d84ec
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_MASK 0xfff
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_ML_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_MASK 0xfff
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_OFFSET 12
+#define CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_ML_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_SMC_MEAS_CTRL_EN_REG_OFFSET 0x58
+#define CLKMGR_SMC_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_SMC_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_SMC_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for smc measurement.
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_REG_OFFSET 0x5c
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_SMC_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_SMC_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_USB_MEAS_CTRL_EN_REG_OFFSET 0x60
+#define CLKMGR_USB_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_USB_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_USB_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for usb measurement.
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_OFFSET 0x64
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_RESVAL 0x1ccfa
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_MASK 0x1ff
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_MASK 0x1ff
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_OFFSET 9
+#define CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Enable for measurement control
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_REG_OFFSET 0x68
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_REG_RESVAL 0x9
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_MASK 0xf
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_OFFSET 0
+#define CLKMGR_VIDEO_MEAS_CTRL_EN_EN_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_EN_EN_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_EN_EN_OFFSET })
+
+// Configuration controls for video measurement.
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_REG_OFFSET 0x6c
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_REG_RESVAL 0x759ea
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_MASK 0x3ff
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_OFFSET 0
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_HI_OFFSET })
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_MASK 0x3ff
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_OFFSET 10
+#define CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_FIELD \
+ ((bitfield_field32_t) { .mask = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_MASK, .index = CLKMGR_VIDEO_MEAS_CTRL_SHADOWED_LO_OFFSET })
+
+// Recoverable Error code
+#define CLKMGR_RECOV_ERR_CODE_REG_OFFSET 0x70
+#define CLKMGR_RECOV_ERR_CODE_REG_RESVAL 0x0
+#define CLKMGR_RECOV_ERR_CODE_SHADOW_UPDATE_ERR_BIT 0
+#define CLKMGR_RECOV_ERR_CODE_AUDIO_MEASURE_ERR_BIT 1
+#define CLKMGR_RECOV_ERR_CODE_IO_MEASURE_ERR_BIT 2
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV2_MEASURE_ERR_BIT 3
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV4_MEASURE_ERR_BIT 4
+#define CLKMGR_RECOV_ERR_CODE_MAIN_MEASURE_ERR_BIT 5
+#define CLKMGR_RECOV_ERR_CODE_ML_MEASURE_ERR_BIT 6
+#define CLKMGR_RECOV_ERR_CODE_SMC_MEASURE_ERR_BIT 7
+#define CLKMGR_RECOV_ERR_CODE_USB_MEASURE_ERR_BIT 8
+#define CLKMGR_RECOV_ERR_CODE_VIDEO_MEASURE_ERR_BIT 9
+#define CLKMGR_RECOV_ERR_CODE_AUDIO_TIMEOUT_ERR_BIT 10
+#define CLKMGR_RECOV_ERR_CODE_IO_TIMEOUT_ERR_BIT 11
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV2_TIMEOUT_ERR_BIT 12
+#define CLKMGR_RECOV_ERR_CODE_IO_DIV4_TIMEOUT_ERR_BIT 13
+#define CLKMGR_RECOV_ERR_CODE_MAIN_TIMEOUT_ERR_BIT 14
+#define CLKMGR_RECOV_ERR_CODE_ML_TIMEOUT_ERR_BIT 15
+#define CLKMGR_RECOV_ERR_CODE_SMC_TIMEOUT_ERR_BIT 16
+#define CLKMGR_RECOV_ERR_CODE_USB_TIMEOUT_ERR_BIT 17
+#define CLKMGR_RECOV_ERR_CODE_VIDEO_TIMEOUT_ERR_BIT 18
+
+// Error code
+#define CLKMGR_FATAL_ERR_CODE_REG_OFFSET 0x74
+#define CLKMGR_FATAL_ERR_CODE_REG_RESVAL 0x0
+#define CLKMGR_FATAL_ERR_CODE_REG_INTG_BIT 0
+#define CLKMGR_FATAL_ERR_CODE_IDLE_CNT_BIT 1
+#define CLKMGR_FATAL_ERR_CODE_SHADOW_STORAGE_ERR_BIT 2
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _CLKMGR_REG_DEFS_
+// End generated register defines for clkmgr
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/ip/pinmux/data/autogen/pinmux_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/ip/pinmux/data/autogen/pinmux_regs.h
new file mode 100644
index 0000000..6afe955
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/ip/pinmux/data/autogen/pinmux_regs.h
@@ -0,0 +1,5240 @@
+// Generated register defines for pinmux
+
+// Copyright information found in source file:
+// Copyright 2022 Google Inc.Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _PINMUX_REG_DEFS_
+#define _PINMUX_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Pad attribute data width
+#define PINMUX_PARAM_ATTR_DW 13
+
+// Number of muxed peripheral inputs
+#define PINMUX_PARAM_N_MIO_PERIPH_IN 84
+
+// Number of muxed peripheral outputs
+#define PINMUX_PARAM_N_MIO_PERIPH_OUT 97
+
+// Number of muxed IO pads
+#define PINMUX_PARAM_N_MIO_PADS 53
+
+// Number of dedicated IO pads
+#define PINMUX_PARAM_N_DIO_PADS 16
+
+// Number of wakeup detectors
+#define PINMUX_PARAM_N_WKUP_DETECT 8
+
+// Number of wakeup counter bits
+#define PINMUX_PARAM_WKUP_CNT_WIDTH 8
+
+// Number of alerts
+#define PINMUX_PARAM_NUM_ALERTS 1
+
+// Register width
+#define PINMUX_PARAM_REG_WIDTH 32
+
+// Alert Test Register
+#define PINMUX_ALERT_TEST_REG_OFFSET 0x0
+#define PINMUX_ALERT_TEST_REG_RESVAL 0x0
+#define PINMUX_ALERT_TEST_FATAL_FAULT_BIT 0
+
+// Register write enable for MIO peripheral input selects. (common
+// parameters)
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT 84
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET 0x4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET 0x8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET 0xc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET 0x10
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_OFFSET 0x14
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_OFFSET 0x18
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_OFFSET 0x1c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_OFFSET 0x20
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_OFFSET 0x24
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_OFFSET 0x28
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_OFFSET 0x2c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_OFFSET 0x30
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_OFFSET 0x34
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_OFFSET 0x38
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_OFFSET 0x3c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_OFFSET 0x40
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_OFFSET 0x44
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_OFFSET 0x48
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_OFFSET 0x4c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_OFFSET 0x50
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_OFFSET 0x54
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_OFFSET 0x58
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_OFFSET 0x5c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_OFFSET 0x60
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_OFFSET 0x64
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_OFFSET 0x68
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_OFFSET 0x6c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_OFFSET 0x70
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_OFFSET 0x74
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_OFFSET 0x78
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_OFFSET 0x7c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_OFFSET 0x80
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_OFFSET 0x84
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_OFFSET 0x88
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_OFFSET 0x8c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_OFFSET 0x90
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_OFFSET 0x94
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_OFFSET 0x98
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_OFFSET 0x9c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_OFFSET 0xa0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_OFFSET 0xa4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_OFFSET 0xa8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_OFFSET 0xac
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_OFFSET 0xb0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_OFFSET 0xb4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_OFFSET 0xb8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_OFFSET 0xbc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_OFFSET 0xc0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_OFFSET 0xc4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_OFFSET 0xc8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_OFFSET 0xcc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_OFFSET 0xd0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_OFFSET 0xd4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_52_EN_52_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_OFFSET 0xd8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_53_EN_53_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_OFFSET 0xdc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_54_EN_54_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_OFFSET 0xe0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_55_EN_55_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_OFFSET 0xe4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_56_EN_56_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_OFFSET 0xe8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_57_EN_57_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_OFFSET 0xec
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_58_EN_58_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_OFFSET 0xf0
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_59_EN_59_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_OFFSET 0xf4
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_60_EN_60_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_OFFSET 0xf8
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_61_EN_61_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_OFFSET 0xfc
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_62_EN_62_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_OFFSET 0x100
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_63_EN_63_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_OFFSET 0x104
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_64_EN_64_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_OFFSET 0x108
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_65_EN_65_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_OFFSET 0x10c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_66_EN_66_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_OFFSET 0x110
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_67_EN_67_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_OFFSET 0x114
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_68_EN_68_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_OFFSET 0x118
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_69_EN_69_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_OFFSET 0x11c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_70_EN_70_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_OFFSET 0x120
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_71_EN_71_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_OFFSET 0x124
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_72_EN_72_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_OFFSET 0x128
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_73_EN_73_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_OFFSET 0x12c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_74_EN_74_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_OFFSET 0x130
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_75_EN_75_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_OFFSET 0x134
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_76_EN_76_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_OFFSET 0x138
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_77_EN_77_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_OFFSET 0x13c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_78_EN_78_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_OFFSET 0x140
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_79_EN_79_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_OFFSET 0x144
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_80_EN_80_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_OFFSET 0x148
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_81_EN_81_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_OFFSET 0x14c
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_82_EN_82_BIT 0
+
+// Register write enable for MIO peripheral input selects.
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_OFFSET 0x150
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_REG_RESVAL 0x1
+#define PINMUX_MIO_PERIPH_INSEL_REGWEN_83_EN_83_BIT 0
+
+// For each peripheral input, this selects the muxable pad input. (common
+// parameters)
+#define PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH 6
+#define PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT 84
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET 0x154
+#define PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK, .index = PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET 0x158
+#define PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK, .index = PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET 0x15c
+#define PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK, .index = PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET 0x160
+#define PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK, .index = PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_4_REG_OFFSET 0x164
+#define PINMUX_MIO_PERIPH_INSEL_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_4_IN_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_4_IN_4_MASK, .index = PINMUX_MIO_PERIPH_INSEL_4_IN_4_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_5_REG_OFFSET 0x168
+#define PINMUX_MIO_PERIPH_INSEL_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_5_IN_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_5_IN_5_MASK, .index = PINMUX_MIO_PERIPH_INSEL_5_IN_5_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_6_REG_OFFSET 0x16c
+#define PINMUX_MIO_PERIPH_INSEL_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_6_IN_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_6_IN_6_MASK, .index = PINMUX_MIO_PERIPH_INSEL_6_IN_6_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_7_REG_OFFSET 0x170
+#define PINMUX_MIO_PERIPH_INSEL_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_7_IN_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_7_IN_7_MASK, .index = PINMUX_MIO_PERIPH_INSEL_7_IN_7_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_8_REG_OFFSET 0x174
+#define PINMUX_MIO_PERIPH_INSEL_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_8_IN_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_8_IN_8_MASK, .index = PINMUX_MIO_PERIPH_INSEL_8_IN_8_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_9_REG_OFFSET 0x178
+#define PINMUX_MIO_PERIPH_INSEL_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_9_IN_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_9_IN_9_MASK, .index = PINMUX_MIO_PERIPH_INSEL_9_IN_9_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_10_REG_OFFSET 0x17c
+#define PINMUX_MIO_PERIPH_INSEL_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_10_IN_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_10_IN_10_MASK, .index = PINMUX_MIO_PERIPH_INSEL_10_IN_10_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_11_REG_OFFSET 0x180
+#define PINMUX_MIO_PERIPH_INSEL_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_11_IN_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_11_IN_11_MASK, .index = PINMUX_MIO_PERIPH_INSEL_11_IN_11_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_12_REG_OFFSET 0x184
+#define PINMUX_MIO_PERIPH_INSEL_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_12_IN_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_12_IN_12_MASK, .index = PINMUX_MIO_PERIPH_INSEL_12_IN_12_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_13_REG_OFFSET 0x188
+#define PINMUX_MIO_PERIPH_INSEL_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_13_IN_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_13_IN_13_MASK, .index = PINMUX_MIO_PERIPH_INSEL_13_IN_13_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_14_REG_OFFSET 0x18c
+#define PINMUX_MIO_PERIPH_INSEL_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_14_IN_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_14_IN_14_MASK, .index = PINMUX_MIO_PERIPH_INSEL_14_IN_14_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_15_REG_OFFSET 0x190
+#define PINMUX_MIO_PERIPH_INSEL_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_15_IN_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_15_IN_15_MASK, .index = PINMUX_MIO_PERIPH_INSEL_15_IN_15_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_16_REG_OFFSET 0x194
+#define PINMUX_MIO_PERIPH_INSEL_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_16_IN_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_16_IN_16_MASK, .index = PINMUX_MIO_PERIPH_INSEL_16_IN_16_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_17_REG_OFFSET 0x198
+#define PINMUX_MIO_PERIPH_INSEL_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_17_IN_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_17_IN_17_MASK, .index = PINMUX_MIO_PERIPH_INSEL_17_IN_17_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_18_REG_OFFSET 0x19c
+#define PINMUX_MIO_PERIPH_INSEL_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_18_IN_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_18_IN_18_MASK, .index = PINMUX_MIO_PERIPH_INSEL_18_IN_18_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_19_REG_OFFSET 0x1a0
+#define PINMUX_MIO_PERIPH_INSEL_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_19_IN_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_19_IN_19_MASK, .index = PINMUX_MIO_PERIPH_INSEL_19_IN_19_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_20_REG_OFFSET 0x1a4
+#define PINMUX_MIO_PERIPH_INSEL_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_20_IN_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_20_IN_20_MASK, .index = PINMUX_MIO_PERIPH_INSEL_20_IN_20_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_21_REG_OFFSET 0x1a8
+#define PINMUX_MIO_PERIPH_INSEL_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_21_IN_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_21_IN_21_MASK, .index = PINMUX_MIO_PERIPH_INSEL_21_IN_21_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_22_REG_OFFSET 0x1ac
+#define PINMUX_MIO_PERIPH_INSEL_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_22_IN_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_22_IN_22_MASK, .index = PINMUX_MIO_PERIPH_INSEL_22_IN_22_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_23_REG_OFFSET 0x1b0
+#define PINMUX_MIO_PERIPH_INSEL_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_23_IN_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_23_IN_23_MASK, .index = PINMUX_MIO_PERIPH_INSEL_23_IN_23_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_24_REG_OFFSET 0x1b4
+#define PINMUX_MIO_PERIPH_INSEL_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_24_IN_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_24_IN_24_MASK, .index = PINMUX_MIO_PERIPH_INSEL_24_IN_24_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_25_REG_OFFSET 0x1b8
+#define PINMUX_MIO_PERIPH_INSEL_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_25_IN_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_25_IN_25_MASK, .index = PINMUX_MIO_PERIPH_INSEL_25_IN_25_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_26_REG_OFFSET 0x1bc
+#define PINMUX_MIO_PERIPH_INSEL_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_26_IN_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_26_IN_26_MASK, .index = PINMUX_MIO_PERIPH_INSEL_26_IN_26_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_27_REG_OFFSET 0x1c0
+#define PINMUX_MIO_PERIPH_INSEL_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_27_IN_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_27_IN_27_MASK, .index = PINMUX_MIO_PERIPH_INSEL_27_IN_27_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_28_REG_OFFSET 0x1c4
+#define PINMUX_MIO_PERIPH_INSEL_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_28_IN_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_28_IN_28_MASK, .index = PINMUX_MIO_PERIPH_INSEL_28_IN_28_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_29_REG_OFFSET 0x1c8
+#define PINMUX_MIO_PERIPH_INSEL_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_29_IN_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_29_IN_29_MASK, .index = PINMUX_MIO_PERIPH_INSEL_29_IN_29_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_30_REG_OFFSET 0x1cc
+#define PINMUX_MIO_PERIPH_INSEL_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_30_IN_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_30_IN_30_MASK, .index = PINMUX_MIO_PERIPH_INSEL_30_IN_30_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_31_REG_OFFSET 0x1d0
+#define PINMUX_MIO_PERIPH_INSEL_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_31_IN_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_31_IN_31_MASK, .index = PINMUX_MIO_PERIPH_INSEL_31_IN_31_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_32_REG_OFFSET 0x1d4
+#define PINMUX_MIO_PERIPH_INSEL_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_32_IN_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_32_IN_32_MASK, .index = PINMUX_MIO_PERIPH_INSEL_32_IN_32_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_33_REG_OFFSET 0x1d8
+#define PINMUX_MIO_PERIPH_INSEL_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_33_IN_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_33_IN_33_MASK, .index = PINMUX_MIO_PERIPH_INSEL_33_IN_33_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_34_REG_OFFSET 0x1dc
+#define PINMUX_MIO_PERIPH_INSEL_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_34_IN_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_34_IN_34_MASK, .index = PINMUX_MIO_PERIPH_INSEL_34_IN_34_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_35_REG_OFFSET 0x1e0
+#define PINMUX_MIO_PERIPH_INSEL_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_35_IN_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_35_IN_35_MASK, .index = PINMUX_MIO_PERIPH_INSEL_35_IN_35_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_36_REG_OFFSET 0x1e4
+#define PINMUX_MIO_PERIPH_INSEL_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_36_IN_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_36_IN_36_MASK, .index = PINMUX_MIO_PERIPH_INSEL_36_IN_36_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_37_REG_OFFSET 0x1e8
+#define PINMUX_MIO_PERIPH_INSEL_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_37_IN_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_37_IN_37_MASK, .index = PINMUX_MIO_PERIPH_INSEL_37_IN_37_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_38_REG_OFFSET 0x1ec
+#define PINMUX_MIO_PERIPH_INSEL_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_38_IN_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_38_IN_38_MASK, .index = PINMUX_MIO_PERIPH_INSEL_38_IN_38_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_39_REG_OFFSET 0x1f0
+#define PINMUX_MIO_PERIPH_INSEL_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_39_IN_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_39_IN_39_MASK, .index = PINMUX_MIO_PERIPH_INSEL_39_IN_39_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_40_REG_OFFSET 0x1f4
+#define PINMUX_MIO_PERIPH_INSEL_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_40_IN_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_40_IN_40_MASK, .index = PINMUX_MIO_PERIPH_INSEL_40_IN_40_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_41_REG_OFFSET 0x1f8
+#define PINMUX_MIO_PERIPH_INSEL_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_41_IN_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_41_IN_41_MASK, .index = PINMUX_MIO_PERIPH_INSEL_41_IN_41_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_42_REG_OFFSET 0x1fc
+#define PINMUX_MIO_PERIPH_INSEL_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_42_IN_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_42_IN_42_MASK, .index = PINMUX_MIO_PERIPH_INSEL_42_IN_42_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_43_REG_OFFSET 0x200
+#define PINMUX_MIO_PERIPH_INSEL_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_43_IN_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_43_IN_43_MASK, .index = PINMUX_MIO_PERIPH_INSEL_43_IN_43_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_44_REG_OFFSET 0x204
+#define PINMUX_MIO_PERIPH_INSEL_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_44_IN_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_44_IN_44_MASK, .index = PINMUX_MIO_PERIPH_INSEL_44_IN_44_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_45_REG_OFFSET 0x208
+#define PINMUX_MIO_PERIPH_INSEL_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_45_IN_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_45_IN_45_MASK, .index = PINMUX_MIO_PERIPH_INSEL_45_IN_45_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_46_REG_OFFSET 0x20c
+#define PINMUX_MIO_PERIPH_INSEL_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_46_IN_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_46_IN_46_MASK, .index = PINMUX_MIO_PERIPH_INSEL_46_IN_46_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_47_REG_OFFSET 0x210
+#define PINMUX_MIO_PERIPH_INSEL_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_47_IN_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_47_IN_47_MASK, .index = PINMUX_MIO_PERIPH_INSEL_47_IN_47_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_48_REG_OFFSET 0x214
+#define PINMUX_MIO_PERIPH_INSEL_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_48_IN_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_48_IN_48_MASK, .index = PINMUX_MIO_PERIPH_INSEL_48_IN_48_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_49_REG_OFFSET 0x218
+#define PINMUX_MIO_PERIPH_INSEL_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_49_IN_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_49_IN_49_MASK, .index = PINMUX_MIO_PERIPH_INSEL_49_IN_49_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_50_REG_OFFSET 0x21c
+#define PINMUX_MIO_PERIPH_INSEL_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_50_IN_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_50_IN_50_MASK, .index = PINMUX_MIO_PERIPH_INSEL_50_IN_50_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_51_REG_OFFSET 0x220
+#define PINMUX_MIO_PERIPH_INSEL_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_51_IN_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_51_IN_51_MASK, .index = PINMUX_MIO_PERIPH_INSEL_51_IN_51_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_52_REG_OFFSET 0x224
+#define PINMUX_MIO_PERIPH_INSEL_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_52_IN_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_52_IN_52_MASK, .index = PINMUX_MIO_PERIPH_INSEL_52_IN_52_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_53_REG_OFFSET 0x228
+#define PINMUX_MIO_PERIPH_INSEL_53_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_53_IN_53_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_53_IN_53_MASK, .index = PINMUX_MIO_PERIPH_INSEL_53_IN_53_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_54_REG_OFFSET 0x22c
+#define PINMUX_MIO_PERIPH_INSEL_54_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_54_IN_54_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_54_IN_54_MASK, .index = PINMUX_MIO_PERIPH_INSEL_54_IN_54_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_55_REG_OFFSET 0x230
+#define PINMUX_MIO_PERIPH_INSEL_55_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_55_IN_55_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_55_IN_55_MASK, .index = PINMUX_MIO_PERIPH_INSEL_55_IN_55_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_56_REG_OFFSET 0x234
+#define PINMUX_MIO_PERIPH_INSEL_56_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_56_IN_56_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_56_IN_56_MASK, .index = PINMUX_MIO_PERIPH_INSEL_56_IN_56_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_57_REG_OFFSET 0x238
+#define PINMUX_MIO_PERIPH_INSEL_57_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_57_IN_57_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_57_IN_57_MASK, .index = PINMUX_MIO_PERIPH_INSEL_57_IN_57_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_58_REG_OFFSET 0x23c
+#define PINMUX_MIO_PERIPH_INSEL_58_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_58_IN_58_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_58_IN_58_MASK, .index = PINMUX_MIO_PERIPH_INSEL_58_IN_58_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_59_REG_OFFSET 0x240
+#define PINMUX_MIO_PERIPH_INSEL_59_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_59_IN_59_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_59_IN_59_MASK, .index = PINMUX_MIO_PERIPH_INSEL_59_IN_59_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_60_REG_OFFSET 0x244
+#define PINMUX_MIO_PERIPH_INSEL_60_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_60_IN_60_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_60_IN_60_MASK, .index = PINMUX_MIO_PERIPH_INSEL_60_IN_60_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_61_REG_OFFSET 0x248
+#define PINMUX_MIO_PERIPH_INSEL_61_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_61_IN_61_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_61_IN_61_MASK, .index = PINMUX_MIO_PERIPH_INSEL_61_IN_61_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_62_REG_OFFSET 0x24c
+#define PINMUX_MIO_PERIPH_INSEL_62_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_62_IN_62_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_62_IN_62_MASK, .index = PINMUX_MIO_PERIPH_INSEL_62_IN_62_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_63_REG_OFFSET 0x250
+#define PINMUX_MIO_PERIPH_INSEL_63_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_63_IN_63_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_63_IN_63_MASK, .index = PINMUX_MIO_PERIPH_INSEL_63_IN_63_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_64_REG_OFFSET 0x254
+#define PINMUX_MIO_PERIPH_INSEL_64_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_64_IN_64_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_64_IN_64_MASK, .index = PINMUX_MIO_PERIPH_INSEL_64_IN_64_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_65_REG_OFFSET 0x258
+#define PINMUX_MIO_PERIPH_INSEL_65_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_65_IN_65_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_65_IN_65_MASK, .index = PINMUX_MIO_PERIPH_INSEL_65_IN_65_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_66_REG_OFFSET 0x25c
+#define PINMUX_MIO_PERIPH_INSEL_66_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_66_IN_66_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_66_IN_66_MASK, .index = PINMUX_MIO_PERIPH_INSEL_66_IN_66_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_67_REG_OFFSET 0x260
+#define PINMUX_MIO_PERIPH_INSEL_67_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_67_IN_67_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_67_IN_67_MASK, .index = PINMUX_MIO_PERIPH_INSEL_67_IN_67_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_68_REG_OFFSET 0x264
+#define PINMUX_MIO_PERIPH_INSEL_68_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_68_IN_68_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_68_IN_68_MASK, .index = PINMUX_MIO_PERIPH_INSEL_68_IN_68_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_69_REG_OFFSET 0x268
+#define PINMUX_MIO_PERIPH_INSEL_69_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_69_IN_69_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_69_IN_69_MASK, .index = PINMUX_MIO_PERIPH_INSEL_69_IN_69_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_70_REG_OFFSET 0x26c
+#define PINMUX_MIO_PERIPH_INSEL_70_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_70_IN_70_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_70_IN_70_MASK, .index = PINMUX_MIO_PERIPH_INSEL_70_IN_70_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_71_REG_OFFSET 0x270
+#define PINMUX_MIO_PERIPH_INSEL_71_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_71_IN_71_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_71_IN_71_MASK, .index = PINMUX_MIO_PERIPH_INSEL_71_IN_71_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_72_REG_OFFSET 0x274
+#define PINMUX_MIO_PERIPH_INSEL_72_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_72_IN_72_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_72_IN_72_MASK, .index = PINMUX_MIO_PERIPH_INSEL_72_IN_72_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_73_REG_OFFSET 0x278
+#define PINMUX_MIO_PERIPH_INSEL_73_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_73_IN_73_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_73_IN_73_MASK, .index = PINMUX_MIO_PERIPH_INSEL_73_IN_73_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_74_REG_OFFSET 0x27c
+#define PINMUX_MIO_PERIPH_INSEL_74_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_74_IN_74_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_74_IN_74_MASK, .index = PINMUX_MIO_PERIPH_INSEL_74_IN_74_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_75_REG_OFFSET 0x280
+#define PINMUX_MIO_PERIPH_INSEL_75_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_75_IN_75_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_75_IN_75_MASK, .index = PINMUX_MIO_PERIPH_INSEL_75_IN_75_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_76_REG_OFFSET 0x284
+#define PINMUX_MIO_PERIPH_INSEL_76_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_76_IN_76_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_76_IN_76_MASK, .index = PINMUX_MIO_PERIPH_INSEL_76_IN_76_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_77_REG_OFFSET 0x288
+#define PINMUX_MIO_PERIPH_INSEL_77_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_77_IN_77_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_77_IN_77_MASK, .index = PINMUX_MIO_PERIPH_INSEL_77_IN_77_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_78_REG_OFFSET 0x28c
+#define PINMUX_MIO_PERIPH_INSEL_78_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_78_IN_78_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_78_IN_78_MASK, .index = PINMUX_MIO_PERIPH_INSEL_78_IN_78_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_79_REG_OFFSET 0x290
+#define PINMUX_MIO_PERIPH_INSEL_79_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_79_IN_79_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_79_IN_79_MASK, .index = PINMUX_MIO_PERIPH_INSEL_79_IN_79_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_80_REG_OFFSET 0x294
+#define PINMUX_MIO_PERIPH_INSEL_80_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_80_IN_80_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_80_IN_80_MASK, .index = PINMUX_MIO_PERIPH_INSEL_80_IN_80_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_81_REG_OFFSET 0x298
+#define PINMUX_MIO_PERIPH_INSEL_81_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_81_IN_81_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_81_IN_81_MASK, .index = PINMUX_MIO_PERIPH_INSEL_81_IN_81_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_82_REG_OFFSET 0x29c
+#define PINMUX_MIO_PERIPH_INSEL_82_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_82_IN_82_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_82_IN_82_MASK, .index = PINMUX_MIO_PERIPH_INSEL_82_IN_82_OFFSET })
+
+// For each peripheral input, this selects the muxable pad input.
+#define PINMUX_MIO_PERIPH_INSEL_83_REG_OFFSET 0x2a0
+#define PINMUX_MIO_PERIPH_INSEL_83_REG_RESVAL 0x0
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK 0x3f
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET 0
+#define PINMUX_MIO_PERIPH_INSEL_83_IN_83_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_83_IN_83_MASK, .index = PINMUX_MIO_PERIPH_INSEL_83_IN_83_OFFSET })
+
+// Register write enable for MIO output selects. (common parameters)
+#define PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET 0x2a4
+#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET 0x2a8
+#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET 0x2ac
+#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET 0x2b0
+#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET 0x2b4
+#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET 0x2b8
+#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET 0x2bc
+#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET 0x2c0
+#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET 0x2c4
+#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET 0x2c8
+#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET 0x2cc
+#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET 0x2d0
+#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_12_REG_OFFSET 0x2d4
+#define PINMUX_MIO_OUTSEL_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_13_REG_OFFSET 0x2d8
+#define PINMUX_MIO_OUTSEL_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_14_REG_OFFSET 0x2dc
+#define PINMUX_MIO_OUTSEL_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_15_REG_OFFSET 0x2e0
+#define PINMUX_MIO_OUTSEL_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_16_REG_OFFSET 0x2e4
+#define PINMUX_MIO_OUTSEL_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_17_REG_OFFSET 0x2e8
+#define PINMUX_MIO_OUTSEL_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_18_REG_OFFSET 0x2ec
+#define PINMUX_MIO_OUTSEL_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_19_REG_OFFSET 0x2f0
+#define PINMUX_MIO_OUTSEL_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_20_REG_OFFSET 0x2f4
+#define PINMUX_MIO_OUTSEL_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_21_REG_OFFSET 0x2f8
+#define PINMUX_MIO_OUTSEL_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_22_REG_OFFSET 0x2fc
+#define PINMUX_MIO_OUTSEL_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_23_REG_OFFSET 0x300
+#define PINMUX_MIO_OUTSEL_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_24_REG_OFFSET 0x304
+#define PINMUX_MIO_OUTSEL_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_25_REG_OFFSET 0x308
+#define PINMUX_MIO_OUTSEL_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_26_REG_OFFSET 0x30c
+#define PINMUX_MIO_OUTSEL_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_27_REG_OFFSET 0x310
+#define PINMUX_MIO_OUTSEL_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_28_REG_OFFSET 0x314
+#define PINMUX_MIO_OUTSEL_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_29_REG_OFFSET 0x318
+#define PINMUX_MIO_OUTSEL_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_30_REG_OFFSET 0x31c
+#define PINMUX_MIO_OUTSEL_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_31_REG_OFFSET 0x320
+#define PINMUX_MIO_OUTSEL_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_32_REG_OFFSET 0x324
+#define PINMUX_MIO_OUTSEL_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_33_REG_OFFSET 0x328
+#define PINMUX_MIO_OUTSEL_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_34_REG_OFFSET 0x32c
+#define PINMUX_MIO_OUTSEL_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_35_REG_OFFSET 0x330
+#define PINMUX_MIO_OUTSEL_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_36_REG_OFFSET 0x334
+#define PINMUX_MIO_OUTSEL_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_37_REG_OFFSET 0x338
+#define PINMUX_MIO_OUTSEL_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_38_REG_OFFSET 0x33c
+#define PINMUX_MIO_OUTSEL_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_39_REG_OFFSET 0x340
+#define PINMUX_MIO_OUTSEL_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_40_REG_OFFSET 0x344
+#define PINMUX_MIO_OUTSEL_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_41_REG_OFFSET 0x348
+#define PINMUX_MIO_OUTSEL_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_42_REG_OFFSET 0x34c
+#define PINMUX_MIO_OUTSEL_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_43_REG_OFFSET 0x350
+#define PINMUX_MIO_OUTSEL_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_44_REG_OFFSET 0x354
+#define PINMUX_MIO_OUTSEL_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_45_REG_OFFSET 0x358
+#define PINMUX_MIO_OUTSEL_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_46_REG_OFFSET 0x35c
+#define PINMUX_MIO_OUTSEL_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_47_REG_OFFSET 0x360
+#define PINMUX_MIO_OUTSEL_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_48_REG_OFFSET 0x364
+#define PINMUX_MIO_OUTSEL_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_49_REG_OFFSET 0x368
+#define PINMUX_MIO_OUTSEL_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_50_REG_OFFSET 0x36c
+#define PINMUX_MIO_OUTSEL_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_51_REG_OFFSET 0x370
+#define PINMUX_MIO_OUTSEL_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO output selects.
+#define PINMUX_MIO_OUTSEL_REGWEN_52_REG_OFFSET 0x374
+#define PINMUX_MIO_OUTSEL_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_OUTSEL_REGWEN_52_EN_52_BIT 0
+
+// For each muxable pad, this selects the peripheral output. (common
+// parameters)
+#define PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH 7
+#define PINMUX_MIO_OUTSEL_MULTIREG_COUNT 53
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_0_REG_OFFSET 0x378
+#define PINMUX_MIO_OUTSEL_0_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_0_OUT_0_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET 0
+#define PINMUX_MIO_OUTSEL_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK, .index = PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_1_REG_OFFSET 0x37c
+#define PINMUX_MIO_OUTSEL_1_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_1_OUT_1_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET 0
+#define PINMUX_MIO_OUTSEL_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_1_OUT_1_MASK, .index = PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_2_REG_OFFSET 0x380
+#define PINMUX_MIO_OUTSEL_2_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_2_OUT_2_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET 0
+#define PINMUX_MIO_OUTSEL_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_2_OUT_2_MASK, .index = PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_3_REG_OFFSET 0x384
+#define PINMUX_MIO_OUTSEL_3_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_3_OUT_3_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET 0
+#define PINMUX_MIO_OUTSEL_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_3_OUT_3_MASK, .index = PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_4_REG_OFFSET 0x388
+#define PINMUX_MIO_OUTSEL_4_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_4_OUT_4_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET 0
+#define PINMUX_MIO_OUTSEL_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_4_OUT_4_MASK, .index = PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_5_REG_OFFSET 0x38c
+#define PINMUX_MIO_OUTSEL_5_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_5_OUT_5_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET 0
+#define PINMUX_MIO_OUTSEL_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_5_OUT_5_MASK, .index = PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_6_REG_OFFSET 0x390
+#define PINMUX_MIO_OUTSEL_6_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_6_OUT_6_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET 0
+#define PINMUX_MIO_OUTSEL_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_6_OUT_6_MASK, .index = PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_7_REG_OFFSET 0x394
+#define PINMUX_MIO_OUTSEL_7_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_7_OUT_7_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET 0
+#define PINMUX_MIO_OUTSEL_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_7_OUT_7_MASK, .index = PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_8_REG_OFFSET 0x398
+#define PINMUX_MIO_OUTSEL_8_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_8_OUT_8_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET 0
+#define PINMUX_MIO_OUTSEL_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_8_OUT_8_MASK, .index = PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_9_REG_OFFSET 0x39c
+#define PINMUX_MIO_OUTSEL_9_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_9_OUT_9_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET 0
+#define PINMUX_MIO_OUTSEL_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_9_OUT_9_MASK, .index = PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_10_REG_OFFSET 0x3a0
+#define PINMUX_MIO_OUTSEL_10_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_10_OUT_10_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET 0
+#define PINMUX_MIO_OUTSEL_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_10_OUT_10_MASK, .index = PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_11_REG_OFFSET 0x3a4
+#define PINMUX_MIO_OUTSEL_11_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_11_OUT_11_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET 0
+#define PINMUX_MIO_OUTSEL_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_11_OUT_11_MASK, .index = PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_12_REG_OFFSET 0x3a8
+#define PINMUX_MIO_OUTSEL_12_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_12_OUT_12_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET 0
+#define PINMUX_MIO_OUTSEL_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_12_OUT_12_MASK, .index = PINMUX_MIO_OUTSEL_12_OUT_12_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_13_REG_OFFSET 0x3ac
+#define PINMUX_MIO_OUTSEL_13_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_13_OUT_13_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET 0
+#define PINMUX_MIO_OUTSEL_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_13_OUT_13_MASK, .index = PINMUX_MIO_OUTSEL_13_OUT_13_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_14_REG_OFFSET 0x3b0
+#define PINMUX_MIO_OUTSEL_14_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_14_OUT_14_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET 0
+#define PINMUX_MIO_OUTSEL_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_14_OUT_14_MASK, .index = PINMUX_MIO_OUTSEL_14_OUT_14_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_15_REG_OFFSET 0x3b4
+#define PINMUX_MIO_OUTSEL_15_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_15_OUT_15_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET 0
+#define PINMUX_MIO_OUTSEL_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_15_OUT_15_MASK, .index = PINMUX_MIO_OUTSEL_15_OUT_15_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_16_REG_OFFSET 0x3b8
+#define PINMUX_MIO_OUTSEL_16_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_16_OUT_16_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET 0
+#define PINMUX_MIO_OUTSEL_16_OUT_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_16_OUT_16_MASK, .index = PINMUX_MIO_OUTSEL_16_OUT_16_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_17_REG_OFFSET 0x3bc
+#define PINMUX_MIO_OUTSEL_17_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_17_OUT_17_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET 0
+#define PINMUX_MIO_OUTSEL_17_OUT_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_17_OUT_17_MASK, .index = PINMUX_MIO_OUTSEL_17_OUT_17_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_18_REG_OFFSET 0x3c0
+#define PINMUX_MIO_OUTSEL_18_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_18_OUT_18_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET 0
+#define PINMUX_MIO_OUTSEL_18_OUT_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_18_OUT_18_MASK, .index = PINMUX_MIO_OUTSEL_18_OUT_18_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_19_REG_OFFSET 0x3c4
+#define PINMUX_MIO_OUTSEL_19_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_19_OUT_19_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET 0
+#define PINMUX_MIO_OUTSEL_19_OUT_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_19_OUT_19_MASK, .index = PINMUX_MIO_OUTSEL_19_OUT_19_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_20_REG_OFFSET 0x3c8
+#define PINMUX_MIO_OUTSEL_20_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_20_OUT_20_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET 0
+#define PINMUX_MIO_OUTSEL_20_OUT_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_20_OUT_20_MASK, .index = PINMUX_MIO_OUTSEL_20_OUT_20_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_21_REG_OFFSET 0x3cc
+#define PINMUX_MIO_OUTSEL_21_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_21_OUT_21_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET 0
+#define PINMUX_MIO_OUTSEL_21_OUT_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_21_OUT_21_MASK, .index = PINMUX_MIO_OUTSEL_21_OUT_21_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_22_REG_OFFSET 0x3d0
+#define PINMUX_MIO_OUTSEL_22_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_22_OUT_22_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET 0
+#define PINMUX_MIO_OUTSEL_22_OUT_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_22_OUT_22_MASK, .index = PINMUX_MIO_OUTSEL_22_OUT_22_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_23_REG_OFFSET 0x3d4
+#define PINMUX_MIO_OUTSEL_23_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_23_OUT_23_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET 0
+#define PINMUX_MIO_OUTSEL_23_OUT_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_23_OUT_23_MASK, .index = PINMUX_MIO_OUTSEL_23_OUT_23_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_24_REG_OFFSET 0x3d8
+#define PINMUX_MIO_OUTSEL_24_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_24_OUT_24_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET 0
+#define PINMUX_MIO_OUTSEL_24_OUT_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_24_OUT_24_MASK, .index = PINMUX_MIO_OUTSEL_24_OUT_24_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_25_REG_OFFSET 0x3dc
+#define PINMUX_MIO_OUTSEL_25_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_25_OUT_25_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET 0
+#define PINMUX_MIO_OUTSEL_25_OUT_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_25_OUT_25_MASK, .index = PINMUX_MIO_OUTSEL_25_OUT_25_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_26_REG_OFFSET 0x3e0
+#define PINMUX_MIO_OUTSEL_26_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_26_OUT_26_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET 0
+#define PINMUX_MIO_OUTSEL_26_OUT_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_26_OUT_26_MASK, .index = PINMUX_MIO_OUTSEL_26_OUT_26_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_27_REG_OFFSET 0x3e4
+#define PINMUX_MIO_OUTSEL_27_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_27_OUT_27_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET 0
+#define PINMUX_MIO_OUTSEL_27_OUT_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_27_OUT_27_MASK, .index = PINMUX_MIO_OUTSEL_27_OUT_27_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_28_REG_OFFSET 0x3e8
+#define PINMUX_MIO_OUTSEL_28_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_28_OUT_28_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET 0
+#define PINMUX_MIO_OUTSEL_28_OUT_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_28_OUT_28_MASK, .index = PINMUX_MIO_OUTSEL_28_OUT_28_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_29_REG_OFFSET 0x3ec
+#define PINMUX_MIO_OUTSEL_29_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_29_OUT_29_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET 0
+#define PINMUX_MIO_OUTSEL_29_OUT_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_29_OUT_29_MASK, .index = PINMUX_MIO_OUTSEL_29_OUT_29_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_30_REG_OFFSET 0x3f0
+#define PINMUX_MIO_OUTSEL_30_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_30_OUT_30_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET 0
+#define PINMUX_MIO_OUTSEL_30_OUT_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_30_OUT_30_MASK, .index = PINMUX_MIO_OUTSEL_30_OUT_30_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_31_REG_OFFSET 0x3f4
+#define PINMUX_MIO_OUTSEL_31_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_31_OUT_31_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET 0
+#define PINMUX_MIO_OUTSEL_31_OUT_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_31_OUT_31_MASK, .index = PINMUX_MIO_OUTSEL_31_OUT_31_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_32_REG_OFFSET 0x3f8
+#define PINMUX_MIO_OUTSEL_32_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_32_OUT_32_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET 0
+#define PINMUX_MIO_OUTSEL_32_OUT_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_32_OUT_32_MASK, .index = PINMUX_MIO_OUTSEL_32_OUT_32_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_33_REG_OFFSET 0x3fc
+#define PINMUX_MIO_OUTSEL_33_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_33_OUT_33_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET 0
+#define PINMUX_MIO_OUTSEL_33_OUT_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_33_OUT_33_MASK, .index = PINMUX_MIO_OUTSEL_33_OUT_33_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_34_REG_OFFSET 0x400
+#define PINMUX_MIO_OUTSEL_34_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_34_OUT_34_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET 0
+#define PINMUX_MIO_OUTSEL_34_OUT_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_34_OUT_34_MASK, .index = PINMUX_MIO_OUTSEL_34_OUT_34_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_35_REG_OFFSET 0x404
+#define PINMUX_MIO_OUTSEL_35_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_35_OUT_35_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET 0
+#define PINMUX_MIO_OUTSEL_35_OUT_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_35_OUT_35_MASK, .index = PINMUX_MIO_OUTSEL_35_OUT_35_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_36_REG_OFFSET 0x408
+#define PINMUX_MIO_OUTSEL_36_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_36_OUT_36_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET 0
+#define PINMUX_MIO_OUTSEL_36_OUT_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_36_OUT_36_MASK, .index = PINMUX_MIO_OUTSEL_36_OUT_36_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_37_REG_OFFSET 0x40c
+#define PINMUX_MIO_OUTSEL_37_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_37_OUT_37_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET 0
+#define PINMUX_MIO_OUTSEL_37_OUT_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_37_OUT_37_MASK, .index = PINMUX_MIO_OUTSEL_37_OUT_37_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_38_REG_OFFSET 0x410
+#define PINMUX_MIO_OUTSEL_38_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_38_OUT_38_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET 0
+#define PINMUX_MIO_OUTSEL_38_OUT_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_38_OUT_38_MASK, .index = PINMUX_MIO_OUTSEL_38_OUT_38_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_39_REG_OFFSET 0x414
+#define PINMUX_MIO_OUTSEL_39_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_39_OUT_39_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET 0
+#define PINMUX_MIO_OUTSEL_39_OUT_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_39_OUT_39_MASK, .index = PINMUX_MIO_OUTSEL_39_OUT_39_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_40_REG_OFFSET 0x418
+#define PINMUX_MIO_OUTSEL_40_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_40_OUT_40_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET 0
+#define PINMUX_MIO_OUTSEL_40_OUT_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_40_OUT_40_MASK, .index = PINMUX_MIO_OUTSEL_40_OUT_40_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_41_REG_OFFSET 0x41c
+#define PINMUX_MIO_OUTSEL_41_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_41_OUT_41_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET 0
+#define PINMUX_MIO_OUTSEL_41_OUT_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_41_OUT_41_MASK, .index = PINMUX_MIO_OUTSEL_41_OUT_41_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_42_REG_OFFSET 0x420
+#define PINMUX_MIO_OUTSEL_42_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_42_OUT_42_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET 0
+#define PINMUX_MIO_OUTSEL_42_OUT_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_42_OUT_42_MASK, .index = PINMUX_MIO_OUTSEL_42_OUT_42_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_43_REG_OFFSET 0x424
+#define PINMUX_MIO_OUTSEL_43_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_43_OUT_43_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET 0
+#define PINMUX_MIO_OUTSEL_43_OUT_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_43_OUT_43_MASK, .index = PINMUX_MIO_OUTSEL_43_OUT_43_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_44_REG_OFFSET 0x428
+#define PINMUX_MIO_OUTSEL_44_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_44_OUT_44_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET 0
+#define PINMUX_MIO_OUTSEL_44_OUT_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_44_OUT_44_MASK, .index = PINMUX_MIO_OUTSEL_44_OUT_44_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_45_REG_OFFSET 0x42c
+#define PINMUX_MIO_OUTSEL_45_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_45_OUT_45_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET 0
+#define PINMUX_MIO_OUTSEL_45_OUT_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_45_OUT_45_MASK, .index = PINMUX_MIO_OUTSEL_45_OUT_45_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_46_REG_OFFSET 0x430
+#define PINMUX_MIO_OUTSEL_46_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_46_OUT_46_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET 0
+#define PINMUX_MIO_OUTSEL_46_OUT_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_46_OUT_46_MASK, .index = PINMUX_MIO_OUTSEL_46_OUT_46_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_47_REG_OFFSET 0x434
+#define PINMUX_MIO_OUTSEL_47_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_47_OUT_47_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_47_OUT_47_OFFSET 0
+#define PINMUX_MIO_OUTSEL_47_OUT_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_47_OUT_47_MASK, .index = PINMUX_MIO_OUTSEL_47_OUT_47_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_48_REG_OFFSET 0x438
+#define PINMUX_MIO_OUTSEL_48_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_48_OUT_48_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_48_OUT_48_OFFSET 0
+#define PINMUX_MIO_OUTSEL_48_OUT_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_48_OUT_48_MASK, .index = PINMUX_MIO_OUTSEL_48_OUT_48_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_49_REG_OFFSET 0x43c
+#define PINMUX_MIO_OUTSEL_49_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_49_OUT_49_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_49_OUT_49_OFFSET 0
+#define PINMUX_MIO_OUTSEL_49_OUT_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_49_OUT_49_MASK, .index = PINMUX_MIO_OUTSEL_49_OUT_49_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_50_REG_OFFSET 0x440
+#define PINMUX_MIO_OUTSEL_50_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_50_OUT_50_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_50_OUT_50_OFFSET 0
+#define PINMUX_MIO_OUTSEL_50_OUT_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_50_OUT_50_MASK, .index = PINMUX_MIO_OUTSEL_50_OUT_50_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_51_REG_OFFSET 0x444
+#define PINMUX_MIO_OUTSEL_51_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_51_OUT_51_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_51_OUT_51_OFFSET 0
+#define PINMUX_MIO_OUTSEL_51_OUT_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_51_OUT_51_MASK, .index = PINMUX_MIO_OUTSEL_51_OUT_51_OFFSET })
+
+// For each muxable pad, this selects the peripheral output.
+#define PINMUX_MIO_OUTSEL_52_REG_OFFSET 0x448
+#define PINMUX_MIO_OUTSEL_52_REG_RESVAL 0x2
+#define PINMUX_MIO_OUTSEL_52_OUT_52_MASK 0x7f
+#define PINMUX_MIO_OUTSEL_52_OUT_52_OFFSET 0
+#define PINMUX_MIO_OUTSEL_52_OUT_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_52_OUT_52_MASK, .index = PINMUX_MIO_OUTSEL_52_OUT_52_OFFSET })
+
+// Register write enable for MIO PAD attributes. (common parameters)
+#define PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x44c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x450
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x454
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x458
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x45c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x460
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x464
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x468
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x46c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x470
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x474
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x478
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x47c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x480
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x484
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x488
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_OFFSET 0x48c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_OFFSET 0x490
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_OFFSET 0x494
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_OFFSET 0x498
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_OFFSET 0x49c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_OFFSET 0x4a0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_OFFSET 0x4a4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_OFFSET 0x4a8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_OFFSET 0x4ac
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_OFFSET 0x4b0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_OFFSET 0x4b4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_OFFSET 0x4b8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_OFFSET 0x4bc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_OFFSET 0x4c0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_OFFSET 0x4c4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_OFFSET 0x4c8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_OFFSET 0x4cc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_OFFSET 0x4d0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_OFFSET 0x4d4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_OFFSET 0x4d8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_OFFSET 0x4dc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_OFFSET 0x4e0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_OFFSET 0x4e4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_OFFSET 0x4e8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_OFFSET 0x4ec
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_OFFSET 0x4f0
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_OFFSET 0x4f4
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_OFFSET 0x4f8
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_OFFSET 0x4fc
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_OFFSET 0x500
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_OFFSET 0x504
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_REG_OFFSET 0x508
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_REG_OFFSET 0x50c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_REG_OFFSET 0x510
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_REG_OFFSET 0x514
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_REG_OFFSET 0x518
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO PAD attributes.
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_REG_OFFSET 0x51c
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_ATTR_REGWEN_52_EN_52_BIT 0
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2
+#define PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4
+#define PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT 53
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_0_REG_OFFSET 0x520
+#define PINMUX_MIO_PAD_ATTR_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT 0
+#define PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1
+#define PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT 2
+#define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3
+#define PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4
+#define PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5
+#define PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT 6
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_1_REG_OFFSET 0x524
+#define PINMUX_MIO_PAD_ATTR_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT 0
+#define PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1
+#define PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT 2
+#define PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3
+#define PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4
+#define PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5
+#define PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT 6
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_2_REG_OFFSET 0x528
+#define PINMUX_MIO_PAD_ATTR_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT 0
+#define PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1
+#define PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT 2
+#define PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3
+#define PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4
+#define PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5
+#define PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT 6
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_3_REG_OFFSET 0x52c
+#define PINMUX_MIO_PAD_ATTR_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT 0
+#define PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1
+#define PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT 2
+#define PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3
+#define PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4
+#define PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5
+#define PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT 6
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_4_REG_OFFSET 0x530
+#define PINMUX_MIO_PAD_ATTR_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT 0
+#define PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1
+#define PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT 2
+#define PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3
+#define PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4
+#define PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5
+#define PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT 6
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_5_REG_OFFSET 0x534
+#define PINMUX_MIO_PAD_ATTR_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT 0
+#define PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1
+#define PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT 2
+#define PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3
+#define PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4
+#define PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5
+#define PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT 6
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_6_REG_OFFSET 0x538
+#define PINMUX_MIO_PAD_ATTR_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT 0
+#define PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1
+#define PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT 2
+#define PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3
+#define PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4
+#define PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5
+#define PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT 6
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_7_REG_OFFSET 0x53c
+#define PINMUX_MIO_PAD_ATTR_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT 0
+#define PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1
+#define PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT 2
+#define PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3
+#define PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4
+#define PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5
+#define PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT 6
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_8_REG_OFFSET 0x540
+#define PINMUX_MIO_PAD_ATTR_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT 0
+#define PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1
+#define PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT 2
+#define PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3
+#define PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4
+#define PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5
+#define PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT 6
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_9_REG_OFFSET 0x544
+#define PINMUX_MIO_PAD_ATTR_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT 0
+#define PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1
+#define PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT 2
+#define PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3
+#define PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4
+#define PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5
+#define PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT 6
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_10_REG_OFFSET 0x548
+#define PINMUX_MIO_PAD_ATTR_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT 0
+#define PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1
+#define PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT 2
+#define PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3
+#define PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4
+#define PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5
+#define PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT 6
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_11_REG_OFFSET 0x54c
+#define PINMUX_MIO_PAD_ATTR_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT 0
+#define PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1
+#define PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT 2
+#define PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3
+#define PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4
+#define PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5
+#define PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT 6
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_12_REG_OFFSET 0x550
+#define PINMUX_MIO_PAD_ATTR_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_12_INVERT_12_BIT 0
+#define PINMUX_MIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1
+#define PINMUX_MIO_PAD_ATTR_12_PULL_EN_12_BIT 2
+#define PINMUX_MIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3
+#define PINMUX_MIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4
+#define PINMUX_MIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5
+#define PINMUX_MIO_PAD_ATTR_12_OD_EN_12_BIT 6
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_MIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_13_REG_OFFSET 0x554
+#define PINMUX_MIO_PAD_ATTR_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_13_INVERT_13_BIT 0
+#define PINMUX_MIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1
+#define PINMUX_MIO_PAD_ATTR_13_PULL_EN_13_BIT 2
+#define PINMUX_MIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3
+#define PINMUX_MIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4
+#define PINMUX_MIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5
+#define PINMUX_MIO_PAD_ATTR_13_OD_EN_13_BIT 6
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_MIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_14_REG_OFFSET 0x558
+#define PINMUX_MIO_PAD_ATTR_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_14_INVERT_14_BIT 0
+#define PINMUX_MIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1
+#define PINMUX_MIO_PAD_ATTR_14_PULL_EN_14_BIT 2
+#define PINMUX_MIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3
+#define PINMUX_MIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4
+#define PINMUX_MIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5
+#define PINMUX_MIO_PAD_ATTR_14_OD_EN_14_BIT 6
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_MIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_15_REG_OFFSET 0x55c
+#define PINMUX_MIO_PAD_ATTR_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_15_INVERT_15_BIT 0
+#define PINMUX_MIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1
+#define PINMUX_MIO_PAD_ATTR_15_PULL_EN_15_BIT 2
+#define PINMUX_MIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3
+#define PINMUX_MIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4
+#define PINMUX_MIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5
+#define PINMUX_MIO_PAD_ATTR_15_OD_EN_15_BIT 6
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_MIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_16_REG_OFFSET 0x560
+#define PINMUX_MIO_PAD_ATTR_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_16_INVERT_16_BIT 0
+#define PINMUX_MIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT 1
+#define PINMUX_MIO_PAD_ATTR_16_PULL_EN_16_BIT 2
+#define PINMUX_MIO_PAD_ATTR_16_PULL_SELECT_16_BIT 3
+#define PINMUX_MIO_PAD_ATTR_16_KEEPER_EN_16_BIT 4
+#define PINMUX_MIO_PAD_ATTR_16_SCHMITT_EN_16_BIT 5
+#define PINMUX_MIO_PAD_ATTR_16_OD_EN_16_BIT 6
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK, .index = PINMUX_MIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_17_REG_OFFSET 0x564
+#define PINMUX_MIO_PAD_ATTR_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_17_INVERT_17_BIT 0
+#define PINMUX_MIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT 1
+#define PINMUX_MIO_PAD_ATTR_17_PULL_EN_17_BIT 2
+#define PINMUX_MIO_PAD_ATTR_17_PULL_SELECT_17_BIT 3
+#define PINMUX_MIO_PAD_ATTR_17_KEEPER_EN_17_BIT 4
+#define PINMUX_MIO_PAD_ATTR_17_SCHMITT_EN_17_BIT 5
+#define PINMUX_MIO_PAD_ATTR_17_OD_EN_17_BIT 6
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK, .index = PINMUX_MIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_18_REG_OFFSET 0x568
+#define PINMUX_MIO_PAD_ATTR_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_18_INVERT_18_BIT 0
+#define PINMUX_MIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT 1
+#define PINMUX_MIO_PAD_ATTR_18_PULL_EN_18_BIT 2
+#define PINMUX_MIO_PAD_ATTR_18_PULL_SELECT_18_BIT 3
+#define PINMUX_MIO_PAD_ATTR_18_KEEPER_EN_18_BIT 4
+#define PINMUX_MIO_PAD_ATTR_18_SCHMITT_EN_18_BIT 5
+#define PINMUX_MIO_PAD_ATTR_18_OD_EN_18_BIT 6
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK, .index = PINMUX_MIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_19_REG_OFFSET 0x56c
+#define PINMUX_MIO_PAD_ATTR_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_19_INVERT_19_BIT 0
+#define PINMUX_MIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT 1
+#define PINMUX_MIO_PAD_ATTR_19_PULL_EN_19_BIT 2
+#define PINMUX_MIO_PAD_ATTR_19_PULL_SELECT_19_BIT 3
+#define PINMUX_MIO_PAD_ATTR_19_KEEPER_EN_19_BIT 4
+#define PINMUX_MIO_PAD_ATTR_19_SCHMITT_EN_19_BIT 5
+#define PINMUX_MIO_PAD_ATTR_19_OD_EN_19_BIT 6
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK, .index = PINMUX_MIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_20_REG_OFFSET 0x570
+#define PINMUX_MIO_PAD_ATTR_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_20_INVERT_20_BIT 0
+#define PINMUX_MIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT 1
+#define PINMUX_MIO_PAD_ATTR_20_PULL_EN_20_BIT 2
+#define PINMUX_MIO_PAD_ATTR_20_PULL_SELECT_20_BIT 3
+#define PINMUX_MIO_PAD_ATTR_20_KEEPER_EN_20_BIT 4
+#define PINMUX_MIO_PAD_ATTR_20_SCHMITT_EN_20_BIT 5
+#define PINMUX_MIO_PAD_ATTR_20_OD_EN_20_BIT 6
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK, .index = PINMUX_MIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_21_REG_OFFSET 0x574
+#define PINMUX_MIO_PAD_ATTR_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_21_INVERT_21_BIT 0
+#define PINMUX_MIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT 1
+#define PINMUX_MIO_PAD_ATTR_21_PULL_EN_21_BIT 2
+#define PINMUX_MIO_PAD_ATTR_21_PULL_SELECT_21_BIT 3
+#define PINMUX_MIO_PAD_ATTR_21_KEEPER_EN_21_BIT 4
+#define PINMUX_MIO_PAD_ATTR_21_SCHMITT_EN_21_BIT 5
+#define PINMUX_MIO_PAD_ATTR_21_OD_EN_21_BIT 6
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK, .index = PINMUX_MIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_22_REG_OFFSET 0x578
+#define PINMUX_MIO_PAD_ATTR_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_22_INVERT_22_BIT 0
+#define PINMUX_MIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT 1
+#define PINMUX_MIO_PAD_ATTR_22_PULL_EN_22_BIT 2
+#define PINMUX_MIO_PAD_ATTR_22_PULL_SELECT_22_BIT 3
+#define PINMUX_MIO_PAD_ATTR_22_KEEPER_EN_22_BIT 4
+#define PINMUX_MIO_PAD_ATTR_22_SCHMITT_EN_22_BIT 5
+#define PINMUX_MIO_PAD_ATTR_22_OD_EN_22_BIT 6
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK, .index = PINMUX_MIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_23_REG_OFFSET 0x57c
+#define PINMUX_MIO_PAD_ATTR_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_23_INVERT_23_BIT 0
+#define PINMUX_MIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT 1
+#define PINMUX_MIO_PAD_ATTR_23_PULL_EN_23_BIT 2
+#define PINMUX_MIO_PAD_ATTR_23_PULL_SELECT_23_BIT 3
+#define PINMUX_MIO_PAD_ATTR_23_KEEPER_EN_23_BIT 4
+#define PINMUX_MIO_PAD_ATTR_23_SCHMITT_EN_23_BIT 5
+#define PINMUX_MIO_PAD_ATTR_23_OD_EN_23_BIT 6
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK, .index = PINMUX_MIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_24_REG_OFFSET 0x580
+#define PINMUX_MIO_PAD_ATTR_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_24_INVERT_24_BIT 0
+#define PINMUX_MIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT 1
+#define PINMUX_MIO_PAD_ATTR_24_PULL_EN_24_BIT 2
+#define PINMUX_MIO_PAD_ATTR_24_PULL_SELECT_24_BIT 3
+#define PINMUX_MIO_PAD_ATTR_24_KEEPER_EN_24_BIT 4
+#define PINMUX_MIO_PAD_ATTR_24_SCHMITT_EN_24_BIT 5
+#define PINMUX_MIO_PAD_ATTR_24_OD_EN_24_BIT 6
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK, .index = PINMUX_MIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_25_REG_OFFSET 0x584
+#define PINMUX_MIO_PAD_ATTR_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_25_INVERT_25_BIT 0
+#define PINMUX_MIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT 1
+#define PINMUX_MIO_PAD_ATTR_25_PULL_EN_25_BIT 2
+#define PINMUX_MIO_PAD_ATTR_25_PULL_SELECT_25_BIT 3
+#define PINMUX_MIO_PAD_ATTR_25_KEEPER_EN_25_BIT 4
+#define PINMUX_MIO_PAD_ATTR_25_SCHMITT_EN_25_BIT 5
+#define PINMUX_MIO_PAD_ATTR_25_OD_EN_25_BIT 6
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK, .index = PINMUX_MIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_26_REG_OFFSET 0x588
+#define PINMUX_MIO_PAD_ATTR_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_26_INVERT_26_BIT 0
+#define PINMUX_MIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT 1
+#define PINMUX_MIO_PAD_ATTR_26_PULL_EN_26_BIT 2
+#define PINMUX_MIO_PAD_ATTR_26_PULL_SELECT_26_BIT 3
+#define PINMUX_MIO_PAD_ATTR_26_KEEPER_EN_26_BIT 4
+#define PINMUX_MIO_PAD_ATTR_26_SCHMITT_EN_26_BIT 5
+#define PINMUX_MIO_PAD_ATTR_26_OD_EN_26_BIT 6
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK, .index = PINMUX_MIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_27_REG_OFFSET 0x58c
+#define PINMUX_MIO_PAD_ATTR_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_27_INVERT_27_BIT 0
+#define PINMUX_MIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT 1
+#define PINMUX_MIO_PAD_ATTR_27_PULL_EN_27_BIT 2
+#define PINMUX_MIO_PAD_ATTR_27_PULL_SELECT_27_BIT 3
+#define PINMUX_MIO_PAD_ATTR_27_KEEPER_EN_27_BIT 4
+#define PINMUX_MIO_PAD_ATTR_27_SCHMITT_EN_27_BIT 5
+#define PINMUX_MIO_PAD_ATTR_27_OD_EN_27_BIT 6
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK, .index = PINMUX_MIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_28_REG_OFFSET 0x590
+#define PINMUX_MIO_PAD_ATTR_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_28_INVERT_28_BIT 0
+#define PINMUX_MIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT 1
+#define PINMUX_MIO_PAD_ATTR_28_PULL_EN_28_BIT 2
+#define PINMUX_MIO_PAD_ATTR_28_PULL_SELECT_28_BIT 3
+#define PINMUX_MIO_PAD_ATTR_28_KEEPER_EN_28_BIT 4
+#define PINMUX_MIO_PAD_ATTR_28_SCHMITT_EN_28_BIT 5
+#define PINMUX_MIO_PAD_ATTR_28_OD_EN_28_BIT 6
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK, .index = PINMUX_MIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_29_REG_OFFSET 0x594
+#define PINMUX_MIO_PAD_ATTR_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_29_INVERT_29_BIT 0
+#define PINMUX_MIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT 1
+#define PINMUX_MIO_PAD_ATTR_29_PULL_EN_29_BIT 2
+#define PINMUX_MIO_PAD_ATTR_29_PULL_SELECT_29_BIT 3
+#define PINMUX_MIO_PAD_ATTR_29_KEEPER_EN_29_BIT 4
+#define PINMUX_MIO_PAD_ATTR_29_SCHMITT_EN_29_BIT 5
+#define PINMUX_MIO_PAD_ATTR_29_OD_EN_29_BIT 6
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK, .index = PINMUX_MIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_30_REG_OFFSET 0x598
+#define PINMUX_MIO_PAD_ATTR_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_30_INVERT_30_BIT 0
+#define PINMUX_MIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT 1
+#define PINMUX_MIO_PAD_ATTR_30_PULL_EN_30_BIT 2
+#define PINMUX_MIO_PAD_ATTR_30_PULL_SELECT_30_BIT 3
+#define PINMUX_MIO_PAD_ATTR_30_KEEPER_EN_30_BIT 4
+#define PINMUX_MIO_PAD_ATTR_30_SCHMITT_EN_30_BIT 5
+#define PINMUX_MIO_PAD_ATTR_30_OD_EN_30_BIT 6
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK, .index = PINMUX_MIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_31_REG_OFFSET 0x59c
+#define PINMUX_MIO_PAD_ATTR_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_31_INVERT_31_BIT 0
+#define PINMUX_MIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT 1
+#define PINMUX_MIO_PAD_ATTR_31_PULL_EN_31_BIT 2
+#define PINMUX_MIO_PAD_ATTR_31_PULL_SELECT_31_BIT 3
+#define PINMUX_MIO_PAD_ATTR_31_KEEPER_EN_31_BIT 4
+#define PINMUX_MIO_PAD_ATTR_31_SCHMITT_EN_31_BIT 5
+#define PINMUX_MIO_PAD_ATTR_31_OD_EN_31_BIT 6
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK, .index = PINMUX_MIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_32_REG_OFFSET 0x5a0
+#define PINMUX_MIO_PAD_ATTR_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_32_INVERT_32_BIT 0
+#define PINMUX_MIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT 1
+#define PINMUX_MIO_PAD_ATTR_32_PULL_EN_32_BIT 2
+#define PINMUX_MIO_PAD_ATTR_32_PULL_SELECT_32_BIT 3
+#define PINMUX_MIO_PAD_ATTR_32_KEEPER_EN_32_BIT 4
+#define PINMUX_MIO_PAD_ATTR_32_SCHMITT_EN_32_BIT 5
+#define PINMUX_MIO_PAD_ATTR_32_OD_EN_32_BIT 6
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK, .index = PINMUX_MIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_33_REG_OFFSET 0x5a4
+#define PINMUX_MIO_PAD_ATTR_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_33_INVERT_33_BIT 0
+#define PINMUX_MIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT 1
+#define PINMUX_MIO_PAD_ATTR_33_PULL_EN_33_BIT 2
+#define PINMUX_MIO_PAD_ATTR_33_PULL_SELECT_33_BIT 3
+#define PINMUX_MIO_PAD_ATTR_33_KEEPER_EN_33_BIT 4
+#define PINMUX_MIO_PAD_ATTR_33_SCHMITT_EN_33_BIT 5
+#define PINMUX_MIO_PAD_ATTR_33_OD_EN_33_BIT 6
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK, .index = PINMUX_MIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_34_REG_OFFSET 0x5a8
+#define PINMUX_MIO_PAD_ATTR_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_34_INVERT_34_BIT 0
+#define PINMUX_MIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT 1
+#define PINMUX_MIO_PAD_ATTR_34_PULL_EN_34_BIT 2
+#define PINMUX_MIO_PAD_ATTR_34_PULL_SELECT_34_BIT 3
+#define PINMUX_MIO_PAD_ATTR_34_KEEPER_EN_34_BIT 4
+#define PINMUX_MIO_PAD_ATTR_34_SCHMITT_EN_34_BIT 5
+#define PINMUX_MIO_PAD_ATTR_34_OD_EN_34_BIT 6
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK, .index = PINMUX_MIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_35_REG_OFFSET 0x5ac
+#define PINMUX_MIO_PAD_ATTR_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_35_INVERT_35_BIT 0
+#define PINMUX_MIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT 1
+#define PINMUX_MIO_PAD_ATTR_35_PULL_EN_35_BIT 2
+#define PINMUX_MIO_PAD_ATTR_35_PULL_SELECT_35_BIT 3
+#define PINMUX_MIO_PAD_ATTR_35_KEEPER_EN_35_BIT 4
+#define PINMUX_MIO_PAD_ATTR_35_SCHMITT_EN_35_BIT 5
+#define PINMUX_MIO_PAD_ATTR_35_OD_EN_35_BIT 6
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK, .index = PINMUX_MIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_36_REG_OFFSET 0x5b0
+#define PINMUX_MIO_PAD_ATTR_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_36_INVERT_36_BIT 0
+#define PINMUX_MIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT 1
+#define PINMUX_MIO_PAD_ATTR_36_PULL_EN_36_BIT 2
+#define PINMUX_MIO_PAD_ATTR_36_PULL_SELECT_36_BIT 3
+#define PINMUX_MIO_PAD_ATTR_36_KEEPER_EN_36_BIT 4
+#define PINMUX_MIO_PAD_ATTR_36_SCHMITT_EN_36_BIT 5
+#define PINMUX_MIO_PAD_ATTR_36_OD_EN_36_BIT 6
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK, .index = PINMUX_MIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_37_REG_OFFSET 0x5b4
+#define PINMUX_MIO_PAD_ATTR_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_37_INVERT_37_BIT 0
+#define PINMUX_MIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT 1
+#define PINMUX_MIO_PAD_ATTR_37_PULL_EN_37_BIT 2
+#define PINMUX_MIO_PAD_ATTR_37_PULL_SELECT_37_BIT 3
+#define PINMUX_MIO_PAD_ATTR_37_KEEPER_EN_37_BIT 4
+#define PINMUX_MIO_PAD_ATTR_37_SCHMITT_EN_37_BIT 5
+#define PINMUX_MIO_PAD_ATTR_37_OD_EN_37_BIT 6
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK, .index = PINMUX_MIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_38_REG_OFFSET 0x5b8
+#define PINMUX_MIO_PAD_ATTR_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_38_INVERT_38_BIT 0
+#define PINMUX_MIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT 1
+#define PINMUX_MIO_PAD_ATTR_38_PULL_EN_38_BIT 2
+#define PINMUX_MIO_PAD_ATTR_38_PULL_SELECT_38_BIT 3
+#define PINMUX_MIO_PAD_ATTR_38_KEEPER_EN_38_BIT 4
+#define PINMUX_MIO_PAD_ATTR_38_SCHMITT_EN_38_BIT 5
+#define PINMUX_MIO_PAD_ATTR_38_OD_EN_38_BIT 6
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK, .index = PINMUX_MIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_39_REG_OFFSET 0x5bc
+#define PINMUX_MIO_PAD_ATTR_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_39_INVERT_39_BIT 0
+#define PINMUX_MIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT 1
+#define PINMUX_MIO_PAD_ATTR_39_PULL_EN_39_BIT 2
+#define PINMUX_MIO_PAD_ATTR_39_PULL_SELECT_39_BIT 3
+#define PINMUX_MIO_PAD_ATTR_39_KEEPER_EN_39_BIT 4
+#define PINMUX_MIO_PAD_ATTR_39_SCHMITT_EN_39_BIT 5
+#define PINMUX_MIO_PAD_ATTR_39_OD_EN_39_BIT 6
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK, .index = PINMUX_MIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_40_REG_OFFSET 0x5c0
+#define PINMUX_MIO_PAD_ATTR_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_40_INVERT_40_BIT 0
+#define PINMUX_MIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT 1
+#define PINMUX_MIO_PAD_ATTR_40_PULL_EN_40_BIT 2
+#define PINMUX_MIO_PAD_ATTR_40_PULL_SELECT_40_BIT 3
+#define PINMUX_MIO_PAD_ATTR_40_KEEPER_EN_40_BIT 4
+#define PINMUX_MIO_PAD_ATTR_40_SCHMITT_EN_40_BIT 5
+#define PINMUX_MIO_PAD_ATTR_40_OD_EN_40_BIT 6
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK, .index = PINMUX_MIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_41_REG_OFFSET 0x5c4
+#define PINMUX_MIO_PAD_ATTR_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_41_INVERT_41_BIT 0
+#define PINMUX_MIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT 1
+#define PINMUX_MIO_PAD_ATTR_41_PULL_EN_41_BIT 2
+#define PINMUX_MIO_PAD_ATTR_41_PULL_SELECT_41_BIT 3
+#define PINMUX_MIO_PAD_ATTR_41_KEEPER_EN_41_BIT 4
+#define PINMUX_MIO_PAD_ATTR_41_SCHMITT_EN_41_BIT 5
+#define PINMUX_MIO_PAD_ATTR_41_OD_EN_41_BIT 6
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK, .index = PINMUX_MIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_42_REG_OFFSET 0x5c8
+#define PINMUX_MIO_PAD_ATTR_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_42_INVERT_42_BIT 0
+#define PINMUX_MIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT 1
+#define PINMUX_MIO_PAD_ATTR_42_PULL_EN_42_BIT 2
+#define PINMUX_MIO_PAD_ATTR_42_PULL_SELECT_42_BIT 3
+#define PINMUX_MIO_PAD_ATTR_42_KEEPER_EN_42_BIT 4
+#define PINMUX_MIO_PAD_ATTR_42_SCHMITT_EN_42_BIT 5
+#define PINMUX_MIO_PAD_ATTR_42_OD_EN_42_BIT 6
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK, .index = PINMUX_MIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_43_REG_OFFSET 0x5cc
+#define PINMUX_MIO_PAD_ATTR_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_43_INVERT_43_BIT 0
+#define PINMUX_MIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT 1
+#define PINMUX_MIO_PAD_ATTR_43_PULL_EN_43_BIT 2
+#define PINMUX_MIO_PAD_ATTR_43_PULL_SELECT_43_BIT 3
+#define PINMUX_MIO_PAD_ATTR_43_KEEPER_EN_43_BIT 4
+#define PINMUX_MIO_PAD_ATTR_43_SCHMITT_EN_43_BIT 5
+#define PINMUX_MIO_PAD_ATTR_43_OD_EN_43_BIT 6
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK, .index = PINMUX_MIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_44_REG_OFFSET 0x5d0
+#define PINMUX_MIO_PAD_ATTR_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_44_INVERT_44_BIT 0
+#define PINMUX_MIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT 1
+#define PINMUX_MIO_PAD_ATTR_44_PULL_EN_44_BIT 2
+#define PINMUX_MIO_PAD_ATTR_44_PULL_SELECT_44_BIT 3
+#define PINMUX_MIO_PAD_ATTR_44_KEEPER_EN_44_BIT 4
+#define PINMUX_MIO_PAD_ATTR_44_SCHMITT_EN_44_BIT 5
+#define PINMUX_MIO_PAD_ATTR_44_OD_EN_44_BIT 6
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK, .index = PINMUX_MIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_45_REG_OFFSET 0x5d4
+#define PINMUX_MIO_PAD_ATTR_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_45_INVERT_45_BIT 0
+#define PINMUX_MIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT 1
+#define PINMUX_MIO_PAD_ATTR_45_PULL_EN_45_BIT 2
+#define PINMUX_MIO_PAD_ATTR_45_PULL_SELECT_45_BIT 3
+#define PINMUX_MIO_PAD_ATTR_45_KEEPER_EN_45_BIT 4
+#define PINMUX_MIO_PAD_ATTR_45_SCHMITT_EN_45_BIT 5
+#define PINMUX_MIO_PAD_ATTR_45_OD_EN_45_BIT 6
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK, .index = PINMUX_MIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_46_REG_OFFSET 0x5d8
+#define PINMUX_MIO_PAD_ATTR_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_46_INVERT_46_BIT 0
+#define PINMUX_MIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT 1
+#define PINMUX_MIO_PAD_ATTR_46_PULL_EN_46_BIT 2
+#define PINMUX_MIO_PAD_ATTR_46_PULL_SELECT_46_BIT 3
+#define PINMUX_MIO_PAD_ATTR_46_KEEPER_EN_46_BIT 4
+#define PINMUX_MIO_PAD_ATTR_46_SCHMITT_EN_46_BIT 5
+#define PINMUX_MIO_PAD_ATTR_46_OD_EN_46_BIT 6
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK, .index = PINMUX_MIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_47_REG_OFFSET 0x5dc
+#define PINMUX_MIO_PAD_ATTR_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_47_INVERT_47_BIT 0
+#define PINMUX_MIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_BIT 1
+#define PINMUX_MIO_PAD_ATTR_47_PULL_EN_47_BIT 2
+#define PINMUX_MIO_PAD_ATTR_47_PULL_SELECT_47_BIT 3
+#define PINMUX_MIO_PAD_ATTR_47_KEEPER_EN_47_BIT 4
+#define PINMUX_MIO_PAD_ATTR_47_SCHMITT_EN_47_BIT 5
+#define PINMUX_MIO_PAD_ATTR_47_OD_EN_47_BIT 6
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_MASK, .index = PINMUX_MIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK, .index = PINMUX_MIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_48_REG_OFFSET 0x5e0
+#define PINMUX_MIO_PAD_ATTR_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_48_INVERT_48_BIT 0
+#define PINMUX_MIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_BIT 1
+#define PINMUX_MIO_PAD_ATTR_48_PULL_EN_48_BIT 2
+#define PINMUX_MIO_PAD_ATTR_48_PULL_SELECT_48_BIT 3
+#define PINMUX_MIO_PAD_ATTR_48_KEEPER_EN_48_BIT 4
+#define PINMUX_MIO_PAD_ATTR_48_SCHMITT_EN_48_BIT 5
+#define PINMUX_MIO_PAD_ATTR_48_OD_EN_48_BIT 6
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_MASK, .index = PINMUX_MIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK, .index = PINMUX_MIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_49_REG_OFFSET 0x5e4
+#define PINMUX_MIO_PAD_ATTR_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_49_INVERT_49_BIT 0
+#define PINMUX_MIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_BIT 1
+#define PINMUX_MIO_PAD_ATTR_49_PULL_EN_49_BIT 2
+#define PINMUX_MIO_PAD_ATTR_49_PULL_SELECT_49_BIT 3
+#define PINMUX_MIO_PAD_ATTR_49_KEEPER_EN_49_BIT 4
+#define PINMUX_MIO_PAD_ATTR_49_SCHMITT_EN_49_BIT 5
+#define PINMUX_MIO_PAD_ATTR_49_OD_EN_49_BIT 6
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_MASK, .index = PINMUX_MIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK, .index = PINMUX_MIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_50_REG_OFFSET 0x5e8
+#define PINMUX_MIO_PAD_ATTR_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_50_INVERT_50_BIT 0
+#define PINMUX_MIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_BIT 1
+#define PINMUX_MIO_PAD_ATTR_50_PULL_EN_50_BIT 2
+#define PINMUX_MIO_PAD_ATTR_50_PULL_SELECT_50_BIT 3
+#define PINMUX_MIO_PAD_ATTR_50_KEEPER_EN_50_BIT 4
+#define PINMUX_MIO_PAD_ATTR_50_SCHMITT_EN_50_BIT 5
+#define PINMUX_MIO_PAD_ATTR_50_OD_EN_50_BIT 6
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_MASK, .index = PINMUX_MIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK, .index = PINMUX_MIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_51_REG_OFFSET 0x5ec
+#define PINMUX_MIO_PAD_ATTR_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_51_INVERT_51_BIT 0
+#define PINMUX_MIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_BIT 1
+#define PINMUX_MIO_PAD_ATTR_51_PULL_EN_51_BIT 2
+#define PINMUX_MIO_PAD_ATTR_51_PULL_SELECT_51_BIT 3
+#define PINMUX_MIO_PAD_ATTR_51_KEEPER_EN_51_BIT 4
+#define PINMUX_MIO_PAD_ATTR_51_SCHMITT_EN_51_BIT 5
+#define PINMUX_MIO_PAD_ATTR_51_OD_EN_51_BIT 6
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_MASK, .index = PINMUX_MIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK, .index = PINMUX_MIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET })
+
+// Muxed pad attributes.
+#define PINMUX_MIO_PAD_ATTR_52_REG_OFFSET 0x5f0
+#define PINMUX_MIO_PAD_ATTR_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_ATTR_52_INVERT_52_BIT 0
+#define PINMUX_MIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_BIT 1
+#define PINMUX_MIO_PAD_ATTR_52_PULL_EN_52_BIT 2
+#define PINMUX_MIO_PAD_ATTR_52_PULL_SELECT_52_BIT 3
+#define PINMUX_MIO_PAD_ATTR_52_KEEPER_EN_52_BIT 4
+#define PINMUX_MIO_PAD_ATTR_52_SCHMITT_EN_52_BIT 5
+#define PINMUX_MIO_PAD_ATTR_52_OD_EN_52_BIT 6
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_MASK 0x3
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET 16
+#define PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_MASK, .index = PINMUX_MIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET })
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK 0xf
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET 20
+#define PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK, .index = PINMUX_MIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET })
+
+// Register write enable for DIO PAD attributes. (common parameters)
+#define PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 16
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x5f4
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x5f8
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x5fc
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x600
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x604
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x608
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x60c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x610
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x614
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x618
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x61c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x620
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x624
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x628
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x62c
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for DIO PAD attributes.
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x630
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2
+#define PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4
+#define PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT 16
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_0_REG_OFFSET 0x634
+#define PINMUX_DIO_PAD_ATTR_0_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT 0
+#define PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1
+#define PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT 2
+#define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3
+#define PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4
+#define PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5
+#define PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT 6
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_1_REG_OFFSET 0x638
+#define PINMUX_DIO_PAD_ATTR_1_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT 0
+#define PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1
+#define PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT 2
+#define PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3
+#define PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4
+#define PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5
+#define PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT 6
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_2_REG_OFFSET 0x63c
+#define PINMUX_DIO_PAD_ATTR_2_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT 0
+#define PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1
+#define PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT 2
+#define PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3
+#define PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4
+#define PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5
+#define PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT 6
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_3_REG_OFFSET 0x640
+#define PINMUX_DIO_PAD_ATTR_3_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT 0
+#define PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1
+#define PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT 2
+#define PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3
+#define PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4
+#define PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5
+#define PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT 6
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_4_REG_OFFSET 0x644
+#define PINMUX_DIO_PAD_ATTR_4_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT 0
+#define PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1
+#define PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT 2
+#define PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3
+#define PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4
+#define PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5
+#define PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT 6
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_5_REG_OFFSET 0x648
+#define PINMUX_DIO_PAD_ATTR_5_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT 0
+#define PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1
+#define PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT 2
+#define PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3
+#define PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4
+#define PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5
+#define PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT 6
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_6_REG_OFFSET 0x64c
+#define PINMUX_DIO_PAD_ATTR_6_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT 0
+#define PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1
+#define PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT 2
+#define PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3
+#define PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4
+#define PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5
+#define PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT 6
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_7_REG_OFFSET 0x650
+#define PINMUX_DIO_PAD_ATTR_7_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT 0
+#define PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1
+#define PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT 2
+#define PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3
+#define PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4
+#define PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5
+#define PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT 6
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_8_REG_OFFSET 0x654
+#define PINMUX_DIO_PAD_ATTR_8_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT 0
+#define PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1
+#define PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT 2
+#define PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3
+#define PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4
+#define PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5
+#define PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT 6
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_9_REG_OFFSET 0x658
+#define PINMUX_DIO_PAD_ATTR_9_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT 0
+#define PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1
+#define PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT 2
+#define PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3
+#define PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4
+#define PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5
+#define PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT 6
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_10_REG_OFFSET 0x65c
+#define PINMUX_DIO_PAD_ATTR_10_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT 0
+#define PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1
+#define PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT 2
+#define PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3
+#define PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4
+#define PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5
+#define PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT 6
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_11_REG_OFFSET 0x660
+#define PINMUX_DIO_PAD_ATTR_11_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT 0
+#define PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1
+#define PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT 2
+#define PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3
+#define PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4
+#define PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5
+#define PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT 6
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_12_REG_OFFSET 0x664
+#define PINMUX_DIO_PAD_ATTR_12_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT 0
+#define PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1
+#define PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT 2
+#define PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3
+#define PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4
+#define PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5
+#define PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT 6
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_13_REG_OFFSET 0x668
+#define PINMUX_DIO_PAD_ATTR_13_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT 0
+#define PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1
+#define PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT 2
+#define PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3
+#define PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4
+#define PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5
+#define PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT 6
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_14_REG_OFFSET 0x66c
+#define PINMUX_DIO_PAD_ATTR_14_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT 0
+#define PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1
+#define PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT 2
+#define PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3
+#define PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4
+#define PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5
+#define PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT 6
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })
+
+// Dedicated pad attributes.
+#define PINMUX_DIO_PAD_ATTR_15_REG_OFFSET 0x670
+#define PINMUX_DIO_PAD_ATTR_15_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT 0
+#define PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1
+#define PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT 2
+#define PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3
+#define PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4
+#define PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5
+#define PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT 6
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16
+#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xf
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20
+#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })
+
+// Register indicating whether the corresponding pad is in sleep mode.
+// (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 2
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET 0x674
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_0_BIT 0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_1_BIT 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_2_BIT 2
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_3_BIT 3
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_4_BIT 4
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_5_BIT 5
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_6_BIT 6
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_7_BIT 7
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_8_BIT 8
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_9_BIT 9
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_10_BIT 10
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_11_BIT 11
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_12_BIT 12
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_13_BIT 13
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_14_BIT 14
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_15_BIT 15
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_16_BIT 16
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_17_BIT 17
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_18_BIT 18
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_19_BIT 19
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_20_BIT 20
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_21_BIT 21
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_22_BIT 22
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_23_BIT 23
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_24_BIT 24
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_25_BIT 25
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_26_BIT 26
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_27_BIT 27
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_28_BIT 28
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_29_BIT 29
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_30_BIT 30
+#define PINMUX_MIO_PAD_SLEEP_STATUS_0_EN_31_BIT 31
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_OFFSET 0x678
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_32_BIT 0
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_33_BIT 1
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_34_BIT 2
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_35_BIT 3
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_36_BIT 4
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_37_BIT 5
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_38_BIT 6
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_39_BIT 7
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_40_BIT 8
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_41_BIT 9
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_42_BIT 10
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_43_BIT 11
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_44_BIT 12
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_45_BIT 13
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_46_BIT 14
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_47_BIT 15
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_48_BIT 16
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_49_BIT 17
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_50_BIT 18
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_51_BIT 19
+#define PINMUX_MIO_PAD_SLEEP_STATUS_1_EN_52_BIT 20
+
+// Register write enable for MIO sleep value configuration. (common
+// parameters)
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 53
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x67c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x680
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x684
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x688
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x68c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x690
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x694
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x698
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x69c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x6a0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x6a4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x6a8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x6ac
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x6b0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x6b4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x6b8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_OFFSET 0x6bc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_16_EN_16_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_OFFSET 0x6c0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_17_EN_17_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_OFFSET 0x6c4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_18_EN_18_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_OFFSET 0x6c8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_19_EN_19_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_OFFSET 0x6cc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_20_EN_20_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_OFFSET 0x6d0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_21_EN_21_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_OFFSET 0x6d4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_22_EN_22_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_OFFSET 0x6d8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_23_EN_23_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_OFFSET 0x6dc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_24_EN_24_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_OFFSET 0x6e0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_25_EN_25_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_OFFSET 0x6e4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_26_EN_26_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_OFFSET 0x6e8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_27_EN_27_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_OFFSET 0x6ec
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_28_EN_28_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_OFFSET 0x6f0
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_29_EN_29_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_OFFSET 0x6f4
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_30_EN_30_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_OFFSET 0x6f8
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_31_EN_31_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_OFFSET 0x6fc
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_32_EN_32_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_OFFSET 0x700
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_33_EN_33_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_OFFSET 0x704
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_34_EN_34_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_OFFSET 0x708
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_35_EN_35_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_OFFSET 0x70c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_36_EN_36_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_OFFSET 0x710
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_37_EN_37_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_OFFSET 0x714
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_38_EN_38_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_OFFSET 0x718
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_39_EN_39_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_OFFSET 0x71c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_40_EN_40_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_OFFSET 0x720
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_41_EN_41_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_OFFSET 0x724
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_42_EN_42_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_OFFSET 0x728
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_43_EN_43_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_OFFSET 0x72c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_44_EN_44_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_OFFSET 0x730
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_45_EN_45_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_OFFSET 0x734
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_46_EN_46_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_REG_OFFSET 0x738
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_47_EN_47_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_REG_OFFSET 0x73c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_48_EN_48_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_REG_OFFSET 0x740
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_49_EN_49_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_REG_OFFSET 0x744
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_50_EN_50_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_REG_OFFSET 0x748
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_51_EN_51_BIT 0
+
+// Register write enable for MIO sleep value configuration.
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_REG_OFFSET 0x74c
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_REG_RESVAL 0x1
+#define PINMUX_MIO_PAD_SLEEP_REGWEN_52_EN_52_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad. (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1
+#define PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT 53
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET 0x750
+#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET 0x754
+#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET 0x758
+#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET 0x75c
+#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET 0x760
+#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET 0x764
+#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET 0x768
+#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET 0x76c
+#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET 0x770
+#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET 0x774
+#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET 0x778
+#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET 0x77c
+#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_12_REG_OFFSET 0x780
+#define PINMUX_MIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_12_EN_12_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_13_REG_OFFSET 0x784
+#define PINMUX_MIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_13_EN_13_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_14_REG_OFFSET 0x788
+#define PINMUX_MIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_14_EN_14_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_15_REG_OFFSET 0x78c
+#define PINMUX_MIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_15_EN_15_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_16_REG_OFFSET 0x790
+#define PINMUX_MIO_PAD_SLEEP_EN_16_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_16_EN_16_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_17_REG_OFFSET 0x794
+#define PINMUX_MIO_PAD_SLEEP_EN_17_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_17_EN_17_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_18_REG_OFFSET 0x798
+#define PINMUX_MIO_PAD_SLEEP_EN_18_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_18_EN_18_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_19_REG_OFFSET 0x79c
+#define PINMUX_MIO_PAD_SLEEP_EN_19_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_19_EN_19_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_20_REG_OFFSET 0x7a0
+#define PINMUX_MIO_PAD_SLEEP_EN_20_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_20_EN_20_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_21_REG_OFFSET 0x7a4
+#define PINMUX_MIO_PAD_SLEEP_EN_21_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_21_EN_21_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_22_REG_OFFSET 0x7a8
+#define PINMUX_MIO_PAD_SLEEP_EN_22_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_22_EN_22_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_23_REG_OFFSET 0x7ac
+#define PINMUX_MIO_PAD_SLEEP_EN_23_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_23_EN_23_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_24_REG_OFFSET 0x7b0
+#define PINMUX_MIO_PAD_SLEEP_EN_24_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_24_EN_24_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_25_REG_OFFSET 0x7b4
+#define PINMUX_MIO_PAD_SLEEP_EN_25_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_25_EN_25_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_26_REG_OFFSET 0x7b8
+#define PINMUX_MIO_PAD_SLEEP_EN_26_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_26_EN_26_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_27_REG_OFFSET 0x7bc
+#define PINMUX_MIO_PAD_SLEEP_EN_27_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_27_EN_27_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_28_REG_OFFSET 0x7c0
+#define PINMUX_MIO_PAD_SLEEP_EN_28_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_28_EN_28_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_29_REG_OFFSET 0x7c4
+#define PINMUX_MIO_PAD_SLEEP_EN_29_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_29_EN_29_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_30_REG_OFFSET 0x7c8
+#define PINMUX_MIO_PAD_SLEEP_EN_30_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_30_EN_30_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_31_REG_OFFSET 0x7cc
+#define PINMUX_MIO_PAD_SLEEP_EN_31_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_31_EN_31_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_32_REG_OFFSET 0x7d0
+#define PINMUX_MIO_PAD_SLEEP_EN_32_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_32_EN_32_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_33_REG_OFFSET 0x7d4
+#define PINMUX_MIO_PAD_SLEEP_EN_33_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_33_EN_33_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_34_REG_OFFSET 0x7d8
+#define PINMUX_MIO_PAD_SLEEP_EN_34_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_34_EN_34_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_35_REG_OFFSET 0x7dc
+#define PINMUX_MIO_PAD_SLEEP_EN_35_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_35_EN_35_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_36_REG_OFFSET 0x7e0
+#define PINMUX_MIO_PAD_SLEEP_EN_36_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_36_EN_36_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_37_REG_OFFSET 0x7e4
+#define PINMUX_MIO_PAD_SLEEP_EN_37_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_37_EN_37_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_38_REG_OFFSET 0x7e8
+#define PINMUX_MIO_PAD_SLEEP_EN_38_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_38_EN_38_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_39_REG_OFFSET 0x7ec
+#define PINMUX_MIO_PAD_SLEEP_EN_39_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_39_EN_39_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_40_REG_OFFSET 0x7f0
+#define PINMUX_MIO_PAD_SLEEP_EN_40_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_40_EN_40_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_41_REG_OFFSET 0x7f4
+#define PINMUX_MIO_PAD_SLEEP_EN_41_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_41_EN_41_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_42_REG_OFFSET 0x7f8
+#define PINMUX_MIO_PAD_SLEEP_EN_42_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_42_EN_42_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_43_REG_OFFSET 0x7fc
+#define PINMUX_MIO_PAD_SLEEP_EN_43_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_43_EN_43_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_44_REG_OFFSET 0x800
+#define PINMUX_MIO_PAD_SLEEP_EN_44_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_44_EN_44_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_45_REG_OFFSET 0x804
+#define PINMUX_MIO_PAD_SLEEP_EN_45_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_45_EN_45_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_46_REG_OFFSET 0x808
+#define PINMUX_MIO_PAD_SLEEP_EN_46_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_46_EN_46_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_47_REG_OFFSET 0x80c
+#define PINMUX_MIO_PAD_SLEEP_EN_47_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_47_EN_47_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_48_REG_OFFSET 0x810
+#define PINMUX_MIO_PAD_SLEEP_EN_48_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_48_EN_48_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_49_REG_OFFSET 0x814
+#define PINMUX_MIO_PAD_SLEEP_EN_49_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_49_EN_49_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_50_REG_OFFSET 0x818
+#define PINMUX_MIO_PAD_SLEEP_EN_50_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_50_EN_50_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_51_REG_OFFSET 0x81c
+#define PINMUX_MIO_PAD_SLEEP_EN_51_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_51_EN_51_BIT 0
+
+// Enables the sleep mode of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_EN_52_REG_OFFSET 0x820
+#define PINMUX_MIO_PAD_SLEEP_EN_52_REG_RESVAL 0x0
+#define PINMUX_MIO_PAD_SLEEP_EN_52_EN_52_BIT 0
+
+// Defines sleep behavior of the corresponding muxed pad. (common parameters)
+#define PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2
+#define PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT 53
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x824
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x828
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x82c
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x830
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x834
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x838
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x83c
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x840
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x844
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x848
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x84c
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x850
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x854
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x858
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x85c
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x860
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_OFFSET 0x864
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_OFFSET 0x868
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_OFFSET 0x86c
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_OFFSET 0x870
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_OFFSET 0x874
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_OFFSET 0x878
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_OFFSET 0x87c
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_OFFSET 0x880
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_OFFSET 0x884
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_OFFSET 0x888
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_OFFSET 0x88c
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_OFFSET 0x890
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_OFFSET 0x894
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_OFFSET 0x898
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_OFFSET 0x89c
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_OFFSET 0x8a0
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_OFFSET 0x8a4
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_OFFSET 0x8a8
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_OFFSET 0x8ac
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_OFFSET 0x8b0
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_OFFSET 0x8b4
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_OFFSET 0x8b8
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_OFFSET 0x8bc
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_OFFSET 0x8c0
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_OFFSET 0x8c4
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_OFFSET 0x8c8
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_OFFSET 0x8cc
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_OFFSET 0x8d0
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_OFFSET 0x8d4
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_OFFSET 0x8d8
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_OFFSET 0x8dc
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_REG_OFFSET 0x8e0
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_REG_OFFSET 0x8e4
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_REG_OFFSET 0x8e8
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_REG_OFFSET 0x8ec
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_REG_OFFSET 0x8f0
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET })
+
+// Defines sleep behavior of the corresponding muxed pad.
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_REG_OFFSET 0x8f4
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_REG_RESVAL 0x2
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_MASK 0x3
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET 0
+#define PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET })
+
+// Register indicating whether the corresponding pad is in sleep mode.
+// (common parameters)
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 1
+
+// Register indicating whether the corresponding pad is in sleep mode.
+#define PINMUX_DIO_PAD_SLEEP_STATUS_REG_OFFSET 0x8f8
+#define PINMUX_DIO_PAD_SLEEP_STATUS_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_0_BIT 0
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_1_BIT 1
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_2_BIT 2
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_3_BIT 3
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_4_BIT 4
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_5_BIT 5
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_6_BIT 6
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_7_BIT 7
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_8_BIT 8
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_9_BIT 9
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_10_BIT 10
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_11_BIT 11
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_12_BIT 12
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_13_BIT 13
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_14_BIT 14
+#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_15_BIT 15
+
+// Register write enable for DIO sleep value configuration. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 16
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x8fc
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x900
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x904
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x908
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x90c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x910
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x914
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x918
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x91c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x920
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x924
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x928
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x92c
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x930
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x934
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0
+
+// Register write enable for DIO sleep value configuration.
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x938
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1
+#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1
+#define PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT 16
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET 0x93c
+#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET 0x940
+#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET 0x944
+#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET 0x948
+#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET 0x94c
+#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET 0x950
+#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET 0x954
+#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET 0x958
+#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET 0x95c
+#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET 0x960
+#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET 0x964
+#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET 0x968
+#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET 0x96c
+#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET 0x970
+#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET 0x974
+#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT 0
+
+// Enables the sleep mode of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET 0x978
+#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0
+#define PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT 0
+
+// Defines sleep behavior of the corresponding dedicated pad. (common
+// parameters)
+#define PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2
+#define PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT 16
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x97c
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x980
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x984
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x988
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x98c
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x990
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x994
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x998
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x99c
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x9a0
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x9a4
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x9a8
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x9ac
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x9b0
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x9b4
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })
+
+// Defines sleep behavior of the corresponding dedicated pad.
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x9b8
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0
+#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })
+
+// Register write enable for wakeup detectors. (common parameters)
+#define PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT 8
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET 0x9bc
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET 0x9c0
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET 0x9c4
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET 0x9c8
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET 0x9cc
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET 0x9d0
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET 0x9d4
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT 0
+
+// Register write enable for wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET 0x9d8
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL 0x1
+#define PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT 8
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET 0x9dc
+#define PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET 0x9e0
+#define PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET 0x9e4
+#define PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET 0x9e8
+#define PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET 0x9ec
+#define PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET 0x9f0
+#define PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET 0x9f4
+#define PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT 0
+
+// Enables for the wakeup detectors.
+#define PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET 0x9f8
+#define PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT 0
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH 3
+#define PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH 1
+#define PINMUX_WKUP_DETECTOR_MULTIREG_COUNT 8
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_0_REG_OFFSET 0x9fc
+#define PINMUX_WKUP_DETECTOR_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_0_MODE_0_MASK, .index = PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET })
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE 0x0
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE 0x1
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE 0x2
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH 0x3
+#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW 0x4
+#define PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT 3
+#define PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_1_REG_OFFSET 0xa00
+#define PINMUX_WKUP_DETECTOR_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_1_MODE_1_MASK, .index = PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET })
+#define PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT 3
+#define PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_2_REG_OFFSET 0xa04
+#define PINMUX_WKUP_DETECTOR_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_2_MODE_2_MASK, .index = PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET })
+#define PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT 3
+#define PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_3_REG_OFFSET 0xa08
+#define PINMUX_WKUP_DETECTOR_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_3_MODE_3_MASK, .index = PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET })
+#define PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT 3
+#define PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_4_REG_OFFSET 0xa0c
+#define PINMUX_WKUP_DETECTOR_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_4_MODE_4_MASK, .index = PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET })
+#define PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT 3
+#define PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_5_REG_OFFSET 0xa10
+#define PINMUX_WKUP_DETECTOR_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_5_MODE_5_MASK, .index = PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET })
+#define PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT 3
+#define PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_6_REG_OFFSET 0xa14
+#define PINMUX_WKUP_DETECTOR_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_6_MODE_6_MASK, .index = PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET })
+#define PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT 3
+#define PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT 4
+
+// Configuration of wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_7_REG_OFFSET 0xa18
+#define PINMUX_WKUP_DETECTOR_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_MASK 0x7
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_7_MODE_7_MASK, .index = PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET })
+#define PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT 3
+#define PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT 4
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH 8
+#define PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT 8
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET 0xa1c
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET 0xa20
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET 0xa24
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET 0xa28
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET 0xa2c
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET 0xa30
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET 0xa34
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET })
+
+// Counter thresholds for wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET 0xa38
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK 0xff
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH 6
+#define PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT 8
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET 0xa3c
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET 0xa40
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET 0xa44
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET 0xa48
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET 0xa4c
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET 0xa50
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET 0xa54
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET })
+
+// Pad selects for pad wakeup condition detectors.
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET 0xa58
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL 0x0
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK 0x3f
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET 0
+#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD \
+ ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET })
+
+// Cause registers for wakeup detectors.
+#define PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH 1
+#define PINMUX_WKUP_CAUSE_MULTIREG_COUNT 1
+
+// Cause registers for wakeup detectors.
+#define PINMUX_WKUP_CAUSE_REG_OFFSET 0xa5c
+#define PINMUX_WKUP_CAUSE_REG_RESVAL 0x0
+#define PINMUX_WKUP_CAUSE_CAUSE_0_BIT 0
+#define PINMUX_WKUP_CAUSE_CAUSE_1_BIT 1
+#define PINMUX_WKUP_CAUSE_CAUSE_2_BIT 2
+#define PINMUX_WKUP_CAUSE_CAUSE_3_BIT 3
+#define PINMUX_WKUP_CAUSE_CAUSE_4_BIT 4
+#define PINMUX_WKUP_CAUSE_CAUSE_5_BIT 5
+#define PINMUX_WKUP_CAUSE_CAUSE_6_BIT 6
+#define PINMUX_WKUP_CAUSE_CAUSE_7_BIT 7
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _PINMUX_REG_DEFS_
+// End generated register defines for pinmux
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_regs.h
new file mode 100644
index 0000000..365bfbf
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_regs.h
@@ -0,0 +1,2256 @@
+// Generated register defines for rv_plic
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _RV_PLIC_REG_DEFS_
+#define _RV_PLIC_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of interrupt sources
+#define RV_PLIC_PARAM_NUM_SRC 190
+
+// Number of Targets (Harts)
+#define RV_PLIC_PARAM_NUM_TARGET 2
+
+// Width of priority signals
+#define RV_PLIC_PARAM_PRIO_WIDTH 2
+
+// Number of alerts
+#define RV_PLIC_PARAM_NUM_ALERTS 1
+
+// Register width
+#define RV_PLIC_PARAM_REG_WIDTH 32
+
+// Interrupt Source 0 Priority
+#define RV_PLIC_PRIO0_REG_OFFSET 0x0
+#define RV_PLIC_PRIO0_REG_RESVAL 0x0
+#define RV_PLIC_PRIO0_PRIO0_MASK 0x3
+#define RV_PLIC_PRIO0_PRIO0_OFFSET 0
+#define RV_PLIC_PRIO0_PRIO0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO0_PRIO0_MASK, .index = RV_PLIC_PRIO0_PRIO0_OFFSET })
+
+// Interrupt Source 1 Priority
+#define RV_PLIC_PRIO1_REG_OFFSET 0x4
+#define RV_PLIC_PRIO1_REG_RESVAL 0x0
+#define RV_PLIC_PRIO1_PRIO1_MASK 0x3
+#define RV_PLIC_PRIO1_PRIO1_OFFSET 0
+#define RV_PLIC_PRIO1_PRIO1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO1_PRIO1_MASK, .index = RV_PLIC_PRIO1_PRIO1_OFFSET })
+
+// Interrupt Source 2 Priority
+#define RV_PLIC_PRIO2_REG_OFFSET 0x8
+#define RV_PLIC_PRIO2_REG_RESVAL 0x0
+#define RV_PLIC_PRIO2_PRIO2_MASK 0x3
+#define RV_PLIC_PRIO2_PRIO2_OFFSET 0
+#define RV_PLIC_PRIO2_PRIO2_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO2_PRIO2_MASK, .index = RV_PLIC_PRIO2_PRIO2_OFFSET })
+
+// Interrupt Source 3 Priority
+#define RV_PLIC_PRIO3_REG_OFFSET 0xc
+#define RV_PLIC_PRIO3_REG_RESVAL 0x0
+#define RV_PLIC_PRIO3_PRIO3_MASK 0x3
+#define RV_PLIC_PRIO3_PRIO3_OFFSET 0
+#define RV_PLIC_PRIO3_PRIO3_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO3_PRIO3_MASK, .index = RV_PLIC_PRIO3_PRIO3_OFFSET })
+
+// Interrupt Source 4 Priority
+#define RV_PLIC_PRIO4_REG_OFFSET 0x10
+#define RV_PLIC_PRIO4_REG_RESVAL 0x0
+#define RV_PLIC_PRIO4_PRIO4_MASK 0x3
+#define RV_PLIC_PRIO4_PRIO4_OFFSET 0
+#define RV_PLIC_PRIO4_PRIO4_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO4_PRIO4_MASK, .index = RV_PLIC_PRIO4_PRIO4_OFFSET })
+
+// Interrupt Source 5 Priority
+#define RV_PLIC_PRIO5_REG_OFFSET 0x14
+#define RV_PLIC_PRIO5_REG_RESVAL 0x0
+#define RV_PLIC_PRIO5_PRIO5_MASK 0x3
+#define RV_PLIC_PRIO5_PRIO5_OFFSET 0
+#define RV_PLIC_PRIO5_PRIO5_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO5_PRIO5_MASK, .index = RV_PLIC_PRIO5_PRIO5_OFFSET })
+
+// Interrupt Source 6 Priority
+#define RV_PLIC_PRIO6_REG_OFFSET 0x18
+#define RV_PLIC_PRIO6_REG_RESVAL 0x0
+#define RV_PLIC_PRIO6_PRIO6_MASK 0x3
+#define RV_PLIC_PRIO6_PRIO6_OFFSET 0
+#define RV_PLIC_PRIO6_PRIO6_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO6_PRIO6_MASK, .index = RV_PLIC_PRIO6_PRIO6_OFFSET })
+
+// Interrupt Source 7 Priority
+#define RV_PLIC_PRIO7_REG_OFFSET 0x1c
+#define RV_PLIC_PRIO7_REG_RESVAL 0x0
+#define RV_PLIC_PRIO7_PRIO7_MASK 0x3
+#define RV_PLIC_PRIO7_PRIO7_OFFSET 0
+#define RV_PLIC_PRIO7_PRIO7_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO7_PRIO7_MASK, .index = RV_PLIC_PRIO7_PRIO7_OFFSET })
+
+// Interrupt Source 8 Priority
+#define RV_PLIC_PRIO8_REG_OFFSET 0x20
+#define RV_PLIC_PRIO8_REG_RESVAL 0x0
+#define RV_PLIC_PRIO8_PRIO8_MASK 0x3
+#define RV_PLIC_PRIO8_PRIO8_OFFSET 0
+#define RV_PLIC_PRIO8_PRIO8_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO8_PRIO8_MASK, .index = RV_PLIC_PRIO8_PRIO8_OFFSET })
+
+// Interrupt Source 9 Priority
+#define RV_PLIC_PRIO9_REG_OFFSET 0x24
+#define RV_PLIC_PRIO9_REG_RESVAL 0x0
+#define RV_PLIC_PRIO9_PRIO9_MASK 0x3
+#define RV_PLIC_PRIO9_PRIO9_OFFSET 0
+#define RV_PLIC_PRIO9_PRIO9_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO9_PRIO9_MASK, .index = RV_PLIC_PRIO9_PRIO9_OFFSET })
+
+// Interrupt Source 10 Priority
+#define RV_PLIC_PRIO10_REG_OFFSET 0x28
+#define RV_PLIC_PRIO10_REG_RESVAL 0x0
+#define RV_PLIC_PRIO10_PRIO10_MASK 0x3
+#define RV_PLIC_PRIO10_PRIO10_OFFSET 0
+#define RV_PLIC_PRIO10_PRIO10_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO10_PRIO10_MASK, .index = RV_PLIC_PRIO10_PRIO10_OFFSET })
+
+// Interrupt Source 11 Priority
+#define RV_PLIC_PRIO11_REG_OFFSET 0x2c
+#define RV_PLIC_PRIO11_REG_RESVAL 0x0
+#define RV_PLIC_PRIO11_PRIO11_MASK 0x3
+#define RV_PLIC_PRIO11_PRIO11_OFFSET 0
+#define RV_PLIC_PRIO11_PRIO11_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO11_PRIO11_MASK, .index = RV_PLIC_PRIO11_PRIO11_OFFSET })
+
+// Interrupt Source 12 Priority
+#define RV_PLIC_PRIO12_REG_OFFSET 0x30
+#define RV_PLIC_PRIO12_REG_RESVAL 0x0
+#define RV_PLIC_PRIO12_PRIO12_MASK 0x3
+#define RV_PLIC_PRIO12_PRIO12_OFFSET 0
+#define RV_PLIC_PRIO12_PRIO12_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO12_PRIO12_MASK, .index = RV_PLIC_PRIO12_PRIO12_OFFSET })
+
+// Interrupt Source 13 Priority
+#define RV_PLIC_PRIO13_REG_OFFSET 0x34
+#define RV_PLIC_PRIO13_REG_RESVAL 0x0
+#define RV_PLIC_PRIO13_PRIO13_MASK 0x3
+#define RV_PLIC_PRIO13_PRIO13_OFFSET 0
+#define RV_PLIC_PRIO13_PRIO13_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO13_PRIO13_MASK, .index = RV_PLIC_PRIO13_PRIO13_OFFSET })
+
+// Interrupt Source 14 Priority
+#define RV_PLIC_PRIO14_REG_OFFSET 0x38
+#define RV_PLIC_PRIO14_REG_RESVAL 0x0
+#define RV_PLIC_PRIO14_PRIO14_MASK 0x3
+#define RV_PLIC_PRIO14_PRIO14_OFFSET 0
+#define RV_PLIC_PRIO14_PRIO14_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO14_PRIO14_MASK, .index = RV_PLIC_PRIO14_PRIO14_OFFSET })
+
+// Interrupt Source 15 Priority
+#define RV_PLIC_PRIO15_REG_OFFSET 0x3c
+#define RV_PLIC_PRIO15_REG_RESVAL 0x0
+#define RV_PLIC_PRIO15_PRIO15_MASK 0x3
+#define RV_PLIC_PRIO15_PRIO15_OFFSET 0
+#define RV_PLIC_PRIO15_PRIO15_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO15_PRIO15_MASK, .index = RV_PLIC_PRIO15_PRIO15_OFFSET })
+
+// Interrupt Source 16 Priority
+#define RV_PLIC_PRIO16_REG_OFFSET 0x40
+#define RV_PLIC_PRIO16_REG_RESVAL 0x0
+#define RV_PLIC_PRIO16_PRIO16_MASK 0x3
+#define RV_PLIC_PRIO16_PRIO16_OFFSET 0
+#define RV_PLIC_PRIO16_PRIO16_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO16_PRIO16_MASK, .index = RV_PLIC_PRIO16_PRIO16_OFFSET })
+
+// Interrupt Source 17 Priority
+#define RV_PLIC_PRIO17_REG_OFFSET 0x44
+#define RV_PLIC_PRIO17_REG_RESVAL 0x0
+#define RV_PLIC_PRIO17_PRIO17_MASK 0x3
+#define RV_PLIC_PRIO17_PRIO17_OFFSET 0
+#define RV_PLIC_PRIO17_PRIO17_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO17_PRIO17_MASK, .index = RV_PLIC_PRIO17_PRIO17_OFFSET })
+
+// Interrupt Source 18 Priority
+#define RV_PLIC_PRIO18_REG_OFFSET 0x48
+#define RV_PLIC_PRIO18_REG_RESVAL 0x0
+#define RV_PLIC_PRIO18_PRIO18_MASK 0x3
+#define RV_PLIC_PRIO18_PRIO18_OFFSET 0
+#define RV_PLIC_PRIO18_PRIO18_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO18_PRIO18_MASK, .index = RV_PLIC_PRIO18_PRIO18_OFFSET })
+
+// Interrupt Source 19 Priority
+#define RV_PLIC_PRIO19_REG_OFFSET 0x4c
+#define RV_PLIC_PRIO19_REG_RESVAL 0x0
+#define RV_PLIC_PRIO19_PRIO19_MASK 0x3
+#define RV_PLIC_PRIO19_PRIO19_OFFSET 0
+#define RV_PLIC_PRIO19_PRIO19_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO19_PRIO19_MASK, .index = RV_PLIC_PRIO19_PRIO19_OFFSET })
+
+// Interrupt Source 20 Priority
+#define RV_PLIC_PRIO20_REG_OFFSET 0x50
+#define RV_PLIC_PRIO20_REG_RESVAL 0x0
+#define RV_PLIC_PRIO20_PRIO20_MASK 0x3
+#define RV_PLIC_PRIO20_PRIO20_OFFSET 0
+#define RV_PLIC_PRIO20_PRIO20_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO20_PRIO20_MASK, .index = RV_PLIC_PRIO20_PRIO20_OFFSET })
+
+// Interrupt Source 21 Priority
+#define RV_PLIC_PRIO21_REG_OFFSET 0x54
+#define RV_PLIC_PRIO21_REG_RESVAL 0x0
+#define RV_PLIC_PRIO21_PRIO21_MASK 0x3
+#define RV_PLIC_PRIO21_PRIO21_OFFSET 0
+#define RV_PLIC_PRIO21_PRIO21_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO21_PRIO21_MASK, .index = RV_PLIC_PRIO21_PRIO21_OFFSET })
+
+// Interrupt Source 22 Priority
+#define RV_PLIC_PRIO22_REG_OFFSET 0x58
+#define RV_PLIC_PRIO22_REG_RESVAL 0x0
+#define RV_PLIC_PRIO22_PRIO22_MASK 0x3
+#define RV_PLIC_PRIO22_PRIO22_OFFSET 0
+#define RV_PLIC_PRIO22_PRIO22_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO22_PRIO22_MASK, .index = RV_PLIC_PRIO22_PRIO22_OFFSET })
+
+// Interrupt Source 23 Priority
+#define RV_PLIC_PRIO23_REG_OFFSET 0x5c
+#define RV_PLIC_PRIO23_REG_RESVAL 0x0
+#define RV_PLIC_PRIO23_PRIO23_MASK 0x3
+#define RV_PLIC_PRIO23_PRIO23_OFFSET 0
+#define RV_PLIC_PRIO23_PRIO23_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO23_PRIO23_MASK, .index = RV_PLIC_PRIO23_PRIO23_OFFSET })
+
+// Interrupt Source 24 Priority
+#define RV_PLIC_PRIO24_REG_OFFSET 0x60
+#define RV_PLIC_PRIO24_REG_RESVAL 0x0
+#define RV_PLIC_PRIO24_PRIO24_MASK 0x3
+#define RV_PLIC_PRIO24_PRIO24_OFFSET 0
+#define RV_PLIC_PRIO24_PRIO24_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO24_PRIO24_MASK, .index = RV_PLIC_PRIO24_PRIO24_OFFSET })
+
+// Interrupt Source 25 Priority
+#define RV_PLIC_PRIO25_REG_OFFSET 0x64
+#define RV_PLIC_PRIO25_REG_RESVAL 0x0
+#define RV_PLIC_PRIO25_PRIO25_MASK 0x3
+#define RV_PLIC_PRIO25_PRIO25_OFFSET 0
+#define RV_PLIC_PRIO25_PRIO25_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO25_PRIO25_MASK, .index = RV_PLIC_PRIO25_PRIO25_OFFSET })
+
+// Interrupt Source 26 Priority
+#define RV_PLIC_PRIO26_REG_OFFSET 0x68
+#define RV_PLIC_PRIO26_REG_RESVAL 0x0
+#define RV_PLIC_PRIO26_PRIO26_MASK 0x3
+#define RV_PLIC_PRIO26_PRIO26_OFFSET 0
+#define RV_PLIC_PRIO26_PRIO26_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO26_PRIO26_MASK, .index = RV_PLIC_PRIO26_PRIO26_OFFSET })
+
+// Interrupt Source 27 Priority
+#define RV_PLIC_PRIO27_REG_OFFSET 0x6c
+#define RV_PLIC_PRIO27_REG_RESVAL 0x0
+#define RV_PLIC_PRIO27_PRIO27_MASK 0x3
+#define RV_PLIC_PRIO27_PRIO27_OFFSET 0
+#define RV_PLIC_PRIO27_PRIO27_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO27_PRIO27_MASK, .index = RV_PLIC_PRIO27_PRIO27_OFFSET })
+
+// Interrupt Source 28 Priority
+#define RV_PLIC_PRIO28_REG_OFFSET 0x70
+#define RV_PLIC_PRIO28_REG_RESVAL 0x0
+#define RV_PLIC_PRIO28_PRIO28_MASK 0x3
+#define RV_PLIC_PRIO28_PRIO28_OFFSET 0
+#define RV_PLIC_PRIO28_PRIO28_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO28_PRIO28_MASK, .index = RV_PLIC_PRIO28_PRIO28_OFFSET })
+
+// Interrupt Source 29 Priority
+#define RV_PLIC_PRIO29_REG_OFFSET 0x74
+#define RV_PLIC_PRIO29_REG_RESVAL 0x0
+#define RV_PLIC_PRIO29_PRIO29_MASK 0x3
+#define RV_PLIC_PRIO29_PRIO29_OFFSET 0
+#define RV_PLIC_PRIO29_PRIO29_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO29_PRIO29_MASK, .index = RV_PLIC_PRIO29_PRIO29_OFFSET })
+
+// Interrupt Source 30 Priority
+#define RV_PLIC_PRIO30_REG_OFFSET 0x78
+#define RV_PLIC_PRIO30_REG_RESVAL 0x0
+#define RV_PLIC_PRIO30_PRIO30_MASK 0x3
+#define RV_PLIC_PRIO30_PRIO30_OFFSET 0
+#define RV_PLIC_PRIO30_PRIO30_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO30_PRIO30_MASK, .index = RV_PLIC_PRIO30_PRIO30_OFFSET })
+
+// Interrupt Source 31 Priority
+#define RV_PLIC_PRIO31_REG_OFFSET 0x7c
+#define RV_PLIC_PRIO31_REG_RESVAL 0x0
+#define RV_PLIC_PRIO31_PRIO31_MASK 0x3
+#define RV_PLIC_PRIO31_PRIO31_OFFSET 0
+#define RV_PLIC_PRIO31_PRIO31_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO31_PRIO31_MASK, .index = RV_PLIC_PRIO31_PRIO31_OFFSET })
+
+// Interrupt Source 32 Priority
+#define RV_PLIC_PRIO32_REG_OFFSET 0x80
+#define RV_PLIC_PRIO32_REG_RESVAL 0x0
+#define RV_PLIC_PRIO32_PRIO32_MASK 0x3
+#define RV_PLIC_PRIO32_PRIO32_OFFSET 0
+#define RV_PLIC_PRIO32_PRIO32_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO32_PRIO32_MASK, .index = RV_PLIC_PRIO32_PRIO32_OFFSET })
+
+// Interrupt Source 33 Priority
+#define RV_PLIC_PRIO33_REG_OFFSET 0x84
+#define RV_PLIC_PRIO33_REG_RESVAL 0x0
+#define RV_PLIC_PRIO33_PRIO33_MASK 0x3
+#define RV_PLIC_PRIO33_PRIO33_OFFSET 0
+#define RV_PLIC_PRIO33_PRIO33_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO33_PRIO33_MASK, .index = RV_PLIC_PRIO33_PRIO33_OFFSET })
+
+// Interrupt Source 34 Priority
+#define RV_PLIC_PRIO34_REG_OFFSET 0x88
+#define RV_PLIC_PRIO34_REG_RESVAL 0x0
+#define RV_PLIC_PRIO34_PRIO34_MASK 0x3
+#define RV_PLIC_PRIO34_PRIO34_OFFSET 0
+#define RV_PLIC_PRIO34_PRIO34_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO34_PRIO34_MASK, .index = RV_PLIC_PRIO34_PRIO34_OFFSET })
+
+// Interrupt Source 35 Priority
+#define RV_PLIC_PRIO35_REG_OFFSET 0x8c
+#define RV_PLIC_PRIO35_REG_RESVAL 0x0
+#define RV_PLIC_PRIO35_PRIO35_MASK 0x3
+#define RV_PLIC_PRIO35_PRIO35_OFFSET 0
+#define RV_PLIC_PRIO35_PRIO35_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO35_PRIO35_MASK, .index = RV_PLIC_PRIO35_PRIO35_OFFSET })
+
+// Interrupt Source 36 Priority
+#define RV_PLIC_PRIO36_REG_OFFSET 0x90
+#define RV_PLIC_PRIO36_REG_RESVAL 0x0
+#define RV_PLIC_PRIO36_PRIO36_MASK 0x3
+#define RV_PLIC_PRIO36_PRIO36_OFFSET 0
+#define RV_PLIC_PRIO36_PRIO36_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO36_PRIO36_MASK, .index = RV_PLIC_PRIO36_PRIO36_OFFSET })
+
+// Interrupt Source 37 Priority
+#define RV_PLIC_PRIO37_REG_OFFSET 0x94
+#define RV_PLIC_PRIO37_REG_RESVAL 0x0
+#define RV_PLIC_PRIO37_PRIO37_MASK 0x3
+#define RV_PLIC_PRIO37_PRIO37_OFFSET 0
+#define RV_PLIC_PRIO37_PRIO37_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO37_PRIO37_MASK, .index = RV_PLIC_PRIO37_PRIO37_OFFSET })
+
+// Interrupt Source 38 Priority
+#define RV_PLIC_PRIO38_REG_OFFSET 0x98
+#define RV_PLIC_PRIO38_REG_RESVAL 0x0
+#define RV_PLIC_PRIO38_PRIO38_MASK 0x3
+#define RV_PLIC_PRIO38_PRIO38_OFFSET 0
+#define RV_PLIC_PRIO38_PRIO38_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO38_PRIO38_MASK, .index = RV_PLIC_PRIO38_PRIO38_OFFSET })
+
+// Interrupt Source 39 Priority
+#define RV_PLIC_PRIO39_REG_OFFSET 0x9c
+#define RV_PLIC_PRIO39_REG_RESVAL 0x0
+#define RV_PLIC_PRIO39_PRIO39_MASK 0x3
+#define RV_PLIC_PRIO39_PRIO39_OFFSET 0
+#define RV_PLIC_PRIO39_PRIO39_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO39_PRIO39_MASK, .index = RV_PLIC_PRIO39_PRIO39_OFFSET })
+
+// Interrupt Source 40 Priority
+#define RV_PLIC_PRIO40_REG_OFFSET 0xa0
+#define RV_PLIC_PRIO40_REG_RESVAL 0x0
+#define RV_PLIC_PRIO40_PRIO40_MASK 0x3
+#define RV_PLIC_PRIO40_PRIO40_OFFSET 0
+#define RV_PLIC_PRIO40_PRIO40_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO40_PRIO40_MASK, .index = RV_PLIC_PRIO40_PRIO40_OFFSET })
+
+// Interrupt Source 41 Priority
+#define RV_PLIC_PRIO41_REG_OFFSET 0xa4
+#define RV_PLIC_PRIO41_REG_RESVAL 0x0
+#define RV_PLIC_PRIO41_PRIO41_MASK 0x3
+#define RV_PLIC_PRIO41_PRIO41_OFFSET 0
+#define RV_PLIC_PRIO41_PRIO41_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO41_PRIO41_MASK, .index = RV_PLIC_PRIO41_PRIO41_OFFSET })
+
+// Interrupt Source 42 Priority
+#define RV_PLIC_PRIO42_REG_OFFSET 0xa8
+#define RV_PLIC_PRIO42_REG_RESVAL 0x0
+#define RV_PLIC_PRIO42_PRIO42_MASK 0x3
+#define RV_PLIC_PRIO42_PRIO42_OFFSET 0
+#define RV_PLIC_PRIO42_PRIO42_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO42_PRIO42_MASK, .index = RV_PLIC_PRIO42_PRIO42_OFFSET })
+
+// Interrupt Source 43 Priority
+#define RV_PLIC_PRIO43_REG_OFFSET 0xac
+#define RV_PLIC_PRIO43_REG_RESVAL 0x0
+#define RV_PLIC_PRIO43_PRIO43_MASK 0x3
+#define RV_PLIC_PRIO43_PRIO43_OFFSET 0
+#define RV_PLIC_PRIO43_PRIO43_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO43_PRIO43_MASK, .index = RV_PLIC_PRIO43_PRIO43_OFFSET })
+
+// Interrupt Source 44 Priority
+#define RV_PLIC_PRIO44_REG_OFFSET 0xb0
+#define RV_PLIC_PRIO44_REG_RESVAL 0x0
+#define RV_PLIC_PRIO44_PRIO44_MASK 0x3
+#define RV_PLIC_PRIO44_PRIO44_OFFSET 0
+#define RV_PLIC_PRIO44_PRIO44_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO44_PRIO44_MASK, .index = RV_PLIC_PRIO44_PRIO44_OFFSET })
+
+// Interrupt Source 45 Priority
+#define RV_PLIC_PRIO45_REG_OFFSET 0xb4
+#define RV_PLIC_PRIO45_REG_RESVAL 0x0
+#define RV_PLIC_PRIO45_PRIO45_MASK 0x3
+#define RV_PLIC_PRIO45_PRIO45_OFFSET 0
+#define RV_PLIC_PRIO45_PRIO45_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO45_PRIO45_MASK, .index = RV_PLIC_PRIO45_PRIO45_OFFSET })
+
+// Interrupt Source 46 Priority
+#define RV_PLIC_PRIO46_REG_OFFSET 0xb8
+#define RV_PLIC_PRIO46_REG_RESVAL 0x0
+#define RV_PLIC_PRIO46_PRIO46_MASK 0x3
+#define RV_PLIC_PRIO46_PRIO46_OFFSET 0
+#define RV_PLIC_PRIO46_PRIO46_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO46_PRIO46_MASK, .index = RV_PLIC_PRIO46_PRIO46_OFFSET })
+
+// Interrupt Source 47 Priority
+#define RV_PLIC_PRIO47_REG_OFFSET 0xbc
+#define RV_PLIC_PRIO47_REG_RESVAL 0x0
+#define RV_PLIC_PRIO47_PRIO47_MASK 0x3
+#define RV_PLIC_PRIO47_PRIO47_OFFSET 0
+#define RV_PLIC_PRIO47_PRIO47_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO47_PRIO47_MASK, .index = RV_PLIC_PRIO47_PRIO47_OFFSET })
+
+// Interrupt Source 48 Priority
+#define RV_PLIC_PRIO48_REG_OFFSET 0xc0
+#define RV_PLIC_PRIO48_REG_RESVAL 0x0
+#define RV_PLIC_PRIO48_PRIO48_MASK 0x3
+#define RV_PLIC_PRIO48_PRIO48_OFFSET 0
+#define RV_PLIC_PRIO48_PRIO48_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO48_PRIO48_MASK, .index = RV_PLIC_PRIO48_PRIO48_OFFSET })
+
+// Interrupt Source 49 Priority
+#define RV_PLIC_PRIO49_REG_OFFSET 0xc4
+#define RV_PLIC_PRIO49_REG_RESVAL 0x0
+#define RV_PLIC_PRIO49_PRIO49_MASK 0x3
+#define RV_PLIC_PRIO49_PRIO49_OFFSET 0
+#define RV_PLIC_PRIO49_PRIO49_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO49_PRIO49_MASK, .index = RV_PLIC_PRIO49_PRIO49_OFFSET })
+
+// Interrupt Source 50 Priority
+#define RV_PLIC_PRIO50_REG_OFFSET 0xc8
+#define RV_PLIC_PRIO50_REG_RESVAL 0x0
+#define RV_PLIC_PRIO50_PRIO50_MASK 0x3
+#define RV_PLIC_PRIO50_PRIO50_OFFSET 0
+#define RV_PLIC_PRIO50_PRIO50_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO50_PRIO50_MASK, .index = RV_PLIC_PRIO50_PRIO50_OFFSET })
+
+// Interrupt Source 51 Priority
+#define RV_PLIC_PRIO51_REG_OFFSET 0xcc
+#define RV_PLIC_PRIO51_REG_RESVAL 0x0
+#define RV_PLIC_PRIO51_PRIO51_MASK 0x3
+#define RV_PLIC_PRIO51_PRIO51_OFFSET 0
+#define RV_PLIC_PRIO51_PRIO51_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO51_PRIO51_MASK, .index = RV_PLIC_PRIO51_PRIO51_OFFSET })
+
+// Interrupt Source 52 Priority
+#define RV_PLIC_PRIO52_REG_OFFSET 0xd0
+#define RV_PLIC_PRIO52_REG_RESVAL 0x0
+#define RV_PLIC_PRIO52_PRIO52_MASK 0x3
+#define RV_PLIC_PRIO52_PRIO52_OFFSET 0
+#define RV_PLIC_PRIO52_PRIO52_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO52_PRIO52_MASK, .index = RV_PLIC_PRIO52_PRIO52_OFFSET })
+
+// Interrupt Source 53 Priority
+#define RV_PLIC_PRIO53_REG_OFFSET 0xd4
+#define RV_PLIC_PRIO53_REG_RESVAL 0x0
+#define RV_PLIC_PRIO53_PRIO53_MASK 0x3
+#define RV_PLIC_PRIO53_PRIO53_OFFSET 0
+#define RV_PLIC_PRIO53_PRIO53_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO53_PRIO53_MASK, .index = RV_PLIC_PRIO53_PRIO53_OFFSET })
+
+// Interrupt Source 54 Priority
+#define RV_PLIC_PRIO54_REG_OFFSET 0xd8
+#define RV_PLIC_PRIO54_REG_RESVAL 0x0
+#define RV_PLIC_PRIO54_PRIO54_MASK 0x3
+#define RV_PLIC_PRIO54_PRIO54_OFFSET 0
+#define RV_PLIC_PRIO54_PRIO54_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO54_PRIO54_MASK, .index = RV_PLIC_PRIO54_PRIO54_OFFSET })
+
+// Interrupt Source 55 Priority
+#define RV_PLIC_PRIO55_REG_OFFSET 0xdc
+#define RV_PLIC_PRIO55_REG_RESVAL 0x0
+#define RV_PLIC_PRIO55_PRIO55_MASK 0x3
+#define RV_PLIC_PRIO55_PRIO55_OFFSET 0
+#define RV_PLIC_PRIO55_PRIO55_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO55_PRIO55_MASK, .index = RV_PLIC_PRIO55_PRIO55_OFFSET })
+
+// Interrupt Source 56 Priority
+#define RV_PLIC_PRIO56_REG_OFFSET 0xe0
+#define RV_PLIC_PRIO56_REG_RESVAL 0x0
+#define RV_PLIC_PRIO56_PRIO56_MASK 0x3
+#define RV_PLIC_PRIO56_PRIO56_OFFSET 0
+#define RV_PLIC_PRIO56_PRIO56_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO56_PRIO56_MASK, .index = RV_PLIC_PRIO56_PRIO56_OFFSET })
+
+// Interrupt Source 57 Priority
+#define RV_PLIC_PRIO57_REG_OFFSET 0xe4
+#define RV_PLIC_PRIO57_REG_RESVAL 0x0
+#define RV_PLIC_PRIO57_PRIO57_MASK 0x3
+#define RV_PLIC_PRIO57_PRIO57_OFFSET 0
+#define RV_PLIC_PRIO57_PRIO57_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO57_PRIO57_MASK, .index = RV_PLIC_PRIO57_PRIO57_OFFSET })
+
+// Interrupt Source 58 Priority
+#define RV_PLIC_PRIO58_REG_OFFSET 0xe8
+#define RV_PLIC_PRIO58_REG_RESVAL 0x0
+#define RV_PLIC_PRIO58_PRIO58_MASK 0x3
+#define RV_PLIC_PRIO58_PRIO58_OFFSET 0
+#define RV_PLIC_PRIO58_PRIO58_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO58_PRIO58_MASK, .index = RV_PLIC_PRIO58_PRIO58_OFFSET })
+
+// Interrupt Source 59 Priority
+#define RV_PLIC_PRIO59_REG_OFFSET 0xec
+#define RV_PLIC_PRIO59_REG_RESVAL 0x0
+#define RV_PLIC_PRIO59_PRIO59_MASK 0x3
+#define RV_PLIC_PRIO59_PRIO59_OFFSET 0
+#define RV_PLIC_PRIO59_PRIO59_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO59_PRIO59_MASK, .index = RV_PLIC_PRIO59_PRIO59_OFFSET })
+
+// Interrupt Source 60 Priority
+#define RV_PLIC_PRIO60_REG_OFFSET 0xf0
+#define RV_PLIC_PRIO60_REG_RESVAL 0x0
+#define RV_PLIC_PRIO60_PRIO60_MASK 0x3
+#define RV_PLIC_PRIO60_PRIO60_OFFSET 0
+#define RV_PLIC_PRIO60_PRIO60_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO60_PRIO60_MASK, .index = RV_PLIC_PRIO60_PRIO60_OFFSET })
+
+// Interrupt Source 61 Priority
+#define RV_PLIC_PRIO61_REG_OFFSET 0xf4
+#define RV_PLIC_PRIO61_REG_RESVAL 0x0
+#define RV_PLIC_PRIO61_PRIO61_MASK 0x3
+#define RV_PLIC_PRIO61_PRIO61_OFFSET 0
+#define RV_PLIC_PRIO61_PRIO61_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO61_PRIO61_MASK, .index = RV_PLIC_PRIO61_PRIO61_OFFSET })
+
+// Interrupt Source 62 Priority
+#define RV_PLIC_PRIO62_REG_OFFSET 0xf8
+#define RV_PLIC_PRIO62_REG_RESVAL 0x0
+#define RV_PLIC_PRIO62_PRIO62_MASK 0x3
+#define RV_PLIC_PRIO62_PRIO62_OFFSET 0
+#define RV_PLIC_PRIO62_PRIO62_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO62_PRIO62_MASK, .index = RV_PLIC_PRIO62_PRIO62_OFFSET })
+
+// Interrupt Source 63 Priority
+#define RV_PLIC_PRIO63_REG_OFFSET 0xfc
+#define RV_PLIC_PRIO63_REG_RESVAL 0x0
+#define RV_PLIC_PRIO63_PRIO63_MASK 0x3
+#define RV_PLIC_PRIO63_PRIO63_OFFSET 0
+#define RV_PLIC_PRIO63_PRIO63_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO63_PRIO63_MASK, .index = RV_PLIC_PRIO63_PRIO63_OFFSET })
+
+// Interrupt Source 64 Priority
+#define RV_PLIC_PRIO64_REG_OFFSET 0x100
+#define RV_PLIC_PRIO64_REG_RESVAL 0x0
+#define RV_PLIC_PRIO64_PRIO64_MASK 0x3
+#define RV_PLIC_PRIO64_PRIO64_OFFSET 0
+#define RV_PLIC_PRIO64_PRIO64_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO64_PRIO64_MASK, .index = RV_PLIC_PRIO64_PRIO64_OFFSET })
+
+// Interrupt Source 65 Priority
+#define RV_PLIC_PRIO65_REG_OFFSET 0x104
+#define RV_PLIC_PRIO65_REG_RESVAL 0x0
+#define RV_PLIC_PRIO65_PRIO65_MASK 0x3
+#define RV_PLIC_PRIO65_PRIO65_OFFSET 0
+#define RV_PLIC_PRIO65_PRIO65_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO65_PRIO65_MASK, .index = RV_PLIC_PRIO65_PRIO65_OFFSET })
+
+// Interrupt Source 66 Priority
+#define RV_PLIC_PRIO66_REG_OFFSET 0x108
+#define RV_PLIC_PRIO66_REG_RESVAL 0x0
+#define RV_PLIC_PRIO66_PRIO66_MASK 0x3
+#define RV_PLIC_PRIO66_PRIO66_OFFSET 0
+#define RV_PLIC_PRIO66_PRIO66_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO66_PRIO66_MASK, .index = RV_PLIC_PRIO66_PRIO66_OFFSET })
+
+// Interrupt Source 67 Priority
+#define RV_PLIC_PRIO67_REG_OFFSET 0x10c
+#define RV_PLIC_PRIO67_REG_RESVAL 0x0
+#define RV_PLIC_PRIO67_PRIO67_MASK 0x3
+#define RV_PLIC_PRIO67_PRIO67_OFFSET 0
+#define RV_PLIC_PRIO67_PRIO67_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO67_PRIO67_MASK, .index = RV_PLIC_PRIO67_PRIO67_OFFSET })
+
+// Interrupt Source 68 Priority
+#define RV_PLIC_PRIO68_REG_OFFSET 0x110
+#define RV_PLIC_PRIO68_REG_RESVAL 0x0
+#define RV_PLIC_PRIO68_PRIO68_MASK 0x3
+#define RV_PLIC_PRIO68_PRIO68_OFFSET 0
+#define RV_PLIC_PRIO68_PRIO68_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO68_PRIO68_MASK, .index = RV_PLIC_PRIO68_PRIO68_OFFSET })
+
+// Interrupt Source 69 Priority
+#define RV_PLIC_PRIO69_REG_OFFSET 0x114
+#define RV_PLIC_PRIO69_REG_RESVAL 0x0
+#define RV_PLIC_PRIO69_PRIO69_MASK 0x3
+#define RV_PLIC_PRIO69_PRIO69_OFFSET 0
+#define RV_PLIC_PRIO69_PRIO69_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO69_PRIO69_MASK, .index = RV_PLIC_PRIO69_PRIO69_OFFSET })
+
+// Interrupt Source 70 Priority
+#define RV_PLIC_PRIO70_REG_OFFSET 0x118
+#define RV_PLIC_PRIO70_REG_RESVAL 0x0
+#define RV_PLIC_PRIO70_PRIO70_MASK 0x3
+#define RV_PLIC_PRIO70_PRIO70_OFFSET 0
+#define RV_PLIC_PRIO70_PRIO70_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO70_PRIO70_MASK, .index = RV_PLIC_PRIO70_PRIO70_OFFSET })
+
+// Interrupt Source 71 Priority
+#define RV_PLIC_PRIO71_REG_OFFSET 0x11c
+#define RV_PLIC_PRIO71_REG_RESVAL 0x0
+#define RV_PLIC_PRIO71_PRIO71_MASK 0x3
+#define RV_PLIC_PRIO71_PRIO71_OFFSET 0
+#define RV_PLIC_PRIO71_PRIO71_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO71_PRIO71_MASK, .index = RV_PLIC_PRIO71_PRIO71_OFFSET })
+
+// Interrupt Source 72 Priority
+#define RV_PLIC_PRIO72_REG_OFFSET 0x120
+#define RV_PLIC_PRIO72_REG_RESVAL 0x0
+#define RV_PLIC_PRIO72_PRIO72_MASK 0x3
+#define RV_PLIC_PRIO72_PRIO72_OFFSET 0
+#define RV_PLIC_PRIO72_PRIO72_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO72_PRIO72_MASK, .index = RV_PLIC_PRIO72_PRIO72_OFFSET })
+
+// Interrupt Source 73 Priority
+#define RV_PLIC_PRIO73_REG_OFFSET 0x124
+#define RV_PLIC_PRIO73_REG_RESVAL 0x0
+#define RV_PLIC_PRIO73_PRIO73_MASK 0x3
+#define RV_PLIC_PRIO73_PRIO73_OFFSET 0
+#define RV_PLIC_PRIO73_PRIO73_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO73_PRIO73_MASK, .index = RV_PLIC_PRIO73_PRIO73_OFFSET })
+
+// Interrupt Source 74 Priority
+#define RV_PLIC_PRIO74_REG_OFFSET 0x128
+#define RV_PLIC_PRIO74_REG_RESVAL 0x0
+#define RV_PLIC_PRIO74_PRIO74_MASK 0x3
+#define RV_PLIC_PRIO74_PRIO74_OFFSET 0
+#define RV_PLIC_PRIO74_PRIO74_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO74_PRIO74_MASK, .index = RV_PLIC_PRIO74_PRIO74_OFFSET })
+
+// Interrupt Source 75 Priority
+#define RV_PLIC_PRIO75_REG_OFFSET 0x12c
+#define RV_PLIC_PRIO75_REG_RESVAL 0x0
+#define RV_PLIC_PRIO75_PRIO75_MASK 0x3
+#define RV_PLIC_PRIO75_PRIO75_OFFSET 0
+#define RV_PLIC_PRIO75_PRIO75_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO75_PRIO75_MASK, .index = RV_PLIC_PRIO75_PRIO75_OFFSET })
+
+// Interrupt Source 76 Priority
+#define RV_PLIC_PRIO76_REG_OFFSET 0x130
+#define RV_PLIC_PRIO76_REG_RESVAL 0x0
+#define RV_PLIC_PRIO76_PRIO76_MASK 0x3
+#define RV_PLIC_PRIO76_PRIO76_OFFSET 0
+#define RV_PLIC_PRIO76_PRIO76_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO76_PRIO76_MASK, .index = RV_PLIC_PRIO76_PRIO76_OFFSET })
+
+// Interrupt Source 77 Priority
+#define RV_PLIC_PRIO77_REG_OFFSET 0x134
+#define RV_PLIC_PRIO77_REG_RESVAL 0x0
+#define RV_PLIC_PRIO77_PRIO77_MASK 0x3
+#define RV_PLIC_PRIO77_PRIO77_OFFSET 0
+#define RV_PLIC_PRIO77_PRIO77_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO77_PRIO77_MASK, .index = RV_PLIC_PRIO77_PRIO77_OFFSET })
+
+// Interrupt Source 78 Priority
+#define RV_PLIC_PRIO78_REG_OFFSET 0x138
+#define RV_PLIC_PRIO78_REG_RESVAL 0x0
+#define RV_PLIC_PRIO78_PRIO78_MASK 0x3
+#define RV_PLIC_PRIO78_PRIO78_OFFSET 0
+#define RV_PLIC_PRIO78_PRIO78_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO78_PRIO78_MASK, .index = RV_PLIC_PRIO78_PRIO78_OFFSET })
+
+// Interrupt Source 79 Priority
+#define RV_PLIC_PRIO79_REG_OFFSET 0x13c
+#define RV_PLIC_PRIO79_REG_RESVAL 0x0
+#define RV_PLIC_PRIO79_PRIO79_MASK 0x3
+#define RV_PLIC_PRIO79_PRIO79_OFFSET 0
+#define RV_PLIC_PRIO79_PRIO79_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO79_PRIO79_MASK, .index = RV_PLIC_PRIO79_PRIO79_OFFSET })
+
+// Interrupt Source 80 Priority
+#define RV_PLIC_PRIO80_REG_OFFSET 0x140
+#define RV_PLIC_PRIO80_REG_RESVAL 0x0
+#define RV_PLIC_PRIO80_PRIO80_MASK 0x3
+#define RV_PLIC_PRIO80_PRIO80_OFFSET 0
+#define RV_PLIC_PRIO80_PRIO80_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO80_PRIO80_MASK, .index = RV_PLIC_PRIO80_PRIO80_OFFSET })
+
+// Interrupt Source 81 Priority
+#define RV_PLIC_PRIO81_REG_OFFSET 0x144
+#define RV_PLIC_PRIO81_REG_RESVAL 0x0
+#define RV_PLIC_PRIO81_PRIO81_MASK 0x3
+#define RV_PLIC_PRIO81_PRIO81_OFFSET 0
+#define RV_PLIC_PRIO81_PRIO81_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO81_PRIO81_MASK, .index = RV_PLIC_PRIO81_PRIO81_OFFSET })
+
+// Interrupt Source 82 Priority
+#define RV_PLIC_PRIO82_REG_OFFSET 0x148
+#define RV_PLIC_PRIO82_REG_RESVAL 0x0
+#define RV_PLIC_PRIO82_PRIO82_MASK 0x3
+#define RV_PLIC_PRIO82_PRIO82_OFFSET 0
+#define RV_PLIC_PRIO82_PRIO82_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO82_PRIO82_MASK, .index = RV_PLIC_PRIO82_PRIO82_OFFSET })
+
+// Interrupt Source 83 Priority
+#define RV_PLIC_PRIO83_REG_OFFSET 0x14c
+#define RV_PLIC_PRIO83_REG_RESVAL 0x0
+#define RV_PLIC_PRIO83_PRIO83_MASK 0x3
+#define RV_PLIC_PRIO83_PRIO83_OFFSET 0
+#define RV_PLIC_PRIO83_PRIO83_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO83_PRIO83_MASK, .index = RV_PLIC_PRIO83_PRIO83_OFFSET })
+
+// Interrupt Source 84 Priority
+#define RV_PLIC_PRIO84_REG_OFFSET 0x150
+#define RV_PLIC_PRIO84_REG_RESVAL 0x0
+#define RV_PLIC_PRIO84_PRIO84_MASK 0x3
+#define RV_PLIC_PRIO84_PRIO84_OFFSET 0
+#define RV_PLIC_PRIO84_PRIO84_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO84_PRIO84_MASK, .index = RV_PLIC_PRIO84_PRIO84_OFFSET })
+
+// Interrupt Source 85 Priority
+#define RV_PLIC_PRIO85_REG_OFFSET 0x154
+#define RV_PLIC_PRIO85_REG_RESVAL 0x0
+#define RV_PLIC_PRIO85_PRIO85_MASK 0x3
+#define RV_PLIC_PRIO85_PRIO85_OFFSET 0
+#define RV_PLIC_PRIO85_PRIO85_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO85_PRIO85_MASK, .index = RV_PLIC_PRIO85_PRIO85_OFFSET })
+
+// Interrupt Source 86 Priority
+#define RV_PLIC_PRIO86_REG_OFFSET 0x158
+#define RV_PLIC_PRIO86_REG_RESVAL 0x0
+#define RV_PLIC_PRIO86_PRIO86_MASK 0x3
+#define RV_PLIC_PRIO86_PRIO86_OFFSET 0
+#define RV_PLIC_PRIO86_PRIO86_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO86_PRIO86_MASK, .index = RV_PLIC_PRIO86_PRIO86_OFFSET })
+
+// Interrupt Source 87 Priority
+#define RV_PLIC_PRIO87_REG_OFFSET 0x15c
+#define RV_PLIC_PRIO87_REG_RESVAL 0x0
+#define RV_PLIC_PRIO87_PRIO87_MASK 0x3
+#define RV_PLIC_PRIO87_PRIO87_OFFSET 0
+#define RV_PLIC_PRIO87_PRIO87_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO87_PRIO87_MASK, .index = RV_PLIC_PRIO87_PRIO87_OFFSET })
+
+// Interrupt Source 88 Priority
+#define RV_PLIC_PRIO88_REG_OFFSET 0x160
+#define RV_PLIC_PRIO88_REG_RESVAL 0x0
+#define RV_PLIC_PRIO88_PRIO88_MASK 0x3
+#define RV_PLIC_PRIO88_PRIO88_OFFSET 0
+#define RV_PLIC_PRIO88_PRIO88_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO88_PRIO88_MASK, .index = RV_PLIC_PRIO88_PRIO88_OFFSET })
+
+// Interrupt Source 89 Priority
+#define RV_PLIC_PRIO89_REG_OFFSET 0x164
+#define RV_PLIC_PRIO89_REG_RESVAL 0x0
+#define RV_PLIC_PRIO89_PRIO89_MASK 0x3
+#define RV_PLIC_PRIO89_PRIO89_OFFSET 0
+#define RV_PLIC_PRIO89_PRIO89_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO89_PRIO89_MASK, .index = RV_PLIC_PRIO89_PRIO89_OFFSET })
+
+// Interrupt Source 90 Priority
+#define RV_PLIC_PRIO90_REG_OFFSET 0x168
+#define RV_PLIC_PRIO90_REG_RESVAL 0x0
+#define RV_PLIC_PRIO90_PRIO90_MASK 0x3
+#define RV_PLIC_PRIO90_PRIO90_OFFSET 0
+#define RV_PLIC_PRIO90_PRIO90_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO90_PRIO90_MASK, .index = RV_PLIC_PRIO90_PRIO90_OFFSET })
+
+// Interrupt Source 91 Priority
+#define RV_PLIC_PRIO91_REG_OFFSET 0x16c
+#define RV_PLIC_PRIO91_REG_RESVAL 0x0
+#define RV_PLIC_PRIO91_PRIO91_MASK 0x3
+#define RV_PLIC_PRIO91_PRIO91_OFFSET 0
+#define RV_PLIC_PRIO91_PRIO91_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO91_PRIO91_MASK, .index = RV_PLIC_PRIO91_PRIO91_OFFSET })
+
+// Interrupt Source 92 Priority
+#define RV_PLIC_PRIO92_REG_OFFSET 0x170
+#define RV_PLIC_PRIO92_REG_RESVAL 0x0
+#define RV_PLIC_PRIO92_PRIO92_MASK 0x3
+#define RV_PLIC_PRIO92_PRIO92_OFFSET 0
+#define RV_PLIC_PRIO92_PRIO92_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO92_PRIO92_MASK, .index = RV_PLIC_PRIO92_PRIO92_OFFSET })
+
+// Interrupt Source 93 Priority
+#define RV_PLIC_PRIO93_REG_OFFSET 0x174
+#define RV_PLIC_PRIO93_REG_RESVAL 0x0
+#define RV_PLIC_PRIO93_PRIO93_MASK 0x3
+#define RV_PLIC_PRIO93_PRIO93_OFFSET 0
+#define RV_PLIC_PRIO93_PRIO93_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO93_PRIO93_MASK, .index = RV_PLIC_PRIO93_PRIO93_OFFSET })
+
+// Interrupt Source 94 Priority
+#define RV_PLIC_PRIO94_REG_OFFSET 0x178
+#define RV_PLIC_PRIO94_REG_RESVAL 0x0
+#define RV_PLIC_PRIO94_PRIO94_MASK 0x3
+#define RV_PLIC_PRIO94_PRIO94_OFFSET 0
+#define RV_PLIC_PRIO94_PRIO94_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO94_PRIO94_MASK, .index = RV_PLIC_PRIO94_PRIO94_OFFSET })
+
+// Interrupt Source 95 Priority
+#define RV_PLIC_PRIO95_REG_OFFSET 0x17c
+#define RV_PLIC_PRIO95_REG_RESVAL 0x0
+#define RV_PLIC_PRIO95_PRIO95_MASK 0x3
+#define RV_PLIC_PRIO95_PRIO95_OFFSET 0
+#define RV_PLIC_PRIO95_PRIO95_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO95_PRIO95_MASK, .index = RV_PLIC_PRIO95_PRIO95_OFFSET })
+
+// Interrupt Source 96 Priority
+#define RV_PLIC_PRIO96_REG_OFFSET 0x180
+#define RV_PLIC_PRIO96_REG_RESVAL 0x0
+#define RV_PLIC_PRIO96_PRIO96_MASK 0x3
+#define RV_PLIC_PRIO96_PRIO96_OFFSET 0
+#define RV_PLIC_PRIO96_PRIO96_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO96_PRIO96_MASK, .index = RV_PLIC_PRIO96_PRIO96_OFFSET })
+
+// Interrupt Source 97 Priority
+#define RV_PLIC_PRIO97_REG_OFFSET 0x184
+#define RV_PLIC_PRIO97_REG_RESVAL 0x0
+#define RV_PLIC_PRIO97_PRIO97_MASK 0x3
+#define RV_PLIC_PRIO97_PRIO97_OFFSET 0
+#define RV_PLIC_PRIO97_PRIO97_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO97_PRIO97_MASK, .index = RV_PLIC_PRIO97_PRIO97_OFFSET })
+
+// Interrupt Source 98 Priority
+#define RV_PLIC_PRIO98_REG_OFFSET 0x188
+#define RV_PLIC_PRIO98_REG_RESVAL 0x0
+#define RV_PLIC_PRIO98_PRIO98_MASK 0x3
+#define RV_PLIC_PRIO98_PRIO98_OFFSET 0
+#define RV_PLIC_PRIO98_PRIO98_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO98_PRIO98_MASK, .index = RV_PLIC_PRIO98_PRIO98_OFFSET })
+
+// Interrupt Source 99 Priority
+#define RV_PLIC_PRIO99_REG_OFFSET 0x18c
+#define RV_PLIC_PRIO99_REG_RESVAL 0x0
+#define RV_PLIC_PRIO99_PRIO99_MASK 0x3
+#define RV_PLIC_PRIO99_PRIO99_OFFSET 0
+#define RV_PLIC_PRIO99_PRIO99_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO99_PRIO99_MASK, .index = RV_PLIC_PRIO99_PRIO99_OFFSET })
+
+// Interrupt Source 100 Priority
+#define RV_PLIC_PRIO100_REG_OFFSET 0x190
+#define RV_PLIC_PRIO100_REG_RESVAL 0x0
+#define RV_PLIC_PRIO100_PRIO100_MASK 0x3
+#define RV_PLIC_PRIO100_PRIO100_OFFSET 0
+#define RV_PLIC_PRIO100_PRIO100_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO100_PRIO100_MASK, .index = RV_PLIC_PRIO100_PRIO100_OFFSET })
+
+// Interrupt Source 101 Priority
+#define RV_PLIC_PRIO101_REG_OFFSET 0x194
+#define RV_PLIC_PRIO101_REG_RESVAL 0x0
+#define RV_PLIC_PRIO101_PRIO101_MASK 0x3
+#define RV_PLIC_PRIO101_PRIO101_OFFSET 0
+#define RV_PLIC_PRIO101_PRIO101_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO101_PRIO101_MASK, .index = RV_PLIC_PRIO101_PRIO101_OFFSET })
+
+// Interrupt Source 102 Priority
+#define RV_PLIC_PRIO102_REG_OFFSET 0x198
+#define RV_PLIC_PRIO102_REG_RESVAL 0x0
+#define RV_PLIC_PRIO102_PRIO102_MASK 0x3
+#define RV_PLIC_PRIO102_PRIO102_OFFSET 0
+#define RV_PLIC_PRIO102_PRIO102_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO102_PRIO102_MASK, .index = RV_PLIC_PRIO102_PRIO102_OFFSET })
+
+// Interrupt Source 103 Priority
+#define RV_PLIC_PRIO103_REG_OFFSET 0x19c
+#define RV_PLIC_PRIO103_REG_RESVAL 0x0
+#define RV_PLIC_PRIO103_PRIO103_MASK 0x3
+#define RV_PLIC_PRIO103_PRIO103_OFFSET 0
+#define RV_PLIC_PRIO103_PRIO103_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO103_PRIO103_MASK, .index = RV_PLIC_PRIO103_PRIO103_OFFSET })
+
+// Interrupt Source 104 Priority
+#define RV_PLIC_PRIO104_REG_OFFSET 0x1a0
+#define RV_PLIC_PRIO104_REG_RESVAL 0x0
+#define RV_PLIC_PRIO104_PRIO104_MASK 0x3
+#define RV_PLIC_PRIO104_PRIO104_OFFSET 0
+#define RV_PLIC_PRIO104_PRIO104_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO104_PRIO104_MASK, .index = RV_PLIC_PRIO104_PRIO104_OFFSET })
+
+// Interrupt Source 105 Priority
+#define RV_PLIC_PRIO105_REG_OFFSET 0x1a4
+#define RV_PLIC_PRIO105_REG_RESVAL 0x0
+#define RV_PLIC_PRIO105_PRIO105_MASK 0x3
+#define RV_PLIC_PRIO105_PRIO105_OFFSET 0
+#define RV_PLIC_PRIO105_PRIO105_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO105_PRIO105_MASK, .index = RV_PLIC_PRIO105_PRIO105_OFFSET })
+
+// Interrupt Source 106 Priority
+#define RV_PLIC_PRIO106_REG_OFFSET 0x1a8
+#define RV_PLIC_PRIO106_REG_RESVAL 0x0
+#define RV_PLIC_PRIO106_PRIO106_MASK 0x3
+#define RV_PLIC_PRIO106_PRIO106_OFFSET 0
+#define RV_PLIC_PRIO106_PRIO106_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO106_PRIO106_MASK, .index = RV_PLIC_PRIO106_PRIO106_OFFSET })
+
+// Interrupt Source 107 Priority
+#define RV_PLIC_PRIO107_REG_OFFSET 0x1ac
+#define RV_PLIC_PRIO107_REG_RESVAL 0x0
+#define RV_PLIC_PRIO107_PRIO107_MASK 0x3
+#define RV_PLIC_PRIO107_PRIO107_OFFSET 0
+#define RV_PLIC_PRIO107_PRIO107_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO107_PRIO107_MASK, .index = RV_PLIC_PRIO107_PRIO107_OFFSET })
+
+// Interrupt Source 108 Priority
+#define RV_PLIC_PRIO108_REG_OFFSET 0x1b0
+#define RV_PLIC_PRIO108_REG_RESVAL 0x0
+#define RV_PLIC_PRIO108_PRIO108_MASK 0x3
+#define RV_PLIC_PRIO108_PRIO108_OFFSET 0
+#define RV_PLIC_PRIO108_PRIO108_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO108_PRIO108_MASK, .index = RV_PLIC_PRIO108_PRIO108_OFFSET })
+
+// Interrupt Source 109 Priority
+#define RV_PLIC_PRIO109_REG_OFFSET 0x1b4
+#define RV_PLIC_PRIO109_REG_RESVAL 0x0
+#define RV_PLIC_PRIO109_PRIO109_MASK 0x3
+#define RV_PLIC_PRIO109_PRIO109_OFFSET 0
+#define RV_PLIC_PRIO109_PRIO109_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO109_PRIO109_MASK, .index = RV_PLIC_PRIO109_PRIO109_OFFSET })
+
+// Interrupt Source 110 Priority
+#define RV_PLIC_PRIO110_REG_OFFSET 0x1b8
+#define RV_PLIC_PRIO110_REG_RESVAL 0x0
+#define RV_PLIC_PRIO110_PRIO110_MASK 0x3
+#define RV_PLIC_PRIO110_PRIO110_OFFSET 0
+#define RV_PLIC_PRIO110_PRIO110_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO110_PRIO110_MASK, .index = RV_PLIC_PRIO110_PRIO110_OFFSET })
+
+// Interrupt Source 111 Priority
+#define RV_PLIC_PRIO111_REG_OFFSET 0x1bc
+#define RV_PLIC_PRIO111_REG_RESVAL 0x0
+#define RV_PLIC_PRIO111_PRIO111_MASK 0x3
+#define RV_PLIC_PRIO111_PRIO111_OFFSET 0
+#define RV_PLIC_PRIO111_PRIO111_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO111_PRIO111_MASK, .index = RV_PLIC_PRIO111_PRIO111_OFFSET })
+
+// Interrupt Source 112 Priority
+#define RV_PLIC_PRIO112_REG_OFFSET 0x1c0
+#define RV_PLIC_PRIO112_REG_RESVAL 0x0
+#define RV_PLIC_PRIO112_PRIO112_MASK 0x3
+#define RV_PLIC_PRIO112_PRIO112_OFFSET 0
+#define RV_PLIC_PRIO112_PRIO112_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO112_PRIO112_MASK, .index = RV_PLIC_PRIO112_PRIO112_OFFSET })
+
+// Interrupt Source 113 Priority
+#define RV_PLIC_PRIO113_REG_OFFSET 0x1c4
+#define RV_PLIC_PRIO113_REG_RESVAL 0x0
+#define RV_PLIC_PRIO113_PRIO113_MASK 0x3
+#define RV_PLIC_PRIO113_PRIO113_OFFSET 0
+#define RV_PLIC_PRIO113_PRIO113_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO113_PRIO113_MASK, .index = RV_PLIC_PRIO113_PRIO113_OFFSET })
+
+// Interrupt Source 114 Priority
+#define RV_PLIC_PRIO114_REG_OFFSET 0x1c8
+#define RV_PLIC_PRIO114_REG_RESVAL 0x0
+#define RV_PLIC_PRIO114_PRIO114_MASK 0x3
+#define RV_PLIC_PRIO114_PRIO114_OFFSET 0
+#define RV_PLIC_PRIO114_PRIO114_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO114_PRIO114_MASK, .index = RV_PLIC_PRIO114_PRIO114_OFFSET })
+
+// Interrupt Source 115 Priority
+#define RV_PLIC_PRIO115_REG_OFFSET 0x1cc
+#define RV_PLIC_PRIO115_REG_RESVAL 0x0
+#define RV_PLIC_PRIO115_PRIO115_MASK 0x3
+#define RV_PLIC_PRIO115_PRIO115_OFFSET 0
+#define RV_PLIC_PRIO115_PRIO115_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO115_PRIO115_MASK, .index = RV_PLIC_PRIO115_PRIO115_OFFSET })
+
+// Interrupt Source 116 Priority
+#define RV_PLIC_PRIO116_REG_OFFSET 0x1d0
+#define RV_PLIC_PRIO116_REG_RESVAL 0x0
+#define RV_PLIC_PRIO116_PRIO116_MASK 0x3
+#define RV_PLIC_PRIO116_PRIO116_OFFSET 0
+#define RV_PLIC_PRIO116_PRIO116_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO116_PRIO116_MASK, .index = RV_PLIC_PRIO116_PRIO116_OFFSET })
+
+// Interrupt Source 117 Priority
+#define RV_PLIC_PRIO117_REG_OFFSET 0x1d4
+#define RV_PLIC_PRIO117_REG_RESVAL 0x0
+#define RV_PLIC_PRIO117_PRIO117_MASK 0x3
+#define RV_PLIC_PRIO117_PRIO117_OFFSET 0
+#define RV_PLIC_PRIO117_PRIO117_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO117_PRIO117_MASK, .index = RV_PLIC_PRIO117_PRIO117_OFFSET })
+
+// Interrupt Source 118 Priority
+#define RV_PLIC_PRIO118_REG_OFFSET 0x1d8
+#define RV_PLIC_PRIO118_REG_RESVAL 0x0
+#define RV_PLIC_PRIO118_PRIO118_MASK 0x3
+#define RV_PLIC_PRIO118_PRIO118_OFFSET 0
+#define RV_PLIC_PRIO118_PRIO118_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO118_PRIO118_MASK, .index = RV_PLIC_PRIO118_PRIO118_OFFSET })
+
+// Interrupt Source 119 Priority
+#define RV_PLIC_PRIO119_REG_OFFSET 0x1dc
+#define RV_PLIC_PRIO119_REG_RESVAL 0x0
+#define RV_PLIC_PRIO119_PRIO119_MASK 0x3
+#define RV_PLIC_PRIO119_PRIO119_OFFSET 0
+#define RV_PLIC_PRIO119_PRIO119_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO119_PRIO119_MASK, .index = RV_PLIC_PRIO119_PRIO119_OFFSET })
+
+// Interrupt Source 120 Priority
+#define RV_PLIC_PRIO120_REG_OFFSET 0x1e0
+#define RV_PLIC_PRIO120_REG_RESVAL 0x0
+#define RV_PLIC_PRIO120_PRIO120_MASK 0x3
+#define RV_PLIC_PRIO120_PRIO120_OFFSET 0
+#define RV_PLIC_PRIO120_PRIO120_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO120_PRIO120_MASK, .index = RV_PLIC_PRIO120_PRIO120_OFFSET })
+
+// Interrupt Source 121 Priority
+#define RV_PLIC_PRIO121_REG_OFFSET 0x1e4
+#define RV_PLIC_PRIO121_REG_RESVAL 0x0
+#define RV_PLIC_PRIO121_PRIO121_MASK 0x3
+#define RV_PLIC_PRIO121_PRIO121_OFFSET 0
+#define RV_PLIC_PRIO121_PRIO121_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO121_PRIO121_MASK, .index = RV_PLIC_PRIO121_PRIO121_OFFSET })
+
+// Interrupt Source 122 Priority
+#define RV_PLIC_PRIO122_REG_OFFSET 0x1e8
+#define RV_PLIC_PRIO122_REG_RESVAL 0x0
+#define RV_PLIC_PRIO122_PRIO122_MASK 0x3
+#define RV_PLIC_PRIO122_PRIO122_OFFSET 0
+#define RV_PLIC_PRIO122_PRIO122_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO122_PRIO122_MASK, .index = RV_PLIC_PRIO122_PRIO122_OFFSET })
+
+// Interrupt Source 123 Priority
+#define RV_PLIC_PRIO123_REG_OFFSET 0x1ec
+#define RV_PLIC_PRIO123_REG_RESVAL 0x0
+#define RV_PLIC_PRIO123_PRIO123_MASK 0x3
+#define RV_PLIC_PRIO123_PRIO123_OFFSET 0
+#define RV_PLIC_PRIO123_PRIO123_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO123_PRIO123_MASK, .index = RV_PLIC_PRIO123_PRIO123_OFFSET })
+
+// Interrupt Source 124 Priority
+#define RV_PLIC_PRIO124_REG_OFFSET 0x1f0
+#define RV_PLIC_PRIO124_REG_RESVAL 0x0
+#define RV_PLIC_PRIO124_PRIO124_MASK 0x3
+#define RV_PLIC_PRIO124_PRIO124_OFFSET 0
+#define RV_PLIC_PRIO124_PRIO124_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO124_PRIO124_MASK, .index = RV_PLIC_PRIO124_PRIO124_OFFSET })
+
+// Interrupt Source 125 Priority
+#define RV_PLIC_PRIO125_REG_OFFSET 0x1f4
+#define RV_PLIC_PRIO125_REG_RESVAL 0x0
+#define RV_PLIC_PRIO125_PRIO125_MASK 0x3
+#define RV_PLIC_PRIO125_PRIO125_OFFSET 0
+#define RV_PLIC_PRIO125_PRIO125_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO125_PRIO125_MASK, .index = RV_PLIC_PRIO125_PRIO125_OFFSET })
+
+// Interrupt Source 126 Priority
+#define RV_PLIC_PRIO126_REG_OFFSET 0x1f8
+#define RV_PLIC_PRIO126_REG_RESVAL 0x0
+#define RV_PLIC_PRIO126_PRIO126_MASK 0x3
+#define RV_PLIC_PRIO126_PRIO126_OFFSET 0
+#define RV_PLIC_PRIO126_PRIO126_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO126_PRIO126_MASK, .index = RV_PLIC_PRIO126_PRIO126_OFFSET })
+
+// Interrupt Source 127 Priority
+#define RV_PLIC_PRIO127_REG_OFFSET 0x1fc
+#define RV_PLIC_PRIO127_REG_RESVAL 0x0
+#define RV_PLIC_PRIO127_PRIO127_MASK 0x3
+#define RV_PLIC_PRIO127_PRIO127_OFFSET 0
+#define RV_PLIC_PRIO127_PRIO127_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO127_PRIO127_MASK, .index = RV_PLIC_PRIO127_PRIO127_OFFSET })
+
+// Interrupt Source 128 Priority
+#define RV_PLIC_PRIO128_REG_OFFSET 0x200
+#define RV_PLIC_PRIO128_REG_RESVAL 0x0
+#define RV_PLIC_PRIO128_PRIO128_MASK 0x3
+#define RV_PLIC_PRIO128_PRIO128_OFFSET 0
+#define RV_PLIC_PRIO128_PRIO128_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO128_PRIO128_MASK, .index = RV_PLIC_PRIO128_PRIO128_OFFSET })
+
+// Interrupt Source 129 Priority
+#define RV_PLIC_PRIO129_REG_OFFSET 0x204
+#define RV_PLIC_PRIO129_REG_RESVAL 0x0
+#define RV_PLIC_PRIO129_PRIO129_MASK 0x3
+#define RV_PLIC_PRIO129_PRIO129_OFFSET 0
+#define RV_PLIC_PRIO129_PRIO129_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO129_PRIO129_MASK, .index = RV_PLIC_PRIO129_PRIO129_OFFSET })
+
+// Interrupt Source 130 Priority
+#define RV_PLIC_PRIO130_REG_OFFSET 0x208
+#define RV_PLIC_PRIO130_REG_RESVAL 0x0
+#define RV_PLIC_PRIO130_PRIO130_MASK 0x3
+#define RV_PLIC_PRIO130_PRIO130_OFFSET 0
+#define RV_PLIC_PRIO130_PRIO130_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO130_PRIO130_MASK, .index = RV_PLIC_PRIO130_PRIO130_OFFSET })
+
+// Interrupt Source 131 Priority
+#define RV_PLIC_PRIO131_REG_OFFSET 0x20c
+#define RV_PLIC_PRIO131_REG_RESVAL 0x0
+#define RV_PLIC_PRIO131_PRIO131_MASK 0x3
+#define RV_PLIC_PRIO131_PRIO131_OFFSET 0
+#define RV_PLIC_PRIO131_PRIO131_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO131_PRIO131_MASK, .index = RV_PLIC_PRIO131_PRIO131_OFFSET })
+
+// Interrupt Source 132 Priority
+#define RV_PLIC_PRIO132_REG_OFFSET 0x210
+#define RV_PLIC_PRIO132_REG_RESVAL 0x0
+#define RV_PLIC_PRIO132_PRIO132_MASK 0x3
+#define RV_PLIC_PRIO132_PRIO132_OFFSET 0
+#define RV_PLIC_PRIO132_PRIO132_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO132_PRIO132_MASK, .index = RV_PLIC_PRIO132_PRIO132_OFFSET })
+
+// Interrupt Source 133 Priority
+#define RV_PLIC_PRIO133_REG_OFFSET 0x214
+#define RV_PLIC_PRIO133_REG_RESVAL 0x0
+#define RV_PLIC_PRIO133_PRIO133_MASK 0x3
+#define RV_PLIC_PRIO133_PRIO133_OFFSET 0
+#define RV_PLIC_PRIO133_PRIO133_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO133_PRIO133_MASK, .index = RV_PLIC_PRIO133_PRIO133_OFFSET })
+
+// Interrupt Source 134 Priority
+#define RV_PLIC_PRIO134_REG_OFFSET 0x218
+#define RV_PLIC_PRIO134_REG_RESVAL 0x0
+#define RV_PLIC_PRIO134_PRIO134_MASK 0x3
+#define RV_PLIC_PRIO134_PRIO134_OFFSET 0
+#define RV_PLIC_PRIO134_PRIO134_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO134_PRIO134_MASK, .index = RV_PLIC_PRIO134_PRIO134_OFFSET })
+
+// Interrupt Source 135 Priority
+#define RV_PLIC_PRIO135_REG_OFFSET 0x21c
+#define RV_PLIC_PRIO135_REG_RESVAL 0x0
+#define RV_PLIC_PRIO135_PRIO135_MASK 0x3
+#define RV_PLIC_PRIO135_PRIO135_OFFSET 0
+#define RV_PLIC_PRIO135_PRIO135_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO135_PRIO135_MASK, .index = RV_PLIC_PRIO135_PRIO135_OFFSET })
+
+// Interrupt Source 136 Priority
+#define RV_PLIC_PRIO136_REG_OFFSET 0x220
+#define RV_PLIC_PRIO136_REG_RESVAL 0x0
+#define RV_PLIC_PRIO136_PRIO136_MASK 0x3
+#define RV_PLIC_PRIO136_PRIO136_OFFSET 0
+#define RV_PLIC_PRIO136_PRIO136_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO136_PRIO136_MASK, .index = RV_PLIC_PRIO136_PRIO136_OFFSET })
+
+// Interrupt Source 137 Priority
+#define RV_PLIC_PRIO137_REG_OFFSET 0x224
+#define RV_PLIC_PRIO137_REG_RESVAL 0x0
+#define RV_PLIC_PRIO137_PRIO137_MASK 0x3
+#define RV_PLIC_PRIO137_PRIO137_OFFSET 0
+#define RV_PLIC_PRIO137_PRIO137_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO137_PRIO137_MASK, .index = RV_PLIC_PRIO137_PRIO137_OFFSET })
+
+// Interrupt Source 138 Priority
+#define RV_PLIC_PRIO138_REG_OFFSET 0x228
+#define RV_PLIC_PRIO138_REG_RESVAL 0x0
+#define RV_PLIC_PRIO138_PRIO138_MASK 0x3
+#define RV_PLIC_PRIO138_PRIO138_OFFSET 0
+#define RV_PLIC_PRIO138_PRIO138_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO138_PRIO138_MASK, .index = RV_PLIC_PRIO138_PRIO138_OFFSET })
+
+// Interrupt Source 139 Priority
+#define RV_PLIC_PRIO139_REG_OFFSET 0x22c
+#define RV_PLIC_PRIO139_REG_RESVAL 0x0
+#define RV_PLIC_PRIO139_PRIO139_MASK 0x3
+#define RV_PLIC_PRIO139_PRIO139_OFFSET 0
+#define RV_PLIC_PRIO139_PRIO139_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO139_PRIO139_MASK, .index = RV_PLIC_PRIO139_PRIO139_OFFSET })
+
+// Interrupt Source 140 Priority
+#define RV_PLIC_PRIO140_REG_OFFSET 0x230
+#define RV_PLIC_PRIO140_REG_RESVAL 0x0
+#define RV_PLIC_PRIO140_PRIO140_MASK 0x3
+#define RV_PLIC_PRIO140_PRIO140_OFFSET 0
+#define RV_PLIC_PRIO140_PRIO140_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO140_PRIO140_MASK, .index = RV_PLIC_PRIO140_PRIO140_OFFSET })
+
+// Interrupt Source 141 Priority
+#define RV_PLIC_PRIO141_REG_OFFSET 0x234
+#define RV_PLIC_PRIO141_REG_RESVAL 0x0
+#define RV_PLIC_PRIO141_PRIO141_MASK 0x3
+#define RV_PLIC_PRIO141_PRIO141_OFFSET 0
+#define RV_PLIC_PRIO141_PRIO141_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO141_PRIO141_MASK, .index = RV_PLIC_PRIO141_PRIO141_OFFSET })
+
+// Interrupt Source 142 Priority
+#define RV_PLIC_PRIO142_REG_OFFSET 0x238
+#define RV_PLIC_PRIO142_REG_RESVAL 0x0
+#define RV_PLIC_PRIO142_PRIO142_MASK 0x3
+#define RV_PLIC_PRIO142_PRIO142_OFFSET 0
+#define RV_PLIC_PRIO142_PRIO142_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO142_PRIO142_MASK, .index = RV_PLIC_PRIO142_PRIO142_OFFSET })
+
+// Interrupt Source 143 Priority
+#define RV_PLIC_PRIO143_REG_OFFSET 0x23c
+#define RV_PLIC_PRIO143_REG_RESVAL 0x0
+#define RV_PLIC_PRIO143_PRIO143_MASK 0x3
+#define RV_PLIC_PRIO143_PRIO143_OFFSET 0
+#define RV_PLIC_PRIO143_PRIO143_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO143_PRIO143_MASK, .index = RV_PLIC_PRIO143_PRIO143_OFFSET })
+
+// Interrupt Source 144 Priority
+#define RV_PLIC_PRIO144_REG_OFFSET 0x240
+#define RV_PLIC_PRIO144_REG_RESVAL 0x0
+#define RV_PLIC_PRIO144_PRIO144_MASK 0x3
+#define RV_PLIC_PRIO144_PRIO144_OFFSET 0
+#define RV_PLIC_PRIO144_PRIO144_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO144_PRIO144_MASK, .index = RV_PLIC_PRIO144_PRIO144_OFFSET })
+
+// Interrupt Source 145 Priority
+#define RV_PLIC_PRIO145_REG_OFFSET 0x244
+#define RV_PLIC_PRIO145_REG_RESVAL 0x0
+#define RV_PLIC_PRIO145_PRIO145_MASK 0x3
+#define RV_PLIC_PRIO145_PRIO145_OFFSET 0
+#define RV_PLIC_PRIO145_PRIO145_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO145_PRIO145_MASK, .index = RV_PLIC_PRIO145_PRIO145_OFFSET })
+
+// Interrupt Source 146 Priority
+#define RV_PLIC_PRIO146_REG_OFFSET 0x248
+#define RV_PLIC_PRIO146_REG_RESVAL 0x0
+#define RV_PLIC_PRIO146_PRIO146_MASK 0x3
+#define RV_PLIC_PRIO146_PRIO146_OFFSET 0
+#define RV_PLIC_PRIO146_PRIO146_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO146_PRIO146_MASK, .index = RV_PLIC_PRIO146_PRIO146_OFFSET })
+
+// Interrupt Source 147 Priority
+#define RV_PLIC_PRIO147_REG_OFFSET 0x24c
+#define RV_PLIC_PRIO147_REG_RESVAL 0x0
+#define RV_PLIC_PRIO147_PRIO147_MASK 0x3
+#define RV_PLIC_PRIO147_PRIO147_OFFSET 0
+#define RV_PLIC_PRIO147_PRIO147_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO147_PRIO147_MASK, .index = RV_PLIC_PRIO147_PRIO147_OFFSET })
+
+// Interrupt Source 148 Priority
+#define RV_PLIC_PRIO148_REG_OFFSET 0x250
+#define RV_PLIC_PRIO148_REG_RESVAL 0x0
+#define RV_PLIC_PRIO148_PRIO148_MASK 0x3
+#define RV_PLIC_PRIO148_PRIO148_OFFSET 0
+#define RV_PLIC_PRIO148_PRIO148_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO148_PRIO148_MASK, .index = RV_PLIC_PRIO148_PRIO148_OFFSET })
+
+// Interrupt Source 149 Priority
+#define RV_PLIC_PRIO149_REG_OFFSET 0x254
+#define RV_PLIC_PRIO149_REG_RESVAL 0x0
+#define RV_PLIC_PRIO149_PRIO149_MASK 0x3
+#define RV_PLIC_PRIO149_PRIO149_OFFSET 0
+#define RV_PLIC_PRIO149_PRIO149_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO149_PRIO149_MASK, .index = RV_PLIC_PRIO149_PRIO149_OFFSET })
+
+// Interrupt Source 150 Priority
+#define RV_PLIC_PRIO150_REG_OFFSET 0x258
+#define RV_PLIC_PRIO150_REG_RESVAL 0x0
+#define RV_PLIC_PRIO150_PRIO150_MASK 0x3
+#define RV_PLIC_PRIO150_PRIO150_OFFSET 0
+#define RV_PLIC_PRIO150_PRIO150_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO150_PRIO150_MASK, .index = RV_PLIC_PRIO150_PRIO150_OFFSET })
+
+// Interrupt Source 151 Priority
+#define RV_PLIC_PRIO151_REG_OFFSET 0x25c
+#define RV_PLIC_PRIO151_REG_RESVAL 0x0
+#define RV_PLIC_PRIO151_PRIO151_MASK 0x3
+#define RV_PLIC_PRIO151_PRIO151_OFFSET 0
+#define RV_PLIC_PRIO151_PRIO151_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO151_PRIO151_MASK, .index = RV_PLIC_PRIO151_PRIO151_OFFSET })
+
+// Interrupt Source 152 Priority
+#define RV_PLIC_PRIO152_REG_OFFSET 0x260
+#define RV_PLIC_PRIO152_REG_RESVAL 0x0
+#define RV_PLIC_PRIO152_PRIO152_MASK 0x3
+#define RV_PLIC_PRIO152_PRIO152_OFFSET 0
+#define RV_PLIC_PRIO152_PRIO152_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO152_PRIO152_MASK, .index = RV_PLIC_PRIO152_PRIO152_OFFSET })
+
+// Interrupt Source 153 Priority
+#define RV_PLIC_PRIO153_REG_OFFSET 0x264
+#define RV_PLIC_PRIO153_REG_RESVAL 0x0
+#define RV_PLIC_PRIO153_PRIO153_MASK 0x3
+#define RV_PLIC_PRIO153_PRIO153_OFFSET 0
+#define RV_PLIC_PRIO153_PRIO153_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO153_PRIO153_MASK, .index = RV_PLIC_PRIO153_PRIO153_OFFSET })
+
+// Interrupt Source 154 Priority
+#define RV_PLIC_PRIO154_REG_OFFSET 0x268
+#define RV_PLIC_PRIO154_REG_RESVAL 0x0
+#define RV_PLIC_PRIO154_PRIO154_MASK 0x3
+#define RV_PLIC_PRIO154_PRIO154_OFFSET 0
+#define RV_PLIC_PRIO154_PRIO154_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO154_PRIO154_MASK, .index = RV_PLIC_PRIO154_PRIO154_OFFSET })
+
+// Interrupt Source 155 Priority
+#define RV_PLIC_PRIO155_REG_OFFSET 0x26c
+#define RV_PLIC_PRIO155_REG_RESVAL 0x0
+#define RV_PLIC_PRIO155_PRIO155_MASK 0x3
+#define RV_PLIC_PRIO155_PRIO155_OFFSET 0
+#define RV_PLIC_PRIO155_PRIO155_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO155_PRIO155_MASK, .index = RV_PLIC_PRIO155_PRIO155_OFFSET })
+
+// Interrupt Source 156 Priority
+#define RV_PLIC_PRIO156_REG_OFFSET 0x270
+#define RV_PLIC_PRIO156_REG_RESVAL 0x0
+#define RV_PLIC_PRIO156_PRIO156_MASK 0x3
+#define RV_PLIC_PRIO156_PRIO156_OFFSET 0
+#define RV_PLIC_PRIO156_PRIO156_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO156_PRIO156_MASK, .index = RV_PLIC_PRIO156_PRIO156_OFFSET })
+
+// Interrupt Source 157 Priority
+#define RV_PLIC_PRIO157_REG_OFFSET 0x274
+#define RV_PLIC_PRIO157_REG_RESVAL 0x0
+#define RV_PLIC_PRIO157_PRIO157_MASK 0x3
+#define RV_PLIC_PRIO157_PRIO157_OFFSET 0
+#define RV_PLIC_PRIO157_PRIO157_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO157_PRIO157_MASK, .index = RV_PLIC_PRIO157_PRIO157_OFFSET })
+
+// Interrupt Source 158 Priority
+#define RV_PLIC_PRIO158_REG_OFFSET 0x278
+#define RV_PLIC_PRIO158_REG_RESVAL 0x0
+#define RV_PLIC_PRIO158_PRIO158_MASK 0x3
+#define RV_PLIC_PRIO158_PRIO158_OFFSET 0
+#define RV_PLIC_PRIO158_PRIO158_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO158_PRIO158_MASK, .index = RV_PLIC_PRIO158_PRIO158_OFFSET })
+
+// Interrupt Source 159 Priority
+#define RV_PLIC_PRIO159_REG_OFFSET 0x27c
+#define RV_PLIC_PRIO159_REG_RESVAL 0x0
+#define RV_PLIC_PRIO159_PRIO159_MASK 0x3
+#define RV_PLIC_PRIO159_PRIO159_OFFSET 0
+#define RV_PLIC_PRIO159_PRIO159_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO159_PRIO159_MASK, .index = RV_PLIC_PRIO159_PRIO159_OFFSET })
+
+// Interrupt Source 160 Priority
+#define RV_PLIC_PRIO160_REG_OFFSET 0x280
+#define RV_PLIC_PRIO160_REG_RESVAL 0x0
+#define RV_PLIC_PRIO160_PRIO160_MASK 0x3
+#define RV_PLIC_PRIO160_PRIO160_OFFSET 0
+#define RV_PLIC_PRIO160_PRIO160_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO160_PRIO160_MASK, .index = RV_PLIC_PRIO160_PRIO160_OFFSET })
+
+// Interrupt Source 161 Priority
+#define RV_PLIC_PRIO161_REG_OFFSET 0x284
+#define RV_PLIC_PRIO161_REG_RESVAL 0x0
+#define RV_PLIC_PRIO161_PRIO161_MASK 0x3
+#define RV_PLIC_PRIO161_PRIO161_OFFSET 0
+#define RV_PLIC_PRIO161_PRIO161_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO161_PRIO161_MASK, .index = RV_PLIC_PRIO161_PRIO161_OFFSET })
+
+// Interrupt Source 162 Priority
+#define RV_PLIC_PRIO162_REG_OFFSET 0x288
+#define RV_PLIC_PRIO162_REG_RESVAL 0x0
+#define RV_PLIC_PRIO162_PRIO162_MASK 0x3
+#define RV_PLIC_PRIO162_PRIO162_OFFSET 0
+#define RV_PLIC_PRIO162_PRIO162_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO162_PRIO162_MASK, .index = RV_PLIC_PRIO162_PRIO162_OFFSET })
+
+// Interrupt Source 163 Priority
+#define RV_PLIC_PRIO163_REG_OFFSET 0x28c
+#define RV_PLIC_PRIO163_REG_RESVAL 0x0
+#define RV_PLIC_PRIO163_PRIO163_MASK 0x3
+#define RV_PLIC_PRIO163_PRIO163_OFFSET 0
+#define RV_PLIC_PRIO163_PRIO163_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO163_PRIO163_MASK, .index = RV_PLIC_PRIO163_PRIO163_OFFSET })
+
+// Interrupt Source 164 Priority
+#define RV_PLIC_PRIO164_REG_OFFSET 0x290
+#define RV_PLIC_PRIO164_REG_RESVAL 0x0
+#define RV_PLIC_PRIO164_PRIO164_MASK 0x3
+#define RV_PLIC_PRIO164_PRIO164_OFFSET 0
+#define RV_PLIC_PRIO164_PRIO164_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO164_PRIO164_MASK, .index = RV_PLIC_PRIO164_PRIO164_OFFSET })
+
+// Interrupt Source 165 Priority
+#define RV_PLIC_PRIO165_REG_OFFSET 0x294
+#define RV_PLIC_PRIO165_REG_RESVAL 0x0
+#define RV_PLIC_PRIO165_PRIO165_MASK 0x3
+#define RV_PLIC_PRIO165_PRIO165_OFFSET 0
+#define RV_PLIC_PRIO165_PRIO165_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO165_PRIO165_MASK, .index = RV_PLIC_PRIO165_PRIO165_OFFSET })
+
+// Interrupt Source 166 Priority
+#define RV_PLIC_PRIO166_REG_OFFSET 0x298
+#define RV_PLIC_PRIO166_REG_RESVAL 0x0
+#define RV_PLIC_PRIO166_PRIO166_MASK 0x3
+#define RV_PLIC_PRIO166_PRIO166_OFFSET 0
+#define RV_PLIC_PRIO166_PRIO166_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO166_PRIO166_MASK, .index = RV_PLIC_PRIO166_PRIO166_OFFSET })
+
+// Interrupt Source 167 Priority
+#define RV_PLIC_PRIO167_REG_OFFSET 0x29c
+#define RV_PLIC_PRIO167_REG_RESVAL 0x0
+#define RV_PLIC_PRIO167_PRIO167_MASK 0x3
+#define RV_PLIC_PRIO167_PRIO167_OFFSET 0
+#define RV_PLIC_PRIO167_PRIO167_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO167_PRIO167_MASK, .index = RV_PLIC_PRIO167_PRIO167_OFFSET })
+
+// Interrupt Source 168 Priority
+#define RV_PLIC_PRIO168_REG_OFFSET 0x2a0
+#define RV_PLIC_PRIO168_REG_RESVAL 0x0
+#define RV_PLIC_PRIO168_PRIO168_MASK 0x3
+#define RV_PLIC_PRIO168_PRIO168_OFFSET 0
+#define RV_PLIC_PRIO168_PRIO168_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO168_PRIO168_MASK, .index = RV_PLIC_PRIO168_PRIO168_OFFSET })
+
+// Interrupt Source 169 Priority
+#define RV_PLIC_PRIO169_REG_OFFSET 0x2a4
+#define RV_PLIC_PRIO169_REG_RESVAL 0x0
+#define RV_PLIC_PRIO169_PRIO169_MASK 0x3
+#define RV_PLIC_PRIO169_PRIO169_OFFSET 0
+#define RV_PLIC_PRIO169_PRIO169_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO169_PRIO169_MASK, .index = RV_PLIC_PRIO169_PRIO169_OFFSET })
+
+// Interrupt Source 170 Priority
+#define RV_PLIC_PRIO170_REG_OFFSET 0x2a8
+#define RV_PLIC_PRIO170_REG_RESVAL 0x0
+#define RV_PLIC_PRIO170_PRIO170_MASK 0x3
+#define RV_PLIC_PRIO170_PRIO170_OFFSET 0
+#define RV_PLIC_PRIO170_PRIO170_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO170_PRIO170_MASK, .index = RV_PLIC_PRIO170_PRIO170_OFFSET })
+
+// Interrupt Source 171 Priority
+#define RV_PLIC_PRIO171_REG_OFFSET 0x2ac
+#define RV_PLIC_PRIO171_REG_RESVAL 0x0
+#define RV_PLIC_PRIO171_PRIO171_MASK 0x3
+#define RV_PLIC_PRIO171_PRIO171_OFFSET 0
+#define RV_PLIC_PRIO171_PRIO171_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO171_PRIO171_MASK, .index = RV_PLIC_PRIO171_PRIO171_OFFSET })
+
+// Interrupt Source 172 Priority
+#define RV_PLIC_PRIO172_REG_OFFSET 0x2b0
+#define RV_PLIC_PRIO172_REG_RESVAL 0x0
+#define RV_PLIC_PRIO172_PRIO172_MASK 0x3
+#define RV_PLIC_PRIO172_PRIO172_OFFSET 0
+#define RV_PLIC_PRIO172_PRIO172_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO172_PRIO172_MASK, .index = RV_PLIC_PRIO172_PRIO172_OFFSET })
+
+// Interrupt Source 173 Priority
+#define RV_PLIC_PRIO173_REG_OFFSET 0x2b4
+#define RV_PLIC_PRIO173_REG_RESVAL 0x0
+#define RV_PLIC_PRIO173_PRIO173_MASK 0x3
+#define RV_PLIC_PRIO173_PRIO173_OFFSET 0
+#define RV_PLIC_PRIO173_PRIO173_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO173_PRIO173_MASK, .index = RV_PLIC_PRIO173_PRIO173_OFFSET })
+
+// Interrupt Source 174 Priority
+#define RV_PLIC_PRIO174_REG_OFFSET 0x2b8
+#define RV_PLIC_PRIO174_REG_RESVAL 0x0
+#define RV_PLIC_PRIO174_PRIO174_MASK 0x3
+#define RV_PLIC_PRIO174_PRIO174_OFFSET 0
+#define RV_PLIC_PRIO174_PRIO174_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO174_PRIO174_MASK, .index = RV_PLIC_PRIO174_PRIO174_OFFSET })
+
+// Interrupt Source 175 Priority
+#define RV_PLIC_PRIO175_REG_OFFSET 0x2bc
+#define RV_PLIC_PRIO175_REG_RESVAL 0x0
+#define RV_PLIC_PRIO175_PRIO175_MASK 0x3
+#define RV_PLIC_PRIO175_PRIO175_OFFSET 0
+#define RV_PLIC_PRIO175_PRIO175_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO175_PRIO175_MASK, .index = RV_PLIC_PRIO175_PRIO175_OFFSET })
+
+// Interrupt Source 176 Priority
+#define RV_PLIC_PRIO176_REG_OFFSET 0x2c0
+#define RV_PLIC_PRIO176_REG_RESVAL 0x0
+#define RV_PLIC_PRIO176_PRIO176_MASK 0x3
+#define RV_PLIC_PRIO176_PRIO176_OFFSET 0
+#define RV_PLIC_PRIO176_PRIO176_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO176_PRIO176_MASK, .index = RV_PLIC_PRIO176_PRIO176_OFFSET })
+
+// Interrupt Source 177 Priority
+#define RV_PLIC_PRIO177_REG_OFFSET 0x2c4
+#define RV_PLIC_PRIO177_REG_RESVAL 0x0
+#define RV_PLIC_PRIO177_PRIO177_MASK 0x3
+#define RV_PLIC_PRIO177_PRIO177_OFFSET 0
+#define RV_PLIC_PRIO177_PRIO177_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO177_PRIO177_MASK, .index = RV_PLIC_PRIO177_PRIO177_OFFSET })
+
+// Interrupt Source 178 Priority
+#define RV_PLIC_PRIO178_REG_OFFSET 0x2c8
+#define RV_PLIC_PRIO178_REG_RESVAL 0x0
+#define RV_PLIC_PRIO178_PRIO178_MASK 0x3
+#define RV_PLIC_PRIO178_PRIO178_OFFSET 0
+#define RV_PLIC_PRIO178_PRIO178_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO178_PRIO178_MASK, .index = RV_PLIC_PRIO178_PRIO178_OFFSET })
+
+// Interrupt Source 179 Priority
+#define RV_PLIC_PRIO179_REG_OFFSET 0x2cc
+#define RV_PLIC_PRIO179_REG_RESVAL 0x0
+#define RV_PLIC_PRIO179_PRIO179_MASK 0x3
+#define RV_PLIC_PRIO179_PRIO179_OFFSET 0
+#define RV_PLIC_PRIO179_PRIO179_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO179_PRIO179_MASK, .index = RV_PLIC_PRIO179_PRIO179_OFFSET })
+
+// Interrupt Source 180 Priority
+#define RV_PLIC_PRIO180_REG_OFFSET 0x2d0
+#define RV_PLIC_PRIO180_REG_RESVAL 0x0
+#define RV_PLIC_PRIO180_PRIO180_MASK 0x3
+#define RV_PLIC_PRIO180_PRIO180_OFFSET 0
+#define RV_PLIC_PRIO180_PRIO180_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO180_PRIO180_MASK, .index = RV_PLIC_PRIO180_PRIO180_OFFSET })
+
+// Interrupt Source 181 Priority
+#define RV_PLIC_PRIO181_REG_OFFSET 0x2d4
+#define RV_PLIC_PRIO181_REG_RESVAL 0x0
+#define RV_PLIC_PRIO181_PRIO181_MASK 0x3
+#define RV_PLIC_PRIO181_PRIO181_OFFSET 0
+#define RV_PLIC_PRIO181_PRIO181_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO181_PRIO181_MASK, .index = RV_PLIC_PRIO181_PRIO181_OFFSET })
+
+// Interrupt Source 182 Priority
+#define RV_PLIC_PRIO182_REG_OFFSET 0x2d8
+#define RV_PLIC_PRIO182_REG_RESVAL 0x0
+#define RV_PLIC_PRIO182_PRIO182_MASK 0x3
+#define RV_PLIC_PRIO182_PRIO182_OFFSET 0
+#define RV_PLIC_PRIO182_PRIO182_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO182_PRIO182_MASK, .index = RV_PLIC_PRIO182_PRIO182_OFFSET })
+
+// Interrupt Source 183 Priority
+#define RV_PLIC_PRIO183_REG_OFFSET 0x2dc
+#define RV_PLIC_PRIO183_REG_RESVAL 0x0
+#define RV_PLIC_PRIO183_PRIO183_MASK 0x3
+#define RV_PLIC_PRIO183_PRIO183_OFFSET 0
+#define RV_PLIC_PRIO183_PRIO183_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO183_PRIO183_MASK, .index = RV_PLIC_PRIO183_PRIO183_OFFSET })
+
+// Interrupt Source 184 Priority
+#define RV_PLIC_PRIO184_REG_OFFSET 0x2e0
+#define RV_PLIC_PRIO184_REG_RESVAL 0x0
+#define RV_PLIC_PRIO184_PRIO184_MASK 0x3
+#define RV_PLIC_PRIO184_PRIO184_OFFSET 0
+#define RV_PLIC_PRIO184_PRIO184_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO184_PRIO184_MASK, .index = RV_PLIC_PRIO184_PRIO184_OFFSET })
+
+// Interrupt Source 185 Priority
+#define RV_PLIC_PRIO185_REG_OFFSET 0x2e4
+#define RV_PLIC_PRIO185_REG_RESVAL 0x0
+#define RV_PLIC_PRIO185_PRIO185_MASK 0x3
+#define RV_PLIC_PRIO185_PRIO185_OFFSET 0
+#define RV_PLIC_PRIO185_PRIO185_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO185_PRIO185_MASK, .index = RV_PLIC_PRIO185_PRIO185_OFFSET })
+
+// Interrupt Source 186 Priority
+#define RV_PLIC_PRIO186_REG_OFFSET 0x2e8
+#define RV_PLIC_PRIO186_REG_RESVAL 0x0
+#define RV_PLIC_PRIO186_PRIO186_MASK 0x3
+#define RV_PLIC_PRIO186_PRIO186_OFFSET 0
+#define RV_PLIC_PRIO186_PRIO186_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO186_PRIO186_MASK, .index = RV_PLIC_PRIO186_PRIO186_OFFSET })
+
+// Interrupt Source 187 Priority
+#define RV_PLIC_PRIO187_REG_OFFSET 0x2ec
+#define RV_PLIC_PRIO187_REG_RESVAL 0x0
+#define RV_PLIC_PRIO187_PRIO187_MASK 0x3
+#define RV_PLIC_PRIO187_PRIO187_OFFSET 0
+#define RV_PLIC_PRIO187_PRIO187_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO187_PRIO187_MASK, .index = RV_PLIC_PRIO187_PRIO187_OFFSET })
+
+// Interrupt Source 188 Priority
+#define RV_PLIC_PRIO188_REG_OFFSET 0x2f0
+#define RV_PLIC_PRIO188_REG_RESVAL 0x0
+#define RV_PLIC_PRIO188_PRIO188_MASK 0x3
+#define RV_PLIC_PRIO188_PRIO188_OFFSET 0
+#define RV_PLIC_PRIO188_PRIO188_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO188_PRIO188_MASK, .index = RV_PLIC_PRIO188_PRIO188_OFFSET })
+
+// Interrupt Source 189 Priority
+#define RV_PLIC_PRIO189_REG_OFFSET 0x2f4
+#define RV_PLIC_PRIO189_REG_RESVAL 0x0
+#define RV_PLIC_PRIO189_PRIO189_MASK 0x3
+#define RV_PLIC_PRIO189_PRIO189_OFFSET 0
+#define RV_PLIC_PRIO189_PRIO189_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_PRIO189_PRIO189_MASK, .index = RV_PLIC_PRIO189_PRIO189_OFFSET })
+
+// Interrupt Pending (common parameters)
+#define RV_PLIC_IP_P_FIELD_WIDTH 1
+#define RV_PLIC_IP_MULTIREG_COUNT 6
+
+// Interrupt Pending
+#define RV_PLIC_IP_0_REG_OFFSET 0x1000
+#define RV_PLIC_IP_0_REG_RESVAL 0x0
+#define RV_PLIC_IP_0_P_0_BIT 0
+#define RV_PLIC_IP_0_P_1_BIT 1
+#define RV_PLIC_IP_0_P_2_BIT 2
+#define RV_PLIC_IP_0_P_3_BIT 3
+#define RV_PLIC_IP_0_P_4_BIT 4
+#define RV_PLIC_IP_0_P_5_BIT 5
+#define RV_PLIC_IP_0_P_6_BIT 6
+#define RV_PLIC_IP_0_P_7_BIT 7
+#define RV_PLIC_IP_0_P_8_BIT 8
+#define RV_PLIC_IP_0_P_9_BIT 9
+#define RV_PLIC_IP_0_P_10_BIT 10
+#define RV_PLIC_IP_0_P_11_BIT 11
+#define RV_PLIC_IP_0_P_12_BIT 12
+#define RV_PLIC_IP_0_P_13_BIT 13
+#define RV_PLIC_IP_0_P_14_BIT 14
+#define RV_PLIC_IP_0_P_15_BIT 15
+#define RV_PLIC_IP_0_P_16_BIT 16
+#define RV_PLIC_IP_0_P_17_BIT 17
+#define RV_PLIC_IP_0_P_18_BIT 18
+#define RV_PLIC_IP_0_P_19_BIT 19
+#define RV_PLIC_IP_0_P_20_BIT 20
+#define RV_PLIC_IP_0_P_21_BIT 21
+#define RV_PLIC_IP_0_P_22_BIT 22
+#define RV_PLIC_IP_0_P_23_BIT 23
+#define RV_PLIC_IP_0_P_24_BIT 24
+#define RV_PLIC_IP_0_P_25_BIT 25
+#define RV_PLIC_IP_0_P_26_BIT 26
+#define RV_PLIC_IP_0_P_27_BIT 27
+#define RV_PLIC_IP_0_P_28_BIT 28
+#define RV_PLIC_IP_0_P_29_BIT 29
+#define RV_PLIC_IP_0_P_30_BIT 30
+#define RV_PLIC_IP_0_P_31_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_1_REG_OFFSET 0x1004
+#define RV_PLIC_IP_1_REG_RESVAL 0x0
+#define RV_PLIC_IP_1_P_32_BIT 0
+#define RV_PLIC_IP_1_P_33_BIT 1
+#define RV_PLIC_IP_1_P_34_BIT 2
+#define RV_PLIC_IP_1_P_35_BIT 3
+#define RV_PLIC_IP_1_P_36_BIT 4
+#define RV_PLIC_IP_1_P_37_BIT 5
+#define RV_PLIC_IP_1_P_38_BIT 6
+#define RV_PLIC_IP_1_P_39_BIT 7
+#define RV_PLIC_IP_1_P_40_BIT 8
+#define RV_PLIC_IP_1_P_41_BIT 9
+#define RV_PLIC_IP_1_P_42_BIT 10
+#define RV_PLIC_IP_1_P_43_BIT 11
+#define RV_PLIC_IP_1_P_44_BIT 12
+#define RV_PLIC_IP_1_P_45_BIT 13
+#define RV_PLIC_IP_1_P_46_BIT 14
+#define RV_PLIC_IP_1_P_47_BIT 15
+#define RV_PLIC_IP_1_P_48_BIT 16
+#define RV_PLIC_IP_1_P_49_BIT 17
+#define RV_PLIC_IP_1_P_50_BIT 18
+#define RV_PLIC_IP_1_P_51_BIT 19
+#define RV_PLIC_IP_1_P_52_BIT 20
+#define RV_PLIC_IP_1_P_53_BIT 21
+#define RV_PLIC_IP_1_P_54_BIT 22
+#define RV_PLIC_IP_1_P_55_BIT 23
+#define RV_PLIC_IP_1_P_56_BIT 24
+#define RV_PLIC_IP_1_P_57_BIT 25
+#define RV_PLIC_IP_1_P_58_BIT 26
+#define RV_PLIC_IP_1_P_59_BIT 27
+#define RV_PLIC_IP_1_P_60_BIT 28
+#define RV_PLIC_IP_1_P_61_BIT 29
+#define RV_PLIC_IP_1_P_62_BIT 30
+#define RV_PLIC_IP_1_P_63_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_2_REG_OFFSET 0x1008
+#define RV_PLIC_IP_2_REG_RESVAL 0x0
+#define RV_PLIC_IP_2_P_64_BIT 0
+#define RV_PLIC_IP_2_P_65_BIT 1
+#define RV_PLIC_IP_2_P_66_BIT 2
+#define RV_PLIC_IP_2_P_67_BIT 3
+#define RV_PLIC_IP_2_P_68_BIT 4
+#define RV_PLIC_IP_2_P_69_BIT 5
+#define RV_PLIC_IP_2_P_70_BIT 6
+#define RV_PLIC_IP_2_P_71_BIT 7
+#define RV_PLIC_IP_2_P_72_BIT 8
+#define RV_PLIC_IP_2_P_73_BIT 9
+#define RV_PLIC_IP_2_P_74_BIT 10
+#define RV_PLIC_IP_2_P_75_BIT 11
+#define RV_PLIC_IP_2_P_76_BIT 12
+#define RV_PLIC_IP_2_P_77_BIT 13
+#define RV_PLIC_IP_2_P_78_BIT 14
+#define RV_PLIC_IP_2_P_79_BIT 15
+#define RV_PLIC_IP_2_P_80_BIT 16
+#define RV_PLIC_IP_2_P_81_BIT 17
+#define RV_PLIC_IP_2_P_82_BIT 18
+#define RV_PLIC_IP_2_P_83_BIT 19
+#define RV_PLIC_IP_2_P_84_BIT 20
+#define RV_PLIC_IP_2_P_85_BIT 21
+#define RV_PLIC_IP_2_P_86_BIT 22
+#define RV_PLIC_IP_2_P_87_BIT 23
+#define RV_PLIC_IP_2_P_88_BIT 24
+#define RV_PLIC_IP_2_P_89_BIT 25
+#define RV_PLIC_IP_2_P_90_BIT 26
+#define RV_PLIC_IP_2_P_91_BIT 27
+#define RV_PLIC_IP_2_P_92_BIT 28
+#define RV_PLIC_IP_2_P_93_BIT 29
+#define RV_PLIC_IP_2_P_94_BIT 30
+#define RV_PLIC_IP_2_P_95_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_3_REG_OFFSET 0x100c
+#define RV_PLIC_IP_3_REG_RESVAL 0x0
+#define RV_PLIC_IP_3_P_96_BIT 0
+#define RV_PLIC_IP_3_P_97_BIT 1
+#define RV_PLIC_IP_3_P_98_BIT 2
+#define RV_PLIC_IP_3_P_99_BIT 3
+#define RV_PLIC_IP_3_P_100_BIT 4
+#define RV_PLIC_IP_3_P_101_BIT 5
+#define RV_PLIC_IP_3_P_102_BIT 6
+#define RV_PLIC_IP_3_P_103_BIT 7
+#define RV_PLIC_IP_3_P_104_BIT 8
+#define RV_PLIC_IP_3_P_105_BIT 9
+#define RV_PLIC_IP_3_P_106_BIT 10
+#define RV_PLIC_IP_3_P_107_BIT 11
+#define RV_PLIC_IP_3_P_108_BIT 12
+#define RV_PLIC_IP_3_P_109_BIT 13
+#define RV_PLIC_IP_3_P_110_BIT 14
+#define RV_PLIC_IP_3_P_111_BIT 15
+#define RV_PLIC_IP_3_P_112_BIT 16
+#define RV_PLIC_IP_3_P_113_BIT 17
+#define RV_PLIC_IP_3_P_114_BIT 18
+#define RV_PLIC_IP_3_P_115_BIT 19
+#define RV_PLIC_IP_3_P_116_BIT 20
+#define RV_PLIC_IP_3_P_117_BIT 21
+#define RV_PLIC_IP_3_P_118_BIT 22
+#define RV_PLIC_IP_3_P_119_BIT 23
+#define RV_PLIC_IP_3_P_120_BIT 24
+#define RV_PLIC_IP_3_P_121_BIT 25
+#define RV_PLIC_IP_3_P_122_BIT 26
+#define RV_PLIC_IP_3_P_123_BIT 27
+#define RV_PLIC_IP_3_P_124_BIT 28
+#define RV_PLIC_IP_3_P_125_BIT 29
+#define RV_PLIC_IP_3_P_126_BIT 30
+#define RV_PLIC_IP_3_P_127_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_4_REG_OFFSET 0x1010
+#define RV_PLIC_IP_4_REG_RESVAL 0x0
+#define RV_PLIC_IP_4_P_128_BIT 0
+#define RV_PLIC_IP_4_P_129_BIT 1
+#define RV_PLIC_IP_4_P_130_BIT 2
+#define RV_PLIC_IP_4_P_131_BIT 3
+#define RV_PLIC_IP_4_P_132_BIT 4
+#define RV_PLIC_IP_4_P_133_BIT 5
+#define RV_PLIC_IP_4_P_134_BIT 6
+#define RV_PLIC_IP_4_P_135_BIT 7
+#define RV_PLIC_IP_4_P_136_BIT 8
+#define RV_PLIC_IP_4_P_137_BIT 9
+#define RV_PLIC_IP_4_P_138_BIT 10
+#define RV_PLIC_IP_4_P_139_BIT 11
+#define RV_PLIC_IP_4_P_140_BIT 12
+#define RV_PLIC_IP_4_P_141_BIT 13
+#define RV_PLIC_IP_4_P_142_BIT 14
+#define RV_PLIC_IP_4_P_143_BIT 15
+#define RV_PLIC_IP_4_P_144_BIT 16
+#define RV_PLIC_IP_4_P_145_BIT 17
+#define RV_PLIC_IP_4_P_146_BIT 18
+#define RV_PLIC_IP_4_P_147_BIT 19
+#define RV_PLIC_IP_4_P_148_BIT 20
+#define RV_PLIC_IP_4_P_149_BIT 21
+#define RV_PLIC_IP_4_P_150_BIT 22
+#define RV_PLIC_IP_4_P_151_BIT 23
+#define RV_PLIC_IP_4_P_152_BIT 24
+#define RV_PLIC_IP_4_P_153_BIT 25
+#define RV_PLIC_IP_4_P_154_BIT 26
+#define RV_PLIC_IP_4_P_155_BIT 27
+#define RV_PLIC_IP_4_P_156_BIT 28
+#define RV_PLIC_IP_4_P_157_BIT 29
+#define RV_PLIC_IP_4_P_158_BIT 30
+#define RV_PLIC_IP_4_P_159_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_IP_5_REG_OFFSET 0x1014
+#define RV_PLIC_IP_5_REG_RESVAL 0x0
+#define RV_PLIC_IP_5_P_160_BIT 0
+#define RV_PLIC_IP_5_P_161_BIT 1
+#define RV_PLIC_IP_5_P_162_BIT 2
+#define RV_PLIC_IP_5_P_163_BIT 3
+#define RV_PLIC_IP_5_P_164_BIT 4
+#define RV_PLIC_IP_5_P_165_BIT 5
+#define RV_PLIC_IP_5_P_166_BIT 6
+#define RV_PLIC_IP_5_P_167_BIT 7
+#define RV_PLIC_IP_5_P_168_BIT 8
+#define RV_PLIC_IP_5_P_169_BIT 9
+#define RV_PLIC_IP_5_P_170_BIT 10
+#define RV_PLIC_IP_5_P_171_BIT 11
+#define RV_PLIC_IP_5_P_172_BIT 12
+#define RV_PLIC_IP_5_P_173_BIT 13
+#define RV_PLIC_IP_5_P_174_BIT 14
+#define RV_PLIC_IP_5_P_175_BIT 15
+#define RV_PLIC_IP_5_P_176_BIT 16
+#define RV_PLIC_IP_5_P_177_BIT 17
+#define RV_PLIC_IP_5_P_178_BIT 18
+#define RV_PLIC_IP_5_P_179_BIT 19
+#define RV_PLIC_IP_5_P_180_BIT 20
+#define RV_PLIC_IP_5_P_181_BIT 21
+#define RV_PLIC_IP_5_P_182_BIT 22
+#define RV_PLIC_IP_5_P_183_BIT 23
+#define RV_PLIC_IP_5_P_184_BIT 24
+#define RV_PLIC_IP_5_P_185_BIT 25
+#define RV_PLIC_IP_5_P_186_BIT 26
+#define RV_PLIC_IP_5_P_187_BIT 27
+#define RV_PLIC_IP_5_P_188_BIT 28
+#define RV_PLIC_IP_5_P_189_BIT 29
+
+// Interrupt Enable for Target 0 (common parameters)
+#define RV_PLIC_IE0_E_FIELD_WIDTH 1
+#define RV_PLIC_IE0_MULTIREG_COUNT 6
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_0_REG_OFFSET 0x2000
+#define RV_PLIC_IE0_0_REG_RESVAL 0x0
+#define RV_PLIC_IE0_0_E_0_BIT 0
+#define RV_PLIC_IE0_0_E_1_BIT 1
+#define RV_PLIC_IE0_0_E_2_BIT 2
+#define RV_PLIC_IE0_0_E_3_BIT 3
+#define RV_PLIC_IE0_0_E_4_BIT 4
+#define RV_PLIC_IE0_0_E_5_BIT 5
+#define RV_PLIC_IE0_0_E_6_BIT 6
+#define RV_PLIC_IE0_0_E_7_BIT 7
+#define RV_PLIC_IE0_0_E_8_BIT 8
+#define RV_PLIC_IE0_0_E_9_BIT 9
+#define RV_PLIC_IE0_0_E_10_BIT 10
+#define RV_PLIC_IE0_0_E_11_BIT 11
+#define RV_PLIC_IE0_0_E_12_BIT 12
+#define RV_PLIC_IE0_0_E_13_BIT 13
+#define RV_PLIC_IE0_0_E_14_BIT 14
+#define RV_PLIC_IE0_0_E_15_BIT 15
+#define RV_PLIC_IE0_0_E_16_BIT 16
+#define RV_PLIC_IE0_0_E_17_BIT 17
+#define RV_PLIC_IE0_0_E_18_BIT 18
+#define RV_PLIC_IE0_0_E_19_BIT 19
+#define RV_PLIC_IE0_0_E_20_BIT 20
+#define RV_PLIC_IE0_0_E_21_BIT 21
+#define RV_PLIC_IE0_0_E_22_BIT 22
+#define RV_PLIC_IE0_0_E_23_BIT 23
+#define RV_PLIC_IE0_0_E_24_BIT 24
+#define RV_PLIC_IE0_0_E_25_BIT 25
+#define RV_PLIC_IE0_0_E_26_BIT 26
+#define RV_PLIC_IE0_0_E_27_BIT 27
+#define RV_PLIC_IE0_0_E_28_BIT 28
+#define RV_PLIC_IE0_0_E_29_BIT 29
+#define RV_PLIC_IE0_0_E_30_BIT 30
+#define RV_PLIC_IE0_0_E_31_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_1_REG_OFFSET 0x2004
+#define RV_PLIC_IE0_1_REG_RESVAL 0x0
+#define RV_PLIC_IE0_1_E_32_BIT 0
+#define RV_PLIC_IE0_1_E_33_BIT 1
+#define RV_PLIC_IE0_1_E_34_BIT 2
+#define RV_PLIC_IE0_1_E_35_BIT 3
+#define RV_PLIC_IE0_1_E_36_BIT 4
+#define RV_PLIC_IE0_1_E_37_BIT 5
+#define RV_PLIC_IE0_1_E_38_BIT 6
+#define RV_PLIC_IE0_1_E_39_BIT 7
+#define RV_PLIC_IE0_1_E_40_BIT 8
+#define RV_PLIC_IE0_1_E_41_BIT 9
+#define RV_PLIC_IE0_1_E_42_BIT 10
+#define RV_PLIC_IE0_1_E_43_BIT 11
+#define RV_PLIC_IE0_1_E_44_BIT 12
+#define RV_PLIC_IE0_1_E_45_BIT 13
+#define RV_PLIC_IE0_1_E_46_BIT 14
+#define RV_PLIC_IE0_1_E_47_BIT 15
+#define RV_PLIC_IE0_1_E_48_BIT 16
+#define RV_PLIC_IE0_1_E_49_BIT 17
+#define RV_PLIC_IE0_1_E_50_BIT 18
+#define RV_PLIC_IE0_1_E_51_BIT 19
+#define RV_PLIC_IE0_1_E_52_BIT 20
+#define RV_PLIC_IE0_1_E_53_BIT 21
+#define RV_PLIC_IE0_1_E_54_BIT 22
+#define RV_PLIC_IE0_1_E_55_BIT 23
+#define RV_PLIC_IE0_1_E_56_BIT 24
+#define RV_PLIC_IE0_1_E_57_BIT 25
+#define RV_PLIC_IE0_1_E_58_BIT 26
+#define RV_PLIC_IE0_1_E_59_BIT 27
+#define RV_PLIC_IE0_1_E_60_BIT 28
+#define RV_PLIC_IE0_1_E_61_BIT 29
+#define RV_PLIC_IE0_1_E_62_BIT 30
+#define RV_PLIC_IE0_1_E_63_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_2_REG_OFFSET 0x2008
+#define RV_PLIC_IE0_2_REG_RESVAL 0x0
+#define RV_PLIC_IE0_2_E_64_BIT 0
+#define RV_PLIC_IE0_2_E_65_BIT 1
+#define RV_PLIC_IE0_2_E_66_BIT 2
+#define RV_PLIC_IE0_2_E_67_BIT 3
+#define RV_PLIC_IE0_2_E_68_BIT 4
+#define RV_PLIC_IE0_2_E_69_BIT 5
+#define RV_PLIC_IE0_2_E_70_BIT 6
+#define RV_PLIC_IE0_2_E_71_BIT 7
+#define RV_PLIC_IE0_2_E_72_BIT 8
+#define RV_PLIC_IE0_2_E_73_BIT 9
+#define RV_PLIC_IE0_2_E_74_BIT 10
+#define RV_PLIC_IE0_2_E_75_BIT 11
+#define RV_PLIC_IE0_2_E_76_BIT 12
+#define RV_PLIC_IE0_2_E_77_BIT 13
+#define RV_PLIC_IE0_2_E_78_BIT 14
+#define RV_PLIC_IE0_2_E_79_BIT 15
+#define RV_PLIC_IE0_2_E_80_BIT 16
+#define RV_PLIC_IE0_2_E_81_BIT 17
+#define RV_PLIC_IE0_2_E_82_BIT 18
+#define RV_PLIC_IE0_2_E_83_BIT 19
+#define RV_PLIC_IE0_2_E_84_BIT 20
+#define RV_PLIC_IE0_2_E_85_BIT 21
+#define RV_PLIC_IE0_2_E_86_BIT 22
+#define RV_PLIC_IE0_2_E_87_BIT 23
+#define RV_PLIC_IE0_2_E_88_BIT 24
+#define RV_PLIC_IE0_2_E_89_BIT 25
+#define RV_PLIC_IE0_2_E_90_BIT 26
+#define RV_PLIC_IE0_2_E_91_BIT 27
+#define RV_PLIC_IE0_2_E_92_BIT 28
+#define RV_PLIC_IE0_2_E_93_BIT 29
+#define RV_PLIC_IE0_2_E_94_BIT 30
+#define RV_PLIC_IE0_2_E_95_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_3_REG_OFFSET 0x200c
+#define RV_PLIC_IE0_3_REG_RESVAL 0x0
+#define RV_PLIC_IE0_3_E_96_BIT 0
+#define RV_PLIC_IE0_3_E_97_BIT 1
+#define RV_PLIC_IE0_3_E_98_BIT 2
+#define RV_PLIC_IE0_3_E_99_BIT 3
+#define RV_PLIC_IE0_3_E_100_BIT 4
+#define RV_PLIC_IE0_3_E_101_BIT 5
+#define RV_PLIC_IE0_3_E_102_BIT 6
+#define RV_PLIC_IE0_3_E_103_BIT 7
+#define RV_PLIC_IE0_3_E_104_BIT 8
+#define RV_PLIC_IE0_3_E_105_BIT 9
+#define RV_PLIC_IE0_3_E_106_BIT 10
+#define RV_PLIC_IE0_3_E_107_BIT 11
+#define RV_PLIC_IE0_3_E_108_BIT 12
+#define RV_PLIC_IE0_3_E_109_BIT 13
+#define RV_PLIC_IE0_3_E_110_BIT 14
+#define RV_PLIC_IE0_3_E_111_BIT 15
+#define RV_PLIC_IE0_3_E_112_BIT 16
+#define RV_PLIC_IE0_3_E_113_BIT 17
+#define RV_PLIC_IE0_3_E_114_BIT 18
+#define RV_PLIC_IE0_3_E_115_BIT 19
+#define RV_PLIC_IE0_3_E_116_BIT 20
+#define RV_PLIC_IE0_3_E_117_BIT 21
+#define RV_PLIC_IE0_3_E_118_BIT 22
+#define RV_PLIC_IE0_3_E_119_BIT 23
+#define RV_PLIC_IE0_3_E_120_BIT 24
+#define RV_PLIC_IE0_3_E_121_BIT 25
+#define RV_PLIC_IE0_3_E_122_BIT 26
+#define RV_PLIC_IE0_3_E_123_BIT 27
+#define RV_PLIC_IE0_3_E_124_BIT 28
+#define RV_PLIC_IE0_3_E_125_BIT 29
+#define RV_PLIC_IE0_3_E_126_BIT 30
+#define RV_PLIC_IE0_3_E_127_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_4_REG_OFFSET 0x2010
+#define RV_PLIC_IE0_4_REG_RESVAL 0x0
+#define RV_PLIC_IE0_4_E_128_BIT 0
+#define RV_PLIC_IE0_4_E_129_BIT 1
+#define RV_PLIC_IE0_4_E_130_BIT 2
+#define RV_PLIC_IE0_4_E_131_BIT 3
+#define RV_PLIC_IE0_4_E_132_BIT 4
+#define RV_PLIC_IE0_4_E_133_BIT 5
+#define RV_PLIC_IE0_4_E_134_BIT 6
+#define RV_PLIC_IE0_4_E_135_BIT 7
+#define RV_PLIC_IE0_4_E_136_BIT 8
+#define RV_PLIC_IE0_4_E_137_BIT 9
+#define RV_PLIC_IE0_4_E_138_BIT 10
+#define RV_PLIC_IE0_4_E_139_BIT 11
+#define RV_PLIC_IE0_4_E_140_BIT 12
+#define RV_PLIC_IE0_4_E_141_BIT 13
+#define RV_PLIC_IE0_4_E_142_BIT 14
+#define RV_PLIC_IE0_4_E_143_BIT 15
+#define RV_PLIC_IE0_4_E_144_BIT 16
+#define RV_PLIC_IE0_4_E_145_BIT 17
+#define RV_PLIC_IE0_4_E_146_BIT 18
+#define RV_PLIC_IE0_4_E_147_BIT 19
+#define RV_PLIC_IE0_4_E_148_BIT 20
+#define RV_PLIC_IE0_4_E_149_BIT 21
+#define RV_PLIC_IE0_4_E_150_BIT 22
+#define RV_PLIC_IE0_4_E_151_BIT 23
+#define RV_PLIC_IE0_4_E_152_BIT 24
+#define RV_PLIC_IE0_4_E_153_BIT 25
+#define RV_PLIC_IE0_4_E_154_BIT 26
+#define RV_PLIC_IE0_4_E_155_BIT 27
+#define RV_PLIC_IE0_4_E_156_BIT 28
+#define RV_PLIC_IE0_4_E_157_BIT 29
+#define RV_PLIC_IE0_4_E_158_BIT 30
+#define RV_PLIC_IE0_4_E_159_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_IE0_5_REG_OFFSET 0x2014
+#define RV_PLIC_IE0_5_REG_RESVAL 0x0
+#define RV_PLIC_IE0_5_E_160_BIT 0
+#define RV_PLIC_IE0_5_E_161_BIT 1
+#define RV_PLIC_IE0_5_E_162_BIT 2
+#define RV_PLIC_IE0_5_E_163_BIT 3
+#define RV_PLIC_IE0_5_E_164_BIT 4
+#define RV_PLIC_IE0_5_E_165_BIT 5
+#define RV_PLIC_IE0_5_E_166_BIT 6
+#define RV_PLIC_IE0_5_E_167_BIT 7
+#define RV_PLIC_IE0_5_E_168_BIT 8
+#define RV_PLIC_IE0_5_E_169_BIT 9
+#define RV_PLIC_IE0_5_E_170_BIT 10
+#define RV_PLIC_IE0_5_E_171_BIT 11
+#define RV_PLIC_IE0_5_E_172_BIT 12
+#define RV_PLIC_IE0_5_E_173_BIT 13
+#define RV_PLIC_IE0_5_E_174_BIT 14
+#define RV_PLIC_IE0_5_E_175_BIT 15
+#define RV_PLIC_IE0_5_E_176_BIT 16
+#define RV_PLIC_IE0_5_E_177_BIT 17
+#define RV_PLIC_IE0_5_E_178_BIT 18
+#define RV_PLIC_IE0_5_E_179_BIT 19
+#define RV_PLIC_IE0_5_E_180_BIT 20
+#define RV_PLIC_IE0_5_E_181_BIT 21
+#define RV_PLIC_IE0_5_E_182_BIT 22
+#define RV_PLIC_IE0_5_E_183_BIT 23
+#define RV_PLIC_IE0_5_E_184_BIT 24
+#define RV_PLIC_IE0_5_E_185_BIT 25
+#define RV_PLIC_IE0_5_E_186_BIT 26
+#define RV_PLIC_IE0_5_E_187_BIT 27
+#define RV_PLIC_IE0_5_E_188_BIT 28
+#define RV_PLIC_IE0_5_E_189_BIT 29
+
+// Interrupt Enable for Target 1 (common parameters)
+#define RV_PLIC_IE1_E_FIELD_WIDTH 1
+#define RV_PLIC_IE1_MULTIREG_COUNT 6
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_0_REG_OFFSET 0x2100
+#define RV_PLIC_IE1_0_REG_RESVAL 0x0
+#define RV_PLIC_IE1_0_E_0_BIT 0
+#define RV_PLIC_IE1_0_E_1_BIT 1
+#define RV_PLIC_IE1_0_E_2_BIT 2
+#define RV_PLIC_IE1_0_E_3_BIT 3
+#define RV_PLIC_IE1_0_E_4_BIT 4
+#define RV_PLIC_IE1_0_E_5_BIT 5
+#define RV_PLIC_IE1_0_E_6_BIT 6
+#define RV_PLIC_IE1_0_E_7_BIT 7
+#define RV_PLIC_IE1_0_E_8_BIT 8
+#define RV_PLIC_IE1_0_E_9_BIT 9
+#define RV_PLIC_IE1_0_E_10_BIT 10
+#define RV_PLIC_IE1_0_E_11_BIT 11
+#define RV_PLIC_IE1_0_E_12_BIT 12
+#define RV_PLIC_IE1_0_E_13_BIT 13
+#define RV_PLIC_IE1_0_E_14_BIT 14
+#define RV_PLIC_IE1_0_E_15_BIT 15
+#define RV_PLIC_IE1_0_E_16_BIT 16
+#define RV_PLIC_IE1_0_E_17_BIT 17
+#define RV_PLIC_IE1_0_E_18_BIT 18
+#define RV_PLIC_IE1_0_E_19_BIT 19
+#define RV_PLIC_IE1_0_E_20_BIT 20
+#define RV_PLIC_IE1_0_E_21_BIT 21
+#define RV_PLIC_IE1_0_E_22_BIT 22
+#define RV_PLIC_IE1_0_E_23_BIT 23
+#define RV_PLIC_IE1_0_E_24_BIT 24
+#define RV_PLIC_IE1_0_E_25_BIT 25
+#define RV_PLIC_IE1_0_E_26_BIT 26
+#define RV_PLIC_IE1_0_E_27_BIT 27
+#define RV_PLIC_IE1_0_E_28_BIT 28
+#define RV_PLIC_IE1_0_E_29_BIT 29
+#define RV_PLIC_IE1_0_E_30_BIT 30
+#define RV_PLIC_IE1_0_E_31_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_1_REG_OFFSET 0x2104
+#define RV_PLIC_IE1_1_REG_RESVAL 0x0
+#define RV_PLIC_IE1_1_E_32_BIT 0
+#define RV_PLIC_IE1_1_E_33_BIT 1
+#define RV_PLIC_IE1_1_E_34_BIT 2
+#define RV_PLIC_IE1_1_E_35_BIT 3
+#define RV_PLIC_IE1_1_E_36_BIT 4
+#define RV_PLIC_IE1_1_E_37_BIT 5
+#define RV_PLIC_IE1_1_E_38_BIT 6
+#define RV_PLIC_IE1_1_E_39_BIT 7
+#define RV_PLIC_IE1_1_E_40_BIT 8
+#define RV_PLIC_IE1_1_E_41_BIT 9
+#define RV_PLIC_IE1_1_E_42_BIT 10
+#define RV_PLIC_IE1_1_E_43_BIT 11
+#define RV_PLIC_IE1_1_E_44_BIT 12
+#define RV_PLIC_IE1_1_E_45_BIT 13
+#define RV_PLIC_IE1_1_E_46_BIT 14
+#define RV_PLIC_IE1_1_E_47_BIT 15
+#define RV_PLIC_IE1_1_E_48_BIT 16
+#define RV_PLIC_IE1_1_E_49_BIT 17
+#define RV_PLIC_IE1_1_E_50_BIT 18
+#define RV_PLIC_IE1_1_E_51_BIT 19
+#define RV_PLIC_IE1_1_E_52_BIT 20
+#define RV_PLIC_IE1_1_E_53_BIT 21
+#define RV_PLIC_IE1_1_E_54_BIT 22
+#define RV_PLIC_IE1_1_E_55_BIT 23
+#define RV_PLIC_IE1_1_E_56_BIT 24
+#define RV_PLIC_IE1_1_E_57_BIT 25
+#define RV_PLIC_IE1_1_E_58_BIT 26
+#define RV_PLIC_IE1_1_E_59_BIT 27
+#define RV_PLIC_IE1_1_E_60_BIT 28
+#define RV_PLIC_IE1_1_E_61_BIT 29
+#define RV_PLIC_IE1_1_E_62_BIT 30
+#define RV_PLIC_IE1_1_E_63_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_2_REG_OFFSET 0x2108
+#define RV_PLIC_IE1_2_REG_RESVAL 0x0
+#define RV_PLIC_IE1_2_E_64_BIT 0
+#define RV_PLIC_IE1_2_E_65_BIT 1
+#define RV_PLIC_IE1_2_E_66_BIT 2
+#define RV_PLIC_IE1_2_E_67_BIT 3
+#define RV_PLIC_IE1_2_E_68_BIT 4
+#define RV_PLIC_IE1_2_E_69_BIT 5
+#define RV_PLIC_IE1_2_E_70_BIT 6
+#define RV_PLIC_IE1_2_E_71_BIT 7
+#define RV_PLIC_IE1_2_E_72_BIT 8
+#define RV_PLIC_IE1_2_E_73_BIT 9
+#define RV_PLIC_IE1_2_E_74_BIT 10
+#define RV_PLIC_IE1_2_E_75_BIT 11
+#define RV_PLIC_IE1_2_E_76_BIT 12
+#define RV_PLIC_IE1_2_E_77_BIT 13
+#define RV_PLIC_IE1_2_E_78_BIT 14
+#define RV_PLIC_IE1_2_E_79_BIT 15
+#define RV_PLIC_IE1_2_E_80_BIT 16
+#define RV_PLIC_IE1_2_E_81_BIT 17
+#define RV_PLIC_IE1_2_E_82_BIT 18
+#define RV_PLIC_IE1_2_E_83_BIT 19
+#define RV_PLIC_IE1_2_E_84_BIT 20
+#define RV_PLIC_IE1_2_E_85_BIT 21
+#define RV_PLIC_IE1_2_E_86_BIT 22
+#define RV_PLIC_IE1_2_E_87_BIT 23
+#define RV_PLIC_IE1_2_E_88_BIT 24
+#define RV_PLIC_IE1_2_E_89_BIT 25
+#define RV_PLIC_IE1_2_E_90_BIT 26
+#define RV_PLIC_IE1_2_E_91_BIT 27
+#define RV_PLIC_IE1_2_E_92_BIT 28
+#define RV_PLIC_IE1_2_E_93_BIT 29
+#define RV_PLIC_IE1_2_E_94_BIT 30
+#define RV_PLIC_IE1_2_E_95_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_3_REG_OFFSET 0x210c
+#define RV_PLIC_IE1_3_REG_RESVAL 0x0
+#define RV_PLIC_IE1_3_E_96_BIT 0
+#define RV_PLIC_IE1_3_E_97_BIT 1
+#define RV_PLIC_IE1_3_E_98_BIT 2
+#define RV_PLIC_IE1_3_E_99_BIT 3
+#define RV_PLIC_IE1_3_E_100_BIT 4
+#define RV_PLIC_IE1_3_E_101_BIT 5
+#define RV_PLIC_IE1_3_E_102_BIT 6
+#define RV_PLIC_IE1_3_E_103_BIT 7
+#define RV_PLIC_IE1_3_E_104_BIT 8
+#define RV_PLIC_IE1_3_E_105_BIT 9
+#define RV_PLIC_IE1_3_E_106_BIT 10
+#define RV_PLIC_IE1_3_E_107_BIT 11
+#define RV_PLIC_IE1_3_E_108_BIT 12
+#define RV_PLIC_IE1_3_E_109_BIT 13
+#define RV_PLIC_IE1_3_E_110_BIT 14
+#define RV_PLIC_IE1_3_E_111_BIT 15
+#define RV_PLIC_IE1_3_E_112_BIT 16
+#define RV_PLIC_IE1_3_E_113_BIT 17
+#define RV_PLIC_IE1_3_E_114_BIT 18
+#define RV_PLIC_IE1_3_E_115_BIT 19
+#define RV_PLIC_IE1_3_E_116_BIT 20
+#define RV_PLIC_IE1_3_E_117_BIT 21
+#define RV_PLIC_IE1_3_E_118_BIT 22
+#define RV_PLIC_IE1_3_E_119_BIT 23
+#define RV_PLIC_IE1_3_E_120_BIT 24
+#define RV_PLIC_IE1_3_E_121_BIT 25
+#define RV_PLIC_IE1_3_E_122_BIT 26
+#define RV_PLIC_IE1_3_E_123_BIT 27
+#define RV_PLIC_IE1_3_E_124_BIT 28
+#define RV_PLIC_IE1_3_E_125_BIT 29
+#define RV_PLIC_IE1_3_E_126_BIT 30
+#define RV_PLIC_IE1_3_E_127_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_4_REG_OFFSET 0x2110
+#define RV_PLIC_IE1_4_REG_RESVAL 0x0
+#define RV_PLIC_IE1_4_E_128_BIT 0
+#define RV_PLIC_IE1_4_E_129_BIT 1
+#define RV_PLIC_IE1_4_E_130_BIT 2
+#define RV_PLIC_IE1_4_E_131_BIT 3
+#define RV_PLIC_IE1_4_E_132_BIT 4
+#define RV_PLIC_IE1_4_E_133_BIT 5
+#define RV_PLIC_IE1_4_E_134_BIT 6
+#define RV_PLIC_IE1_4_E_135_BIT 7
+#define RV_PLIC_IE1_4_E_136_BIT 8
+#define RV_PLIC_IE1_4_E_137_BIT 9
+#define RV_PLIC_IE1_4_E_138_BIT 10
+#define RV_PLIC_IE1_4_E_139_BIT 11
+#define RV_PLIC_IE1_4_E_140_BIT 12
+#define RV_PLIC_IE1_4_E_141_BIT 13
+#define RV_PLIC_IE1_4_E_142_BIT 14
+#define RV_PLIC_IE1_4_E_143_BIT 15
+#define RV_PLIC_IE1_4_E_144_BIT 16
+#define RV_PLIC_IE1_4_E_145_BIT 17
+#define RV_PLIC_IE1_4_E_146_BIT 18
+#define RV_PLIC_IE1_4_E_147_BIT 19
+#define RV_PLIC_IE1_4_E_148_BIT 20
+#define RV_PLIC_IE1_4_E_149_BIT 21
+#define RV_PLIC_IE1_4_E_150_BIT 22
+#define RV_PLIC_IE1_4_E_151_BIT 23
+#define RV_PLIC_IE1_4_E_152_BIT 24
+#define RV_PLIC_IE1_4_E_153_BIT 25
+#define RV_PLIC_IE1_4_E_154_BIT 26
+#define RV_PLIC_IE1_4_E_155_BIT 27
+#define RV_PLIC_IE1_4_E_156_BIT 28
+#define RV_PLIC_IE1_4_E_157_BIT 29
+#define RV_PLIC_IE1_4_E_158_BIT 30
+#define RV_PLIC_IE1_4_E_159_BIT 31
+
+// Interrupt Enable for Target 1
+#define RV_PLIC_IE1_5_REG_OFFSET 0x2114
+#define RV_PLIC_IE1_5_REG_RESVAL 0x0
+#define RV_PLIC_IE1_5_E_160_BIT 0
+#define RV_PLIC_IE1_5_E_161_BIT 1
+#define RV_PLIC_IE1_5_E_162_BIT 2
+#define RV_PLIC_IE1_5_E_163_BIT 3
+#define RV_PLIC_IE1_5_E_164_BIT 4
+#define RV_PLIC_IE1_5_E_165_BIT 5
+#define RV_PLIC_IE1_5_E_166_BIT 6
+#define RV_PLIC_IE1_5_E_167_BIT 7
+#define RV_PLIC_IE1_5_E_168_BIT 8
+#define RV_PLIC_IE1_5_E_169_BIT 9
+#define RV_PLIC_IE1_5_E_170_BIT 10
+#define RV_PLIC_IE1_5_E_171_BIT 11
+#define RV_PLIC_IE1_5_E_172_BIT 12
+#define RV_PLIC_IE1_5_E_173_BIT 13
+#define RV_PLIC_IE1_5_E_174_BIT 14
+#define RV_PLIC_IE1_5_E_175_BIT 15
+#define RV_PLIC_IE1_5_E_176_BIT 16
+#define RV_PLIC_IE1_5_E_177_BIT 17
+#define RV_PLIC_IE1_5_E_178_BIT 18
+#define RV_PLIC_IE1_5_E_179_BIT 19
+#define RV_PLIC_IE1_5_E_180_BIT 20
+#define RV_PLIC_IE1_5_E_181_BIT 21
+#define RV_PLIC_IE1_5_E_182_BIT 22
+#define RV_PLIC_IE1_5_E_183_BIT 23
+#define RV_PLIC_IE1_5_E_184_BIT 24
+#define RV_PLIC_IE1_5_E_185_BIT 25
+#define RV_PLIC_IE1_5_E_186_BIT 26
+#define RV_PLIC_IE1_5_E_187_BIT 27
+#define RV_PLIC_IE1_5_E_188_BIT 28
+#define RV_PLIC_IE1_5_E_189_BIT 29
+
+// Threshold of priority for Target 0
+#define RV_PLIC_THRESHOLD0_REG_OFFSET 0x200000
+#define RV_PLIC_THRESHOLD0_REG_RESVAL 0x0
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_MASK 0x3
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET 0
+#define RV_PLIC_THRESHOLD0_THRESHOLD0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_THRESHOLD0_THRESHOLD0_MASK, .index = RV_PLIC_THRESHOLD0_THRESHOLD0_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+#define RV_PLIC_CC0_REG_OFFSET 0x200004
+#define RV_PLIC_CC0_REG_RESVAL 0x0
+#define RV_PLIC_CC0_CC0_MASK 0xff
+#define RV_PLIC_CC0_CC0_OFFSET 0
+#define RV_PLIC_CC0_CC0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_CC0_CC0_MASK, .index = RV_PLIC_CC0_CC0_OFFSET })
+
+// Threshold of priority for Target 1
+#define RV_PLIC_THRESHOLD1_REG_OFFSET 0x201000
+#define RV_PLIC_THRESHOLD1_REG_RESVAL 0x0
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_MASK 0x3
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET 0
+#define RV_PLIC_THRESHOLD1_THRESHOLD1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_THRESHOLD1_THRESHOLD1_MASK, .index = RV_PLIC_THRESHOLD1_THRESHOLD1_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 1.
+#define RV_PLIC_CC1_REG_OFFSET 0x201004
+#define RV_PLIC_CC1_REG_RESVAL 0x0
+#define RV_PLIC_CC1_CC1_MASK 0xff
+#define RV_PLIC_CC1_CC1_OFFSET 0
+#define RV_PLIC_CC1_CC1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_CC1_CC1_MASK, .index = RV_PLIC_CC1_CC1_OFFSET })
+
+// msip for Hart 0.
+#define RV_PLIC_MSIP0_REG_OFFSET 0x4000000
+#define RV_PLIC_MSIP0_REG_RESVAL 0x0
+#define RV_PLIC_MSIP0_MSIP0_BIT 0
+
+// msip for Hart 1.
+#define RV_PLIC_MSIP1_REG_OFFSET 0x4000004
+#define RV_PLIC_MSIP1_REG_RESVAL 0x0
+#define RV_PLIC_MSIP1_MSIP1_BIT 0
+
+// Alert Test Register.
+#define RV_PLIC_ALERT_TEST_REG_OFFSET 0x4004000
+#define RV_PLIC_ALERT_TEST_REG_RESVAL 0x0
+#define RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _RV_PLIC_REG_DEFS_
+// End generated register defines for rv_plic
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_smc_regs.h b/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_smc_regs.h
new file mode 100644
index 0000000..9b2d0cf
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/rv_plic_smc_regs.h
@@ -0,0 +1,555 @@
+// Generated register defines for rv_plic_smc
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _RV_PLIC_SMC_REG_DEFS_
+#define _RV_PLIC_SMC_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Number of interrupt sources
+#define RV_PLIC_SMC_PARAM_NUM_SRC 47
+
+// Number of Targets (Harts)
+#define RV_PLIC_SMC_PARAM_NUM_TARGET 1
+
+// Width of priority signals
+#define RV_PLIC_SMC_PARAM_PRIO_WIDTH 2
+
+// Number of alerts
+#define RV_PLIC_SMC_PARAM_NUM_ALERTS 1
+
+// Register width
+#define RV_PLIC_SMC_PARAM_REG_WIDTH 32
+
+// Interrupt Source 0 Priority
+#define RV_PLIC_SMC_PRIO0_REG_OFFSET 0x0
+#define RV_PLIC_SMC_PRIO0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO0_PRIO0_MASK 0x3
+#define RV_PLIC_SMC_PRIO0_PRIO0_OFFSET 0
+#define RV_PLIC_SMC_PRIO0_PRIO0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO0_PRIO0_MASK, .index = RV_PLIC_SMC_PRIO0_PRIO0_OFFSET })
+
+// Interrupt Source 1 Priority
+#define RV_PLIC_SMC_PRIO1_REG_OFFSET 0x4
+#define RV_PLIC_SMC_PRIO1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO1_PRIO1_MASK 0x3
+#define RV_PLIC_SMC_PRIO1_PRIO1_OFFSET 0
+#define RV_PLIC_SMC_PRIO1_PRIO1_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO1_PRIO1_MASK, .index = RV_PLIC_SMC_PRIO1_PRIO1_OFFSET })
+
+// Interrupt Source 2 Priority
+#define RV_PLIC_SMC_PRIO2_REG_OFFSET 0x8
+#define RV_PLIC_SMC_PRIO2_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO2_PRIO2_MASK 0x3
+#define RV_PLIC_SMC_PRIO2_PRIO2_OFFSET 0
+#define RV_PLIC_SMC_PRIO2_PRIO2_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO2_PRIO2_MASK, .index = RV_PLIC_SMC_PRIO2_PRIO2_OFFSET })
+
+// Interrupt Source 3 Priority
+#define RV_PLIC_SMC_PRIO3_REG_OFFSET 0xc
+#define RV_PLIC_SMC_PRIO3_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO3_PRIO3_MASK 0x3
+#define RV_PLIC_SMC_PRIO3_PRIO3_OFFSET 0
+#define RV_PLIC_SMC_PRIO3_PRIO3_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO3_PRIO3_MASK, .index = RV_PLIC_SMC_PRIO3_PRIO3_OFFSET })
+
+// Interrupt Source 4 Priority
+#define RV_PLIC_SMC_PRIO4_REG_OFFSET 0x10
+#define RV_PLIC_SMC_PRIO4_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO4_PRIO4_MASK 0x3
+#define RV_PLIC_SMC_PRIO4_PRIO4_OFFSET 0
+#define RV_PLIC_SMC_PRIO4_PRIO4_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO4_PRIO4_MASK, .index = RV_PLIC_SMC_PRIO4_PRIO4_OFFSET })
+
+// Interrupt Source 5 Priority
+#define RV_PLIC_SMC_PRIO5_REG_OFFSET 0x14
+#define RV_PLIC_SMC_PRIO5_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO5_PRIO5_MASK 0x3
+#define RV_PLIC_SMC_PRIO5_PRIO5_OFFSET 0
+#define RV_PLIC_SMC_PRIO5_PRIO5_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO5_PRIO5_MASK, .index = RV_PLIC_SMC_PRIO5_PRIO5_OFFSET })
+
+// Interrupt Source 6 Priority
+#define RV_PLIC_SMC_PRIO6_REG_OFFSET 0x18
+#define RV_PLIC_SMC_PRIO6_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO6_PRIO6_MASK 0x3
+#define RV_PLIC_SMC_PRIO6_PRIO6_OFFSET 0
+#define RV_PLIC_SMC_PRIO6_PRIO6_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO6_PRIO6_MASK, .index = RV_PLIC_SMC_PRIO6_PRIO6_OFFSET })
+
+// Interrupt Source 7 Priority
+#define RV_PLIC_SMC_PRIO7_REG_OFFSET 0x1c
+#define RV_PLIC_SMC_PRIO7_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO7_PRIO7_MASK 0x3
+#define RV_PLIC_SMC_PRIO7_PRIO7_OFFSET 0
+#define RV_PLIC_SMC_PRIO7_PRIO7_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO7_PRIO7_MASK, .index = RV_PLIC_SMC_PRIO7_PRIO7_OFFSET })
+
+// Interrupt Source 8 Priority
+#define RV_PLIC_SMC_PRIO8_REG_OFFSET 0x20
+#define RV_PLIC_SMC_PRIO8_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO8_PRIO8_MASK 0x3
+#define RV_PLIC_SMC_PRIO8_PRIO8_OFFSET 0
+#define RV_PLIC_SMC_PRIO8_PRIO8_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO8_PRIO8_MASK, .index = RV_PLIC_SMC_PRIO8_PRIO8_OFFSET })
+
+// Interrupt Source 9 Priority
+#define RV_PLIC_SMC_PRIO9_REG_OFFSET 0x24
+#define RV_PLIC_SMC_PRIO9_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO9_PRIO9_MASK 0x3
+#define RV_PLIC_SMC_PRIO9_PRIO9_OFFSET 0
+#define RV_PLIC_SMC_PRIO9_PRIO9_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO9_PRIO9_MASK, .index = RV_PLIC_SMC_PRIO9_PRIO9_OFFSET })
+
+// Interrupt Source 10 Priority
+#define RV_PLIC_SMC_PRIO10_REG_OFFSET 0x28
+#define RV_PLIC_SMC_PRIO10_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO10_PRIO10_MASK 0x3
+#define RV_PLIC_SMC_PRIO10_PRIO10_OFFSET 0
+#define RV_PLIC_SMC_PRIO10_PRIO10_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO10_PRIO10_MASK, .index = RV_PLIC_SMC_PRIO10_PRIO10_OFFSET })
+
+// Interrupt Source 11 Priority
+#define RV_PLIC_SMC_PRIO11_REG_OFFSET 0x2c
+#define RV_PLIC_SMC_PRIO11_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO11_PRIO11_MASK 0x3
+#define RV_PLIC_SMC_PRIO11_PRIO11_OFFSET 0
+#define RV_PLIC_SMC_PRIO11_PRIO11_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO11_PRIO11_MASK, .index = RV_PLIC_SMC_PRIO11_PRIO11_OFFSET })
+
+// Interrupt Source 12 Priority
+#define RV_PLIC_SMC_PRIO12_REG_OFFSET 0x30
+#define RV_PLIC_SMC_PRIO12_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO12_PRIO12_MASK 0x3
+#define RV_PLIC_SMC_PRIO12_PRIO12_OFFSET 0
+#define RV_PLIC_SMC_PRIO12_PRIO12_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO12_PRIO12_MASK, .index = RV_PLIC_SMC_PRIO12_PRIO12_OFFSET })
+
+// Interrupt Source 13 Priority
+#define RV_PLIC_SMC_PRIO13_REG_OFFSET 0x34
+#define RV_PLIC_SMC_PRIO13_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO13_PRIO13_MASK 0x3
+#define RV_PLIC_SMC_PRIO13_PRIO13_OFFSET 0
+#define RV_PLIC_SMC_PRIO13_PRIO13_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO13_PRIO13_MASK, .index = RV_PLIC_SMC_PRIO13_PRIO13_OFFSET })
+
+// Interrupt Source 14 Priority
+#define RV_PLIC_SMC_PRIO14_REG_OFFSET 0x38
+#define RV_PLIC_SMC_PRIO14_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO14_PRIO14_MASK 0x3
+#define RV_PLIC_SMC_PRIO14_PRIO14_OFFSET 0
+#define RV_PLIC_SMC_PRIO14_PRIO14_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO14_PRIO14_MASK, .index = RV_PLIC_SMC_PRIO14_PRIO14_OFFSET })
+
+// Interrupt Source 15 Priority
+#define RV_PLIC_SMC_PRIO15_REG_OFFSET 0x3c
+#define RV_PLIC_SMC_PRIO15_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO15_PRIO15_MASK 0x3
+#define RV_PLIC_SMC_PRIO15_PRIO15_OFFSET 0
+#define RV_PLIC_SMC_PRIO15_PRIO15_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO15_PRIO15_MASK, .index = RV_PLIC_SMC_PRIO15_PRIO15_OFFSET })
+
+// Interrupt Source 16 Priority
+#define RV_PLIC_SMC_PRIO16_REG_OFFSET 0x40
+#define RV_PLIC_SMC_PRIO16_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO16_PRIO16_MASK 0x3
+#define RV_PLIC_SMC_PRIO16_PRIO16_OFFSET 0
+#define RV_PLIC_SMC_PRIO16_PRIO16_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO16_PRIO16_MASK, .index = RV_PLIC_SMC_PRIO16_PRIO16_OFFSET })
+
+// Interrupt Source 17 Priority
+#define RV_PLIC_SMC_PRIO17_REG_OFFSET 0x44
+#define RV_PLIC_SMC_PRIO17_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO17_PRIO17_MASK 0x3
+#define RV_PLIC_SMC_PRIO17_PRIO17_OFFSET 0
+#define RV_PLIC_SMC_PRIO17_PRIO17_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO17_PRIO17_MASK, .index = RV_PLIC_SMC_PRIO17_PRIO17_OFFSET })
+
+// Interrupt Source 18 Priority
+#define RV_PLIC_SMC_PRIO18_REG_OFFSET 0x48
+#define RV_PLIC_SMC_PRIO18_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO18_PRIO18_MASK 0x3
+#define RV_PLIC_SMC_PRIO18_PRIO18_OFFSET 0
+#define RV_PLIC_SMC_PRIO18_PRIO18_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO18_PRIO18_MASK, .index = RV_PLIC_SMC_PRIO18_PRIO18_OFFSET })
+
+// Interrupt Source 19 Priority
+#define RV_PLIC_SMC_PRIO19_REG_OFFSET 0x4c
+#define RV_PLIC_SMC_PRIO19_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO19_PRIO19_MASK 0x3
+#define RV_PLIC_SMC_PRIO19_PRIO19_OFFSET 0
+#define RV_PLIC_SMC_PRIO19_PRIO19_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO19_PRIO19_MASK, .index = RV_PLIC_SMC_PRIO19_PRIO19_OFFSET })
+
+// Interrupt Source 20 Priority
+#define RV_PLIC_SMC_PRIO20_REG_OFFSET 0x50
+#define RV_PLIC_SMC_PRIO20_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO20_PRIO20_MASK 0x3
+#define RV_PLIC_SMC_PRIO20_PRIO20_OFFSET 0
+#define RV_PLIC_SMC_PRIO20_PRIO20_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO20_PRIO20_MASK, .index = RV_PLIC_SMC_PRIO20_PRIO20_OFFSET })
+
+// Interrupt Source 21 Priority
+#define RV_PLIC_SMC_PRIO21_REG_OFFSET 0x54
+#define RV_PLIC_SMC_PRIO21_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO21_PRIO21_MASK 0x3
+#define RV_PLIC_SMC_PRIO21_PRIO21_OFFSET 0
+#define RV_PLIC_SMC_PRIO21_PRIO21_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO21_PRIO21_MASK, .index = RV_PLIC_SMC_PRIO21_PRIO21_OFFSET })
+
+// Interrupt Source 22 Priority
+#define RV_PLIC_SMC_PRIO22_REG_OFFSET 0x58
+#define RV_PLIC_SMC_PRIO22_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO22_PRIO22_MASK 0x3
+#define RV_PLIC_SMC_PRIO22_PRIO22_OFFSET 0
+#define RV_PLIC_SMC_PRIO22_PRIO22_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO22_PRIO22_MASK, .index = RV_PLIC_SMC_PRIO22_PRIO22_OFFSET })
+
+// Interrupt Source 23 Priority
+#define RV_PLIC_SMC_PRIO23_REG_OFFSET 0x5c
+#define RV_PLIC_SMC_PRIO23_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO23_PRIO23_MASK 0x3
+#define RV_PLIC_SMC_PRIO23_PRIO23_OFFSET 0
+#define RV_PLIC_SMC_PRIO23_PRIO23_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO23_PRIO23_MASK, .index = RV_PLIC_SMC_PRIO23_PRIO23_OFFSET })
+
+// Interrupt Source 24 Priority
+#define RV_PLIC_SMC_PRIO24_REG_OFFSET 0x60
+#define RV_PLIC_SMC_PRIO24_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO24_PRIO24_MASK 0x3
+#define RV_PLIC_SMC_PRIO24_PRIO24_OFFSET 0
+#define RV_PLIC_SMC_PRIO24_PRIO24_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO24_PRIO24_MASK, .index = RV_PLIC_SMC_PRIO24_PRIO24_OFFSET })
+
+// Interrupt Source 25 Priority
+#define RV_PLIC_SMC_PRIO25_REG_OFFSET 0x64
+#define RV_PLIC_SMC_PRIO25_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO25_PRIO25_MASK 0x3
+#define RV_PLIC_SMC_PRIO25_PRIO25_OFFSET 0
+#define RV_PLIC_SMC_PRIO25_PRIO25_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO25_PRIO25_MASK, .index = RV_PLIC_SMC_PRIO25_PRIO25_OFFSET })
+
+// Interrupt Source 26 Priority
+#define RV_PLIC_SMC_PRIO26_REG_OFFSET 0x68
+#define RV_PLIC_SMC_PRIO26_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO26_PRIO26_MASK 0x3
+#define RV_PLIC_SMC_PRIO26_PRIO26_OFFSET 0
+#define RV_PLIC_SMC_PRIO26_PRIO26_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO26_PRIO26_MASK, .index = RV_PLIC_SMC_PRIO26_PRIO26_OFFSET })
+
+// Interrupt Source 27 Priority
+#define RV_PLIC_SMC_PRIO27_REG_OFFSET 0x6c
+#define RV_PLIC_SMC_PRIO27_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO27_PRIO27_MASK 0x3
+#define RV_PLIC_SMC_PRIO27_PRIO27_OFFSET 0
+#define RV_PLIC_SMC_PRIO27_PRIO27_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO27_PRIO27_MASK, .index = RV_PLIC_SMC_PRIO27_PRIO27_OFFSET })
+
+// Interrupt Source 28 Priority
+#define RV_PLIC_SMC_PRIO28_REG_OFFSET 0x70
+#define RV_PLIC_SMC_PRIO28_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO28_PRIO28_MASK 0x3
+#define RV_PLIC_SMC_PRIO28_PRIO28_OFFSET 0
+#define RV_PLIC_SMC_PRIO28_PRIO28_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO28_PRIO28_MASK, .index = RV_PLIC_SMC_PRIO28_PRIO28_OFFSET })
+
+// Interrupt Source 29 Priority
+#define RV_PLIC_SMC_PRIO29_REG_OFFSET 0x74
+#define RV_PLIC_SMC_PRIO29_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO29_PRIO29_MASK 0x3
+#define RV_PLIC_SMC_PRIO29_PRIO29_OFFSET 0
+#define RV_PLIC_SMC_PRIO29_PRIO29_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO29_PRIO29_MASK, .index = RV_PLIC_SMC_PRIO29_PRIO29_OFFSET })
+
+// Interrupt Source 30 Priority
+#define RV_PLIC_SMC_PRIO30_REG_OFFSET 0x78
+#define RV_PLIC_SMC_PRIO30_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO30_PRIO30_MASK 0x3
+#define RV_PLIC_SMC_PRIO30_PRIO30_OFFSET 0
+#define RV_PLIC_SMC_PRIO30_PRIO30_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO30_PRIO30_MASK, .index = RV_PLIC_SMC_PRIO30_PRIO30_OFFSET })
+
+// Interrupt Source 31 Priority
+#define RV_PLIC_SMC_PRIO31_REG_OFFSET 0x7c
+#define RV_PLIC_SMC_PRIO31_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO31_PRIO31_MASK 0x3
+#define RV_PLIC_SMC_PRIO31_PRIO31_OFFSET 0
+#define RV_PLIC_SMC_PRIO31_PRIO31_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO31_PRIO31_MASK, .index = RV_PLIC_SMC_PRIO31_PRIO31_OFFSET })
+
+// Interrupt Source 32 Priority
+#define RV_PLIC_SMC_PRIO32_REG_OFFSET 0x80
+#define RV_PLIC_SMC_PRIO32_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO32_PRIO32_MASK 0x3
+#define RV_PLIC_SMC_PRIO32_PRIO32_OFFSET 0
+#define RV_PLIC_SMC_PRIO32_PRIO32_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO32_PRIO32_MASK, .index = RV_PLIC_SMC_PRIO32_PRIO32_OFFSET })
+
+// Interrupt Source 33 Priority
+#define RV_PLIC_SMC_PRIO33_REG_OFFSET 0x84
+#define RV_PLIC_SMC_PRIO33_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO33_PRIO33_MASK 0x3
+#define RV_PLIC_SMC_PRIO33_PRIO33_OFFSET 0
+#define RV_PLIC_SMC_PRIO33_PRIO33_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO33_PRIO33_MASK, .index = RV_PLIC_SMC_PRIO33_PRIO33_OFFSET })
+
+// Interrupt Source 34 Priority
+#define RV_PLIC_SMC_PRIO34_REG_OFFSET 0x88
+#define RV_PLIC_SMC_PRIO34_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO34_PRIO34_MASK 0x3
+#define RV_PLIC_SMC_PRIO34_PRIO34_OFFSET 0
+#define RV_PLIC_SMC_PRIO34_PRIO34_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO34_PRIO34_MASK, .index = RV_PLIC_SMC_PRIO34_PRIO34_OFFSET })
+
+// Interrupt Source 35 Priority
+#define RV_PLIC_SMC_PRIO35_REG_OFFSET 0x8c
+#define RV_PLIC_SMC_PRIO35_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO35_PRIO35_MASK 0x3
+#define RV_PLIC_SMC_PRIO35_PRIO35_OFFSET 0
+#define RV_PLIC_SMC_PRIO35_PRIO35_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO35_PRIO35_MASK, .index = RV_PLIC_SMC_PRIO35_PRIO35_OFFSET })
+
+// Interrupt Source 36 Priority
+#define RV_PLIC_SMC_PRIO36_REG_OFFSET 0x90
+#define RV_PLIC_SMC_PRIO36_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO36_PRIO36_MASK 0x3
+#define RV_PLIC_SMC_PRIO36_PRIO36_OFFSET 0
+#define RV_PLIC_SMC_PRIO36_PRIO36_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO36_PRIO36_MASK, .index = RV_PLIC_SMC_PRIO36_PRIO36_OFFSET })
+
+// Interrupt Source 37 Priority
+#define RV_PLIC_SMC_PRIO37_REG_OFFSET 0x94
+#define RV_PLIC_SMC_PRIO37_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO37_PRIO37_MASK 0x3
+#define RV_PLIC_SMC_PRIO37_PRIO37_OFFSET 0
+#define RV_PLIC_SMC_PRIO37_PRIO37_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO37_PRIO37_MASK, .index = RV_PLIC_SMC_PRIO37_PRIO37_OFFSET })
+
+// Interrupt Source 38 Priority
+#define RV_PLIC_SMC_PRIO38_REG_OFFSET 0x98
+#define RV_PLIC_SMC_PRIO38_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO38_PRIO38_MASK 0x3
+#define RV_PLIC_SMC_PRIO38_PRIO38_OFFSET 0
+#define RV_PLIC_SMC_PRIO38_PRIO38_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO38_PRIO38_MASK, .index = RV_PLIC_SMC_PRIO38_PRIO38_OFFSET })
+
+// Interrupt Source 39 Priority
+#define RV_PLIC_SMC_PRIO39_REG_OFFSET 0x9c
+#define RV_PLIC_SMC_PRIO39_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO39_PRIO39_MASK 0x3
+#define RV_PLIC_SMC_PRIO39_PRIO39_OFFSET 0
+#define RV_PLIC_SMC_PRIO39_PRIO39_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO39_PRIO39_MASK, .index = RV_PLIC_SMC_PRIO39_PRIO39_OFFSET })
+
+// Interrupt Source 40 Priority
+#define RV_PLIC_SMC_PRIO40_REG_OFFSET 0xa0
+#define RV_PLIC_SMC_PRIO40_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO40_PRIO40_MASK 0x3
+#define RV_PLIC_SMC_PRIO40_PRIO40_OFFSET 0
+#define RV_PLIC_SMC_PRIO40_PRIO40_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO40_PRIO40_MASK, .index = RV_PLIC_SMC_PRIO40_PRIO40_OFFSET })
+
+// Interrupt Source 41 Priority
+#define RV_PLIC_SMC_PRIO41_REG_OFFSET 0xa4
+#define RV_PLIC_SMC_PRIO41_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO41_PRIO41_MASK 0x3
+#define RV_PLIC_SMC_PRIO41_PRIO41_OFFSET 0
+#define RV_PLIC_SMC_PRIO41_PRIO41_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO41_PRIO41_MASK, .index = RV_PLIC_SMC_PRIO41_PRIO41_OFFSET })
+
+// Interrupt Source 42 Priority
+#define RV_PLIC_SMC_PRIO42_REG_OFFSET 0xa8
+#define RV_PLIC_SMC_PRIO42_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO42_PRIO42_MASK 0x3
+#define RV_PLIC_SMC_PRIO42_PRIO42_OFFSET 0
+#define RV_PLIC_SMC_PRIO42_PRIO42_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO42_PRIO42_MASK, .index = RV_PLIC_SMC_PRIO42_PRIO42_OFFSET })
+
+// Interrupt Source 43 Priority
+#define RV_PLIC_SMC_PRIO43_REG_OFFSET 0xac
+#define RV_PLIC_SMC_PRIO43_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO43_PRIO43_MASK 0x3
+#define RV_PLIC_SMC_PRIO43_PRIO43_OFFSET 0
+#define RV_PLIC_SMC_PRIO43_PRIO43_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO43_PRIO43_MASK, .index = RV_PLIC_SMC_PRIO43_PRIO43_OFFSET })
+
+// Interrupt Source 44 Priority
+#define RV_PLIC_SMC_PRIO44_REG_OFFSET 0xb0
+#define RV_PLIC_SMC_PRIO44_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO44_PRIO44_MASK 0x3
+#define RV_PLIC_SMC_PRIO44_PRIO44_OFFSET 0
+#define RV_PLIC_SMC_PRIO44_PRIO44_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO44_PRIO44_MASK, .index = RV_PLIC_SMC_PRIO44_PRIO44_OFFSET })
+
+// Interrupt Source 45 Priority
+#define RV_PLIC_SMC_PRIO45_REG_OFFSET 0xb4
+#define RV_PLIC_SMC_PRIO45_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO45_PRIO45_MASK 0x3
+#define RV_PLIC_SMC_PRIO45_PRIO45_OFFSET 0
+#define RV_PLIC_SMC_PRIO45_PRIO45_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO45_PRIO45_MASK, .index = RV_PLIC_SMC_PRIO45_PRIO45_OFFSET })
+
+// Interrupt Source 46 Priority
+#define RV_PLIC_SMC_PRIO46_REG_OFFSET 0xb8
+#define RV_PLIC_SMC_PRIO46_REG_RESVAL 0x0
+#define RV_PLIC_SMC_PRIO46_PRIO46_MASK 0x3
+#define RV_PLIC_SMC_PRIO46_PRIO46_OFFSET 0
+#define RV_PLIC_SMC_PRIO46_PRIO46_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_PRIO46_PRIO46_MASK, .index = RV_PLIC_SMC_PRIO46_PRIO46_OFFSET })
+
+// Interrupt Pending (common parameters)
+#define RV_PLIC_SMC_IP_P_FIELD_WIDTH 1
+#define RV_PLIC_SMC_IP_MULTIREG_COUNT 2
+
+// Interrupt Pending
+#define RV_PLIC_SMC_IP_0_REG_OFFSET 0x1000
+#define RV_PLIC_SMC_IP_0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IP_0_P_0_BIT 0
+#define RV_PLIC_SMC_IP_0_P_1_BIT 1
+#define RV_PLIC_SMC_IP_0_P_2_BIT 2
+#define RV_PLIC_SMC_IP_0_P_3_BIT 3
+#define RV_PLIC_SMC_IP_0_P_4_BIT 4
+#define RV_PLIC_SMC_IP_0_P_5_BIT 5
+#define RV_PLIC_SMC_IP_0_P_6_BIT 6
+#define RV_PLIC_SMC_IP_0_P_7_BIT 7
+#define RV_PLIC_SMC_IP_0_P_8_BIT 8
+#define RV_PLIC_SMC_IP_0_P_9_BIT 9
+#define RV_PLIC_SMC_IP_0_P_10_BIT 10
+#define RV_PLIC_SMC_IP_0_P_11_BIT 11
+#define RV_PLIC_SMC_IP_0_P_12_BIT 12
+#define RV_PLIC_SMC_IP_0_P_13_BIT 13
+#define RV_PLIC_SMC_IP_0_P_14_BIT 14
+#define RV_PLIC_SMC_IP_0_P_15_BIT 15
+#define RV_PLIC_SMC_IP_0_P_16_BIT 16
+#define RV_PLIC_SMC_IP_0_P_17_BIT 17
+#define RV_PLIC_SMC_IP_0_P_18_BIT 18
+#define RV_PLIC_SMC_IP_0_P_19_BIT 19
+#define RV_PLIC_SMC_IP_0_P_20_BIT 20
+#define RV_PLIC_SMC_IP_0_P_21_BIT 21
+#define RV_PLIC_SMC_IP_0_P_22_BIT 22
+#define RV_PLIC_SMC_IP_0_P_23_BIT 23
+#define RV_PLIC_SMC_IP_0_P_24_BIT 24
+#define RV_PLIC_SMC_IP_0_P_25_BIT 25
+#define RV_PLIC_SMC_IP_0_P_26_BIT 26
+#define RV_PLIC_SMC_IP_0_P_27_BIT 27
+#define RV_PLIC_SMC_IP_0_P_28_BIT 28
+#define RV_PLIC_SMC_IP_0_P_29_BIT 29
+#define RV_PLIC_SMC_IP_0_P_30_BIT 30
+#define RV_PLIC_SMC_IP_0_P_31_BIT 31
+
+// Interrupt Pending
+#define RV_PLIC_SMC_IP_1_REG_OFFSET 0x1004
+#define RV_PLIC_SMC_IP_1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IP_1_P_32_BIT 0
+#define RV_PLIC_SMC_IP_1_P_33_BIT 1
+#define RV_PLIC_SMC_IP_1_P_34_BIT 2
+#define RV_PLIC_SMC_IP_1_P_35_BIT 3
+#define RV_PLIC_SMC_IP_1_P_36_BIT 4
+#define RV_PLIC_SMC_IP_1_P_37_BIT 5
+#define RV_PLIC_SMC_IP_1_P_38_BIT 6
+#define RV_PLIC_SMC_IP_1_P_39_BIT 7
+#define RV_PLIC_SMC_IP_1_P_40_BIT 8
+#define RV_PLIC_SMC_IP_1_P_41_BIT 9
+#define RV_PLIC_SMC_IP_1_P_42_BIT 10
+#define RV_PLIC_SMC_IP_1_P_43_BIT 11
+#define RV_PLIC_SMC_IP_1_P_44_BIT 12
+#define RV_PLIC_SMC_IP_1_P_45_BIT 13
+#define RV_PLIC_SMC_IP_1_P_46_BIT 14
+
+// Interrupt Enable for Target 0 (common parameters)
+#define RV_PLIC_SMC_IE0_E_FIELD_WIDTH 1
+#define RV_PLIC_SMC_IE0_MULTIREG_COUNT 2
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_SMC_IE0_0_REG_OFFSET 0x2000
+#define RV_PLIC_SMC_IE0_0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IE0_0_E_0_BIT 0
+#define RV_PLIC_SMC_IE0_0_E_1_BIT 1
+#define RV_PLIC_SMC_IE0_0_E_2_BIT 2
+#define RV_PLIC_SMC_IE0_0_E_3_BIT 3
+#define RV_PLIC_SMC_IE0_0_E_4_BIT 4
+#define RV_PLIC_SMC_IE0_0_E_5_BIT 5
+#define RV_PLIC_SMC_IE0_0_E_6_BIT 6
+#define RV_PLIC_SMC_IE0_0_E_7_BIT 7
+#define RV_PLIC_SMC_IE0_0_E_8_BIT 8
+#define RV_PLIC_SMC_IE0_0_E_9_BIT 9
+#define RV_PLIC_SMC_IE0_0_E_10_BIT 10
+#define RV_PLIC_SMC_IE0_0_E_11_BIT 11
+#define RV_PLIC_SMC_IE0_0_E_12_BIT 12
+#define RV_PLIC_SMC_IE0_0_E_13_BIT 13
+#define RV_PLIC_SMC_IE0_0_E_14_BIT 14
+#define RV_PLIC_SMC_IE0_0_E_15_BIT 15
+#define RV_PLIC_SMC_IE0_0_E_16_BIT 16
+#define RV_PLIC_SMC_IE0_0_E_17_BIT 17
+#define RV_PLIC_SMC_IE0_0_E_18_BIT 18
+#define RV_PLIC_SMC_IE0_0_E_19_BIT 19
+#define RV_PLIC_SMC_IE0_0_E_20_BIT 20
+#define RV_PLIC_SMC_IE0_0_E_21_BIT 21
+#define RV_PLIC_SMC_IE0_0_E_22_BIT 22
+#define RV_PLIC_SMC_IE0_0_E_23_BIT 23
+#define RV_PLIC_SMC_IE0_0_E_24_BIT 24
+#define RV_PLIC_SMC_IE0_0_E_25_BIT 25
+#define RV_PLIC_SMC_IE0_0_E_26_BIT 26
+#define RV_PLIC_SMC_IE0_0_E_27_BIT 27
+#define RV_PLIC_SMC_IE0_0_E_28_BIT 28
+#define RV_PLIC_SMC_IE0_0_E_29_BIT 29
+#define RV_PLIC_SMC_IE0_0_E_30_BIT 30
+#define RV_PLIC_SMC_IE0_0_E_31_BIT 31
+
+// Interrupt Enable for Target 0
+#define RV_PLIC_SMC_IE0_1_REG_OFFSET 0x2004
+#define RV_PLIC_SMC_IE0_1_REG_RESVAL 0x0
+#define RV_PLIC_SMC_IE0_1_E_32_BIT 0
+#define RV_PLIC_SMC_IE0_1_E_33_BIT 1
+#define RV_PLIC_SMC_IE0_1_E_34_BIT 2
+#define RV_PLIC_SMC_IE0_1_E_35_BIT 3
+#define RV_PLIC_SMC_IE0_1_E_36_BIT 4
+#define RV_PLIC_SMC_IE0_1_E_37_BIT 5
+#define RV_PLIC_SMC_IE0_1_E_38_BIT 6
+#define RV_PLIC_SMC_IE0_1_E_39_BIT 7
+#define RV_PLIC_SMC_IE0_1_E_40_BIT 8
+#define RV_PLIC_SMC_IE0_1_E_41_BIT 9
+#define RV_PLIC_SMC_IE0_1_E_42_BIT 10
+#define RV_PLIC_SMC_IE0_1_E_43_BIT 11
+#define RV_PLIC_SMC_IE0_1_E_44_BIT 12
+#define RV_PLIC_SMC_IE0_1_E_45_BIT 13
+#define RV_PLIC_SMC_IE0_1_E_46_BIT 14
+
+// Threshold of priority for Target 0
+#define RV_PLIC_SMC_THRESHOLD0_REG_OFFSET 0x200000
+#define RV_PLIC_SMC_THRESHOLD0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_MASK 0x3
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_OFFSET 0
+#define RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_MASK, .index = RV_PLIC_SMC_THRESHOLD0_THRESHOLD0_OFFSET })
+
+// Claim interrupt by read, complete interrupt by write for Target 0.
+#define RV_PLIC_SMC_CC0_REG_OFFSET 0x200004
+#define RV_PLIC_SMC_CC0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_CC0_CC0_MASK 0x3f
+#define RV_PLIC_SMC_CC0_CC0_OFFSET 0
+#define RV_PLIC_SMC_CC0_CC0_FIELD \
+ ((bitfield_field32_t) { .mask = RV_PLIC_SMC_CC0_CC0_MASK, .index = RV_PLIC_SMC_CC0_CC0_OFFSET })
+
+// msip for Hart 0.
+#define RV_PLIC_SMC_MSIP0_REG_OFFSET 0x4000000
+#define RV_PLIC_SMC_MSIP0_REG_RESVAL 0x0
+#define RV_PLIC_SMC_MSIP0_MSIP0_BIT 0
+
+// Alert Test Register.
+#define RV_PLIC_SMC_ALERT_TEST_REG_OFFSET 0x4004000
+#define RV_PLIC_SMC_ALERT_TEST_REG_RESVAL 0x0
+#define RV_PLIC_SMC_ALERT_TEST_FATAL_FAULT_BIT 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _RV_PLIC_SMC_REG_DEFS_
+// End generated register defines for rv_plic_smc
\ No newline at end of file
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/BUILD b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/BUILD
new file mode 100644
index 0000000..5502e84
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/BUILD
@@ -0,0 +1,12 @@
+# Copyright 2022 Google Inc. All Rights Reserved.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+load("@lowrisc_opentitan//rules:linker.bzl", "ld_library")
+
+package(default_visibility = ["//visibility:public"])
+
+filegroup(
+ name = "all_files",
+ srcs = glob(["**"]),
+)
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.c b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.c
new file mode 100644
index 0000000..83359a8
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.c
@@ -0,0 +1,343 @@
+// Copyright 2022 Google Inc.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "hw/top_matcha/sw/autogen/top_matcha.h"
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_matcha_plic_irq_id_t` to
+ * `top_matcha_plic_peripheral_t`.
+ */
+const top_matcha_plic_peripheral_t
+ top_matcha_plic_interrupt_for_peripheral[190] = {
+ [kTopMatchaPlicIrqIdNone] = kTopMatchaPlicPeripheralUnknown,
+ [kTopMatchaPlicIrqIdUart0TxWatermark] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxWatermark] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0TxEmpty] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxOverflow] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxFrameErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxBreakErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxTimeout] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart0RxParityErr] = kTopMatchaPlicPeripheralUart0,
+ [kTopMatchaPlicIrqIdUart1TxWatermark] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxWatermark] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1TxEmpty] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxOverflow] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxFrameErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxBreakErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxTimeout] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart1RxParityErr] = kTopMatchaPlicPeripheralUart1,
+ [kTopMatchaPlicIrqIdUart2TxWatermark] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxWatermark] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2TxEmpty] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxOverflow] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxFrameErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxBreakErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxTimeout] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart2RxParityErr] = kTopMatchaPlicPeripheralUart2,
+ [kTopMatchaPlicIrqIdUart3TxWatermark] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxWatermark] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3TxEmpty] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxOverflow] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxFrameErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxBreakErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxTimeout] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdUart3RxParityErr] = kTopMatchaPlicPeripheralUart3,
+ [kTopMatchaPlicIrqIdGpioGpio0] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio1] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio2] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio3] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio4] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio5] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio6] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio7] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio8] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio9] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio10] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio11] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio12] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio13] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio14] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio15] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio16] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio17] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio18] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio19] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio20] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio21] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio22] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio23] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio24] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio25] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio26] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio27] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio28] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio29] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio30] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdGpioGpio31] = kTopMatchaPlicPeripheralGpio,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxFull] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericTxWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxError] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericRxOverflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceGenericTxUnderflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceUploadPayloadOverflow] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceReadbufWatermark] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceReadbufFlip] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopMatchaPlicPeripheralSpiDevice,
+ [kTopMatchaPlicIrqIdI2c0FmtThreshold] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0RxThreshold] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0FmtOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0RxOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0Nak] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SclInterference] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SdaInterference] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0StretchTimeout] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0SdaUnstable] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0CmdComplete] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0TxStretch] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0TxOverflow] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0AcqFull] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0UnexpStop] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c0HostTimeout] = kTopMatchaPlicPeripheralI2c0,
+ [kTopMatchaPlicIrqIdI2c1FmtThreshold] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1RxThreshold] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1FmtOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1RxOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1Nak] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SclInterference] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SdaInterference] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1StretchTimeout] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1SdaUnstable] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1CmdComplete] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1TxStretch] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1TxOverflow] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1AcqFull] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1UnexpStop] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c1HostTimeout] = kTopMatchaPlicPeripheralI2c1,
+ [kTopMatchaPlicIrqIdI2c2FmtThreshold] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2RxThreshold] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2FmtOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2RxOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2Nak] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SclInterference] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SdaInterference] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2StretchTimeout] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2SdaUnstable] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2CmdComplete] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2TxStretch] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2TxOverflow] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2AcqFull] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2UnexpStop] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdI2c2HostTimeout] = kTopMatchaPlicPeripheralI2c2,
+ [kTopMatchaPlicIrqIdPattgenDoneCh0] = kTopMatchaPlicPeripheralPattgen,
+ [kTopMatchaPlicIrqIdPattgenDoneCh1] = kTopMatchaPlicPeripheralPattgen,
+ [kTopMatchaPlicIrqIdRvTimerTimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimer,
+ [kTopMatchaPlicIrqIdOtpCtrlOtpOperationDone] = kTopMatchaPlicPeripheralOtpCtrl,
+ [kTopMatchaPlicIrqIdOtpCtrlOtpError] = kTopMatchaPlicPeripheralOtpCtrl,
+ [kTopMatchaPlicIrqIdAlertHandlerClassa] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassb] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassc] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdAlertHandlerClassd] = kTopMatchaPlicPeripheralAlertHandler,
+ [kTopMatchaPlicIrqIdSpiHost0Error] = kTopMatchaPlicPeripheralSpiHost0,
+ [kTopMatchaPlicIrqIdSpiHost0SpiEvent] = kTopMatchaPlicPeripheralSpiHost0,
+ [kTopMatchaPlicIrqIdSpiHost1Error] = kTopMatchaPlicPeripheralSpiHost1,
+ [kTopMatchaPlicIrqIdSpiHost1SpiEvent] = kTopMatchaPlicPeripheralSpiHost1,
+ [kTopMatchaPlicIrqIdUsbdevPktReceived] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevPktSent] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevDisconnected] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevHostLost] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkReset] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkSuspend] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkResume] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevAvEmpty] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxFull] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevAvOverflow] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkInErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxCrcErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxPidErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevRxBitstuffErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevFrame] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevPowered] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdUsbdevLinkOutErr] = kTopMatchaPlicPeripheralUsbdev,
+ [kTopMatchaPlicIrqIdPwrmgrAonWakeup] = kTopMatchaPlicPeripheralPwrmgrAon,
+ [kTopMatchaPlicIrqIdSysrstCtrlAonEventDetected] = kTopMatchaPlicPeripheralSysrstCtrlAon,
+ [kTopMatchaPlicIrqIdAdcCtrlAonMatchDone] = kTopMatchaPlicPeripheralAdcCtrlAon,
+ [kTopMatchaPlicIrqIdAonTimerAonWkupTimerExpired] = kTopMatchaPlicPeripheralAonTimerAon,
+ [kTopMatchaPlicIrqIdAonTimerAonWdogTimerBark] = kTopMatchaPlicPeripheralAonTimerAon,
+ [kTopMatchaPlicIrqIdSensorCtrlIoStatusChange] = kTopMatchaPlicPeripheralSensorCtrl,
+ [kTopMatchaPlicIrqIdSensorCtrlInitStatusChange] = kTopMatchaPlicPeripheralSensorCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlProgEmpty] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlProgLvl] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlRdFull] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlRdLvl] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlOpDone] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdFlashCtrlCorrErr] = kTopMatchaPlicPeripheralFlashCtrl,
+ [kTopMatchaPlicIrqIdHmacHmacDone] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdHmacFifoEmpty] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdHmacHmacErr] = kTopMatchaPlicPeripheralHmac,
+ [kTopMatchaPlicIrqIdKmacKmacDone] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdKmacFifoEmpty] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdKmacKmacErr] = kTopMatchaPlicPeripheralKmac,
+ [kTopMatchaPlicIrqIdOtbnDone] = kTopMatchaPlicPeripheralOtbn,
+ [kTopMatchaPlicIrqIdKeymgrOpDone] = kTopMatchaPlicPeripheralKeymgr,
+ [kTopMatchaPlicIrqIdCsrngCsCmdReqDone] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsEntropyReq] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsHwInstExc] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdCsrngCsFatalErr] = kTopMatchaPlicPeripheralCsrng,
+ [kTopMatchaPlicIrqIdEntropySrcEsEntropyValid] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsHealthTestFailed] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsObserveFifoReady] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEntropySrcEsFatalErr] = kTopMatchaPlicPeripheralEntropySrc,
+ [kTopMatchaPlicIrqIdEdn0EdnCmdReqDone] = kTopMatchaPlicPeripheralEdn0,
+ [kTopMatchaPlicIrqIdEdn0EdnFatalErr] = kTopMatchaPlicPeripheralEdn0,
+ [kTopMatchaPlicIrqIdEdn1EdnCmdReqDone] = kTopMatchaPlicPeripheralEdn1,
+ [kTopMatchaPlicIrqIdEdn1EdnFatalErr] = kTopMatchaPlicPeripheralEdn1,
+ [kTopMatchaPlicIrqIdDma0WriterDone] = kTopMatchaPlicPeripheralDma0,
+ [kTopMatchaPlicIrqIdDma0ReaderDone] = kTopMatchaPlicPeripheralDma0,
+ [kTopMatchaPlicIrqIdTlulMailboxSecWtirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+ [kTopMatchaPlicIrqIdTlulMailboxSecRtirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+ [kTopMatchaPlicIrqIdTlulMailboxSecEirq] = kTopMatchaPlicPeripheralTlulMailboxSec,
+};
+
+const top_matcha_plic_peripheral_smc_t
+ top_matcha_plic_interrupt_for_peripheral_smc[47] = {
+ [kTopMatchaPlicIrqIdNoneSmc] = kTopMatchaPlicPeripheralUnknownSmc,
+ [kTopMatchaPlicIrqIdSmcUartTxWatermark] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxWatermark] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartTxEmpty] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxOverflow] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxFrameErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxBreakErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxTimeout] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdSmcUartRxParityErr] = kTopMatchaPlicPeripheralSmcUart,
+ [kTopMatchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimerSmc,
+ [kTopMatchaPlicIrqIdCamI2cFmtThreshold] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cRxThreshold] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cFmtOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cRxOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cNak] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSclInterference] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSdaInterference] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cStretchTimeout] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cSdaUnstable] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cCmdComplete] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cTxStretch] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cTxOverflow] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cAcqFull] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cUnexpStop] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamI2cHostTimeout] = kTopMatchaPlicPeripheralCamI2c,
+ [kTopMatchaPlicIrqIdCamCtrlCamMotionDetect] = kTopMatchaPlicPeripheralCamCtrl,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperIsp] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperMi] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperMipi] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperEncoder] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperUpstream] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdVideoAudioWrapperAudioSmc] = kTopMatchaPlicPeripheralVideoAudioWrapper,
+ [kTopMatchaPlicIrqIdDmaSmcWriterDone] = kTopMatchaPlicPeripheralDmaSmc,
+ [kTopMatchaPlicIrqIdDmaSmcReaderDone] = kTopMatchaPlicPeripheralDmaSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcWtirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcRtirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdTlulMailboxSmcEirq] = kTopMatchaPlicPeripheralTlulMailboxSmc,
+ [kTopMatchaPlicIrqIdMlTopHostReq] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdMlTopFinish] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdMlTopFault] = kTopMatchaPlicPeripheralMlTop,
+ [kTopMatchaPlicIrqIdSpiHost2Error] = kTopMatchaPlicPeripheralSpiHost2,
+ [kTopMatchaPlicIrqIdSpiHost2SpiEvent] = kTopMatchaPlicPeripheralSpiHost2,
+ [kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0] = kTopMatchaPlicPeripheralRvTimerSmc2,
+ [kTopMatchaPlicIrqIdI2s0TxWatermark] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0RxWatermark] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0TxEmpty] = kTopMatchaPlicPeripheralI2s0,
+ [kTopMatchaPlicIrqIdI2s0RxOverflow] = kTopMatchaPlicPeripheralI2s0,
+};
+
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_matcha_alert_id_t` to
+ * `top_matcha_alert_peripheral_t`.
+ */
+const top_matcha_alert_peripheral_t
+ top_matcha_alert_for_peripheral[75] = {
+ [kTopMatchaAlertIdUart0FatalFault] = kTopMatchaAlertPeripheralUart0,
+ [kTopMatchaAlertIdUart1FatalFault] = kTopMatchaAlertPeripheralUart1,
+ [kTopMatchaAlertIdUart2FatalFault] = kTopMatchaAlertPeripheralUart2,
+ [kTopMatchaAlertIdUart3FatalFault] = kTopMatchaAlertPeripheralUart3,
+ [kTopMatchaAlertIdGpioFatalFault] = kTopMatchaAlertPeripheralGpio,
+ [kTopMatchaAlertIdSpiDeviceFatalFault] = kTopMatchaAlertPeripheralSpiDevice,
+ [kTopMatchaAlertIdI2c0FatalFault] = kTopMatchaAlertPeripheralI2c0,
+ [kTopMatchaAlertIdI2c1FatalFault] = kTopMatchaAlertPeripheralI2c1,
+ [kTopMatchaAlertIdI2c2FatalFault] = kTopMatchaAlertPeripheralI2c2,
+ [kTopMatchaAlertIdPattgenFatalFault] = kTopMatchaAlertPeripheralPattgen,
+ [kTopMatchaAlertIdRvTimerFatalFault] = kTopMatchaAlertPeripheralRvTimer,
+ [kTopMatchaAlertIdOtpCtrlFatalMacroError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalCheckError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalBusIntegError] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlFatalPrimOtpAlert] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdOtpCtrlRecovPrimOtpAlert] = kTopMatchaAlertPeripheralOtpCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalProgError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalStateError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdLcCtrlFatalBusIntegError] = kTopMatchaAlertPeripheralLcCtrl,
+ [kTopMatchaAlertIdSpiHost0FatalFault] = kTopMatchaAlertPeripheralSpiHost0,
+ [kTopMatchaAlertIdSpiHost1FatalFault] = kTopMatchaAlertPeripheralSpiHost1,
+ [kTopMatchaAlertIdUsbdevFatalFault] = kTopMatchaAlertPeripheralUsbdev,
+ [kTopMatchaAlertIdPwrmgrAonFatalFault] = kTopMatchaAlertPeripheralPwrmgrAon,
+ [kTopMatchaAlertIdRstmgrAonFatalFault] = kTopMatchaAlertPeripheralRstmgrAon,
+ [kTopMatchaAlertIdRstmgrAonFatalCnstyFault] = kTopMatchaAlertPeripheralRstmgrAon,
+ [kTopMatchaAlertIdClkmgrAonRecovFault] = kTopMatchaAlertPeripheralClkmgrAon,
+ [kTopMatchaAlertIdClkmgrAonFatalFault] = kTopMatchaAlertPeripheralClkmgrAon,
+ [kTopMatchaAlertIdSysrstCtrlAonFatalFault] = kTopMatchaAlertPeripheralSysrstCtrlAon,
+ [kTopMatchaAlertIdAdcCtrlAonFatalFault] = kTopMatchaAlertPeripheralAdcCtrlAon,
+ [kTopMatchaAlertIdPwmAonFatalFault] = kTopMatchaAlertPeripheralPwmAon,
+ [kTopMatchaAlertIdPinmuxAonFatalFault] = kTopMatchaAlertPeripheralPinmuxAon,
+ [kTopMatchaAlertIdAonTimerAonFatalFault] = kTopMatchaAlertPeripheralAonTimerAon,
+ [kTopMatchaAlertIdSensorCtrlRecovAlert] = kTopMatchaAlertPeripheralSensorCtrl,
+ [kTopMatchaAlertIdSensorCtrlFatalAlert] = kTopMatchaAlertPeripheralSensorCtrl,
+ [kTopMatchaAlertIdSramCtrlRetAonFatalError] = kTopMatchaAlertPeripheralSramCtrlRetAon,
+ [kTopMatchaAlertIdFlashCtrlRecovErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalStdErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalErr] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlFatalPrimFlashAlert] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdFlashCtrlRecovPrimFlashAlert] = kTopMatchaAlertPeripheralFlashCtrl,
+ [kTopMatchaAlertIdRvDmFatalFault] = kTopMatchaAlertPeripheralRvDm,
+ [kTopMatchaAlertIdRvPlicFatalFault] = kTopMatchaAlertPeripheralRvPlic,
+ [kTopMatchaAlertIdAesRecovCtrlUpdateErr] = kTopMatchaAlertPeripheralAes,
+ [kTopMatchaAlertIdAesFatalFault] = kTopMatchaAlertPeripheralAes,
+ [kTopMatchaAlertIdHmacFatalFault] = kTopMatchaAlertPeripheralHmac,
+ [kTopMatchaAlertIdKmacRecovOperationErr] = kTopMatchaAlertPeripheralKmac,
+ [kTopMatchaAlertIdKmacFatalFaultErr] = kTopMatchaAlertPeripheralKmac,
+ [kTopMatchaAlertIdOtbnFatal] = kTopMatchaAlertPeripheralOtbn,
+ [kTopMatchaAlertIdOtbnRecov] = kTopMatchaAlertPeripheralOtbn,
+ [kTopMatchaAlertIdKeymgrRecovOperationErr] = kTopMatchaAlertPeripheralKeymgr,
+ [kTopMatchaAlertIdKeymgrFatalFaultErr] = kTopMatchaAlertPeripheralKeymgr,
+ [kTopMatchaAlertIdCsrngRecovAlert] = kTopMatchaAlertPeripheralCsrng,
+ [kTopMatchaAlertIdCsrngFatalAlert] = kTopMatchaAlertPeripheralCsrng,
+ [kTopMatchaAlertIdEntropySrcRecovAlert] = kTopMatchaAlertPeripheralEntropySrc,
+ [kTopMatchaAlertIdEntropySrcFatalAlert] = kTopMatchaAlertPeripheralEntropySrc,
+ [kTopMatchaAlertIdEdn0RecovAlert] = kTopMatchaAlertPeripheralEdn0,
+ [kTopMatchaAlertIdEdn0FatalAlert] = kTopMatchaAlertPeripheralEdn0,
+ [kTopMatchaAlertIdEdn1RecovAlert] = kTopMatchaAlertPeripheralEdn1,
+ [kTopMatchaAlertIdEdn1FatalAlert] = kTopMatchaAlertPeripheralEdn1,
+ [kTopMatchaAlertIdSramCtrlMainFatalError] = kTopMatchaAlertPeripheralSramCtrlMain,
+ [kTopMatchaAlertIdRomCtrlFatal] = kTopMatchaAlertPeripheralRomCtrl,
+ [kTopMatchaAlertIdRvCoreIbexSecFatalSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecRecovSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecFatalHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdRvCoreIbexSecRecovHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSec,
+ [kTopMatchaAlertIdSmcUartFatalFault] = kTopMatchaAlertPeripheralSmcUart,
+ [kTopMatchaAlertIdRvTimerSmcFatalFault] = kTopMatchaAlertPeripheralRvTimerSmc,
+ [kTopMatchaAlertIdCamI2cFatalFault] = kTopMatchaAlertPeripheralCamI2c,
+ [kTopMatchaAlertIdRvPlicSmcFatalFault] = kTopMatchaAlertPeripheralRvPlicSmc,
+ [kTopMatchaAlertIdSpiHost2FatalFault] = kTopMatchaAlertPeripheralSpiHost2,
+ [kTopMatchaAlertIdRvTimerSmc2FatalFault] = kTopMatchaAlertPeripheralRvTimerSmc2,
+ [kTopMatchaAlertIdRvCoreIbexSmcFatalSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcRecovSwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcFatalHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+ [kTopMatchaAlertIdRvCoreIbexSmcRecovHwErr] = kTopMatchaAlertPeripheralRvCoreIbexSmc,
+};
+
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.h b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.h
new file mode 100644
index 0000000..bdc6438
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha.h
@@ -0,0 +1,2392 @@
+// Copyright Google Inc.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
+#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
+
+#define MATCHA_SPARROW
+
+/**
+ * @file
+ * @brief Top-specific Definitions
+ *
+ * This file contains preprocessor and type definitions for use within the
+ * device C/C++ codebase.
+ *
+ * These definitions are for information that depends on the top-specific chip
+ * configuration, which includes:
+ * - Device Memory Information (for Peripherals and Memory)
+ * - PLIC Interrupt ID Names and Source Mappings
+ * - Alert ID Names and Source Mappings
+ * - Pinmux Pin/Select Names
+ * - Power Manager Wakeups
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Peripheral base address for uart0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000u
+
+/**
+ * Peripheral size for uart0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART0_BASE_ADDR and
+ * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000u
+
+/**
+ * Peripheral size for uart1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART1_BASE_ADDR and
+ * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000u
+
+/**
+ * Peripheral size for uart2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART2_BASE_ADDR and
+ * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for uart3 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000u
+
+/**
+ * Peripheral size for uart3 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART3_BASE_ADDR and
+ * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART3_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for gpio in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000u
+
+/**
+ * Peripheral size for gpio in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_GPIO_BASE_ADDR and
+ * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_device in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000u
+
+/**
+ * Peripheral size for spi_device in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for i2c0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000u
+
+/**
+ * Peripheral size for i2c0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C0_BASE_ADDR and
+ * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000u
+
+/**
+ * Peripheral size for i2c1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C1_BASE_ADDR and
+ * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for i2c2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000u
+
+/**
+ * Peripheral size for i2c2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C2_BASE_ADDR and
+ * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pattgen in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000u
+
+/**
+ * Peripheral size for pattgen in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
+ * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000u
+
+/**
+ * Peripheral size for rv_timer in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for core device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000u
+
+/**
+ * Peripheral size for core device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000u
+
+/**
+ * Peripheral base address for prim device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000u
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for lc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000u
+
+/**
+ * Peripheral size for lc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for alert_handler in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000u
+
+/**
+ * Peripheral size for alert_handler in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800u
+
+/**
+ * Peripheral base address for spi_host0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000u
+
+/**
+ * Peripheral size for spi_host0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for spi_host1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000u
+
+/**
+ * Peripheral size for spi_host1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for usbdev in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000u
+
+/**
+ * Peripheral size for usbdev in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
+ * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for pwrmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000u
+
+/**
+ * Peripheral size for pwrmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rstmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000u
+
+/**
+ * Peripheral size for rstmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for clkmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000u
+
+/**
+ * Peripheral size for clkmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000u
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for adc_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000u
+
+/**
+ * Peripheral size for adc_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pwm_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000u
+
+/**
+ * Peripheral size for pwm_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for pinmux_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000u
+
+/**
+ * Peripheral size for pinmux_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for aon_timer_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000u
+
+/**
+ * Peripheral size for aon_timer_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for ast in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_BASE_ADDR 0x40480000u
+
+/**
+ * Peripheral size for ast in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_BASE_ADDR and
+ * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_SIZE_BYTES 0x400u
+
+/**
+ * Peripheral base address for sensor_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000u
+
+/**
+ * Peripheral size for sensor_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for ast_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_AON_BASE_ADDR 0x404C0000u
+
+/**
+ * Peripheral size for ast_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_AON_BASE_ADDR and
+ * `TOP_MATCHA_AST_AON_BASE_ADDR + TOP_MATCHA_AST_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_AON_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for core device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000u
+
+/**
+ * Peripheral size for core device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for prim device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for mem device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000u
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000u
+
+/**
+ * Peripheral base address for regs device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000u
+
+/**
+ * Peripheral size for regs device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4u
+
+/**
+ * Peripheral base address for mem device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000u
+
+/**
+ * Peripheral size for mem device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for rv_plic in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000u
+
+/**
+ * Peripheral size for rv_plic in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for aes in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AES_BASE_ADDR 0x41100000u
+
+/**
+ * Peripheral size for aes in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AES_BASE_ADDR and
+ * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AES_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for hmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000u
+
+/**
+ * Peripheral size for hmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_HMAC_BASE_ADDR and
+ * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for kmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000u
+
+/**
+ * Peripheral size for kmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KMAC_BASE_ADDR and
+ * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for otbn in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000u
+
+/**
+ * Peripheral size for otbn in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTBN_BASE_ADDR and
+ * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for keymgr in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000u
+
+/**
+ * Peripheral size for keymgr in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
+ * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for csrng in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000u
+
+/**
+ * Peripheral size for csrng in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
+ * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for entropy_src in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000u
+
+/**
+ * Peripheral size for entropy_src in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for edn0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000u
+
+/**
+ * Peripheral size for edn0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN0_BASE_ADDR and
+ * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for edn1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000u
+
+/**
+ * Peripheral size for edn1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN1_BASE_ADDR and
+ * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000u
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20u
+
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000u
+
+/**
+ * Peripheral base address for regs device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000u
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for rom device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100u
+
+/**
+ * Peripheral base address for dma0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000u
+
+/**
+ * Peripheral size for dma0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA0_BASE_ADDR and
+ * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for smc_uart in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000u
+
+/**
+ * Peripheral size for smc_uart in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
+ * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000u
+
+/**
+ * Peripheral size for rv_timer_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for smc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000u
+
+/**
+ * Peripheral size for smc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8u
+
+/**
+ * Peripheral base address for cam_i2c in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000u
+
+/**
+ * Peripheral size for cam_i2c in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80u
+
+/**
+ * Peripheral base address for cam_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000u
+
+/**
+ * Peripheral size for cam_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10u
+
+/**
+ * Peripheral base address for vca device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR 0x55400000u
+
+/**
+ * Peripheral size for vca device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES 0x400000u
+
+/**
+ * Peripheral base address for isp device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR 0x54060000u
+
+/**
+ * Peripheral size for isp device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for enc device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR 0x55200000u
+
+/**
+ * Peripheral size for enc device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES 0x10000u
+
+/**
+ * Peripheral base address for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR 0x55000000u
+
+/**
+ * Peripheral size for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES 0x200000u
+
+/**
+ * Peripheral base address for vsi_ctl_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR 0x55210000u
+
+/**
+ * Peripheral size for vsi_ctl_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR and
+ * `TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR + TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for dma_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000u
+
+/**
+ * Peripheral size for dma_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_plic_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000u
+
+/**
+ * Peripheral size for rv_plic_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000u
+
+/**
+ * Peripheral base address for tlul_mailbox_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000u
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for tlul_mailbox_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000u
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for core device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000u
+
+/**
+ * Peripheral size for core device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for dmem device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Peripheral size for dmem device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000u
+
+/**
+ * Peripheral base address for spi_host2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000u
+
+/**
+ * Peripheral size for spi_host2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for rv_timer_smc2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000u
+
+/**
+ * Peripheral size for rv_timer_smc2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200u
+
+/**
+ * Peripheral base address for i2s0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000u
+
+/**
+ * Peripheral size for i2s0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2S0_BASE_ADDR and
+ * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40u
+
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000u
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100u
+
+
+/**
+ * Memory base address for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000u
+
+/**
+ * Memory size for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000u
+
+/**
+ * Memory base address for ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000u
+
+/**
+ * Memory size for ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000u
+
+/**
+ * Memory base address for eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000u
+
+/**
+ * Memory size for eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000u
+
+/**
+ * Memory base address for ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000u
+
+/**
+ * Memory size for ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000u
+
+/**
+ * Memory base address for rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_BASE_ADDR 0x8000u
+
+/**
+ * Memory size for rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000u
+
+/**
+ * Memory base address for video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_BASE_ADDR 0x55000000u
+
+/**
+ * Memory size for video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_SIZE_BYTES 0x200000u
+
+/**
+ * Memory base address for ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000u
+
+/**
+ * Memory size for ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000u
+
+
+/**
+ * PLIC Interrupt Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * interrupt.
+ */
+typedef enum top_matcha_plic_peripheral {
+ kTopMatchaPlicPeripheralUnknown = 0, /**< Unknown Peripheral */
+ kTopMatchaPlicPeripheralUart0 = 1, /**< uart0 */
+ kTopMatchaPlicPeripheralUart1 = 2, /**< uart1 */
+ kTopMatchaPlicPeripheralUart2 = 3, /**< uart2 */
+ kTopMatchaPlicPeripheralUart3 = 4, /**< uart3 */
+ kTopMatchaPlicPeripheralGpio = 5, /**< gpio */
+ kTopMatchaPlicPeripheralSpiDevice = 6, /**< spi_device */
+ kTopMatchaPlicPeripheralI2c0 = 7, /**< i2c0 */
+ kTopMatchaPlicPeripheralI2c1 = 8, /**< i2c1 */
+ kTopMatchaPlicPeripheralI2c2 = 9, /**< i2c2 */
+ kTopMatchaPlicPeripheralPattgen = 10, /**< pattgen */
+ kTopMatchaPlicPeripheralRvTimer = 11, /**< rv_timer */
+ kTopMatchaPlicPeripheralOtpCtrl = 12, /**< otp_ctrl */
+ kTopMatchaPlicPeripheralAlertHandler = 13, /**< alert_handler */
+ kTopMatchaPlicPeripheralSpiHost0 = 14, /**< spi_host0 */
+ kTopMatchaPlicPeripheralSpiHost1 = 15, /**< spi_host1 */
+ kTopMatchaPlicPeripheralUsbdev = 16, /**< usbdev */
+ kTopMatchaPlicPeripheralPwrmgrAon = 17, /**< pwrmgr_aon */
+ kTopMatchaPlicPeripheralSysrstCtrlAon = 18, /**< sysrst_ctrl_aon */
+ kTopMatchaPlicPeripheralAdcCtrlAon = 19, /**< adc_ctrl_aon */
+ kTopMatchaPlicPeripheralAonTimerAon = 20, /**< aon_timer_aon */
+ kTopMatchaPlicPeripheralSensorCtrl = 21, /**< sensor_ctrl */
+ kTopMatchaPlicPeripheralFlashCtrl = 22, /**< flash_ctrl */
+ kTopMatchaPlicPeripheralHmac = 23, /**< hmac */
+ kTopMatchaPlicPeripheralKmac = 24, /**< kmac */
+ kTopMatchaPlicPeripheralOtbn = 25, /**< otbn */
+ kTopMatchaPlicPeripheralKeymgr = 26, /**< keymgr */
+ kTopMatchaPlicPeripheralCsrng = 27, /**< csrng */
+ kTopMatchaPlicPeripheralEntropySrc = 28, /**< entropy_src */
+ kTopMatchaPlicPeripheralEdn0 = 29, /**< edn0 */
+ kTopMatchaPlicPeripheralEdn1 = 30, /**< edn1 */
+ kTopMatchaPlicPeripheralDma0 = 31, /**< dma0 */
+ kTopMatchaPlicPeripheralTlulMailboxSec = 32, /**< tlul_mailbox_sec */
+ kTopMatchaPlicPeripheralLast = 32, /**< \internal Final PLIC peripheral */
+} top_matcha_plic_peripheral_t;
+
+typedef enum top_matcha_plic_peripheral_smc {
+ kTopMatchaPlicPeripheralUnknownSmc = 0, /**< Unknown Peripheral */
+ kTopMatchaPlicPeripheralSmcUart = 1, /**< smc_uart */
+ kTopMatchaPlicPeripheralRvTimerSmc = 2, /**< rv_timer_smc */
+ kTopMatchaPlicPeripheralCamI2c = 3, /**< cam_i2c */
+ kTopMatchaPlicPeripheralCamCtrl = 4, /**< cam_ctrl */
+ kTopMatchaPlicPeripheralVideoAudioWrapper = 5, /**< video_audio_wrapper */
+ kTopMatchaPlicPeripheralDmaSmc = 6, /**< dma_smc */
+ kTopMatchaPlicPeripheralTlulMailboxSmc = 7, /**< tlul_mailbox_smc */
+ kTopMatchaPlicPeripheralMlTop = 8, /**< ml_top */
+ kTopMatchaPlicPeripheralSpiHost2 = 9, /**< spi_host2 */
+ kTopMatchaPlicPeripheralRvTimerSmc2 = 10, /**< rv_timer_smc2 */
+ kTopMatchaPlicPeripheralI2s0 = 11, /**< i2s0 */
+ kTopMatchaPlicPeripheralLastSmc = 11, /**< \internal Final PLIC peripheral */
+} top_matcha_plic_peripheral_smc_t;
+
+/**
+ * PLIC Interrupt Source.
+ *
+ * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_matcha_plic_irq_id {
+ kTopMatchaPlicIrqIdNone = 0, /**< No Interrupt */
+ kTopMatchaPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */
+ kTopMatchaPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */
+ kTopMatchaPlicIrqIdUart0TxEmpty = 3, /**< uart0_tx_empty */
+ kTopMatchaPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */
+ kTopMatchaPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */
+ kTopMatchaPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */
+ kTopMatchaPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */
+ kTopMatchaPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */
+ kTopMatchaPlicIrqIdUart1TxWatermark = 9, /**< uart1_tx_watermark */
+ kTopMatchaPlicIrqIdUart1RxWatermark = 10, /**< uart1_rx_watermark */
+ kTopMatchaPlicIrqIdUart1TxEmpty = 11, /**< uart1_tx_empty */
+ kTopMatchaPlicIrqIdUart1RxOverflow = 12, /**< uart1_rx_overflow */
+ kTopMatchaPlicIrqIdUart1RxFrameErr = 13, /**< uart1_rx_frame_err */
+ kTopMatchaPlicIrqIdUart1RxBreakErr = 14, /**< uart1_rx_break_err */
+ kTopMatchaPlicIrqIdUart1RxTimeout = 15, /**< uart1_rx_timeout */
+ kTopMatchaPlicIrqIdUart1RxParityErr = 16, /**< uart1_rx_parity_err */
+ kTopMatchaPlicIrqIdUart2TxWatermark = 17, /**< uart2_tx_watermark */
+ kTopMatchaPlicIrqIdUart2RxWatermark = 18, /**< uart2_rx_watermark */
+ kTopMatchaPlicIrqIdUart2TxEmpty = 19, /**< uart2_tx_empty */
+ kTopMatchaPlicIrqIdUart2RxOverflow = 20, /**< uart2_rx_overflow */
+ kTopMatchaPlicIrqIdUart2RxFrameErr = 21, /**< uart2_rx_frame_err */
+ kTopMatchaPlicIrqIdUart2RxBreakErr = 22, /**< uart2_rx_break_err */
+ kTopMatchaPlicIrqIdUart2RxTimeout = 23, /**< uart2_rx_timeout */
+ kTopMatchaPlicIrqIdUart2RxParityErr = 24, /**< uart2_rx_parity_err */
+ kTopMatchaPlicIrqIdUart3TxWatermark = 25, /**< uart3_tx_watermark */
+ kTopMatchaPlicIrqIdUart3RxWatermark = 26, /**< uart3_rx_watermark */
+ kTopMatchaPlicIrqIdUart3TxEmpty = 27, /**< uart3_tx_empty */
+ kTopMatchaPlicIrqIdUart3RxOverflow = 28, /**< uart3_rx_overflow */
+ kTopMatchaPlicIrqIdUart3RxFrameErr = 29, /**< uart3_rx_frame_err */
+ kTopMatchaPlicIrqIdUart3RxBreakErr = 30, /**< uart3_rx_break_err */
+ kTopMatchaPlicIrqIdUart3RxTimeout = 31, /**< uart3_rx_timeout */
+ kTopMatchaPlicIrqIdUart3RxParityErr = 32, /**< uart3_rx_parity_err */
+ kTopMatchaPlicIrqIdGpioGpio0 = 33, /**< gpio_gpio 0 */
+ kTopMatchaPlicIrqIdGpioGpio1 = 34, /**< gpio_gpio 1 */
+ kTopMatchaPlicIrqIdGpioGpio2 = 35, /**< gpio_gpio 2 */
+ kTopMatchaPlicIrqIdGpioGpio3 = 36, /**< gpio_gpio 3 */
+ kTopMatchaPlicIrqIdGpioGpio4 = 37, /**< gpio_gpio 4 */
+ kTopMatchaPlicIrqIdGpioGpio5 = 38, /**< gpio_gpio 5 */
+ kTopMatchaPlicIrqIdGpioGpio6 = 39, /**< gpio_gpio 6 */
+ kTopMatchaPlicIrqIdGpioGpio7 = 40, /**< gpio_gpio 7 */
+ kTopMatchaPlicIrqIdGpioGpio8 = 41, /**< gpio_gpio 8 */
+ kTopMatchaPlicIrqIdGpioGpio9 = 42, /**< gpio_gpio 9 */
+ kTopMatchaPlicIrqIdGpioGpio10 = 43, /**< gpio_gpio 10 */
+ kTopMatchaPlicIrqIdGpioGpio11 = 44, /**< gpio_gpio 11 */
+ kTopMatchaPlicIrqIdGpioGpio12 = 45, /**< gpio_gpio 12 */
+ kTopMatchaPlicIrqIdGpioGpio13 = 46, /**< gpio_gpio 13 */
+ kTopMatchaPlicIrqIdGpioGpio14 = 47, /**< gpio_gpio 14 */
+ kTopMatchaPlicIrqIdGpioGpio15 = 48, /**< gpio_gpio 15 */
+ kTopMatchaPlicIrqIdGpioGpio16 = 49, /**< gpio_gpio 16 */
+ kTopMatchaPlicIrqIdGpioGpio17 = 50, /**< gpio_gpio 17 */
+ kTopMatchaPlicIrqIdGpioGpio18 = 51, /**< gpio_gpio 18 */
+ kTopMatchaPlicIrqIdGpioGpio19 = 52, /**< gpio_gpio 19 */
+ kTopMatchaPlicIrqIdGpioGpio20 = 53, /**< gpio_gpio 20 */
+ kTopMatchaPlicIrqIdGpioGpio21 = 54, /**< gpio_gpio 21 */
+ kTopMatchaPlicIrqIdGpioGpio22 = 55, /**< gpio_gpio 22 */
+ kTopMatchaPlicIrqIdGpioGpio23 = 56, /**< gpio_gpio 23 */
+ kTopMatchaPlicIrqIdGpioGpio24 = 57, /**< gpio_gpio 24 */
+ kTopMatchaPlicIrqIdGpioGpio25 = 58, /**< gpio_gpio 25 */
+ kTopMatchaPlicIrqIdGpioGpio26 = 59, /**< gpio_gpio 26 */
+ kTopMatchaPlicIrqIdGpioGpio27 = 60, /**< gpio_gpio 27 */
+ kTopMatchaPlicIrqIdGpioGpio28 = 61, /**< gpio_gpio 28 */
+ kTopMatchaPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
+ kTopMatchaPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
+ kTopMatchaPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxFull = 65, /**< spi_device_generic_rx_full */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxWatermark = 66, /**< spi_device_generic_rx_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceGenericTxWatermark = 67, /**< spi_device_generic_tx_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxError = 68, /**< spi_device_generic_rx_error */
+ kTopMatchaPlicIrqIdSpiDeviceGenericRxOverflow = 69, /**< spi_device_generic_rx_overflow */
+ kTopMatchaPlicIrqIdSpiDeviceGenericTxUnderflow = 70, /**< spi_device_generic_tx_underflow */
+ kTopMatchaPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 71, /**< spi_device_upload_cmdfifo_not_empty */
+ kTopMatchaPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 72, /**< spi_device_upload_payload_not_empty */
+ kTopMatchaPlicIrqIdSpiDeviceUploadPayloadOverflow = 73, /**< spi_device_upload_payload_overflow */
+ kTopMatchaPlicIrqIdSpiDeviceReadbufWatermark = 74, /**< spi_device_readbuf_watermark */
+ kTopMatchaPlicIrqIdSpiDeviceReadbufFlip = 75, /**< spi_device_readbuf_flip */
+ kTopMatchaPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 76, /**< spi_device_tpm_header_not_empty */
+ kTopMatchaPlicIrqIdI2c0FmtThreshold = 77, /**< i2c0_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c0RxThreshold = 78, /**< i2c0_rx_threshold */
+ kTopMatchaPlicIrqIdI2c0FmtOverflow = 79, /**< i2c0_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c0RxOverflow = 80, /**< i2c0_rx_overflow */
+ kTopMatchaPlicIrqIdI2c0Nak = 81, /**< i2c0_nak */
+ kTopMatchaPlicIrqIdI2c0SclInterference = 82, /**< i2c0_scl_interference */
+ kTopMatchaPlicIrqIdI2c0SdaInterference = 83, /**< i2c0_sda_interference */
+ kTopMatchaPlicIrqIdI2c0StretchTimeout = 84, /**< i2c0_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c0SdaUnstable = 85, /**< i2c0_sda_unstable */
+ kTopMatchaPlicIrqIdI2c0CmdComplete = 86, /**< i2c0_cmd_complete */
+ kTopMatchaPlicIrqIdI2c0TxStretch = 87, /**< i2c0_tx_stretch */
+ kTopMatchaPlicIrqIdI2c0TxOverflow = 88, /**< i2c0_tx_overflow */
+ kTopMatchaPlicIrqIdI2c0AcqFull = 89, /**< i2c0_acq_full */
+ kTopMatchaPlicIrqIdI2c0UnexpStop = 90, /**< i2c0_unexp_stop */
+ kTopMatchaPlicIrqIdI2c0HostTimeout = 91, /**< i2c0_host_timeout */
+ kTopMatchaPlicIrqIdI2c1FmtThreshold = 92, /**< i2c1_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c1RxThreshold = 93, /**< i2c1_rx_threshold */
+ kTopMatchaPlicIrqIdI2c1FmtOverflow = 94, /**< i2c1_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c1RxOverflow = 95, /**< i2c1_rx_overflow */
+ kTopMatchaPlicIrqIdI2c1Nak = 96, /**< i2c1_nak */
+ kTopMatchaPlicIrqIdI2c1SclInterference = 97, /**< i2c1_scl_interference */
+ kTopMatchaPlicIrqIdI2c1SdaInterference = 98, /**< i2c1_sda_interference */
+ kTopMatchaPlicIrqIdI2c1StretchTimeout = 99, /**< i2c1_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c1SdaUnstable = 100, /**< i2c1_sda_unstable */
+ kTopMatchaPlicIrqIdI2c1CmdComplete = 101, /**< i2c1_cmd_complete */
+ kTopMatchaPlicIrqIdI2c1TxStretch = 102, /**< i2c1_tx_stretch */
+ kTopMatchaPlicIrqIdI2c1TxOverflow = 103, /**< i2c1_tx_overflow */
+ kTopMatchaPlicIrqIdI2c1AcqFull = 104, /**< i2c1_acq_full */
+ kTopMatchaPlicIrqIdI2c1UnexpStop = 105, /**< i2c1_unexp_stop */
+ kTopMatchaPlicIrqIdI2c1HostTimeout = 106, /**< i2c1_host_timeout */
+ kTopMatchaPlicIrqIdI2c2FmtThreshold = 107, /**< i2c2_fmt_threshold */
+ kTopMatchaPlicIrqIdI2c2RxThreshold = 108, /**< i2c2_rx_threshold */
+ kTopMatchaPlicIrqIdI2c2FmtOverflow = 109, /**< i2c2_fmt_overflow */
+ kTopMatchaPlicIrqIdI2c2RxOverflow = 110, /**< i2c2_rx_overflow */
+ kTopMatchaPlicIrqIdI2c2Nak = 111, /**< i2c2_nak */
+ kTopMatchaPlicIrqIdI2c2SclInterference = 112, /**< i2c2_scl_interference */
+ kTopMatchaPlicIrqIdI2c2SdaInterference = 113, /**< i2c2_sda_interference */
+ kTopMatchaPlicIrqIdI2c2StretchTimeout = 114, /**< i2c2_stretch_timeout */
+ kTopMatchaPlicIrqIdI2c2SdaUnstable = 115, /**< i2c2_sda_unstable */
+ kTopMatchaPlicIrqIdI2c2CmdComplete = 116, /**< i2c2_cmd_complete */
+ kTopMatchaPlicIrqIdI2c2TxStretch = 117, /**< i2c2_tx_stretch */
+ kTopMatchaPlicIrqIdI2c2TxOverflow = 118, /**< i2c2_tx_overflow */
+ kTopMatchaPlicIrqIdI2c2AcqFull = 119, /**< i2c2_acq_full */
+ kTopMatchaPlicIrqIdI2c2UnexpStop = 120, /**< i2c2_unexp_stop */
+ kTopMatchaPlicIrqIdI2c2HostTimeout = 121, /**< i2c2_host_timeout */
+ kTopMatchaPlicIrqIdPattgenDoneCh0 = 122, /**< pattgen_done_ch0 */
+ kTopMatchaPlicIrqIdPattgenDoneCh1 = 123, /**< pattgen_done_ch1 */
+ kTopMatchaPlicIrqIdRvTimerTimerExpiredHart0Timer0 = 124, /**< rv_timer_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdOtpCtrlOtpOperationDone = 125, /**< otp_ctrl_otp_operation_done */
+ kTopMatchaPlicIrqIdOtpCtrlOtpError = 126, /**< otp_ctrl_otp_error */
+ kTopMatchaPlicIrqIdAlertHandlerClassa = 127, /**< alert_handler_classa */
+ kTopMatchaPlicIrqIdAlertHandlerClassb = 128, /**< alert_handler_classb */
+ kTopMatchaPlicIrqIdAlertHandlerClassc = 129, /**< alert_handler_classc */
+ kTopMatchaPlicIrqIdAlertHandlerClassd = 130, /**< alert_handler_classd */
+ kTopMatchaPlicIrqIdSpiHost0Error = 131, /**< spi_host0_error */
+ kTopMatchaPlicIrqIdSpiHost0SpiEvent = 132, /**< spi_host0_spi_event */
+ kTopMatchaPlicIrqIdSpiHost1Error = 133, /**< spi_host1_error */
+ kTopMatchaPlicIrqIdSpiHost1SpiEvent = 134, /**< spi_host1_spi_event */
+ kTopMatchaPlicIrqIdUsbdevPktReceived = 135, /**< usbdev_pkt_received */
+ kTopMatchaPlicIrqIdUsbdevPktSent = 136, /**< usbdev_pkt_sent */
+ kTopMatchaPlicIrqIdUsbdevDisconnected = 137, /**< usbdev_disconnected */
+ kTopMatchaPlicIrqIdUsbdevHostLost = 138, /**< usbdev_host_lost */
+ kTopMatchaPlicIrqIdUsbdevLinkReset = 139, /**< usbdev_link_reset */
+ kTopMatchaPlicIrqIdUsbdevLinkSuspend = 140, /**< usbdev_link_suspend */
+ kTopMatchaPlicIrqIdUsbdevLinkResume = 141, /**< usbdev_link_resume */
+ kTopMatchaPlicIrqIdUsbdevAvEmpty = 142, /**< usbdev_av_empty */
+ kTopMatchaPlicIrqIdUsbdevRxFull = 143, /**< usbdev_rx_full */
+ kTopMatchaPlicIrqIdUsbdevAvOverflow = 144, /**< usbdev_av_overflow */
+ kTopMatchaPlicIrqIdUsbdevLinkInErr = 145, /**< usbdev_link_in_err */
+ kTopMatchaPlicIrqIdUsbdevRxCrcErr = 146, /**< usbdev_rx_crc_err */
+ kTopMatchaPlicIrqIdUsbdevRxPidErr = 147, /**< usbdev_rx_pid_err */
+ kTopMatchaPlicIrqIdUsbdevRxBitstuffErr = 148, /**< usbdev_rx_bitstuff_err */
+ kTopMatchaPlicIrqIdUsbdevFrame = 149, /**< usbdev_frame */
+ kTopMatchaPlicIrqIdUsbdevPowered = 150, /**< usbdev_powered */
+ kTopMatchaPlicIrqIdUsbdevLinkOutErr = 151, /**< usbdev_link_out_err */
+ kTopMatchaPlicIrqIdPwrmgrAonWakeup = 152, /**< pwrmgr_aon_wakeup */
+ kTopMatchaPlicIrqIdSysrstCtrlAonEventDetected = 153, /**< sysrst_ctrl_aon_event_detected */
+ kTopMatchaPlicIrqIdAdcCtrlAonMatchDone = 154, /**< adc_ctrl_aon_match_done */
+ kTopMatchaPlicIrqIdAonTimerAonWkupTimerExpired = 155, /**< aon_timer_aon_wkup_timer_expired */
+ kTopMatchaPlicIrqIdAonTimerAonWdogTimerBark = 156, /**< aon_timer_aon_wdog_timer_bark */
+ kTopMatchaPlicIrqIdSensorCtrlIoStatusChange = 157, /**< sensor_ctrl_io_status_change */
+ kTopMatchaPlicIrqIdSensorCtrlInitStatusChange = 158, /**< sensor_ctrl_init_status_change */
+ kTopMatchaPlicIrqIdFlashCtrlProgEmpty = 159, /**< flash_ctrl_prog_empty */
+ kTopMatchaPlicIrqIdFlashCtrlProgLvl = 160, /**< flash_ctrl_prog_lvl */
+ kTopMatchaPlicIrqIdFlashCtrlRdFull = 161, /**< flash_ctrl_rd_full */
+ kTopMatchaPlicIrqIdFlashCtrlRdLvl = 162, /**< flash_ctrl_rd_lvl */
+ kTopMatchaPlicIrqIdFlashCtrlOpDone = 163, /**< flash_ctrl_op_done */
+ kTopMatchaPlicIrqIdFlashCtrlCorrErr = 164, /**< flash_ctrl_corr_err */
+ kTopMatchaPlicIrqIdHmacHmacDone = 165, /**< hmac_hmac_done */
+ kTopMatchaPlicIrqIdHmacFifoEmpty = 166, /**< hmac_fifo_empty */
+ kTopMatchaPlicIrqIdHmacHmacErr = 167, /**< hmac_hmac_err */
+ kTopMatchaPlicIrqIdKmacKmacDone = 168, /**< kmac_kmac_done */
+ kTopMatchaPlicIrqIdKmacFifoEmpty = 169, /**< kmac_fifo_empty */
+ kTopMatchaPlicIrqIdKmacKmacErr = 170, /**< kmac_kmac_err */
+ kTopMatchaPlicIrqIdOtbnDone = 171, /**< otbn_done */
+ kTopMatchaPlicIrqIdKeymgrOpDone = 172, /**< keymgr_op_done */
+ kTopMatchaPlicIrqIdCsrngCsCmdReqDone = 173, /**< csrng_cs_cmd_req_done */
+ kTopMatchaPlicIrqIdCsrngCsEntropyReq = 174, /**< csrng_cs_entropy_req */
+ kTopMatchaPlicIrqIdCsrngCsHwInstExc = 175, /**< csrng_cs_hw_inst_exc */
+ kTopMatchaPlicIrqIdCsrngCsFatalErr = 176, /**< csrng_cs_fatal_err */
+ kTopMatchaPlicIrqIdEntropySrcEsEntropyValid = 177, /**< entropy_src_es_entropy_valid */
+ kTopMatchaPlicIrqIdEntropySrcEsHealthTestFailed = 178, /**< entropy_src_es_health_test_failed */
+ kTopMatchaPlicIrqIdEntropySrcEsObserveFifoReady = 179, /**< entropy_src_es_observe_fifo_ready */
+ kTopMatchaPlicIrqIdEntropySrcEsFatalErr = 180, /**< entropy_src_es_fatal_err */
+ kTopMatchaPlicIrqIdEdn0EdnCmdReqDone = 181, /**< edn0_edn_cmd_req_done */
+ kTopMatchaPlicIrqIdEdn0EdnFatalErr = 182, /**< edn0_edn_fatal_err */
+ kTopMatchaPlicIrqIdEdn1EdnCmdReqDone = 183, /**< edn1_edn_cmd_req_done */
+ kTopMatchaPlicIrqIdEdn1EdnFatalErr = 184, /**< edn1_edn_fatal_err */
+ kTopMatchaPlicIrqIdDma0WriterDone = 185, /**< dma0_writer_done */
+ kTopMatchaPlicIrqIdDma0ReaderDone = 186, /**< dma0_reader_done */
+ kTopMatchaPlicIrqIdTlulMailboxSecWtirq = 187, /**< tlul_mailbox_sec_wtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSecRtirq = 188, /**< tlul_mailbox_sec_rtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSecEirq = 189, /**< tlul_mailbox_sec_eirq */
+ kTopMatchaPlicIrqIdLast = 189, /**< \internal The Last Valid Interrupt ID. */
+} top_matcha_plic_irq_id_t;
+
+typedef enum top_matcha_plic_irq_id_smc {
+ kTopMatchaPlicIrqIdNoneSmc = 0, /**< No Interrupt */
+ kTopMatchaPlicIrqIdSmcUartTxWatermark = 1, /**< smc_uart_tx_watermark */
+ kTopMatchaPlicIrqIdSmcUartRxWatermark = 2, /**< smc_uart_rx_watermark */
+ kTopMatchaPlicIrqIdSmcUartTxEmpty = 3, /**< smc_uart_tx_empty */
+ kTopMatchaPlicIrqIdSmcUartRxOverflow = 4, /**< smc_uart_rx_overflow */
+ kTopMatchaPlicIrqIdSmcUartRxFrameErr = 5, /**< smc_uart_rx_frame_err */
+ kTopMatchaPlicIrqIdSmcUartRxBreakErr = 6, /**< smc_uart_rx_break_err */
+ kTopMatchaPlicIrqIdSmcUartRxTimeout = 7, /**< smc_uart_rx_timeout */
+ kTopMatchaPlicIrqIdSmcUartRxParityErr = 8, /**< smc_uart_rx_parity_err */
+ kTopMatchaPlicIrqIdRvTimerSmcTimerExpiredHart0Timer0 = 9, /**< rv_timer_smc_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdCamI2cFmtThreshold = 10, /**< cam_i2c_fmt_threshold */
+ kTopMatchaPlicIrqIdCamI2cRxThreshold = 11, /**< cam_i2c_rx_threshold */
+ kTopMatchaPlicIrqIdCamI2cFmtOverflow = 12, /**< cam_i2c_fmt_overflow */
+ kTopMatchaPlicIrqIdCamI2cRxOverflow = 13, /**< cam_i2c_rx_overflow */
+ kTopMatchaPlicIrqIdCamI2cNak = 14, /**< cam_i2c_nak */
+ kTopMatchaPlicIrqIdCamI2cSclInterference = 15, /**< cam_i2c_scl_interference */
+ kTopMatchaPlicIrqIdCamI2cSdaInterference = 16, /**< cam_i2c_sda_interference */
+ kTopMatchaPlicIrqIdCamI2cStretchTimeout = 17, /**< cam_i2c_stretch_timeout */
+ kTopMatchaPlicIrqIdCamI2cSdaUnstable = 18, /**< cam_i2c_sda_unstable */
+ kTopMatchaPlicIrqIdCamI2cCmdComplete = 19, /**< cam_i2c_cmd_complete */
+ kTopMatchaPlicIrqIdCamI2cTxStretch = 20, /**< cam_i2c_tx_stretch */
+ kTopMatchaPlicIrqIdCamI2cTxOverflow = 21, /**< cam_i2c_tx_overflow */
+ kTopMatchaPlicIrqIdCamI2cAcqFull = 22, /**< cam_i2c_acq_full */
+ kTopMatchaPlicIrqIdCamI2cUnexpStop = 23, /**< cam_i2c_unexp_stop */
+ kTopMatchaPlicIrqIdCamI2cHostTimeout = 24, /**< cam_i2c_host_timeout */
+ kTopMatchaPlicIrqIdCamCtrlCamMotionDetect = 25, /**< cam_ctrl_cam_motion_detect */
+ kTopMatchaPlicIrqIdVideoAudioWrapperIsp = 26, /**< video_audio_wrapper_isp */
+ kTopMatchaPlicIrqIdVideoAudioWrapperMi = 27, /**< video_audio_wrapper_mi */
+ kTopMatchaPlicIrqIdVideoAudioWrapperMipi = 28, /**< video_audio_wrapper_mipi */
+ kTopMatchaPlicIrqIdVideoAudioWrapperEncoder = 29, /**< video_audio_wrapper_encoder */
+ kTopMatchaPlicIrqIdVideoAudioWrapperUpstream = 30, /**< video_audio_wrapper_upstream */
+ kTopMatchaPlicIrqIdVideoAudioWrapperAudioSmc = 31, /**< video_audio_wrapper_audio_smc */
+ kTopMatchaPlicIrqIdDmaSmcWriterDone = 32, /**< dma_smc_writer_done */
+ kTopMatchaPlicIrqIdDmaSmcReaderDone = 33, /**< dma_smc_reader_done */
+ kTopMatchaPlicIrqIdTlulMailboxSmcWtirq = 34, /**< tlul_mailbox_smc_wtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSmcRtirq = 35, /**< tlul_mailbox_smc_rtirq */
+ kTopMatchaPlicIrqIdTlulMailboxSmcEirq = 36, /**< tlul_mailbox_smc_eirq */
+ kTopMatchaPlicIrqIdMlTopHostReq = 37, /**< ml_top_host_req */
+ kTopMatchaPlicIrqIdMlTopFinish = 38, /**< ml_top_finish */
+ kTopMatchaPlicIrqIdMlTopFault = 39, /**< ml_top_fault */
+ kTopMatchaPlicIrqIdSpiHost2Error = 40, /**< spi_host2_error */
+ kTopMatchaPlicIrqIdSpiHost2SpiEvent = 41, /**< spi_host2_spi_event */
+ kTopMatchaPlicIrqIdRvTimerSmc2TimerExpiredHart0Timer0 = 42, /**< rv_timer_smc2_timer_expired_hart0_timer0 */
+ kTopMatchaPlicIrqIdI2s0TxWatermark = 43, /**< i2s0_tx_watermark */
+ kTopMatchaPlicIrqIdI2s0RxWatermark = 44, /**< i2s0_rx_watermark */
+ kTopMatchaPlicIrqIdI2s0TxEmpty = 45, /**< i2s0_tx_empty */
+ kTopMatchaPlicIrqIdI2s0RxOverflow = 46, /**< i2s0_rx_overflow */
+ kTopMatchaPlicIrqIdLastSmc = 46, /**< \internal The Last Valid Interrupt ID. */
+} top_matcha_plic_irq_id_smc_t;
+
+/**
+ * PLIC Interrupt Source to Peripheral Map
+ *
+ * This array is a mapping from `top_matcha_plic_irq_id_t` to
+ * `top_matcha_plic_peripheral_t`.
+ */
+extern const top_matcha_plic_peripheral_t
+ top_matcha_plic_interrupt_for_peripheral[190];
+
+extern const top_matcha_plic_peripheral_smc_t
+ top_matcha_plic_interrupt_for_peripheral_smc[47];
+
+/**
+ * PLIC Interrupt Target.
+ *
+ * Enumeration used to determine which set of IE, CC, threshold registers to
+ * access for a given interrupt target.
+ */
+typedef enum top_matcha_plic_target {
+ kTopMatchaPlicTargetIbex0 = 0, /**< Ibex Core 0 */
+ kTopMatchaPlicTargetIbex1 = 1, /**< Ibex Core 1 */
+ kTopMatchaPlicTargetLast = 1, /**< \internal Final PLIC target */
+} top_matcha_plic_target_t;
+
+typedef enum top_matcha_plic_target_smc {
+ kTopMatchaPlicTargetIbex0Smc = 0, /**< Ibex Core 0 */
+ kTopMatchaPlicTargetLastSmc = 0, /**< \internal Final PLIC target */
+} top_matcha_plic_target_smc_t;
+
+/**
+ * Alert Handler Source Peripheral.
+ *
+ * Enumeration used to determine which peripheral asserted the corresponding
+ * alert.
+ */
+typedef enum top_matcha_alert_peripheral {
+ kTopMatchaAlertPeripheralUart0 = 0, /**< uart0 */
+ kTopMatchaAlertPeripheralUart1 = 1, /**< uart1 */
+ kTopMatchaAlertPeripheralUart2 = 2, /**< uart2 */
+ kTopMatchaAlertPeripheralUart3 = 3, /**< uart3 */
+ kTopMatchaAlertPeripheralGpio = 4, /**< gpio */
+ kTopMatchaAlertPeripheralSpiDevice = 5, /**< spi_device */
+ kTopMatchaAlertPeripheralI2c0 = 6, /**< i2c0 */
+ kTopMatchaAlertPeripheralI2c1 = 7, /**< i2c1 */
+ kTopMatchaAlertPeripheralI2c2 = 8, /**< i2c2 */
+ kTopMatchaAlertPeripheralPattgen = 9, /**< pattgen */
+ kTopMatchaAlertPeripheralRvTimer = 10, /**< rv_timer */
+ kTopMatchaAlertPeripheralOtpCtrl = 11, /**< otp_ctrl */
+ kTopMatchaAlertPeripheralLcCtrl = 12, /**< lc_ctrl */
+ kTopMatchaAlertPeripheralSpiHost0 = 13, /**< spi_host0 */
+ kTopMatchaAlertPeripheralSpiHost1 = 14, /**< spi_host1 */
+ kTopMatchaAlertPeripheralUsbdev = 15, /**< usbdev */
+ kTopMatchaAlertPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
+ kTopMatchaAlertPeripheralRstmgrAon = 17, /**< rstmgr_aon */
+ kTopMatchaAlertPeripheralClkmgrAon = 18, /**< clkmgr_aon */
+ kTopMatchaAlertPeripheralSysrstCtrlAon = 19, /**< sysrst_ctrl_aon */
+ kTopMatchaAlertPeripheralAdcCtrlAon = 20, /**< adc_ctrl_aon */
+ kTopMatchaAlertPeripheralPwmAon = 21, /**< pwm_aon */
+ kTopMatchaAlertPeripheralPinmuxAon = 22, /**< pinmux_aon */
+ kTopMatchaAlertPeripheralAonTimerAon = 23, /**< aon_timer_aon */
+ kTopMatchaAlertPeripheralSensorCtrl = 24, /**< sensor_ctrl */
+ kTopMatchaAlertPeripheralSramCtrlRetAon = 25, /**< sram_ctrl_ret_aon */
+ kTopMatchaAlertPeripheralFlashCtrl = 26, /**< flash_ctrl */
+ kTopMatchaAlertPeripheralRvDm = 27, /**< rv_dm */
+ kTopMatchaAlertPeripheralRvPlic = 28, /**< rv_plic */
+ kTopMatchaAlertPeripheralAes = 29, /**< aes */
+ kTopMatchaAlertPeripheralHmac = 30, /**< hmac */
+ kTopMatchaAlertPeripheralKmac = 31, /**< kmac */
+ kTopMatchaAlertPeripheralOtbn = 32, /**< otbn */
+ kTopMatchaAlertPeripheralKeymgr = 33, /**< keymgr */
+ kTopMatchaAlertPeripheralCsrng = 34, /**< csrng */
+ kTopMatchaAlertPeripheralEntropySrc = 35, /**< entropy_src */
+ kTopMatchaAlertPeripheralEdn0 = 36, /**< edn0 */
+ kTopMatchaAlertPeripheralEdn1 = 37, /**< edn1 */
+ kTopMatchaAlertPeripheralSramCtrlMain = 38, /**< sram_ctrl_main */
+ kTopMatchaAlertPeripheralRomCtrl = 39, /**< rom_ctrl */
+ kTopMatchaAlertPeripheralRvCoreIbexSec = 40, /**< rv_core_ibex_sec */
+ kTopMatchaAlertPeripheralSmcUart = 41, /**< smc_uart */
+ kTopMatchaAlertPeripheralRvTimerSmc = 42, /**< rv_timer_smc */
+ kTopMatchaAlertPeripheralCamI2c = 43, /**< cam_i2c */
+ kTopMatchaAlertPeripheralRvPlicSmc = 44, /**< rv_plic_smc */
+ kTopMatchaAlertPeripheralSpiHost2 = 45, /**< spi_host2 */
+ kTopMatchaAlertPeripheralRvTimerSmc2 = 46, /**< rv_timer_smc2 */
+ kTopMatchaAlertPeripheralRvCoreIbexSmc = 47, /**< rv_core_ibex_smc */
+ kTopMatchaAlertPeripheralLast = 47, /**< \internal Final Alert peripheral */
+} top_matcha_alert_peripheral_t;
+
+/**
+ * Alert Handler Alert Source.
+ *
+ * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
+ * the same peripheral are guaranteed to be consecutive.
+ */
+typedef enum top_matcha_alert_id {
+ kTopMatchaAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
+ kTopMatchaAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
+ kTopMatchaAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
+ kTopMatchaAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
+ kTopMatchaAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
+ kTopMatchaAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
+ kTopMatchaAlertIdI2c0FatalFault = 6, /**< i2c0_fatal_fault */
+ kTopMatchaAlertIdI2c1FatalFault = 7, /**< i2c1_fatal_fault */
+ kTopMatchaAlertIdI2c2FatalFault = 8, /**< i2c2_fatal_fault */
+ kTopMatchaAlertIdPattgenFatalFault = 9, /**< pattgen_fatal_fault */
+ kTopMatchaAlertIdRvTimerFatalFault = 10, /**< rv_timer_fatal_fault */
+ kTopMatchaAlertIdOtpCtrlFatalMacroError = 11, /**< otp_ctrl_fatal_macro_error */
+ kTopMatchaAlertIdOtpCtrlFatalCheckError = 12, /**< otp_ctrl_fatal_check_error */
+ kTopMatchaAlertIdOtpCtrlFatalBusIntegError = 13, /**< otp_ctrl_fatal_bus_integ_error */
+ kTopMatchaAlertIdOtpCtrlFatalPrimOtpAlert = 14, /**< otp_ctrl_fatal_prim_otp_alert */
+ kTopMatchaAlertIdOtpCtrlRecovPrimOtpAlert = 15, /**< otp_ctrl_recov_prim_otp_alert */
+ kTopMatchaAlertIdLcCtrlFatalProgError = 16, /**< lc_ctrl_fatal_prog_error */
+ kTopMatchaAlertIdLcCtrlFatalStateError = 17, /**< lc_ctrl_fatal_state_error */
+ kTopMatchaAlertIdLcCtrlFatalBusIntegError = 18, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopMatchaAlertIdSpiHost0FatalFault = 19, /**< spi_host0_fatal_fault */
+ kTopMatchaAlertIdSpiHost1FatalFault = 20, /**< spi_host1_fatal_fault */
+ kTopMatchaAlertIdUsbdevFatalFault = 21, /**< usbdev_fatal_fault */
+ kTopMatchaAlertIdPwrmgrAonFatalFault = 22, /**< pwrmgr_aon_fatal_fault */
+ kTopMatchaAlertIdRstmgrAonFatalFault = 23, /**< rstmgr_aon_fatal_fault */
+ kTopMatchaAlertIdRstmgrAonFatalCnstyFault = 24, /**< rstmgr_aon_fatal_cnsty_fault */
+ kTopMatchaAlertIdClkmgrAonRecovFault = 25, /**< clkmgr_aon_recov_fault */
+ kTopMatchaAlertIdClkmgrAonFatalFault = 26, /**< clkmgr_aon_fatal_fault */
+ kTopMatchaAlertIdSysrstCtrlAonFatalFault = 27, /**< sysrst_ctrl_aon_fatal_fault */
+ kTopMatchaAlertIdAdcCtrlAonFatalFault = 28, /**< adc_ctrl_aon_fatal_fault */
+ kTopMatchaAlertIdPwmAonFatalFault = 29, /**< pwm_aon_fatal_fault */
+ kTopMatchaAlertIdPinmuxAonFatalFault = 30, /**< pinmux_aon_fatal_fault */
+ kTopMatchaAlertIdAonTimerAonFatalFault = 31, /**< aon_timer_aon_fatal_fault */
+ kTopMatchaAlertIdSensorCtrlRecovAlert = 32, /**< sensor_ctrl_recov_alert */
+ kTopMatchaAlertIdSensorCtrlFatalAlert = 33, /**< sensor_ctrl_fatal_alert */
+ kTopMatchaAlertIdSramCtrlRetAonFatalError = 34, /**< sram_ctrl_ret_aon_fatal_error */
+ kTopMatchaAlertIdFlashCtrlRecovErr = 35, /**< flash_ctrl_recov_err */
+ kTopMatchaAlertIdFlashCtrlFatalStdErr = 36, /**< flash_ctrl_fatal_std_err */
+ kTopMatchaAlertIdFlashCtrlFatalErr = 37, /**< flash_ctrl_fatal_err */
+ kTopMatchaAlertIdFlashCtrlFatalPrimFlashAlert = 38, /**< flash_ctrl_fatal_prim_flash_alert */
+ kTopMatchaAlertIdFlashCtrlRecovPrimFlashAlert = 39, /**< flash_ctrl_recov_prim_flash_alert */
+ kTopMatchaAlertIdRvDmFatalFault = 40, /**< rv_dm_fatal_fault */
+ kTopMatchaAlertIdRvPlicFatalFault = 41, /**< rv_plic_fatal_fault */
+ kTopMatchaAlertIdAesRecovCtrlUpdateErr = 42, /**< aes_recov_ctrl_update_err */
+ kTopMatchaAlertIdAesFatalFault = 43, /**< aes_fatal_fault */
+ kTopMatchaAlertIdHmacFatalFault = 44, /**< hmac_fatal_fault */
+ kTopMatchaAlertIdKmacRecovOperationErr = 45, /**< kmac_recov_operation_err */
+ kTopMatchaAlertIdKmacFatalFaultErr = 46, /**< kmac_fatal_fault_err */
+ kTopMatchaAlertIdOtbnFatal = 47, /**< otbn_fatal */
+ kTopMatchaAlertIdOtbnRecov = 48, /**< otbn_recov */
+ kTopMatchaAlertIdKeymgrRecovOperationErr = 49, /**< keymgr_recov_operation_err */
+ kTopMatchaAlertIdKeymgrFatalFaultErr = 50, /**< keymgr_fatal_fault_err */
+ kTopMatchaAlertIdCsrngRecovAlert = 51, /**< csrng_recov_alert */
+ kTopMatchaAlertIdCsrngFatalAlert = 52, /**< csrng_fatal_alert */
+ kTopMatchaAlertIdEntropySrcRecovAlert = 53, /**< entropy_src_recov_alert */
+ kTopMatchaAlertIdEntropySrcFatalAlert = 54, /**< entropy_src_fatal_alert */
+ kTopMatchaAlertIdEdn0RecovAlert = 55, /**< edn0_recov_alert */
+ kTopMatchaAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */
+ kTopMatchaAlertIdEdn1RecovAlert = 57, /**< edn1_recov_alert */
+ kTopMatchaAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */
+ kTopMatchaAlertIdSramCtrlMainFatalError = 59, /**< sram_ctrl_main_fatal_error */
+ kTopMatchaAlertIdRomCtrlFatal = 60, /**< rom_ctrl_fatal */
+ kTopMatchaAlertIdRvCoreIbexSecFatalSwErr = 61, /**< rv_core_ibex_sec_fatal_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSecRecovSwErr = 62, /**< rv_core_ibex_sec_recov_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSecFatalHwErr = 63, /**< rv_core_ibex_sec_fatal_hw_err */
+ kTopMatchaAlertIdRvCoreIbexSecRecovHwErr = 64, /**< rv_core_ibex_sec_recov_hw_err */
+ kTopMatchaAlertIdSmcUartFatalFault = 65, /**< smc_uart_fatal_fault */
+ kTopMatchaAlertIdRvTimerSmcFatalFault = 66, /**< rv_timer_smc_fatal_fault */
+ kTopMatchaAlertIdCamI2cFatalFault = 67, /**< cam_i2c_fatal_fault */
+ kTopMatchaAlertIdRvPlicSmcFatalFault = 68, /**< rv_plic_smc_fatal_fault */
+ kTopMatchaAlertIdSpiHost2FatalFault = 69, /**< spi_host2_fatal_fault */
+ kTopMatchaAlertIdRvTimerSmc2FatalFault = 70, /**< rv_timer_smc2_fatal_fault */
+ kTopMatchaAlertIdRvCoreIbexSmcFatalSwErr = 71, /**< rv_core_ibex_smc_fatal_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcRecovSwErr = 72, /**< rv_core_ibex_smc_recov_sw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcFatalHwErr = 73, /**< rv_core_ibex_smc_fatal_hw_err */
+ kTopMatchaAlertIdRvCoreIbexSmcRecovHwErr = 74, /**< rv_core_ibex_smc_recov_hw_err */
+ kTopMatchaAlertIdLast = 74, /**< \internal The Last Valid Alert ID. */
+} top_matcha_alert_id_t;
+
+/**
+ * Alert Handler Alert Source to Peripheral Map
+ *
+ * This array is a mapping from `top_matcha_alert_id_t` to
+ * `top_matcha_alert_peripheral_t`.
+ */
+extern const top_matcha_alert_peripheral_t
+ top_matcha_alert_for_peripheral[75];
+
+#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
+// 0 and 1 are tied to value 0 and 1
+#define NUM_MIO_PADS 53
+#define NUM_DIO_PADS 16
+
+#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
+
+/**
+ * Pinmux Peripheral Input.
+ */
+typedef enum top_matcha_pinmux_peripheral_in {
+ kTopMatchaPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
+ kTopMatchaPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
+ kTopMatchaPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
+ kTopMatchaPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
+ kTopMatchaPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
+ kTopMatchaPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
+ kTopMatchaPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
+ kTopMatchaPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
+ kTopMatchaPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
+ kTopMatchaPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
+ kTopMatchaPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
+ kTopMatchaPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
+ kTopMatchaPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
+ kTopMatchaPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
+ kTopMatchaPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
+ kTopMatchaPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
+ kTopMatchaPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
+ kTopMatchaPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
+ kTopMatchaPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
+ kTopMatchaPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
+ kTopMatchaPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
+ kTopMatchaPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
+ kTopMatchaPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
+ kTopMatchaPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
+ kTopMatchaPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
+ kTopMatchaPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
+ kTopMatchaPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
+ kTopMatchaPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
+ kTopMatchaPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
+ kTopMatchaPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
+ kTopMatchaPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
+ kTopMatchaPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
+ kTopMatchaPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
+ kTopMatchaPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
+ kTopMatchaPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
+ kTopMatchaPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
+ kTopMatchaPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
+ kTopMatchaPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
+ kTopMatchaPinmuxPeripheralInCamI2cSda = 38, /**< Peripheral Input 38 */
+ kTopMatchaPinmuxPeripheralInCamI2cScl = 39, /**< Peripheral Input 39 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sWs = 40, /**< Peripheral Input 40 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sSck = 41, /**< Peripheral Input 41 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd0 = 42, /**< Peripheral Input 42 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd1 = 43, /**< Peripheral Input 43 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd2 = 44, /**< Peripheral Input 44 */
+ kTopMatchaPinmuxPeripheralInSpiHost1Sd3 = 45, /**< Peripheral Input 45 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd0 = 46, /**< Peripheral Input 46 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd1 = 47, /**< Peripheral Input 47 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd2 = 48, /**< Peripheral Input 48 */
+ kTopMatchaPinmuxPeripheralInSpiHost2Sd3 = 49, /**< Peripheral Input 49 */
+ kTopMatchaPinmuxPeripheralInUart0Rx = 50, /**< Peripheral Input 50 */
+ kTopMatchaPinmuxPeripheralInUart1Rx = 51, /**< Peripheral Input 51 */
+ kTopMatchaPinmuxPeripheralInUart2Rx = 52, /**< Peripheral Input 52 */
+ kTopMatchaPinmuxPeripheralInSmcUartRx = 53, /**< Peripheral Input 53 */
+ kTopMatchaPinmuxPeripheralInCamCtrlCamInt = 54, /**< Peripheral Input 54 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData0 = 55, /**< Peripheral Input 55 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData1 = 56, /**< Peripheral Input 56 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData2 = 57, /**< Peripheral Input 57 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData3 = 58, /**< Peripheral Input 58 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData4 = 59, /**< Peripheral Input 59 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData5 = 60, /**< Peripheral Input 60 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData6 = 61, /**< Peripheral Input 61 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData7 = 62, /**< Peripheral Input 62 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSHsync = 63, /**< Peripheral Input 63 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperSVsync = 64, /**< Peripheral Input 64 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioPdmDat = 65, /**< Peripheral Input 65 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTck = 66, /**< Peripheral Input 66 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTms = 67, /**< Peripheral Input 67 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagTdi = 68, /**< Peripheral Input 68 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperJtagRstn = 69, /**< Peripheral Input 69 */
+ kTopMatchaPinmuxPeripheralInVideoAudioWrapperAudioI2sSdIn = 70, /**< Peripheral Input 70 */
+ kTopMatchaPinmuxPeripheralInVsiCtlWrapperIspSclk = 71, /**< Peripheral Input 71 */
+ kTopMatchaPinmuxPeripheralInI2s0RxSd = 72, /**< Peripheral Input 72 */
+ kTopMatchaPinmuxPeripheralInSpiDeviceTpmCsb = 73, /**< Peripheral Input 73 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTck = 74, /**< Peripheral Input 74 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTms = 75, /**< Peripheral Input 75 */
+ kTopMatchaPinmuxPeripheralInFlashCtrlTdi = 76, /**< Peripheral Input 76 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonAcPresent = 77, /**< Peripheral Input 77 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey0In = 78, /**< Peripheral Input 78 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey1In = 79, /**< Peripheral Input 79 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonKey2In = 80, /**< Peripheral Input 80 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonPwrbIn = 81, /**< Peripheral Input 81 */
+ kTopMatchaPinmuxPeripheralInSysrstCtrlAonLidOpen = 82, /**< Peripheral Input 82 */
+ kTopMatchaPinmuxPeripheralInUsbdevSense = 83, /**< Peripheral Input 83 */
+ kTopMatchaPinmuxPeripheralInLast = 83, /**< \internal Last valid peripheral input */
+} top_matcha_pinmux_peripheral_in_t;
+
+/**
+ * Pinmux MIO Input Selector.
+ */
+typedef enum top_matcha_pinmux_insel {
+ kTopMatchaPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
+ kTopMatchaPinmuxInselConstantOne = 1, /**< Tie constantly to one */
+ kTopMatchaPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
+ kTopMatchaPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
+ kTopMatchaPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
+ kTopMatchaPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
+ kTopMatchaPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
+ kTopMatchaPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
+ kTopMatchaPinmuxInselIoa6 = 8, /**< MIO Pad 6 */
+ kTopMatchaPinmuxInselIoa7 = 9, /**< MIO Pad 7 */
+ kTopMatchaPinmuxInselIoa8 = 10, /**< MIO Pad 8 */
+ kTopMatchaPinmuxInselIob0 = 11, /**< MIO Pad 9 */
+ kTopMatchaPinmuxInselIob1 = 12, /**< MIO Pad 10 */
+ kTopMatchaPinmuxInselIob2 = 13, /**< MIO Pad 11 */
+ kTopMatchaPinmuxInselIob3 = 14, /**< MIO Pad 12 */
+ kTopMatchaPinmuxInselIob4 = 15, /**< MIO Pad 13 */
+ kTopMatchaPinmuxInselIob5 = 16, /**< MIO Pad 14 */
+ kTopMatchaPinmuxInselIob6 = 17, /**< MIO Pad 15 */
+ kTopMatchaPinmuxInselIob7 = 18, /**< MIO Pad 16 */
+ kTopMatchaPinmuxInselIob8 = 19, /**< MIO Pad 17 */
+ kTopMatchaPinmuxInselIob9 = 20, /**< MIO Pad 18 */
+ kTopMatchaPinmuxInselIob10 = 21, /**< MIO Pad 19 */
+ kTopMatchaPinmuxInselIob11 = 22, /**< MIO Pad 20 */
+ kTopMatchaPinmuxInselIob12 = 23, /**< MIO Pad 21 */
+ kTopMatchaPinmuxInselIoc0 = 24, /**< MIO Pad 22 */
+ kTopMatchaPinmuxInselIoc1 = 25, /**< MIO Pad 23 */
+ kTopMatchaPinmuxInselIoc2 = 26, /**< MIO Pad 24 */
+ kTopMatchaPinmuxInselIoc3 = 27, /**< MIO Pad 25 */
+ kTopMatchaPinmuxInselIoc4 = 28, /**< MIO Pad 26 */
+ kTopMatchaPinmuxInselIoc5 = 29, /**< MIO Pad 27 */
+ kTopMatchaPinmuxInselIoc6 = 30, /**< MIO Pad 28 */
+ kTopMatchaPinmuxInselIoc7 = 31, /**< MIO Pad 29 */
+ kTopMatchaPinmuxInselIoc8 = 32, /**< MIO Pad 30 */
+ kTopMatchaPinmuxInselIoc9 = 33, /**< MIO Pad 31 */
+ kTopMatchaPinmuxInselIoc10 = 34, /**< MIO Pad 32 */
+ kTopMatchaPinmuxInselIoc11 = 35, /**< MIO Pad 33 */
+ kTopMatchaPinmuxInselIoc12 = 36, /**< MIO Pad 34 */
+ kTopMatchaPinmuxInselIor0 = 37, /**< MIO Pad 35 */
+ kTopMatchaPinmuxInselIor1 = 38, /**< MIO Pad 36 */
+ kTopMatchaPinmuxInselIor2 = 39, /**< MIO Pad 37 */
+ kTopMatchaPinmuxInselIor3 = 40, /**< MIO Pad 38 */
+ kTopMatchaPinmuxInselIor4 = 41, /**< MIO Pad 39 */
+ kTopMatchaPinmuxInselIor5 = 42, /**< MIO Pad 40 */
+ kTopMatchaPinmuxInselIor6 = 43, /**< MIO Pad 41 */
+ kTopMatchaPinmuxInselIor7 = 44, /**< MIO Pad 42 */
+ kTopMatchaPinmuxInselIor10 = 45, /**< MIO Pad 43 */
+ kTopMatchaPinmuxInselIor11 = 46, /**< MIO Pad 44 */
+ kTopMatchaPinmuxInselIor12 = 47, /**< MIO Pad 45 */
+ kTopMatchaPinmuxInselIor13 = 48, /**< MIO Pad 46 */
+ kTopMatchaPinmuxInselIod0 = 49, /**< MIO Pad 47 */
+ kTopMatchaPinmuxInselIod1 = 50, /**< MIO Pad 48 */
+ kTopMatchaPinmuxInselIod2 = 51, /**< MIO Pad 49 */
+ kTopMatchaPinmuxInselIod3 = 52, /**< MIO Pad 50 */
+ kTopMatchaPinmuxInselIod4 = 53, /**< MIO Pad 51 */
+ kTopMatchaPinmuxInselIod5 = 54, /**< MIO Pad 52 */
+ kTopMatchaPinmuxInselLast = 54, /**< \internal Last valid insel value */
+} top_matcha_pinmux_insel_t;
+
+/**
+ * Pinmux MIO Output.
+ */
+typedef enum top_matcha_pinmux_mio_out {
+ kTopMatchaPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
+ kTopMatchaPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
+ kTopMatchaPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
+ kTopMatchaPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
+ kTopMatchaPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
+ kTopMatchaPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
+ kTopMatchaPinmuxMioOutIoa6 = 6, /**< MIO Pad 6 */
+ kTopMatchaPinmuxMioOutIoa7 = 7, /**< MIO Pad 7 */
+ kTopMatchaPinmuxMioOutIoa8 = 8, /**< MIO Pad 8 */
+ kTopMatchaPinmuxMioOutIob0 = 9, /**< MIO Pad 9 */
+ kTopMatchaPinmuxMioOutIob1 = 10, /**< MIO Pad 10 */
+ kTopMatchaPinmuxMioOutIob2 = 11, /**< MIO Pad 11 */
+ kTopMatchaPinmuxMioOutIob3 = 12, /**< MIO Pad 12 */
+ kTopMatchaPinmuxMioOutIob4 = 13, /**< MIO Pad 13 */
+ kTopMatchaPinmuxMioOutIob5 = 14, /**< MIO Pad 14 */
+ kTopMatchaPinmuxMioOutIob6 = 15, /**< MIO Pad 15 */
+ kTopMatchaPinmuxMioOutIob7 = 16, /**< MIO Pad 16 */
+ kTopMatchaPinmuxMioOutIob8 = 17, /**< MIO Pad 17 */
+ kTopMatchaPinmuxMioOutIob9 = 18, /**< MIO Pad 18 */
+ kTopMatchaPinmuxMioOutIob10 = 19, /**< MIO Pad 19 */
+ kTopMatchaPinmuxMioOutIob11 = 20, /**< MIO Pad 20 */
+ kTopMatchaPinmuxMioOutIob12 = 21, /**< MIO Pad 21 */
+ kTopMatchaPinmuxMioOutIoc0 = 22, /**< MIO Pad 22 */
+ kTopMatchaPinmuxMioOutIoc1 = 23, /**< MIO Pad 23 */
+ kTopMatchaPinmuxMioOutIoc2 = 24, /**< MIO Pad 24 */
+ kTopMatchaPinmuxMioOutIoc3 = 25, /**< MIO Pad 25 */
+ kTopMatchaPinmuxMioOutIoc4 = 26, /**< MIO Pad 26 */
+ kTopMatchaPinmuxMioOutIoc5 = 27, /**< MIO Pad 27 */
+ kTopMatchaPinmuxMioOutIoc6 = 28, /**< MIO Pad 28 */
+ kTopMatchaPinmuxMioOutIoc7 = 29, /**< MIO Pad 29 */
+ kTopMatchaPinmuxMioOutIoc8 = 30, /**< MIO Pad 30 */
+ kTopMatchaPinmuxMioOutIoc9 = 31, /**< MIO Pad 31 */
+ kTopMatchaPinmuxMioOutIoc10 = 32, /**< MIO Pad 32 */
+ kTopMatchaPinmuxMioOutIoc11 = 33, /**< MIO Pad 33 */
+ kTopMatchaPinmuxMioOutIoc12 = 34, /**< MIO Pad 34 */
+ kTopMatchaPinmuxMioOutIor0 = 35, /**< MIO Pad 35 */
+ kTopMatchaPinmuxMioOutIor1 = 36, /**< MIO Pad 36 */
+ kTopMatchaPinmuxMioOutIor2 = 37, /**< MIO Pad 37 */
+ kTopMatchaPinmuxMioOutIor3 = 38, /**< MIO Pad 38 */
+ kTopMatchaPinmuxMioOutIor4 = 39, /**< MIO Pad 39 */
+ kTopMatchaPinmuxMioOutIor5 = 40, /**< MIO Pad 40 */
+ kTopMatchaPinmuxMioOutIor6 = 41, /**< MIO Pad 41 */
+ kTopMatchaPinmuxMioOutIor7 = 42, /**< MIO Pad 42 */
+ kTopMatchaPinmuxMioOutIor10 = 43, /**< MIO Pad 43 */
+ kTopMatchaPinmuxMioOutIor11 = 44, /**< MIO Pad 44 */
+ kTopMatchaPinmuxMioOutIor12 = 45, /**< MIO Pad 45 */
+ kTopMatchaPinmuxMioOutIor13 = 46, /**< MIO Pad 46 */
+ kTopMatchaPinmuxMioOutIod0 = 47, /**< MIO Pad 47 */
+ kTopMatchaPinmuxMioOutIod1 = 48, /**< MIO Pad 48 */
+ kTopMatchaPinmuxMioOutIod2 = 49, /**< MIO Pad 49 */
+ kTopMatchaPinmuxMioOutIod3 = 50, /**< MIO Pad 50 */
+ kTopMatchaPinmuxMioOutIod4 = 51, /**< MIO Pad 51 */
+ kTopMatchaPinmuxMioOutIod5 = 52, /**< MIO Pad 52 */
+ kTopMatchaPinmuxMioOutLast = 52, /**< \internal Last valid mio output */
+} top_matcha_pinmux_mio_out_t;
+
+/**
+ * Pinmux Peripheral Output Selector.
+ */
+typedef enum top_matcha_pinmux_outsel {
+ kTopMatchaPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
+ kTopMatchaPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
+ kTopMatchaPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
+ kTopMatchaPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
+ kTopMatchaPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
+ kTopMatchaPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
+ kTopMatchaPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
+ kTopMatchaPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
+ kTopMatchaPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
+ kTopMatchaPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
+ kTopMatchaPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
+ kTopMatchaPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
+ kTopMatchaPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
+ kTopMatchaPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
+ kTopMatchaPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
+ kTopMatchaPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
+ kTopMatchaPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
+ kTopMatchaPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
+ kTopMatchaPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
+ kTopMatchaPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
+ kTopMatchaPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
+ kTopMatchaPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
+ kTopMatchaPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
+ kTopMatchaPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
+ kTopMatchaPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
+ kTopMatchaPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
+ kTopMatchaPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
+ kTopMatchaPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
+ kTopMatchaPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
+ kTopMatchaPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
+ kTopMatchaPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
+ kTopMatchaPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
+ kTopMatchaPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
+ kTopMatchaPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
+ kTopMatchaPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
+ kTopMatchaPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
+ kTopMatchaPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
+ kTopMatchaPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
+ kTopMatchaPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
+ kTopMatchaPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
+ kTopMatchaPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
+ kTopMatchaPinmuxOutselCamI2cSda = 41, /**< Peripheral Output 38 */
+ kTopMatchaPinmuxOutselCamI2cScl = 42, /**< Peripheral Output 39 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sWs = 43, /**< Peripheral Output 40 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sSck = 44, /**< Peripheral Output 41 */
+ kTopMatchaPinmuxOutselSpiHost1Sd0 = 45, /**< Peripheral Output 42 */
+ kTopMatchaPinmuxOutselSpiHost1Sd1 = 46, /**< Peripheral Output 43 */
+ kTopMatchaPinmuxOutselSpiHost1Sd2 = 47, /**< Peripheral Output 44 */
+ kTopMatchaPinmuxOutselSpiHost1Sd3 = 48, /**< Peripheral Output 45 */
+ kTopMatchaPinmuxOutselSpiHost2Sd0 = 49, /**< Peripheral Output 46 */
+ kTopMatchaPinmuxOutselSpiHost2Sd1 = 50, /**< Peripheral Output 47 */
+ kTopMatchaPinmuxOutselSpiHost2Sd2 = 51, /**< Peripheral Output 48 */
+ kTopMatchaPinmuxOutselSpiHost2Sd3 = 52, /**< Peripheral Output 49 */
+ kTopMatchaPinmuxOutselUart0Tx = 53, /**< Peripheral Output 50 */
+ kTopMatchaPinmuxOutselUart1Tx = 54, /**< Peripheral Output 51 */
+ kTopMatchaPinmuxOutselUart2Tx = 55, /**< Peripheral Output 52 */
+ kTopMatchaPinmuxOutselSmcUartTx = 56, /**< Peripheral Output 53 */
+ kTopMatchaPinmuxOutselCamCtrlCamTrig = 57, /**< Peripheral Output 54 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperJtagTdo = 58, /**< Peripheral Output 55 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioPdmClk = 59, /**< Peripheral Output 56 */
+ kTopMatchaPinmuxOutselVideoAudioWrapperAudioI2sSdOut = 60, /**< Peripheral Output 57 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllSysClkoDiv8 = 61, /**< Peripheral Output 58 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllMlClkoDiv8 = 62, /**< Peripheral Output 59 */
+ kTopMatchaPinmuxOutselVsiCtlWrapperPllAudioClkoDiv8 = 63, /**< Peripheral Output 60 */
+ kTopMatchaPinmuxOutselI2s0RxSclk = 64, /**< Peripheral Output 61 */
+ kTopMatchaPinmuxOutselI2s0RxWs = 65, /**< Peripheral Output 62 */
+ kTopMatchaPinmuxOutselI2s0TxSclk = 66, /**< Peripheral Output 63 */
+ kTopMatchaPinmuxOutselI2s0TxWs = 67, /**< Peripheral Output 64 */
+ kTopMatchaPinmuxOutselI2s0TxSd = 68, /**< Peripheral Output 65 */
+ kTopMatchaPinmuxOutselPattgenPda0Tx = 69, /**< Peripheral Output 66 */
+ kTopMatchaPinmuxOutselPattgenPcl0Tx = 70, /**< Peripheral Output 67 */
+ kTopMatchaPinmuxOutselPattgenPda1Tx = 71, /**< Peripheral Output 68 */
+ kTopMatchaPinmuxOutselPattgenPcl1Tx = 72, /**< Peripheral Output 69 */
+ kTopMatchaPinmuxOutselSpiHost1Sck = 73, /**< Peripheral Output 70 */
+ kTopMatchaPinmuxOutselSpiHost1Csb = 74, /**< Peripheral Output 71 */
+ kTopMatchaPinmuxOutselSpiHost2Sck = 75, /**< Peripheral Output 72 */
+ kTopMatchaPinmuxOutselSpiHost2Csb = 76, /**< Peripheral Output 73 */
+ kTopMatchaPinmuxOutselFlashCtrlTdo = 77, /**< Peripheral Output 74 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut0 = 78, /**< Peripheral Output 75 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut1 = 79, /**< Peripheral Output 76 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut2 = 80, /**< Peripheral Output 77 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut3 = 81, /**< Peripheral Output 78 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut4 = 82, /**< Peripheral Output 79 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut5 = 83, /**< Peripheral Output 80 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut6 = 84, /**< Peripheral Output 81 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut7 = 85, /**< Peripheral Output 82 */
+ kTopMatchaPinmuxOutselSensorCtrlAstDebugOut8 = 86, /**< Peripheral Output 83 */
+ kTopMatchaPinmuxOutselPwmAonPwm0 = 87, /**< Peripheral Output 84 */
+ kTopMatchaPinmuxOutselPwmAonPwm1 = 88, /**< Peripheral Output 85 */
+ kTopMatchaPinmuxOutselPwmAonPwm2 = 89, /**< Peripheral Output 86 */
+ kTopMatchaPinmuxOutselPwmAonPwm3 = 90, /**< Peripheral Output 87 */
+ kTopMatchaPinmuxOutselPwmAonPwm4 = 91, /**< Peripheral Output 88 */
+ kTopMatchaPinmuxOutselPwmAonPwm5 = 92, /**< Peripheral Output 89 */
+ kTopMatchaPinmuxOutselOtpCtrlTest0 = 93, /**< Peripheral Output 90 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonBatDisable = 94, /**< Peripheral Output 91 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey0Out = 95, /**< Peripheral Output 92 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey1Out = 96, /**< Peripheral Output 93 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonKey2Out = 97, /**< Peripheral Output 94 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonPwrbOut = 98, /**< Peripheral Output 95 */
+ kTopMatchaPinmuxOutselSysrstCtrlAonZ3Wakeup = 99, /**< Peripheral Output 96 */
+ kTopMatchaPinmuxOutselLast = 99, /**< \internal Last valid outsel value */
+} top_matcha_pinmux_outsel_t;
+
+/**
+ * Dedicated Pad Selects
+ */
+typedef enum top_matcha_direct_pads {
+ kTopMatchaDirectPadsUsbdevUsbDp = 0, /**< */
+ kTopMatchaDirectPadsUsbdevUsbDn = 1, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd0 = 2, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd1 = 3, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd2 = 4, /**< */
+ kTopMatchaDirectPadsSpiHost0Sd3 = 5, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd0 = 6, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd1 = 7, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd2 = 8, /**< */
+ kTopMatchaDirectPadsSpiDeviceSd3 = 9, /**< */
+ kTopMatchaDirectPadsSysrstCtrlAonEcRstL = 10, /**< */
+ kTopMatchaDirectPadsSysrstCtrlAonFlashWpL = 11, /**< */
+ kTopMatchaDirectPadsSpiDeviceSck = 12, /**< */
+ kTopMatchaDirectPadsSpiDeviceCsb = 13, /**< */
+ kTopMatchaDirectPadsSpiHost0Sck = 14, /**< */
+ kTopMatchaDirectPadsSpiHost0Csb = 15, /**< */
+ kTopMatchaDirectPadsLast = 15, /**< \internal Last valid direct pad */
+} top_matcha_direct_pads_t;
+
+/**
+ * Muxed Pad Selects
+ */
+typedef enum top_matcha_muxed_pads {
+ kTopMatchaMuxedPadsIoa0 = 0, /**< */
+ kTopMatchaMuxedPadsIoa1 = 1, /**< */
+ kTopMatchaMuxedPadsIoa2 = 2, /**< */
+ kTopMatchaMuxedPadsIoa3 = 3, /**< */
+ kTopMatchaMuxedPadsIoa4 = 4, /**< */
+ kTopMatchaMuxedPadsIoa5 = 5, /**< */
+ kTopMatchaMuxedPadsIoa6 = 6, /**< */
+ kTopMatchaMuxedPadsIoa7 = 7, /**< */
+ kTopMatchaMuxedPadsIoa8 = 8, /**< */
+ kTopMatchaMuxedPadsIob0 = 9, /**< */
+ kTopMatchaMuxedPadsIob1 = 10, /**< */
+ kTopMatchaMuxedPadsIob2 = 11, /**< */
+ kTopMatchaMuxedPadsIob3 = 12, /**< */
+ kTopMatchaMuxedPadsIob4 = 13, /**< */
+ kTopMatchaMuxedPadsIob5 = 14, /**< */
+ kTopMatchaMuxedPadsIob6 = 15, /**< */
+ kTopMatchaMuxedPadsIob7 = 16, /**< */
+ kTopMatchaMuxedPadsIob8 = 17, /**< */
+ kTopMatchaMuxedPadsIob9 = 18, /**< */
+ kTopMatchaMuxedPadsIob10 = 19, /**< */
+ kTopMatchaMuxedPadsIob11 = 20, /**< */
+ kTopMatchaMuxedPadsIob12 = 21, /**< */
+ kTopMatchaMuxedPadsIoc0 = 22, /**< */
+ kTopMatchaMuxedPadsIoc1 = 23, /**< */
+ kTopMatchaMuxedPadsIoc2 = 24, /**< */
+ kTopMatchaMuxedPadsIoc3 = 25, /**< */
+ kTopMatchaMuxedPadsIoc4 = 26, /**< */
+ kTopMatchaMuxedPadsIoc5 = 27, /**< */
+ kTopMatchaMuxedPadsIoc6 = 28, /**< */
+ kTopMatchaMuxedPadsIoc7 = 29, /**< */
+ kTopMatchaMuxedPadsIoc8 = 30, /**< */
+ kTopMatchaMuxedPadsIoc9 = 31, /**< */
+ kTopMatchaMuxedPadsIoc10 = 32, /**< */
+ kTopMatchaMuxedPadsIoc11 = 33, /**< */
+ kTopMatchaMuxedPadsIoc12 = 34, /**< */
+ kTopMatchaMuxedPadsIor0 = 35, /**< */
+ kTopMatchaMuxedPadsIor1 = 36, /**< */
+ kTopMatchaMuxedPadsIor2 = 37, /**< */
+ kTopMatchaMuxedPadsIor3 = 38, /**< */
+ kTopMatchaMuxedPadsIor4 = 39, /**< */
+ kTopMatchaMuxedPadsIor5 = 40, /**< */
+ kTopMatchaMuxedPadsIor6 = 41, /**< */
+ kTopMatchaMuxedPadsIor7 = 42, /**< */
+ kTopMatchaMuxedPadsIor10 = 43, /**< */
+ kTopMatchaMuxedPadsIor11 = 44, /**< */
+ kTopMatchaMuxedPadsIor12 = 45, /**< */
+ kTopMatchaMuxedPadsIor13 = 46, /**< */
+ kTopMatchaMuxedPadsIod0 = 47, /**< */
+ kTopMatchaMuxedPadsIod1 = 48, /**< */
+ kTopMatchaMuxedPadsIod2 = 49, /**< */
+ kTopMatchaMuxedPadsIod3 = 50, /**< */
+ kTopMatchaMuxedPadsIod4 = 51, /**< */
+ kTopMatchaMuxedPadsIod5 = 52, /**< */
+ kTopMatchaMuxedPadsLast = 52, /**< \internal Last valid muxed pad */
+} top_matcha_muxed_pads_t;
+
+/**
+ * Power Manager Wakeup Signals
+ */
+typedef enum top_matcha_power_manager_wake_ups {
+ kTopMatchaPowerManagerWakeUpsSysrstCtrlAonWkupReq = 0, /**< */
+ kTopMatchaPowerManagerWakeUpsAdcCtrlAonWkupReq = 1, /**< */
+ kTopMatchaPowerManagerWakeUpsPinmuxAonPinWkupReq = 2, /**< */
+ kTopMatchaPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
+ kTopMatchaPowerManagerWakeUpsAonTimerAonWkupReq = 4, /**< */
+ kTopMatchaPowerManagerWakeUpsSensorCtrlWkupReq = 5, /**< */
+ kTopMatchaPowerManagerWakeUpsLast = 5, /**< \internal Last valid pwrmgr wakeup signal */
+} top_matcha_power_manager_wake_ups_t;
+
+/**
+ * Reset Manager Software Controlled Resets
+ */
+typedef enum top_matcha_reset_manager_sw_resets {
+ kTopMatchaResetManagerSwResetsSpiDevice = 0, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost0 = 1, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost1 = 2, /**< */
+ kTopMatchaResetManagerSwResetsSpiHost2 = 3, /**< */
+ kTopMatchaResetManagerSwResetsUsb = 4, /**< */
+ kTopMatchaResetManagerSwResetsUsbAon = 5, /**< */
+ kTopMatchaResetManagerSwResetsI2c0 = 6, /**< */
+ kTopMatchaResetManagerSwResetsI2c1 = 7, /**< */
+ kTopMatchaResetManagerSwResetsI2c2 = 8, /**< */
+ kTopMatchaResetManagerSwResetsSmc = 9, /**< */
+ kTopMatchaResetManagerSwResetsMl = 10, /**< */
+ kTopMatchaResetManagerSwResetsCamI2c = 11, /**< */
+ kTopMatchaResetManagerSwResetsVideo = 12, /**< */
+ kTopMatchaResetManagerSwResetsAudio = 13, /**< */
+ kTopMatchaResetManagerSwResetsLast = 13, /**< \internal Last valid rstmgr software reset request */
+} top_matcha_reset_manager_sw_resets_t;
+
+/**
+ * Power Manager Reset Request Signals
+ */
+typedef enum top_matcha_power_manager_reset_requests {
+ kTopMatchaPowerManagerResetRequestsSysrstCtrlAonRstReq = 0, /**< */
+ kTopMatchaPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
+ kTopMatchaPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
+} top_matcha_power_manager_reset_requests_t;
+
+/**
+ * Clock Manager Software-Controlled ("Gated") Clocks.
+ *
+ * The Software has full control over these clocks.
+ */
+typedef enum top_matcha_gateable_clocks {
+ kTopMatchaGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */
+ kTopMatchaGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */
+ kTopMatchaGateableClocksIoPeri = 2, /**< Clock clk_io_peri in group peri */
+ kTopMatchaGateableClocksUsbPeri = 3, /**< Clock clk_usb_peri in group peri */
+ kTopMatchaGateableClocksMlPeri = 4, /**< Clock clk_ml_peri in group peri */
+ kTopMatchaGateableClocksAudioPeri = 5, /**< Clock clk_audio_peri in group peri */
+ kTopMatchaGateableClocksSmcPeri = 6, /**< Clock clk_smc_peri in group peri */
+ kTopMatchaGateableClocksLast = 6, /**< \internal Last Valid Gateable Clock */
+} top_matcha_gateable_clocks_t;
+
+/**
+ * Clock Manager Software-Hinted Clocks.
+ *
+ * The Software has partial control over these clocks. It can ask them to stop,
+ * but the clock manager is in control of whether the clock actually is stopped.
+ */
+typedef enum top_matcha_hintable_clocks {
+ kTopMatchaHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */
+ kTopMatchaHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */
+ kTopMatchaHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */
+ kTopMatchaHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */
+ kTopMatchaHintableClocksSmcVideoAudioWrapper = 4, /**< Clock clk_smc_video_audio_wrapper in group trans */
+ kTopMatchaHintableClocksVideoVsiCtlWrapper = 5, /**< Clock clk_video_vsi_ctl_wrapper in group trans */
+ kTopMatchaHintableClocksAudioVsiCtlWrapper = 6, /**< Clock clk_audio_vsi_ctl_wrapper in group trans */
+ kTopMatchaHintableClocksLast = 6, /**< \internal Last Valid Hintable Clock */
+} top_matcha_hintable_clocks_t;
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000u
+#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000u
+
+// Header Extern Guard
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_H_
diff --git a/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha_memory.h b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha_memory.h
new file mode 100644
index 0000000..32d46ac
--- /dev/null
+++ b/hw/top_matcha/sparrow/hw/top_matcha/sw/autogen/top_matcha_memory.h
@@ -0,0 +1,1333 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
+#define MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
+
+/**
+ * @file
+ * @brief Assembler-only Top-Specific Definitions.
+ *
+ * This file contains preprocessor definitions for use within assembly code.
+ *
+ * These are not shared with C/C++ code because these are only allowed to be
+ * preprocessor definitions, no data or type declarations are allowed. The
+ * assembler is also stricter about literals (not allowing suffixes for
+ * signed/unsigned which are sensible to use for unsigned values in C/C++).
+ */
+
+// Include guard for assembler
+#ifdef __ASSEMBLER__
+
+
+/**
+ * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_BASE_ADDR 0x40600000
+
+/**
+ * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top matcha.
+ */
+#define TOP_MATCHA_RAM_RET_AON_SIZE_BYTES 0x1000
+
+/**
+ * Memory base for flash_ctrl_eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_BASE_ADDR 0x20000000
+
+/**
+ * Memory size for flash_ctrl_eflash in top matcha.
+ */
+#define TOP_MATCHA_EFLASH_SIZE_BYTES 0x100000
+
+/**
+ * Memory base for sram_ctrl_main_ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_BASE_ADDR 0x10000000
+
+/**
+ * Memory size for sram_ctrl_main_ram_main in top matcha.
+ */
+#define TOP_MATCHA_RAM_MAIN_SIZE_BYTES 0x20000
+
+/**
+ * Memory base for rom_ctrl_rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_BASE_ADDR 0x00008000
+
+/**
+ * Memory size for rom_ctrl_rom in top matcha.
+ */
+#define TOP_MATCHA_ROM_SIZE_BYTES 0x8000
+
+/**
+ * Memory base for video_audio_wrapper_video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_BASE_ADDR 0x55000000
+
+/**
+ * Memory size for video_audio_wrapper_video_sram in top matcha.
+ */
+#define TOP_MATCHA_VIDEO_SRAM_SIZE_BYTES 0x200000
+
+/**
+ * Memory base for ml_top_ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Memory size for ml_top_ram_ml_dmem in top matcha.
+ */
+#define TOP_MATCHA_RAM_ML_DMEM_SIZE_BYTES 0x400000
+
+
+/**
+ * Memory base address for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_BASE_ADDR 0x50000000
+
+/**
+ * Memory size for ram_smc in top matcha.
+ */
+#define TOP_MATCHA_RAM_SMC_SIZE_BYTES 0x400000
+
+
+/**
+ * Peripheral base address for uart0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART0_BASE_ADDR 0x40000000
+
+/**
+ * Peripheral size for uart0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART0_BASE_ADDR and
+ * `TOP_MATCHA_UART0_BASE_ADDR + TOP_MATCHA_UART0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART1_BASE_ADDR 0x40010000
+
+/**
+ * Peripheral size for uart1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART1_BASE_ADDR and
+ * `TOP_MATCHA_UART1_BASE_ADDR + TOP_MATCHA_UART1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART2_BASE_ADDR 0x40020000
+
+/**
+ * Peripheral size for uart2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART2_BASE_ADDR and
+ * `TOP_MATCHA_UART2_BASE_ADDR + TOP_MATCHA_UART2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for uart3 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_UART3_BASE_ADDR 0x40030000
+
+/**
+ * Peripheral size for uart3 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_UART3_BASE_ADDR and
+ * `TOP_MATCHA_UART3_BASE_ADDR + TOP_MATCHA_UART3_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_UART3_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for gpio in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_GPIO_BASE_ADDR 0x40040000
+
+/**
+ * Peripheral size for gpio in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_GPIO_BASE_ADDR and
+ * `TOP_MATCHA_GPIO_BASE_ADDR + TOP_MATCHA_GPIO_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_GPIO_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_device in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_DEVICE_BASE_ADDR 0x40050000
+
+/**
+ * Peripheral size for spi_device in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_DEVICE_BASE_ADDR and
+ * `TOP_MATCHA_SPI_DEVICE_BASE_ADDR + TOP_MATCHA_SPI_DEVICE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_DEVICE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for i2c0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C0_BASE_ADDR 0x40080000
+
+/**
+ * Peripheral size for i2c0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C0_BASE_ADDR and
+ * `TOP_MATCHA_I2C0_BASE_ADDR + TOP_MATCHA_I2C0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C1_BASE_ADDR 0x40090000
+
+/**
+ * Peripheral size for i2c1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C1_BASE_ADDR and
+ * `TOP_MATCHA_I2C1_BASE_ADDR + TOP_MATCHA_I2C1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for i2c2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2C2_BASE_ADDR 0x400A0000
+
+/**
+ * Peripheral size for i2c2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2C2_BASE_ADDR and
+ * `TOP_MATCHA_I2C2_BASE_ADDR + TOP_MATCHA_I2C2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2C2_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pattgen in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PATTGEN_BASE_ADDR 0x400E0000
+
+/**
+ * Peripheral size for pattgen in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PATTGEN_BASE_ADDR and
+ * `TOP_MATCHA_PATTGEN_BASE_ADDR + TOP_MATCHA_PATTGEN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PATTGEN_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_BASE_ADDR 0x40100000
+
+/**
+ * Peripheral size for rv_timer in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_BASE_ADDR + TOP_MATCHA_RV_TIMER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for core device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR 0x40130000
+
+/**
+ * Peripheral size for core device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_CORE_BASE_ADDR + TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_CORE_SIZE_BYTES 0x2000
+/**
+ * Peripheral base address for prim device on otp_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR 0x40132000
+
+/**
+ * Peripheral size for prim device on otp_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_OTP_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTP_CTRL_PRIM_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for lc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_LC_CTRL_BASE_ADDR 0x40140000
+
+/**
+ * Peripheral size for lc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_LC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_LC_CTRL_BASE_ADDR + TOP_MATCHA_LC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_LC_CTRL_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for alert_handler in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ALERT_HANDLER_BASE_ADDR 0x40150000
+
+/**
+ * Peripheral size for alert_handler in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ALERT_HANDLER_BASE_ADDR and
+ * `TOP_MATCHA_ALERT_HANDLER_BASE_ADDR + TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ALERT_HANDLER_SIZE_BYTES 0x800
+/**
+ * Peripheral base address for spi_host0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST0_BASE_ADDR 0x40300000
+
+/**
+ * Peripheral size for spi_host0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST0_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST0_BASE_ADDR + TOP_MATCHA_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for spi_host1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST1_BASE_ADDR 0x40310000
+
+/**
+ * Peripheral size for spi_host1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST1_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST1_BASE_ADDR + TOP_MATCHA_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST1_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for usbdev in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_USBDEV_BASE_ADDR 0x40320000
+
+/**
+ * Peripheral size for usbdev in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_USBDEV_BASE_ADDR and
+ * `TOP_MATCHA_USBDEV_BASE_ADDR + TOP_MATCHA_USBDEV_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_USBDEV_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for pwrmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWRMGR_AON_BASE_ADDR 0x40400000
+
+/**
+ * Peripheral size for pwrmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWRMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWRMGR_AON_BASE_ADDR + TOP_MATCHA_PWRMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWRMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rstmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RSTMGR_AON_BASE_ADDR 0x40410000
+
+/**
+ * Peripheral size for rstmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RSTMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_RSTMGR_AON_BASE_ADDR + TOP_MATCHA_RSTMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RSTMGR_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for clkmgr_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CLKMGR_AON_BASE_ADDR 0x40420000
+
+/**
+ * Peripheral size for clkmgr_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CLKMGR_AON_BASE_ADDR and
+ * `TOP_MATCHA_CLKMGR_AON_BASE_ADDR + TOP_MATCHA_CLKMGR_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CLKMGR_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for sysrst_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR 0x40430000
+
+/**
+ * Peripheral size for sysrst_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_SYSRST_CTRL_AON_BASE_ADDR + TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SYSRST_CTRL_AON_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for adc_ctrl_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR 0x40440000
+
+/**
+ * Peripheral size for adc_ctrl_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR and
+ * `TOP_MATCHA_ADC_CTRL_AON_BASE_ADDR + TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ADC_CTRL_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pwm_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PWM_AON_BASE_ADDR 0x40450000
+
+/**
+ * Peripheral size for pwm_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PWM_AON_BASE_ADDR and
+ * `TOP_MATCHA_PWM_AON_BASE_ADDR + TOP_MATCHA_PWM_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PWM_AON_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for pinmux_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_PINMUX_AON_BASE_ADDR 0x40460000
+
+/**
+ * Peripheral size for pinmux_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_PINMUX_AON_BASE_ADDR and
+ * `TOP_MATCHA_PINMUX_AON_BASE_ADDR + TOP_MATCHA_PINMUX_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_PINMUX_AON_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for aon_timer_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AON_TIMER_AON_BASE_ADDR 0x40470000
+
+/**
+ * Peripheral size for aon_timer_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AON_TIMER_AON_BASE_ADDR and
+ * `TOP_MATCHA_AON_TIMER_AON_BASE_ADDR + TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AON_TIMER_AON_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for ast in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_BASE_ADDR 0x40480000
+
+/**
+ * Peripheral size for ast in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_BASE_ADDR and
+ * `TOP_MATCHA_AST_BASE_ADDR + TOP_MATCHA_AST_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_SIZE_BYTES 0x400
+/**
+ * Peripheral base address for sensor_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SENSOR_CTRL_BASE_ADDR 0x40490000
+
+/**
+ * Peripheral size for sensor_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SENSOR_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SENSOR_CTRL_BASE_ADDR + TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SENSOR_CTRL_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for ast_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AST_AON_BASE_ADDR 0x404C0000
+
+/**
+ * Peripheral size for ast_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AST_AON_BASE_ADDR and
+ * `TOP_MATCHA_AST_AON_BASE_ADDR + TOP_MATCHA_AST_AON_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AST_AON_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_ret_aon in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for core device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
+
+/**
+ * Peripheral size for core device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_CORE_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_CORE_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for prim device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
+
+/**
+ * Peripheral size for prim device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_PRIM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for mem device on flash_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
+
+/**
+ * Peripheral size for mem device on flash_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR and
+ * `TOP_MATCHA_FLASH_CTRL_MEM_BASE_ADDR + TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
+/**
+ * Peripheral base address for regs device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_REGS_BASE_ADDR 0x6000
+
+/**
+ * Peripheral size for regs device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_REGS_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_REGS_BASE_ADDR + TOP_MATCHA_RV_DM_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_REGS_SIZE_BYTES 0x4
+/**
+ * Peripheral base address for mem device on rv_dm in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_DM_MEM_BASE_ADDR 0x4000
+
+/**
+ * Peripheral size for mem device on rv_dm in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_DM_MEM_BASE_ADDR and
+ * `TOP_MATCHA_RV_DM_MEM_BASE_ADDR + TOP_MATCHA_RV_DM_MEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_DM_MEM_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for rv_plic in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_BASE_ADDR 0x48000000
+
+/**
+ * Peripheral size for rv_plic in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for aes in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_AES_BASE_ADDR 0x41100000
+
+/**
+ * Peripheral size for aes in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_AES_BASE_ADDR and
+ * `TOP_MATCHA_AES_BASE_ADDR + TOP_MATCHA_AES_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_AES_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for hmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_HMAC_BASE_ADDR 0x41110000
+
+/**
+ * Peripheral size for hmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_HMAC_BASE_ADDR and
+ * `TOP_MATCHA_HMAC_BASE_ADDR + TOP_MATCHA_HMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_HMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for kmac in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KMAC_BASE_ADDR 0x41120000
+
+/**
+ * Peripheral size for kmac in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KMAC_BASE_ADDR and
+ * `TOP_MATCHA_KMAC_BASE_ADDR + TOP_MATCHA_KMAC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KMAC_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for otbn in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_OTBN_BASE_ADDR 0x41130000
+
+/**
+ * Peripheral size for otbn in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_OTBN_BASE_ADDR and
+ * `TOP_MATCHA_OTBN_BASE_ADDR + TOP_MATCHA_OTBN_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_OTBN_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for keymgr in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_KEYMGR_BASE_ADDR 0x41140000
+
+/**
+ * Peripheral size for keymgr in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_KEYMGR_BASE_ADDR and
+ * `TOP_MATCHA_KEYMGR_BASE_ADDR + TOP_MATCHA_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_KEYMGR_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for csrng in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CSRNG_BASE_ADDR 0x41150000
+
+/**
+ * Peripheral size for csrng in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CSRNG_BASE_ADDR and
+ * `TOP_MATCHA_CSRNG_BASE_ADDR + TOP_MATCHA_CSRNG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CSRNG_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for entropy_src in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ENTROPY_SRC_BASE_ADDR 0x41160000
+
+/**
+ * Peripheral size for entropy_src in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ENTROPY_SRC_BASE_ADDR and
+ * `TOP_MATCHA_ENTROPY_SRC_BASE_ADDR + TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ENTROPY_SRC_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for edn0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN0_BASE_ADDR 0x41170000
+
+/**
+ * Peripheral size for edn0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN0_BASE_ADDR and
+ * `TOP_MATCHA_EDN0_BASE_ADDR + TOP_MATCHA_EDN0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN0_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for edn1 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_EDN1_BASE_ADDR 0x41180000
+
+/**
+ * Peripheral size for edn1 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_EDN1_BASE_ADDR and
+ * `TOP_MATCHA_EDN1_BASE_ADDR + TOP_MATCHA_EDN1_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_EDN1_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for regs device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
+
+/**
+ * Peripheral size for regs device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x20
+/**
+ * Peripheral base address for ram device on sram_ctrl_main in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
+
+/**
+ * Peripheral size for ram device on sram_ctrl_main in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
+ * `TOP_MATCHA_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
+/**
+ * Peripheral base address for regs device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
+
+/**
+ * Peripheral size for regs device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_REGS_BASE_ADDR + TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_REGS_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for rom device on rom_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR 0x8000
+
+/**
+ * Peripheral size for rom device on rom_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR and
+ * `TOP_MATCHA_ROM_CTRL_ROM_BASE_ADDR + TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ROM_CTRL_ROM_SIZE_BYTES 0x8000
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR 0x411F0000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SEC_CFG_SIZE_BYTES 0x100
+/**
+ * Peripheral base address for dma0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA0_BASE_ADDR 0x40200000
+
+/**
+ * Peripheral size for dma0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA0_BASE_ADDR and
+ * `TOP_MATCHA_DMA0_BASE_ADDR + TOP_MATCHA_DMA0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for smc_uart in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_UART_BASE_ADDR 0x54000000
+
+/**
+ * Peripheral size for smc_uart in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_UART_BASE_ADDR and
+ * `TOP_MATCHA_SMC_UART_BASE_ADDR + TOP_MATCHA_SMC_UART_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_UART_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR 0x54010000
+
+/**
+ * Peripheral size for rv_timer_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for smc_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SMC_CTRL_BASE_ADDR 0x54020000
+
+/**
+ * Peripheral size for smc_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SMC_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_SMC_CTRL_BASE_ADDR + TOP_MATCHA_SMC_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SMC_CTRL_SIZE_BYTES 0x8
+/**
+ * Peripheral base address for cam_i2c in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_I2C_BASE_ADDR 0x54040000
+
+/**
+ * Peripheral size for cam_i2c in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_I2C_BASE_ADDR and
+ * `TOP_MATCHA_CAM_I2C_BASE_ADDR + TOP_MATCHA_CAM_I2C_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_I2C_SIZE_BYTES 0x80
+/**
+ * Peripheral base address for cam_ctrl in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_CAM_CTRL_BASE_ADDR 0x54050000
+
+/**
+ * Peripheral size for cam_ctrl in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_CAM_CTRL_BASE_ADDR and
+ * `TOP_MATCHA_CAM_CTRL_BASE_ADDR + TOP_MATCHA_CAM_CTRL_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_CAM_CTRL_SIZE_BYTES 0x10
+/**
+ * Peripheral base address for vca device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR 0x55400000
+
+/**
+ * Peripheral size for vca device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_VCA_SIZE_BYTES 0x400000
+/**
+ * Peripheral base address for isp device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR 0x54060000
+
+/**
+ * Peripheral size for isp device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for enc device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR 0x55200000
+
+/**
+ * Peripheral size for enc device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ENC_SIZE_BYTES 0x10000
+/**
+ * Peripheral base address for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR 0x55000000
+
+/**
+ * Peripheral size for stream_buf device on video_audio_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR and
+ * `TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_BASE_ADDR + TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VIDEO_AUDIO_WRAPPER_STREAM_BUF_SIZE_BYTES 0x200000
+/**
+ * Peripheral base address for vsi_ctl_wrapper in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR 0x55210000
+
+/**
+ * Peripheral size for vsi_ctl_wrapper in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR and
+ * `TOP_MATCHA_VSI_CTL_WRAPPER_BASE_ADDR + TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_VSI_CTL_WRAPPER_SIZE_BYTES 0x1000
+/**
+ * Peripheral base address for dma_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_DMA_SMC_BASE_ADDR 0x54070000
+
+/**
+ * Peripheral size for dma_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_DMA_SMC_BASE_ADDR and
+ * `TOP_MATCHA_DMA_SMC_BASE_ADDR + TOP_MATCHA_DMA_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_DMA_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_plic_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR 0x60000000
+
+/**
+ * Peripheral size for rv_plic_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR and
+ * `TOP_MATCHA_RV_PLIC_SMC_BASE_ADDR + TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_PLIC_SMC_SIZE_BYTES 0x8000000
+/**
+ * Peripheral base address for tlul_mailbox_sec in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR 0x40800000
+
+/**
+ * Peripheral size for tlul_mailbox_sec in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SEC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SEC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for tlul_mailbox_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR 0x540F1000
+
+/**
+ * Peripheral size for tlul_mailbox_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR and
+ * `TOP_MATCHA_TLUL_MAILBOX_SMC_BASE_ADDR + TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_TLUL_MAILBOX_SMC_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for core device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_CORE_BASE_ADDR 0x5C000000
+
+/**
+ * Peripheral size for core device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_CORE_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_CORE_BASE_ADDR + TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_CORE_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for dmem device on ml_top in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR 0x5A000000
+
+/**
+ * Peripheral size for dmem device on ml_top in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR and
+ * `TOP_MATCHA_ML_TOP_DMEM_BASE_ADDR + TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_ML_TOP_DMEM_SIZE_BYTES 0x400000
+/**
+ * Peripheral base address for spi_host2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_SPI_HOST2_BASE_ADDR 0x54090000
+
+/**
+ * Peripheral size for spi_host2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_SPI_HOST2_BASE_ADDR and
+ * `TOP_MATCHA_SPI_HOST2_BASE_ADDR + TOP_MATCHA_SPI_HOST2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_SPI_HOST2_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for rv_timer_smc2 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR 0x54011000
+
+/**
+ * Peripheral size for rv_timer_smc2 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR and
+ * `TOP_MATCHA_RV_TIMER_SMC2_BASE_ADDR + TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_TIMER_SMC2_SIZE_BYTES 0x200
+/**
+ * Peripheral base address for i2s0 in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_I2S0_BASE_ADDR 0x54100000
+
+/**
+ * Peripheral size for i2s0 in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_I2S0_BASE_ADDR and
+ * `TOP_MATCHA_I2S0_BASE_ADDR + TOP_MATCHA_I2S0_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_I2S0_SIZE_BYTES 0x40
+/**
+ * Peripheral base address for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR 0x54030000
+
+/**
+ * Peripheral size for cfg device on rv_core_ibex_smc in top matcha.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR and
+ * `TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_BASE_ADDR + TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES`.
+ */
+#define TOP_MATCHA_RV_CORE_IBEX_SMC_CFG_SIZE_BYTES 0x100
+
+/**
+ * MMIO Region
+ *
+ * MMIO region excludes any memory that is separate from the module
+ * configuration space, i.e. ROM, main SRAM, and flash are excluded but
+ * retention SRAM, spi_device memory, or usbdev memory are included.
+ */
+#define TOP_MATCHA_MMIO_BASE_ADDR 0x40000000
+#define TOP_MATCHA_MMIO_SIZE_BYTES 0x28000000
+
+#endif // __ASSEMBLER__
+
+#endif // MATCHA_HW_TOP_MATCHA_SW_AUTOGEN_TOP_MATCHA_MEMORY_H_
diff --git a/hw/top_matcha/sw/BUILD b/hw/top_matcha/sw/BUILD
index 36beb77..25e6f81 100644
--- a/hw/top_matcha/sw/BUILD
+++ b/hw/top_matcha/sw/BUILD
@@ -8,3 +8,16 @@
name = "all_files",
srcs = glob(["**"]),
)
+
+cc_library(
+ name = "top_matcha",
+ deps = select({
+ "//rules:sparrow_platform": [
+ "//hw/top_matcha/sparrow:top_matcha",
+ ],
+ "//conditions:default": [
+ "//hw/top_matcha/sw/autogen:top_matcha",
+ ],
+ }),
+)
+
diff --git a/platforms/riscv32/BUILD b/platforms/riscv32/BUILD
index 39cfec3..76bbdd9 100644
--- a/platforms/riscv32/BUILD
+++ b/platforms/riscv32/BUILD
@@ -7,3 +7,11 @@
"@platforms//os:none",
],
)
+
+platform(
+ name = "sparrow",
+ constraint_values = [
+ "@platforms//cpu:riscv32",
+ "@platforms//os:none",
+ ],
+)
diff --git a/rules/BUILD b/rules/BUILD
index a1e69a7..d21803e 100644
--- a/rules/BUILD
+++ b/rules/BUILD
@@ -3,6 +3,7 @@
# SPDX-License-Identifier: Apache-2.0
load("//rules:matcha.bzl", "OPENTITAN_PLATFORM")
+load("@bazel_skylib//lib:selects.bzl", "selects")
package(default_visibility = ["//visibility:public"])
@@ -10,3 +11,18 @@
name = "opentitan_platform",
values = {"platforms": OPENTITAN_PLATFORM},
)
+
+config_setting(
+ name = "sparrow_platform_internal",
+ values = {"platforms": "//platforms/riscv32:sparrow"},
+)
+
+config_setting(
+ name = "sparrow_platform_external",
+ values = {"platforms": "@matcha//platforms/riscv32:sparrow"},
+)
+
+selects.config_setting_group(
+ name = "sparrow_platform",
+ match_any = [":sparrow_platform_internal", ":sparrow_platform_external"],
+)
diff --git a/rules/matcha.bzl b/rules/matcha.bzl
index 9010841..1166ccb 100644
--- a/rules/matcha.bzl
+++ b/rules/matcha.bzl
@@ -16,7 +16,6 @@
"@lowrisc_opentitan//rules:opentitan.bzl",
"bin_to_vmem",
"opentitan_binary",
- "pick_correct_archive_for_device",
"scramble_flash_vmem",
"sign_bin",
)
@@ -119,6 +118,31 @@
},
)
+ArchiveInfo = provider(fields = ["archive_infos"])
+def _pick_correct_archive_for_device(ctx):
+ cc_infos = []
+ for dep in ctx.attr.deps:
+ if CcInfo in dep:
+ cc_info = dep[CcInfo]
+ elif ArchiveInfo in dep:
+ cc_info = dep[ArchiveInfo].archive_infos[ctx.attr.device]
+ else:
+ fail("Expected either a CcInfo or an ArchiveInfo")
+ cc_infos.append(cc_info)
+ return [cc_common.merge_cc_infos(cc_infos = cc_infos)]
+
+pick_correct_archive_for_device = rv_rule(
+ implementation = _pick_correct_archive_for_device,
+ attrs = {
+ "deps": attr.label_list(allow_files = True),
+ "device": attr.string(),
+ "platform": attr.string(),
+ },
+ fragments = ["cpp"],
+ toolchains = ["@rules_cc//cc:toolchain_type"],
+
+)
+
def opentitan_rom_binary(
name,
per_device_deps = device_deps("secure_core"),
@@ -272,8 +296,10 @@
dev_targets = []
depname = "{}_deps".format(devname)
+ _platform = "@matcha//platforms/riscv32:sparrow" if device == "asic" else platform
pick_correct_archive_for_device(
name = depname,
+ platform = _platform,
deps = deps + dev_deps,
device = device,
testonly = testonly,
@@ -359,7 +385,7 @@
platform = platform,
testonly = testonly,
)
- if device == "fpga_nexus" and var_name:
+ if (device == "fpga_nexus" or device == "asic") and var_name:
# Generate c header based on the bin file
bin_c_header = "{}_bin_c".format(devname)
dev_targets.append(":" + bin_c_header)
diff --git a/sw/device/examples/demo_hps_from_test_images/BUILD b/sw/device/examples/demo_hps_from_test_images/BUILD
index 04715b6..3dec3b8 100644
--- a/sw/device/examples/demo_hps_from_test_images/BUILD
+++ b/sw/device/examples/demo_hps_from_test_images/BUILD
@@ -5,6 +5,7 @@
load(
"//rules:matcha.bzl",
+ "ASIC_CORE_TARGETS",
"NEXUS_CORE_TARGETS",
"sec_flash_binary",
"smc_flash_binary",
@@ -28,8 +29,8 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -56,8 +57,8 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -84,8 +85,8 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -109,7 +110,6 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("smc")],
},
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/tests:test_lib_smc",
"@lowrisc_opentitan//sw/device/silicon_creator/lib:manifest_def",
],
@@ -128,10 +128,11 @@
],
per_device_deps = {
"fpga_nexus": [NEXUS_CORE_TARGETS.get("smc")],
+ "asic": [ASIC_CORE_TARGETS.get("smc")],
},
deps = [
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:ml_top",
"//sw/device/lib/dif:rv_plic_smc",
"//sw/device/tests:test_lib_smc",
@@ -155,7 +156,6 @@
},
deps = [
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:ml_top",
"//sw/device/lib/dif:rv_plic_smc",
"//sw/device/tests:test_lib_smc",
diff --git a/sw/device/examples/demo_isp/BUILD b/sw/device/examples/demo_isp/BUILD
index 73ed5c4..ce52fd9 100644
--- a/sw/device/examples/demo_isp/BUILD
+++ b/sw/device/examples/demo_isp/BUILD
@@ -28,7 +28,7 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -55,7 +55,7 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -82,7 +82,7 @@
"fpga_nexus": [NEXUS_CORE_TARGETS.get("secure_core")],
},
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
diff --git a/sw/device/examples/hello_world/BUILD b/sw/device/examples/hello_world/BUILD
index 23e5ae0..ea9de45 100644
--- a/sw/device/examples/hello_world/BUILD
+++ b/sw/device/examples/hello_world/BUILD
@@ -24,7 +24,6 @@
name = "hello_world_lib",
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:pinmux",
"//sw/device/lib/testing:pinmux_testutils",
"//sw/device/lib/testing/test_framework:ottf_start",
diff --git a/sw/device/examples/hello_world_multicore/BUILD b/sw/device/examples/hello_world_multicore/BUILD
index 1267682..9d68700 100644
--- a/sw/device/examples/hello_world_multicore/BUILD
+++ b/sw/device/examples/hello_world_multicore/BUILD
@@ -16,7 +16,7 @@
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:smc_ctrl",
"//sw/device/lib/testing/test_framework:ottf_start",
"//sw/device/lib/testing/test_framework:test_util",
@@ -81,7 +81,6 @@
var_name = "hello_world_multicore_smc_fpga_nexus_bin",
deps = [
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:ml_top",
"//sw/device/lib/testing/test_framework:ottf_start_smc",
"//sw/device/lib/testing/test_framework:test_util",
diff --git a/sw/device/lib/BUILD b/sw/device/lib/BUILD
index 20bd3ff..62fa121 100644
--- a/sw/device/lib/BUILD
+++ b/sw/device/lib/BUILD
@@ -51,7 +51,7 @@
deps = [
":eflash",
":tar_header",
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/arch:device",
"@lowrisc_opentitan//sw/device/lib/dif:spi_host",
"@lowrisc_opentitan//sw/device/lib/testing/test_framework:check",
@@ -68,7 +68,7 @@
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"@lowrisc_opentitan//sw/device/lib/dif:flash_ctrl",
"@lowrisc_opentitan//sw/device/lib/testing:flash_ctrl_testutils",
"@lowrisc_opentitan//sw/device/silicon_creator/lib/drivers:flash_ctrl",
@@ -86,7 +86,7 @@
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:rv_plic_smc",
"@lowrisc_opentitan//sw/device/lib/dif:i2c",
"@lowrisc_opentitan//sw/device/lib/testing/test_framework:check",
diff --git a/sw/device/lib/dif/BUILD b/sw/device/lib/dif/BUILD
index 3dab550..19a0f06 100644
--- a/sw/device/lib/dif/BUILD
+++ b/sw/device/lib/dif/BUILD
@@ -77,7 +77,7 @@
"dif_rv_plic.h",
],
deps = [
- "//hw/top_matcha:rv_plic_regs",
+ "//hw/top_matcha:rv_plic_regs_h",
"@lowrisc_opentitan//sw/device/lib/base:bitfield",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/base:memory",
@@ -98,7 +98,7 @@
"dif_rv_plic.h",
],
deps = [
- "//hw/top_matcha:rv_plic_smc_regs",
+ "//hw/top_matcha:rv_plic_smc_regs_h",
"@lowrisc_opentitan//sw/device/lib/base:bitfield",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/base:memory",
@@ -179,7 +179,7 @@
"@lowrisc_opentitan//sw/device/lib/dif:dif_pinmux.h",
],
deps = [
- "//hw/top_matcha/ip/pinmux/data/autogen:pinmux_regs",
+ "//hw/top_matcha:pinmux_regs",
"@lowrisc_opentitan//sw/device/lib/base:bitfield",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/base:memory",
@@ -216,7 +216,7 @@
],
hdrs = ["dif_clkmgr.h"],
deps = [
- "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr_regs",
+ "//hw/top_matcha:clkmgr_regs",
"@lowrisc_opentitan//sw/device/lib/base:bitfield",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/base:memory",
@@ -257,7 +257,7 @@
"@lowrisc_opentitan//sw/device/lib/dif:dif_alert_handler.h",
],
deps = [
- "//hw/top_matcha:alert_handler_regs",
+ "//hw/top_matcha:alert_handler_regs_h",
"@lowrisc_opentitan//sw/device/lib/base:bitfield",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/base:memory",
diff --git a/sw/device/lib/spi_to_host/BUILD b/sw/device/lib/spi_to_host/BUILD
index ef55243..7791704 100644
--- a/sw/device/lib/spi_to_host/BUILD
+++ b/sw/device/lib/spi_to_host/BUILD
@@ -5,7 +5,7 @@
srcs = ["spi_to_host.c"],
hdrs = ["spi_to_host.h"],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib:util",
"//sw/device/lib/dif:rv_plic_sec",
"@lowrisc_opentitan//sw/device/lib/dif:gpio",
diff --git a/sw/device/lib/testing/BUILD b/sw/device/lib/testing/BUILD
index 813a87d..5f8fd9f 100644
--- a/sw/device/lib/testing/BUILD
+++ b/sw/device/lib/testing/BUILD
@@ -12,7 +12,7 @@
hdrs = ["autogen/isr_testutils.h"],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"@lowrisc_opentitan//sw/device/lib/dif:adc_ctrl",
"@lowrisc_opentitan//sw/device/lib/dif:alert_handler",
"@lowrisc_opentitan//sw/device/lib/dif:aon_timer",
@@ -47,7 +47,7 @@
hdrs = ["pinmux_testutils.h"],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/arch:device",
"//sw/device/lib/dif:pinmux",
"@lowrisc_opentitan//sw/device/lib/dif:base",
@@ -88,7 +88,7 @@
hdrs = ["@lowrisc_opentitan//sw/device/lib/testing:i2c_testutils.h"],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:pinmux",
"@lowrisc_opentitan//hw/ip/i2c/data:i2c_regs",
"@lowrisc_opentitan//sw/device/lib/dif:i2c",
diff --git a/sw/device/lib/testing/pinmux_testutils.c b/sw/device/lib/testing/pinmux_testutils.c
index 087b62c..ed64c67 100644
--- a/sw/device/lib/testing/pinmux_testutils.c
+++ b/sw/device/lib/testing/pinmux_testutils.c
@@ -184,7 +184,41 @@
if (pinmux == NULL) {
return kDifBadArg;
}
- // Mux ISP wrapper
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData0,
+ kTopMatchaPinmuxInselIob0));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData1,
+ kTopMatchaPinmuxInselIob1));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData2,
+ kTopMatchaPinmuxInselIob2));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData3,
+ kTopMatchaPinmuxInselIob3));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData4,
+ kTopMatchaPinmuxInselIob4));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData5,
+ kTopMatchaPinmuxInselIob5));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData6,
+ kTopMatchaPinmuxInselIob6));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSData7,
+ kTopMatchaPinmuxInselIob7));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSVsync,
+ kTopMatchaPinmuxInselIob9));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVideoAudioWrapperSHsync,
+ kTopMatchaPinmuxInselIob8));
+ CHECK_DIF_OK(dif_pinmux_input_select(
+ pinmux, kTopMatchaPinmuxPeripheralInVsiCtlWrapperIspSclk,
+ kTopMatchaPinmuxInselIob10));
+#else
CHECK_DIF_OK(dif_pinmux_input_select(
pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSData0,
kTopMatchaPinmuxInselIob0));
@@ -218,6 +252,7 @@
CHECK_DIF_OK(dif_pinmux_input_select(
pinmux, kTopMatchaPinmuxPeripheralInIspWrapperSPclk,
kTopMatchaPinmuxInselIob8));
+#endif
CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopMatchaPinmuxMioOutIoa2,
kTopMatchaPinmuxOutselConstantHighZ));
diff --git a/sw/device/lib/testing/test_framework/BUILD b/sw/device/lib/testing/test_framework/BUILD
index 0f37ce6..6f9912e 100644
--- a/sw/device/lib/testing/test_framework/BUILD
+++ b/sw/device/lib/testing/test_framework/BUILD
@@ -46,7 +46,6 @@
target_compatible_with = [OPENTITAN_CPU],
deps = [
":linker_script",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:rv_plic_sec",
"@lowrisc_opentitan//sw/device/lib/base:csr",
"@lowrisc_opentitan//sw/device/lib/base:macros",
@@ -76,7 +75,7 @@
target_compatible_with = [OPENTITAN_CPU],
deps = [
":linker_script_smc",
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib/dif:rv_plic_smc",
"@lowrisc_opentitan//sw/device/lib/base:csr",
"@lowrisc_opentitan//sw/device/lib/base:macros",
@@ -116,7 +115,6 @@
deps = [
":freertos_port",
":ottf_start",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/arch:device",
"@lowrisc_opentitan//sw/device/lib/base:macros",
"@lowrisc_opentitan//sw/device/lib/dif:rv_core_ibex",
@@ -149,7 +147,7 @@
],
deps = [
":ottf_start",
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"@lowrisc_opentitan//sw/device/lib/dif:rv_timer",
"@lowrisc_opentitan//sw/device/lib/dif:uart",
"@lowrisc_opentitan//sw/device/lib/runtime:hart",
diff --git a/sw/device/lib/testing/test_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD
index 163c8aa..83f3c27 100644
--- a/sw/device/lib/testing/test_rom/BUILD
+++ b/sw/device/lib/testing/test_rom/BUILD
@@ -65,11 +65,11 @@
target_compatible_with = [OPENTITAN_CPU],
deps = [
":chip_info",
- "//hw/top_matcha/ip/ast/data:ast_regs",
- "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr_regs",
+ "//hw/top_matcha:ast_regs",
+ "//hw/top_matcha:clkmgr_regs",
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/flash_ctrl/data/autogen:flash_ctrl_regs",
"//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib:spi_flash",
"//sw/device/lib/dif:pinmux",
"//sw/device/lib/testing:pinmux_testutils",
@@ -144,11 +144,11 @@
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/ip/ast/data:ast_regs",
- "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr_regs",
- "//hw/top_matcha/ip/pinmux/data/autogen:pinmux_regs",
+ "//hw/top_matcha:ast_regs",
+ "//hw/top_matcha:clkmgr_regs",
+ "//hw/top_matcha:pinmux_regs",
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/sensor_ctrl/data:sensor_ctrl_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/testing/test_rom/puppeteer_utils",
"@lowrisc_opentitan//hw/ip/csrng/data:csrng_regs",
"@lowrisc_opentitan//hw/ip/edn/data:edn_regs",
diff --git a/sw/device/lib/testing/test_rom/puppeteer_utils/BUILD b/sw/device/lib/testing/test_rom/puppeteer_utils/BUILD
index 4436479..dd1397c 100644
--- a/sw/device/lib/testing/test_rom/puppeteer_utils/BUILD
+++ b/sw/device/lib/testing/test_rom/puppeteer_utils/BUILD
@@ -32,8 +32,8 @@
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/ip/pinmux/data/autogen:pinmux_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha:pinmux_regs",
+ "//hw/top_matcha/sw:top_matcha",
"//sw/device/lib:tar_header",
"@lowrisc_opentitan//hw/ip/hmac/data:hmac_regs",
"@lowrisc_opentitan//hw/ip/uart/data:uart_regs",
diff --git a/sw/device/silicon_creator/rom/BUILD b/sw/device/silicon_creator/rom/BUILD
index 690d41f..08c1a4b 100644
--- a/sw/device/silicon_creator/rom/BUILD
+++ b/sw/device/silicon_creator/rom/BUILD
@@ -6,7 +6,7 @@
package(default_visibility = ["//visibility:public"])
BOOTSTRAP_DEPS = [
- "//hw/top_matcha/sw/autogen:top_matcha",
+ "//hw/top_matcha/sw:top_matcha",
"//hw/top_matcha/ip/flash_ctrl/data/autogen:flash_ctrl_regs",
"@lowrisc_opentitan//hw/ip/gpio/data:gpio_regs",
"@lowrisc_opentitan//hw/ip/otp_ctrl/data:otp_ctrl_regs",
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index d249090..64f3b94 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -468,7 +468,6 @@
name = "test_lib_base",
target_compatible_with = [OPENTITAN_CPU],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/arch:device",
"//sw/device/lib/dif:pinmux",
"//sw/device/lib/testing:pinmux_testutils",
@@ -507,7 +506,6 @@
target_compatible_with = [OPENTITAN_CPU],
deps = [
":test_dv_lib_base",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/arch:device",
],
)
@@ -863,7 +861,7 @@
srcs = ["@lowrisc_opentitan//sw/device/tests:alert_handler_ping_timeout_test.c"],
deps = [
":test_dv_lib_opentitan",
- "//hw/top_matcha:alert_handler_regs",
+ "//hw/top_matcha:alert_handler_regs_h",
"//sw/device/lib/dif:alert_handler",
"//sw/device/lib/testing:alert_handler_testutils",
"@lowrisc_opentitan//sw/device/lib/base:math",
diff --git a/sw/device/tests/kelvin/fpga_tests/BUILD b/sw/device/tests/kelvin/fpga_tests/BUILD
index 612828e..10b4be8 100644
--- a/sw/device/tests/kelvin/fpga_tests/BUILD
+++ b/sw/device/tests/kelvin/fpga_tests/BUILD
@@ -21,7 +21,6 @@
},
deps = [
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib:spi_flash",
"//sw/device/lib/dif:rv_plic_sec",
"//sw/device/lib/dif:smc_ctrl",
@@ -44,7 +43,6 @@
},
deps = [
"//hw/top_matcha/ip/ml_top/data:ml_top_regs",
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/lib/dif:ml_top",
"//sw/device/lib/dif:rv_plic_smc",
"//sw/device/lib/dif:tlul_mailbox",
diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index 7e707b0..27b336c 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -388,7 +388,7 @@
name = "i2c_device_tx_rx_test",
srcs = ["i2c_device_tx_rx_test.c"],
deps = [
- "//hw/top_matcha/ip/clkmgr/data/autogen:clkmgr_regs",
+ "//hw/top_matcha:clkmgr_regs",
"//sw/device/lib/dif:pinmux",
"//sw/device/lib/dif:rv_plic_sec",
"//sw/device/lib/testing:i2c_testutils",
@@ -456,7 +456,7 @@
"-Wno-unused-variable",
],
deps = [
- "//hw/top_matcha:alert_handler_regs",
+ "//hw/top_matcha:alert_handler_regs_h",
"//sw/device/lib/arch:device",
"//sw/device/lib/dif:alert_handler",
"//sw/device/lib/dif:clkmgr",
diff --git a/sw/device/tests/smc/BUILD b/sw/device/tests/smc/BUILD
index a86fe8d..ec158be 100644
--- a/sw/device/tests/smc/BUILD
+++ b/sw/device/tests/smc/BUILD
@@ -332,7 +332,6 @@
"-ffreestanding",
],
deps = [
- "//hw/top_matcha/sw/autogen:top_matcha",
"//sw/device/tests:test_lib_smc",
"@lowrisc_opentitan//sw/device/silicon_creator/lib:manifest_def",
],
diff --git a/sw/device/tests/smc/smc_cam_irq_test.c b/sw/device/tests/smc/smc_cam_irq_test.c
index a86bbbd..347fd2a 100644
--- a/sw/device/tests/smc/smc_cam_irq_test.c
+++ b/sw/device/tests/smc/smc_cam_irq_test.c
@@ -81,8 +81,15 @@
// Check if the interrupted peripheral is UART.
top_matcha_plic_peripheral_smc_t peripheral_id =
top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
+ top_matcha_plic_peripheral_smc_t expected_isp_peripheral_id =
+#if defined(MATCHA_SPARROW)
+ kTopMatchaPlicPeripheralVideoAudioWrapper
+#else
+ kTopMatchaPlicPeripheralIspWrapper
+#endif
+ ;
CHECK(peripheral_id == kTopMatchaPlicPeripheralCamCtrl ||
- peripheral_id == kTopMatchaPlicPeripheralIspWrapper,
+ peripheral_id == expected_isp_peripheral_id,
"ISR interrupted peripheral is not CAM_CTRL or ISP_WRAPPER!");
switch (peripheral_id) {
case kTopMatchaPlicPeripheralCamCtrl:
@@ -113,10 +120,17 @@
// Set IRQ priorities to MAX
CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
plic, kTopMatchaPlicIrqIdCamCtrlCamMotionDetect, kDifRvPlicMaxPriority));
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kDifRvPlicMaxPriority));
+#else
CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
plic, kTopMatchaPlicIrqIdIspWrapperIsp, kDifRvPlicMaxPriority));
CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
plic, kTopMatchaPlicIrqIdIspWrapperMi, kDifRvPlicMaxPriority));
+#endif
// Set Ibex IRQ priority threshold level
CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
@@ -126,12 +140,21 @@
CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
plic, kTopMatchaPlicIrqIdCamCtrlCamMotionDetect,
kTopMatchaPlicTargetIbex0Smc, kDifToggleEnabled));
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kTopMatchaPlicTargetIbex0Smc,
+ kDifToggleEnabled));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kTopMatchaPlicTargetIbex0Smc,
+ kDifToggleEnabled));
+#else
CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
plic, kTopMatchaPlicIrqIdIspWrapperIsp, kTopMatchaPlicTargetIbex0Smc,
kDifToggleEnabled));
CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
plic, kTopMatchaPlicIrqIdIspWrapperMi, kTopMatchaPlicTargetIbex0Smc,
kDifToggleEnabled));
+#endif
}
static void execute_test() {
diff --git a/sw/device/tests/smc/smc_isp_wrapper_irq_test.c b/sw/device/tests/smc/smc_isp_wrapper_irq_test.c
index 05ea9a4..e3b56ac 100644
--- a/sw/device/tests/smc/smc_isp_wrapper_irq_test.c
+++ b/sw/device/tests/smc/smc_isp_wrapper_irq_test.c
@@ -54,7 +54,11 @@
// dif_isp_wrapper_irq_t isp_ctrl_irq = 0;
switch (interrupt_id) {
+#if defined(MATCHA_SPARROW)
+ case kTopMatchaPlicIrqIdVideoAudioWrapperIsp:
+#else
case kTopMatchaPlicIrqIdIspWrapperIsp:
+#endif
CHECK(!isp_wrapper_isp_handled,
"ISP_WRAPPER isp IRQ asserted more than once");
uint32_t isp_mis;
@@ -64,7 +68,11 @@
isp_wrapper_isp_handled = true;
LOG_INFO("ISP Wrapper isp interrupt occurred!");
break;
+#if defined(MATCHA_SPARROW)
+ case kTopMatchaPlicIrqIdVideoAudioWrapperMi:
+#else
case kTopMatchaPlicIrqIdIspWrapperMi:
+#endif
CHECK(!isp_wrapper_mi_handled,
"ISP_WRAPPER mi IRQ asserted more than once");
uint32_t mi_mis;
@@ -92,10 +100,21 @@
// Check if the interrupted peripheral is ISP WRAPPER.
top_matcha_plic_peripheral_smc_t peripheral_id =
top_matcha_plic_interrupt_for_peripheral_smc[interrupt_id];
- CHECK(peripheral_id == kTopMatchaPlicPeripheralIspWrapper,
+ top_matcha_plic_peripheral_smc_t expected_peripheral_id =
+#if defined(MATCHA_SPARROW)
+ kTopMatchaPlicPeripheralVideoAudioWrapper
+#else
+ kTopMatchaPlicPeripheralIspWrapper
+#endif
+ ;
+ CHECK(peripheral_id == expected_peripheral_id,
"ISR interrupted peripheral is ISP_WRAPPER!");
switch (peripheral_id) {
+#if defined(MATCHA_SPARROW)
+ case kTopMatchaPlicPeripheralVideoAudioWrapper:
+#else
case kTopMatchaPlicPeripheralIspWrapper:
+#endif
handle_isp_ctrl_isr(interrupt_id);
break;
default:
@@ -113,22 +132,38 @@
*/
static void plic_smc_configure_irqs(dif_rv_plic_t *plic) {
// Set IRQ priorities to MAX
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kDifRvPlicMaxPriority));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kDifRvPlicMaxPriority));
+#else
CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
plic, kTopMatchaPlicIrqIdIspWrapperIsp, kDifRvPlicMaxPriority));
CHECK_DIF_OK(dif_rv_plic_irq_set_priority(
plic, kTopMatchaPlicIrqIdIspWrapperMi, kDifRvPlicMaxPriority));
+#endif
// Set Ibex IRQ priority threshold level
CHECK_DIF_OK(dif_rv_plic_target_set_threshold(
plic, kTopMatchaPlicTargetIbex0Smc, kDifRvPlicMinPriority));
// Enable IRQs in PLIC
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperIsp, kTopMatchaPlicTargetIbex0Smc,
+ kDifToggleEnabled));
+ CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
+ plic, kTopMatchaPlicIrqIdVideoAudioWrapperMi, kTopMatchaPlicTargetIbex0Smc,
+ kDifToggleEnabled));
+#else
CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
plic, kTopMatchaPlicIrqIdIspWrapperIsp, kTopMatchaPlicTargetIbex0Smc,
kDifToggleEnabled));
CHECK_DIF_OK(dif_rv_plic_irq_set_enabled(
plic, kTopMatchaPlicIrqIdIspWrapperMi, kTopMatchaPlicTargetIbex0Smc,
kDifToggleEnabled));
+#endif
}
void _ottf_main(void) {
@@ -144,8 +179,13 @@
init_uart(TOP_MATCHA_SMC_UART_BASE_ADDR, &smc_uart);
}
LOG_INFO("Hello from the SMC!");
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_isp_wrapper_init(
+ mmio_region_from_addr(TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR), &isp_wrapper));
+#else
CHECK_DIF_OK(dif_isp_wrapper_init(
mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR), &isp_wrapper));
+#endif
CHECK_DIF_OK(dif_isp_wrapper_set_en(&isp_wrapper),
"isp_wrapper failed to be set in TPG mode");
diff --git a/sw/device/tests/smc/smc_isp_wrapper_test.c b/sw/device/tests/smc/smc_isp_wrapper_test.c
index 5a6eacc..be5d64f 100644
--- a/sw/device/tests/smc/smc_isp_wrapper_test.c
+++ b/sw/device/tests/smc/smc_isp_wrapper_test.c
@@ -44,10 +44,17 @@
LOG_INFO("Hello from the SMC!");
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_isp_wrapper_init(
+ mmio_region_from_addr(TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR),
+ &isp_wrapper),
+ "isp_wrapper failed to start");
+#else
CHECK_DIF_OK(dif_isp_wrapper_init(
mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR),
&isp_wrapper),
"isp_wrapper_start failed");
+#endif
CHECK_DIF_OK(dif_isp_wrapper_set_en(&isp_wrapper), "isp_wrapper_en failed");
diff --git a/sw/device/tests/smc/smc_isp_wrapper_tpg_128_64_test.c b/sw/device/tests/smc/smc_isp_wrapper_tpg_128_64_test.c
index 210a470..ca2cb90 100644
--- a/sw/device/tests/smc/smc_isp_wrapper_tpg_128_64_test.c
+++ b/sw/device/tests/smc/smc_isp_wrapper_tpg_128_64_test.c
@@ -51,10 +51,17 @@
LOG_INFO("Hello from the SMC!");
+#if defined(MATCHA_SPARROW)
+ CHECK_DIF_OK(dif_isp_wrapper_init(
+ mmio_region_from_addr(TOP_MATCHA_VIDEO_AUDIO_WRAPPER_ISP_BASE_ADDR),
+ &isp_wrapper),
+ "isp_wrapper failed to start");
+#else
CHECK_DIF_OK(dif_isp_wrapper_init(
mmio_region_from_addr(TOP_MATCHA_ISP_WRAPPER_BASE_ADDR),
&isp_wrapper),
"isp_wrapper failed to start");
+#endif
CHECK_DIF_OK(dif_isp_wrapper_set_en(&isp_wrapper),
"isp_wrapper failed to set to 128*64 TPG mode");
