)]}'
{
  "id": "f6b9e7c89b162f9d6ed4c073bcdd9de6382640be",
  "repo": "hw/kelvin",
  "revision": "f49212f10d46aa0f681c2ed407eeed8f33889274",
  "path": "hdl/verilog/ClockGate.v"
}