commit f44aac4eab2942d838cde47c38c1f20a33b59a0a
author Alex Van Damme <atv@google.com> Mon Jan 08 16:56:45 2024 -0800
committer Alex Van Damme <atv@google.com> Thu Jan 11 19:23:03 2024 +0000
tree 080f3ce6f270374695f638e55e1e0b48c0a5172c
parent 418c56048a122e802103577f5f4b5a491aa2b20b

Add mcycle CSR

Change-Id: I37b12c7d85f17aa264b5000be33fb01b50bf3996

hdl/chisel/src/kelvin/scalar/Csr.scala

diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala
index 6d5311e..346c9dc 100644
--- a/hdl/chisel/src/kelvin/scalar/Csr.scala
+++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -130,6 +130,9 @@
   val mepc      = RegInit(0.U(32.W))
 
   val mhartid   = RegInit(0.U(32.W))
+
+  val mcycle    = RegInit(0.U(64.W))
+
   // 32-bit MXLEN, I,M,X extensions
   val misa      = RegInit(0x40801100.U(32.W))
   // Kelvin-specific ISA register.
@@ -165,6 +168,10 @@
   val mcontext7En = index === 0x7C7.U
   val mpcEn       = index === 0x7E0.U
   val mspEn       = index === 0x7E1.U
+  // M-mode performance CSRs.
+  val mcycleEn    = index === 0xB00.U
+  val mcyclehEn   = index === 0xB80.U
+  // M-mode information CSRs.
   val mvendoridEn = index === 0xF11.U
   val marchidEn   = index === 0xF12.U
   val mimpidEn    = index === 0xF13.U
@@ -222,6 +229,8 @@
               MuxOR(mcontext7En,  mcontext7) |
               MuxOR(mpcEn,        mpc) |
               MuxOR(mspEn,        msp) |
+              MuxOR(mcycleEn,     mcycle(31,0)) |
+              MuxOR(mcyclehEn,    mcycle(63,32)) |
               MuxOR(mvendoridEn,  mvendorid) |
               MuxOR(marchidEn,    marchid) |
               MuxOR(mimpidEn,     mimpid) |
@@ -255,6 +264,16 @@
     when (mcontext7En)  { mcontext7 := wdata }
   }
 
+  // mcycle implementation
+  // If one of the enable signals for
+  // the register are true, overwrite the enabled half
+  // of the register.
+  // Increment the value of mcycle by 1.
+  val mcycle_th = Mux(mcyclehEn, wdata, mcycle(63,32))
+  val mcycle_tl = Mux(mcycleEn, wdata, mcycle(31,0))
+  val mcycle_t = Cat(mcycle_th, mcycle_tl)
+  mcycle := Mux(valid, mcycle_t, mcycle) + 1.U
+
   when (io.bru.in.mode.valid) {
     mode := io.bru.in.mode.bits
   }