| commit | ef7ec3f7a90866e1a0a656d464392207222f7378 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Wed Dec 04 11:13:36 2024 -0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Dec 04 11:13:36 2024 -0800 |
| tree | 4f3a5f1f91cc90a3cd95fa8f306dcb3eae23d730 | |
| parent | 423cd185a1c30257dc5b7e99d51e7d6375eb57bf [diff] |
Eliminate inferred latches in Dvu. Change-Id: Ic6c25806b11b76c64bc11b447dbdca3488ec9956
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog