| commit | eb1b2123883491d1dc9f6915628fe369c798e218 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Jul 01 14:29:46 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Tue Jul 01 14:29:46 2025 -0700 |
| tree | 0efafd7f599aea660ea4e47f9b0f276665b464b5 | |
| parent | 315f34e50df8544d75cb8f787bcd0da41f03f97c [diff] |
Increase the FPU pipeline register count for timing - Increase from two pipeline registers to three, to satisfy timing in the FPU. Change-Id: Iab5911e3caa48d1f02121282e5c8785ee7d78543
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog