diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index 8277e44..cdae970 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -178,26 +178,41 @@
 
 genrule(
     name = "matcha_kelvin_verilog",
-    srcs = [":Kelvin.v"],
-    outs = ["kelvin.v"],
+    srcs = [
+        ":Kelvin.v",
+        "//hdl/verilog:ClockGate.v",
+        "//hdl/verilog:Sram_1rw_256x256.v",
+        "//hdl/verilog:Sram_1rwm_256x288.v",
+    ],
+    outs = [
+        "kelvin.v",
+        "ClockGate.v",
+        "Sram_1rw_256x256.v",
+        "Sram_1rwm_256x288.v",
+    ],
+    # Prepend extra definition on Kelvin.v for DV. Collect other verilog files
+    # to the GenDir so they can be referenced by kelvin.core.
     cmd = """
-    echo "// Copyright 2023 Google LLC
-//
-// Licensed under the Apache License, Version 2.0 (the \\"License\\");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an \\"AS IS\\" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// SHA: $$(awk '/KELVIN_BUILD_GIT_VERSION/ { print $$2 }'\
-      bazel-out/volatile-status.txt)" > $@
-    cat $< >> $@
+    echo "\\`define STOP_COND 0
+\\`define PRINTF_COND 0
+" > $(location kelvin.v)
+    cat $(location Kelvin.v) >> $(location kelvin.v)
+    cp -f $(location //hdl/verilog:ClockGate.v) $(location ClockGate.v)
+    cp -f $(location //hdl/verilog:Sram_1rw_256x256.v) $(location Sram_1rw_256x256.v)
+    cp -f $(location //hdl/verilog:Sram_1rwm_256x288.v) $(location Sram_1rwm_256x288.v)
     """,
-    stamp = 1,  # this provides volatile-status.txt
+    visibility = ["//visibility:public"],
+)
+
+# Generate kelvin.core from this template so it can sit at the same GenDir as
+# the RTL files.
+genrule(
+    name = "kelvin_core",
+    srcs = [
+        "kelvin.core.in",
+        "matcha_kelvin_verilog",
+    ],
+    outs = ["kelvin.core"],
+    cmd = "cp -f $(location kelvin.core.in) $@",
+    visibility = ["//visibility:public"],
 )
diff --git a/hdl/chisel/kelvin.core.in b/hdl/chisel/kelvin.core.in
new file mode 100644
index 0000000..5aa27ae
--- /dev/null
+++ b/hdl/chisel/kelvin.core.in
@@ -0,0 +1,37 @@
+CAPI=2:
+# Copyright 2023 Google LLC
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "google:ip:kelvin:0.1"
+description: "Kelvin Core Level"
+filesets:
+  files_rtl:
+    files:
+      - kelvin.v
+      - ClockGate.v
+      - Sram_1rw_256x256.v
+      - Sram_1rwm_256x288.v
+    file_type: systemVerilogSource
+
+parameters:
+  SYNTHESIS:
+    datatype: bool
+    paramtype: vlogdefine
+
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl
+    toplevel: kelvin
+
+  lint:
+    <<: *default_target
+    default_tool: verilator
+    parameters:
+      - SYNTHESIS=true
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"
diff --git a/hdl/verilog/BUILD b/hdl/verilog/BUILD
index a1df259..802e2db 100644
--- a/hdl/verilog/BUILD
+++ b/hdl/verilog/BUILD
@@ -12,7 +12,16 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-load("@rules_hdl//verilog:providers.bzl", "VerilogInfo", "verilog_library")
+load("@rules_hdl//verilog:providers.bzl", "verilog_library")
+
+exports_files(
+    srcs = [
+        "ClockGate.v",
+        "Sram_1rw_256x256.v",
+        "Sram_1rwm_256x288.v",
+    ],
+    visibility = ["//visibility:public"],
+)
 
 verilog_library(
     name = "clock_gate",
diff --git a/hdl/verilog/ClockGate.v b/hdl/verilog/ClockGate.v
index 3993c52..f6b9e7c 100644
--- a/hdl/verilog/ClockGate.v
+++ b/hdl/verilog/ClockGate.v
@@ -17,24 +17,22 @@
   input         enable,  // '1' passthrough, '0' disable.
   output        clk_o
 );
-
-`ifndef CLOCKGATE_ENABLE
-
+// Note: Bypass clock gate for now. It causes FPGA build failures and
+// simulation issues
 assign clk_o = clk_i;
-
-`else
-
+/*
 reg clk_en;
+`ifdef FPGA
+    assign clk_o = clk_i;
+`else
+    // Capture 'enable' during low phase of the clock.
+    always @(clk_i or enable)
+    begin
+      if (~clk_i)
+      clk_en = enable;
+    end
 
-// Capture 'enable' during low phase of the clock.
-always_latch begin
-  if (~clk_i) begin
-    clk_en <= enable;
-  end
-end
-
-assign clk_o = clk_i & clk_en;
-
+  assign clk_o = clk_i & clk_en;
 `endif
-
+*/
 endmodule  // ClockGate
diff --git a/rules/chisel.bzl b/rules/chisel.bzl
index c31f0cf..b101108 100644
--- a/rules/chisel.bzl
+++ b/rules/chisel.bzl
@@ -12,9 +12,11 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+"""chisel build rules"""
+
 load("@io_bazel_rules_scala//scala:scala.bzl", "scala_binary", "scala_library")
-load("@rules_hdl//verilog:providers.bzl", "VerilogInfo", "verilog_library")
 load("@kelvin_hw//rules:verilator.bzl", "verilator_cc_library")
+load("@rules_hdl//verilog:providers.bzl", "verilog_library")
 
 def chisel_library(
         name,
diff --git a/rules/deps.bzl b/rules/deps.bzl
index e4e5404..917c021 100644
--- a/rules/deps.bzl
+++ b/rules/deps.bzl
@@ -12,16 +12,18 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
+"""Kelvin HW dependent repositories."""
+
 load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive")
 load(
-    "@io_bazel_rules_scala//scala:scala_maven_import_external.bzl",
-    "scala_maven_import_external",
-)
-load(
     "@io_bazel_rules_scala//scala:scala_cross_version.bzl",
     "default_maven_server_urls",
 )
 load(
+    "@io_bazel_rules_scala//scala:scala_maven_import_external.bzl",
+    "scala_maven_import_external",
+)
+load(
     "@rules_foreign_cc//foreign_cc:repositories.bzl",
     "rules_foreign_cc_dependencies",
 )
@@ -30,19 +32,8 @@
     rules_hdl_dependency_support = "dependency_support",
 )
 
-def kelvin_deps():
-    rules_foreign_cc_dependencies()
-    rules_hdl_dependency_support()
-
-    http_archive(
-        name = "accellera_systemc",
-        build_file = "@kelvin_hw//external:systemc.BUILD",
-        sha256 = "bfb309485a8ad35a08ee78827d1647a451ec5455767b25136e74522a6f41e0ea",
-        strip_prefix = "systemc-2.3.4",
-        urls = [
-            "https://github.com/accellera-official/systemc/archive/refs/tags/2.3.4.tar.gz",
-        ],
-    )
+def kelvin_chisel_deps():
+    """Dependent repositories to build chisel"""
 
     # paranamer
     scala_maven_import_external(
@@ -141,3 +132,22 @@
         server_urls = default_maven_server_urls(),
         licenses = ["notice"],
     )
+
+def kelvin_deps():
+    """Full kelvin dependent repositories
+
+    Including chisel and systemC test code
+    """
+    rules_foreign_cc_dependencies()
+    rules_hdl_dependency_support()
+    kelvin_chisel_deps()
+
+    http_archive(
+        name = "accellera_systemc",
+        build_file = "@kelvin_hw//external:systemc.BUILD",
+        sha256 = "bfb309485a8ad35a08ee78827d1647a451ec5455767b25136e74522a6f41e0ea",
+        strip_prefix = "systemc-2.3.4",
+        urls = [
+            "https://github.com/accellera-official/systemc/archive/refs/tags/2.3.4.tar.gz",
+        ],
+    )