diff --git a/hdl/chisel/src/chai/ChAI.scala b/hdl/chisel/src/chai/ChAI.scala
index 97ce896..cfd1ba6 100644
--- a/hdl/chisel/src/chai/ChAI.scala
+++ b/hdl/chisel/src/chai/ChAI.scala
@@ -70,6 +70,7 @@
   u_kelvin.ml_reset := 0.U
   u_kelvin.pc_start := 0.U
   u_kelvin.volt_sel := 0.U
+  u_kelvin.debug_req := 0.U
 
   io.finish := u_kelvin.finish
   io.fault := u_kelvin.fault
diff --git a/hdl/chisel/src/kelvin/Core.scala b/hdl/chisel/src/kelvin/Core.scala
index ee59964..100078c 100644
--- a/hdl/chisel/src/kelvin/Core.scala
+++ b/hdl/chisel/src/kelvin/Core.scala
@@ -30,6 +30,7 @@
     val csr = new CsrInOutIO(p)
     val halted = Output(Bool())
     val fault = Output(Bool())
+    val debug_req = Input(Bool())
 
     val ibus = new IBusIO(p)
     val dbus = new DBusIO(p)
diff --git a/hdl/chisel/src/kelvin/Parameters.scala b/hdl/chisel/src/kelvin/Parameters.scala
index 7c4b983..5b4b14e 100644
--- a/hdl/chisel/src/kelvin/Parameters.scala
+++ b/hdl/chisel/src/kelvin/Parameters.scala
@@ -31,7 +31,7 @@
 
 }
 
-case class Parameters(m: Seq[MemoryRegion] = Seq()) {
+case class Parameters(m: Seq[MemoryRegion] = Seq(), hartId: UInt = 0.U(32.W)) {
   case object Core {
     val tiny = 0
     val little = 1
diff --git a/hdl/chisel/src/kelvin/scalar/Csr.scala b/hdl/chisel/src/kelvin/scalar/Csr.scala
index 9536f11..b7c2315 100644
--- a/hdl/chisel/src/kelvin/scalar/Csr.scala
+++ b/hdl/chisel/src/kelvin/scalar/Csr.scala
@@ -139,7 +139,7 @@
   val mscratch  = RegInit(0.U(32.W))
   val mepc      = RegInit(0.U(32.W))
 
-  val mhartid   = RegInit(0.U(32.W))
+  val mhartid   = RegInit(p.hartId)
 
   val mcycle    = RegInit(0.U(64.W))
   val minstret  = RegInit(0.U(64.W))
diff --git a/hdl/chisel/src/matcha/BUILD b/hdl/chisel/src/matcha/BUILD
index eb4ab1b..ebbc792 100644
--- a/hdl/chisel/src/matcha/BUILD
+++ b/hdl/chisel/src/matcha/BUILD
@@ -22,6 +22,7 @@
         "Axi2Sram.scala",
         "Crossbar.scala",
         "Kelvin.scala",
+        "MatchaParameters.scala",
     ],
     deps = [
         "//hdl/chisel/src/common:common",
diff --git a/hdl/chisel/src/matcha/Kelvin.scala b/hdl/chisel/src/matcha/Kelvin.scala
index b8ed6cf..5fd07aa 100644
--- a/hdl/chisel/src/matcha/Kelvin.scala
+++ b/hdl/chisel/src/matcha/Kelvin.scala
@@ -49,6 +49,7 @@
   val ml_reset   = IO(Input(Bool()))
   val pc_start   = IO(Input(UInt(32.W)))
   val volt_sel   = IO(Input(Bool()))
+  val debug_req  = IO(Input(Bool()))
 
   val finish   = IO(Output(Bool()))
   val host_req = IO(Output(Bool()))
@@ -104,6 +105,10 @@
     slog   := core.io.slog
 
     // -------------------------------------------------------------------------
+    // Debug Request.
+    core.io.debug_req   := debug_req
+
+    // -------------------------------------------------------------------------
     // L1Cache.
     l1d.io.dbus     <> core.io.dbus
     l1d.io.flush    <> core.io.dflush
@@ -144,6 +149,6 @@
 }
 
 object EmitKelvin extends App {
-  val p = new kelvin.Parameters(Seq())
+  val p = new kelvin.MatchaParameters
   ChiselStage.emitSystemVerilogFile(new Kelvin(p), args)
 }
diff --git a/hdl/chisel/src/matcha/MatchaParameters.scala b/hdl/chisel/src/matcha/MatchaParameters.scala
new file mode 100644
index 0000000..7b5e6cf
--- /dev/null
+++ b/hdl/chisel/src/matcha/MatchaParameters.scala
@@ -0,0 +1,29 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package kelvin
+
+import chisel3._
+import chisel3.util._
+
+class MatchaParameters(m: Seq[MemoryRegion] = Seq(),
+        hartId: UInt = 2.U(32.W)) extends Parameters(m) {
+
+  // Debug
+  // tl_main_pkg::ADDR_SPACE_DBG + dm::HaltAddress
+  val dbgBase = 0x4000
+  val haltAddress = 0x800
+  val dmHaltAddress = dbgBase + haltAddress
+
+}
diff --git a/tests/verilator_sim/kelvin/core_tb.cc b/tests/verilator_sim/kelvin/core_tb.cc
index 9836dc6..969e361 100644
--- a/tests/verilator_sim/kelvin/core_tb.cc
+++ b/tests/verilator_sim/kelvin/core_tb.cc
@@ -45,6 +45,7 @@
 
   sc_signal<bool> io_halted;
   sc_signal<bool> io_fault;
+  sc_signal<bool> io_debug_req;
   sc_signal<bool> io_ibus_valid;
   sc_signal<bool> io_ibus_ready;
   sc_signal<bool> io_dbus_valid;
@@ -150,6 +151,7 @@
   core.reset(tb.reset);
   core.io_halted(io_halted);
   core.io_fault(io_fault);
+  core.io_debug_req(io_debug_req);
   core.io_ibus_valid(io_ibus_valid);
   core.io_ibus_ready(io_ibus_ready);
   core.io_dbus_valid(io_dbus_valid);
diff --git a/tests/verilator_sim/matcha/kelvin_tb.cc b/tests/verilator_sim/matcha/kelvin_tb.cc
index 5211117..5304184 100644
--- a/tests/verilator_sim/matcha/kelvin_tb.cc
+++ b/tests/verilator_sim/matcha/kelvin_tb.cc
@@ -42,6 +42,7 @@
   sc_signal<bool> clk_freeze;
   sc_signal<bool> ml_reset;
   sc_signal<bool> volt_sel;
+  sc_signal<bool> debug_req;
   sc_signal<bool> slog_valid;
   sc_signal<sc_bv<5> > slog_addr;
   sc_signal<sc_bv<32> > slog_data;
@@ -61,6 +62,7 @@
   clk_freeze = 0;
   pc_start = 0x00000000;
   volt_sel = 0;
+  debug_req = 0;
 
   tb.io_halted(finish);
   tb.io_fault(fault);
@@ -74,6 +76,7 @@
   core.finish(finish);
   core.fault(fault);
   core.host_req(host_req);
+  core.host_req(debug_req);
   core.slog_valid(slog_valid);
   core.slog_addr(slog_addr);
   core.slog_data(slog_data);