)]}'
{
  "commit": "97b73bfa8229815735763bc6335181a8c732ffc8",
  "tree": "aa7cb6cd0f202006f89216f53f26a0fe408738d9",
  "parents": [
    "088a57782dbdf57660439a9b53b6cdda89d2d2fb"
  ],
  "author": {
    "name": "zsp_hw_cd_dev",
    "email": "beck.zhang@verisilicon.com",
    "time": "Tue Aug 05 10:55:33 2025 -0700"
  },
  "committer": {
    "name": "Derek Chow",
    "email": "derekjchow@google.com",
    "time": "Wed Aug 06 13:05:23 2025 -0700"
  },
  "message": "Clean lint warning: W416b,W362,W486...\n\nChange-Id: Ie5350b57c334c856fee8815411ea03960649bfa5\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a8be9edb1eccb7f6c9cfa71b85f453a67befef79",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/common/multi_fifo.sv",
      "new_id": "16deccfa1552469f85c9f1e1be3eb03870f048da",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/common/multi_fifo.sv"
    },
    {
      "type": "modify",
      "old_id": "2d6aa0f55892a9b13669223d2901e501662da658",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_addsub.sv",
      "new_id": "cc35a7e3667350baea829ef59596ec5a52514e75",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_addsub.sv"
    },
    {
      "type": "modify",
      "old_id": "4251810a28bb5c729d6dc4a0da97bb1731d58367",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_execution_p1.sv",
      "new_id": "dbc75bcb3c3b2eca3ad2d1a11b45832ddef3d15c",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_execution_p1.sv"
    },
    {
      "type": "modify",
      "old_id": "a6d88fbbb42f163b21b88c0f4686fd251d77676c",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_mask.sv",
      "new_id": "256d6e3cc8481b8c5a7586c77176c2db47834c97",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_mask.sv"
    },
    {
      "type": "modify",
      "old_id": "30a987683990f117c745377267ba9001fe7ecc45",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_mask_viota.sv",
      "new_id": "3d3b5cd2bc868c4fd4dd0abe04801b9f6105471b",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_mask_viota.sv"
    },
    {
      "type": "modify",
      "old_id": "a9fd507f20ee252c40d5daf413235373687bc9c8",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_other.sv",
      "new_id": "b9d5498cfef4d1191bd2ea6a7b9e013043a0a956",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_other.sv"
    },
    {
      "type": "modify",
      "old_id": "ed55d3e9aaadffdb0fd840f3b01ca6203f09eebc",
      "old_mode": 33261,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_shift.sv",
      "new_id": "b84b5645ba44bc92352d5a1b989d7210c7a18902",
      "new_mode": 33261,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_alu_unit_shift.sv"
    },
    {
      "type": "modify",
      "old_id": "ee86f5f309803747db4a0ca2a126c51258ce8f48",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_decode_unit_ari.sv",
      "new_id": "61b3e2c8695c5d0c4baa58643109a563223ddd38",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_decode_unit_ari.sv"
    },
    {
      "type": "modify",
      "old_id": "e4af58f5f0694f10602f7f174cf9c83d70e922bf",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_decode_unit_lsu.sv",
      "new_id": "a940fe2a91a48f90dd44337854891b4257680621",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_decode_unit_lsu.sv"
    },
    {
      "type": "modify",
      "old_id": "ed76dc54ff2505680863627bb82257e60a3c5933",
      "old_mode": 33261,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_dispatch.sv",
      "new_id": "e7ef0538e49edf98db94d2e7b037003876b4f70b",
      "new_mode": 33261,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_dispatch.sv"
    },
    {
      "type": "modify",
      "old_id": "770243a205477b621750fef363d5637c1afc936d",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_dispatch_opr_byte_type.sv",
      "new_id": "2db3a49cc2646c73533fa949c8d7eb95ad2fb88e",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_dispatch_opr_byte_type.sv"
    },
    {
      "type": "modify",
      "old_id": "77a66bd0ee475b3ccd3850b0d5bec441430fa3b0",
      "old_mode": 33261,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_div_unit.sv",
      "new_id": "d60697ede2bdf1f5793ebbbbe16ade26582ce966",
      "new_mode": 33261,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_div_unit.sv"
    },
    {
      "type": "modify",
      "old_id": "a25a32ac85e62303f9696a7073cc5566b7abb9bc",
      "old_mode": 33261,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_div_unit_divider.sv",
      "new_id": "336febafca6cc97c79b522fd876d9f143ce87b0b",
      "new_mode": 33261,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_div_unit_divider.sv"
    },
    {
      "type": "modify",
      "old_id": "d3561711acb7ff0a854f2db1c1dbfb4529e6fc11",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_mac_unit.sv",
      "new_id": "6ae4f741ff0348275d052a1563c8fc1fae7ad0c4",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_mac_unit.sv"
    },
    {
      "type": "modify",
      "old_id": "c291c852333779d17aff39bd67fe3c8607337812",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_mul_unit_mul8.sv",
      "new_id": "360cfce93bb7df4e847218fd9b2f25c483a5bc9f",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_mul_unit_mul8.sv"
    },
    {
      "type": "modify",
      "old_id": "862e4693408dc114dc8c73795c807de6d5799e9e",
      "old_mode": 33188,
      "old_path": "hdl/verilog/rvv/design/rvv_backend_pmtrdt_unit.sv",
      "new_id": "09417e441b2af44077a4fd008f570264066c455d",
      "new_mode": 33188,
      "new_path": "hdl/verilog/rvv/design/rvv_backend_pmtrdt_unit.sv"
    }
  ]
}
