third_party/ip/lowrisc/0002-Modify-TLUL-and-SRAM-adapter-for-ChAI.patch

From 617fc52a30d18725e50080e64bc6459fa24ca709 Mon Sep 17 00:00:00 2001
From: Alex Van Damme <atv@google.com>
Date: Thu, 15 Feb 2024 11:24:49 -0800
Subject: [PATCH 2/3] Modify TLUL and SRAM adapter for ChAI

---
 hw/ip/tlul/rtl/tlul_adapter_reg.sv  | 12 +++++-------
 hw/ip/tlul/rtl/tlul_adapter_sram.sv | 21 +++------------------
 hw/ip/tlul/rtl/tlul_err.sv          | 15 ++++++++++-----
 hw/ip/tlul/rtl/tlul_pkg.sv          | 18 ------------------
 4 files changed, 18 insertions(+), 48 deletions(-)

diff --git a/hw/ip/tlul/rtl/tlul_adapter_reg.sv b/hw/ip/tlul/rtl/tlul_adapter_reg.sv
index ac48750129..85e89d63f4 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_reg.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_reg.sv
@@ -82,8 +82,8 @@ module tlul_adapter_reg
 
   assign we_o    = wr_req & ~err_internal;
   assign re_o    = rd_req & ~err_internal;
-  assign wdata_o = tl_i.a_data;
-  assign be_o    = tl_i.a_mask;
+  assign wdata_o = tl_i.a_data[RegDw-1:0];
+  assign be_o    = tl_i.a_mask[RegBw-1:0];
 
   if (RegAw <= 2) begin : gen_only_one_reg
     assign addr_o  = '0;
@@ -161,7 +161,7 @@ module tlul_adapter_reg
     d_size:   reqsz_q,
     d_source: reqid_q,
     d_sink:   '0,
-    d_data:   rdata,
+    d_data:   {224'b0, rdata},
     d_user:   '0,
     d_error:  error
   };
@@ -201,14 +201,12 @@ module tlul_adapter_reg
 
   // An instruction type transaction is only valid if en_ifetch is enabled
   // If the instruction type is completely invalid, also considered an instruction error
-  assign instr_error = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type) |
-                       (prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
-                        prim_mubi_pkg::mubi4_test_false_loose(en_ifetch_i));
+  assign instr_error = '0;
 
   assign err_internal = addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error;
 
   // Don't allow unsupported values.
-  assign malformed_meta_err = tl_a_user_chk(tl_i.a_user);
+  assign malformed_meta_err = '0;
 
   // addr_align_err
   //    Raised if addr isn't aligned with the size
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index ec764cbefa..8f41f38581 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
@@ -106,7 +106,7 @@ module tlul_adapter_sram
   //    Here it checks any partial write if ByteAccess isn't allowed.
   assign wr_attr_error = (tl_i.a_opcode == PutFullData || tl_i.a_opcode == PutPartialData)
                          ? ((ByteAccess == 0) ?
-                           (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0)
+                           (tl_i.a_mask != '1 || tl_i.a_size != 6'h2) : 1'b0)
                            : 1'b0;
 
   // An instruction type transaction is only valid if en_ifetch is enabled
@@ -268,24 +268,9 @@ module tlul_adapter_sram
                                  DataWhenInstrError :
                                  DataWhenError;
 
-  // Since DataWhenInstrError and DataWhenError can be arbitrary parameters
-  // we statically calculate the correct integrity values for these parameters here so that
-  // they do not have to be supplied externally.
-  logic [top_pkg::TL_DW-1:0] unused_instr, unused_data;
-  logic [DataIntgWidth-1:0] error_instr_integ, error_data_integ;
-  tlul_data_integ_enc u_tlul_data_integ_enc_instr (
-    .data_i(DataMaxWidth'(DataWhenInstrError)),
-    .data_intg_o({error_instr_integ, unused_instr})
-  );
-  tlul_data_integ_enc u_tlul_data_integ_enc_data (
-    .data_i(DataMaxWidth'(DataWhenError)),
-    .data_intg_o({error_data_integ, unused_data})
-  );
 
   logic [DataIntgWidth-1:0] error_blanking_integ;
-  assign error_blanking_integ = (prim_mubi_pkg::mubi4_test_true_strict(reqfifo_rdata.instr_type)) ?
-                                 error_instr_integ :
-                                 error_data_integ;
+  assign error_blanking_integ = '0;
 
   logic [top_pkg::TL_DW-1:0] d_data;
   assign d_data = (vld_rd_rsp & ~d_error) ? rspfifo_rdata.data   // valid read
@@ -445,7 +430,7 @@ module tlul_adapter_sram
     error     : rerror_i[1] // Only care for Uncorrectable error
   };
   assign rspfifo_rready = (reqfifo_rdata.op == OpRead & ~reqfifo_rdata.error)
-                        ? reqfifo_rready : 1'b0 ;
+                        ? reqfifo_rready : 1'b1 ;
 
   // This module only cares about uncorrectable errors.
   logic unused_rerror;
diff --git a/hw/ip/tlul/rtl/tlul_err.sv b/hw/ip/tlul/rtl/tlul_err.sv
index c887cc387b..6cb3ea380a 100644
--- a/hw/ip/tlul/rtl/tlul_err.sv
+++ b/hw/ip/tlul/rtl/tlul_err.sv
@@ -29,11 +29,10 @@ module tlul_err import tlul_pkg::*; (
 
   // An instruction type transaction cannot be write
   logic instr_wr_err;
-  assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
-                        (op_full | op_partial);
+  assign instr_wr_err = '0;
 
   logic instr_type_err;
-  assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type);
+  assign instr_type_err = '0;
 
   // Anything that doesn't fall into the permitted category, it raises an error
   assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err;
@@ -68,8 +67,8 @@ module tlul_err import tlul_pkg::*; (
         'h1: begin // 2 Byte
           addr_sz_chk  = ~tl_i.a_address[0];
           // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
-          mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
-                       : ~|(tl_i.a_mask & 4'b1100);
+          mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 32'b0011)
+                       : ~|(tl_i.a_mask & 32'b1100);
           fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
         end
 
@@ -79,6 +78,12 @@ module tlul_err import tlul_pkg::*; (
           fulldata_chk = &tl_i.a_mask[3:0];
         end
 
+        'h5: begin  // 32 Byte
+          addr_sz_chk  = 1'b1;
+          mask_chk     = 1'b1;
+          fulldata_chk = 1'b1;
+        end
+
         default: begin // else
           addr_sz_chk  = 1'b0;
           mask_chk     = 1'b0;
diff --git a/hw/ip/tlul/rtl/tlul_pkg.sv b/hw/ip/tlul/rtl/tlul_pkg.sv
index 4e9401fdf9..dae9671f25 100644
--- a/hw/ip/tlul/rtl/tlul_pkg.sv
+++ b/hw/ip/tlul/rtl/tlul_pkg.sv
@@ -179,17 +179,6 @@ package tlul_pkg;
    return cmd_intg;
   endfunction  // get_cmd_intg
 
-  // calculate ecc for data checking
-  function automatic logic [DataIntgWidth-1:0] get_data_intg(logic [top_pkg::TL_DW-1:0] data);
-    logic [DataIntgWidth-1:0] data_intg;
-    logic [top_pkg::TL_DW-1:0] unused_data;
-    logic [DataIntgWidth + top_pkg::TL_DW - 1 : 0] enc_data;
-    enc_data = prim_secded_pkg::prim_secded_inv_39_32_enc(data);
-    data_intg = enc_data[DataIntgWidth + top_pkg::TL_DW - 1 : top_pkg::TL_DW];
-    unused_data = enc_data[top_pkg::TL_DW - 1 : 0];
-    return data_intg;
-  endfunction  // get_data_intg
-
   // return inverted integrity for command payload
   function automatic logic [H2DCmdIntgWidth-1:0] get_bad_cmd_intg(tl_h2d_t tl);
     logic [H2DCmdIntgWidth-1:0] cmd_intg;
@@ -197,11 +186,4 @@ package tlul_pkg;
     return ~cmd_intg;
   endfunction // get_bad_cmd_intg
 
-  // return inverted integrity for data payload
-  function automatic logic [H2DCmdIntgWidth-1:0] get_bad_data_intg(logic [top_pkg::TL_DW-1:0] data);
-    logic [H2DCmdIntgWidth-1:0] data_intg;
-    data_intg = get_data_intg(data);
-    return ~data_intg;
-  endfunction // get_bad_data_intg
-
 endpackage
-- 
2.43.0.687.g38aa6559b0-goog