| commit | bece15cfba8c5b715897220fbfed04b5b7d576bc | [log] [tgz] |
|---|---|---|
| author | Zhidong Liang <Zhidong.Liang@verisilicon.com> | Tue Nov 19 14:34:18 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | 15d575db106359f728fbb4613c55a78c2513c9e0 | |
| parent | 6d388fe2cc90dd110c1b57050c1a6905196f4df5 [diff] |
add rvv_vrf_reg module Change-Id: Ice93289e867e31fe0b08c34b2573eef87435d9f4
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog