diff --git a/hdl/chisel/src/common/FifoX.scala b/hdl/chisel/src/common/FifoX.scala
index ee3f041..7e6a925 100644
--- a/hdl/chisel/src/common/FifoX.scala
+++ b/hdl/chisel/src/common/FifoX.scala
@@ -131,7 +131,6 @@
   when (mcount > 0.U) {
     mslice.io.in.bits := mem(outpos)
   } .elsewhen (ivalid) {
-    assert(PopCount(iactive) >= 1.U)
     when (iactive =/= 0.U) {
       val idx = PriorityEncoder(iactive)
       mslice.io.in.bits := io.in.bits(idx).bits