| commit | 907eafd7c2e01cba545c1bd67575b60143c18b09 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Tue Apr 02 21:38:49 2024 +0000 |
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | Tue Apr 02 21:38:49 2024 +0000 |
| tree | 6758ac192c478b9b6600589cc6c1af30ea4f18fb | |
| parent | 73f9f6974ac428c65a947d667a8b0d336599d30a [diff] | |
| parent | 8477fa8bef38dff634146c1d33ab4a036ef1003a [diff] |
Merge "Disable assert in FifoX."
diff --git a/hdl/chisel/src/common/FifoX.scala b/hdl/chisel/src/common/FifoX.scala index ee3f041..7e6a925 100644 --- a/hdl/chisel/src/common/FifoX.scala +++ b/hdl/chisel/src/common/FifoX.scala
@@ -131,7 +131,6 @@ when (mcount > 0.U) { mslice.io.in.bits := mem(outpos) } .elsewhen (ivalid) { - assert(PopCount(iactive) >= 1.U) when (iactive =/= 0.U) { val idx = PriorityEncoder(iactive) mslice.io.in.bits := io.in.bits(idx).bits