CAPI=2:
name: "com.google.kelvin:fpga:kelvin_soc:0.2"
description: "The Kelvin SoC for FPGA."

filesets:
  rtl:
    depend:
      - kelvinv2:ip:xbar_kelvin_soc_chisel:0.1
      - com.google.kelvin:fpga:kelvin_soc_pkg:0.1
      - com.google.kelvin:fpga:racl_pkg:0.1
      - lowrisc:ip:uart:0.1
      - lowrisc:prim:rom_adv
      - lowrisc:prim_generic:rom
      - lowrisc:tlul:adapter_sram
      - lowrisc:ip:spi_device:0.1
      - lowrisc:kelvin_ip:rv_core_ibex:0.1
      - google:kelvin:rvv_core_mini_tlul
      - lowrisc:ibex:ibex_tracer
      - kelvinv2:ip:sram:0.1
      - kelvinv2:ip:kelvin_tlul:0.1
    files:
      - rtl/kelvin_soc.sv
    file_type: systemVerilogSource

  sim_src:
    depend:
      - lowrisc:dv_verilator:memutil_verilator
      - lowrisc:dv_verilator:simutil_verilator
    files:
      - main.cc
    file_type: cppSource

mapping:
  "lowrisc:virtual_constants:top_racl_pkg": "com.google.kelvin:fpga:racl_pkg:0.1"

parameters:
  ClockFrequencyMhz:
    datatype: int
    description: "Target clock frequency in MHz."
    default: 10
    paramtype: vlogparam
  MemInitFile:
    datatype: str
    description: Path to ROM
    default: "fpga/wfi.bin"
    paramtype: vlogparam
  USE_GENERIC:
    datatype: bool
    description: "Use generic primitives"
    default: false
    paramtype: vlogdefine
  FPGA_XILINX:
    datatype: bool
    description: "Use Xilinx FPGA primitives"
    default: false
    paramtype: vlogdefine

targets:
  default: &default
    filesets:
      - rtl

  sim:
    <<: *default
    filesets:
      - rtl
      - sim_src
    default_tool: verilator
    description: "Simulation target for the Kelvin SoC"
    parameters:
      - MemInitFile
    tools:
      verilator:
        mode: cc
        verilator_options:
          - '--trace'
          - '--trace-fst'
          - '-CFLAGS "-DTOPLEVEL_NAME=kelvin_soc -std=c++17 -Wall -DVM_TRACE_FMT_FST"'
          - '-LDFLAGS "-lelf"'
          - '-Wall'
          - '--threads 16'
          - '-Wno-fatal'

  synth:
    <<: *default
    default_tool: vivado
    filesets:
      - rtl
    parameters:
      - MemInitFile
      - USE_GENERIC=true
      - FPGA_XILINX=true
    tools:
      vivado:
        part: "xcvu13p-fhga2104-2-e"
        STEPS.SYNTH_DESIGN.TCL.PRE:
          - vivado_pre_synth.tcl