From 37adcc443c2d7879079ca6e634f2992dbc9bfac8 Mon Sep 17 00:00:00 2001
From: Alex Van Damme <atv@google.com>
Date: Wed, 14 Feb 2024 15:29:54 -0800
Subject: [PATCH 3/3] Modify UART for ChAI

---
 hw/ip/uart/rtl/uart_reg_pkg.sv | 28 ++++++++++++++--------------
 hw/ip/uart/rtl/uart_reg_top.sv |  7 ++-----
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/hw/ip/uart/rtl/uart_reg_pkg.sv b/hw/ip/uart/rtl/uart_reg_pkg.sv
index 355afaff1b..8a44cd5af8 100644
--- a/hw/ip/uart/rtl/uart_reg_pkg.sv
+++ b/hw/ip/uart/rtl/uart_reg_pkg.sv
@@ -10,7 +10,7 @@ package uart_reg_pkg;
   parameter int NumAlerts = 1;
 
   // Address widths within the block
-  parameter int BlockAw = 6;
+  parameter int BlockAw = 9;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -324,19 +324,19 @@ package uart_reg_pkg;
   } uart_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] UART_INTR_STATE_OFFSET = 6'h 0;
-  parameter logic [BlockAw-1:0] UART_INTR_ENABLE_OFFSET = 6'h 4;
-  parameter logic [BlockAw-1:0] UART_INTR_TEST_OFFSET = 6'h 8;
-  parameter logic [BlockAw-1:0] UART_ALERT_TEST_OFFSET = 6'h c;
-  parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 6'h 10;
-  parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 6'h 14;
-  parameter logic [BlockAw-1:0] UART_RDATA_OFFSET = 6'h 18;
-  parameter logic [BlockAw-1:0] UART_WDATA_OFFSET = 6'h 1c;
-  parameter logic [BlockAw-1:0] UART_FIFO_CTRL_OFFSET = 6'h 20;
-  parameter logic [BlockAw-1:0] UART_FIFO_STATUS_OFFSET = 6'h 24;
-  parameter logic [BlockAw-1:0] UART_OVRD_OFFSET = 6'h 28;
-  parameter logic [BlockAw-1:0] UART_VAL_OFFSET = 6'h 2c;
-  parameter logic [BlockAw-1:0] UART_TIMEOUT_CTRL_OFFSET = 6'h 30;
+  parameter logic [BlockAw-1:0] UART_INTR_STATE_OFFSET = 9'h 0;
+  parameter logic [BlockAw-1:0] UART_INTR_ENABLE_OFFSET = 9'h 20;
+  parameter logic [BlockAw-1:0] UART_INTR_TEST_OFFSET = 9'h 40;
+  parameter logic [BlockAw-1:0] UART_ALERT_TEST_OFFSET = 9'h 60;
+  parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 9'h 80;
+  parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 9'h a0;
+  parameter logic [BlockAw-1:0] UART_RDATA_OFFSET = 9'h c0;
+  parameter logic [BlockAw-1:0] UART_WDATA_OFFSET = 9'h e0;
+  parameter logic [BlockAw-1:0] UART_FIFO_CTRL_OFFSET = 9'h 100;
+  parameter logic [BlockAw-1:0] UART_FIFO_STATUS_OFFSET = 9'h120 ;
+  parameter logic [BlockAw-1:0] UART_OVRD_OFFSET = 9'h 140;
+  parameter logic [BlockAw-1:0] UART_VAL_OFFSET = 9'h 160;
+  parameter logic [BlockAw-1:0] UART_TIMEOUT_CTRL_OFFSET = 9'h180;
 
   // Reset values for hwext registers and their fields
   parameter logic [7:0] UART_INTR_TEST_RESVAL = 8'h 0;
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 6b6952f5d8..b105550cc4 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv
@@ -24,7 +24,7 @@ module uart_reg_top (
 
   import uart_reg_pkg::* ;
 
-  localparam int AW = 6;
+  localparam int AW = 9;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width
 
@@ -48,10 +48,7 @@ module uart_reg_top (
 
   // incoming payload check
   logic intg_err;
-  tlul_cmd_intg_chk u_chk (
-    .tl_i(tl_i),
-    .err_o(intg_err)
-  );
+  assign intg_err = '0;
 
   // also check for spurious write enables
   logic reg_we_err;
-- 
2.43.0.687.g38aa6559b0-goog