tree 114e4c42a1fe8dbdfc879d3c3ae917052527877c
parent 7759a66faa0121563684b83fabb179db5f0ca410
author Alex Van Damme <atv@google.com> 1758151006 -0700
committer Alex Van Damme <atv@google.com> 1758216634 -0700

feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit

This change increases the maximum bulk transfer size of the Spi2TLUL module from 256 bytes to 65536 bytes by widening the length registers from 8 to 16 bits.

The key changes include:
- Updated the Spi2TLUL Chisel module to use 16-bit length registers for both bulk and regular TileLink transfers.
- Modified the SPI command state machine to handle two-byte length transactions.
- Re-implemented the internal data buffers using SyncReadMem to support larger, configurable depths, and increased the buffer size to 4KB.
- Introduced pipelining for SRAM reads to improve performance with larger data transfers.
- Updated the Python SPI master utility and cocotb tests to support 16-bit register accesses and larger data transfers.
- Added new cocotb tests to verify large (up to 4KB) packed writes and pipelined reads.

Change-Id: I4420f969584976c4fb16b25513c1791e54aced4c