)]}'
{
  "commit": "813d03e1c896c4c6c44a9eda9e25e7686d0b4e85",
  "tree": "114e4c42a1fe8dbdfc879d3c3ae917052527877c",
  "parents": [
    "7759a66faa0121563684b83fabb179db5f0ca410"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Wed Sep 17 16:16:46 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Sep 18 10:30:34 2025 -0700"
  },
  "message": "feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit\n\nThis change increases the maximum bulk transfer size of the Spi2TLUL module from 256 bytes to 65536 bytes by widening the length registers from 8 to 16 bits.\n\nThe key changes include:\n- Updated the Spi2TLUL Chisel module to use 16-bit length registers for both bulk and regular TileLink transfers.\n- Modified the SPI command state machine to handle two-byte length transactions.\n- Re-implemented the internal data buffers using SyncReadMem to support larger, configurable depths, and increased the buffer size to 4KB.\n- Introduced pipelining for SRAM reads to improve performance with larger data transfers.\n- Updated the Python SPI master utility and cocotb tests to support 16-bit register accesses and larger data transfers.\n- Added new cocotb tests to verify large (up to 4KB) packed writes and pipelined reads.\n\nChange-Id: I4420f969584976c4fb16b25513c1791e54aced4c\n",
  "tree_diff": [
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      "new_path": "hdl/chisel/src/bus/Spi2TLUL.scala"
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}