commit 7c162368e877629a2d888886ca4a4578d223b574
author Cindy Liu <hcindyl@google.com> Fri Oct 20 19:53:43 2023 +0000
committer Gerrit Code Review <noreply-gerritcodereview@google.com> Fri Oct 20 19:53:43 2023 +0000
tree bb822f63b3238eeb256dda37a1260d59f5e48155
parent 785139588bc2b362aa211117c4eea52b02a2ac6a
parent e7e931fb12ad249fd2c6fb44545626a6b4ddd220

Merge "OSS copyright header cleanup"

hdl/chisel/BUILD

diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index fb0f1ee..11c0dcd 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -73,6 +73,16 @@
 )
 
 chisel_cc_library(
+    name = "l1dcachebank_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitL1DCacheBank",
+    module_name = "L1DCacheBank",
+    verilog_deps = [
+        "//hdl/verilog:sram_1rw_256x288",
+    ],
+)
+
+chisel_cc_library(
     name = "l1icache_cc_library",
     chisel_lib = ":kelvin",
     emit_class = "kelvin.EmitL1ICache",

tests/verilator_sim/BUILD

diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index f5139c2..c47127e 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -92,6 +92,21 @@
 )
 
 cc_test(
+    name = "l1dcachebank_tb",
+    srcs = [
+        "kelvin/l1dcache_tb.cc",
+    ],
+    defines = [
+        "L1DCACHEBANK",
+    ],
+    deps = [
+        ":kelvin_if",
+        ":sim_libs",
+        "//hdl/chisel:l1dcachebank_cc_library",
+    ],
+)
+
+cc_test(
     name = "l1icache_tb",
     srcs = [
         "kelvin/l1icache_tb.cc",

tests/verilator_sim/kelvin/l1dcache_tb.cc

diff --git a/tests/verilator_sim/kelvin/l1dcache_tb.cc b/tests/verilator_sim/kelvin/l1dcache_tb.cc
index cb901d1..c305fbf 100644
--- a/tests/verilator_sim/kelvin/l1dcache_tb.cc
+++ b/tests/verilator_sim/kelvin/l1dcache_tb.cc
@@ -18,6 +18,7 @@
 #include "VL1DCache.h"
 constexpr int kDBusBankAdj = 0;
 #else
+#include "VL1DCacheBank.h"
 constexpr int kDBusBankAdj = 1;
 #endif
 
@@ -135,11 +136,13 @@
         p_wdata[i] = io_dbus_wdata.read().get_word(i);
       }
       const uint32_t linemask = kVLenB - 1;
+#ifdef L1DCACHEBANK
+      const uint32_t linebase = addr & ~linemask;
+#endif
       for (int i = 0; i < size; ++i, ++addr) {
         const uint32_t lineoffset = addr & linemask;
         if (io_dbus_wmask.read().get_bit(lineoffset)) {
 #ifdef L1DCACHEBANK
-          const uint32_t linebase = addr & ~linemask;
           WriteBus(linebase + lineoffset, wdata[lineoffset]);
 #else
           WriteBus(addr, wdata[lineoffset]);
@@ -375,10 +378,12 @@
     const uint32_t laddr = addr & kLineBase;
     const uint32_t loffset = addr & kLineOffset;
     const uint32_t doffset = addr & (outsz - 1);
+#ifndef L1DCACHEBANK
     uint32_t start = addr;
     uint32_t end = std::min(addr + size, laddr + kLineSize);
     int size0 = end - start;
     int size1 = size - size0;
+#endif
 
     memset(data, 0xCC, outsz);
 #ifdef L1DCACHEBANK