diff --git a/hdl/chisel/BUILD b/hdl/chisel/BUILD
index 42deab7..d821feb 100644
--- a/hdl/chisel/BUILD
+++ b/hdl/chisel/BUILD
@@ -12,174 +12,10 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-load("@kelvin_hw//rules:chisel.bzl", "chisel_cc_library", "chisel_library")
-
-chisel_library(
-    name = "common",
-    srcs = glob(["src/common/*.scala"]),
-)
-
-chisel_library(
-    name = "kelvin",
-    srcs = glob(["src/kelvin/**/*.scala"]),
-    deps = [
-        ":common",
-    ],
-)
-
-chisel_library(
-    name = "matcha",
-    srcs = glob(["src/matcha/**/*.scala"]),
-    deps = [
-        ":common",
-        ":kelvin",
-    ],
-)
-
-chisel_cc_library(
-    name = "kelvin_cc_library",
-    chisel_lib = ":matcha",
-    emit_class = "matcha.EmitKelvin",
-    module_name = "Kelvin",
-    verilog_deps = [
-        "//hdl/verilog:clock_gate",
-        "//hdl/verilog:sram_1rw_256x256",
-        "//hdl/verilog:sram_1rw_256x288",
-    ],
-)
-
-chisel_cc_library(
-    name = "core_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitCore",
-    module_name = "Core",
-)
-
-chisel_cc_library(
-    name = "dbus2axi_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitDBus2Axi",
-    module_name = "DBus2Axi",
-)
-
-chisel_cc_library(
-    name = "l1dcache_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitL1DCache",
-    module_name = "L1DCache",
-    verilog_deps = [
-        "//hdl/verilog:sram_1rw_256x288",
-    ],
-)
-
-chisel_cc_library(
-    name = "l1dcachebank_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitL1DCacheBank",
-    module_name = "L1DCacheBank",
-    verilog_deps = [
-        "//hdl/verilog:sram_1rw_256x288",
-    ],
-)
-
-chisel_cc_library(
-    name = "l1icache_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitL1ICache",
-    module_name = "L1ICache",
-    verilog_deps = [
-        "//hdl/verilog:sram_1rw_256x256",
-    ],
-)
-
-chisel_cc_library(
-    name = "valu_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVAlu",
-    module_name = "VAlu",
-)
-
-chisel_cc_library(
-    name = "valuint_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVAluInt",
-    module_name = "VAluInt",
-)
-
-chisel_cc_library(
-    name = "vcmdq_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVCmdq",
-    module_name = "VCmdq",
-)
-
-chisel_cc_library(
-    name = "vconvalu_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVConvAlu",
-    module_name = "VConvAlu",
-)
-
-chisel_cc_library(
-    name = "vconvctrl_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVConvCtrl",
-    module_name = "VConvCtrl",
-)
-
-chisel_cc_library(
-    name = "vdecode_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVDecode",
-    module_name = "VDecode",
-)
-
-chisel_cc_library(
-    name = "vdecodeinstruction_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVDecodeInstruction",
-    module_name = "VDecodeInstruction",
-)
-
-chisel_cc_library(
-    name = "vldst_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVLdSt",
-    module_name = "VLdSt",
-)
-
-chisel_cc_library(
-    name = "vld_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVLd",
-    module_name = "VLd",
-)
-
-chisel_cc_library(
-    name = "vregfile_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVRegfile",
-    module_name = "VRegfile",
-)
-
-chisel_cc_library(
-    name = "vregfilesegment_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVRegfileSegment",
-    module_name = "VRegfileSegment",
-)
-
-chisel_cc_library(
-    name = "vst_cc_library",
-    chisel_lib = ":kelvin",
-    emit_class = "kelvin.EmitVSt",
-    module_name = "VSt",
-)
-
 genrule(
     name = "matcha_kelvin_verilog",
     srcs = [
-        ":Kelvin.sv",
+        "//hdl/chisel/src/matcha:Kelvin.sv",
         "//hdl/verilog:ClockGate.v",
         "//hdl/verilog:Sram_1rw_256x256.v",
         "//hdl/verilog:Sram_1rwm_256x288.v",
@@ -196,7 +32,7 @@
     echo "\\`define STOP_COND 0
 \\`define PRINTF_COND 0
 " > $(location kelvin.sv)
-    cat $(location Kelvin.sv) >> $(location kelvin.sv)
+    cat $(location //hdl/chisel/src/matcha:Kelvin.sv) >> $(location kelvin.sv)
     cp -f $(location //hdl/verilog:ClockGate.v) $(location ClockGate.v)
     cp -f $(location //hdl/verilog:Sram_1rw_256x256.v) $(location Sram_1rw_256x256.v)
     cp -f $(location //hdl/verilog:Sram_1rwm_256x288.v) $(location Sram_1rwm_256x288.v)
diff --git a/hdl/chisel/src/BUILD b/hdl/chisel/src/BUILD
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/hdl/chisel/src/BUILD
diff --git a/hdl/chisel/src/common/BUILD b/hdl/chisel/src/common/BUILD
new file mode 100644
index 0000000..2dc5305
--- /dev/null
+++ b/hdl/chisel/src/common/BUILD
@@ -0,0 +1,47 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load("@kelvin_hw//rules:chisel.bzl",
+     "chisel_cc_library", "chisel_library", "chisel_test")
+
+chisel_library(
+    name = "common",
+    srcs = [
+        "Fifo4e.scala",
+        "Fifo4.scala",
+        "Fifo4x4.scala",
+        "Fifo.scala",
+        "IDiv.scala",
+        "Library.scala",
+        "Slice.scala",
+    ],
+    visibility = ["//visibility:public"],
+)
+
+chisel_library(
+    name = "fp",
+    srcs = [
+        "Fp.scala",
+    ],
+)
+
+chisel_test(
+    name = "fp_test",
+    srcs = [
+        "FpTest.scala",
+    ],
+    deps = [
+        ":fp",
+    ],
+)
\ No newline at end of file
diff --git a/hdl/chisel/src/common/Fp.scala b/hdl/chisel/src/common/Fp.scala
new file mode 100644
index 0000000..1cc1c07
--- /dev/null
+++ b/hdl/chisel/src/common/Fp.scala
@@ -0,0 +1,90 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package common
+
+import chisel3._
+import chisel3.util._
+
+class Fp32 extends Bundle {
+  val mantissa = UInt(23.W)
+  val exponent = UInt(8.W)
+  val sign     = Bool()
+
+  def asWord(): UInt = {
+    Cat(sign, exponent, mantissa)
+  }
+
+  def isZero(): Bool = {
+    (exponent === 0.U) && (mantissa === 0.U)
+  }
+
+  def isInf(): Bool = {
+    (exponent === "b11111111".U) && (mantissa === 0.U)
+  }
+
+  def isNan(): Bool = {
+    (exponent === "b11111111".U) && (mantissa =/= 0.U)
+  }
+
+  // The mantissa is generally the fractional component of significand.
+  def significand(): UInt = {
+    Cat(1.U(1.W), mantissa)
+  }
+}
+
+object Fp32 {
+  def apply(sign: Bool, exponent: UInt, mantissa: UInt): Fp32 = {
+    assert(exponent.getWidth == 8)
+    assert(mantissa.getWidth == 23)
+    val fp = Wire(new Fp32)
+    fp.mantissa := mantissa
+    fp.exponent := exponent
+    fp.sign := sign
+    fp
+  }
+
+  def fromWord(word: UInt): Fp32 = {
+    assert(word.getWidth == 32)
+    val fp = Wire(new Fp32)
+    fp.mantissa := word(22, 0)
+    fp.exponent := word(30, 23)
+    fp.sign := word(31)
+    fp
+  }
+
+  def Zero(sign: Bool): Fp32 = {
+    val fp = Wire(new Fp32)
+    fp.mantissa := 0.U
+    fp.exponent := 0.U
+    fp.sign := sign
+    fp
+  }
+
+  def Inf(sign: Bool): Fp32 = {
+    val fp = Wire(new Fp32)
+    fp.mantissa := 0.U
+    fp.exponent := "b11111111".U
+    fp.sign := sign
+    fp
+  }
+
+  def NaN(): Fp32 = {
+    val fp = Wire(new Fp32)
+    fp.mantissa := (1 << 22).U  // Cannonical NaN per RV32F spec
+    fp.exponent := "b11111111".U
+    fp.sign := 0.U
+    fp
+  }
+}
\ No newline at end of file
diff --git a/hdl/chisel/src/common/FpTest.scala b/hdl/chisel/src/common/FpTest.scala
new file mode 100644
index 0000000..70bf7b8
--- /dev/null
+++ b/hdl/chisel/src/common/FpTest.scala
@@ -0,0 +1,78 @@
+// Copyright 2024 Google LLC
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+package common
+
+import chisel3._
+import chisel3.util._
+import chiseltest._
+import org.scalatest.freespec.AnyFreeSpec
+import chisel3.experimental.BundleLiterals._
+
+class Fp32Tester extends Module {
+  val io = IO(new Bundle {
+    val in     = Input(UInt(32.W))
+    val is_zero = Output(Bool())
+    val is_inf  = Output(Bool())
+    val is_nan  = Output(Bool())
+  })
+
+  val fp = Fp32.fromWord(io.in)
+  io.is_zero := fp.isZero()
+  io.is_inf := fp.isInf()
+  io.is_nan := fp.isNan()
+}
+
+class FpSpec extends AnyFreeSpec with ChiselScalatestTester {
+  "Zero" in {
+    test(new Fp32Tester()) { dut =>
+      dut.io.in.poke(0.U)
+      assert(dut.io.is_zero.peekInt() == 1)
+      assert(dut.io.is_inf.peekInt() == 0)
+      assert(dut.io.is_nan.peekInt() == 0)
+    }
+  }
+
+  "Inf" in {
+    test(new Fp32Tester()) { dut =>
+      dut.io.in.poke(BigInt(
+          "0" + "11111111" + "00000000000000000000000", 2))
+      assert(dut.io.is_zero.peekInt() == 0)
+      assert(dut.io.is_inf.peekInt() == 1)
+      assert(dut.io.is_nan.peekInt() == 0)
+
+      dut.io.in.poke(BigInt(
+          "1" + "11111111" + "00000000000000000000000", 2))
+      assert(dut.io.is_zero.peekInt() == 0)
+      assert(dut.io.is_inf.peekInt() == 1)
+      assert(dut.io.is_nan.peekInt() == 0)
+    }
+  }
+
+  "Nan" in {
+    test(new Fp32Tester()) { dut =>
+      dut.io.in.poke(BigInt(
+          "0" + "11111111" + "00011000011000111000100", 2))
+      assert(dut.io.is_zero.peekInt() == 0)
+      assert(dut.io.is_inf.peekInt() == 0)
+      assert(dut.io.is_nan.peekInt() == 1)
+
+      dut.io.in.poke(BigInt(
+          "1" + "11111111" + "00011000011000111000100", 2))
+      assert(dut.io.is_zero.peekInt() == 0)
+      assert(dut.io.is_inf.peekInt() == 0)
+      assert(dut.io.is_nan.peekInt() == 1)
+    }
+  }
+}
\ No newline at end of file
diff --git a/hdl/chisel/src/kelvin/BUILD b/hdl/chisel/src/kelvin/BUILD
new file mode 100644
index 0000000..a6a2085
--- /dev/null
+++ b/hdl/chisel/src/kelvin/BUILD
@@ -0,0 +1,196 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load("@kelvin_hw//rules:chisel.bzl", "chisel_cc_library", "chisel_library")
+
+package(default_visibility = ["//visibility:public"])
+
+chisel_library(
+    name = "kelvin",
+    srcs = [
+        "Axi.scala",
+        "ClockGate.scala",
+        "Core.scala",
+        "DBus2Axi.scala",
+        "DBusMux.scala",
+        "L1DCache.scala",
+        "L1ICache.scala",
+        "Library.scala",
+        "Parameters.scala",
+        "scalar/Alu.scala",
+        "scalar/Bru.scala",
+        "scalar/Csr.scala",
+        "scalar/Debug.scala",
+        "scalar/Decode.scala",
+        "scalar/Dvu.scala",
+        "scalar/Fetch.scala",
+        "scalar/Flush.scala",
+        "scalar/Lsu.scala",
+        "scalar/Mlu.scala",
+        "scalar/Regfile.scala",
+        "scalar/SCore.scala",
+        "scalar/SLog.scala",
+        "vector/VAluInt.scala",
+        "vector/VAlu.scala",
+        "vector/VCmdq.scala",
+        "vector/VCommon.scala",
+        "vector/VConvAlu.scala",
+        "vector/VConvCtrl.scala",
+        "vector/VCore.scala",
+        "vector/VDecodeInstruction.scala",
+        "vector/VDecodeOp.scala",
+        "vector/VDecode.scala",
+        "vector/VDot.scala",
+        "vector/VEncodeOp.scala",
+        "vector/VInst.scala",
+        "vector/VLd.scala",
+        "vector/VLdSt.scala",
+        "vector/VRegfile.scala",
+        "vector/VRegfileSegment.scala",
+        "vector/VSt.scala",
+    ],
+    deps = [
+        "//hdl/chisel/src/common:common",
+    ],
+)
+
+
+
+chisel_cc_library(
+    name = "core_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitCore",
+    module_name = "Core",
+)
+
+chisel_cc_library(
+    name = "dbus2axi_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitDBus2Axi",
+    module_name = "DBus2Axi",
+)
+
+chisel_cc_library(
+    name = "l1dcache_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitL1DCache",
+    module_name = "L1DCache",
+    verilog_deps = [
+        "//hdl/verilog:sram_1rw_256x288",
+    ],
+)
+
+chisel_cc_library(
+    name = "l1dcachebank_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitL1DCacheBank",
+    module_name = "L1DCacheBank",
+    verilog_deps = [
+        "//hdl/verilog:sram_1rw_256x288",
+    ],
+)
+
+chisel_cc_library(
+    name = "l1icache_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitL1ICache",
+    module_name = "L1ICache",
+    verilog_deps = [
+        "//hdl/verilog:sram_1rw_256x256",
+    ],
+)
+
+chisel_cc_library(
+    name = "valu_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVAlu",
+    module_name = "VAlu",
+)
+
+chisel_cc_library(
+    name = "valuint_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVAluInt",
+    module_name = "VAluInt",
+)
+
+chisel_cc_library(
+    name = "vcmdq_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVCmdq",
+    module_name = "VCmdq",
+)
+
+chisel_cc_library(
+    name = "vconvalu_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVConvAlu",
+    module_name = "VConvAlu",
+)
+
+chisel_cc_library(
+    name = "vconvctrl_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVConvCtrl",
+    module_name = "VConvCtrl",
+)
+
+chisel_cc_library(
+    name = "vdecode_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVDecode",
+    module_name = "VDecode",
+)
+
+chisel_cc_library(
+    name = "vdecodeinstruction_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVDecodeInstruction",
+    module_name = "VDecodeInstruction",
+)
+
+chisel_cc_library(
+    name = "vldst_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVLdSt",
+    module_name = "VLdSt",
+)
+
+chisel_cc_library(
+    name = "vld_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVLd",
+    module_name = "VLd",
+)
+
+chisel_cc_library(
+    name = "vregfile_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVRegfile",
+    module_name = "VRegfile",
+)
+
+chisel_cc_library(
+    name = "vregfilesegment_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVRegfileSegment",
+    module_name = "VRegfileSegment",
+)
+
+chisel_cc_library(
+    name = "vst_cc_library",
+    chisel_lib = ":kelvin",
+    emit_class = "kelvin.EmitVSt",
+    module_name = "VSt",
+)
\ No newline at end of file
diff --git a/hdl/chisel/src/matcha/BUILD b/hdl/chisel/src/matcha/BUILD
new file mode 100644
index 0000000..6b10e4e
--- /dev/null
+++ b/hdl/chisel/src/matcha/BUILD
@@ -0,0 +1,42 @@
+# Copyright 2024 Google LLC
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+load("@kelvin_hw//rules:chisel.bzl", "chisel_cc_library", "chisel_library")
+
+package(default_visibility = ["//visibility:public"])
+
+chisel_library(
+    name = "matcha",
+    srcs = [
+        "Axi2Sram.scala",
+        "Crossbar.scala",
+        "Kelvin.scala",
+    ],
+    deps = [
+        "//hdl/chisel/src/common:common",
+        "//hdl/chisel/src/kelvin:kelvin",
+    ],
+)
+
+chisel_cc_library(
+    name = "kelvin_cc_library",
+    chisel_lib = ":matcha",
+    emit_class = "matcha.EmitKelvin",
+    module_name = "Kelvin",
+    verilog_deps = [
+        "//hdl/verilog:clock_gate",
+        "//hdl/verilog:sram_1rw_256x256",
+        "//hdl/verilog:sram_1rw_256x288",
+    ],
+)
\ No newline at end of file
diff --git a/tests/verilator_sim/BUILD b/tests/verilator_sim/BUILD
index c47127e..681096f 100644
--- a/tests/verilator_sim/BUILD
+++ b/tests/verilator_sim/BUILD
@@ -46,7 +46,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:core_cc_library",
+        "//hdl/chisel/src/kelvin:core_cc_library",
         "@com_google_absl//absl/flags:flag",
         "@com_google_absl//absl/flags:parse",
         "@com_google_absl//absl/flags:usage",
@@ -62,7 +62,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:kelvin_cc_library",
+        "//hdl/chisel/src/matcha:kelvin_cc_library",
     ],
 )
 
@@ -74,7 +74,7 @@
     ],
     deps = [
         ":sim_libs",
-        "//hdl/chisel:dbus2axi_cc_library",
+        "//hdl/chisel/src/kelvin:dbus2axi_cc_library",
     ],
 )
 
@@ -87,7 +87,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:l1dcache_cc_library",
+        "//hdl/chisel/src/kelvin:l1dcache_cc_library",
     ],
 )
 
@@ -102,7 +102,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:l1dcachebank_cc_library",
+        "//hdl/chisel/src/kelvin:l1dcachebank_cc_library",
     ],
 )
 
@@ -114,7 +114,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:l1icache_cc_library",
+        "//hdl/chisel/src/kelvin:l1icache_cc_library",
     ],
 )
 
@@ -139,7 +139,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":valu",
-        "//hdl/chisel:valu_cc_library",
+        "//hdl/chisel/src/kelvin:valu_cc_library",
     ],
 )
 
@@ -153,7 +153,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":valu",
-        "//hdl/chisel:valuint_cc_library",
+        "//hdl/chisel/src/kelvin:valuint_cc_library",
     ],
 )
 
@@ -191,7 +191,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vencodeop",
-        "//hdl/chisel:vcmdq_cc_library",
+        "//hdl/chisel/src/kelvin:vcmdq_cc_library",
     ],
 )
 
@@ -203,7 +203,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:vconvalu_cc_library",
+        "//hdl/chisel/src/kelvin:vconvalu_cc_library",
     ],
 )
 
@@ -217,7 +217,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vencodeop",
-        "//hdl/chisel:vconvctrl_cc_library",
+        "//hdl/chisel/src/kelvin:vconvctrl_cc_library",
     ],
 )
 
@@ -231,7 +231,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vdecode",
-        "//hdl/chisel:vdecodeinstruction_cc_library",
+        "//hdl/chisel/src/kelvin:vdecodeinstruction_cc_library",
     ],
 )
 
@@ -244,7 +244,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vdecode",
-        "//hdl/chisel:vdecode_cc_library",
+        "//hdl/chisel/src/kelvin:vdecode_cc_library",
     ],
 )
 
@@ -257,7 +257,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vencodeop",
-        "//hdl/chisel:vldst_cc_library",
+        "//hdl/chisel/src/kelvin:vldst_cc_library",
     ],
 )
 
@@ -271,7 +271,7 @@
         ":kelvin_if",
         ":sim_libs",
         ":vencodeop",
-        "//hdl/chisel:vld_cc_library",
+        "//hdl/chisel/src/kelvin:vld_cc_library",
     ],
 )
 
@@ -284,7 +284,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:vregfilesegment_cc_library",
+        "//hdl/chisel/src/kelvin:vregfilesegment_cc_library",
     ],
 )
 
@@ -296,7 +296,7 @@
     deps = [
         ":kelvin_if",
         ":sim_libs",
-        "//hdl/chisel:vregfile_cc_library",
+        "//hdl/chisel/src/kelvin:vregfile_cc_library",
     ],
 )
 
@@ -309,6 +309,6 @@
         ":kelvin_if",
         ":sim_libs",
         ":vencodeop",
-        "//hdl/chisel:vst_cc_library",
+        "//hdl/chisel/src/kelvin:vst_cc_library",
     ],
 )