tree df6c375c3259669b31a287455047a52f92505056
parent 0004fc32c1b0d4287693d1d0d1febce780730cf0
author Alex Van Damme <atv@google.com> 1755635505 -0700
committer Alex Van Damme <atv@google.com> 1756426581 -0700

refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar

This commit replaces the legacy `tlgen`-based crossbar with the new,
data-driven Chisel-based `KelvinXbar` in the FPGA design. This change
simplifies the build system, improves maintainability, and provides a
more flexible and robust interconnect.

Key changes:
- Removed the `tlgen` and `post_process_xbar.py` infrastructure from
  the FPGA build system.
- Instantiated the new `KelvinXbar` in `kelvin_soc.sv`, replacing the
  old crossbar and all associated width-sizers.
- Updated the clocking and reset logic to support the new crossbar's
  asynchronous domains, placing the Ibex core on its own clock.
- Removed the now-redundant Verilog implementations of the TileLink-UL
  primitives (FIFOs, sockets, width bridges).
- Added integrity generation to the `CoreTlul` module to ensure data
  integrity on the TileLink bus.
- Increased the FPGA clock frequency to 80MHz.

Change-Id: I340658419ca5cc93acee481c16334aeb026b2e7e