)]}' { "commit": "6edcd4e5a3f1bba747833970daf821a54c573fd1", "tree": "df6c375c3259669b31a287455047a52f92505056", "parents": [ "0004fc32c1b0d4287693d1d0d1febce780730cf0" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:31:45 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 17:16:21 2025 -0700" }, "message": "refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar\n\nThis commit replaces the legacy `tlgen`-based crossbar with the new,\ndata-driven Chisel-based `KelvinXbar` in the FPGA design. This change\nsimplifies the build system, improves maintainability, and provides a\nmore flexible and robust interconnect.\n\nKey changes:\n- Removed the `tlgen` and `post_process_xbar.py` infrastructure from\n the FPGA build system.\n- Instantiated the new `KelvinXbar` in `kelvin_soc.sv`, replacing the\n old crossbar and all associated width-sizers.\n- Updated the clocking and reset logic to support the new crossbar\u0027s\n asynchronous domains, placing the Ibex core on its own clock.\n- Removed the now-redundant Verilog implementations of the TileLink-UL\n primitives (FIFOs, sockets, width bridges).\n- Added integrity generation to the `CoreTlul` module to ensure data\n integrity on the TileLink bus.\n- Increased the FPGA clock frequency to 80MHz.\n\nChange-Id: I340658419ca5cc93acee481c16334aeb026b2e7e\n", "tree_diff": [ { "type": "modify", "old_id": "f221189d0e8806292aac74620907be3a475391e8", "old_mode": 33188, "old_path": "fpga/BUILD", "new_id": "4d8dc816900584f291249e8993badd8236176411", "new_mode": 33188, "new_path": "fpga/BUILD" }, { "type": "modify", "old_id": "912ddafb0081c98ed649d9227cf4bfe7d7c8f4c6", "old_mode": 33188, "old_path": "fpga/chip_nexus.core", "new_id": "4d930ddbf3c80955c1d30830e632f97fc3f09e4b", "new_mode": 33188, "new_path": "fpga/chip_nexus.core" }, { "type": "modify", "old_id": "0971b5ad5a7490fb0293167e565504f7163e9ead", "old_mode": 33188, "old_path": "fpga/chip_verilator.core", "new_id": "343866e39314195d500ada22277c35d8681eeacd", "new_mode": 33188, "new_path": "fpga/chip_verilator.core" }, { "type": "modify", "old_id": "37336d3b4cd6a5357f8347750707203a321d9172", "old_mode": 33188, "old_path": "fpga/ip/kelvin_tlul/kelvin_tlul.core", "new_id": "f1897533f4076e29465527dd9586ce44100b5c74", "new_mode": 33188, "new_path": "fpga/ip/kelvin_tlul/kelvin_tlul.core" }, { "type": "delete", "old_id": "22894bb13a5c16beca1206c92faca932d7e98fcd", "old_mode": 33188, "old_path": "fpga/ip/kelvin_tlul/tlul_fifo_async_128.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "af404f1f3d20a807ab448e0563a076fe1ec8255a", "old_mode": 33188, "old_path": "fpga/ip/kelvin_tlul/tlul_fifo_sync_128.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "2b333f00a32fb8df19252d4d1b58e62652bcf9c9", "old_mode": 33188, "old_path": "fpga/ip/kelvin_tlul/tlul_socket_1n_128.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "cded907588d96e2eee287b154f9fb311322e3f2c", "old_mode": 33188, "old_path": "fpga/ip/kelvin_tlul/tlul_socket_m1_128.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "5cc620393cb6070e5b67427b7f273ac089ab5173", "old_mode": 33188, "old_path": "fpga/ip/tlul_width_bridge/tlul_device_downsizer.core", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "524fb6b98ef091fd97855f990e9a57f72f962764", "old_mode": 33188, "old_path": "fpga/ip/tlul_width_bridge/tlul_device_downsizer.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "3c2511251b3a78d720f68e13235fe2bc3983c47f", "old_mode": 33188, "old_path": "fpga/ip/tlul_width_bridge/tlul_host_upsizer.core", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "delete", "old_id": "6958dfd37c59eb29720aa539f8e25500d413dddb", "old_mode": 33188, "old_path": "fpga/ip/tlul_width_bridge/tlul_host_upsizer.sv", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "rename", "old_id": "d78f918baa5ba58e71ef6db14395289dbc7dc15b", "old_mode": 33188, "old_path": "fpga/ip/tlul_width_bridge/BUILD", "new_id": "fe7f6ab92c3a7b91227fa066529833d4e1c43092", "new_mode": 33188, "new_path": "fpga/ip/xbar_kelvin_soc_chisel/BUILD", "score": 60 }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "b469a7ab70d4a1f76b55a682e5cd0065b58d10c4", "new_mode": 33188, "new_path": "fpga/ip/xbar_kelvin_soc_chisel/xbar_kelvin_soc_chisel.core" }, { "type": "add", "old_id": "0000000000000000000000000000000000000000", "old_mode": 0, "old_path": "/dev/null", "new_id": "88044d929869f7791df5a9349889f74a52249b35", "new_mode": 33188, "new_path": "fpga/ip/xbar_kelvin_soc_chisel/xbar_kelvin_soc_chisel.core.tpl" }, { "type": "modify", "old_id": "3db97b42395fd3bcd8bf12fa274a04f670512937", "old_mode": 33188, "old_path": "fpga/kelvin_soc.core", "new_id": "7cfb9e2e15f23acc0d32236c9db14377f265a325", "new_mode": 33188, "new_path": "fpga/kelvin_soc.core" }, { "type": "modify", "old_id": "3e1d3526f399f5f6fa6e27bb969a5def1b830e1b", "old_mode": 33188, "old_path": "fpga/main.cc", "new_id": "bc5fe646047622639758ccfa17210613e46748ca", "new_mode": 33188, "new_path": "fpga/main.cc" }, { "type": "delete", "old_id": "20179ab47c6e1f1247d1a92d51901b0dd3d473aa", "old_mode": 33188, "old_path": "fpga/post_process_xbar.py", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "modify", "old_id": "30f8dff55bec9731144eb66c817c0ee24488b70d", "old_mode": 33188, "old_path": "fpga/rtl/chip_nexus.sv", "new_id": "50dd2281f8dd514cc046fdf4531299433ecb11c7", "new_mode": 33188, "new_path": "fpga/rtl/chip_nexus.sv" }, { "type": "modify", "old_id": "b94ffcb2b8dc0b2cf52867db0865034907d4a3d5", "old_mode": 33188, "old_path": "fpga/rtl/chip_verilator.sv", "new_id": "ce495ed7c861e846f5ce4ae37c09665d9fcdde1f", "new_mode": 33188, "new_path": "fpga/rtl/chip_verilator.sv" }, { "type": "modify", "old_id": "55339efc5207defbd7fedbeaf965c52575d5a20c", "old_mode": 33188, "old_path": "fpga/rtl/clkgen_wrapper.sv", "new_id": "bcc8bcc22aa84ce92a6c024e3aee389e3465abd9", "new_mode": 33188, "new_path": "fpga/rtl/clkgen_wrapper.sv" }, { "type": "modify", "old_id": "98172658b232f201dc541e59b31b4b07f5705e22", "old_mode": 33188, "old_path": "fpga/rtl/clkgen_xilultrascaleplus.sv", "new_id": "bedc4a54c36fe6cd0e7f49c0fb6a648b47f05bcc", "new_mode": 33188, "new_path": "fpga/rtl/clkgen_xilultrascaleplus.sv" }, { "type": "modify", "old_id": "1c23def12d7de97c7262937769bc4402031a0356", "old_mode": 33188, "old_path": "fpga/rtl/kelvin_soc.sv", "new_id": "479f88749ce85ccf3d9d3d7c253b6a9680283b34", "new_mode": 33188, "new_path": "fpga/rtl/kelvin_soc.sv" }, { "type": "delete", "old_id": "df307ad1ad4e0ae175716eb806ddc4c1940a5e2c", "old_mode": 33188, "old_path": "fpga/rules.bzl", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "modify", "old_id": "3ff561f503fa23288708fbfebc82c035a744db54", "old_mode": 33188, "old_path": "fpga/sw/main.cc", "new_id": "f9c7b8e98283fc0e8b9ed1d15cf422e9238a1a30", "new_mode": 33188, "new_path": "fpga/sw/main.cc" }, { "type": "delete", "old_id": "82f5a8342bb143fd480c53dc944b61c4e361e5b2", "old_mode": 33188, "old_path": "fpga/tl_config.hjson", "new_id": "0000000000000000000000000000000000000000", "new_mode": 0, "new_path": "/dev/null" }, { "type": "modify", "old_id": "7c41c55970def87f6e09e3540a5ec2ecd1661656", "old_mode": 33188, "old_path": "hdl/chisel/src/kelvin/CoreTlul.scala", "new_id": "88ba92be7ab40e6fd52edca46dede2a91a9b23cf", "new_mode": 33188, "new_path": "hdl/chisel/src/kelvin/CoreTlul.scala" } ] }