diff --git a/hdl/chisel/src/common/Fifo.scala b/hdl/chisel/src/common/Fifo.scala
index 8c653b2..abced79 100644
--- a/hdl/chisel/src/common/Fifo.scala
+++ b/hdl/chisel/src/common/Fifo.scala
@@ -34,7 +34,7 @@
   // An (n-1) queue with a registered output stage.
   val m = n - 1  // n = Mem(n-1) + Out
 
-  val mem = Mem(m, t)
+  val mem = RegInit(VecInit(Seq.fill(n)(0.U(t.getWidth.W).asTypeOf(t))))
   val rdata = Reg(t)
 
   val rvalid = RegInit(false.B)
diff --git a/hdl/chisel/src/common/FifoIxO.scala b/hdl/chisel/src/common/FifoIxO.scala
index 5be7dd6..cdcf4bb 100644
--- a/hdl/chisel/src/common/FifoIxO.scala
+++ b/hdl/chisel/src/common/FifoIxO.scala
@@ -46,7 +46,7 @@
     d
   }
 
-  val mem = Reg(Vec(n, t))
+  val mem = RegInit(VecInit(Seq.fill(n)(0.U(t.getWidth.W).asTypeOf(t))))
 
   val inpos  = Reg(Vec(i, UInt(mb.W)))  // reset below
   val outpos = Reg(Vec(o, UInt(mb.W)))  // reset below
diff --git a/hdl/chisel/src/common/FifoX.scala b/hdl/chisel/src/common/FifoX.scala
index 7e6a925..8ec1d60 100644
--- a/hdl/chisel/src/common/FifoX.scala
+++ b/hdl/chisel/src/common/FifoX.scala
@@ -57,7 +57,7 @@
     d
   }
 
-  val mem = Mem(m, t)
+  val mem = RegInit(VecInit(Seq.fill(n)(0.U(t.getWidth.W).asTypeOf(t))))
   val mslice = Slice(t, false, true)
 
   val inxpos = RegInit(VecInit((0 until x).map(x => x.U(log2Ceil(m).W))))
diff --git a/hdl/chisel/src/common/FifoXe.scala b/hdl/chisel/src/common/FifoXe.scala
index 587be62..77e15bc 100644
--- a/hdl/chisel/src/common/FifoXe.scala
+++ b/hdl/chisel/src/common/FifoXe.scala
@@ -41,7 +41,7 @@
     d
   }
 
-  val mem = Mem(n, t)
+  val mem = RegInit(VecInit(Seq.fill(n)(0.U(t.getWidth.W).asTypeOf(t))))
 
   val inxpos = RegInit(VecInit((0 until x).map(x => x.U((log2Ceil(n) + 1).W))))
   val outpos = RegInit(0.U(log2Ceil(n).W))