diff --git a/hdl/verilog/ClockGate.sv b/hdl/verilog/ClockGate.sv
index 1dfb778..52a3aef 100644
--- a/hdl/verilog/ClockGate.sv
+++ b/hdl/verilog/ClockGate.sv
@@ -24,16 +24,28 @@
   output        clk_o
 );
 
-`ifndef USE_GENERIC
-CKLNQD10BWP6T20P96CPDLVT u_cg(
-  .TE(te),
-  .E(enable),
-  .CP(clk_i),
-  .Q(clk_o)
-);
-`else
+///////////////////////////
+/// ClockGate Selection ///
+///////////////////////////
+`ifdef USE_TSMC12FFC
+  // TSMC12FFC Specific ClockGate
+  CKLNQD10BWP6T20P96CPDLVT u_cg(
+    .TE(te),
+    .E(enable),
+    .CP(clk_i),
+    .Q(clk_o)
+  );
+`elsif USE_GF22
+  // GF22 Specific ClockGate
+  SC7P5T_CKGPRELATNX8_CSC36L u_cg (
+    .CLK(clk_i),
+    .E(enable),
+    .TE(te),
+    .Z(clk_o)
+  );
 
-`ifdef FPGA_XILINX
+`elsif FPGA_XILINX
+  // Xilinx FPGA Specific ClockGate
   BUFGCE #(
     .SIM_DEVICE("ULTRASCALE_PLUS")
   ) u_bufgce (
@@ -42,6 +54,7 @@
     .O (clk_o)
   );
 `else
+  // Default: Verilator implementation
   logic en_latch /* verilator clock_enable */;
   always_latch begin
     if (!clk_i) begin
@@ -49,8 +62,6 @@
     end
   end
   assign clk_o = en_latch & clk_i;
-`endif  // FPGA_XILINX
-
-`endif  // USE_GENERIC
+`endif
 
 endmodule  // ClockGate