tree 19304191fab669b98b7e06b837461d3aaf515432
parent 5a16231216eeb507e8863578a299b9de672a6218
author Alex Van Damme <atv@google.com> 1756855519 -0700
committer Alex Van Damme <atv@google.com> 1758216634 -0700

feat(fpga): Integrate Chisel Subsystem into FPGA build

This commit integrates the newly created `KelvinChiselSubsystem` into the top-level FPGA design for both Verilator simulation and the Nexus hardware target.

Key changes:
- **`kelvin_soc.sv`**: The top-level SoC module is updated to instantiate the `KelvinChiselSubsystem` instead of the individual Chisel-generated modules (core, crossbar). This greatly simplifies the top-level Verilog.
- **FPGA Build System**: The `fpga/BUILD` file is updated to build and use the `KelvinChiselSubsystem`. The dependencies on the old, individual modules (`rvv_core_mini_tlul`, `xbar_kelvin_soc_chisel`, `rv_core_ibex`) have been removed.
- **Verilator Simulation**: The `chip_verilator.sv` wrapper now includes the `spi_dpi_master`, allowing host-driven SPI communication with the simulated SoC.
- **Ibex Boot ROM Removal**: The Ibex core and its associated software boot ROM have been removed from the FPGA build.
- **Clocking**: The clock generator has been simplified to remove the dedicated clock for the now-removed standalone Ibex core.

This commit completes the transition to the unified Chisel subsystem architecture at the FPGA level.

Change-Id: I8de2a29e3f59ec834647f644c13bd9f6b9b4bb6c