)]}'
{
  "commit": "5fad6ba07730f96e34f323f734dcf656fff199df",
  "tree": "19304191fab669b98b7e06b837461d3aaf515432",
  "parents": [
    "5a16231216eeb507e8863578a299b9de672a6218"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Sep 02 16:25:19 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Sep 18 10:30:34 2025 -0700"
  },
  "message": "feat(fpga): Integrate Chisel Subsystem into FPGA build\n\nThis commit integrates the newly created `KelvinChiselSubsystem` into the top-level FPGA design for both Verilator simulation and the Nexus hardware target.\n\nKey changes:\n- **`kelvin_soc.sv`**: The top-level SoC module is updated to instantiate the `KelvinChiselSubsystem` instead of the individual Chisel-generated modules (core, crossbar). This greatly simplifies the top-level Verilog.\n- **FPGA Build System**: The `fpga/BUILD` file is updated to build and use the `KelvinChiselSubsystem`. The dependencies on the old, individual modules (`rvv_core_mini_tlul`, `xbar_kelvin_soc_chisel`, `rv_core_ibex`) have been removed.\n- **Verilator Simulation**: The `chip_verilator.sv` wrapper now includes the `spi_dpi_master`, allowing host-driven SPI communication with the simulated SoC.\n- **Ibex Boot ROM Removal**: The Ibex core and its associated software boot ROM have been removed from the FPGA build.\n- **Clocking**: The clock generator has been simplified to remove the dedicated clock for the now-removed standalone Ibex core.\n\nThis commit completes the transition to the unified Chisel subsystem architecture at the FPGA level.\n\nChange-Id: I8de2a29e3f59ec834647f644c13bd9f6b9b4bb6c\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4d8dc816900584f291249e8993badd8236176411",
      "old_mode": 33188,
      "old_path": "fpga/BUILD",
      "new_id": "57a5b3b5d6c80b7dfdca341fe4b8cb39d313c3a8",
      "new_mode": 33188,
      "new_path": "fpga/BUILD"
    },
    {
      "type": "modify",
      "old_id": "4d930ddbf3c80955c1d30830e632f97fc3f09e4b",
      "old_mode": 33188,
      "old_path": "fpga/chip_nexus.core",
      "new_id": "7a85b64323c5e44c16aa25c84e76517d729cd2ad",
      "new_mode": 33188,
      "new_path": "fpga/chip_nexus.core"
    },
    {
      "type": "modify",
      "old_id": "343866e39314195d500ada22277c35d8681eeacd",
      "old_mode": 33188,
      "old_path": "fpga/chip_verilator.core",
      "new_id": "3e52a5ad317703558f2457d2888d29500a00244a",
      "new_mode": 33188,
      "new_path": "fpga/chip_verilator.core"
    },
    {
      "type": "rename",
      "old_id": "fe7f6ab92c3a7b91227fa066529833d4e1c43092",
      "old_mode": 33188,
      "old_path": "fpga/ip/xbar_kelvin_soc_chisel/BUILD",
      "new_id": "f21f6680a611539034fb429a7c1bcf6ec6153c93",
      "new_mode": 33188,
      "new_path": "fpga/ip/kelvin_chisel_subsystem/BUILD",
      "score": 65
    },
    {
      "type": "rename",
      "old_id": "b48b9399221639c8905211fc207a14aeb1f5fe1b",
      "old_mode": 33188,
      "old_path": "fpga/ip/rvv_core_mini_tlul/rvv_core_mini_tlul.core.tpl",
      "new_id": "caa82c06325b116a4a3c66de808272f7db94c141",
      "new_mode": 33188,
      "new_path": "fpga/ip/kelvin_chisel_subsystem/kelvin_chisel_subsystem.core",
      "score": 72
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c7c85d252089614b88f594aa908572715caab57e",
      "new_mode": 33188,
      "new_path": "fpga/ip/kelvin_chisel_subsystem/kelvin_chisel_subsystem.core.tpl"
    },
    {
      "type": "delete",
      "old_id": "e8edeb8ef89dca6abd1332d8c7342d04c332acd3",
      "old_mode": 33188,
      "old_path": "fpga/ip/rvv_core_mini_tlul/BUILD",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "0b58a3458445fc00b52df8c9b833472d6b835e86",
      "old_mode": 33188,
      "old_path": "fpga/ip/rvv_core_mini_tlul/rvv_core_mini_tlul.core",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "1cd1f3dc11abd906ee57747e8a7cf072771c3e64",
      "old_mode": 33188,
      "old_path": "fpga/ip/sram/Sram.sv",
      "new_id": "6221bf3126438f4ce88e6b9adffcaff8541502b0",
      "new_mode": 33188,
      "new_path": "fpga/ip/sram/Sram.sv"
    },
    {
      "type": "delete",
      "old_id": "b469a7ab70d4a1f76b55a682e5cd0065b58d10c4",
      "old_mode": 33188,
      "old_path": "fpga/ip/xbar_kelvin_soc_chisel/xbar_kelvin_soc_chisel.core",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "88044d929869f7791df5a9349889f74a52249b35",
      "old_mode": 33188,
      "old_path": "fpga/ip/xbar_kelvin_soc_chisel/xbar_kelvin_soc_chisel.core.tpl",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "7cfb9e2e15f23acc0d32236c9db14377f265a325",
      "old_mode": 33188,
      "old_path": "fpga/kelvin_soc.core",
      "new_id": "fbf47498d3d03135dee5778f09e0ccba4610e08a",
      "new_mode": 33188,
      "new_path": "fpga/kelvin_soc.core"
    },
    {
      "type": "modify",
      "old_id": "1f881acef50e758fb774d2549c12fdbf98e8356d",
      "old_mode": 33188,
      "old_path": "fpga/pins.xdc",
      "new_id": "ebb1fe65dfc5005124afb247cb96198d00388515",
      "new_mode": 33188,
      "new_path": "fpga/pins.xdc"
    },
    {
      "type": "modify",
      "old_id": "50dd2281f8dd514cc046fdf4531299433ecb11c7",
      "old_mode": 33188,
      "old_path": "fpga/rtl/chip_nexus.sv",
      "new_id": "588dfc396f1639adc82d998e411657be2aa66668",
      "new_mode": 33188,
      "new_path": "fpga/rtl/chip_nexus.sv"
    },
    {
      "type": "modify",
      "old_id": "ce495ed7c861e846f5ce4ae37c09665d9fcdde1f",
      "old_mode": 33188,
      "old_path": "fpga/rtl/chip_verilator.sv",
      "new_id": "b83d8dc9aada2f6578d56d84d452d9b522e98dac",
      "new_mode": 33188,
      "new_path": "fpga/rtl/chip_verilator.sv"
    },
    {
      "type": "modify",
      "old_id": "bcc8bcc22aa84ce92a6c024e3aee389e3465abd9",
      "old_mode": 33188,
      "old_path": "fpga/rtl/clkgen_wrapper.sv",
      "new_id": "9ea066c41129c0f21322079cac2ffcfbcfde7c2b",
      "new_mode": 33188,
      "new_path": "fpga/rtl/clkgen_wrapper.sv"
    },
    {
      "type": "modify",
      "old_id": "bedc4a54c36fe6cd0e7f49c0fb6a648b47f05bcc",
      "old_mode": 33188,
      "old_path": "fpga/rtl/clkgen_xilultrascaleplus.sv",
      "new_id": "7c3de4cbd1ea2000ebd3ff1fa512fedfb4c35113",
      "new_mode": 33188,
      "new_path": "fpga/rtl/clkgen_xilultrascaleplus.sv"
    },
    {
      "type": "modify",
      "old_id": "37de7076a2a65b712f5438536c44fa78fd85b608",
      "old_mode": 33188,
      "old_path": "fpga/rtl/kelvin_soc.sv",
      "new_id": "3f61b7c21353035c1b51605f8996ef7b24e55206",
      "new_mode": 33188,
      "new_path": "fpga/rtl/kelvin_soc.sv"
    },
    {
      "type": "delete",
      "old_id": "1c2bfe84e7aea41b3c0041d6169888895fddda0f",
      "old_mode": 33188,
      "old_path": "fpga/sw/ibex_boot_rom.S",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "95ab2327db0d327dd3eab466e7f3a1eba4aef9bf",
      "old_mode": 33188,
      "old_path": "fpga/sw/ibex_boot_rom.ld",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "f9c7b8e98283fc0e8b9ed1d15cf422e9238a1a30",
      "old_mode": 33188,
      "old_path": "fpga/sw/main.cc",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}