commit 468532a912457a70e7b738924c74386521d39256
author Yenkai Wang <ykwang@google.com> Wed Dec 20 20:17:06 2023 -0600
committer Yenkai Wang <ykwang@google.com> Tue Jan 02 17:38:11 2024 -0600
tree 74fa180f3322a2e7e7f2467895303e3cefff9066
parent aaf3e5456ee29ec15835a4a7b79b5771845b5d91

Add macro definition for srams in ML core

Change-Id: I9cbe391f9cafdefecff706e8ea75a94ea7ee9eec

hdl/verilog/Sram_1rw_256x256.v

diff --git a/hdl/verilog/Sram_1rw_256x256.v b/hdl/verilog/Sram_1rw_256x256.v
index d0a0b9a..a6a6d52 100644
--- a/hdl/verilog/Sram_1rw_256x256.v
+++ b/hdl/verilog/Sram_1rw_256x256.v
@@ -22,6 +22,42 @@
   input          volt_sel
 );
 
+`ifdef GF22_ML_CACHE
+  logic [1:0] ma_sawl;
+  logic [1:0] ma_wras;
+  logic       ma_wrasd;
+
+  always_comb begin
+    if(volt_sel)begin
+     ma_sawl = 2'b11;
+     ma_wras = 2'b10;
+     ma_wrasd = 1'b0;
+    end
+    else begin
+     ma_sawl = 2'b00;
+     ma_wras = 2'b00;
+     ma_wrasd = 1'b1;
+    end
+  end
+
+  MBH_ZSNL_IN22FDX_S1PL_NFLG_W00256B256M04C128  u_gf22_ml_icache
+    (
+     .clk(clock),
+     .cen(~valid),
+     .rdwen(~write),
+     .deepsleep(1'b0),
+     .powergate(1'b0),
+     .MA_SAWL0(ma_sawl[0]),
+     .MA_SAWL1(ma_sawl[1]),
+     .MA_WRAS0(ma_wras[0]),
+     .MA_WRAS1(ma_wras[1]),
+     .MA_WRASD(ma_wrasd),
+     .a(addr),
+     .d(wdata),
+     .bw({256{1'b1}}),
+     .q(rdata)
+     );
+`else
   reg [255:0] mem [0:255];
   reg [7:0] raddr;
 
@@ -35,4 +71,5 @@
       raddr <= addr;
     end
   end
+`endif // GF22_ML_CACHE
 endmodule

hdl/verilog/Sram_1rwm_256x288.v

diff --git a/hdl/verilog/Sram_1rwm_256x288.v b/hdl/verilog/Sram_1rwm_256x288.v
index 7750f9d..65e252d 100644
--- a/hdl/verilog/Sram_1rwm_256x288.v
+++ b/hdl/verilog/Sram_1rwm_256x288.v
@@ -89,6 +89,47 @@
   input          volt_sel
 );
 
+
+
+`ifdef GF22_ML_CACHE
+logic [1:0] ma_sawl;
+logic [1:0] ma_wras;
+logic       ma_wrasd;
+
+  always_comb begin
+    if(volt_sel)begin
+     ma_sawl = 2'b11;
+     ma_wras = 2'b10;
+     ma_wrasd = 1'b0;
+    end
+    else begin
+     ma_sawl = 2'b00;
+     ma_wras = 2'b00;
+     ma_wrasd = 1'b1;
+    end
+  end
+
+  begin
+   MBH_ZSNL_IN22FDX_S1PL_NFLG_W00256B009M16C128  u_gf22_ml_dcache
+   (
+    .clk(clock),
+    .cen(~valid),
+    .rdwen(~write),
+    .deepsleep(1'b0),
+    .powergate(1'b0),
+    .MA_SAWL0(ma_sawl[0]),
+    .MA_SAWL1(ma_sawl[1]),
+    .MA_WRAS0(ma_wras[0]),
+    .MA_WRAS1(ma_wras[1]),
+    .MA_WRASD(ma_wrasd),
+    .a(addr),
+    .d(wdata),
+    .bw({9{1'b1}}),
+    .q(rdata)
+    );
+  end
+`else
+
   reg [8:0] mem [0:255];
   reg [7:0] raddr;
 
@@ -102,6 +143,7 @@
       raddr <= addr;
     end
   end
+`endif // GF22_ML_CACHE
 endmodule  // Sram_1rw_256x9
 
 `endif  // FPGA