)]}'
{
  "commit": "148e450ec330c1cd4236d5caa317c0b4b1e34f9f",
  "tree": "126e67a850338811ada1742451acf848e9af47e0",
  "parents": [
    "b9b0d55ba96b549756bb207a33dae793a9495859"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Aug 19 13:27:12 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Aug 28 16:49:58 2025 -0700"
  },
  "message": "refactor(bus): Clean up AXI/TL-UL bridges and tests\n\nThis commit refactors the AXI-to-TileLink and TileLink-to-AXI bridge\nlogic and cleans up the associated test infrastructure.\n\nKey changes:\n- Simplified the ready signal logic in `Axi2TLUL.scala` for better\n  clarity and correctness.\n- Moved the cocotb test files for the AXI/TL-UL bridges from\n  `hdl/chisel/src/bus` to a dedicated `tests/cocotb/tlul` directory.\n- Reorganized the Bazel BUILD files to reflect the new test locations\n  and improve dependency management.\n- Added minor delays at the end of the `tlul2axi` tests to facilitate\n  easier waveform debugging.\n\nChange-Id: I9a2a3c6510d34b010e0ecc2ba1da1db3e1462f2b\n",
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