Lint cleanup Change-Id: I5f176d3a7e8daadc51b769818bb6724611faa4c3
diff --git a/hdl/verilog/BUILD b/hdl/verilog/BUILD index 81d5af0..85ee4f8 100644 --- a/hdl/verilog/BUILD +++ b/hdl/verilog/BUILD
@@ -16,4 +16,4 @@ name = "sram_1rw_256x288", srcs = ["Sram_1rwm_256x288.v"], visibility = ["//visibility:public"], -) \ No newline at end of file +)
diff --git a/lib/BUILD b/lib/BUILD index 79ff16e..7c0b795 100644 --- a/lib/BUILD +++ b/lib/BUILD
@@ -2,45 +2,41 @@ scala_library( name = "chisel_lib", - - deps = [ - "@com_thoughtworks_paranamer//jar", - "@org_json4s_json4s_scalap//jar", - "@org_json4s_json4s_ast//jar", - "@org_json4s_json4s_core//jar", - "@org_json4s_json4s_native//jar", - "@org_apache_commons_commons_lang3//jar", - "@org_apache_commons_commons_text//jar", - "@edu_berkeley_cs_chisel3_plugin//jar", - "@com_github_scopt//jar", - "@net_jcazevedo_moultingyaml//jar", - "@edu_berkeley_cs_firrtl//jar", - "@edu_berkeley_cs_chisel3_core//jar", - "@edu_berkeley_cs_chisel3_macros//jar", - "@edu_berkeley_cs_chisel3//jar", - ], - - exports = [ - "@com_thoughtworks_paranamer//jar", - "@org_json4s_json4s_scalap//jar", - "@org_json4s_json4s_ast//jar", - "@org_json4s_json4s_core//jar", - "@org_json4s_json4s_native//jar", - "@org_apache_commons_commons_lang3//jar", - "@org_apache_commons_commons_text//jar", - "@edu_berkeley_cs_chisel3_plugin//jar", - "@com_github_scopt//jar", - "@net_jcazevedo_moultingyaml//jar", - "@edu_berkeley_cs_firrtl//jar", - "@edu_berkeley_cs_chisel3_core//jar", - "@edu_berkeley_cs_chisel3_macros//jar", - "@edu_berkeley_cs_chisel3//jar", - ], - - visibility = ["//visibility:public"], - scalacopts = [ "-Xplugin:$(execpath @edu_berkeley_cs_chisel3_plugin//jar)", "-P:chiselplugin:genBundleElements", ], -) \ No newline at end of file + visibility = ["//visibility:public"], + exports = [ + "@com_github_scopt//jar", + "@com_thoughtworks_paranamer//jar", + "@edu_berkeley_cs_chisel3//jar", + "@edu_berkeley_cs_chisel3_core//jar", + "@edu_berkeley_cs_chisel3_macros//jar", + "@edu_berkeley_cs_chisel3_plugin//jar", + "@edu_berkeley_cs_firrtl//jar", + "@net_jcazevedo_moultingyaml//jar", + "@org_apache_commons_commons_lang3//jar", + "@org_apache_commons_commons_text//jar", + "@org_json4s_json4s_ast//jar", + "@org_json4s_json4s_core//jar", + "@org_json4s_json4s_native//jar", + "@org_json4s_json4s_scalap//jar", + ], + deps = [ + "@com_github_scopt//jar", + "@com_thoughtworks_paranamer//jar", + "@edu_berkeley_cs_chisel3//jar", + "@edu_berkeley_cs_chisel3_core//jar", + "@edu_berkeley_cs_chisel3_macros//jar", + "@edu_berkeley_cs_chisel3_plugin//jar", + "@edu_berkeley_cs_firrtl//jar", + "@net_jcazevedo_moultingyaml//jar", + "@org_apache_commons_commons_lang3//jar", + "@org_apache_commons_commons_text//jar", + "@org_json4s_json4s_ast//jar", + "@org_json4s_json4s_core//jar", + "@org_json4s_json4s_native//jar", + "@org_json4s_json4s_scalap//jar", + ], +)
diff --git a/rules/deps.bzl b/rules/deps.bzl index 8f1645a..e26ce4d 100644 --- a/rules/deps.bzl +++ b/rules/deps.bzl
@@ -1,13 +1,20 @@ load("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") -load("@io_bazel_rules_scala//scala:scala_maven_import_external.bzl", - "scala_maven_import_external") -load("@io_bazel_rules_scala//scala:scala_cross_version.bzl", - "default_maven_server_urls") -load("@rules_foreign_cc//foreign_cc:repositories.bzl", - "rules_foreign_cc_dependencies") -load("@rules_hdl//dependency_support:dependency_support.bzl", - rules_hdl_dependency_support = "dependency_support") - +load( + "@io_bazel_rules_scala//scala:scala_maven_import_external.bzl", + "scala_maven_import_external", +) +load( + "@io_bazel_rules_scala//scala:scala_cross_version.bzl", + "default_maven_server_urls", +) +load( + "@rules_foreign_cc//foreign_cc:repositories.bzl", + "rules_foreign_cc_dependencies", +) +load( + "@rules_hdl//dependency_support:dependency_support.bzl", + rules_hdl_dependency_support = "dependency_support", +) def kelvin_deps(): rules_foreign_cc_dependencies()
diff --git a/tests/verilator_sim/fifo.h b/tests/verilator_sim/fifo.h index ed078e6..2e00709 100644 --- a/tests/verilator_sim/fifo.h +++ b/tests/verilator_sim/fifo.h
@@ -2,6 +2,8 @@ #ifndef TESTS_VERILATOR_SIM_FIFO_H_ #define TESTS_VERILATOR_SIM_FIFO_H_ +#include <vector> + // A SystemC CRT transaction queue. template <typename T>
diff --git a/tests/verilator_sim/kelvin/core_if.h b/tests/verilator_sim/kelvin/core_if.h index 427e617..7ecbf4a 100644 --- a/tests/verilator_sim/kelvin/core_if.h +++ b/tests/verilator_sim/kelvin/core_if.h
@@ -146,7 +146,7 @@ sc_bv<256> rdata; uint32_t addr = io_ibus_addr.read().get_word(0); uint32_t words[256 / 32]; - Read(addr, 256 / 8, (uint8_t*) words); + Read(addr, 256 / 8, reinterpret_cast<uint8_t*>(words)); for (int i = 0; i < 256 / 32; ++i) { rdata.set_word(i, words[i]); @@ -162,8 +162,8 @@ uint32_t words[kVector / 32] = {0}; memset(words, 0xcc, sizeof(words)); int bytes = io_dbus_size.read().get_word(0); - Read(addr, bytes, (uint8_t*) words); - ReadSwizzle(addr, kVector / 8, (uint8_t*) words); + Read(addr, bytes, reinterpret_cast<uint8_t*>(words)); + ReadSwizzle(addr, kVector / 8, reinterpret_cast<uint8_t*>(words)); for (int i = 0; i < kVector / 32; ++i) { rdata.set_word(i, words[i]); } @@ -179,8 +179,8 @@ for (int i = 0; i < kVector / 32; ++i) { words[i] = wdata.get_word(i); } - WriteSwizzle(addr, kVector / 8, (uint8_t*) words); - Write(addr, bytes, (uint8_t*) words); + WriteSwizzle(addr, kVector / 8, reinterpret_cast<uint8_t*>(words)); + Write(addr, bytes, reinterpret_cast<uint8_t*>(words)); } rtcm_t tcm_read; @@ -190,7 +190,7 @@ if (io_axi0_read_addr_valid && io_axi0_read_addr_ready) { uint32_t addr = io_axi0_read_addr_bits_addr.read().get_word(0); uint32_t words[kUncBits / 32]; - Read(addr, kUncBits / 8, (uint8_t*) words); + Read(addr, kUncBits / 8, reinterpret_cast<uint8_t*>(words)); tcm_read.cycle = cycle_; tcm_read.id = io_axi0_read_addr_bits_id.read().get_word(0); @@ -217,7 +217,7 @@ assert(io_axi0_write_data_valid && io_axi0_write_data_valid); uint8_t wdata[kUncBits / 8]; uint32_t addr = io_axi0_write_addr_bits_addr.read().get_word(0); - uint32_t* p_wdata = (uint32_t*) wdata; + uint32_t* p_wdata = reinterpret_cast<uint32_t*>(wdata); for (int i = 0; i < kUncBits / 32; ++i) { p_wdata[i] = io_axi0_write_data_bits_data.read().get_word(i); @@ -239,7 +239,7 @@ if (io_axi1_read_addr_valid && io_axi1_read_addr_ready) { uint32_t addr = io_axi1_read_addr_bits_addr.read().get_word(0); uint32_t words[kUncBits / 32]; - Read(addr, kUncBits / 8, (uint8_t*) words); + Read(addr, kUncBits / 8, reinterpret_cast<uint8_t*>(words)); tcm_read.cycle = cycle_; tcm_read.id = io_axi1_read_addr_bits_id.read().get_word(0); @@ -266,7 +266,7 @@ assert(io_axi1_write_data_valid && io_axi1_write_data_valid); uint8_t wdata[kUncBits / 8]; uint32_t addr = io_axi1_write_addr_bits_addr.read().get_word(0); - uint32_t* p_wdata = (uint32_t*) wdata; + uint32_t* p_wdata = reinterpret_cast<uint32_t*>(wdata); for (int i = 0; i < kUncBits / 32; ++i) { p_wdata[i] = io_axi1_write_data_bits_data.read().get_word(i); @@ -286,7 +286,7 @@ } } -private: + private: uint32_t cycle_ = 0; struct rtcm_t {
diff --git a/tests/verilator_sim/kelvin/dbus2axi_tb.cc b/tests/verilator_sim/kelvin/dbus2axi_tb.cc index 14d6e33..91f1da7 100644 --- a/tests/verilator_sim/kelvin/dbus2axi_tb.cc +++ b/tests/verilator_sim/kelvin/dbus2axi_tb.cc
@@ -175,93 +175,94 @@ private: - struct axi_read_addr_t { - uint32_t addr; - uint32_t id : 7; + struct axi_read_addr_t { + uint32_t addr; + uint32_t id : 7; - bool operator!=(const axi_read_addr_t& rhs) const { - if (addr != rhs.addr) return true; - if (id != rhs.id) return true; - return false; - } + bool operator!=(const axi_read_addr_t& rhs) const { + if (addr != rhs.addr) return true; + if (id != rhs.id) return true; + return false; + } - void print(const char* name) { - printf("[%s]: id=%x addr=%08x\n", name, id, addr); - } - }; + void print(const char* name) { + printf("[%s]: id=%x addr=%08x\n", name, id, addr); + } + }; - struct axi_read_data_t { - uint32_t id : 7; - uint32_t resp : 7; - sc_bv<256> data; + struct axi_read_data_t { + uint32_t id : 7; + uint32_t resp : 7; + sc_bv<256> data; - bool operator!=(const axi_read_data_t& rhs) const { - if (id != rhs.id) return true; - if (data != rhs.data) return true; - return false; - } + bool operator!=(const axi_read_data_t& rhs) const { + if (id != rhs.id) return true; + if (data != rhs.data) return true; + return false; + } - void print(const char* name) { - printf("[%s]: id=%x data=", name, id); - for (int i = 0; i < 256 / 32; ++i) { - printf("%08x ", data.get_word(i)); - } - printf("\n"); - } - }; + void print(const char* name) { + printf("[%s]: id=%x data=", name, id); + for (int i = 0; i < 256 / 32; ++i) { + printf("%08x ", data.get_word(i)); + } + printf("\n"); + } + }; - struct axi_write_addr_t { - uint32_t addr; - uint32_t id : 7; - sc_bv<256> data; - sc_bv<32> strb; + struct axi_write_addr_t { + uint32_t addr; + uint32_t id : 7; + sc_bv<256> data; + sc_bv<32> strb; - bool operator!=(const axi_write_addr_t& rhs) const { - if (addr != rhs.addr) return true; - if (id != rhs.id) return true; - if (strb != rhs.strb) return true; - if (data != rhs.data) return true; - return false; - } + bool operator!=(const axi_write_addr_t& rhs) const { + if (addr != rhs.addr) return true; + if (id != rhs.id) return true; + if (strb != rhs.strb) return true; + if (data != rhs.data) return true; + return false; + } - void print(const char* name) { - printf("[%s]: id=%x addr=%08x strb=%08x data=", name, id, addr, strb.get_word(0)); - for (int i = 0; i < 256 / 32; ++i) { - printf("%08x ", data.get_word(0)); - } - printf("\n"); - } - }; + void print(const char* name) { + printf("[%s]: id=%x addr=%08x strb=%08x data=", name, id, addr, + strb.get_word(0)); + for (int i = 0; i < 256 / 32; ++i) { + printf("%08x ", data.get_word(0)); + } + printf("\n"); + } + }; - struct axi_write_resp_t { - uint32_t id : 7; - uint32_t resp : 2; - }; + struct axi_write_resp_t { + uint32_t id : 7; + uint32_t resp : 2; + }; - struct dbus_read_data_t { - sc_bv<256> data; + struct dbus_read_data_t { + sc_bv<256> data; - bool operator!=(const dbus_read_data_t& rhs) const { - if (data != rhs.data) return true; - return false; - } + bool operator!=(const dbus_read_data_t& rhs) const { + if (data != rhs.data) return true; + return false; + } - void print(const char* name) { - printf("[%s]: data=", name); - for (int i = 0; i < 256 / 32; ++i) { - printf("%08x ", data.get_word(i)); - } - printf("\n"); - } - }; + void print(const char* name) { + printf("[%s]: data=", name); + for (int i = 0; i < 256 / 32; ++i) { + printf("%08x ", data.get_word(i)); + } + printf("\n"); + } + }; - bool dbus_read_ready_ = false; - bool dbus_read_active_ = false; - fifo_t<axi_read_addr_t> axi_read_addr_; - fifo_t<axi_read_data_t> axi_read_data_; - fifo_t<axi_write_addr_t> axi_write_addr_; - fifo_t<axi_write_resp_t> axi_write_resp_; - fifo_t<dbus_read_data_t> dbus_read_data_; + bool dbus_read_ready_ = false; + bool dbus_read_active_ = false; + fifo_t<axi_read_addr_t> axi_read_addr_; + fifo_t<axi_read_data_t> axi_read_data_; + fifo_t<axi_write_addr_t> axi_write_addr_; + fifo_t<axi_write_resp_t> axi_write_resp_; + fifo_t<dbus_read_data_t> dbus_read_data_; }; static void DBus2Axi_test(char* name, int loops, bool trace) {
diff --git a/tests/verilator_sim/kelvin/l1dcachebank_tb.cc b/tests/verilator_sim/kelvin/l1dcachebank_tb.cc deleted file mode 100644 index 0048f07..0000000 --- a/tests/verilator_sim/kelvin/l1dcachebank_tb.cc +++ /dev/null
@@ -1,7 +0,0 @@ -// Copyright 2023 Google LLC - -#include "VL1DCacheBank.h" - -#define L1DCACHEBANK - -#include "l1dcache_tb.cc"
diff --git a/tests/verilator_sim/kelvin/l1icache_tb.cc b/tests/verilator_sim/kelvin/l1icache_tb.cc index 4a2c0a5..3f05e7f 100644 --- a/tests/verilator_sim/kelvin/l1icache_tb.cc +++ b/tests/verilator_sim/kelvin/l1icache_tb.cc
@@ -6,8 +6,7 @@ #include "tests/verilator_sim/kelvin/kelvin_cfg.h" -struct L1ICache_tb : Sysc_tb -{ +struct L1ICache_tb : Sysc_tb { sc_out<bool> io_flush_valid; sc_in<bool> io_flush_ready; sc_out<bool> io_ibus_valid; @@ -100,7 +99,7 @@ } } -private: + private: struct command_t { uint32_t addr; };
diff --git a/tests/verilator_sim/kelvin/vconvctrl_tb.cc b/tests/verilator_sim/kelvin/vconvctrl_tb.cc index 6f1f926..daee93e 100644 --- a/tests/verilator_sim/kelvin/vconvctrl_tb.cc +++ b/tests/verilator_sim/kelvin/vconvctrl_tb.cc
@@ -317,7 +317,8 @@ "addr1=%d addr2=%d index=%d asign=%d bsign=%d " "abias=%d " "bbias=%d\n", - name, conv, tran, wclr, addr1, addr2, index, asign, bsign, abias, bbias); + name, conv, tran, wclr, addr1, addr2, index, asign, bsign, abias, + bbias); } };
diff --git a/tests/verilator_sim/matcha/kelvin_if.h b/tests/verilator_sim/matcha/kelvin_if.h index 9c77ecd..bf32c6c 100644 --- a/tests/verilator_sim/matcha/kelvin_if.h +++ b/tests/verilator_sim/matcha/kelvin_if.h
@@ -45,7 +45,7 @@ sc_bv<kBusBits> rdata; uint32_t addr = io_bus_caddr.read().get_word(0); uint32_t words[kBusBits / 32]; - Read(addr, kBusBits / 8, (uint8_t*) words); + Read(addr, kBusBits / 8, reinterpret_cast<uint8_t*>(words)); for (int i = 0; i < kBusBits / 32; ++i) { rdata.set_word(i, words[i]); @@ -78,7 +78,7 @@ if (io_bus_cvalid && io_bus_cready && io_bus_cwrite) { uint8_t wdata[kBusBits / 8]; uint32_t addr = io_bus_caddr.read().get_word(0); - uint32_t* p_wdata = (uint32_t*) wdata; + uint32_t* p_wdata = reinterpret_cast<uint32_t*>(wdata); for (int i = 0; i < kBusBits / 32; ++i) { p_wdata[i] = io_bus_wdata.read().get_word(i); @@ -92,7 +92,7 @@ } } -private: + private: uint32_t cycle_ = 0; struct resp_t {