diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/env/rvs_agent.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/env/rvs_agent.sv
index 1820d97..8009941 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/env/rvs_agent.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/env/rvs_agent.sv
@@ -26,6 +26,9 @@
     if(is_active == UVM_ACTIVE) begin
       rvs_sqr = rvs_sequencer::type_id::create("rvs_sqr", this);
       rvs_drv = rvs_driver::type_id::create("rvs_drv", this);
+      rvs_mon.is_active = UVM_ACTIVE;
+    end else begin
+      rvs_mon.is_active = UVM_PASSIVE;
     end
     if(!uvm_config_db#(v_if1)::get(this, "", "rvs_if", rvs_agt_if)) begin
       `uvm_fatal("AGT/NOVIF", "No virtual interface specified for this agent instance")
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_monitor.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_monitor.sv
index b9e7b9d..71627c3 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_monitor.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_monitor.sv
@@ -8,7 +8,7 @@
   `uvm_analysis_imp_decl(_rvs_mon_inst)
   `uvm_blocking_get_imp_decl(_rvv_state)
 class rvs_monitor extends uvm_monitor;
-
+  uvm_active_passive_enum is_active = UVM_ACTIVE;
   uvm_analysis_imp_rvs_mon_inst #(rvs_transaction,rvs_monitor) inst_imp; 
   uvm_blocking_get_imp_rvv_state #(rvv_state_pkg::rvv_state_e, rvs_monitor) rvv_state_imp;
 
@@ -33,7 +33,9 @@
   int inst_tx_timeout_max = 500;
   int inst_tx_timeout_cnt = 0;
 
-  `uvm_component_utils_begin(rvs_monitor)
+  bit use_tr_from_drv;
+
+  `uvm_component_param_utils_begin(rvs_monitor)
   `uvm_component_utils_end
 
   extern function new(string name = "rvs_monitor",uvm_component parent);
@@ -69,6 +71,11 @@
   ctrl_ap = new("ctrl_ap", this);
 
   ctrl_tr = new("ctrl_tr");
+  if($test$plusargs("use_tr_from_drv")) begin
+    use_tr_from_drv = 1;
+  end else begin
+    use_tr_from_drv = 0;
+  end
 endfunction: build_phase
 
 function void rvs_monitor::connect_phase(uvm_phase phase);
@@ -118,24 +125,26 @@
 endtask: run_phase
 
 task rvs_monitor::main_phase(uvm_phase phase);
-  rvv_state_pkg::rvv_state_e rvv_state;
-  phase.raise_objection( .obj( this ) );
-  super.main_phase(phase);
-  forever begin
-    @(posedge rvs_if.clk);
-    if(ctrl_tr.is_last_inst) begin
-      get_rvv_state(rvv_state);
-      if(inst_tx_queue.size()==0 && inst_rx_queue.size()==0 && inst_temp_queue.size()==0 && rvv_state==rvv_state_pkg::IDLE) begin 
-        repeat(10) @(posedge rvs_if.clk);
-        ctrl_ap.write(ctrl_tr);
-        `uvm_info(get_type_name(), "ready to drop obj", UVM_HIGH)
-        `uvm_info(get_type_name(), $sformatf("rvv state=%s", rvv_state), UVM_HIGH)
-        repeat(10) @(posedge rvs_if.clk);
-        break;
+  if(is_active) begin
+    rvv_state_pkg::rvv_state_e rvv_state;
+    phase.raise_objection( .obj( this ) );
+    super.main_phase(phase);
+    forever begin
+      @(posedge rvs_if.clk);
+      if(ctrl_tr.is_last_inst) begin
+        get_rvv_state(rvv_state);
+        if(inst_tx_queue.size()==0 && inst_rx_queue.size()==0 && inst_temp_queue.size()==0 && rvv_state==rvv_state_pkg::IDLE) begin 
+          repeat(10) @(posedge rvs_if.clk);
+          ctrl_ap.write(ctrl_tr);
+          `uvm_info(get_type_name(), "ready to drop obj", UVM_HIGH)
+          `uvm_info(get_type_name(), $sformatf("rvv state=%s", rvv_state), UVM_HIGH)
+          repeat(10) @(posedge rvs_if.clk);
+          break;
+        end
       end
     end
+    phase.drop_objection( .obj( this ) );
   end
-  phase.drop_objection( .obj( this ) );
 endtask: main_phase
 
 task rvs_monitor::tx_monitor();
@@ -150,21 +159,50 @@
     end else begin
       for(int i=0; i<`ISSUE_LANE; i++) begin
         if(rvs_if.insts_valid_rvs2cq[i] && rvs_if.insts_ready_cq2rvs[i]) begin
+          logic [31:0] inst_32;
           inst_tr = new("inst_tr");
-          inst_tr = inst_tx_queue.pop_front();
-          `uvm_info(get_type_name(), $sformatf("Send transaction to mdl"),UVM_HIGH)
-          `uvm_info(get_type_name(), inst_tr.sprint(),UVM_HIGH)
+          temp_tr = new("temp_tr");
+
+          if(use_tr_from_drv && is_active) begin
+            inst_tr = inst_tx_queue.pop_front();
+          end else begin
+            // Got inst from interface
+            inst_tr.constraint_mode(0);
+            inst_tr.set_config_state(
+              rvs_if.insts_rvs2cq[i].arch_state.ma,
+              rvs_if.insts_rvs2cq[i].arch_state.ta,
+              rvs_if.insts_rvs2cq[i].arch_state.sew,
+              rvs_if.insts_rvs2cq[i].arch_state.lmul,
+              rvs_if.insts_rvs2cq[i].arch_state.vl,
+              rvs_if.insts_rvs2cq[i].arch_state.vstart,
+              rvs_if.insts_rvs2cq[i].arch_state.xrm
+            );
+            inst_32[31:7] = rvs_if.insts_rvs2cq[i].bits;
+            case(rvs_if.insts_rvs2cq[i].opcode)
+              2'b00: inst_32[6:0] = 7'b000_0111; // LOAD
+              2'b01: inst_32[6:0] = 7'b010_0111; // STORE
+              2'b10: inst_32[6:0] = 7'b101_0111; // ARI
+            endcase
+            inst_tr.bin2tr(inst_32, rvs_if.insts_rvs2cq[i].rs1);
+            inst_tr.pc = rvs_if.insts_rvs2cq[i].inst_pc;
+
+            if(is_active) begin
+              inst_tr.is_last_inst = inst_tx_queue[0].is_last_inst;
+              inst_tx_queue.pop_front();
+            end
+          end
+
           `uvm_info("INST_TR", inst_tr.sprint(),UVM_LOW)
           `uvm_info("ASM_DUMP",$sformatf("0x%8x\t%s", inst_tr.pc, inst_tr.asm_string),UVM_LOW)
           if(inst_tr.reserve_inst_check()) begin
+            `uvm_info(get_type_name(), $sformatf("Send transaction to mdl:\n%s", inst_tr.sprint()), UVM_HIGH)
             inst_ap.write(inst_tr); // write to mdl/lsu
           end else begin 
-            `uvm_info(get_type_name(), $sformatf("MON discarded inst:\n%s",inst_tr.sprint()), UVM_HIGH)
+            `uvm_info(get_type_name(), $sformatf("MON discarded inst:\n%s", inst_tr.sprint()), UVM_HIGH)
           end
-          temp_tr = new("temp_tr");
           temp_tr.copy(inst_tr);
           inst_temp_queue.push_back(temp_tr);
-          ctrl_tr = inst_tr;
+          ctrl_tr = temp_tr;
           this.total_inst++;
         end
       end
@@ -332,7 +370,9 @@
 function void rvs_monitor::write_rvs_mon_inst(rvs_transaction inst_tr);
   `uvm_info(get_type_name(), "get a inst", UVM_HIGH)
   `uvm_info(get_type_name(), inst_tr.sprint(), UVM_HIGH)
-  inst_tx_queue.push_back(inst_tr);
+  if(is_active) begin
+    inst_tx_queue.push_back(inst_tr);
+  end
 endfunction
 
 task rvs_monitor::get_rvv_state(output rvv_state_pkg::rvv_state_e rvv_state);
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_transaction.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_transaction.sv
index 84db5de..7286bb1 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_transaction.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvs_agent_rvs_transaction.sv
@@ -72,7 +72,7 @@
   rand logic [4:0] src1_idx;
   rand logic [4:0] src2_idx;
   rand logic [4:0] src3_idx;
-       vxunary0_e src1_func_vext;
+       vxunary0_e  src1_func_vext;
        vwxunary0_e src2_func_vwxunary0;
        vwxunary0_e src1_func_vwxunary0;
        vmunary0_e  src1_func_vmunary0;
@@ -91,7 +91,7 @@
 
        int    eew_max;
        real   emul_max;
-      int     elm_idx_max;
+       int    elm_idx_max;
 
        int    dest_eew;
        int    src3_eew;
@@ -1172,8 +1172,9 @@
   extern function void pre_randomize();
   extern function void post_randomize();
   extern function void tr2bin();
-  extern function void bin2tr();
-  extern function void decode_vtype(bit dec_evl = 0);
+  extern function bit bin2tr(logic [31:0] inst_in, logic [`XLEN-1:0] rs_data);
+  extern function void set_config_state(logic [`XLEN-1:0] vma, logic [`XLEN-1:0] vta, logic [`XLEN-1:0] vsew, logic [`XLEN-1:0] vlmul, logic [`XLEN-1:0] vl, logic [`XLEN-1:0] vstart, logic [`XLEN-1:0] vxrm);
+  extern function void decode_vtype(bit dec_evl = 0, bit dec_vlmax = 0);
   extern function void get_vec_group_range();
   extern protected function void overlap_unalign_correct();
   extern function bit reserve_inst_check();
@@ -1250,14 +1251,13 @@
     vstart = 0;
   end
 
-  decode_vtype(0);
+  decode_vtype(0, 0);
   get_vec_group_range();
 
   // check overlap
   if(!overlap_unalign_en) begin overlap_unalign_correct(); end
   get_vec_group_range();
 
-
   // gen bin_inst
   tr2bin();
 
@@ -1291,13 +1291,227 @@
   bin_inst[6:0]   = inst_type;
 endfunction: tr2bin
 
-function void rvs_transaction::bin2tr();
-  //TODO
-  decode_vtype(1);
+function bit rvs_transaction::bin2tr(logic [31:0] inst_in, logic [`XLEN-1:0] rs_data);
+  bin_inst = inst_in;
+
+  // decode bin field
+  inst_type = bin_inst[6:0];
+  /* func6 */
+  case(inst_type)
+    LD, ST: begin
+      lsu_nf        = bin_inst[31:29];
+      lsu_mop       = bin_inst[27:26];
+    end
+    ALU: begin
+      alu_inst[5:0] = bin_inst[31:26];
+    end 
+  endcase
+  /* vm */
+  vm            = bin_inst[25];
+  src2_idx      = bin_inst[24:20];
+  src1_idx      = bin_inst[19:15];
+  case(inst_type)
+    LD, ST: begin
+      lsu_width = bin_inst[14:12];
+      if(lsu_width == LSU_8BIT)  lsu_eew = EEW8;
+      if(lsu_width == LSU_16BIT) lsu_eew = EEW16;
+      if(lsu_width == LSU_32BIT) lsu_eew = EEW32;
+      if(lsu_width == LSU_64BIT) lsu_eew = EEW64;
+    end 
+    ALU: alu_type = bin_inst[14:12];
+  endcase
+  case(inst_type)
+    ST:      src3_idx = bin_inst[11:7]; 
+    ALU, LD: dest_idx = bin_inst[11:7];
+  endcase
+
+  if(inst_type == ALU) begin
+    src3_type = UNUSE;
+    // OPI
+    if(alu_type inside {OPIVV, OPIVX, OPIVI}) begin
+      alu_inst[7:6] = 2'b00;
+      if(alu_type == OPIVV) begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = VRF;
+        if(alu_inst inside {VMERGE_VMVV} && vm == 1) begin
+          src2_type = UNUSE;
+        end
+        if(alu_inst inside {VWREDSUMU, VWREDSUM}) begin
+          dest_type = SCALAR;
+          src1_type = SCALAR;
+        end
+      end
+      if(alu_type == OPIVX) begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = XRF;
+        if(alu_inst inside {VMERGE_VMVV} && vm == 1) begin
+          src2_type = UNUSE;
+        end
+      end
+      if(alu_type == OPIVI) begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = IMM;
+        if(alu_inst inside {VMERGE_VMVV} && vm == 1) begin
+          src2_type = UNUSE;
+        end
+        if(alu_inst inside {
+          VSLL, VSRL, VSRA, VNSRL, VNSRA,
+          VSSRL, VSSRA, VNCLIPU, VNCLIP
+        }) begin
+          src1_type = UIMM;
+        end
+        if(alu_inst inside {VRGATHER}) begin
+          src1_type = UIMM;
+        end
+        if(alu_inst inside {VSMUL_VMVNRR}) begin
+          src1_type = FUNC;
+        end
+      end
+    end
+
+    // OPM
+    if(alu_type inside {OPMVV, OPMVX}) begin
+      alu_inst[7:6] = 2'b01;      
+      if(alu_type == OPMVV) begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = VRF;
+        if(alu_inst == VXUNARY0) begin
+          src1_type = FUNC;
+        end
+        if(alu_inst == VMUNARY0) begin
+          src1_type = FUNC;
+          if(src1_idx == VID) begin
+            src2_type = UNUSE;
+          end
+        end
+        if(alu_inst == VWXUNARY0) begin
+          dest_type = XRF;
+          src1_type = FUNC;
+          if(src1_idx == VMV_X_S) begin
+            src2_type = SCALAR;
+          end
+        end
+        if(alu_inst inside {
+          VREDSUM, VREDAND, VREDOR, VREDXOR,
+          VREDMINU,VREDMIN,VREDMAXU,VREDMAX
+        }) begin
+          dest_type = SCALAR;
+          src2_type = VRF;
+          src1_type = SCALAR;
+        end
+      end
+      if(alu_type == OPMVX) begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = XRF;
+        if(alu_inst == VWXUNARY0) begin
+          dest_type = SCALAR;
+          src2_type = FUNC;
+          src1_type = XRF;
+        end
+      end
+    end
+  end // ALU
+
+  if(inst_type == LD) begin
+    src3_type = UNUSE;
+    case(lsu_mop)
+      LSU_US: begin
+        dest_type = VRF;
+        src2_type = FUNC;
+        src1_type = XRF;
+      end
+      LSU_CS: begin
+        dest_type = VRF;
+        src2_type = XRF;
+        src1_type = XRF;
+      end
+      LSU_UI, 
+      LSU_OI: begin
+        dest_type = VRF;
+        src2_type = VRF;
+        src1_type = XRF;
+      end
+    endcase
+  end // LD
+
+  if(inst_type == ST) begin
+    dest_type = UNUSE;
+    case(lsu_mop)
+      LSU_US: begin
+        src3_type = VRF;
+        src2_type = FUNC;
+        src1_type = XRF;
+      end
+      LSU_CS: begin
+        src3_type = VRF;
+        src2_type = XRF;
+        src1_type = XRF;
+      end
+      LSU_UI, 
+      LSU_OI: begin
+        src3_type = VRF;
+        src2_type = VRF;
+        src1_type = XRF;
+      end
+    endcase
+  end // ST
+
+  // misc
+  if(src1_type == FUNC && inst_type == ALU && alu_inst == VXUNARY0) begin
+    if(!$cast(src1_func_vext,src1_idx))
+      src1_func_vext = VXUNARY0_NONE;
+  end
+  if(src1_type == FUNC && inst_type == ALU && alu_inst == VWXUNARY0) begin
+    if(!$cast(src1_func_vwxunary0,src1_idx))
+      src1_func_vwxunary0 = VWXUNARY0_NONE;
+  end
+  if(src2_type == FUNC && inst_type == ALU && alu_inst == VWXUNARY0) begin
+    if(!$cast(src2_func_vwxunary0,src2_idx))
+      src2_func_vwxunary0 = VWXUNARY0_NONE;
+  end
+  if(src1_type == FUNC && inst_type == ALU && alu_inst == VMUNARY0) begin
+    if(!$cast(src1_func_vmunary0,src1_idx))
+      src1_func_vmunary0 = VMUNARY0_NONE;
+  end
+  if(src2_type == FUNC && inst_type inside {LD,ST} && lsu_mop == LSU_US) begin
+    if(!$cast(lsu_umop,src2_idx))
+      lsu_umop = LSU_UMOP_NONE;
+  end
+    
+  if(src2_type == XRF) rs2_data = rs_data; else rs2_data = 'x;
+  if(src1_type == XRF) rs1_data = rs_data; else rs1_data = 'x;
+
+  decode_vtype(1, 1);
   get_vec_group_range();
+  asm_string_gen();
+
+  return 0;
 endfunction: bin2tr
 
-function void rvs_transaction::decode_vtype(bit dec_evl);      
+function void rvs_transaction::set_config_state(
+  logic [`XLEN-1:0] vma,
+  logic [`XLEN-1:0] vta,
+  logic [`XLEN-1:0] vsew, 
+  logic [`XLEN-1:0] vlmul,
+  logic [`XLEN-1:0] vl,
+  logic [`XLEN-1:0] vstart,
+  logic [`XLEN-1:0] vxrm
+);      
+  this.vma    = vma;
+  this.vta    = vta;
+  this.vsew   = vsew; 
+  this.vlmul  = vlmul;
+  this.vl     = vl;
+  this.vstart = vstart;
+  this.vxrm   = vxrm;
+endfunction: set_config_state
+
+function void rvs_transaction::decode_vtype(bit dec_evl, bit dec_vlmax);      
   // Calculate eew/emul
   if(inst_type == ALU && (alu_inst inside {VADC, VSBC, VMADC, VMSBC, VMERGE_VMVV}))
     use_vm_to_cal = 1;
@@ -1431,7 +1645,7 @@
               eew_max   = src3_eew;
               emul_max  = src3_emul;
               seg_num   = 1;
-              evl       = dec_evl ? dest_emul * `VLEN / dest_eew : evl;
+              evl       = dec_evl ? src3_emul * `VLEN / src3_eew : evl;
             end
             default: begin
               src3_eew  = lsu_eew;
@@ -1588,6 +1802,26 @@
     elm_idx_max = int'($ceil(emul_max)) * `VLEN / eew_max;
   end
 
+  // decode vlmax
+  if(dec_vlmax) begin
+    vlmax_max = 8 * `VLEN / 8;
+    if(inst_type == ALU && alu_inst inside {VMAND, VMOR, VMXOR, VMORN, VMNAND, VMNOR, VMANDN, VMXNOR}) begin
+      vlmax = vlmax_max;  
+    end else if(inst_type == ALU && alu_inst inside {VMUNARY0} && src1_idx inside {VMSBF, VMSOF, VMSIF}) begin
+      vlmax = vlmax_max;  
+    end else if(inst_type == ALU && alu_inst inside {VMSEQ, VMSNE, VMSLTU, VMSLT, VMSLEU, VMSLE, VMSGTU, VMSGT, VMADC, VMSBC}) begin
+      if(vlmul[2]) // fraction_lmul
+        vlmax = (`VLENB >> vsew);
+      else  
+        vlmax = ((`VLENB << vlmul) >> vsew);
+    end else begin
+      if(vlmul[2]) // fraction_lmul
+        vlmax = ((`VLENB >> (~vlmul +3'b1)) >> vsew);
+      else  
+        vlmax = ((`VLENB << vlmul) >> vsew);
+    end
+  end
+
 endfunction: decode_vtype
 
 function void rvs_transaction::get_vec_group_range();    
@@ -2453,6 +2687,7 @@
     end
   end
 
+  `uvm_info("TR/ISNT_CHECK", $sformatf("Check pass:\n%s", this.sprint()), UVM_HIGH)
   return PASS;
 endfunction: reserve_inst_check
 
diff --git a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_scoreboard.sv b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_scoreboard.sv
index b68b4e9..fc83666 100644
--- a/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_scoreboard.sv
+++ b/hdl/verilog/rvv/sve/rvv_backend_tb/src/rvv_scoreboard.sv
@@ -89,26 +89,12 @@
 endfunction:connect_phase
 
 task rvv_scoreboard::main_phase(uvm_phase phase);
-  phase.raise_objection( .obj( this ) );
   super.main_phase(phase);
   fork
     rt_checker();
     vrf_checker();
     mem_access_checker();
-    begin
-      forever begin
-        @(posedge rvs_if.clk);
-        if(ctrl_tr.is_last_inst) begin
-          if(rt_queue_rvs.size()==0 && rt_queue_mdl.size()==0) begin 
-            repeat(10) @(posedge rvs_if.clk);
-            `uvm_info(get_type_name(), "ready to drop obj", UVM_HIGH)
-            break;
-          end
-        end
-      end
-    end
-  join_any
-  phase.drop_objection( .obj( this ) );
+  join
 endtask: main_phase 
 
 function void rvv_scoreboard::report_phase(uvm_phase phase);
@@ -174,11 +160,11 @@
   reg_idx_t  rvs_rt_xrf_index, mdl_rt_xrf_index;
   xrf_t      rvs_rt_xrf_data , mdl_rt_xrf_data ;
   forever begin
-    @(posedge rvs_if.clk);
+    @(negedge rvs_if.clk);
     if(rt_queue_mdl.size() != rt_queue_rvs.size()) begin
-      `uvm_fatal("RT_CHECKER","Retire number mismatch between DUT & MDL.");
+      `uvm_fatal("RT_CHECKER","Retire inst number mismatch between DUT & MDL.");
     end
-    while(rt_queue_rvs.size()>0) begin 
+    while(rt_queue_rvs.size()>0 && rt_queue_mdl.size()>0) begin 
       rvs_tr = rt_queue_rvs.pop_front();
       mdl_tr = rt_queue_mdl.pop_front();
 
@@ -187,11 +173,11 @@
       `uvm_info("RT_RECORDER", $sformatf("Got retire transaction from MDL:\n%s",mdl_tr.sprint()),UVM_LOW)
 
       // PC check
-      if(rvs_tr.pc !== mdl_tr.pc) begin
-        `uvm_error("RT_CHECKER", $sformatf("Retire PC mismatch:\nDUT retired pc 0x%8x, \nMDL retired pc 0x%8x.", 
-                                            rvs_tr.pc,
-                                            mdl_tr.pc))
-      end
+      // if(rvs_tr.pc !== mdl_tr.pc) begin
+      //   `uvm_error("RT_CHECKER", $sformatf("Retire PC mismatch:\nDUT retired pc 0x%8x, \nMDL retired pc 0x%8x.", 
+      //                                       rvs_tr.pc,
+      //                                       mdl_tr.pc))
+      // end
 
       // VRF check
       if(rvs_tr.rt_vrf_index.size() != mdl_tr.rt_vrf_index.size()) begin
@@ -324,7 +310,7 @@
   string vreg_dut_val;
   string vreg_mdl_val;
   forever begin
-    @(posedge rvs_if.clk); 
+    @(negedge rvs_if.clk); 
     err = 0;
     if(vrf_queue_rvs.size()>1 || vrf_queue_mdl.size()>1) begin
       `uvm_error("TB_ISSUE", "Got more than 1 vrf check request, please check the TB.");
@@ -364,7 +350,7 @@
   mem_transaction mdl_tr;
   int err;
   forever begin
-    @(posedge rvs_if.clk); 
+    @(negedge rvs_if.clk); 
     if(~rvs_if.rst_n) begin
       mem_queue_lsu.delete();
       mem_queue_mdl.delete();