| # Full System Instruction Set Simulation |
| |
| And instruction set simulation (ISS) is a high-level simulation |
| intended to capture the behavior of the full system. |
| It is useful for testing software and ideas before |
| running a complete cycle-accurate simulator which |
| can have low host performance and before actual hardware is |
| available for testing. Since it can exist before hardware |
| is implemented in an RTL it also allows hardware/software |
| co-development, taking what can be a serial process into |
| a parallel workflow. |
| |
| # Shodan ISS Environment |
| |
| Shodan ISS is developed in Renode. Renode provides the ability to |
| simulate a full system including custom peripherals and a heterogenous |
| core configuration as is present in the Shodan SoC design. |
| |
| # Simulating the Secure Core |
| |
| Before beginning a simulation make sure to setup your workstation environment |
| as described in the Getting Started document. |
| |
| The scripts set up an alias to launch renode: |
| |
| ``` |
| renode |
| ``` |
| |
| This will launch the renode console. |
| To launch a simulation of the shodan secure core run the following |
| command in the Renode console: |
| |
| ``` |
| i @sim/config/shodan_secure.resc |
| ``` |
| |
| Execute the simualtion with that following command: |
| |
| ``` |
| start |
| ``` |
| |
| |
| It is possible to debug the running program with the following command at the console: |
| |
| ``` |
| riscv64-unknown-elf-gdb --command=sim/config/gdbinit out/opentitan/build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf |
| ``` |
| |
