Update doc for generating and inspecting IREE executables

Update GenerateAndInspectIreeExecutables.md to match the latest IREE
flags and API.

Change-Id: Id08024bf36b855b67b6c6b113e653d2992fcf88e

GenerateAndInspectIreeExecutables.md

diff --git a/GenerateAndInspectIreeExecutables.md b/GenerateAndInspectIreeExecutables.md
index cc4c10f..f521ef8 100644
--- a/GenerateAndInspectIreeExecutables.md
+++ b/GenerateAndInspectIreeExecutables.md
@@ -15,12 +15,12 @@
 
 ```bash
 ${CACHE}/iree_compiler/install/bin/iree-compile \
-    --iree-hal-target-backends=llvm-cpu
-    --iree-llvm-target-triple=riscv32-pc-linux-elf \
-    --iree-llvm-target-cpu=generic-rv32 \
-    --iree-llvm-target-cpu-features="+m,+f" \
-    --iree-llvm-target-abi=ilp32 \
-    --iree-llvm-embedded-linker-path=${CACHE}/iree_compiler/install/bin/lld \
+    --iree-hal-target-backends=llvm-cpu \
+    --iree-llvmcpu-target-triple=riscv32-pc-linux-elf \
+    --iree-llvmcpu-target-cpu=generic-rv32 \
+    --iree-llvmcpu-target-cpu-features="+m,+f" \
+    --iree-llvmcpu-target-abi=ilp32 \
+    --iree-llvmcpu-embedded-linker-path=${CACHE}/iree_compiler/install/bin/iree-lld \
     ${ROOTDIR}/toolchain/iree/samples/simple_embedding/simple_embedding_test.mlir \
     -o /tmp/simple_mul-llvm_aot.vmfb
 
@@ -32,23 +32,23 @@
 the workload. In Shodan, the supported targets are:
   * llvm-cpu: the library for LLVM ahead-of-time (AOT) compilation.
   * vmvx
-* iree-llvm-target-triple: The flag is populated to LLVM target triple.
-* iree-llvm-target-cpu: The flag populated to LLVM target cpu. It can be
+* iree-llvmcpu-target-triple: The flag is populated to LLVM target triple.
+* iree-llvmcpu-target-cpu: The flag populated to LLVM target cpu. It can be
 pre-defined cpu targets or the generic ones
-([link](https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/RISCVTargetParser.def)).
-* iree-llvm-target-cpu-features: The flag is populated to LLVM target features for
+([link](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVProcessors.td)).
+* iree-llvmcpu-target-cpu-features: The flag is populated to LLVM target features for
 extra CPU extensions. For RISC-V, it can include the typical ISA extensions,
 such as multiplication/division, atomic, floating point, and compression ISA
 support.
-__For the vector extension, it can be enabled with "+experimental-v"__.
-* iree-llvm-target-abi: The flag is polulated to LLVM target abi.
-* iree-llvm-embedded-linker-path: Linker for the device executable. It is
-  recommanded to use the lld from the IREE compiler release.
+__For the vector extension, it can be enabled with "+v"__.
+* iree-llvmcpu-target-abi: The flag is polulated to LLVM target abi.
+* iree-llvmcpu-embedded-linker-path: Linker for the device executable. It is
+  recommanded to use iree-lld from the IREE compiler release.
 
 Some extra options:
 
-* iree-llvm-keep-linker-artifacts: Aside from the generated bytecode flatbuffer
-(with [schema](https://github.com/google/iree/blob/main/iree/schemas/bytecode_module_def.fbs)),
+* iree-llvmcpu-keep-linker-artifacts: Aside from the generated bytecode flatbuffer
+(with [schema](https://github.com/openxla/iree/blob/main/runtime/src/iree/schemas/bytecode_module_def.fbs)),
 the intermediate linker is generated at `/tmp/<module_name>_linked_<hal_target>-xxxxxx.so`.
 (the exact path is printed in the stdout).
 * iree-vm-emit-polyglot-zip: Instead of the previous flag, by enabling this flag
@@ -59,10 +59,10 @@
 ```
 
 * riscv-v-fixed-length-vector-lmul-max: If the
-vector extension is enabled in `iree-llvm-target-cpu-features`, the RVV VLS
+vector extension is enabled in `iree-llvmcpu-target-cpu-features`, the RVV VLS
 (vector length specific) code will be generated with the vector length specified
-by these two options.
-* iree-llvm-debug-symbols: Add the debug information in the executable. Setting
+by this option.
+* iree-llvmcpu-debug-symbols: Add the debug information in the executable. Setting
 this to `false` at the production executable can reduce the workload size.
 
 ## Inspect IREE executables
@@ -72,7 +72,7 @@
 weights in the ML model.
 
 ```bash
-${CACHE}/iree-compiler/install/bin/iree-dump-module <vmfb file>
+${CACHE}/iree_compiler/install/bin/iree-dump-module <vmfb file>
 ```
 
 With the linker artifact enabled, The `.so` file contends the dispatch functions
@@ -94,13 +94,13 @@
 Use `iree-opt` to check the IR output
 
 ```bash
-${CACHE}/iree-compiler/install/bin/iree-opt \
-  -print-ir-after-all \
-  -iree-transformation-pipeline \
-  -iree-hal-target-backends=llvm-cpu \
-  -iree-llvm-target-triple=riscv32-pc-linux-elf \
-  -iree-llvm-target-cpu=generic-rv32 \
-  -iree-llvm-target-cpu-features="+m,+f" \
-  -iree-llvm-target-abi=ilp32 \
+${CACHE}/iree_compiler/install/bin/iree-opt \
+  --mlir-print-ir-after-all \
+  --iree-transformation-pipeline \
+  --iree-hal-target-backends=llvm-cpu \
+  --iree-llvmcpu-target-triple=riscv32-pc-linux-elf \
+  --iree-llvmcpu-target-cpu=generic-rv32 \
+  --iree-llvmcpu-target-cpu-features="+m,+f" \
+  --iree-llvmcpu-target-abi=ilp32 \
   <MLIR input>
 ```