# Copyright 2024 Google LLC
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

SENCHA_SRC_DIR                := $(ROOTDIR)/hw/matcha
SENCHA_OUT_DIR                := $(OUT)/sencha/hw
SENCHA_VERILATOR_TB           := $(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb
SENCHA_TESTLOG_DIR            := $(SENCHA_OUT_DIR)/test-log
SENCHA_FPGA_BINARY_DIR        := $(SENCHA_OUT_DIR)/fpga_tests
SENCHA_FPGA_SENCHA_BINARY_DIR := $(SENCHA_FPGA_BINARY_DIR)/sencha
SENCHA_FPGA_KELVIN_BINARY_DIR := $(SENCHA_FPGA_BINARY_DIR)/kelvin
BOOT_ROM_ELF                  := boot_rom.elf

$(SENCHA_OUT_DIR):
	mkdir -p $(SENCHA_OUT_DIR)

## Regenerate Sencha HW files frop IPs and top_sencha definition.
# This target uses Open Titan's autogen tools as well as the HW IPs to generate
# the system verilog files as well as the DV register definition cores and
# system verilog files. The source code is from both hw/opentitan-upstream and
# hw/matcha/, while the output is stored at out/sencha/hw.
#
# This is a dev-only target (not for CI), as it modifies the hw/sencha source
# tree with generated code.
sencha_hw_generate_all: | $(SENCHA_OUT_DIR)
	$(MAKE) -C "$(SENCHA_SRC_DIR)/hw" TOPS=top_sencha all

## Build Sencha verilator testbench.
# This target builds the verilator testbench binary from hw/matcha/hw/top_sencha
# using hw/matcha/hw/ip and hw/opentitan-upstream as the libraries. The output is
# stored in out/sencha/hw/.
# This target is compute-intensive. Make sure you have a powerful enough machine
# to build it.
sencha_hw_verilator_sim: $(SENCHA_VERILATOR_TB)

$(SENCHA_VERILATOR_TB): $(SENCHA_OUT_DIR) verilator
	cd $(SENCHA_SRC_DIR) && \
		bazel build //hw:sencha_verilator
	cd $(SENCHA_SRC_DIR) && \
		cp -rf --no-preserve=mode bazel-bin/hw/build.sencha_verilator_real/* "$(SENCHA_OUT_DIR)" && \
		chmod +x "$(SENCHA_OUT_DIR)/sim-verilator/Vsencha_sim_tb"

## Build Sencha FPGA Target for Nexus Board.
# This target builds the FPGA bit file from hw/matcha/hw/top_sencha
# using hw/matcha/hw/ip and hw/opentitan-upstream as the libraries.
# The output is stored in out/sencha/hw/.
# This target is compute-intensive. Make sure you have a powerful enough machine
# and Vivado suporting the latest UltraScale+ device to build it.
sencha_hw_fpga_nexus: | $(SENCHA_OUT_DIR)
	cd $(SENCHA_SRC_DIR) && \
		bazel build //hw/bitstream/vivado:sencha_fpga_nexus
	cd $(SENCHA_SRC_DIR) && \
		find bazel-bin/hw/bitstream/vivado/build.sencha_fpga_nexus/ -regex '.*.\(bit\|mmi\)' \
			-exec cp -f '{}' "$(SENCHA_OUT_DIR)" \;

$(SENCHA_TESTLOG_DIR):
	mkdir -p $(SENCHA_TESTLOG_DIR)

## Build Sencha sw artifacts
#
# Checks the sencha sw code integrity for targets not covered by the verilator
# tests.
#
# TODO(hoangm): Change below target to test Sencha-specific target once CHERIoT binaries can be
# built. Currently the target builds matcha targets as well.
sencha_sw_all: | $(SENCHA_OUT_DIR)
	cd $(SENCHA_SRC_DIR) && \
	  bazel build --define DISABLE_VERILATOR_BUILD=true --build_tag_filters="-kelvin_fpga,-cheri" \
			//sw/device/...
	cd $(SENCHA_SRC_DIR) && \
	  find "bazel-out/" \( -type f -name "*.elf" -o -name "*.bin" -o -name "*.vmem" \) \
		-exec cp -f --parents "{}" "$(SENCHA_OUT_DIR)" \;

$(SENCHA_FPGA_SENCHA_BINARY_DIR):
	mkdir -p $(SENCHA_FPGA_SENCHA_BINARY_DIR)

## Build test binaries that run on FPGA
sencha_fpga_tests: | $(SENCHA_FPGA_SENCHA_BINARY_DIR)
	cd $(SENCHA_SRC_DIR) && \
		bazel query //sw/device/tests/... \
			| grep 'fpga_nexus' \
			| egrep '_bin$$' \
			| grep -v '/smc:' \
			| grep -v 'kelvin' \
			| grep -v 'example_test_from_rom_rom_prog_fpga_nexus_bin' \
			| xargs bazel build
	cd $(SENCHA_SRC_DIR) && \
		find 'bazel-out/' \
			-type f \
			\( -wholename "*ST-*/*fpga_nexus.elf" -o -wholename "*ST-*/*fpga_nexus.bin" \) \
			-exec cp -f '{}' "$(SENCHA_FPGA_SENCHA_BINARY_DIR)" \;

$(SENCHA_FPGA_KELVIN_BINARY_DIR):
	mkdir -p "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"


## Build Sencha Kelvin SW FPGA test artifacts
#
# Build kelvin artifacts and package it in a tarball and ready for use on the FPGA
# The output is at out/sencha/hw/fpga_tests/kelvin
#
sencha_kelvin_fpga_tarballs: kelvin_sw | $(SENCHA_FPGA_KELVIN_BINARY_DIR)
	cd $(SENCHA_SRC_DIR) && \
	  bazel build --define DISABLE_VERILATOR_BUILD=true \
			@kelvin-binary//...
# Copy the tarballs and sc binary to out/.
	cd $(SENCHA_SRC_DIR) && \
		find "bazel-out/" -type f -wholename "*fastbuild-*/sw/device/tests/kelvin/fpga_tests/kelvin_test_sc_extflash_fpga_nexus.bin" |\
			xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"
	cd $(SENCHA_SRC_DIR) && \
		find "bazel-bin/external/kelvin-binary" -name "*.tar" |\
			xargs -I {} cp -f {} "$(SENCHA_FPGA_KELVIN_BINARY_DIR)"


## Build opentitantool for sencha FPGA tests
opentitantool_pkg: | $(SENCHA_OUT_DIR)
	cd $(SENCHA_SRC_DIR) && \
	  bazel build //sw:opentitantool_pkg
	cd $(SENCHA_SRC_DIR) && \
		cp -f bazel-bin/sw/opentitantool_pkg.tar.gz $(SENCHA_OUT_DIR)

## Build and run sencha verilator test suite
#
# TODO(hoangm): Change below target to test Sencha-specific target once CHERIoT binaries can be
# built. Currently the target builds matcha targets.
sencha_hw_verilator_tests: verilator | $(SENCHA_TESTLOG_DIR)
	cd $(SENCHA_SRC_DIR) && \
		bazel test --test_output=errors --test_timeout=180,600,1800,3600 \
			--local_test_jobs=HOST_CPUS*0.25 \
			--//hw:make_options=-j,16 \
			//sw/device/tests:verilator_test_suite
	cd $(SENCHA_SRC_DIR) && cp -rf "bazel-testlogs/sw" "$(SENCHA_TESTLOG_DIR)"

## Build the boot ROM image
#
# This builds the HW boot rom executable for simulation.
# Source is in hw/matcha, while output is placed in
# out/sencha/hw/
multihart_boot_rom:  | $(SENCHA_OUT_DIR)
	cd $(SENCHA_SRC_DIR) && \
		bazel build --config=riscv32 //sw/device/lib/testing/test_rom:sencha_test_rom_no_otp_fpga_nexus.elf
	cd $(SENCHA_SRC_DIR) && \
		find "bazel-out/" -wholename "*test_rom/sencha_test_rom_no_otp_fpga_nexus.elf" \
		-exec cp -f '{}' "$(SENCHA_OUT_DIR)/$(BOOT_ROM_ELF)" \;

## Clean Sencha HW artifact
sencha_hw_clean:
	rm -rf $(SENCHA_OUT_DIR)
	cd $(SENCHA_SRC_DIR) && \
		bazel clean --expunge

## Build the spi_passthough binary
#
# This builds the spi_passthrough_fpga_nexus.bin binary that can be used to
# write flash tarballs to the nexus SPI boot flash. The binary will be copied
# to out/spi_passthrough_fpga_nexus.bin
spi_passthrough: | $(OUT)
	cd $(SENCHA_SRC_DIR) && \
	  bazel build --define DISABLE_VERILATOR_BUILD=true \
		sw/device/examples/spi_passthrough
	find "$(SENCHA_SRC_DIR)/bazel-out/" -type f -wholename "*fastbuild-*/sw/device/examples/spi_passthrough/spi_passthrough_fpga_nexus.bin" |\
			xargs -I '{}' cp -f '{}' "$(OUT)"

# TODO(hoangm): Align the public bitstream naming artifacts once the sencha bitstream has been added to CI.
## Fetch latest Nexus bitstream and matching opentitantool
latest_bitstream: | $(OUT)
	curl https://storage.googleapis.com/shodan-public-artifacts/nexus-bitstream_latest.tar.gz -o $(OUT)/nexus-bitstream.tar.gz
	tar -C $(OUT) -xf $(OUT)/nexus-bitstream.tar.gz
	tar -C $(OUT) -xf $(OUT)/results/sencha_fpga_nexus_smoketest.tar.gz
	curl https://storage.googleapis.com/shodan-public-artifacts/opentitantool_pkg_latest.tar.gz -o $(OUT)/opentitantool_pkg.tar.gz
	tar -C $(OUT) -xf $(OUT)/opentitantool_pkg.tar.gz

.PHONY:: sencha_hw_verilator_sim sencha_hw_clean sencha_hw_verilator_tests
.PHONY:: sencha_sw_all opentitantool_pkg
.PHONY:: sencha_hw_fpga_nexus sencha_kelvin_fpga_tarballs
.PHONY:: multihart_boot_rom
.PHONY:: spi_passthrough
.PHONY:: latest_bitstream