tree 6a78c8845bf02ebb36efc82bab99f7658c1ec9a2
parent 818997709960c0b0eac1fd52e032e612cc0a2227
author Matthew Wilson <mwilson@google.com> 1716402933 -0700
committer Matthew Wilson <mwilson@google.com> 1716403888 +0000

Fix kelvin_hw_verilog target

build now outputs .sv system verilog files instead of .v verilog

Change-Id: I9954ba0af7fa816768afe05a115612e01fa940bf
Bypass-Presubmit-Reason: No presubmit exists