| commit | bb54330fda290a905fa694eadeab0aa085378222 | [log] [tgz] |
|---|---|---|
| author | David Davis <ddavis-2015@users.noreply.github.com> | Tue Jan 02 14:22:36 2024 -0800 |
| committer | GitHub <noreply@github.com> | Tue Jan 02 22:22:36 2024 +0000 |
| tree | f40ba94c74db1538a7b42b0c9f2156f081d815ab | |
| parent | 17d0e7f6bb4edb70acaa69ddb6734cbb9ebfe49d [diff] |
Compute output shapes for some kernels (#2356) @tensorflow/micro Update the output tensor shape during prepare phase when the computed shape does not match the shape in the flatbuffer. Kernels: - BATCH_TO_SPACE_ND - SPACE_TO_BATCH_ND - CONV - RESHAPE - EXPAND_DIMS - DEPTHWISE_CONV Update CMSIS_NN and ARC_MLI optimized kernels. Add additional tests from TfLite for BATCH_TO_SPACE_ND and SPACE_TO_BATCH_ND. Update existing tests. Add tests for Keras model using convolution with dilation > 1. Update memory_arena_threshold_test to increase total, tail, and persistent allocation sizes: - Add 20 bytes for CONV output shape - Add 15 bytes for arena allocation alignment - x2 convolution layers Update micro_speech_test arena size as per description in C++ code. See #2319 for additional details. Resolves [b/317362237](https://issuetracker.google.com/317362237) bug=fixes #2368 #1646 #1629 #1231 #2338 #2319
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: