| commit | a3be93b49bde7856a135497a02643cb382d88a30 | [log] [tgz] |
|---|---|---|
| author | RJ Ascani <rjascani@google.com> | Fri Apr 26 12:29:45 2024 -0700 |
| committer | GitHub <noreply@github.com> | Fri Apr 26 19:29:45 2024 +0000 |
| tree | 6b15cc6350a64c6c1b93def4f8d281876de65a49 | |
| parent | fc498a80493b26226fc8a48b53dff669104bbd74 [diff] |
Enable hifi5 optimized kernels (#2555) Several of the xtensa optimized kernels were guarded with #ifdefs for HIFI3 and HIFI4, but were missing HIFI5. Those kernels have also been enabled via the hifi5 nnlib, so we can add the defines. BUG=none
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: