This doc outlines how to use Arm IP with TFLM. The following sub chapters contain more details of the respective IP.
Arm's Cortex-M processor support is fully integrated to TFLM. To build a TFLM library for any Cortex-M processor, check out the Cortex-M generic readme. Additionally, CMSIS-NN provides optimal performance executing machine learning workloads on Cortex-M. See the sub chapter CMSIS-NN.
Common Microcontroller Software Interface Standard for Neural Networks (CMSIS-NN) is a collection of efficient neural network kernels developed to maximize performance on Cortex-M processors. The CMSIS-NN optimized kernel are highly integrated to TFLM. For more information how to utilize these kernels, see CMSIS-NN readme.
The Ethos-U microNPU (Neural Processing Unit) family consist of Ethos-U55 and Ethos-U65. Ethos-U55 is designed to accelerate ML inference in area-constrained embedded and IoT devices, whereas Ethos-U65 extends its applicability to be used as an Cortex-M subsystem to a larger Arm Cortex-A, Cortex-R and Neoverse-based system.
To get started with TFLM and Ethos-U, see the Ethos-U readme.
Corstone-300 is a hardware reference design based on the Arm Cortex-M55 processor, which integrates the Ethos-U55 microNPU. The Corstone-300 FVP (Fixed Virtual Platform) is a model of the hardware which enables execution of full software stacks ahead of silicon.
To get started with TFLM and Corstone-300 FVP, see the Corstone-300 readme.