| commit | 7811156ef476bdea9cc5bf38b04703908552b4eb | [log] [tgz] |
|---|---|---|
| author | jwithers <jpwithers@gmail.com> | Wed Nov 15 13:12:36 2023 -0800 |
| committer | GitHub <noreply@github.com> | Wed Nov 15 21:12:36 2023 +0000 |
| tree | a9e41efeb4e7dce8bb4d8cd76d81601d87404978 | |
| parent | 0996efe9b60fde8efcde5242df1afc6ee24d9ee2 [diff] |
PyPI whl build and upload to PyPI test server nightly job (#2317) This script builds the python 3.10 and 3.11 wheels using python/tflite_micro/pypi_build.sh and then uploads to the test PyPI server with python/tflite_micro/pypi_upload.sh. It is scheduled to run at 1300 UTC each day (0600 or 0700 PST). The runs require approximately 11 minutes. This job can also be run manually by going to Actions > PyPI Build. There is an option to run only the whl build without upload for troubleshooting. It also should be relatively obvious how to add a release build option if the live server key was added to repo secrets and the script env block and another optional run block added with the -p <live server key> switch added to a copy of the upload script line. I have tested the build block, but can't test the upload section since I don't have access to the PYPI_API_KEY secret. BUG=request from rj
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: