Fix benchmarking utils on RISC-V (#2130) The generic benchmarking utilities added in PR 2125 did not compile on RISC-V due to two separate issues: * An incorrect format specifier for int32_t on RISC-V. This is resolved by using PRId32 instead of %ld or %d. * The fileno() is undeclared with the RISC-V toolchain, similar to how it is with the Embedded ARM toolchain. This PR resolves this by forgoing the fstat() check on file size (as this is what used fileno), and instead attempting to read the maximum number of bytes we can fit in the model buffer. We can then use feof() to verify that we read the entirety of the model, and error out if we did not. This solution also eliminates needing to worry about different file types, such as how the Xtensa simulator treats files from the host system as character devices. BUG=2129
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: