| commit | 73e419e793cbba5d4e759c98bb71a943f7474070 | [log] [tgz] |
|---|---|---|
| author | RJ Ascani <rjascani@google.com> | Thu Jan 18 17:50:10 2024 -0800 |
| committer | GitHub <noreply@github.com> | Fri Jan 19 01:50:10 2024 +0000 |
| tree | b9f2ddae3018faf154f85a74a1d70709cbff8bbd | |
| parent | 2d80ee4dce4b721cbc8369530121a803103a731a [diff] |
Enable optimized ADD/SUB for HiFi5 (#2399) The HiFi5 nnlib has the same optimized kernels for ADD and SUB as the HiFi4 nnlib, but the proper defines were not added to the kernel implementation. This was resulting in falling back to reference kernels for both of those operators on HiFi5. BUG=none
TensorFlow Lite for Microcontrollers is a port of TensorFlow Lite designed to run machine learning models on DSPs, microcontrollers and other devices with limited memory.
Additional Links:
| Build Type | Status |
|---|---|
| CI (Linux) |  |
| Code Sync |  |
This table captures platforms that TFLM has been ported to. Please see New Platform Support for additional documentation.
| Platform | Status |
|---|---|
| Arduino |   |
| Coral Dev Board Micro | TFLM + EdgeTPU Examples for Coral Dev Board Micro |
| Espressif Systems Dev Boards |  |
| Renesas Boards | TFLM Examples for Renesas Boards |
| Silicon Labs Dev Kits | TFLM Examples for Silicon Labs Dev Kits |
| Sparkfun Edge |  |
| Texas Instruments Dev Boards |  |
This is a list of targets that have optimized kernel implementations and/or run the TFLM unit tests using software emulation or instruction set simulators.
| Build Type | Status |
|---|---|
| Cortex-M |  |
| Hexagon |  |
| RISC-V |  |
| Xtensa |  |
| Generate Integration Test |  |
See our contribution documentation.
A Github issue should be the primary method of getting in touch with the TensorFlow Lite Micro (TFLM) team.
The following resources may also be useful:
SIG Micro email group and monthly meetings.
SIG Micro gitter chat room.
For questions that are not specific to TFLM, please consult the broader TensorFlow project, e.g.: